diff --git a/README.md b/README.md
index eb827f083..f60530c98 100644
--- a/README.md
+++ b/README.md
@@ -10,7 +10,7 @@ FSP uses an open software ecosystem and provides flexibility in using your prefe
 
 ### Current Release
 
-[FSP v4.2.0](https://github.com/renesas/fsp/releases/tag/v4.2.0)
+[FSP v4.3.0](https://github.com/renesas/fsp/releases/tag/v4.3.0)
 
 ### Supported RA MCU Kits
 
@@ -36,6 +36,11 @@ FSP uses an open software ecosystem and provides flexibility in using your prefe
 - MCK-RA6T2
 - RSSK-RA2L1
 - RSSK-RA6T1
+- FPB-RA4E2
+- FPB-RA6E2
+- EK-RA4E2
+- EK-RA6E2
+
 
 ### Supported Software Packaged with FSP
 
@@ -64,6 +69,7 @@ For a list of software modules packaged with FSP, see [Supported Software](SUPPO
 - FSP versions of 3.7.0 and later require a minimum e² studio version of 2022-04.
 - FSP versions of 4.0.0 and later require a minimum e² studio version of 2022-07.
 - FSP versions of 4.1.0 and later require a minimum e² studio version of 2022-10.
+- FSP versions of 4.3.0 and later require a minimum e² studio version of 2023-01.
 
 If you have already installed a previous FSP release that included e² studio then you can download the packs separately. These are available for download under the Assets section for each release. There is a zipped version, FSP_Packs_\<version\>.zip, that will work on any supported OS. There is also a self-extracting installer version, FSP_Packs_\<version\>.exe, that will work on Windows.
 
@@ -71,7 +77,7 @@ When using the zipped version of the packs the zip file should be extracted into
 
 #### For new users that are using FSP with e² studio
 
-1.	Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v4.2.0).
+1.	Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v4.3.0).
 2.	Run the installer. This will install the e² studio tool, FSP packs, GCC toolchain and other tools required to use this software. No additional installations are required.
 
 #### If using RA Smart Configurator (RASC) with IAR Embedded Workbench or Keil MDK ####
diff --git a/SUPPORTED_SOFTWARE.md b/SUPPORTED_SOFTWARE.md
index f687619f2..41552b4eb 100644
--- a/SUPPORTED_SOFTWARE.md
+++ b/SUPPORTED_SOFTWARE.md
@@ -23,6 +23,7 @@
     * [CTSU (r_ctsu)](https://renesas.github.io/fsp/group___c_t_s_u.html)
     * [Touch (rm_touch)](https://renesas.github.io/fsp/group___t_o_u_c_h.html)
   * Connectivity
+    * [Azure RTOS USBX DFU](https://docs.microsoft.com/en-us/azure/rtos/usbx/)
     * [Azure RTOS USBX HCDC](https://docs.microsoft.com/en-us/azure/rtos/usbx/)
     * [Azure RTOS USBX HHID](https://docs.microsoft.com/en-us/azure/rtos/usbx/)
     * [Azure RTOS USBX HPRN](https://docs.microsoft.com/en-us/azure/rtos/usbx/)
@@ -102,6 +103,8 @@
     * [Motor Sensorless Vector Control (rm_motor_sensorless)](https://renesas.github.io/fsp/group___m_o_t_o_r___s_e_n_s_o_r_l_e_s_s.html)
     * [Motor Speed Controller (rm_motor_speed)](https://renesas.github.io/fsp/group___m_o_t_o_r___s_p_e_e_d.html)
     * [Motor Vector Control with hall sensors(rm_motor_hall)](https://renesas.github.io/fsp/group___m_o_t_o_r___h_a_l_l.html)
+    * [Motor inertia estimation (rm_motor_inertia_estimate)](https://renesas.github.io/fsp/group___m_o_t_o_r___i_n_e_r_t_i_a___e_s_t_i_m_a_t_e.html)
+    * [Motor return origin function (rm_motor_return_origin)](https://renesas.github.io/fsp/group___m_o_t_o_r___r_e_t_u_r_n___o_r_i_g_i_n.html)
     * [Motor vector control with induction sensor (rm_motor_induction)](https://renesas.github.io/fsp/group___m_o_t_o_r___i_n_d_u_c_t_i_o_n.html)
   * Networking
     * Bluetooth Low Energy Mesh Network modules
@@ -159,6 +162,7 @@
     * [AWS Core MQTT](https://docs.aws.amazon.com/freertos/latest/userguide/coremqtt.html)
     * [AWS Transport Interface on MbedTLS/PKCS11 (rm_aws_transport_interface_port)](https://docs.aws.amazon.com/embedded-csdk/latest/lib-ref/libraries/standard/coreMQTT/docs/doxygen/output/html/mqtt_transport_interface.html)
     * [Azure EWF Adapter on RYZ014A](https://renesas.github.io/fsp/group___r_m___a_z_u_r_e___e_w_f___r_y_z.html)
+    * [Azure EWF Adapter on RYZ024A](https://renesas.github.io/fsp/group___r_m___a_z_u_r_e___e_w_f___r_y_z.html)
     * [Azure RTOS NetX Duo Auto IP](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-auto-ip/chapter1)
     * [Azure RTOS NetX Duo BSD Support](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-bsd/chapter1)
     * [Azure RTOS NetX Duo Common](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/)
@@ -191,6 +195,7 @@
     * [Ethernet (r_ether)](https://renesas.github.io/fsp/group___e_t_h_e_r.html)
     * [Ethernet (r_ether_phy)](https://renesas.github.io/fsp/group___e_t_h_e_r___p_h_y.html)
     * [FreeRTOS+TCP](https://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/TCP_IP_Configuration.html)
+    * [GTL BLE Abstraction (rm_ble_abs_gtl)](https://renesas.github.io/fsp/group___b_l_e___a_b_s.html)
     * [PTP (r_ptp)](https://renesas.github.io/fsp/group___p_t_p.html)
     * [SPP BLE Abstraction (rm_ble_abs_spp)](https://renesas.github.io/fsp/group___b_l_e___a_b_s.html)
   * Power
@@ -213,7 +218,7 @@
     * [TinyCrypt (H/W Accelerated)](https://github.com/01org/tinycrypt/blob/master/documentation/tinycrypt.rst)
     * [TinyCrypt (S/W Only)](https://github.com/01org/tinycrypt/blob/master/documentation/tinycrypt.rst)
     * [Trusted Firmware-M](https://tf-m-user-guide.trustedfirmware.org/)
-    * [Trusted Firmware-M BL2](https://tf-m-user-guide.trustedfirmware.org/docs/technical_references/design_docs/tfm_secure_boot.html)
+    * [Trusted Firmware-M BL2](https://tf-m-user-guide.trustedfirmware.org/design_docs/booting/tfm_secure_boot.html)
     * [Trusted Firmware-M Non-Secure](https://tf-m-user-guide.trustedfirmware.org/)
   * Sensor
     * [FS1015 Flow Sensor (rm_fs1015)](https://renesas.github.io/fsp/group___r_m___f_s1015.html)
@@ -251,6 +256,7 @@
     * [Three-Phase PWM (r_gpt_three_phase)](https://renesas.github.io/fsp/group___g_p_t___t_h_r_e_e___p_h_a_s_e.html)
     * [Timer, General PWM (r_gpt)](https://renesas.github.io/fsp/group___g_p_t.html)
     * [Timer, Low-Power (r_agt)](https://renesas.github.io/fsp/group___a_g_t.html)
+    * [Timer, Ultra-Low-Power (r_ulpt)](https://renesas.github.io/fsp/group___u_l_p_t.html)
   * Transfer
     * [Transfer (r_dmac)](https://renesas.github.io/fsp/group___d_m_a_c.html)
     * [Transfer (r_dtc)](https://renesas.github.io/fsp/group___d_t_c.html)
@@ -266,7 +272,6 @@
     * [MCUboot Custom Crypto (Protected Mode)](https://renesas.github.io/fsp/group___r_m___m_c_u_b_o_o_t___p_o_r_t.html)
     * [MCUboot Example Keys (NOT FOR PRODUCTION)](https://github.com/mcu-tools/mcuboot)
     * [MCUboot External Memory (QSPI)](https://renesas.github.io/fsp/)
-    * [MCUboot External Memory (Unsupported)](https://renesas.github.io/fsp/)
     * [MCUboot Port for RA (rm_mcuboot_port)](https://renesas.github.io/fsp/group___r_m___m_c_u_b_o_o_t___p_o_r_t.html)
     * [MCUboot config](https://github.com/mcu-tools/mcuboot)
     * [MCUboot logging](https://github.com/mcu-tools/mcuboot)
@@ -289,7 +294,6 @@
   * Graphics
     * [Azure RTOS GUIX Port (rm_guix_port)](https://renesas.github.io/fsp/group___r_m___g_u_i_x___p_o_r_t.html)
     * [SEGGER emWin RA Port (rm_emwin_port)](https://renesas.github.io/fsp/group___r_m___e_m_w_i_n___p_o_r_t.html)
-    * [Software JPEG Placeholder (r_jpeg) [DO NOT USE]](https://renesas.github.io/fsp/group___j_p_e_g.html)
   * Networking
     * [AWS Cellular Interface Common](https://www.freertos.org/Documentation/api-ref/cellular/index.html)
     * [AWS Cellular Platform (rm_cellular_platform_aws)](https://www.freertos.org/Documentation/api-ref/cellular/cellular_porting.html)
@@ -310,16 +314,19 @@
     * [AWS Secure Sockets Common (No Longer Supported)](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html)
     * [AWS Secure Sockets TLS Support (No Longer Supported)](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html)
     * [AWS Secure Sockets on FreeRTOS Plus TCP (No Longer Supported)](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html)
-    * [AWS Secure Sockets on WiFi (No Longer Supported)](https://renesas.github.io/fsp/)
+    * [AWS Secure Sockets on WiFi (No Longer Supported)](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html)
     * [AWS Silex WiFi Sockets Wrapper (rm_aws_sockets_wrapper_silex)](https://docs.aws.amazon.com/embedded-csdk/latest/lib-ref/libraries/standard/coreMQTT/docs/doxygen/output/html/mqtt_transport_interface.html)
     * [AWS TCP Sockets Wrapper](https://docs.aws.amazon.com/embedded-csdk/latest/lib-ref/libraries/standard/coreMQTT/docs/doxygen/output/html/mqtt_transport_interface.html)
     * [AWS Transport Interface on Secure Sockets (No Longer Supported)](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html)
     * [AWS WiFi Common](https://docs.aws.amazon.com/freertos/latest/userguide/freertos-wifi.html)
     * [AWS da16200 WiFi Sockets Wrapper (rm_aws_sockets_wrapper_da16200)](https://docs.aws.amazon.com/embedded-csdk/latest/lib-ref/libraries/standard/coreMQTT/docs/doxygen/output/html/mqtt_transport_interface.html)
-    * [Azure EWF Allocator on ThreadX](https://azure.github.io/embedded-wireless-framework/html/index.html)
+    * [Azure EWF Heap Allocator](https://azure.github.io/embedded-wireless-framework/html/index.html)
     * [Azure EWF Interface on r_uart](https://azure.github.io/embedded-wireless-framework/html/index.html)
+    * [Azure EWF Memory Pool Allocator](https://azure.github.io/embedded-wireless-framework/html/index.html)
     * [Azure EWF NetX Duo Middleware](https://azure.github.io/embedded-wireless-framework/html/index.html)
+    * [Azure EWF Platform on Bare Metal](https://azure.github.io/embedded-wireless-framework/html/index.html)
     * [Azure EWF Platform on ThreadX](https://azure.github.io/embedded-wireless-framework/html/index.html)
+    * [Azure EWF ThreadX Allocator](https://azure.github.io/embedded-wireless-framework/html/index.html)
     * [Azure Embedded Wireless Framework Common](https://azure.github.io/embedded-wireless-framework/html/index.html)
     * [Azure RTOS NetX Duo NAT](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/netx-duo-nat/chapter1)
     * [BLE Driver (r_ble_balance)](https://renesas.github.io/fsp/group___b_l_e___b_a_l_a_n_c_e.html)
@@ -331,11 +338,13 @@
     * [BLE Driver (r_ble_extended)](https://renesas.github.io/fsp/group___b_l_e___e_x_t_e_n_d_e_d.html)
     * [BLE Driver (r_ble_extended_freertos)](https://renesas.github.io/fsp/group___b_l_e___e_x_t_e_n_d_e_d.html)
     * [BLE Driver (r_ble_extended_threadx)](https://renesas.github.io/fsp/group___b_l_e___e_x_t_e_n_d_e_d.html)
+    * [BLE GTL Transport on UART (rm_ble_abs_gtl_transport)](https://renesas.github.io/fsp/group___b_l_e___a_b_s.html)
     * [BLE Mesh OS on Baremetal (rm_mesh_os_baremetal)](https://renesas.github.io/fsp/group___m_e_s_h___o_s___b_a_r_e_m_e_t_a_l.html)
     * [BLE Mesh OS on FreeRTOS (rm_mesh_os_freertos)](https://renesas.github.io/fsp/group___m_e_s_h___o_s___f_r_e_e_r_t_o_s.html)
     * [BLE Mesh Timer on Baremetal (rm_mesh_timer_baremetal)](https://renesas.github.io/fsp/group___m_e_s_h___t_i_m_e_r___b_a_r_e_m_e_t_a_l.html)
     * [BLE Mesh Timer on FreeRTOS (rm_mesh_timer_freertos)](https://renesas.github.io/fsp/group___m_e_s_h___t_i_m_e_r___f_r_e_e_r_t_o_s.html)
     * [Cellular Comm Interface on UART (rm_cellular_comm_uart_aws)](https://www.freertos.org/Documentation/api-ref/cellular/cellular__comm__interface_8h.html)
+    * [DA14531 GTL Driver Layer](https://renesas.github.io/fsp/group___b_l_e___a_b_s___g_t_l.html)
     * [FreeRTOS+TCP Wrapper to r_ether (rm_freertos_plus_tcp)](https://renesas.github.io/fsp/group___f_r_e_e_r_t_o_s___p_l_u_s___t_c_p.html)
     * [FreeRTOS+TLS (No Longer Supported)](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html)
     * [NetX Duo Ethernet Driver (rm_netxduo_ether)](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/chapter5)
@@ -346,20 +355,21 @@
   * Security
     * [Azure RTOS NetX Crypto HW Acceleration (rm_netx_secure_crypto)](https://renesas.github.io/fsp/group___r_m___n_e_t_x___s_e_c_u_r_e___c_r_y_p_t_o.html)
     * [Azure RTOS NetX Crypto Software Only](https://renesas.github.io/fsp/group___r_m___n_e_t_x___s_e_c_u_r_e___c_r_y_p_t_o.html)
+    * [Crypto AES2](https://renesas.github.io/fsp/)
     * [Crypto RA2](https://renesas.github.io/fsp/)
     * [FreeRTOS MbedTLS Port](https://renesas.github.io/fsp/)
     * [Key Injection for PSA Crypto](https://renesas.github.io/fsp/group___s_c_e___k_e_y___i_n_j_e_c_t_i_o_n.html)
-    * [MCUBoot TinyCrypt TRNG (rm_mcuboot_tinycrypt_port)](https://renesas.github.io/fsp/group___r_m___t_i_n_y_c_r_y_p_t___p_o_r_t.html)
+    * [MCUBoot TinyCrypt H/W Acceleration (rm_mcuboot_tinycrypt_port)](https://renesas.github.io/fsp/group___r_m___t_i_n_y_c_r_y_p_t___p_o_r_t.html)
     * [MCUboot TinyCrypt (H/W Accelerated)](https://github.com/01org/tinycrypt/blob/master/documentation/tinycrypt.rst)
     * [MCUboot TinyCrypt (S/W Only)](https://github.com/01org/tinycrypt/blob/master/documentation/tinycrypt.rst)
-    * [Mbed Crypto HW Acceleration (rm_psa_crypto)](https://renesas.github.io/fsp/group___r_m___p_s_a___c_r_y_p_t_o.html)
+    * [Mbed Crypto H/W Acceleration (rm_psa_crypto)](https://renesas.github.io/fsp/group___r_m___p_s_a___c_r_y_p_t_o.html)
     * [MbedTLS FSP Port (rm_mbedtls)](https://www.trustedfirmware.org/projects/mbed-tls/)
     * [RSIP Compatibility Mode](https://renesas.github.io/fsp/)
     * [SCE Compatibility Mode](https://renesas.github.io/fsp/)
     * [SCE5](https://renesas.github.io/fsp/)
     * [SCE5B](https://renesas.github.io/fsp/)
     * [SCE7](https://renesas.github.io/fsp/)
-    * [TinyCrypt TRNG (rm_tinycrypt_port)](https://renesas.github.io/fsp/group___r_m___t_i_n_y_c_r_y_p_t___p_o_r_t.html)
+    * [TinyCrypt H/W Acceleration (rm_tinycrypt_port)](https://renesas.github.io/fsp/group___r_m___t_i_n_y_c_r_y_p_t___p_o_r_t.html)
     * [Trusted Firmware-M BL2 Port (rm_bl2_port)](https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/design/firmware-design.rst#bl2)
     * [Trusted Firmware-M FreeRTOS Integration](https://tf-m-user-guide.trustedfirmware.org/)
     * [Trusted Firmware-M Port (rm_tfm_port)](https://tf-m-user-guide.trustedfirmware.org/)
@@ -384,7 +394,6 @@
     * [FreeRTOS+FAT Port for RA (rm_freertos_plus_fat)](https://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_FAT/index.html)
     * [LevelX NOR Port (rm_levelx_nor_spi)](https://renesas.github.io/fsp/group___r_m___l_e_v_e_l_x___n_o_r___s_p_i.html)
     * [LittleFS on Flash (rm_littlefs_flash)](https://renesas.github.io/fsp/group___r_m___l_i_t_t_l_e_f_s___f_l_a_s_h.html)
-    * [Persistent Storage Stub (not currently supported)](https://renesas.github.io/fsp/group___r_m___l_i_t_t_l_e_f_s___f_l_a_s_h.html)
   * System
     * [Arm CMSIS5 Core (M)](https://arm-software.github.io/CMSIS_5/Core/html/index.html)
   * Transfer
diff --git a/ra/board/ra2a1_ek/board.h b/ra/board/ra2a1_ek/board.h
index 306a83172..44a657b39 100644
--- a/ra/board/ra2a1_ek/board.h
+++ b/ra/board/ra2a1_ek/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2a1_ek/board_init.c b/ra/board/ra2a1_ek/board_init.c
index dd12b0949..c0f64dbed 100644
--- a/ra/board/ra2a1_ek/board_init.c
+++ b/ra/board/ra2a1_ek/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2a1_ek/board_init.h b/ra/board/ra2a1_ek/board_init.h
index c512bce4a..74bac4a39 100644
--- a/ra/board/ra2a1_ek/board_init.h
+++ b/ra/board/ra2a1_ek/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2a1_ek/board_leds.c b/ra/board/ra2a1_ek/board_leds.c
index f35a611d3..ce039163a 100644
--- a/ra/board/ra2a1_ek/board_leds.c
+++ b/ra/board/ra2a1_ek/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2a1_ek/board_leds.h b/ra/board/ra2a1_ek/board_leds.h
index b4cdc8a9b..cc71822e8 100644
--- a/ra/board/ra2a1_ek/board_leds.h
+++ b/ra/board/ra2a1_ek/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2e1_ek/board.h b/ra/board/ra2e1_ek/board.h
index 6a7beaa54..cb3df81cc 100644
--- a/ra/board/ra2e1_ek/board.h
+++ b/ra/board/ra2e1_ek/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2e1_ek/board_init.c b/ra/board/ra2e1_ek/board_init.c
index 0af000a32..9a148f186 100644
--- a/ra/board/ra2e1_ek/board_init.c
+++ b/ra/board/ra2e1_ek/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2e1_ek/board_init.h b/ra/board/ra2e1_ek/board_init.h
index f997f73f1..0d97fdcbb 100644
--- a/ra/board/ra2e1_ek/board_init.h
+++ b/ra/board/ra2e1_ek/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2e1_ek/board_leds.c b/ra/board/ra2e1_ek/board_leds.c
index 9f980a2d9..36fd1f668 100644
--- a/ra/board/ra2e1_ek/board_leds.c
+++ b/ra/board/ra2e1_ek/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2e1_ek/board_leds.h b/ra/board/ra2e1_ek/board_leds.h
index d6f265bd6..e1495d14e 100644
--- a/ra/board/ra2e1_ek/board_leds.h
+++ b/ra/board/ra2e1_ek/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2e1_fpb/board.h b/ra/board/ra2e1_fpb/board.h
index 25623ca47..42cdcca1c 100644
--- a/ra/board/ra2e1_fpb/board.h
+++ b/ra/board/ra2e1_fpb/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2e1_fpb/board_init.c b/ra/board/ra2e1_fpb/board_init.c
index cbb25791a..b3a6734df 100644
--- a/ra/board/ra2e1_fpb/board_init.c
+++ b/ra/board/ra2e1_fpb/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2e1_fpb/board_init.h b/ra/board/ra2e1_fpb/board_init.h
index 193cbb0c7..459036c2b 100644
--- a/ra/board/ra2e1_fpb/board_init.h
+++ b/ra/board/ra2e1_fpb/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2e1_fpb/board_leds.c b/ra/board/ra2e1_fpb/board_leds.c
index 434d4052a..be026a352 100644
--- a/ra/board/ra2e1_fpb/board_leds.c
+++ b/ra/board/ra2e1_fpb/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2e1_fpb/board_leds.h b/ra/board/ra2e1_fpb/board_leds.h
index 22e0ace4c..9f893741e 100644
--- a/ra/board/ra2e1_fpb/board_leds.h
+++ b/ra/board/ra2e1_fpb/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2e2_ek/board.h b/ra/board/ra2e2_ek/board.h
index 754806fd7..fb9b711b1 100644
--- a/ra/board/ra2e2_ek/board.h
+++ b/ra/board/ra2e2_ek/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2e2_ek/board_init.c b/ra/board/ra2e2_ek/board_init.c
index acf080097..85380bcd8 100644
--- a/ra/board/ra2e2_ek/board_init.c
+++ b/ra/board/ra2e2_ek/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2e2_ek/board_init.h b/ra/board/ra2e2_ek/board_init.h
index e7cf0e077..f007255d4 100644
--- a/ra/board/ra2e2_ek/board_init.h
+++ b/ra/board/ra2e2_ek/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2e2_ek/board_leds.c b/ra/board/ra2e2_ek/board_leds.c
index 9f08b159f..7f6666a53 100644
--- a/ra/board/ra2e2_ek/board_leds.c
+++ b/ra/board/ra2e2_ek/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2e2_ek/board_leds.h b/ra/board/ra2e2_ek/board_leds.h
index 61532bd11..b03ed23c3 100644
--- a/ra/board/ra2e2_ek/board_leds.h
+++ b/ra/board/ra2e2_ek/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2e2_fpb/board.h b/ra/board/ra2e2_fpb/board.h
index 08a72d942..2c3de100a 100644
--- a/ra/board/ra2e2_fpb/board.h
+++ b/ra/board/ra2e2_fpb/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2e2_fpb/board_init.c b/ra/board/ra2e2_fpb/board_init.c
index 102b31d7b..64606020e 100644
--- a/ra/board/ra2e2_fpb/board_init.c
+++ b/ra/board/ra2e2_fpb/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2e2_fpb/board_init.h b/ra/board/ra2e2_fpb/board_init.h
index 0d3f6e64e..d98f6afa2 100644
--- a/ra/board/ra2e2_fpb/board_init.h
+++ b/ra/board/ra2e2_fpb/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2e2_fpb/board_leds.c b/ra/board/ra2e2_fpb/board_leds.c
index 7ead13115..4acf4b709 100644
--- a/ra/board/ra2e2_fpb/board_leds.c
+++ b/ra/board/ra2e2_fpb/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2e2_fpb/board_leds.h b/ra/board/ra2e2_fpb/board_leds.h
index 7f2936d38..73fa0ec80 100644
--- a/ra/board/ra2e2_fpb/board_leds.h
+++ b/ra/board/ra2e2_fpb/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2l1_ek/board.h b/ra/board/ra2l1_ek/board.h
index 670f51deb..2ba249357 100644
--- a/ra/board/ra2l1_ek/board.h
+++ b/ra/board/ra2l1_ek/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2l1_ek/board_init.c b/ra/board/ra2l1_ek/board_init.c
index 6bde3c221..ce4e4b91e 100644
--- a/ra/board/ra2l1_ek/board_init.c
+++ b/ra/board/ra2l1_ek/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2l1_ek/board_init.h b/ra/board/ra2l1_ek/board_init.h
index 6418aef15..b3f634f08 100644
--- a/ra/board/ra2l1_ek/board_init.h
+++ b/ra/board/ra2l1_ek/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2l1_ek/board_leds.c b/ra/board/ra2l1_ek/board_leds.c
index 69e285cda..a3ffbfe58 100644
--- a/ra/board/ra2l1_ek/board_leds.c
+++ b/ra/board/ra2l1_ek/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2l1_ek/board_leds.h b/ra/board/ra2l1_ek/board_leds.h
index c491e1fdb..50cc2ddb7 100644
--- a/ra/board/ra2l1_ek/board_leds.h
+++ b/ra/board/ra2l1_ek/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2l1_rssk/board.h b/ra/board/ra2l1_rssk/board.h
index 266bf1c89..1a85f925c 100644
--- a/ra/board/ra2l1_rssk/board.h
+++ b/ra/board/ra2l1_rssk/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2l1_rssk/board_init.c b/ra/board/ra2l1_rssk/board_init.c
index 700edfda2..6a9244120 100644
--- a/ra/board/ra2l1_rssk/board_init.c
+++ b/ra/board/ra2l1_rssk/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2l1_rssk/board_init.h b/ra/board/ra2l1_rssk/board_init.h
index 8b1c5c342..ac5afd005 100644
--- a/ra/board/ra2l1_rssk/board_init.h
+++ b/ra/board/ra2l1_rssk/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2l1_rssk/board_leds.c b/ra/board/ra2l1_rssk/board_leds.c
index fc1df442c..093a05d39 100644
--- a/ra/board/ra2l1_rssk/board_leds.c
+++ b/ra/board/ra2l1_rssk/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra2l1_rssk/board_leds.h b/ra/board/ra2l1_rssk/board_leds.h
index 9475b27bb..cc9e7bc3d 100644
--- a/ra/board/ra2l1_rssk/board_leds.h
+++ b/ra/board/ra2l1_rssk/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4e1_fpb/board.h b/ra/board/ra4e1_fpb/board.h
index 4f7f7ba8a..57f5c9c98 100644
--- a/ra/board/ra4e1_fpb/board.h
+++ b/ra/board/ra4e1_fpb/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4e1_fpb/board_init.c b/ra/board/ra4e1_fpb/board_init.c
index 51625c50c..35fc69c43 100644
--- a/ra/board/ra4e1_fpb/board_init.c
+++ b/ra/board/ra4e1_fpb/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4e1_fpb/board_init.h b/ra/board/ra4e1_fpb/board_init.h
index e68ad2aea..298aa4338 100644
--- a/ra/board/ra4e1_fpb/board_init.h
+++ b/ra/board/ra4e1_fpb/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4e1_fpb/board_leds.c b/ra/board/ra4e1_fpb/board_leds.c
index 3d21fd010..b719414ed 100644
--- a/ra/board/ra4e1_fpb/board_leds.c
+++ b/ra/board/ra4e1_fpb/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4e1_fpb/board_leds.h b/ra/board/ra4e1_fpb/board_leds.h
index 87a094852..b90562cb8 100644
--- a/ra/board/ra4e1_fpb/board_leds.h
+++ b/ra/board/ra4e1_fpb/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4e2_ek/board.h b/ra/board/ra4e2_ek/board.h
new file mode 100644
index 000000000..7d937f11d
--- /dev/null
+++ b/ra/board/ra4e2_ek/board.h
@@ -0,0 +1,66 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * File Name    : board.h
+ * Description  : Includes and API function available for this board.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup BOARDS
+ * @defgroup BOARD_RA4E2_EK
+ * @brief BSP for the RA4E2_EK Board
+ *
+ * The RA4E2_EK is a development kit for the Renesas RA4E2 microcontroller.
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/* BSP Board Specific Includes. */
+#include "board_init.h"
+#include "board_leds.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BOARD_RA4E2_EK
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** @} (end defgroup BOARD_RA4E2_EK) */
+
+#endif
diff --git a/ra/board/ra4e2_ek/board_init.c b/ra/board/ra4e2_ek/board_init.c
new file mode 100644
index 000000000..361794eac
--- /dev/null
+++ b/ra/board/ra4e2_ek/board_init.c
@@ -0,0 +1,67 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * File Name    : board_init.c
+ * Description  : This module calls any initialization code specific to this BSP.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BOARD_RA4E2_EK_INIT
+ *
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+#if defined(BOARD_RA4E2_EK)
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @brief      Performs any initialization specific to this BSP.
+ *
+ * @param[in]  p_args         Pointer to arguments of the user's choice.
+ **********************************************************************************************************************/
+void bsp_init (void * p_args)
+{
+    FSP_PARAMETER_NOT_USED(p_args);
+}
+
+#endif
+
+/** @} (end addtogroup BOARD_RA4E2_EK_INIT) */
diff --git a/ra/board/ra4e2_ek/board_init.h b/ra/board/ra4e2_ek/board_init.h
new file mode 100644
index 000000000..2189ce9a5
--- /dev/null
+++ b/ra/board/ra4e2_ek/board_init.h
@@ -0,0 +1,64 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * File Name    : board_init.h
+ * Description  : This module calls any initialization code specific to this BSP.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup BOARD_RA4E2_EK
+ * @defgroup BOARD_RA4E2_EK_INIT
+ * @brief Board specific code for the RA4E2_EK Board
+ *
+ * This include file is specific to the RA4E2_EK board.
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef BOARD_INIT_H
+#define BOARD_INIT_H
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+void bsp_init(void * p_args);
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
+
+/** @} (end defgroup BOARD_RA4E2_EK_INIT) */
diff --git a/ra/board/ra4e2_ek/board_leds.c b/ra/board/ra4e2_ek/board_leds.c
new file mode 100644
index 000000000..720e83f4f
--- /dev/null
+++ b/ra/board/ra4e2_ek/board_leds.c
@@ -0,0 +1,76 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * File Name    : board_leds.c
+ * Description  : This module has information about the LEDs on this board.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BOARD_RA4E2_EK_LEDS
+ *
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#if defined(BOARD_RA4E2_EK)
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/** Array of LED IOPORT pins. */
+static const uint16_t g_bsp_prv_leds[] =
+{
+    (uint16_t) BSP_IO_PORT_02_PIN_07,  ///< LED1
+    (uint16_t) BSP_IO_PORT_01_PIN_04,  ///< LED2
+    (uint16_t) BSP_IO_PORT_01_PIN_12,  ///< LED3
+};
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** Structure with LED information for this board. */
+
+const bsp_leds_t g_bsp_leds =
+{
+    .led_count = (uint16_t) ((sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0]))),
+    .p_leds    = &g_bsp_prv_leds[0]
+};
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+#endif
+
+/** @} (end addtogroup BOARD_RA4E2_EK_LEDS) */
diff --git a/ra/board/ra4e2_ek/board_leds.h b/ra/board/ra4e2_ek/board_leds.h
new file mode 100644
index 000000000..39872a1a4
--- /dev/null
+++ b/ra/board/ra4e2_ek/board_leds.h
@@ -0,0 +1,80 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * File Name    : board_leds.h
+ * Description  : This module has information about the LEDs on this board.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup BOARD_RA4E2_EK
+ * @defgroup BOARD_RA4E2_EK_LEDS Board LEDs
+ * @brief LED information for this board.
+ *
+ * This is code specific to the RA4E2_EK board. It includes info on the number of LEDs and which pins are they
+ * are on.
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef BOARD_LEDS_H
+#define BOARD_LEDS_H
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Information on how many LEDs and what pins they are on. */
+typedef struct st_bsp_leds
+{
+    uint16_t         led_count;        ///< The number of LEDs on this board
+    uint16_t const * p_leds;           ///< Pointer to an array of IOPORT pins for controlling LEDs
+} bsp_leds_t;
+
+/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins
+ * found in the bsp_leds_t structure. */
+typedef enum e_bsp_led
+{
+    BSP_LED_LED1 = 0,
+    BSP_LED_LED2 = 1,
+    BSP_LED_LED3 = 2,
+} bsp_led_t;
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Public Functions
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
+
+/** @} (end defgroup BOARD_RA4E2_EK_LEDS) */
diff --git a/ra/board/ra4m1_ek/board.h b/ra/board/ra4m1_ek/board.h
index 710e3ee14..994d1cc56 100644
--- a/ra/board/ra4m1_ek/board.h
+++ b/ra/board/ra4m1_ek/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4m1_ek/board_init.c b/ra/board/ra4m1_ek/board_init.c
index fb8b25aa2..a63c1a26c 100644
--- a/ra/board/ra4m1_ek/board_init.c
+++ b/ra/board/ra4m1_ek/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4m1_ek/board_init.h b/ra/board/ra4m1_ek/board_init.h
index 71a6ba639..e5baf7ae4 100644
--- a/ra/board/ra4m1_ek/board_init.h
+++ b/ra/board/ra4m1_ek/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4m1_ek/board_leds.c b/ra/board/ra4m1_ek/board_leds.c
index 964515b5b..64ca3574f 100644
--- a/ra/board/ra4m1_ek/board_leds.c
+++ b/ra/board/ra4m1_ek/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4m1_ek/board_leds.h b/ra/board/ra4m1_ek/board_leds.h
index fb447bec7..06d873a6b 100644
--- a/ra/board/ra4m1_ek/board_leds.h
+++ b/ra/board/ra4m1_ek/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4m2_ek/board.h b/ra/board/ra4m2_ek/board.h
index ad6ff6439..a9d96ff2c 100644
--- a/ra/board/ra4m2_ek/board.h
+++ b/ra/board/ra4m2_ek/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4m2_ek/board_init.c b/ra/board/ra4m2_ek/board_init.c
index 9f11579b1..ddf2e1c48 100644
--- a/ra/board/ra4m2_ek/board_init.c
+++ b/ra/board/ra4m2_ek/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4m2_ek/board_init.h b/ra/board/ra4m2_ek/board_init.h
index 77381777e..5d762360f 100644
--- a/ra/board/ra4m2_ek/board_init.h
+++ b/ra/board/ra4m2_ek/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4m2_ek/board_leds.c b/ra/board/ra4m2_ek/board_leds.c
index 53058d850..15d9e939d 100644
--- a/ra/board/ra4m2_ek/board_leds.c
+++ b/ra/board/ra4m2_ek/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4m2_ek/board_leds.h b/ra/board/ra4m2_ek/board_leds.h
index 89c6f6b1e..b447dc19f 100644
--- a/ra/board/ra4m2_ek/board_leds.h
+++ b/ra/board/ra4m2_ek/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4m3_ek/board.h b/ra/board/ra4m3_ek/board.h
index bfb3b4848..5626bad83 100644
--- a/ra/board/ra4m3_ek/board.h
+++ b/ra/board/ra4m3_ek/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4m3_ek/board_init.c b/ra/board/ra4m3_ek/board_init.c
index 258183b35..778760263 100644
--- a/ra/board/ra4m3_ek/board_init.c
+++ b/ra/board/ra4m3_ek/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4m3_ek/board_init.h b/ra/board/ra4m3_ek/board_init.h
index a752aa166..2f3f652f3 100644
--- a/ra/board/ra4m3_ek/board_init.h
+++ b/ra/board/ra4m3_ek/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4m3_ek/board_leds.c b/ra/board/ra4m3_ek/board_leds.c
index 32e761424..0bd236f8d 100644
--- a/ra/board/ra4m3_ek/board_leds.c
+++ b/ra/board/ra4m3_ek/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4m3_ek/board_leds.h b/ra/board/ra4m3_ek/board_leds.h
index a6891ac15..a773841ee 100644
--- a/ra/board/ra4m3_ek/board_leds.h
+++ b/ra/board/ra4m3_ek/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4w1_ek/board.h b/ra/board/ra4w1_ek/board.h
index bfa2c622b..7a4a4906a 100644
--- a/ra/board/ra4w1_ek/board.h
+++ b/ra/board/ra4w1_ek/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4w1_ek/board_init.c b/ra/board/ra4w1_ek/board_init.c
index 93ca51da8..f9ec9c30f 100644
--- a/ra/board/ra4w1_ek/board_init.c
+++ b/ra/board/ra4w1_ek/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4w1_ek/board_init.h b/ra/board/ra4w1_ek/board_init.h
index 10843e90d..08d57bac9 100644
--- a/ra/board/ra4w1_ek/board_init.h
+++ b/ra/board/ra4w1_ek/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4w1_ek/board_leds.c b/ra/board/ra4w1_ek/board_leds.c
index 4715d9fc2..d1e56a46a 100644
--- a/ra/board/ra4w1_ek/board_leds.c
+++ b/ra/board/ra4w1_ek/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra4w1_ek/board_leds.h b/ra/board/ra4w1_ek/board_leds.h
index 3ca7fa3d8..95ec96ef7 100644
--- a/ra/board/ra4w1_ek/board_leds.h
+++ b/ra/board/ra4w1_ek/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6e1_fpb/board.h b/ra/board/ra6e1_fpb/board.h
index 5b04613b2..265da7f7a 100644
--- a/ra/board/ra6e1_fpb/board.h
+++ b/ra/board/ra6e1_fpb/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6e1_fpb/board_init.c b/ra/board/ra6e1_fpb/board_init.c
index 362b1a544..7838e7044 100644
--- a/ra/board/ra6e1_fpb/board_init.c
+++ b/ra/board/ra6e1_fpb/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6e1_fpb/board_init.h b/ra/board/ra6e1_fpb/board_init.h
index 354c5efbd..df6f85987 100644
--- a/ra/board/ra6e1_fpb/board_init.h
+++ b/ra/board/ra6e1_fpb/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6e1_fpb/board_leds.c b/ra/board/ra6e1_fpb/board_leds.c
index 42fe8332a..6cb24fd36 100644
--- a/ra/board/ra6e1_fpb/board_leds.c
+++ b/ra/board/ra6e1_fpb/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6e1_fpb/board_leds.h b/ra/board/ra6e1_fpb/board_leds.h
index 5b695ce5e..a8d28571b 100644
--- a/ra/board/ra6e1_fpb/board_leds.h
+++ b/ra/board/ra6e1_fpb/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6e2_ek/board.h b/ra/board/ra6e2_ek/board.h
new file mode 100644
index 000000000..90397f244
--- /dev/null
+++ b/ra/board/ra6e2_ek/board.h
@@ -0,0 +1,66 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * File Name    : board.h
+ * Description  : Includes and API function available for this board.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup BOARDS
+ * @defgroup BOARD_RA6E2_EK
+ * @brief BSP for the RA6E2_EK Board
+ *
+ * The RA6E2_EK is a development kit for the Renesas RA6E2 microcontroller.
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/* BSP Board Specific Includes. */
+#include "board_init.h"
+#include "board_leds.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BOARD_RA6E2_EK
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** @} (end defgroup BOARD_RA6E2_EK) */
+
+#endif
diff --git a/ra/board/ra6e2_ek/board_init.c b/ra/board/ra6e2_ek/board_init.c
new file mode 100644
index 000000000..e79bfb00a
--- /dev/null
+++ b/ra/board/ra6e2_ek/board_init.c
@@ -0,0 +1,67 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * File Name    : board_init.c
+ * Description  : This module calls any initialization code specific to this BSP.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BOARD_RA6E2_EK_INIT
+ *
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+#if defined(BOARD_RA6E2_EK)
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @brief      Performs any initialization specific to this BSP.
+ *
+ * @param[in]  p_args         Pointer to arguments of the user's choice.
+ **********************************************************************************************************************/
+void bsp_init (void * p_args)
+{
+    FSP_PARAMETER_NOT_USED(p_args);
+}
+
+#endif
+
+/** @} (end addtogroup BOARD_RA6E2_EK_INIT) */
diff --git a/ra/board/ra6e2_ek/board_init.h b/ra/board/ra6e2_ek/board_init.h
new file mode 100644
index 000000000..691e2a281
--- /dev/null
+++ b/ra/board/ra6e2_ek/board_init.h
@@ -0,0 +1,64 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * File Name    : board_init.h
+ * Description  : This module calls any initialization code specific to this BSP.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup BOARD_RA6E2_EK
+ * @defgroup BOARD_RA6E2_EK_INIT
+ * @brief Board specific code for the RA6E2_EK Board
+ *
+ * This include file is specific to the RA6E2_EK board.
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef BOARD_INIT_H
+#define BOARD_INIT_H
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+void bsp_init(void * p_args);
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
+
+/** @} (end defgroup BOARD_RA6E2_EK_INIT) */
diff --git a/ra/board/ra6e2_ek/board_leds.c b/ra/board/ra6e2_ek/board_leds.c
new file mode 100644
index 000000000..d4b1f0b33
--- /dev/null
+++ b/ra/board/ra6e2_ek/board_leds.c
@@ -0,0 +1,76 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * File Name    : board_leds.c
+ * Description  : This module has information about the LEDs on this board.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BOARD_RA6E2_EK_LEDS
+ *
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#if defined(BOARD_RA6E2_EK)
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/** Array of LED IOPORT pins. */
+static const uint16_t g_bsp_prv_leds[] =
+{
+    (uint16_t) BSP_IO_PORT_02_PIN_07,  ///< LED1
+    (uint16_t) BSP_IO_PORT_04_PIN_00,  ///< LED2
+    (uint16_t) BSP_IO_PORT_01_PIN_13,  ///< LED3
+};
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** Structure with LED information for this board. */
+
+const bsp_leds_t g_bsp_leds =
+{
+    .led_count = (uint16_t) ((sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0]))),
+    .p_leds    = &g_bsp_prv_leds[0]
+};
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+#endif
+
+/** @} (end addtogroup BOARD_RA6E2_EK_LEDS) */
diff --git a/ra/board/ra6e2_ek/board_leds.h b/ra/board/ra6e2_ek/board_leds.h
new file mode 100644
index 000000000..f40c98451
--- /dev/null
+++ b/ra/board/ra6e2_ek/board_leds.h
@@ -0,0 +1,80 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * File Name    : board_leds.h
+ * Description  : This module has information about the LEDs on this board.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup BOARD_RA6E2_EK
+ * @defgroup BOARD_RA6E2_EK_LEDS Board LEDs
+ * @brief LED information for this board.
+ *
+ * This is code specific to the RA6E2_EK board. It includes info on the number of LEDs and which pins are they
+ * are on.
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef BOARD_LEDS_H
+#define BOARD_LEDS_H
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Information on how many LEDs and what pins they are on. */
+typedef struct st_bsp_leds
+{
+    uint16_t         led_count;        ///< The number of LEDs on this board
+    uint16_t const * p_leds;           ///< Pointer to an array of IOPORT pins for controlling LEDs
+} bsp_leds_t;
+
+/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins
+ * found in the bsp_leds_t structure. */
+typedef enum e_bsp_led
+{
+    BSP_LED_LED1 = 0,
+    BSP_LED_LED2 = 1,
+    BSP_LED_LED3 = 2,
+} bsp_led_t;
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Public Functions
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
+
+/** @} (end defgroup BOARD_RA6E2_EK_LEDS) */
diff --git a/ra/board/ra6m1_ek/board.h b/ra/board/ra6m1_ek/board.h
index c1301ae9a..daf0224bf 100644
--- a/ra/board/ra6m1_ek/board.h
+++ b/ra/board/ra6m1_ek/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m1_ek/board_init.c b/ra/board/ra6m1_ek/board_init.c
index ea50f379e..4ac6204f1 100644
--- a/ra/board/ra6m1_ek/board_init.c
+++ b/ra/board/ra6m1_ek/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m1_ek/board_init.h b/ra/board/ra6m1_ek/board_init.h
index a0050d454..dd61bc111 100644
--- a/ra/board/ra6m1_ek/board_init.h
+++ b/ra/board/ra6m1_ek/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m1_ek/board_leds.c b/ra/board/ra6m1_ek/board_leds.c
index 90ad46e63..5bb0c0700 100644
--- a/ra/board/ra6m1_ek/board_leds.c
+++ b/ra/board/ra6m1_ek/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m1_ek/board_leds.h b/ra/board/ra6m1_ek/board_leds.h
index 52b45c4b3..a43b4f8c9 100644
--- a/ra/board/ra6m1_ek/board_leds.h
+++ b/ra/board/ra6m1_ek/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m2_ek/board.h b/ra/board/ra6m2_ek/board.h
index fea7fd366..371dbfca9 100644
--- a/ra/board/ra6m2_ek/board.h
+++ b/ra/board/ra6m2_ek/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m2_ek/board_ethernet_phy.h b/ra/board/ra6m2_ek/board_ethernet_phy.h
index 0767e059b..08e0149a1 100644
--- a/ra/board/ra6m2_ek/board_ethernet_phy.h
+++ b/ra/board/ra6m2_ek/board_ethernet_phy.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m2_ek/board_init.c b/ra/board/ra6m2_ek/board_init.c
index ca31dd5bc..f8a0524f5 100644
--- a/ra/board/ra6m2_ek/board_init.c
+++ b/ra/board/ra6m2_ek/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m2_ek/board_init.h b/ra/board/ra6m2_ek/board_init.h
index 1d85da4c8..95f448221 100644
--- a/ra/board/ra6m2_ek/board_init.h
+++ b/ra/board/ra6m2_ek/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m2_ek/board_leds.c b/ra/board/ra6m2_ek/board_leds.c
index 41067176a..1236098a9 100644
--- a/ra/board/ra6m2_ek/board_leds.c
+++ b/ra/board/ra6m2_ek/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m2_ek/board_leds.h b/ra/board/ra6m2_ek/board_leds.h
index 0ba6e39f1..529c26b53 100644
--- a/ra/board/ra6m2_ek/board_leds.h
+++ b/ra/board/ra6m2_ek/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m3_ek/board.h b/ra/board/ra6m3_ek/board.h
index 2b7ee525e..6759a6e4d 100644
--- a/ra/board/ra6m3_ek/board.h
+++ b/ra/board/ra6m3_ek/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m3_ek/board_ethernet_phy.h b/ra/board/ra6m3_ek/board_ethernet_phy.h
index ba306c2a7..9f8400f73 100644
--- a/ra/board/ra6m3_ek/board_ethernet_phy.h
+++ b/ra/board/ra6m3_ek/board_ethernet_phy.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m3_ek/board_init.c b/ra/board/ra6m3_ek/board_init.c
index 1d378baad..b2909906a 100644
--- a/ra/board/ra6m3_ek/board_init.c
+++ b/ra/board/ra6m3_ek/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m3_ek/board_init.h b/ra/board/ra6m3_ek/board_init.h
index c1b5b635f..5a515bedd 100644
--- a/ra/board/ra6m3_ek/board_init.h
+++ b/ra/board/ra6m3_ek/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m3_ek/board_leds.c b/ra/board/ra6m3_ek/board_leds.c
index c89293dc5..2fdaf5e85 100644
--- a/ra/board/ra6m3_ek/board_leds.c
+++ b/ra/board/ra6m3_ek/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m3_ek/board_leds.h b/ra/board/ra6m3_ek/board_leds.h
index 02680211e..ddff479ab 100644
--- a/ra/board/ra6m3_ek/board_leds.h
+++ b/ra/board/ra6m3_ek/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m3g_ek/board.h b/ra/board/ra6m3g_ek/board.h
index fd1dc4133..a430dce61 100644
--- a/ra/board/ra6m3g_ek/board.h
+++ b/ra/board/ra6m3g_ek/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m3g_ek/board_ethernet_phy.h b/ra/board/ra6m3g_ek/board_ethernet_phy.h
index 0e6b24ef6..2be879029 100644
--- a/ra/board/ra6m3g_ek/board_ethernet_phy.h
+++ b/ra/board/ra6m3g_ek/board_ethernet_phy.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m3g_ek/board_init.c b/ra/board/ra6m3g_ek/board_init.c
index b8b346cb5..69afcb8f9 100644
--- a/ra/board/ra6m3g_ek/board_init.c
+++ b/ra/board/ra6m3g_ek/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m3g_ek/board_init.h b/ra/board/ra6m3g_ek/board_init.h
index db76ac4ef..c2e0ab96c 100644
--- a/ra/board/ra6m3g_ek/board_init.h
+++ b/ra/board/ra6m3g_ek/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m3g_ek/board_leds.c b/ra/board/ra6m3g_ek/board_leds.c
index 59d57a6d2..0ba966feb 100644
--- a/ra/board/ra6m3g_ek/board_leds.c
+++ b/ra/board/ra6m3g_ek/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m3g_ek/board_leds.h b/ra/board/ra6m3g_ek/board_leds.h
index 8b3549221..9d25acba3 100644
--- a/ra/board/ra6m3g_ek/board_leds.h
+++ b/ra/board/ra6m3g_ek/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m4_ek/board.h b/ra/board/ra6m4_ek/board.h
index 7a56995d4..e83997b3e 100644
--- a/ra/board/ra6m4_ek/board.h
+++ b/ra/board/ra6m4_ek/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m4_ek/board_ethernet_phy.h b/ra/board/ra6m4_ek/board_ethernet_phy.h
index 934234757..df4cac6c8 100644
--- a/ra/board/ra6m4_ek/board_ethernet_phy.h
+++ b/ra/board/ra6m4_ek/board_ethernet_phy.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m4_ek/board_init.c b/ra/board/ra6m4_ek/board_init.c
index ac1c0a1ee..673825b79 100644
--- a/ra/board/ra6m4_ek/board_init.c
+++ b/ra/board/ra6m4_ek/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m4_ek/board_init.h b/ra/board/ra6m4_ek/board_init.h
index 9b387e207..cde14dfe1 100644
--- a/ra/board/ra6m4_ek/board_init.h
+++ b/ra/board/ra6m4_ek/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m4_ek/board_leds.c b/ra/board/ra6m4_ek/board_leds.c
index 36901b22d..bd4c031ae 100644
--- a/ra/board/ra6m4_ek/board_leds.c
+++ b/ra/board/ra6m4_ek/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m4_ek/board_leds.h b/ra/board/ra6m4_ek/board_leds.h
index 17cbb889b..fd811ab5f 100644
--- a/ra/board/ra6m4_ek/board_leds.h
+++ b/ra/board/ra6m4_ek/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m5_ck/board.h b/ra/board/ra6m5_ck/board.h
index 25e1d0c67..2fe390e94 100644
--- a/ra/board/ra6m5_ck/board.h
+++ b/ra/board/ra6m5_ck/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m5_ck/board_ethernet_phy.h b/ra/board/ra6m5_ck/board_ethernet_phy.h
index 134c34264..9538e28b3 100644
--- a/ra/board/ra6m5_ck/board_ethernet_phy.h
+++ b/ra/board/ra6m5_ck/board_ethernet_phy.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m5_ck/board_init.c b/ra/board/ra6m5_ck/board_init.c
index 1d325d4cc..0750a7bbf 100644
--- a/ra/board/ra6m5_ck/board_init.c
+++ b/ra/board/ra6m5_ck/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m5_ck/board_init.h b/ra/board/ra6m5_ck/board_init.h
index 2352848d1..7aae11634 100644
--- a/ra/board/ra6m5_ck/board_init.h
+++ b/ra/board/ra6m5_ck/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m5_ck/board_leds.c b/ra/board/ra6m5_ck/board_leds.c
index cdf567e00..b8e94c2fb 100644
--- a/ra/board/ra6m5_ck/board_leds.c
+++ b/ra/board/ra6m5_ck/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m5_ck/board_leds.h b/ra/board/ra6m5_ck/board_leds.h
index ee109f903..a33170842 100644
--- a/ra/board/ra6m5_ck/board_leds.h
+++ b/ra/board/ra6m5_ck/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m5_ek/board.h b/ra/board/ra6m5_ek/board.h
index 3a069d536..d60014507 100644
--- a/ra/board/ra6m5_ek/board.h
+++ b/ra/board/ra6m5_ek/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m5_ek/board_ethernet_phy.h b/ra/board/ra6m5_ek/board_ethernet_phy.h
index 8dba15491..0dc0983ef 100644
--- a/ra/board/ra6m5_ek/board_ethernet_phy.h
+++ b/ra/board/ra6m5_ek/board_ethernet_phy.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m5_ek/board_init.c b/ra/board/ra6m5_ek/board_init.c
index eb91274a4..c1a607041 100644
--- a/ra/board/ra6m5_ek/board_init.c
+++ b/ra/board/ra6m5_ek/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m5_ek/board_init.h b/ra/board/ra6m5_ek/board_init.h
index 755f73cdd..3be95ba4d 100644
--- a/ra/board/ra6m5_ek/board_init.h
+++ b/ra/board/ra6m5_ek/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m5_ek/board_leds.c b/ra/board/ra6m5_ek/board_leds.c
index 97a0ac47b..7aad245f8 100644
--- a/ra/board/ra6m5_ek/board_leds.c
+++ b/ra/board/ra6m5_ek/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6m5_ek/board_leds.h b/ra/board/ra6m5_ek/board_leds.h
index ad1e76ddd..43ec36b85 100644
--- a/ra/board/ra6m5_ek/board_leds.h
+++ b/ra/board/ra6m5_ek/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6t1_rssk/board.h b/ra/board/ra6t1_rssk/board.h
index 178328082..89ae248b0 100644
--- a/ra/board/ra6t1_rssk/board.h
+++ b/ra/board/ra6t1_rssk/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6t1_rssk/board_init.c b/ra/board/ra6t1_rssk/board_init.c
index ad6294dd9..735dae539 100644
--- a/ra/board/ra6t1_rssk/board_init.c
+++ b/ra/board/ra6t1_rssk/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6t1_rssk/board_init.h b/ra/board/ra6t1_rssk/board_init.h
index 94a34315d..1f83d5cc4 100644
--- a/ra/board/ra6t1_rssk/board_init.h
+++ b/ra/board/ra6t1_rssk/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6t1_rssk/board_leds.c b/ra/board/ra6t1_rssk/board_leds.c
index 681c72dce..f8bf98cf1 100644
--- a/ra/board/ra6t1_rssk/board_leds.c
+++ b/ra/board/ra6t1_rssk/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6t1_rssk/board_leds.h b/ra/board/ra6t1_rssk/board_leds.h
index d13a36901..aa3e17c5d 100644
--- a/ra/board/ra6t1_rssk/board_leds.h
+++ b/ra/board/ra6t1_rssk/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6t2_mck/board.h b/ra/board/ra6t2_mck/board.h
index 4b0908b71..024a6d0cd 100644
--- a/ra/board/ra6t2_mck/board.h
+++ b/ra/board/ra6t2_mck/board.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6t2_mck/board_init.c b/ra/board/ra6t2_mck/board_init.c
index 02862198b..18573cff0 100644
--- a/ra/board/ra6t2_mck/board_init.c
+++ b/ra/board/ra6t2_mck/board_init.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6t2_mck/board_init.h b/ra/board/ra6t2_mck/board_init.h
index 9ce31824f..38fa013db 100644
--- a/ra/board/ra6t2_mck/board_init.h
+++ b/ra/board/ra6t2_mck/board_init.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6t2_mck/board_leds.c b/ra/board/ra6t2_mck/board_leds.c
index 13061f5e4..17de1a2b4 100644
--- a/ra/board/ra6t2_mck/board_leds.c
+++ b/ra/board/ra6t2_mck/board_leds.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/board/ra6t2_mck/board_leds.h b/ra/board/ra6t2_mck/board_leds.h
index 01e90a3c6..b8726af45 100644
--- a/ra/board/ra6t2_mck/board_leds.h
+++ b/ra/board/ra6t2_mck/board_leds.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/bsp_api.h b/ra/fsp/inc/api/bsp_api.h
index c492baf3a..9148440c8 100644
--- a/ra/fsp/inc/api/bsp_api.h
+++ b/ra/fsp/inc/api/bsp_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_adc_api.h b/ra/fsp/inc/api/r_adc_api.h
index 0063be446..54893f84e 100644
--- a/ra/fsp/inc/api/r_adc_api.h
+++ b/ra/fsp/inc/api/r_adc_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_ble_api.h b/ra/fsp/inc/api/r_ble_api.h
index 7a9362b5d..721e619d4 100644
--- a/ra/fsp/inc/api/r_ble_api.h
+++ b/ra/fsp/inc/api/r_ble_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_cac_api.h b/ra/fsp/inc/api/r_cac_api.h
index f4ac0feae..213dd8750 100644
--- a/ra/fsp/inc/api/r_cac_api.h
+++ b/ra/fsp/inc/api/r_cac_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_can_api.h b/ra/fsp/inc/api/r_can_api.h
index 729d08de8..10249c0d0 100644
--- a/ra/fsp/inc/api/r_can_api.h
+++ b/ra/fsp/inc/api/r_can_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_cec_api.h b/ra/fsp/inc/api/r_cec_api.h
index 2da565b17..e40386f38 100644
--- a/ra/fsp/inc/api/r_cec_api.h
+++ b/ra/fsp/inc/api/r_cec_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_cgc_api.h b/ra/fsp/inc/api/r_cgc_api.h
index 0637f9401..0ce587e43 100644
--- a/ra/fsp/inc/api/r_cgc_api.h
+++ b/ra/fsp/inc/api/r_cgc_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_comparator_api.h b/ra/fsp/inc/api/r_comparator_api.h
index 156448b80..4bdbf3035 100644
--- a/ra/fsp/inc/api/r_comparator_api.h
+++ b/ra/fsp/inc/api/r_comparator_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_crc_api.h b/ra/fsp/inc/api/r_crc_api.h
index 530a059e5..c1a78fe58 100644
--- a/ra/fsp/inc/api/r_crc_api.h
+++ b/ra/fsp/inc/api/r_crc_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -150,7 +150,8 @@ typedef struct st_crc_cfg
 {
     crc_polynomial_t    polynomial;    ///< CRC Generating Polynomial Switching (GPS)
     crc_bit_order_t     bit_order;     ///< CRC Calculation Switching (LMS)
-    crc_snoop_address_t snoop_address; ///< Register Snoop Address (CRCSA)
+    /* crc_snoop_address_t is to be deprecated. */
+    int32_t             snoop_address; ///< Register Snoop Address (CRCSA)
     void const        * p_extend;      ///< CRC Hardware Dependent Configuration
 } crc_cfg_t;
 
diff --git a/ra/fsp/inc/api/r_ctsu_api.h b/ra/fsp/inc/api/r_ctsu_api.h
index 62da563eb..fe99b58df 100644
--- a/ra/fsp/inc/api/r_ctsu_api.h
+++ b/ra/fsp/inc/api/r_ctsu_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_dac_api.h b/ra/fsp/inc/api/r_dac_api.h
index 63b14b8f1..774991965 100644
--- a/ra/fsp/inc/api/r_dac_api.h
+++ b/ra/fsp/inc/api/r_dac_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_display_api.h b/ra/fsp/inc/api/r_display_api.h
index 4da5f97f7..a21b54227 100644
--- a/ra/fsp/inc/api/r_display_api.h
+++ b/ra/fsp/inc/api/r_display_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_doc_api.h b/ra/fsp/inc/api/r_doc_api.h
index 028b84d76..523dfef26 100644
--- a/ra/fsp/inc/api/r_doc_api.h
+++ b/ra/fsp/inc/api/r_doc_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_elc_api.h b/ra/fsp/inc/api/r_elc_api.h
index 8e885b656..4b0dc2e5a 100644
--- a/ra/fsp/inc/api/r_elc_api.h
+++ b/ra/fsp/inc/api/r_elc_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_ether_api.h b/ra/fsp/inc/api/r_ether_api.h
index 2b7370a23..ce3bb989c 100644
--- a/ra/fsp/inc/api/r_ether_api.h
+++ b/ra/fsp/inc/api/r_ether_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_ether_phy_api.h b/ra/fsp/inc/api/r_ether_phy_api.h
index 5f041f1cb..5128d6978 100644
--- a/ra/fsp/inc/api/r_ether_phy_api.h
+++ b/ra/fsp/inc/api/r_ether_phy_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_external_irq_api.h b/ra/fsp/inc/api/r_external_irq_api.h
index f8b7e0436..1f60b32dd 100644
--- a/ra/fsp/inc/api/r_external_irq_api.h
+++ b/ra/fsp/inc/api/r_external_irq_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_flash_api.h b/ra/fsp/inc/api/r_flash_api.h
index 4c9c7236c..bb96af929 100644
--- a/ra/fsp/inc/api/r_flash_api.h
+++ b/ra/fsp/inc/api/r_flash_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_i2c_master_api.h b/ra/fsp/inc/api/r_i2c_master_api.h
index d9f60b36c..733f3c71a 100644
--- a/ra/fsp/inc/api/r_i2c_master_api.h
+++ b/ra/fsp/inc/api/r_i2c_master_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_i2c_slave_api.h b/ra/fsp/inc/api/r_i2c_slave_api.h
index 4339c9083..1ec67ef94 100644
--- a/ra/fsp/inc/api/r_i2c_slave_api.h
+++ b/ra/fsp/inc/api/r_i2c_slave_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_i2s_api.h b/ra/fsp/inc/api/r_i2s_api.h
index c19e99564..35d51428b 100644
--- a/ra/fsp/inc/api/r_i2s_api.h
+++ b/ra/fsp/inc/api/r_i2s_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_i3c_api.h b/ra/fsp/inc/api/r_i3c_api.h
index 0f07dc2d4..3f2c2313f 100644
--- a/ra/fsp/inc/api/r_i3c_api.h
+++ b/ra/fsp/inc/api/r_i3c_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_iir_api.h b/ra/fsp/inc/api/r_iir_api.h
index 3cb837278..29ef5a5ff 100644
--- a/ra/fsp/inc/api/r_iir_api.h
+++ b/ra/fsp/inc/api/r_iir_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_ioport_api.h b/ra/fsp/inc/api/r_ioport_api.h
index b2fcfdfc1..3ebc3aaa8 100644
--- a/ra/fsp/inc/api/r_ioport_api.h
+++ b/ra/fsp/inc/api/r_ioport_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_jpeg_api.h b/ra/fsp/inc/api/r_jpeg_api.h
index 28bf5056e..20eb98449 100644
--- a/ra/fsp/inc/api/r_jpeg_api.h
+++ b/ra/fsp/inc/api/r_jpeg_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_keymatrix_api.h b/ra/fsp/inc/api/r_keymatrix_api.h
index 5012d5916..a0ba4bec0 100644
--- a/ra/fsp/inc/api/r_keymatrix_api.h
+++ b/ra/fsp/inc/api/r_keymatrix_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_lpm_api.h b/ra/fsp/inc/api/r_lpm_api.h
index 5fcf1c207..ad7c91140 100644
--- a/ra/fsp/inc/api/r_lpm_api.h
+++ b/ra/fsp/inc/api/r_lpm_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_lvd_api.h b/ra/fsp/inc/api/r_lvd_api.h
index b73977c1c..ce9af107f 100644
--- a/ra/fsp/inc/api/r_lvd_api.h
+++ b/ra/fsp/inc/api/r_lvd_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_opamp_api.h b/ra/fsp/inc/api/r_opamp_api.h
index 9684f7bac..371a7d151 100644
--- a/ra/fsp/inc/api/r_opamp_api.h
+++ b/ra/fsp/inc/api/r_opamp_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_pdc_api.h b/ra/fsp/inc/api/r_pdc_api.h
index ca1e48f99..5fbae9b01 100644
--- a/ra/fsp/inc/api/r_pdc_api.h
+++ b/ra/fsp/inc/api/r_pdc_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_poeg_api.h b/ra/fsp/inc/api/r_poeg_api.h
index 2a46c65a8..13e0f12e9 100644
--- a/ra/fsp/inc/api/r_poeg_api.h
+++ b/ra/fsp/inc/api/r_poeg_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_ptp_api.h b/ra/fsp/inc/api/r_ptp_api.h
index f175175a6..53d67041a 100644
--- a/ra/fsp/inc/api/r_ptp_api.h
+++ b/ra/fsp/inc/api/r_ptp_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_rtc_api.h b/ra/fsp/inc/api/r_rtc_api.h
index b61e643c6..e72958c07 100644
--- a/ra/fsp/inc/api/r_rtc_api.h
+++ b/ra/fsp/inc/api/r_rtc_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_sce_key_injection_api.h b/ra/fsp/inc/api/r_sce_key_injection_api.h
index c2d943780..e6560e2ff 100644
--- a/ra/fsp/inc/api/r_sce_key_injection_api.h
+++ b/ra/fsp/inc/api/r_sce_key_injection_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -223,6 +223,21 @@ typedef struct st_sce_key_injection_api
                                         const uint8_t * const initial_vector,
                                         const uint8_t * const encrypted_key, sce_aes_wrapped_key_t * const wrapped_key);
 
+    /** This API outputs 192-bit AES wrapped key.
+     * @par Implemented as
+     * -  @ref R_SCE_AES192_InitialKeyWrap "R_SCE_AES192_InitialKeyWrap()"
+     *
+     * @param[in]     key_type                              Key type whether encrypted_key or plain key
+     * @param[in]     wrapped_user_factory_programming_key  Provisioning key wrapped by the DLM server
+     * @param[in]     initial_vector                        Initialization vector when generating encrypted_key
+     * @param[in]     encrypted_key                         User key encrypted and MAC appended
+     * @param[in,out] wrapped_key                           192-bit AES wrapped key
+     */
+    fsp_err_t (* AES192_InitialKeyWrap)(const uint8_t * const key_type,
+                                        const uint8_t * const wrapped_user_factory_programming_key,
+                                        const uint8_t * const initial_vector,
+                                        const uint8_t * const encrypted_key, sce_aes_wrapped_key_t * const wrapped_key);
+
     /** This API outputs 256-bit AES wrapped key.
      * @par Implemented as
      * - @ref R_SCE_AES256_InitialKeyWrap "R_SCE_AES256_InitialKeyWrap()"
@@ -559,6 +574,73 @@ typedef struct st_sce_key_injection_api
                                                         const sce_key_update_key_t * const    key_update_key,
                                                         sce_ecc_private_wrapped_key_t * const wrapped_key);
 
+    /** This API outputs 256-bit Brainpool ECC public wrapped key.
+     * @par Implemented as
+     * - @ref R_SCE_ECC_brainpoolP256r1_InitialPublicKeyWrap "R_SCE_ECC_brainpoolP256r1_InitialPublicKeyWrap()"
+     *
+     * @param[in]     key_type                              Key type whether encrypted_key or plain key
+     * @param[in]     wrapped_user_factory_programming_key  Provisioning key wrapped by the DLM server
+     * @param[in]     initial_vector                        Initialization vector when generating encrypted_key
+     * @param[in]     encrypted_key                         User key encrypted and MAC appended
+     * @param[in,out] wrapped_key                           256-bit ECC wrapped key
+     */
+    fsp_err_t (* ECC_brainpoolP256r1_InitialPublicKeyWrap)(const uint8_t * const key_type,
+                                                           const uint8_t * const
+                                                           wrapped_user_factory_programming_key,
+                                                           const uint8_t * const                initial_vector,
+                                                           const uint8_t * const                encrypted_key,
+                                                           sce_ecc_public_wrapped_key_t * const wrapped_key);
+
+    /** This API outputs 256-bit Brainpool ECC private wrapped key.
+     * @par Implemented as
+     * - @ref R_SCE_ECC_brainpoolP256r1_InitialPrivateKeyWrap "R_SCE_ECC_brainpoolP256r1_InitialPrivateKeyWrap()"
+     *
+     * @param[in]     key_type                              Key type whether encrypted_key or plain key
+     * @param[in]     wrapped_user_factory_programming_key  Provisioning key wrapped by the DLM server
+     * @param[in]     initial_vector                        Initialization vector when generating encrypted_key
+     * @param[in]     encrypted_key                         User key encrypted and MAC appended
+     * @param[in,out] wrapped_key                           256-bit ECC wrapped key
+     */
+    fsp_err_t (* ECC_brainpoolP256r1_InitialPrivateKeyWrap)(const uint8_t * const key_type,
+                                                            const uint8_t * const
+                                                            wrapped_user_factory_programming_key,
+                                                            const uint8_t * const                 initial_vector,
+                                                            const uint8_t * const                 encrypted_key,
+                                                            sce_ecc_private_wrapped_key_t * const wrapped_key);
+
+    /** This API outputs 384-bit Brainpool ECC public wrapped key.
+     * @par Implemented as
+     * - @ref R_SCE_ECC_brainpoolP384r1_InitialPublicKeyWrap "R_SCE_ECC_brainpoolP384r1_InitialPublicKeyWrap()"
+     *
+     * @param[in]     key_type                              Key type whether encrypted_key or plain key
+     * @param[in]     wrapped_user_factory_programming_key  Provisioning key wrapped by the DLM server
+     * @param[in]     initial_vector                        Initialization vector when generating encrypted_key
+     * @param[in]     encrypted_key                         User key encrypted and MAC appended
+     * @param[in,out] wrapped_key                           384-bit ECC wrapped key
+     */
+    fsp_err_t (* ECC_brainpoolP384r1_InitialPublicKeyWrap)(const uint8_t * const key_type,
+                                                           const uint8_t * const
+                                                           wrapped_user_factory_programming_key,
+                                                           const uint8_t * const                initial_vector,
+                                                           const uint8_t * const                encrypted_key,
+                                                           sce_ecc_public_wrapped_key_t * const wrapped_key);
+    
+    /** This API outputs 384-bit Brainpool ECC private wrapped key.
+     * @par Implemented as
+     * - @ref R_SCE_ECC_brainpoolP384r1_InitialPrivateKeyWrap "R_SCE_ECC_brainpoolP384r1_InitialPrivateKeyWrap()"
+     *
+     * @param[in]     key_type                              Key type whether encrypted_key or plain key
+     * @param[in]     wrapped_user_factory_programming_key  Provisioning key wrapped by the DLM server
+     * @param[in]     initial_vector                        Initialization vector when generating encrypted_key
+     * @param[in]     encrypted_key                         User key encrypted and MAC appended
+     * @param[in,out] wrapped_key                           384-bit ECC wrapped key
+     */
+    fsp_err_t (* ECC_brainpoolP384r1_InitialPrivateKeyWrap)(const uint8_t * const key_type,
+                                                            const uint8_t * const
+                                                            wrapped_user_factory_programming_key,
+                                                            const uint8_t * const                 initial_vector,
+                                                            const uint8_t * const                 encrypted_key,
+                                                            sce_ecc_private_wrapped_key_t * const wrapped_key);
 
 } sce_key_injection_api_t;
 
diff --git a/ra/fsp/inc/api/r_sdmmc_api.h b/ra/fsp/inc/api/r_sdmmc_api.h
index ebb756f69..6ae7d933c 100644
--- a/ra/fsp/inc/api/r_sdmmc_api.h
+++ b/ra/fsp/inc/api/r_sdmmc_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_slcdc_api.h b/ra/fsp/inc/api/r_slcdc_api.h
index d8351af45..41083504c 100644
--- a/ra/fsp/inc/api/r_slcdc_api.h
+++ b/ra/fsp/inc/api/r_slcdc_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_spi_api.h b/ra/fsp/inc/api/r_spi_api.h
index bc5ab3e72..2078d9d0e 100644
--- a/ra/fsp/inc/api/r_spi_api.h
+++ b/ra/fsp/inc/api/r_spi_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_spi_flash_api.h b/ra/fsp/inc/api/r_spi_flash_api.h
index ea304d1d5..733d793a0 100644
--- a/ra/fsp/inc/api/r_spi_flash_api.h
+++ b/ra/fsp/inc/api/r_spi_flash_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_three_phase_api.h b/ra/fsp/inc/api/r_three_phase_api.h
index 11599e0dd..af0b422d0 100644
--- a/ra/fsp/inc/api/r_three_phase_api.h
+++ b/ra/fsp/inc/api/r_three_phase_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_timer_api.h b/ra/fsp/inc/api/r_timer_api.h
index 57ef0c806..f53db2c8b 100644
--- a/ra/fsp/inc/api/r_timer_api.h
+++ b/ra/fsp/inc/api/r_timer_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_transfer_api.h b/ra/fsp/inc/api/r_transfer_api.h
index 2902df476..383b828d4 100644
--- a/ra/fsp/inc/api/r_transfer_api.h
+++ b/ra/fsp/inc/api/r_transfer_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_uart_api.h b/ra/fsp/inc/api/r_uart_api.h
index 8c130dbbc..779af1e80 100644
--- a/ra/fsp/inc/api/r_uart_api.h
+++ b/ra/fsp/inc/api/r_uart_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_usb_basic_api.h b/ra/fsp/inc/api/r_usb_basic_api.h
index 7b71b463e..c11aa65b2 100644
--- a/ra/fsp/inc/api/r_usb_basic_api.h
+++ b/ra/fsp/inc/api/r_usb_basic_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -234,6 +234,7 @@ typedef enum e_usb_class
     USB_CLASS_PHID2,                   ///< PHID2 Class
     USB_CLASS_PAUD,                    ///< PAUD Class
     USB_CLASS_PPRN,                    ///< PPRN Class
+    USB_CLASS_DFU,                     ///< DFU Class
     USB_CLASS_PVND,                    ///< PVND Class
     USB_CLASS_HCDC,                    ///< HCDC Class
     USB_CLASS_HCDCC,                   ///< HCDCC Class
diff --git a/ra/fsp/inc/api/r_usb_hcdc_api.h b/ra/fsp/inc/api/r_usb_hcdc_api.h
index 47fd966a1..ce9655a03 100644
--- a/ra/fsp/inc/api/r_usb_hcdc_api.h
+++ b/ra/fsp/inc/api/r_usb_hcdc_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_usb_hhid_api.h b/ra/fsp/inc/api/r_usb_hhid_api.h
index c012ecd97..0dacb197e 100644
--- a/ra/fsp/inc/api/r_usb_hhid_api.h
+++ b/ra/fsp/inc/api/r_usb_hhid_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_usb_hmsc_api.h b/ra/fsp/inc/api/r_usb_hmsc_api.h
index fd072a63d..2b3c22ab5 100644
--- a/ra/fsp/inc/api/r_usb_hmsc_api.h
+++ b/ra/fsp/inc/api/r_usb_hmsc_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_usb_pcdc_api.h b/ra/fsp/inc/api/r_usb_pcdc_api.h
index 3dde63385..c70ec1104 100644
--- a/ra/fsp/inc/api/r_usb_pcdc_api.h
+++ b/ra/fsp/inc/api/r_usb_pcdc_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_usb_phid_api.h b/ra/fsp/inc/api/r_usb_phid_api.h
index 28435464a..6f99bf594 100644
--- a/ra/fsp/inc/api/r_usb_phid_api.h
+++ b/ra/fsp/inc/api/r_usb_phid_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_usb_pmsc_api.h b/ra/fsp/inc/api/r_usb_pmsc_api.h
index d073f229e..0942ddd67 100644
--- a/ra/fsp/inc/api/r_usb_pmsc_api.h
+++ b/ra/fsp/inc/api/r_usb_pmsc_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_usb_pprn_api.h b/ra/fsp/inc/api/r_usb_pprn_api.h
index df390fe64..0e991a6f7 100644
--- a/ra/fsp/inc/api/r_usb_pprn_api.h
+++ b/ra/fsp/inc/api/r_usb_pprn_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/r_wdt_api.h b/ra/fsp/inc/api/r_wdt_api.h
index 0d3205599..0b8b58af1 100644
--- a/ra/fsp/inc/api/r_wdt_api.h
+++ b/ra/fsp/inc/api/r_wdt_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_adpcm_decoder_api.h b/ra/fsp/inc/api/rm_adpcm_decoder_api.h
index 0c9ecbf57..34073f62c 100644
--- a/ra/fsp/inc/api/rm_adpcm_decoder_api.h
+++ b/ra/fsp/inc/api/rm_adpcm_decoder_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_audio_playback_api.h b/ra/fsp/inc/api/rm_audio_playback_api.h
index c8a585b4f..736695dfa 100644
--- a/ra/fsp/inc/api/rm_audio_playback_api.h
+++ b/ra/fsp/inc/api/rm_audio_playback_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_ble_abs_api.h b/ra/fsp/inc/api/rm_ble_abs_api.h
index fe0bbd2ab..17bc04394 100644
--- a/ra/fsp/inc/api/rm_ble_abs_api.h
+++ b/ra/fsp/inc/api/rm_ble_abs_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -42,15 +42,14 @@
 /* Register definitions, common services and error codes. */
 #include "bsp_api.h"
 #include "r_ble_api.h"
-#ifndef BLE_CFG_RYZ012_DEVICE
- #ifndef BLE_CFG_DA14531_DEVICE
-   #include "r_flash_api.h"
-   #include "r_timer_api.h"
-  #endif
-#else
+
+#if defined(BLE_CFG_RYZ012_DEVICE) || defined(BLE_CFG_DA14xxx_DEVICE)
  #include "r_uart_api.h"
  #include "r_spi_api.h"
  #include "r_external_irq_api.h"
+#else
+ #include "r_flash_api.h"
+ #include "r_timer_api.h"
 #endif
 
 #include "fsp_common_api.h"
@@ -183,7 +182,7 @@ typedef struct st_ble_abs_pairing_parameter
     uint8_t local_key_distribute;        ///< Type of keys to be distributed from local device.
     uint8_t remote_key_distribute;       ///< Type of keys which local device requests a remote device to distribute.
     uint8_t maximum_key_size;            ///< Maximum LTK size.
-    uint8_t padding[2];                  ///< padding
+    uint8_t padding[2];                  ///< Reserved
 } ble_abs_pairing_parameter_t;
 
 /** GATT Server callback function and the priority. */
@@ -224,37 +223,36 @@ typedef struct st_ble_abs_legacy_advertising_parameter
     uint8_t * p_scan_response_data;
 
     /**
-     *  @brief  Advertising with the fast_advertising_interval parameter continues for the period specified \n
-     *  by the fast_period parameter.\n
-     *  Time(ms) = fast_advertising_interval * 0.625. \n
-     *  If the fast_period parameter is 0, this parameter is ignored.\n
+     *  @brief  Advertising with the  @ref fast_advertising_interval parameter continues for the period specified \n
+     *  by the  @ref fast_advertising_period parameter.\n
+     *  Time(ms) =  @ref fast_advertising_interval * 0.625. \n
+     *  If the @ref fast_advertising_period parameter is 0, this parameter is ignored.\n
      *  Valid range is 0x00000020 - 0x00FFFFFF.
      */
     uint32_t fast_advertising_interval;
 
     /**
-     *  @brief After the elapse of the fast_period, advertising with the slow_advertising_interval parameter continues \n
-     *  for the period specified by the slow_advertising_interval parameter.\n
-     *  Time(ms) = slow_advertising_interval * 0.625. \n
-     *  If the slow_advertising_interval parameter is 0, this parameter is ignored.\n
+     *  @brief After the elapse of the @ref fast_advertising_period, advertising with the @ref slow_advertising_interval parameter continues \n
+     *  for the period specified by the @ref slow_advertising_period parameter.\n
+     *  Time(ms) = @ref slow_advertising_interval * 0.625. \n
      *  Valid range is 0x00000020 - 0x00FFFFFF.
      */
     uint32_t slow_advertising_interval;
 
     /**
-     *  @brief The period which advertising with the fast_advertising_interval parameter continues for. \n
+     *  @brief The period which advertising with the  @ref fast_advertising_interval parameter continues for. \n
      *  Time = duration * 10ms.\n
-     *  After the elapse of the fast_advertising_period, @ref BLE_GAP_EVENT_ADV_OFF event notifies that the advertising has stopped.\n
+     *  After the elapse of the @ref fast_advertising_period, @ref BLE_GAP_EVENT_ADV_OFF event notifies that the advertising has stopped.\n
      *  Valid range is 0x0000 - 0xFFFF. \n
-     *  If the fast_advertising_period parameter is 0x0000, advertising with the fast_advertising_interval parameter is not performed.
+     *  If the @ref fast_advertising_period parameter is 0x0000, advertising with the @ref fast_advertising_interval parameter is not performed.
      */
     uint16_t fast_advertising_period;
 
     /**
-     *  @brief The period which advertising with the slow_advertising_interval parameter continues for. Time = duration * 10ms. \n
-     *  After the elapse of the slow_advertising_period, @ref BLE_GAP_EVENT_ADV_OFF event notifies that the advertising has stopped. \n
+     *  @brief The period which advertising with the @ref slow_advertising_interval parameter continues for. Time = duration * 10ms. \n
+     *  After the elapse of the @ref slow_advertising_period, @ref BLE_GAP_EVENT_ADV_OFF event notifies that the advertising has stopped. \n
      *  Valid range is 0x0000 - 0xFFFF. \n
-     *  If the slow_advertising_period parameter is 0x0000, the advertising continues.
+     *  If the @ref slow_advertising_period parameter is 0x0000, the advertising continues.
      */
     uint16_t slow_advertising_period;
 
@@ -298,14 +296,14 @@ typedef struct st_ble_abs_legacy_advertising_parameter
 
     /**
      *  @brief  Own Bluetooth address type. \n Select one of the following.
-     *    |  macro                              |   description                                                                                                                |
-     *    |:------------------------------------|:---------------------------------------------------------------------------------------------------------------------------- |
-     *    | BLE_GAP_ADDR_PUBLIC(0x00)           | Public Address                                                                                                               |
-     *    | BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02)    | Resolvable Private Address. \n If the IRK of local device has not been registered in Resolving List, public address is used. |
+     *    |  macro                              |   description                                                                                                                                         |
+     *    |:------------------------------------|:----------------------------------------------------------------------------------------------------------------------------------------------------- |
+     *    | BLE_GAP_ADDR_PUBLIC(0x00)           | Public Address                                                                                                                                        |
+     *    | BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02)    | Resolvable Private Address. \n If the IRK (Identity Resolving Key) of local device has not been registered in Resolving List, public address is used. |
      */
     uint8_t own_bluetooth_address_type;
     uint8_t own_bluetooth_address[6];  ///< Own Bluetooth address.
-    uint8_t padding[3];                ///< padding
+    uint8_t padding[3];                ///< Reserved
 } ble_abs_legacy_advertising_parameter_t;
 
 /** st_ble_abs_extend_advertising_parameter_t is the parameters for extended advertising. */
@@ -325,38 +323,37 @@ typedef struct st_ble_abs_extend_advertising_parameter
     uint8_t * p_advertising_data;
 
     /**
-     *  @brief Advertising with the fast_advertising_interval parameter continues for \n
-     *  the period specified by the fast_advertising_period parameter. \n
-     *  Time(ms) = fast_advertising_interval * 0.625. \n
-     *  If the fast_advertising_period parameter is 0, this parameter is ignored. \n
+     *  @brief Advertising with the @ref fast_advertising_interval parameter continues for \n
+     *  the period specified by the @ref fast_advertising_period parameter. \n
+     *  Time(ms) = @ref fast_advertising_interval * 0.625. \n
+     *  If the @ref fast_advertising_period parameter is 0, this parameter is ignored. \n
      *  Valid range is 0x00000020 - 0x00FFFFFF.
      */
     uint32_t fast_advertising_interval;
 
     /**
-     *  @brief After the elapse of the fast_advertising_period, advertising with the slow_advertising_interval parameter \n
-     *  continues for the period specified by the slow_advertising_period parameter. \n
-     *  Time(ms) = fast_advertising_interval * 0.625. \n
-     *  If the fast_advertising_period parameter is 0, this parameter is ignored. \n
+     *  @brief After the elapse of the @ref fast_advertising_period, advertising with the @ref slow_advertising_interval parameter \n
+     *  continues for the period specified by the @ref slow_advertising_period parameter. \n
+     *  Time(ms) = @ref slow_advertising_interval * 0.625. \n
      *  Valid range is 0x00000020 - 0x00FFFFFF.
      */
     uint32_t slow_advertising_interval;
 
     /**
-     *  @brief The period which advertising with the fast_advertising_interval parameter continues for. \n
+     *  @brief The period which advertising with the @ref fast_advertising_interval parameter continues for. \n
      *  Time = duration * 10ms. \n
-     *  After the elapse of the fast_advertising_period, @ref BLE_GAP_EVENT_ADV_OFF event notifies that the advertising has stopped. \n
+     *  After the elapse of the @ref fast_advertising_period, @ref BLE_GAP_EVENT_ADV_OFF event notifies that the advertising has stopped. \n
      *  Valid range is 0x0000 - 0xFFFF. \n
-     *  If the fast_advertising_period parameter is 0x0000, the fast_advertising_interval parameter is ignored.
+     *  If the @ref fast_advertising_period parameter is 0x0000, the @ref fast_advertising_interval parameter is ignored.
      */
     uint16_t fast_advertising_period;
 
     /**
-     *  @brief The period which advertising with the slow_advertising_interval parameter continues for. \n
+     *  @brief The period which advertising with the @ref slow_advertising_interval parameter continues for. \n
      *  Time = duration * 10ms. \n
-     *  After the elapse of the slow_advertising_period, @ref BLE_GAP_EVENT_ADV_OFF event notifies that the advertising has stopped. \n
+     *  After the elapse of the @ref slow_advertising_period, @ref BLE_GAP_EVENT_ADV_OFF event notifies that the advertising has stopped. \n
      *  Valid range is 0x0000 - 0xFFFF. \n
-     *  If the slow_advertising_period parameter is 0x0000, the advertising continues.
+     *  If the @ref slow_advertising_period parameter is 0x0000, the advertising continues.
      */
     uint16_t slow_advertising_period;
 
@@ -392,10 +389,10 @@ typedef struct st_ble_abs_extend_advertising_parameter
 
     /**
      *  @brief  Own Bluetooth address type. Select one of the following. \n
-     *    |  macro                              |   description                                                                                                                |
-     *    |:------------------------------------|:---------------------------------------------------------------------------------------------------------------------------- |
-     *    | BLE_GAP_ADDR_PUBLIC(0x00)           | Public Address                                                                                                               |
-     *    | BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02)    | Resolvable Private Address. \n If the IRK of local device has not been registered in Resolving List, public address is used. |
+     *    |  macro                              |   description                                                                                                                                         |
+     *    |:------------------------------------|:----------------------------------------------------------------------------------------------------------------------------------------------------- |
+     *    | BLE_GAP_ADDR_PUBLIC(0x00)           | Public Address                                                                                                                                        |
+     *    | BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02)    | Resolvable Private Address. \n If the IRK (Identity Resolving Key) of local device has not been registered in Resolving List, public address is used. |
      */
     uint8_t own_bluetooth_address_type;
     uint8_t own_bluetooth_address[6];  ///< Own Bluetooth address.
@@ -420,7 +417,7 @@ typedef struct st_ble_abs_extend_advertising_parameter
      *    | BLE_GAP_ADV_PHY_CD(0x03)   | Use Coded PHY(S=8) as Secondary Advertising PHY. \n Coding scheme is configured by @ref R_BLE_VS_SetCodingScheme(). |
      */
     uint8_t secondary_advertising_phy;
-    uint8_t padding[3];                ///< padding
+    uint8_t padding[3];                ///< Reserved
 } ble_abs_extend_advertising_parameter_t;
 
 /** st_ble_abs_non_connectable_advertising_parameter_t is the parameters for non-connectable advertising. */
@@ -478,10 +475,10 @@ typedef struct st_ble_abs_non_connectable_advertising_parameter
 
     /**
      *  @brief  Own Bluetooth address type. Select one of the following. \n
-     *    |  macro                              |   description                                                                                                                |
-     *    |:------------------------------------|:---------------------------------------------------------------------------------------------------------------------------- |
-     *    | BLE_GAP_ADDR_PUBLIC(0x00)           | Public Address                                                                                                               |
-     *    | BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02)    | Resolvable Private Address. \n If the IRK of local device has not been registered in Resolving List, public address is used. |
+     *    |  macro                              |   description                                                                                                                                         |
+     *    |:------------------------------------|:----------------------------------------------------------------------------------------------------------------------------------------------------- |
+     *    | BLE_GAP_ADDR_PUBLIC(0x00)           | Public Address                                                                                                                                        |
+     *    | BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02)    | Resolvable Private Address. \n If the IRK (Identity Resolving Key) of local device has not been registered in Resolving List, public address is used. |
      */
     uint8_t own_bluetooth_address_type;
     uint8_t own_bluetooth_address[6];  ///< Own Bluetooth address.
@@ -506,7 +503,7 @@ typedef struct st_ble_abs_non_connectable_advertising_parameter
      *    | BLE_GAP_ADV_PHY_CD(0x03)   | Use Coded PHY(S=8) as Secondary Advertising PHY. \n Coding scheme is configured by @ref R_BLE_VS_SetCodingScheme(). |
      */
     uint8_t secondary_advertising_phy;
-    uint8_t padding[2];                ///< padding
+    uint8_t padding[2];                ///< Reserved
 } ble_abs_non_connectable_advertising_parameter_t;
 
 /** st_ble_abs_periodic_advertising_parameter_t is the parameters for periodic advertising. */
@@ -579,7 +576,7 @@ typedef struct st_ble_abs_scan_phy_parameter
     uint8_t scan_type;
 
     /**
-     *  @brief padding.
+     *  @brief Reserved.
      */
     uint8_t padding[3];
 } ble_abs_scan_phy_parameter_t;
@@ -637,12 +634,12 @@ typedef struct st_ble_abs_scan_parameter
     /**
      *  @brief Scan Filter Policy. Select one of the following.\n
      *    - Address type setting (Field [7:4])
-     *    |  macro                           |   description                                                                                           |
-     *    |:---------------------------------|:------------------------------------------------------------------------------------------------------- |
-     *    | BLE_GAP_ADDR_PUBLIC(0x00)        | Use Public Address.                                                                                     |
-     *    | BLE_GAP_ADDR_RAND(0x01)          | Use Random Address.                                                                                     |
-     *    | BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02) | If the IRK of local device has been registered in Resolving list, use RPA. If not, use Public Address.  |
-     *    | BLE_GAP_ADDR_RPA_ID_RANDOM(0x03) | If the IRK of local device has been registered in Resolving list, use RPA. If not, use Random Address.  |
+     *    |  macro                           |   description                                                                                                                    |
+     *    |:---------------------------------|:-------------------------------------------------------------------------------------------------------------------------------- |
+     *    | BLE_GAP_ADDR_PUBLIC(0x00)        | Use Public Address.                                                                                                              |
+     *    | BLE_GAP_ADDR_RAND(0x01)          | Use Random Address.                                                                                                              |
+     *    | BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02) | If the IRK (Identity Resolving Key) of local device has been registered in Resolving list, use RPA. If not, use Public Address.  |
+     *    | BLE_GAP_ADDR_RPA_ID_RANDOM(0x03) | If the IRK (Identity Resolving Key) of local device has been registered in Resolving list, use RPA. If not, use Random Address.  |
      *
      *    - White list setting (Field [3:0])
      *    |  macro                                            |   description                                                                                                                                                                                                                                                                                                                                                                                                               |
@@ -739,12 +736,12 @@ typedef struct st_ble_abs_connection_parameter
     /**
      *  @brief The filter field specifies whether the White List is used or not, when connecting with a remote device.\n
      *    - Address type setting (Field [7:4])
-     *    |  macro                           |   description                                                                                           |
-     *    |:---------------------------------|:------------------------------------------------------------------------------------------------------- |
-     *    | BLE_GAP_ADDR_PUBLIC(0x00)        | Use Public Address.                                                                                     |
-     *    | BLE_GAP_ADDR_RAND(0x01)          | Use Random Address.                                                                                     |
-     *    | BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02) | If the IRK of local device has been registered in Resolving list, use RPA. If not, use Public Address.  |
-     *    | BLE_GAP_ADDR_RPA_ID_RANDOM(0x03) | If the IRK of local device has been registered in Resolving list, use RPA. If not, use Random Address.  |
+     *    |  macro                           |   description                                                                                                                    |
+     *    |:---------------------------------|:-------------------------------------------------------------------------------------------------------------------------------- |
+     *    | BLE_GAP_ADDR_PUBLIC(0x00)        | Use Public Address.                                                                                                              |
+     *    | BLE_GAP_ADDR_RAND(0x01)          | Use Random Address.                                                                                                              |
+     *    | BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02) | If the IRK (Identity Resolving Key) of local device has been registered in Resolving list, use RPA. If not, use Public Address.  |
+     *    | BLE_GAP_ADDR_RPA_ID_RANDOM(0x03) | If the IRK (Identity Resolving Key) of local device has been registered in Resolving list, use RPA. If not, use Random Address.  |
      *
      *    - White list setting (Field [3:0])
      *    |  macro                           |   description                                                                                                                      |
@@ -788,16 +785,16 @@ typedef struct st_ble_abs_cfg
     ble_abs_gatt_client_callback_set_t * p_gatt_client_callback_list;       ///< GATT Client callback set.
     uint8_t gatt_client_callback_list_number;                               ///< The number of GATT Client callback functions.
     ble_abs_pairing_parameter_t * p_pairing_parameter;                      ///< Pairing parameters.
-#ifndef BLE_CFG_RYZ012_DEVICE
-    #ifndef BLE_CFG_DA14531_DEVICE
-    flash_instance_t const * p_flash_instance;                              ///< Pointer to flash instance.
-    timer_instance_t const * p_timer_instance;                              ///< Pointer to timer instance.
-    #endif
-#else
+
+#if defined(BLE_CFG_RYZ012_DEVICE) || defined(BLE_CFG_DA14xxx_DEVICE)
     const uart_instance_t         * p_uart_instance;                        ///< SCI UART instance
     const spi_instance_t          * p_spi_instance;                         ///< SPI instance
     const external_irq_instance_t * p_irq_instance;                         ///< IRQ instance
+#else
+    flash_instance_t const * p_flash_instance;                              ///< Pointer to flash instance.
+    timer_instance_t const * p_timer_instance;                              ///< Pointer to timer instance.
 #endif
+
     void (* p_callback)(ble_abs_callback_args_t * p_args);                  ///< Callback provided when a BLE ISR occurs.
     void const * p_context;                                                 ///< Placeholder for user data.  Passed to the user callback in ble_abs_callback_args_t.
     void const * p_extend;                                                  ///< Placeholder for user extension.
@@ -891,7 +888,7 @@ typedef struct st_ble_abs_api
      * @par Implemented as
      * - RM_BLE_ABS_SetLocalPrivacy()
      * @param[in]  p_ctrl       Pointer to control structure.
-     * @param[in]  p_lc_irk        Pointer to IRK to be registered in the resolving list.
+     * @param[in]  p_lc_irk        Pointer to IRK (Identity Resolving Key) to be registered in the resolving list.
      * @param[in]  privacy_mode        privacy_mode privacy mode.
      */
     fsp_err_t (* setLocalPrivacy)(ble_abs_ctrl_t * const p_ctrl, uint8_t const * const p_lc_irk, uint8_t privacy_mode);
@@ -918,7 +915,7 @@ typedef struct st_ble_abs_api
      * - RM_BLE_ABS_ImportKeyInformation()
      * @param[in]  p_ctrl       Pointer to control structure.
      * @param[in]  p_local_identity_address Pointer to local identiry address.
-     * @param[in]  uint8_t  p_local_irk Pointer to local IRK
+     * @param[in]  uint8_t  p_local_irk Pointer to local IRK (Identity Resolving Key)
      * @param[in]  uint8_t  p_local_csrk    Pointer to local CSRK
      */
     fsp_err_t (* importKeyInformation)(ble_abs_ctrl_t * const p_ctrl, ble_device_address_t * p_local_identity_address,
@@ -929,7 +926,7 @@ typedef struct st_ble_abs_api
      * - RM_BLE_ABS_ExportKeyInformation()
      * @param[in]   p_ctrl       Pointer to control structure.
      * @param[out]  p_local_identity_address Pointer to local identiry address.
-     * @param[out]  uint8_t  p_local_irk Pointer to local IRK
+     * @param[out]  uint8_t  p_local_irk Pointer to local IRK (Identity Resolving Key)
      * @param[out]  uint8_t  p_local_csrk    Pointer to local CSRK
      */
     fsp_err_t (* exportKeyInformation)(ble_abs_ctrl_t * const p_ctrl, ble_device_address_t * p_local_identity_address,
diff --git a/ra/fsp/inc/api/rm_ble_mesh_access_api.h b/ra/fsp/inc/api/rm_ble_mesh_access_api.h
index 006f111f1..1e9943be7 100644
--- a/ra/fsp/inc/api/rm_ble_mesh_access_api.h
+++ b/ra/fsp/inc/api/rm_ble_mesh_access_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_ble_mesh_api.h b/ra/fsp/inc/api/rm_ble_mesh_api.h
index 054f4c2eb..55107fb9a 100644
--- a/ra/fsp/inc/api/rm_ble_mesh_api.h
+++ b/ra/fsp/inc/api/rm_ble_mesh_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_ble_mesh_bearer_api.h b/ra/fsp/inc/api/rm_ble_mesh_bearer_api.h
index 72aa79462..313a63e5f 100644
--- a/ra/fsp/inc/api/rm_ble_mesh_bearer_api.h
+++ b/ra/fsp/inc/api/rm_ble_mesh_bearer_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_ble_mesh_config_client_api.h b/ra/fsp/inc/api/rm_ble_mesh_config_client_api.h
index b30a914cf..e225c93c0 100644
--- a/ra/fsp/inc/api/rm_ble_mesh_config_client_api.h
+++ b/ra/fsp/inc/api/rm_ble_mesh_config_client_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_ble_mesh_health_server_api.h b/ra/fsp/inc/api/rm_ble_mesh_health_server_api.h
index 7af540ec2..7015c7658 100644
--- a/ra/fsp/inc/api/rm_ble_mesh_health_server_api.h
+++ b/ra/fsp/inc/api/rm_ble_mesh_health_server_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_ble_mesh_lower_trans_api.h b/ra/fsp/inc/api/rm_ble_mesh_lower_trans_api.h
index 93b20dde7..b2339d894 100644
--- a/ra/fsp/inc/api/rm_ble_mesh_lower_trans_api.h
+++ b/ra/fsp/inc/api/rm_ble_mesh_lower_trans_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_ble_mesh_model_client_api.h b/ra/fsp/inc/api/rm_ble_mesh_model_client_api.h
index bb16e357b..eebd00085 100644
--- a/ra/fsp/inc/api/rm_ble_mesh_model_client_api.h
+++ b/ra/fsp/inc/api/rm_ble_mesh_model_client_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_ble_mesh_model_server_api.h b/ra/fsp/inc/api/rm_ble_mesh_model_server_api.h
index e69a54ef5..abf905b1b 100644
--- a/ra/fsp/inc/api/rm_ble_mesh_model_server_api.h
+++ b/ra/fsp/inc/api/rm_ble_mesh_model_server_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_ble_mesh_network_api.h b/ra/fsp/inc/api/rm_ble_mesh_network_api.h
index 393ec464c..b0a65a98d 100644
--- a/ra/fsp/inc/api/rm_ble_mesh_network_api.h
+++ b/ra/fsp/inc/api/rm_ble_mesh_network_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_ble_mesh_provision_api.h b/ra/fsp/inc/api/rm_ble_mesh_provision_api.h
index 502b535f7..704f1f03b 100644
--- a/ra/fsp/inc/api/rm_ble_mesh_provision_api.h
+++ b/ra/fsp/inc/api/rm_ble_mesh_provision_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_ble_mesh_scene_server_api.h b/ra/fsp/inc/api/rm_ble_mesh_scene_server_api.h
index a885a6a0c..8968d5d25 100644
--- a/ra/fsp/inc/api/rm_ble_mesh_scene_server_api.h
+++ b/ra/fsp/inc/api/rm_ble_mesh_scene_server_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_ble_mesh_upper_trans_api.h b/ra/fsp/inc/api/rm_ble_mesh_upper_trans_api.h
index bed80b7fc..70bdf7850 100644
--- a/ra/fsp/inc/api/rm_ble_mesh_upper_trans_api.h
+++ b/ra/fsp/inc/api/rm_ble_mesh_upper_trans_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_block_media_api.h b/ra/fsp/inc/api/rm_block_media_api.h
index 5bf593c95..82542dde4 100644
--- a/ra/fsp/inc/api/rm_block_media_api.h
+++ b/ra/fsp/inc/api/rm_block_media_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_comms_api.h b/ra/fsp/inc/api/rm_comms_api.h
index c67c87f21..c50108b19 100644
--- a/ra/fsp/inc/api/rm_comms_api.h
+++ b/ra/fsp/inc/api/rm_comms_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_filex_block_media_api.h b/ra/fsp/inc/api/rm_filex_block_media_api.h
index 0561d5eda..20add1e43 100644
--- a/ra/fsp/inc/api/rm_filex_block_media_api.h
+++ b/ra/fsp/inc/api/rm_filex_block_media_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_freertos_plus_fat_api.h b/ra/fsp/inc/api/rm_freertos_plus_fat_api.h
index bcb6efd4c..c7657504a 100644
--- a/ra/fsp/inc/api/rm_freertos_plus_fat_api.h
+++ b/ra/fsp/inc/api/rm_freertos_plus_fat_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_fsxxxx_api.h b/ra/fsp/inc/api/rm_fsxxxx_api.h
index c3df078ec..e2e957a00 100644
--- a/ra/fsp/inc/api/rm_fsxxxx_api.h
+++ b/ra/fsp/inc/api/rm_fsxxxx_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_hs300x_api.h b/ra/fsp/inc/api/rm_hs300x_api.h
index fc5d50fcd..027fc8721 100644
--- a/ra/fsp/inc/api/rm_hs300x_api.h
+++ b/ra/fsp/inc/api/rm_hs300x_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_hs400x_api.h b/ra/fsp/inc/api/rm_hs400x_api.h
index 4024a8bc7..c7d67a5b3 100644
--- a/ra/fsp/inc/api/rm_hs400x_api.h
+++ b/ra/fsp/inc/api/rm_hs400x_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_littlefs_api.h b/ra/fsp/inc/api/rm_littlefs_api.h
index 97beef83c..ea4696a95 100644
--- a/ra/fsp/inc/api/rm_littlefs_api.h
+++ b/ra/fsp/inc/api/rm_littlefs_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_mesh_bearer_platform_api.h b/ra/fsp/inc/api/rm_mesh_bearer_platform_api.h
index 7ba299052..e285fef2a 100644
--- a/ra/fsp/inc/api/rm_mesh_bearer_platform_api.h
+++ b/ra/fsp/inc/api/rm_mesh_bearer_platform_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_motor_120_control_api.h b/ra/fsp/inc/api/rm_motor_120_control_api.h
index a2abc35c8..c9a55d067 100644
--- a/ra/fsp/inc/api/rm_motor_120_control_api.h
+++ b/ra/fsp/inc/api/rm_motor_120_control_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_motor_120_driver_api.h b/ra/fsp/inc/api/rm_motor_120_driver_api.h
index ac881909a..070ce73c4 100644
--- a/ra/fsp/inc/api/rm_motor_120_driver_api.h
+++ b/ra/fsp/inc/api/rm_motor_120_driver_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_motor_angle_api.h b/ra/fsp/inc/api/rm_motor_angle_api.h
index 9c420b86e..216318932 100644
--- a/ra/fsp/inc/api/rm_motor_angle_api.h
+++ b/ra/fsp/inc/api/rm_motor_angle_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_motor_api.h b/ra/fsp/inc/api/rm_motor_api.h
index 3157b3ee0..23716b3a3 100644
--- a/ra/fsp/inc/api/rm_motor_api.h
+++ b/ra/fsp/inc/api/rm_motor_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -96,6 +96,14 @@ typedef enum  e_motor_wait_stop_flag
     MOTOR_WAIT_STOP_FLAG_SET   = 1,    ///< Wait stop flag set
 } motor_wait_stop_flag_t;
 
+/** Function select */
+typedef enum e_motor_function_select
+{
+    MOTOR_FUNCTION_SELECT_NONE             = 0, ///< No function selected
+    MOTOR_FUNCTION_SELECT_INERTIA_ESTIMATE = 1, ///< Inertia estimation
+    MOTOR_FUNCTION_SELECT_RETURN_ORIGIN    = 2, ///< Return origin position
+} motor_function_select_t;
+
 /** callback function parameter data */
 typedef struct st_rm_motor_callback_args
 {
@@ -275,6 +283,19 @@ typedef struct st_motor_api
      * @param[out] p_error      Pointer to get occured error
      */
     fsp_err_t (* errorCheck)(motor_ctrl_t * const p_ctrl, uint16_t * const p_error);
+
+    /** FunctionSelect.
+     * @par Implemented as
+     * - @ref RM_MOTOR_ENCODER_FunctionSelect()
+     * - @ref RM_MOTOR_INDUCTION_FunctionSelect()
+     * - @ref RM_MOTOR_SENSORLESS_FunctionSelect()
+     * - @ref RM_MOTOR_HALL_FunctionSelect()
+     * - @ref RM_MOTOR_120_DEGREE_FunctionSelect()
+     *
+     * @param[in]  p_ctrl              Pointer to control structure.
+     * @param[in]  function            Selected function
+     */
+    fsp_err_t (* functionSelect)(motor_ctrl_t * const p_ctrl, motor_function_select_t const function);
 } motor_api_t;
 
 /** This structure encompasses everything that is needed to use an instance of this interface. */
diff --git a/ra/fsp/inc/api/rm_motor_current_api.h b/ra/fsp/inc/api/rm_motor_current_api.h
index 6bf795b18..5f0fa5fd7 100644
--- a/ra/fsp/inc/api/rm_motor_current_api.h
+++ b/ra/fsp/inc/api/rm_motor_current_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_motor_driver_api.h b/ra/fsp/inc/api/rm_motor_driver_api.h
index d00a4d403..46b2ed4d9 100644
--- a/ra/fsp/inc/api/rm_motor_driver_api.h
+++ b/ra/fsp/inc/api/rm_motor_driver_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_motor_inertia_estimate_api.h b/ra/fsp/inc/api/rm_motor_inertia_estimate_api.h
new file mode 100644
index 000000000..02537e822
--- /dev/null
+++ b/ra/fsp/inc/api/rm_motor_inertia_estimate_api.h
@@ -0,0 +1,202 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup RENESAS_INTERFACES
+ * @defgroup MOTOR_INERTIA_ESTIMATE_API Motor Inertia Estimate Interface
+ * @brief Interface for Motor inertia estimate functions.
+ *
+ * @section MOTOR_INERTIA_ESTIMATE_API_Summary Summary
+ * The Motor interface provides Motor inertia estimate functionality.
+ *
+ * Implemented by:
+ * - @ref MOTOR_INERTIA_ESTIMATE
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef RM_MOTOR_INERTIA_ESTIMATE_API_H
+#define RM_MOTOR_INERTIA_ESTIMATE_API_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Register definitions, common services and error codes. */
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/* Internal mode */
+typedef enum e_motor_inertia_estimate_mode
+{
+    MOTOR_INERTIA_ESTIMATE_MODE_START = 0,
+    MOTOR_INERTIA_ESTIMATE_MODE_WAIT,
+    MOTOR_INERTIA_ESTIMATE_MODE_FORWARD,
+    MOTOR_INERTIA_ESTIMATE_MODE_REVERSE,
+    MOTOR_INERTIA_ESTIMATE_MODE_CALCULATE,
+    MOTOR_INERTIA_ESTIMATE_MODE_FINISH,
+    MOTOR_INERTIA_ESTIMATE_MODE_ERROR,
+} motor_inertia_estimate_mode_t;
+
+/** Interface data structure */
+typedef struct st_motor_inertia_estimate_info
+{
+    int16_t s2_position_reference_degree; ///< Position reference [degree]
+    motor_inertia_estimate_mode_t mode;   ///< Internal mode of inertia estimation
+    float f_estimated_inertia;            ///< Estimated inertia data
+} motor_inertia_estimate_info_t;
+
+typedef struct st_motor_inertia_estimate_set_data
+{
+    float   f_iq;                      ///< q-axis current data
+    float   f_speed_radian_control;    ///< Speed information
+    int16_t s2_position_degree;        ///< Rotor position [degree]
+    uint8_t u1_position_state;         ///< State of position control (0:STEADY 1:TRANSITION)
+} motor_inertia_estimate_set_data_t;
+
+/** Motor inertia estimate block.  Allocate an instance specific control block to pass into the API calls.
+ * @par Implemented as
+ * - motor_inertia_estimate_instance_ctrl_t
+ */
+typedef void motor_inertia_estimate_ctrl_t;
+
+/** Configuration parameters. */
+typedef struct st_motor_inertia_estimate_cfg
+{
+    void const * p_context;
+    void const * p_extend;             ///< Placeholder for user extension.
+} motor_inertia_estimate_cfg_t;
+
+/** Functions implemented at the HAL layer will follow this API. */
+typedef struct st_motor_inertia_estimate_api
+{
+    /** Open driver.
+     * @par Implemented as
+     * - @ref RM_MOTOR_INERTIA_ESTIMATE_Open()
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  p_cfg        Pointer to configuration structure.
+     */
+    fsp_err_t (* open)(motor_inertia_estimate_ctrl_t * const p_ctrl, motor_inertia_estimate_cfg_t const * const p_cfg);
+
+    /** Close driver.
+     * @par Implemented as
+     * - @ref RM_MOTOR_INERTIA_ESTIMATE_Close()
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* close)(motor_inertia_estimate_ctrl_t * const p_ctrl);
+
+    /** Start the function.
+     * @par Implemented as
+     * - @ref RM_MOTOR_INERTIA_ESTIMATE_Start()
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* start)(motor_inertia_estimate_ctrl_t * const p_ctrl);
+
+    /** Stop( same as cancel ) the function.
+     * @par Implemented as
+     * - @ref RM_MOTOR_INERTIA_ESTIMATE_Stop()
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* stop)(motor_inertia_estimate_ctrl_t * const p_ctrl);
+
+    /** Reset the function. (recover from error state)
+     * @par Implemented as
+     * - @ref RM_MOTOR_INERTIA_ESTIMATE_Reset()
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* reset)(motor_inertia_estimate_ctrl_t * const p_ctrl);
+
+    /** Get information from the function (to set speed & position control)
+     * @par Implemented as
+     * - @ref RM_MOTOR_INERTIA_ESTIMATE_InfoGet()
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[out] p_info       Pointer to information
+     */
+    fsp_err_t (* infoGet)(motor_inertia_estimate_ctrl_t * const p_ctrl, motor_inertia_estimate_info_t * const p_info);
+
+    /** Set the data to the function (from speed, position and current control)
+     * @par Implemented as
+     * - @ref RM_MOTOR_INERTIA_ESTIMATE_DataSet()
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[out] p_set_data   Pointer to set the data
+     */
+    fsp_err_t (* dataSet)(motor_inertia_estimate_ctrl_t * const     p_ctrl,
+                          motor_inertia_estimate_set_data_t * const p_set_data);
+
+    /** Speed cyclic process of the function
+     * @par Implemented as
+     * - @ref RM_MOTOR_INERTIA_ESTIMATE_SpeedCyclic()
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* speedCyclic)(motor_inertia_estimate_ctrl_t * const p_ctrl);
+
+    /** Current cyclic process of the function
+     * @par Implemented as
+     * - @ref RM_MOTOR_INERTIA_ESTIMATE_CurrentCyclic()
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* currentCyclic)(motor_inertia_estimate_ctrl_t * const p_ctrl);
+
+    /** Update parameters for the function.
+     * @par Implemented as
+     * - @ref RM_MOTOR_INERTIA_ESTIMATE_ParameterUpdate()
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  p_cfg        Pointer to configuration structure include update parameters.
+     */
+    fsp_err_t (* parameterUpdate)(motor_inertia_estimate_ctrl_t * const p_ctrl,
+                                  motor_inertia_estimate_cfg_t const  * p_cfg);
+} motor_inertia_estimate_api_t;
+
+/** This structure encompasses everything that is needed to use an instance of this interface. */
+typedef struct st_motor_inertia_estimate_instance
+{
+    motor_inertia_estimate_ctrl_t      * p_ctrl; ///< Pointer to the control structure for this instance
+    motor_inertia_estimate_cfg_t const * p_cfg;  ///< Pointer to the configuration structure for this instance
+    motor_inertia_estimate_api_t const * p_api;  ///< Pointer to the API structure for this instance
+} motor_inertia_estimate_instance_t;
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup MOTOR_INERTIA_ESTIMATE_API)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif                                 /* RM_MOTOR_INERTIA_ESTIMATE_API_H */
diff --git a/ra/fsp/inc/api/rm_motor_position_api.h b/ra/fsp/inc/api/rm_motor_position_api.h
index 27522293c..89e603ce1 100644
--- a/ra/fsp/inc/api/rm_motor_position_api.h
+++ b/ra/fsp/inc/api/rm_motor_position_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -63,6 +63,13 @@ typedef enum  e_motor_position_ctrl_mode
     MOTOR_POSITION_CTRL_MODE_STEP,
 } motor_position_ctrl_mode_t;
 
+/** Position information */
+typedef struct e_motor_position_info
+{
+    uint8_t u1_state_position_profile; ///< Position control profile state
+    int16_t s2_position_degree;        ///< Position data [degree]
+} motor_position_info_t;
+
 /** Control block.  Allocate an instance specific control block to pass into the API calls.
  * @par Implemented as
  * - motor_position_ctrl_t
@@ -188,6 +195,15 @@ typedef struct st_motor_position_api
      */
     fsp_err_t (* speedReferenceFeedforwardGet)(motor_position_ctrl_t * const p_ctrl, float * const p_speed_ref);
 
+    /** Get Position information.
+     * @par Implemented as
+     * - @ref RM_MOTOR_POSITION_InfoGet()
+     *
+     * @param[in]  p_ctrl           Pointer to control structure.
+     * @param[out] p_info           Pointer to get information
+     */
+    fsp_err_t (* infoGet)(motor_position_ctrl_t * const p_ctrl, motor_position_info_t * const p_info);
+
     /** Update Parameters for the calculation in the Motor Position Module.
      * @par Implemented as
      * - @ref RM_MOTOR_POSITION_ParameterUpdate()
diff --git a/ra/fsp/inc/api/rm_motor_return_origin_api.h b/ra/fsp/inc/api/rm_motor_return_origin_api.h
new file mode 100644
index 000000000..e17960c5d
--- /dev/null
+++ b/ra/fsp/inc/api/rm_motor_return_origin_api.h
@@ -0,0 +1,201 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup RENESAS_INTERFACES
+ * @defgroup MOTOR_RETURN_ORIGIN_API Motor Return Origin Function Interface
+ * @brief Interface for Motor return origin functions.
+ *
+ * @section MOTOR_RETURN_ORIGIN_API_Summary Summary
+ * The Motor interface provides Motor return origin functionality.
+ *
+ * Implemented by:
+ * - @ref MOTOR_RETURN_ORIGIN
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef RM_MOTOR_RETURN_ORIGIN_API_H
+#define RM_MOTOR_RETURN_ORIGIN_API_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Register definitions, common services and error codes. */
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Selection type of return origin function */
+typedef enum  e_motor_return_origin_mode
+{
+    MOTOR_RETURN_ORIGIN_MODE_PUSH = 1, ///< Return origin position with pushing
+    MOTOR_RETURN_ORIGIN_MODE_SENSOR,   ///< Return origin position with origin sensor
+    MOTOR_RETURN_ORIGIN_MODE_2_SENSOR, ///< Return origin position with 2 sensors
+    MOTOR_RETURN_ORIGIN_MODE_3_SENSOR, ///< Return origin position with 3 sensors
+} motor_return_origin_mode_t;
+
+/* Internal state */
+typedef enum e_motor_return_origin_state
+{
+    MOTOR_RETURN_ORIGIN_STATE_NONE = 0,
+    MOTOR_RETURN_ORIGIN_STATE_START,
+    MOTOR_RETURN_ORIGIN_STATE_SEARCH_STOPPER,
+    MOTOR_RETURN_ORIGIN_STATE_REVERSE,
+    MOTOR_RETURN_ORIGIN_STATE_DECELERATE,
+    MOTOR_RETURN_ORIGIN_STATE_DONE,
+    MOTOR_RETURN_ORIGIN_STATE_ERROR,
+} motor_return_origin_state_t;
+
+/** Interface data structure */
+typedef struct st_motor_return_origin_info
+{
+    float f_position_reference_degree; ///< Position reference [degree]
+    motor_return_origin_state_t state; // < Function state
+    float f_result_angle;              ///< Result angle position
+} motor_return_origin_info_t;
+
+typedef struct st_motor_return_origin_set_data
+{
+    float f_iq;                        ///< q-axis current data
+    float f_position_degree;           ///< Rotor position [degree]
+} motor_return_origin_set_data_t;
+
+/** Motor return origin function block.  Allocate an instance specific control block to pass into the API calls.
+ * @par Implemented as
+ * - motor_return_origin_instance_ctrl_t
+ */
+typedef void motor_return_origin_ctrl_t;
+
+/** Configuration parameters. */
+typedef struct st_motor_return_origin_cfg
+{
+    motor_return_origin_mode_t mode;
+
+    void const * p_context;
+    void const * p_extend;             ///< Placeholder for user extension.
+} motor_return_origin_cfg_t;
+
+/** Functions implemented at the HAL layer will follow this API. */
+typedef struct st_motor_return_origin_api
+{
+    /** Open driver.
+     * @par Implemented as
+     * - @ref RM_MOTOR_RETURN_ORIGIN_Open()
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  p_cfg        Pointer to configuration structure.
+     */
+    fsp_err_t (* open)(motor_return_origin_ctrl_t * const p_ctrl, motor_return_origin_cfg_t const * const p_cfg);
+
+    /** Close driver.
+     * @par Implemented as
+     * - @ref RM_MOTOR_RETURN_ORIGIN_Close()
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* close)(motor_return_origin_ctrl_t * const p_ctrl);
+
+    /** Start the function.
+     * @par Implemented as
+     * - @ref RM_MOTOR_RETURN_ORIGIN_Start()
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* start)(motor_return_origin_ctrl_t * const p_ctrl);
+
+    /** Stop the function. (Cancel the function works.)
+     * @par Implemented as
+     * - @ref RM_MOTOR_RETURN_ORIGIN_Stop()
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* stop)(motor_return_origin_ctrl_t * const p_ctrl);
+
+    /** Reset the function. (Initialize the function.)
+     * @par Implemented as
+     * - @ref RM_MOTOR_RETURN_ORIGIN_Reset()
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* reset)(motor_return_origin_ctrl_t * const p_ctrl);
+
+    /** Get the function information.
+     * @par Implemented as
+     * - @ref RM_MOTOR_RETURN_ORIGIN_InfoGet()
+     *
+     * @param[in]  p_ctrl   Pointer to control structure.
+     * @param[out] p_info   Pointer to info
+     */
+    fsp_err_t (* infoGet)(motor_return_origin_ctrl_t * const p_ctrl, motor_return_origin_info_t * const p_info);
+
+    /** Set the data to the function
+     * @par Implemented as
+     * - @ref RM_MOTOR_RETURN_ORIGIN_DataSet()
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[out] p_set_data   Pointer to set the data
+     */
+    fsp_err_t (* dataSet)(motor_return_origin_ctrl_t * const p_ctrl, motor_return_origin_set_data_t * const p_set_data);
+
+    /** Speed cyclic process of the function
+     * @par Implemented as
+     * - @ref RM_MOTOR_RETURN_ORIGIN_SpeedCyclic()
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* speedCyclic)(motor_return_origin_ctrl_t * const p_ctrl);
+
+    /** Update parameters for the function.
+     * @par Implemented as
+     * - @ref RM_MOTOR_RETURN_ORIGIN_ParameterUpdate()
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  p_cfg        Pointer to configuration structure include update parameters.
+     */
+    fsp_err_t (* parameterUpdate)(motor_return_origin_ctrl_t * const p_ctrl, motor_return_origin_cfg_t const * p_cfg);
+} motor_return_origin_api_t;
+
+/** This structure encompasses everything that is needed to use an instance of this interface. */
+typedef struct st_motor_return_origin_instance
+{
+    motor_return_origin_ctrl_t      * p_ctrl; ///< Pointer to the control structure for this instance
+    motor_return_origin_cfg_t const * p_cfg;  ///< Pointer to the configuration structure for this instance
+    motor_return_origin_api_t const * p_api;  ///< Pointer to the API structure for this instance
+} motor_return_origin_instance_t;
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup MOTOR_RETURN_ORIGIN_API)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif                                 /* RM_MOTOR_RETURN_ORIGIN_API_H */
diff --git a/ra/fsp/inc/api/rm_motor_speed_api.h b/ra/fsp/inc/api/rm_motor_speed_api.h
index 71687af0c..65481603a 100644
--- a/ra/fsp/inc/api/rm_motor_speed_api.h
+++ b/ra/fsp/inc/api/rm_motor_speed_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_ob1203_api.h b/ra/fsp/inc/api/rm_ob1203_api.h
index df6da33ae..cf481ec5a 100644
--- a/ra/fsp/inc/api/rm_ob1203_api.h
+++ b/ra/fsp/inc/api/rm_ob1203_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_touch_api.h b/ra/fsp/inc/api/rm_touch_api.h
index 1344b7b2b..ca22efc0a 100644
--- a/ra/fsp/inc/api/rm_touch_api.h
+++ b/ra/fsp/inc/api/rm_touch_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_vee_api.h b/ra/fsp/inc/api/rm_vee_api.h
index ad0f828e1..5890677cf 100644
--- a/ra/fsp/inc/api/rm_vee_api.h
+++ b/ra/fsp/inc/api/rm_vee_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_wifi_api.h b/ra/fsp/inc/api/rm_wifi_api.h
index c91f338e5..f40b29d6c 100644
--- a/ra/fsp/inc/api/rm_wifi_api.h
+++ b/ra/fsp/inc/api/rm_wifi_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/api/rm_zmod4xxx_api.h b/ra/fsp/inc/api/rm_zmod4xxx_api.h
index 3fcf625d1..06de583a7 100644
--- a/ra/fsp/inc/api/rm_zmod4xxx_api.h
+++ b/ra/fsp/inc/api/rm_zmod4xxx_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/fsp_common_api.h b/ra/fsp/inc/fsp_common_api.h
index b9f468a0c..42a0133f9 100644
--- a/ra/fsp/inc/fsp_common_api.h
+++ b/ra/fsp/inc/fsp_common_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/fsp_features.h b/ra/fsp/inc/fsp_features.h
index 70ee51cd7..13aaec26e 100644
--- a/ra/fsp/inc/fsp_features.h
+++ b/ra/fsp/inc/fsp_features.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -121,6 +121,7 @@ typedef enum e_fsp_ip
     FSP_IP_TFU    = 74,                ///< Trigonometric Function Unit
     FSP_IP_IIRFA  = 75,                ///< IIR Filter Accelerator
     FSP_IP_CANFD  = 76,                ///< CAN-FD
+    FSP_IP_ULPT   = 77,                ///< Ultra Low Power Timer ULPT
 } fsp_ip_t;
 
 /** Signals that can be mapped to an interrupt. */
@@ -288,6 +289,9 @@ typedef enum e_fsp_signal
     FSP_SIGNAL_USB_RESUME,                        ///< USB RESUME
     FSP_SIGNAL_USB_USB_INT_RESUME,                ///< USB USB INT RESUME
     FSP_SIGNAL_WDT_UNDERFLOW = 0,                 ///< WDT UNDERFLOW
+    FSP_SIGNAL_ULPT_COMPARE_A = 0,                ///< ULPT COMPARE A
+    FSP_SIGNAL_ULPT_COMPARE_B,                    ///< ULPT COMPARE B
+    FSP_SIGNAL_ULPT_INT,                          ///< ULPT INT
 } fsp_signal_t;
 
 typedef void (* fsp_vector_t)(void);
diff --git a/ra/fsp/inc/fsp_version.h b/ra/fsp/inc/fsp_version.h
index 5b9bc2295..7e88ffa6d 100644
--- a/ra/fsp/inc/fsp_version.h
+++ b/ra/fsp/inc/fsp_version.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -45,7 +45,7 @@ extern "C" {
  #define FSP_VERSION_MAJOR (4U)
 
 /** FSP pack minor version. */
- #define FSP_VERSION_MINOR (2U)
+ #define FSP_VERSION_MINOR (3U)
 
 /** FSP pack patch version. */
  #define FSP_VERSION_PATCH (0U)
@@ -54,10 +54,10 @@ extern "C" {
  #define FSP_VERSION_BUILD           (0U)
 
 /** Public FSP version name. */
- #define FSP_VERSION_STRING          ("4.2.0")
+ #define FSP_VERSION_STRING          ("4.3.0")
 
 /** Unique FSP version ID. */
- #define FSP_VERSION_BUILD_STRING    ("Built with Renesas Advanced Flexible Software Package version 4.2.0")
+ #define FSP_VERSION_BUILD_STRING    ("Built with Renesas Advanced Flexible Software Package version 4.3.0")
 
 /**********************************************************************************************************************
  * Typedef definitions
diff --git a/ra/fsp/inc/instances/r_acmphs.h b/ra/fsp/inc/instances/r_acmphs.h
index 42a38c82e..7ce6633cb 100644
--- a/ra/fsp/inc/instances/r_acmphs.h
+++ b/ra/fsp/inc/instances/r_acmphs.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_acmplp.h b/ra/fsp/inc/instances/r_acmplp.h
index 08b143167..5b721cd62 100644
--- a/ra/fsp/inc/instances/r_acmplp.h
+++ b/ra/fsp/inc/instances/r_acmplp.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_adc.h b/ra/fsp/inc/instances/r_adc.h
index 82fc564d2..62b6e58b7 100644
--- a/ra/fsp/inc/instances/r_adc.h
+++ b/ra/fsp/inc/instances/r_adc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_adc_b.h b/ra/fsp/inc/instances/r_adc_b.h
index caae05a93..91d688929 100644
--- a/ra/fsp/inc/instances/r_adc_b.h
+++ b/ra/fsp/inc/instances/r_adc_b.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_agt.h b/ra/fsp/inc/instances/r_agt.h
index e55060d14..ce08879b8 100644
--- a/ra/fsp/inc/instances/r_agt.h
+++ b/ra/fsp/inc/instances/r_agt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -37,19 +37,17 @@ FSP_HEADER
 
 /* Leading zeroes removed to avoid coding standards violation. */
 
-/** Maximum number of clock counts in 16 bit timer. */
-#if BSP_FEATURE_AGT_HAS_AGTW
- #define AGT_MAX_CLOCK_COUNTS    (UINT32_MAX)
-#else
- #define AGT_MAX_CLOCK_COUNTS    (UINT16_MAX)
-#endif
+/** Maximum number of clock counts for standard AGT peripheral. */
+#define AGT_MAX_CLOCK_COUNTS_16BIT  (UINT16_MAX)
 
-/** Maximum period value allowed for AGT. */
-#if BSP_FEATURE_AGT_HAS_AGTW
- #define AGT_MAX_PERIOD          (UINT32_MAX)
-#else
- #define AGT_MAX_PERIOD          (UINT16_MAX + 1U)
-#endif
+/** Maximum number of clock counts for AGTW peripheral. */
+#define AGT_MAX_CLOCK_COUNTS_32BIT  (UINT32_MAX)
+
+/** Maximum period value allowed for standard AGT peripheral. */
+#define AGT_MAX_PERIOD_16BIT        (UINT16_MAX + 1U)
+
+/** Maximum period valud allowed for AGTW peripheral. */
+#define AGT_MAX_PERIOD_32BIT        (UINT32_MAX)
 
 /*******************************************************************************************************************//**
  * @addtogroup AGT
@@ -127,11 +125,7 @@ typedef struct st_agt_instance_ctrl
 {
     uint32_t            open;                     // Whether or not channel is open
     const timer_cfg_t * p_cfg;                    // Pointer to initial configurations
-#if BSP_FEATURE_AGT_HAS_AGTW
-    R_AGTW0_Type * p_reg;                         // Base register for this channel
-#else
-    R_AGT0_Type * p_reg;                          // Base register for this channel
-#endif
+    R_AGTX0_Type * p_reg;                         // Base register for this channel
     uint32_t period;                              // Current timer period (counts)
 
     void (* p_callback)(timer_callback_args_t *); // Pointer to callback that is called when a timer_event_t occurs.
diff --git a/ra/fsp/inc/instances/r_cac.h b/ra/fsp/inc/instances/r_cac.h
index a02c56d84..e1e80edf5 100644
--- a/ra/fsp/inc/instances/r_cac.h
+++ b/ra/fsp/inc/instances/r_cac.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_can.h b/ra/fsp/inc/instances/r_can.h
index 90f55b717..8edc90151 100644
--- a/ra/fsp/inc/instances/r_can.h
+++ b/ra/fsp/inc/instances/r_can.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_canfd.h b/ra/fsp/inc/instances/r_canfd.h
index f74402808..8f8d720aa 100644
--- a/ra/fsp/inc/instances/r_canfd.h
+++ b/ra/fsp/inc/instances/r_canfd.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_cec.h b/ra/fsp/inc/instances/r_cec.h
index 09e778760..7d0fad932 100644
--- a/ra/fsp/inc/instances/r_cec.h
+++ b/ra/fsp/inc/instances/r_cec.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_cgc.h b/ra/fsp/inc/instances/r_cgc.h
index 986f5bd48..0421aa2ac 100644
--- a/ra/fsp/inc/instances/r_cgc.h
+++ b/ra/fsp/inc/instances/r_cgc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_crc.h b/ra/fsp/inc/instances/r_crc.h
index d68a84bf3..870a63179 100644
--- a/ra/fsp/inc/instances/r_crc.h
+++ b/ra/fsp/inc/instances/r_crc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_ctsu.h b/ra/fsp/inc/instances/r_ctsu.h
index 6c5894d98..346a2066a 100644
--- a/ra/fsp/inc/instances/r_ctsu.h
+++ b/ra/fsp/inc/instances/r_ctsu.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -19,7 +19,7 @@
  **********************************************************************************************************************/
 
 /*******************************************************************************************************************//**
- * @addtogroup CTSU
+ * @addtogroup CTSU 
  * @{
  **********************************************************************************************************************/
 
@@ -36,6 +36,7 @@
 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
 FSP_HEADER
 
+
 /***********************************************************************************************************************
  * Macro definitions
  **********************************************************************************************************************/
@@ -148,6 +149,12 @@ typedef struct st_ctsu_self_buf
 } ctsu_self_buf_t;
 #endif
 
+typedef struct st_ctsu_data
+{
+    uint16_t decimal_point_data;
+    uint16_t int_data;
+} ctsu_data_t;
+
 /** Scan buffer data formats (Mutual) */
 #if (BSP_FEATURE_CTSU_VERSION == 2)
 typedef uint16_t ctsu_mutual_buf_t;
@@ -282,12 +289,12 @@ typedef struct st_ctsu_instance_ctrl
     ctsu_ctsuwr_t          * p_ctsuwr;           ///< CTSUWR write register value. g_ctsu_ctsuwr[] is set by Open API.
     ctsu_self_buf_t        * p_self_raw;         ///< Pointer to Self raw data. g_ctsu_self_raw[] is set by Open API.
     uint16_t               * p_self_corr;        ///< Pointer to Self correction data. g_ctsu_self_corr[] is set by Open API.
-    uint16_t               * p_self_data;        ///< Pointer to Self moving average data. g_ctsu_self_data[] is set by Open API.
+    ctsu_data_t            * p_self_data;        ///< Pointer to Self moving average data. g_ctsu_self_data[] is set by Open API.
     ctsu_mutual_buf_t      * p_mutual_raw;       ///< Pointer to Mutual raw data. g_ctsu_mutual_raw[] is set by Open API.
     uint16_t               * p_mutual_pri_corr;  ///< Pointer to Mutual primary correction data. g_ctsu_self_corr[] is set by Open API.
     uint16_t               * p_mutual_snd_corr;  ///< Pointer to Mutual secondary correction data. g_ctsu_self_corr[] is set by Open API.
-    uint16_t               * p_mutual_pri_data;  ///< Pointer to Mutual primary moving average data. g_ctsu_mutual_pri_data[] is set by Open API.
-    uint16_t               * p_mutual_snd_data;  ///< Pointer to Mutual secondary moving average data. g_ctsu_mutual_snd_data[] is set by Open API.
+    ctsu_data_t            * p_mutual_pri_data;  ///< Pointer to Mutual primary moving average data. g_ctsu_mutual_pri_data[] is set by Open API.
+    ctsu_data_t            * p_mutual_snd_data;  ///< Pointer to Mutual secondary moving average data. g_ctsu_mutual_snd_data[] is set by Open API.
     ctsu_correction_info_t * p_correction_info;  ///< Pointer to correction info
     ctsu_txvsel_t            txvsel;             ///< CTSU Transmission Power Supply Select
     ctsu_txvsel2_t           txvsel2;            ///< CTSU Transmission Power Supply Select 2 (CTSU2 Only)
diff --git a/ra/fsp/inc/instances/r_dac.h b/ra/fsp/inc/instances/r_dac.h
index 1defc8db8..adb41a655 100644
--- a/ra/fsp/inc/instances/r_dac.h
+++ b/ra/fsp/inc/instances/r_dac.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_dac8.h b/ra/fsp/inc/instances/r_dac8.h
index b07182b33..26e89ea17 100644
--- a/ra/fsp/inc/instances/r_dac8.h
+++ b/ra/fsp/inc/instances/r_dac8.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_dmac.h b/ra/fsp/inc/instances/r_dmac.h
index 9b436c1a6..b337bc0fd 100644
--- a/ra/fsp/inc/instances/r_dmac.h
+++ b/ra/fsp/inc/instances/r_dmac.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_doc.h b/ra/fsp/inc/instances/r_doc.h
index 4a8d5a190..8b49a6986 100644
--- a/ra/fsp/inc/instances/r_doc.h
+++ b/ra/fsp/inc/instances/r_doc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_dtc.h b/ra/fsp/inc/instances/r_dtc.h
index 84749411b..ed7e0315d 100644
--- a/ra/fsp/inc/instances/r_dtc.h
+++ b/ra/fsp/inc/instances/r_dtc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_elc.h b/ra/fsp/inc/instances/r_elc.h
index 093d51c65..59a35b457 100644
--- a/ra/fsp/inc/instances/r_elc.h
+++ b/ra/fsp/inc/instances/r_elc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_ether.h b/ra/fsp/inc/instances/r_ether.h
index 6ffb7d24a..b7c83159d 100644
--- a/ra/fsp/inc/instances/r_ether.h
+++ b/ra/fsp/inc/instances/r_ether.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_ether_phy.h b/ra/fsp/inc/instances/r_ether_phy.h
index 891d3fcb6..83c5903a0 100644
--- a/ra/fsp/inc/instances/r_ether_phy.h
+++ b/ra/fsp/inc/instances/r_ether_phy.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_flash_hp.h b/ra/fsp/inc/instances/r_flash_hp.h
index 46c638ede..f042ccaa8 100644
--- a/ra/fsp/inc/instances/r_flash_hp.h
+++ b/ra/fsp/inc/instances/r_flash_hp.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_flash_lp.h b/ra/fsp/inc/instances/r_flash_lp.h
index 78b682c3d..70a40b654 100644
--- a/ra/fsp/inc/instances/r_flash_lp.h
+++ b/ra/fsp/inc/instances/r_flash_lp.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_glcdc.h b/ra/fsp/inc/instances/r_glcdc.h
index 97679631c..fa5854ac0 100644
--- a/ra/fsp/inc/instances/r_glcdc.h
+++ b/ra/fsp/inc/instances/r_glcdc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_gpt.h b/ra/fsp/inc/instances/r_gpt.h
index b45564305..208ff3563 100644
--- a/ra/fsp/inc/instances/r_gpt.h
+++ b/ra/fsp/inc/instances/r_gpt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_gpt_three_phase.h b/ra/fsp/inc/instances/r_gpt_three_phase.h
index 7a7e6b771..d36df77fb 100644
--- a/ra/fsp/inc/instances/r_gpt_three_phase.h
+++ b/ra/fsp/inc/instances/r_gpt_three_phase.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_i3c.h b/ra/fsp/inc/instances/r_i3c.h
index bcf9f881a..f60f48798 100644
--- a/ra/fsp/inc/instances/r_i3c.h
+++ b/ra/fsp/inc/instances/r_i3c.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_icu.h b/ra/fsp/inc/instances/r_icu.h
index c265d895c..469edac07 100644
--- a/ra/fsp/inc/instances/r_icu.h
+++ b/ra/fsp/inc/instances/r_icu.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_iic_b_master.h b/ra/fsp/inc/instances/r_iic_b_master.h
index 03db66383..a42f0a3c0 100644
--- a/ra/fsp/inc/instances/r_iic_b_master.h
+++ b/ra/fsp/inc/instances/r_iic_b_master.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_iic_b_slave.h b/ra/fsp/inc/instances/r_iic_b_slave.h
index 89cc23171..e3b9ec424 100644
--- a/ra/fsp/inc/instances/r_iic_b_slave.h
+++ b/ra/fsp/inc/instances/r_iic_b_slave.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_iic_master.h b/ra/fsp/inc/instances/r_iic_master.h
index 012a39da9..f4523d240 100644
--- a/ra/fsp/inc/instances/r_iic_master.h
+++ b/ra/fsp/inc/instances/r_iic_master.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_iic_slave.h b/ra/fsp/inc/instances/r_iic_slave.h
index b160fb077..8803e8ee0 100644
--- a/ra/fsp/inc/instances/r_iic_slave.h
+++ b/ra/fsp/inc/instances/r_iic_slave.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_iirfa.h b/ra/fsp/inc/instances/r_iirfa.h
index 12719e6b5..47ab1ddd4 100644
--- a/ra/fsp/inc/instances/r_iirfa.h
+++ b/ra/fsp/inc/instances/r_iirfa.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_ioport.h b/ra/fsp/inc/instances/r_ioport.h
index 95e9cf7dd..b46cbf72b 100644
--- a/ra/fsp/inc/instances/r_ioport.h
+++ b/ra/fsp/inc/instances/r_ioport.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_iwdt.h b/ra/fsp/inc/instances/r_iwdt.h
index 5ea2a7255..b0e96b79a 100644
--- a/ra/fsp/inc/instances/r_iwdt.h
+++ b/ra/fsp/inc/instances/r_iwdt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_jpeg.h b/ra/fsp/inc/instances/r_jpeg.h
index 5f398b329..f229d1ab8 100644
--- a/ra/fsp/inc/instances/r_jpeg.h
+++ b/ra/fsp/inc/instances/r_jpeg.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_kint.h b/ra/fsp/inc/instances/r_kint.h
index 1f7d624b4..a81d98750 100644
--- a/ra/fsp/inc/instances/r_kint.h
+++ b/ra/fsp/inc/instances/r_kint.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_lpm.h b/ra/fsp/inc/instances/r_lpm.h
index 86b11b9a5..a158b8399 100644
--- a/ra/fsp/inc/instances/r_lpm.h
+++ b/ra/fsp/inc/instances/r_lpm.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_lvd.h b/ra/fsp/inc/instances/r_lvd.h
index 52826ba00..7a22ec708 100644
--- a/ra/fsp/inc/instances/r_lvd.h
+++ b/ra/fsp/inc/instances/r_lvd.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_opamp.h b/ra/fsp/inc/instances/r_opamp.h
index 823c84e1e..aac2a2e21 100644
--- a/ra/fsp/inc/instances/r_opamp.h
+++ b/ra/fsp/inc/instances/r_opamp.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_ospi.h b/ra/fsp/inc/instances/r_ospi.h
index 2126ab742..c6a7d596c 100644
--- a/ra/fsp/inc/instances/r_ospi.h
+++ b/ra/fsp/inc/instances/r_ospi.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_pdc.h b/ra/fsp/inc/instances/r_pdc.h
index 99bc51765..7fdf79532 100644
--- a/ra/fsp/inc/instances/r_pdc.h
+++ b/ra/fsp/inc/instances/r_pdc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_poeg.h b/ra/fsp/inc/instances/r_poeg.h
index 3aec2ea2e..616238fb0 100644
--- a/ra/fsp/inc/instances/r_poeg.h
+++ b/ra/fsp/inc/instances/r_poeg.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_ptp.h b/ra/fsp/inc/instances/r_ptp.h
index 31b557877..6c80ce1cf 100644
--- a/ra/fsp/inc/instances/r_ptp.h
+++ b/ra/fsp/inc/instances/r_ptp.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_qspi.h b/ra/fsp/inc/instances/r_qspi.h
index 7b67669f0..41cdc3bd6 100644
--- a/ra/fsp/inc/instances/r_qspi.h
+++ b/ra/fsp/inc/instances/r_qspi.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_rtc.h b/ra/fsp/inc/instances/r_rtc.h
index 7222c8d48..fd7a357b9 100644
--- a/ra/fsp/inc/instances/r_rtc.h
+++ b/ra/fsp/inc/instances/r_rtc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_sce_key_injection.h b/ra/fsp/inc/instances/r_sce_key_injection.h
index 53d5f58b9..e4d16d375 100644
--- a/ra/fsp/inc/instances/r_sce_key_injection.h
+++ b/ra/fsp/inc/instances/r_sce_key_injection.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -60,6 +60,12 @@ fsp_err_t R_SCE_AES128_InitialKeyWrap(const uint8_t * const         key_type,
                                       const uint8_t * const         encrypted_key,
                                       sce_aes_wrapped_key_t * const wrapped_key);
 
+fsp_err_t R_SCE_AES192_InitialKeyWrap(const uint8_t * const         key_type,
+                                      const uint8_t * const         wrapped_user_factory_programming_key,
+                                      const uint8_t * const         initial_vector,
+                                      const uint8_t * const         encrypted_key,
+                                      sce_aes_wrapped_key_t * const wrapped_key);
+
 fsp_err_t R_SCE_AES256_InitialKeyWrap(const uint8_t * const         key_type,
                                       const uint8_t * const         wrapped_user_factory_programming_key,
                                       const uint8_t * const         initial_vector,
@@ -193,6 +199,30 @@ fsp_err_t R_SCE_ECC_secp384r1_EncryptedPrivateKeyWrap(const uint8_t * const
                                                       const sce_key_update_key_t * const    key_update_key,
                                                       sce_ecc_private_wrapped_key_t * const wrapped_key);
 
+fsp_err_t R_SCE_ECC_brainpoolP256r1_InitialPublicKeyWrap(const uint8_t * const                key_type,
+                                                         const uint8_t * const                wrapped_user_factory_programming_key,
+                                                         const uint8_t * const                initial_vector,
+                                                         const uint8_t * const                encrypted_key,
+                                                         sce_ecc_public_wrapped_key_t * const wrapped_key);
+
+fsp_err_t R_SCE_ECC_brainpoolP256r1_InitialPrivateKeyWrap(const uint8_t * const                 key_type,
+                                                          const uint8_t * const                 wrapped_user_factory_programming_key,
+                                                          const uint8_t * const                 initial_vector,
+                                                          const uint8_t * const                 encrypted_key,
+                                                          sce_ecc_private_wrapped_key_t * const wrapped_key);
+
+fsp_err_t R_SCE_ECC_brainpoolP384r1_InitialPublicKeyWrap(const uint8_t * const                key_type,
+                                                         const uint8_t * const                wrapped_user_factory_programming_key,
+                                                         const uint8_t * const                initial_vector,
+                                                         const uint8_t * const                encrypted_key,
+                                                         sce_ecc_public_wrapped_key_t * const wrapped_key);
+
+fsp_err_t R_SCE_ECC_brainpoolP384r1_InitialPrivateKeyWrap(const uint8_t * const                 key_type,
+                                                          const uint8_t * const                 wrapped_user_factory_programming_key,
+                                                          const uint8_t * const                 initial_vector,
+                                                          const uint8_t * const                 encrypted_key,
+                                                          sce_ecc_private_wrapped_key_t * const wrapped_key);
+
 /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
 FSP_FOOTER
 
diff --git a/ra/fsp/inc/instances/r_sci_b_i2c.h b/ra/fsp/inc/instances/r_sci_b_i2c.h
index 8cdaf2903..749076820 100644
--- a/ra/fsp/inc/instances/r_sci_b_i2c.h
+++ b/ra/fsp/inc/instances/r_sci_b_i2c.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_sci_b_spi.h b/ra/fsp/inc/instances/r_sci_b_spi.h
index e5ffa5abc..e8e68d241 100644
--- a/ra/fsp/inc/instances/r_sci_b_spi.h
+++ b/ra/fsp/inc/instances/r_sci_b_spi.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_sci_b_uart.h b/ra/fsp/inc/instances/r_sci_b_uart.h
index 91a893df1..11529a431 100644
--- a/ra/fsp/inc/instances/r_sci_b_uart.h
+++ b/ra/fsp/inc/instances/r_sci_b_uart.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_sci_i2c.h b/ra/fsp/inc/instances/r_sci_i2c.h
index b1f4fe530..9ac6e2b4a 100644
--- a/ra/fsp/inc/instances/r_sci_i2c.h
+++ b/ra/fsp/inc/instances/r_sci_i2c.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_sci_spi.h b/ra/fsp/inc/instances/r_sci_spi.h
index 5ccdccaec..5cce512ee 100644
--- a/ra/fsp/inc/instances/r_sci_spi.h
+++ b/ra/fsp/inc/instances/r_sci_spi.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_sci_uart.h b/ra/fsp/inc/instances/r_sci_uart.h
index d83b397c5..1cbbeb7d7 100644
--- a/ra/fsp/inc/instances/r_sci_uart.h
+++ b/ra/fsp/inc/instances/r_sci_uart.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_sdadc.h b/ra/fsp/inc/instances/r_sdadc.h
index 929ae2e3b..da36a18ae 100644
--- a/ra/fsp/inc/instances/r_sdadc.h
+++ b/ra/fsp/inc/instances/r_sdadc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_sdhi.h b/ra/fsp/inc/instances/r_sdhi.h
index c38fb20c3..085156e1c 100644
--- a/ra/fsp/inc/instances/r_sdhi.h
+++ b/ra/fsp/inc/instances/r_sdhi.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_slcdc.h b/ra/fsp/inc/instances/r_slcdc.h
index e78adcaf5..f58c6d495 100644
--- a/ra/fsp/inc/instances/r_slcdc.h
+++ b/ra/fsp/inc/instances/r_slcdc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_spi.h b/ra/fsp/inc/instances/r_spi.h
index 076d03d0b..c5307293e 100644
--- a/ra/fsp/inc/instances/r_spi.h
+++ b/ra/fsp/inc/instances/r_spi.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_spi_b.h b/ra/fsp/inc/instances/r_spi_b.h
index 19536ef3c..e32dffd58 100644
--- a/ra/fsp/inc/instances/r_spi_b.h
+++ b/ra/fsp/inc/instances/r_spi_b.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_ssi.h b/ra/fsp/inc/instances/r_ssi.h
index 264e99de9..8aeef4461 100644
--- a/ra/fsp/inc/instances/r_ssi.h
+++ b/ra/fsp/inc/instances/r_ssi.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_ulpt.h b/ra/fsp/inc/instances/r_ulpt.h
new file mode 100644
index 000000000..9059578b0
--- /dev/null
+++ b/ra/fsp/inc/instances/r_ulpt.h
@@ -0,0 +1,193 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef R_ULPT_H
+#define R_ULPT_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#include "r_ulpt_cfg.h"
+#include "r_timer_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup ULPT
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Count source. */
+typedef enum e_ulpt_clock
+{
+    ULPT_CLOCK_LOCO     = 0x00U,       ///< LOCO count source, division by 1, 2, 4, 8, 16, 32, 64, 128.
+    ULPT_CLOCK_SUBCLOCK = 0x20U,       ///< Subclock count source, division by 1, 2, 4, 8, 16, 32, 64, 128.
+    ULPT_CLOCK_ULPTEVI  = 0x02U,       ///< Counts external events on ULPTEVI.
+} ulpt_clock_t;
+
+/** Counter mode for event enable. */
+typedef enum e_ulpt_enable_function
+{
+   // R_ULPT0_ULPTIOC_TIOGT0_Msk    0X00 0000 0=Always count, 1 count external events (Not to be mized with nonzero TEECTL)
+   // R_ULPT0_ULPTISR_RCCPSEL2_Msk  0000 0X00 0=count low level, 1 count high level, only valid when TIOGT0=1 (Not to be mized with nonzero TEECTL)
+   // R_ULPT0_ULPTMR3_TEECTL_Msk    00XX 0000
+    //0100 0000 Count external high,
+    //0100 0100 Count external low
+    ULPT_ENABLE_FUNCTION_IGNORED     = 0x00U, ///< Always count external events, ignore ULPTEE.
+    ULPT_ENABLE_FUNCTION_ENABLE_LOW  = 0x40U, ///< Event counting is enabled while ULPTEE is low (event counting only).
+    ULPT_ENABLE_FUNCTION_ENABLE_HIGH = 0x44U, ///< Event counting is enabled while ULPTEE is high (event counting only).
+    ULPT_ENABLE_FUNCTION_START       = 0x20U, ///< Counting is started after ULPTEE.
+    ULPT_ENABLE_FUNCTION_RESTART     = 0x30U, ///< Counting is restarted after ULPTEE.
+
+} ulpt_enable_function_t;
+
+/** Enable signal trigger edge for start and restart functions. */
+typedef enum e_ulpt_trigger_edge
+{
+    ULPT_TRIGGER_EDGE_RISING  = 0x00U, ///< Timer enable function occurs on the rising edge of ULPTEE.
+    ULPT_TRIGGER_EDGE_FALLING = 0x40U, ///< Timer enable function occurs on the falling edge of ULPTEE.
+    ULPT_TRIGGER_EDGE_BOTH    = 0x80U, ///< Timer enable function occurs on any edge of ULPTEE.
+} ulpt_trigger_edge_t;
+
+/** Event signal pin. */
+typedef enum e_ulpt_event_pin
+{
+    ULPT_EVENT_PIN_RISING  = 0x00U,    ///< Event count occurs on the rising edge.
+    ULPT_EVENT_PIN_FALLING = 0x02U,    ///< Event count occurs on the falling edge.
+    ULPT_EVENT_PIN_BOTH    = 0x08U,    ///< Event count occurs on both edges.
+} ulpt_event_pin_t;
+
+/** Output pins, used to select which duty cycle to update in R_ULPT_DutyCycleSet(). */
+typedef enum e_ulpt_output_pin
+{
+    ULPT_OUTPUT_PIN_ULPTOA = 0U,       ///< Compare match A output.
+    ULPT_OUTPUT_PIN_ULPTOB = 1U,       ///< Compare match B output.
+} ulpt_output_pin_t;
+
+/** ULPTO pulse output pin. */
+typedef enum e_ulpt_pulse_pin_cfg
+{
+    ULPT_PULSE_PIN_CFG_DISABLED = 0x00U, ///< Output pin disabled.
+    ULPT_PULSE_PIN_CFG_ENABLED_START_LEVEL_LOW  = 0x01U, ///< Output pin Enabled Start Low
+    ULPT_PULSE_PIN_CFG_ENABLED_START_LEVEL_HIGH  = 0x02U, ///< Output pin enabled Start Hig
+} ulpt_pulse_pin_cfg_t;
+
+/** ULPT match output pin. */
+typedef enum e_ulpt_match_pin_cfg
+{
+    ULPT_MATCH_PIN_CFG_DISABLED         = 0x00U, ///< Match output disabled.
+    ULPT_MATCH_PIN_CFG_START_LEVEL_LOW  = 0x03U, ///< Match output enabled, starts low.
+    ULPT_MATCH_PIN_CFG_START_LEVEL_HIGH = 0x07U, ///< Match output enabled, starts high.
+} ulpt_match_pin_cfg_t;
+
+/** Input filter, applied to ULPTEVI in event counter mode. The filter requires the signal to be at the same level for
+ *  3 successive reads at the specified filter frequency. */
+typedef enum e_ulpt_ulptevi_filter
+{
+    ULPT_ULPTEVI_FILTER_NONE         = 0x00U, ///< No filter
+    ULPT_ULPTEVI_FILTER_PCLKB        = 0x10U, ///< Filter at PCLKB
+    ULPT_ULPTEVI_FILTER_PCLKB_DIV_8  = 0x20U, ///< Filter at PCLKB / 8
+    ULPT_ULPTEVI_FILTER_PCLKB_DIV_32 = 0x30U, ///< Filter at PCLKB / 32
+} ulpt_ulptevi_filter_t;
+
+/** Channel control block. DO NOT INITIALIZE.  Initialization occurs when @ref timer_api_t::open is called. */
+typedef struct st_ulpt_instance_ctrl
+{
+    uint32_t            open;                     // Whether or not the channel is open.
+    const timer_cfg_t * p_cfg;                    // Pointer to initial configuration.
+    R_ULPT0_Type      * p_reg;                    // Base register for this channel.
+    uint32_t            period;                   // Current timer period (counts).
+
+    void (* p_callback)(timer_callback_args_t *); // Pointer to callback that is called when a timer_event_t occurs.
+    timer_callback_args_t * p_callback_memory;    // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory.
+    void const            * p_context;            // Pointer to context to be passed into callback function
+} ulpt_instance_ctrl_t;
+
+/** Optional ULPT extension data structure. */
+typedef struct st_ulpt_extended_cfg
+{
+    ulpt_clock_t count_source;               ///< ULPT channel clock source.
+
+    /* Input pin settings */
+    ulpt_ulptevi_filter_t  ulptevi_filter;   ///< Input filter for ULTPEVI.
+    ulpt_enable_function_t enable_function;  ///< Counter function when ULPTEE is valid.
+    ulpt_trigger_edge_t    trigger_edge;     ///< Enable trigger edge (start and restart functions only).
+    ulpt_event_pin_t       event_pin;        ///< Event pin (event counting only).
+
+    /* Output settings */
+    ulpt_pulse_pin_cfg_t ulpto;              ///< Pulse output pin.
+    union
+    {
+        uint8_t ulptoab_settings;            ///< Compare match output register.
+        struct
+        {
+            ulpt_match_pin_cfg_t ulptoa : 3; ///< Compare match A output pin.
+            uint8_t                     : 1;
+            ulpt_match_pin_cfg_t ulptob : 3; ///< Compare match B output pin.
+            uint8_t                     : 1;
+        } ulptoab_settings_b;
+    };
+} ulpt_extended_cfg_t;
+
+/**********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/** @cond INC_HEADER_DEFS_SEC */
+/** Filled in Interface API structure for this Instance. */
+extern const timer_api_t g_timer_on_ulpt;
+
+/** @endcond */
+
+fsp_err_t R_ULPT_Close(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_ULPT_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts);
+fsp_err_t R_ULPT_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin);
+fsp_err_t R_ULPT_Reset(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_ULPT_Start(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_ULPT_Enable(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_ULPT_Disable(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_ULPT_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info);
+fsp_err_t R_ULPT_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status);
+fsp_err_t R_ULPT_Stop(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_ULPT_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg);
+fsp_err_t R_ULPT_CallbackSet(timer_ctrl_t * const          p_api_ctrl,
+                             void (                      * p_callback)(timer_callback_args_t *),
+                             void const * const            p_context,
+                             timer_callback_args_t * const p_callback_memory);
+
+/*******************************************************************************************************************//**
+ * @} (end defgroup ULPT)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+
+FSP_FOOTER
+
+#endif                                 // R_ULPT_H
diff --git a/ra/fsp/inc/instances/r_usb_basic.h b/ra/fsp/inc/instances/r_usb_basic.h
index 503b6c79f..c8e867c8e 100644
--- a/ra/fsp/inc/instances/r_usb_basic.h
+++ b/ra/fsp/inc/instances/r_usb_basic.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_usb_hhid.h b/ra/fsp/inc/instances/r_usb_hhid.h
index 4c27f819d..e615080af 100644
--- a/ra/fsp/inc/instances/r_usb_hhid.h
+++ b/ra/fsp/inc/instances/r_usb_hhid.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_usb_hmsc.h b/ra/fsp/inc/instances/r_usb_hmsc.h
index a46657173..e00dab95c 100644
--- a/ra/fsp/inc/instances/r_usb_hmsc.h
+++ b/ra/fsp/inc/instances/r_usb_hmsc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/r_wdt.h b/ra/fsp/inc/instances/r_wdt.h
index de3eea737..fcbd565b2 100644
--- a/ra/fsp/inc/instances/r_wdt.h
+++ b/ra/fsp/inc/instances/r_wdt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_adpcm_decoder.h b/ra/fsp/inc/instances/rm_adpcm_decoder.h
index 1676b4f6b..a2ff59ce7 100644
--- a/ra/fsp/inc/instances/rm_adpcm_decoder.h
+++ b/ra/fsp/inc/instances/rm_adpcm_decoder.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_audio_playback_pwm.h b/ra/fsp/inc/instances/rm_audio_playback_pwm.h
index a1ed41d5e..469672594 100644
--- a/ra/fsp/inc/instances/rm_audio_playback_pwm.h
+++ b/ra/fsp/inc/instances/rm_audio_playback_pwm.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_ble_abs.h b/ra/fsp/inc/instances/rm_ble_abs.h
index 7f7c7a204..e77080d2e 100644
--- a/ra/fsp/inc/instances/rm_ble_abs.h
+++ b/ra/fsp/inc/instances/rm_ble_abs.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -29,9 +29,9 @@
 #include "bsp_api.h"
 #include "r_ble_cfg.h"
 
-#ifdef BLE_CFG_RYZ012_DEVICE
+#if defined (BLE_CFG_RYZ012_DEVICE)
  #include "rm_ble_abs_spp_cfg.h"
-#elif BLE_CFG_DA14531_DEVICE
+#elif defined (BLE_CFG_DA14xxx_DEVICE)
  #include "rm_ble_abs_gtl_cfg.h"
 #else
  #include "rm_ble_abs_cfg.h"
diff --git a/ra/fsp/inc/instances/rm_ble_mesh.h b/ra/fsp/inc/instances/rm_ble_mesh.h
index 55208dca0..3a8a734de 100644
--- a/ra/fsp/inc/instances/rm_ble_mesh.h
+++ b/ra/fsp/inc/instances/rm_ble_mesh.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_ble_mesh_access.h b/ra/fsp/inc/instances/rm_ble_mesh_access.h
index 6720e7d6d..5b97b3ae5 100644
--- a/ra/fsp/inc/instances/rm_ble_mesh_access.h
+++ b/ra/fsp/inc/instances/rm_ble_mesh_access.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_ble_mesh_bearer.h b/ra/fsp/inc/instances/rm_ble_mesh_bearer.h
index 84e06e72c..03c68814e 100644
--- a/ra/fsp/inc/instances/rm_ble_mesh_bearer.h
+++ b/ra/fsp/inc/instances/rm_ble_mesh_bearer.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_ble_mesh_lower_trans.h b/ra/fsp/inc/instances/rm_ble_mesh_lower_trans.h
index 24ad64c00..e66af8104 100644
--- a/ra/fsp/inc/instances/rm_ble_mesh_lower_trans.h
+++ b/ra/fsp/inc/instances/rm_ble_mesh_lower_trans.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_ble_mesh_network.h b/ra/fsp/inc/instances/rm_ble_mesh_network.h
index d6bfd0476..3ff69d5a0 100644
--- a/ra/fsp/inc/instances/rm_ble_mesh_network.h
+++ b/ra/fsp/inc/instances/rm_ble_mesh_network.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_ble_mesh_provision.h b/ra/fsp/inc/instances/rm_ble_mesh_provision.h
index 960bf6dda..74d858a8f 100644
--- a/ra/fsp/inc/instances/rm_ble_mesh_provision.h
+++ b/ra/fsp/inc/instances/rm_ble_mesh_provision.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_ble_mesh_upper_trans.h b/ra/fsp/inc/instances/rm_ble_mesh_upper_trans.h
index e43b4b09d..8cbaafbe4 100644
--- a/ra/fsp/inc/instances/rm_ble_mesh_upper_trans.h
+++ b/ra/fsp/inc/instances/rm_ble_mesh_upper_trans.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_block_media_sdmmc.h b/ra/fsp/inc/instances/rm_block_media_sdmmc.h
index 40f5c3fae..897e463a8 100644
--- a/ra/fsp/inc/instances/rm_block_media_sdmmc.h
+++ b/ra/fsp/inc/instances/rm_block_media_sdmmc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_block_media_spi.h b/ra/fsp/inc/instances/rm_block_media_spi.h
index 9ccd8d3b0..064af17ff 100644
--- a/ra/fsp/inc/instances/rm_block_media_spi.h
+++ b/ra/fsp/inc/instances/rm_block_media_spi.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_block_media_usb.h b/ra/fsp/inc/instances/rm_block_media_usb.h
index d54670038..983547d99 100644
--- a/ra/fsp/inc/instances/rm_block_media_usb.h
+++ b/ra/fsp/inc/instances/rm_block_media_usb.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_cellular_comm_uart_aws.h b/ra/fsp/inc/instances/rm_cellular_comm_uart_aws.h
index 2865638a9..7c3734c1c 100644
--- a/ra/fsp/inc/instances/rm_cellular_comm_uart_aws.h
+++ b/ra/fsp/inc/instances/rm_cellular_comm_uart_aws.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_comms_i2c.h b/ra/fsp/inc/instances/rm_comms_i2c.h
index 8c30e2bf2..54f914863 100644
--- a/ra/fsp/inc/instances/rm_comms_i2c.h
+++ b/ra/fsp/inc/instances/rm_comms_i2c.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_filex_block_media.h b/ra/fsp/inc/instances/rm_filex_block_media.h
index 2ed9da887..e9a647640 100644
--- a/ra/fsp/inc/instances/rm_filex_block_media.h
+++ b/ra/fsp/inc/instances/rm_filex_block_media.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_filex_levelx_nor.h b/ra/fsp/inc/instances/rm_filex_levelx_nor.h
index ae6bd6778..1732b2cde 100644
--- a/ra/fsp/inc/instances/rm_filex_levelx_nor.h
+++ b/ra/fsp/inc/instances/rm_filex_levelx_nor.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_freertos_plus_fat.h b/ra/fsp/inc/instances/rm_freertos_plus_fat.h
index 36b24d5dd..d6cbba488 100644
--- a/ra/fsp/inc/instances/rm_freertos_plus_fat.h
+++ b/ra/fsp/inc/instances/rm_freertos_plus_fat.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_fs1015.h b/ra/fsp/inc/instances/rm_fs1015.h
index 045c0627c..d1131e1c3 100644
--- a/ra/fsp/inc/instances/rm_fs1015.h
+++ b/ra/fsp/inc/instances/rm_fs1015.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_fs2012.h b/ra/fsp/inc/instances/rm_fs2012.h
index b16122be8..a1b2fea45 100644
--- a/ra/fsp/inc/instances/rm_fs2012.h
+++ b/ra/fsp/inc/instances/rm_fs2012.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_fs3000.h b/ra/fsp/inc/instances/rm_fs3000.h
index 3e8d89262..faa0f0ce5 100644
--- a/ra/fsp/inc/instances/rm_fs3000.h
+++ b/ra/fsp/inc/instances/rm_fs3000.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_guix_port.h b/ra/fsp/inc/instances/rm_guix_port.h
index e4a6e7dea..de12d3272 100644
--- a/ra/fsp/inc/instances/rm_guix_port.h
+++ b/ra/fsp/inc/instances/rm_guix_port.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_hs300x.h b/ra/fsp/inc/instances/rm_hs300x.h
index 91fbe8fc8..a94efc5c1 100644
--- a/ra/fsp/inc/instances/rm_hs300x.h
+++ b/ra/fsp/inc/instances/rm_hs300x.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_hs400x.h b/ra/fsp/inc/instances/rm_hs400x.h
index 2cc4d50e6..32bea5b35 100644
--- a/ra/fsp/inc/instances/rm_hs400x.h
+++ b/ra/fsp/inc/instances/rm_hs400x.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_levelx_nor_spi.h b/ra/fsp/inc/instances/rm_levelx_nor_spi.h
index 6bf099337..76cf05290 100644
--- a/ra/fsp/inc/instances/rm_levelx_nor_spi.h
+++ b/ra/fsp/inc/instances/rm_levelx_nor_spi.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_littlefs_flash.h b/ra/fsp/inc/instances/rm_littlefs_flash.h
index 8f50a6e2b..e24351a43 100644
--- a/ra/fsp/inc/instances/rm_littlefs_flash.h
+++ b/ra/fsp/inc/instances/rm_littlefs_flash.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_bearer_platform.h b/ra/fsp/inc/instances/rm_mesh_bearer_platform.h
index 72297f312..8bac998c5 100644
--- a/ra/fsp/inc/instances/rm_mesh_bearer_platform.h
+++ b/ra/fsp/inc/instances/rm_mesh_bearer_platform.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_config_clt.h b/ra/fsp/inc/instances/rm_mesh_config_clt.h
index c52303263..388335b3f 100644
--- a/ra/fsp/inc/instances/rm_mesh_config_clt.h
+++ b/ra/fsp/inc/instances/rm_mesh_config_clt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_config_srv.h b/ra/fsp/inc/instances/rm_mesh_config_srv.h
index e1ab69d6c..e75d7822d 100644
--- a/ra/fsp/inc/instances/rm_mesh_config_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_config_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_generic_admin_prop_srv.h b/ra/fsp/inc/instances/rm_mesh_generic_admin_prop_srv.h
index 8c0d45dd5..f947dbcc3 100644
--- a/ra/fsp/inc/instances/rm_mesh_generic_admin_prop_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_generic_admin_prop_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_generic_battery_clt.h b/ra/fsp/inc/instances/rm_mesh_generic_battery_clt.h
index 4cbba2019..97329ba31 100644
--- a/ra/fsp/inc/instances/rm_mesh_generic_battery_clt.h
+++ b/ra/fsp/inc/instances/rm_mesh_generic_battery_clt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_generic_battery_srv.h b/ra/fsp/inc/instances/rm_mesh_generic_battery_srv.h
index 9d5a338cd..6edf55141 100644
--- a/ra/fsp/inc/instances/rm_mesh_generic_battery_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_generic_battery_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_generic_client_prop_srv.h b/ra/fsp/inc/instances/rm_mesh_generic_client_prop_srv.h
index f6a872fa3..5f53b6501 100644
--- a/ra/fsp/inc/instances/rm_mesh_generic_client_prop_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_generic_client_prop_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_generic_dtt_clt.h b/ra/fsp/inc/instances/rm_mesh_generic_dtt_clt.h
index d299637fa..c649b473f 100644
--- a/ra/fsp/inc/instances/rm_mesh_generic_dtt_clt.h
+++ b/ra/fsp/inc/instances/rm_mesh_generic_dtt_clt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_generic_dtt_srv.h b/ra/fsp/inc/instances/rm_mesh_generic_dtt_srv.h
index b9398167f..fb24b7863 100644
--- a/ra/fsp/inc/instances/rm_mesh_generic_dtt_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_generic_dtt_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_generic_level_clt.h b/ra/fsp/inc/instances/rm_mesh_generic_level_clt.h
index 875263cf0..fed745d39 100644
--- a/ra/fsp/inc/instances/rm_mesh_generic_level_clt.h
+++ b/ra/fsp/inc/instances/rm_mesh_generic_level_clt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_generic_level_srv.h b/ra/fsp/inc/instances/rm_mesh_generic_level_srv.h
index a444f6856..b8656e8c5 100644
--- a/ra/fsp/inc/instances/rm_mesh_generic_level_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_generic_level_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_generic_loc_clt.h b/ra/fsp/inc/instances/rm_mesh_generic_loc_clt.h
index 9eef0d783..7b838d821 100644
--- a/ra/fsp/inc/instances/rm_mesh_generic_loc_clt.h
+++ b/ra/fsp/inc/instances/rm_mesh_generic_loc_clt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_generic_loc_srv.h b/ra/fsp/inc/instances/rm_mesh_generic_loc_srv.h
index d69e45996..47477db21 100644
--- a/ra/fsp/inc/instances/rm_mesh_generic_loc_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_generic_loc_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_generic_mfr_prop_srv.h b/ra/fsp/inc/instances/rm_mesh_generic_mfr_prop_srv.h
index ee0ca6ae6..2a9086132 100644
--- a/ra/fsp/inc/instances/rm_mesh_generic_mfr_prop_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_generic_mfr_prop_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_generic_on_off_clt.h b/ra/fsp/inc/instances/rm_mesh_generic_on_off_clt.h
index 9d986eb49..1dc41c85c 100644
--- a/ra/fsp/inc/instances/rm_mesh_generic_on_off_clt.h
+++ b/ra/fsp/inc/instances/rm_mesh_generic_on_off_clt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_generic_on_off_srv.h b/ra/fsp/inc/instances/rm_mesh_generic_on_off_srv.h
index 7b44807c9..5d3b6f16d 100644
--- a/ra/fsp/inc/instances/rm_mesh_generic_on_off_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_generic_on_off_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_generic_pl_clt.h b/ra/fsp/inc/instances/rm_mesh_generic_pl_clt.h
index 9e1adcb96..be31023dc 100644
--- a/ra/fsp/inc/instances/rm_mesh_generic_pl_clt.h
+++ b/ra/fsp/inc/instances/rm_mesh_generic_pl_clt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_generic_pl_srv.h b/ra/fsp/inc/instances/rm_mesh_generic_pl_srv.h
index edb12e6d1..15691602d 100644
--- a/ra/fsp/inc/instances/rm_mesh_generic_pl_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_generic_pl_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_generic_poo_clt.h b/ra/fsp/inc/instances/rm_mesh_generic_poo_clt.h
index 7622d2854..19ce079d2 100644
--- a/ra/fsp/inc/instances/rm_mesh_generic_poo_clt.h
+++ b/ra/fsp/inc/instances/rm_mesh_generic_poo_clt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_generic_poo_srv.h b/ra/fsp/inc/instances/rm_mesh_generic_poo_srv.h
index 6452f58de..431f60af4 100644
--- a/ra/fsp/inc/instances/rm_mesh_generic_poo_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_generic_poo_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_generic_prop_clt.h b/ra/fsp/inc/instances/rm_mesh_generic_prop_clt.h
index 4869c7501..b43928ff2 100644
--- a/ra/fsp/inc/instances/rm_mesh_generic_prop_clt.h
+++ b/ra/fsp/inc/instances/rm_mesh_generic_prop_clt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_generic_user_prop_srv.h b/ra/fsp/inc/instances/rm_mesh_generic_user_prop_srv.h
index c8e6d1111..2813e218d 100644
--- a/ra/fsp/inc/instances/rm_mesh_generic_user_prop_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_generic_user_prop_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_health_clt.h b/ra/fsp/inc/instances/rm_mesh_health_clt.h
index 85b562559..7d6cb2df1 100644
--- a/ra/fsp/inc/instances/rm_mesh_health_clt.h
+++ b/ra/fsp/inc/instances/rm_mesh_health_clt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_health_srv.h b/ra/fsp/inc/instances/rm_mesh_health_srv.h
index 22918f8ff..30703b775 100644
--- a/ra/fsp/inc/instances/rm_mesh_health_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_health_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_light_ctl_clt.h b/ra/fsp/inc/instances/rm_mesh_light_ctl_clt.h
index 0ef1e356f..24ddaf446 100644
--- a/ra/fsp/inc/instances/rm_mesh_light_ctl_clt.h
+++ b/ra/fsp/inc/instances/rm_mesh_light_ctl_clt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_light_ctl_srv.h b/ra/fsp/inc/instances/rm_mesh_light_ctl_srv.h
index e6437433d..ef3f121a8 100644
--- a/ra/fsp/inc/instances/rm_mesh_light_ctl_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_light_ctl_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_light_hsl_clt.h b/ra/fsp/inc/instances/rm_mesh_light_hsl_clt.h
index eed3b59e4..a2fdfdcf4 100644
--- a/ra/fsp/inc/instances/rm_mesh_light_hsl_clt.h
+++ b/ra/fsp/inc/instances/rm_mesh_light_hsl_clt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_light_hsl_srv.h b/ra/fsp/inc/instances/rm_mesh_light_hsl_srv.h
index 35eba506c..a566ee0fb 100644
--- a/ra/fsp/inc/instances/rm_mesh_light_hsl_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_light_hsl_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_light_lc_clt.h b/ra/fsp/inc/instances/rm_mesh_light_lc_clt.h
index 556a80d73..39bb04c28 100644
--- a/ra/fsp/inc/instances/rm_mesh_light_lc_clt.h
+++ b/ra/fsp/inc/instances/rm_mesh_light_lc_clt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_light_lc_srv.h b/ra/fsp/inc/instances/rm_mesh_light_lc_srv.h
index dc2fb46a7..333a8a820 100644
--- a/ra/fsp/inc/instances/rm_mesh_light_lc_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_light_lc_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_light_lightness_clt.h b/ra/fsp/inc/instances/rm_mesh_light_lightness_clt.h
index 072c50b1c..210055c58 100644
--- a/ra/fsp/inc/instances/rm_mesh_light_lightness_clt.h
+++ b/ra/fsp/inc/instances/rm_mesh_light_lightness_clt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_light_lightness_srv.h b/ra/fsp/inc/instances/rm_mesh_light_lightness_srv.h
index 2df50c75c..630d84d50 100644
--- a/ra/fsp/inc/instances/rm_mesh_light_lightness_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_light_lightness_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_light_xyl_clt.h b/ra/fsp/inc/instances/rm_mesh_light_xyl_clt.h
index e5ee9cbab..96e4042e5 100644
--- a/ra/fsp/inc/instances/rm_mesh_light_xyl_clt.h
+++ b/ra/fsp/inc/instances/rm_mesh_light_xyl_clt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_light_xyl_srv.h b/ra/fsp/inc/instances/rm_mesh_light_xyl_srv.h
index 16ad9cd40..3c63f4f44 100644
--- a/ra/fsp/inc/instances/rm_mesh_light_xyl_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_light_xyl_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_scene_clt.h b/ra/fsp/inc/instances/rm_mesh_scene_clt.h
index 15fb9730e..981c82ad7 100644
--- a/ra/fsp/inc/instances/rm_mesh_scene_clt.h
+++ b/ra/fsp/inc/instances/rm_mesh_scene_clt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_scene_srv.h b/ra/fsp/inc/instances/rm_mesh_scene_srv.h
index 7066d6a02..9cab1b1f5 100644
--- a/ra/fsp/inc/instances/rm_mesh_scene_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_scene_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_scheduler_clt.h b/ra/fsp/inc/instances/rm_mesh_scheduler_clt.h
index ed671f4f2..08cdd75d2 100644
--- a/ra/fsp/inc/instances/rm_mesh_scheduler_clt.h
+++ b/ra/fsp/inc/instances/rm_mesh_scheduler_clt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_scheduler_srv.h b/ra/fsp/inc/instances/rm_mesh_scheduler_srv.h
index 5ef1197bf..d730e66c8 100644
--- a/ra/fsp/inc/instances/rm_mesh_scheduler_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_scheduler_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_sensor_clt.h b/ra/fsp/inc/instances/rm_mesh_sensor_clt.h
index f4e4a296d..efe9daed8 100644
--- a/ra/fsp/inc/instances/rm_mesh_sensor_clt.h
+++ b/ra/fsp/inc/instances/rm_mesh_sensor_clt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_sensor_srv.h b/ra/fsp/inc/instances/rm_mesh_sensor_srv.h
index 900e29d0b..05549b858 100644
--- a/ra/fsp/inc/instances/rm_mesh_sensor_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_sensor_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_time_clt.h b/ra/fsp/inc/instances/rm_mesh_time_clt.h
index c47dbdfe6..3379eb90d 100644
--- a/ra/fsp/inc/instances/rm_mesh_time_clt.h
+++ b/ra/fsp/inc/instances/rm_mesh_time_clt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_mesh_time_srv.h b/ra/fsp/inc/instances/rm_mesh_time_srv.h
index 7c1f0f32e..fbe07f64e 100644
--- a/ra/fsp/inc/instances/rm_mesh_time_srv.h
+++ b/ra/fsp/inc/instances/rm_mesh_time_srv.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_motor_120_control_hall.h b/ra/fsp/inc/instances/rm_motor_120_control_hall.h
index a1f7dcd6a..6690e4b72 100644
--- a/ra/fsp/inc/instances/rm_motor_120_control_hall.h
+++ b/ra/fsp/inc/instances/rm_motor_120_control_hall.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -110,6 +110,8 @@ typedef struct st_motor_120_control_hall_instance_ctrl
 
     motor_120_control_cfg_t const * p_cfg;                     ///< Pointer of configuration structure
 
+    timer_direction_t timer_direction;                         ///< Hold timer direction
+
     external_irq_callback_args_t hall_interrupt_args;          ///< For call IRQ callbackSet function
     timer_callback_args_t        timer_args;                   ///< For call timer callbackSet function
 } motor_120_control_hall_instance_ctrl_t;
diff --git a/ra/fsp/inc/instances/rm_motor_120_control_sensorless.h b/ra/fsp/inc/instances/rm_motor_120_control_sensorless.h
index 7e66514ec..cf9db761e 100644
--- a/ra/fsp/inc/instances/rm_motor_120_control_sensorless.h
+++ b/ra/fsp/inc/instances/rm_motor_120_control_sensorless.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -136,6 +136,8 @@ typedef struct st_motor_120_control_sensorless_instance_ctrl
 
     motor_120_control_cfg_t const * p_cfg;                                  ///< Pointer of configuration structure
 
+    timer_direction_t timer_direction;                                      ///< Hold timer direction
+
     /* cyclic timer callback */
     timer_callback_args_t timer_args;                                       ///< For call timer callbackSet function
 } motor_120_control_sensorless_instance_ctrl_t;
diff --git a/ra/fsp/inc/instances/rm_motor_120_degree.h b/ra/fsp/inc/instances/rm_motor_120_degree.h
index 5289f97ab..6277727f3 100644
--- a/ra/fsp/inc/instances/rm_motor_120_degree.h
+++ b/ra/fsp/inc/instances/rm_motor_120_degree.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -78,7 +78,7 @@ typedef struct st_motor_120_degree_extended_cfg
 
     float f_overcurrent_limit;                                         ///< Over-current limit (A)
     float f_overvoltage_limit;                                         ///< Over-voltage limit (V)
-    float f_overspeed_limit;                                           ///< Over-speed limit (rad/s)
+    float f_overspeed_limit;                                           ///< Over-speed limit (rpm)
     float f_lowvoltage_limit;                                          ///< Low-voltage limit (V)
 } motor_120_degree_extended_cfg_t;
 
@@ -140,6 +140,8 @@ fsp_err_t RM_MOTOR_120_DEGREE_PositionSet(motor_ctrl_t * const
 
 fsp_err_t RM_MOTOR_120_DEGREE_AngleGet(motor_ctrl_t * const p_ctrl, float * const p_angle_rad);
 
+fsp_err_t RM_MOTOR_120_DEGREE_FunctionSelect(motor_ctrl_t * const p_ctrl, motor_function_select_t const function);
+
 extern void rm_motor_120_degree_120_control_callback(motor_120_control_callback_args_t * p_args);
 
 /*******************************************************************************************************************//**
diff --git a/ra/fsp/inc/instances/rm_motor_120_driver.h b/ra/fsp/inc/instances/rm_motor_120_driver.h
index 259da8d70..09dc482c7 100644
--- a/ra/fsp/inc/instances/rm_motor_120_driver.h
+++ b/ra/fsp/inc/instances/rm_motor_120_driver.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_motor_current.h b/ra/fsp/inc/instances/rm_motor_current.h
index 0354845e5..f1353969b 100644
--- a/ra/fsp/inc/instances/rm_motor_current.h
+++ b/ra/fsp/inc/instances/rm_motor_current.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_motor_driver.h b/ra/fsp/inc/instances/rm_motor_driver.h
index 70bb5dd8f..8adc2c2ac 100644
--- a/ra/fsp/inc/instances/rm_motor_driver.h
+++ b/ra/fsp/inc/instances/rm_motor_driver.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -87,6 +87,14 @@ typedef struct st_motor_driver_extended_cfg
 
     motor_driver_modulation_method_t modulation_method; ///< Modulation method
 
+    /* PWM output port */
+    bsp_io_port_pin_t port_up;                          ///< PWM output port UP
+    bsp_io_port_pin_t port_un;                          ///< PWM output port UN
+    bsp_io_port_pin_t port_vp;                          ///< PWM output port VP
+    bsp_io_port_pin_t port_vn;                          ///< PWM output port VN
+    bsp_io_port_pin_t port_wp;                          ///< PWM output port WP
+    bsp_io_port_pin_t port_wn;                          ///< PWM output port WN
+
     /* For 1shunt */
     float   f_ad_current_adjust;                        ///< Adjustment value for 1shunt A/D current
     int32_t s4_difference_minimum;                      ///< Minimum difference of PWM duty
@@ -128,6 +136,10 @@ typedef struct st_motor_driver_instance_ctrl
     motor_driver_phase_t min_phase;    ///< Minimum phase information to calculate 1shunt current
     motor_driver_phase_t mid_phase;    ///< Middle phase information to calculate 1shunt current
 
+    /* Port configuration */
+    uint32_t u4_gtioca_low_cfg;        ///< I/O port "Low" config for gtioca
+    uint32_t u4_gtiocb_low_cfg;        ///< I/O port "Low" config for gtioca
+
     motor_driver_modulation_t  st_modulation;
     motor_driver_cfg_t const * p_cfg;
 
diff --git a/ra/fsp/inc/instances/rm_motor_encoder.h b/ra/fsp/inc/instances/rm_motor_encoder.h
index 2a7178388..9288a2e37 100644
--- a/ra/fsp/inc/instances/rm_motor_encoder.h
+++ b/ra/fsp/inc/instances/rm_motor_encoder.h
@@ -13,6 +13,8 @@
 #include "rm_motor_api.h"
 #include "rm_motor_speed.h"
 #include "rm_motor_current.h"
+#include "rm_motor_inertia_estimate_api.h"
+#include "rm_motor_return_origin_api.h"
 
 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
 FSP_HEADER
@@ -50,27 +52,43 @@ typedef struct  rm_motor_encoder_statemachine
 
 typedef struct st_motor_encoder_extended_cfg
 {
-    float f_overcurrent_limit;         ///< Over-current limit [A]
-    float f_overvoltage_limit;         ///< Over-voltage limit [V]
-    float f_overspeed_limit;           ///< Over-speed limit [rad/s]
-    float f_lowvoltage_limit;          ///< Low-voltage limit [V]
+    float f_overcurrent_limit;                                                   ///< Over-current limit [A]
+    float f_overvoltage_limit;                                                   ///< Over-voltage limit [V]
+    float f_overspeed_limit;                                                     ///< Over-speed limit [rpm]
+    float f_lowvoltage_limit;                                                    ///< Low-voltage limit [V]
+
+    /* Optional lower module instance used at inertia estimate function. Set to NULL if unused. */
+    motor_inertia_estimate_instance_t const * p_motor_inertia_estimate_instance; ///< Inertia estimate instance
+
+    /* Optional lower module instance used at return origin function. Set to NULL if unused. */
+    motor_return_origin_instance_t const * p_motor_return_origin_instance;       ///< Return origin instance
 } motor_encoder_extended_cfg_t;
 
 typedef struct st_motor_encoder_instance_ctrl
 {
-    uint32_t open;                            ///< Used to determine if the channel is configured
+    uint32_t open;                                    ///< Used to determine if the channel is configured
 
-    uint16_t u2_error_info;                   ///< Happened error
+    uint16_t u2_error_info;                           ///< Happened error
 
-    motor_encoder_statemachine_t st_statem;   ///< Statemachine structure
+    motor_encoder_statemachine_t st_statem;           ///< Statemachine structure
 
     /* Speed control <=> Current control interface */
-    motor_speed_input_t    st_speed_input;    ///< Speed input data buffer
-    motor_speed_output_t   st_speed_output;   ///< Speed output data buffer
-    motor_current_input_t  st_current_input;  ///< Current input data buffer
-    motor_current_output_t st_current_output; ///< Current output data buffer
+    motor_speed_input_t    st_speed_input;            ///< Speed input data buffer
+    motor_speed_output_t   st_speed_output;           ///< Speed output data buffer
+    motor_current_input_t  st_current_input;          ///< Current input data buffer
+    motor_current_output_t st_current_output;         ///< Current output data buffer
+
+    motor_function_select_t e_function;               ///< Selected function
+
+    /* Support inertia estimate */
+    motor_inertia_estimate_info_t     st_ie_get_data; ///< Data buffer gotten from inertia estimation
+    motor_inertia_estimate_set_data_t st_ie_set_data; ///< Data buffer set to inertia estimation
+
+    /* Support return origin */
+    motor_return_origin_info_t     st_ro_info;        ///< Data buffer gotten from return origin
+    motor_return_origin_set_data_t st_ro_set_data;    ///< Data buffer set to return origin
 
-    motor_cfg_t const * p_cfg;                ///< Pointer of configuration structure
+    motor_cfg_t const * p_cfg;                        ///< Pointer of configuration structure
 } motor_encoder_instance_ctrl_t;
 
 /**********************************************************************************************************************
@@ -117,6 +135,16 @@ fsp_err_t RM_MOTOR_ENCODER_ErrorCheck(motor_ctrl_t * const p_ctrl, uint16_t * co
 
 fsp_err_t RM_MOTOR_ENCODER_WaitStopFlagGet(motor_ctrl_t * const p_ctrl, motor_wait_stop_flag_t * const p_flag);
 
+fsp_err_t RM_MOTOR_ENCODER_FunctionSelect(motor_ctrl_t * const p_ctrl, motor_function_select_t const function);
+
+fsp_err_t RM_MOTOR_ENCODER_InertiaEstimateStart(motor_ctrl_t * const p_ctrl);
+
+fsp_err_t RM_MOTOR_ENCODER_InertiaEstimateStop(motor_ctrl_t * const p_ctrl);
+
+fsp_err_t RM_MOTOR_ENCODER_ReturnOriginStart(motor_ctrl_t * const p_ctrl);
+
+fsp_err_t RM_MOTOR_ENCODER_ReturnOriginStop(motor_ctrl_t * const p_ctrl);
+
 /*******************************************************************************************************************//**
  * @} (end addtogroup MOTOR_ENCODER)
  **********************************************************************************************************************/
diff --git a/ra/fsp/inc/instances/rm_motor_estimate.h b/ra/fsp/inc/instances/rm_motor_estimate.h
index 34e682c62..f73feaeb0 100644
--- a/ra/fsp/inc/instances/rm_motor_estimate.h
+++ b/ra/fsp/inc/instances/rm_motor_estimate.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_motor_hall.h b/ra/fsp/inc/instances/rm_motor_hall.h
index a67a963dd..730ba6ad8 100644
--- a/ra/fsp/inc/instances/rm_motor_hall.h
+++ b/ra/fsp/inc/instances/rm_motor_hall.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -136,6 +136,8 @@ fsp_err_t RM_MOTOR_HALL_PositionSet(motor_ctrl_t * const p_ctrl, motor_speed_pos
 
 fsp_err_t RM_MOTOR_HALL_WaitStopFlagGet(motor_ctrl_t * const p_ctrl, motor_wait_stop_flag_t * const p_flag);
 
+fsp_err_t RM_MOTOR_HALL_FunctionSelect(motor_ctrl_t * const p_ctrl, motor_function_select_t const function);
+
 /*******************************************************************************************************************//**
  * @} (end addtogroup MOTOR_HALL)
  **********************************************************************************************************************/
diff --git a/ra/fsp/inc/instances/rm_motor_induction.h b/ra/fsp/inc/instances/rm_motor_induction.h
index 271a39cee..77d1e0408 100644
--- a/ra/fsp/inc/instances/rm_motor_induction.h
+++ b/ra/fsp/inc/instances/rm_motor_induction.h
@@ -13,6 +13,8 @@
 #include "rm_motor_api.h"
 #include "rm_motor_speed.h"
 #include "rm_motor_current.h"
+#include "rm_motor_inertia_estimate_api.h"
+#include "rm_motor_return_origin_api.h"
 
 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
 FSP_HEADER
@@ -50,27 +52,43 @@ typedef struct  rm_motor_induction_statemachine
 
 typedef struct st_motor_induction_extended_cfg
 {
-    float f_overcurrent_limit;         ///< Over-current limit [A]
-    float f_overvoltage_limit;         ///< Over-voltage limit [V]
-    float f_overspeed_limit;           ///< Over-speed limit [rpm]
-    float f_lowvoltage_limit;          ///< Low-voltage limit [V]
+    float f_overcurrent_limit;                                                   ///< Over-current limit [A]
+    float f_overvoltage_limit;                                                   ///< Over-voltage limit [V]
+    float f_overspeed_limit;                                                     ///< Over-speed limit [rpm]
+    float f_lowvoltage_limit;                                                    ///< Low-voltage limit [V]
+
+    /* Optional lower module instance used at inertia estimate function. Set to NULL if unused. */
+    motor_inertia_estimate_instance_t const * p_motor_inertia_estimate_instance; ///< Inertia estimate instance
+
+    /* Optional lower module instance used at return origin function. Set to NULL if unused. */
+    motor_return_origin_instance_t const * p_motor_return_origin_instance;       ///< Return origin instance
 } motor_induction_extended_cfg_t;
 
 typedef struct st_motor_induction_instance_ctrl
 {
-    uint32_t open;                            ///< Used to determine if the channel is configured
+    uint32_t open;                                    ///< Used to determine if the channel is configured
 
-    uint16_t u2_error_info;                   ///< Happened error
+    uint16_t u2_error_info;                           ///< Happened error
 
-    motor_induction_statemachine_t st_statem; ///< Statemachine structure
+    motor_induction_statemachine_t st_statem;         ///< Statemachine structure
 
     /* Speed control <=> Current control interface */
-    motor_speed_input_t    st_speed_input;    ///< Speed input data buffer
-    motor_speed_output_t   st_speed_output;   ///< Speed output data buffer
-    motor_current_input_t  st_current_input;  ///< Current input data buffer
-    motor_current_output_t st_current_output; ///< Current output data buffer
+    motor_speed_input_t    st_speed_input;            ///< Speed input data buffer
+    motor_speed_output_t   st_speed_output;           ///< Speed output data buffer
+    motor_current_input_t  st_current_input;          ///< Current input data buffer
+    motor_current_output_t st_current_output;         ///< Current output data buffer
+
+    motor_function_select_t e_function;               ///< Selected function
+
+    /* Support inertia estimate */
+    motor_inertia_estimate_info_t     st_ie_get_data; ///< Data buffer gotten from inertia estimation
+    motor_inertia_estimate_set_data_t st_ie_set_data; ///< Data buffer set to inertia estimation
+
+    /* Support return orign */
+    motor_return_origin_info_t     st_ro_info;        ///< Data buffer gotten from return origin
+    motor_return_origin_set_data_t st_ro_set_data;    ///< Data buffer set to return origin
 
-    motor_cfg_t const * p_cfg;                ///< Pointer of configuration structure
+    motor_cfg_t const * p_cfg;                        ///< Pointer of configuration structure
 } motor_induction_instance_ctrl_t;
 
 /**********************************************************************************************************************
@@ -117,6 +135,16 @@ fsp_err_t RM_MOTOR_INDUCTION_ErrorCheck(motor_ctrl_t * const p_ctrl, uint16_t *
 
 fsp_err_t RM_MOTOR_INDUCTION_WaitStopFlagGet(motor_ctrl_t * const p_ctrl, motor_wait_stop_flag_t * const p_flag);
 
+fsp_err_t RM_MOTOR_INDUCTION_FunctionSelect(motor_ctrl_t * const p_ctrl, motor_function_select_t const function);
+
+fsp_err_t RM_MOTOR_INDUCTION_InertiaEstimateStart(motor_ctrl_t * const p_ctrl);
+
+fsp_err_t RM_MOTOR_INDUCTION_InertiaEstimateStop(motor_ctrl_t * const p_ctrl);
+
+fsp_err_t RM_MOTOR_INDUCTION_ReturnOriginStart(motor_ctrl_t * const p_ctrl);
+
+fsp_err_t RM_MOTOR_INDUCTION_ReturnOriginStop(motor_ctrl_t * const p_ctrl);
+
 /*******************************************************************************************************************//**
  * @} (end addtogroup MOTOR_INDUCTION)
  **********************************************************************************************************************/
diff --git a/ra/fsp/inc/instances/rm_motor_inertia_estimate.h b/ra/fsp/inc/instances/rm_motor_inertia_estimate.h
new file mode 100644
index 000000000..513f4cc13
--- /dev/null
+++ b/ra/fsp/inc/instances/rm_motor_inertia_estimate.h
@@ -0,0 +1,186 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup MOTOR_INERTIA_ESTIMATE
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef RM_MOTOR_INERTIA_ESTIMATE_H
+#define RM_MOTOR_INERTIA_ESTIMATE_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#include "rm_motor_inertia_estimate_cfg.h"
+#include "rm_motor_inertia_estimate_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+typedef enum e_motor_inertia_estimate_start_flag
+{
+    MOTOR_INERTIA_ESTIMATE_START_FLAG_STOP  = 0,
+    MOTOR_INERTIA_ESTIMATE_START_FLAG_START = 1,
+} motor_inertia_estimate_start_flag_t;
+
+/* Measure period */
+typedef enum e_motor_inertia_estimate_period
+{
+    MOTOR_INERTIA_ESTIMATE_PERIOD_NO_MOVE = 0,
+    MOTOR_INERTIA_ESTIMATE_PERIOD_FORWARD_ACCELL,
+    MOTOR_INERTIA_ESTIMATE_PERIOD_FORWARD_DECELERATE,
+    MOTOR_INERTIA_ESTIMATE_PERIOD_REVERSE_ACCELL,
+    MOTOR_INERTIA_ESTIMATE_PERIOD_REVERSE_DECELERATE,
+    MOTOR_INERTIA_ESTIMATE_PERIOD_MEASURE_FINISH,
+} motor_inertia_estimate_period_t;
+
+/** Extended configurations for motor inertia estimate */
+typedef struct st_motor_inertia_estimate_extended_cfg
+{
+    int16_t  s2_move_degree;           ///< Moving position reference [degree]
+    uint16_t u2_J_max_speed_rpm;       ///< Maximum Speed [rpm]
+    float    f_accel_time;             ///< Acceleration time
+    float    f_rotor_inertia;          ///< Initialized rotor inertia value
+
+    float f_judge_low_threshold;       ///< Low threshold to judge speed
+    float f_judge_high_threshold;      ///< High threshold to judge speed
+    float f_change_mode_time;          ///< Timing value to change internal mode
+
+    float   f_current_ctrl_period;     ///< Period of current control [sec]
+    float   f_speed_ctrl_period;       ///< Period of speed control [sec]
+    uint8_t u1_motor_polepairs;        ///< Motor pole pairs
+    float   f_motor_m;                 ///< Motor magnet flux [Wb]
+    float   f_position_interval;       ///< Interval counts for reference position change
+} motor_inertia_estimate_extended_cfg_t;
+
+/** Inertia estimate instance control block */
+typedef struct st_motor_inertia_estimate_instance_ctrl
+{
+    uint32_t open;                                       ///< Used to determine if the module is configured
+
+    motor_inertia_estimate_start_flag_t start_flag;      ///< start/stop flag
+    motor_inertia_estimate_mode_t       mode;            ///< Internal mode
+    uint8_t u1_mode_count;                               ///< Use to manage internal mode
+    motor_inertia_estimate_period_t speed_period;        ///< Measure period
+    motor_inertia_estimate_period_t speed_period_buffer; ///< Buffer of measure period to be reffered by current cyclic
+
+    uint32_t u4_measure_count;                           ///< Counter for speed control cycle
+    uint32_t u4_wait_count;                              ///< Counter to wait change mode timing
+
+    uint8_t u1_position_move_mode;                       ///< Position move mode (TRIANGLE/TRAPEZOID)
+
+    int16_t s2_initial_position_degree;                  ///< Initial position
+    float   f_iq_ad;                                     ///< q-axis current [A]
+    float   f_summary_iq_ad;                             ///< Summary of q-axis current
+    float   f_position_mode_time;                        ///< Summary of speed control period to judge the timing
+    float   f_position_dt_time_sec;                      ///< Differencial time of move
+
+    int16_t s2_position_reference_degree;                ///< Position reference [degree]
+
+    float f_estimated_value;                             ///< Estimated inertia
+    float f_inertia_value1;                              ///< Buffer to calculate inertia 1
+    float f_inertia_value2;                              ///< Buffer to calculate inertia 2
+
+    float f_interval_time;                               ///< Interval time about position transition
+
+    /* Measured data to estimate inertia */
+    float f_inertia_speed_ctrl1;
+    float f_inertia_speed_ctrl2;
+    float f_inertia_speed_ctrl3;
+    float f_inertia_speed_ctrl4;
+    float f_inertia_speed_ctrl5;
+    float f_inertia_speed_ctrl6;
+    float f_inertia_speed_ctrl7;
+    float f_inertia_speed_ctrl8;
+
+    float f_inertia_integ_iq1;
+    float f_inertia_integ_iq2;
+    float f_inertia_integ_iq3;
+    float f_inertia_integ_iq4;
+
+    float f_inertia_integ_time1;
+    float f_inertia_integ_time2;
+    float f_inertia_integ_time3;
+    float f_inertia_integ_time4;
+
+    float f_inverse_motor_polepairs;                   ///< Inverse motor pole pairs (for calculation)
+
+    motor_inertia_estimate_set_data_t    receive_data; ///< Received data set from speed(position) and current
+    motor_inertia_estimate_cfg_t const * p_cfg;        ///< Pointer of configuration structure
+} motor_inertia_estimate_instance_ctrl_t;
+
+/**********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/** @cond INC_HEADER_DEFS_SEC */
+/** Filled in interface API structure for this instance. */
+extern const motor_inertia_estimate_api_t g_motor_inertia_estimate_on_motor_inertia_estimate;
+
+/** @endcond */
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Public Function Prototypes
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_INERTIA_ESTIMATE_Open(motor_inertia_estimate_ctrl_t * const      p_ctrl,
+                                         motor_inertia_estimate_cfg_t const * const p_cfg);
+
+fsp_err_t RM_MOTOR_INERTIA_ESTIMATE_Close(motor_inertia_estimate_ctrl_t * const p_ctrl);
+
+fsp_err_t RM_MOTOR_INERTIA_ESTIMATE_Start(motor_inertia_estimate_ctrl_t * const p_ctrl);
+
+fsp_err_t RM_MOTOR_INERTIA_ESTIMATE_Stop(motor_inertia_estimate_ctrl_t * const p_ctrl);
+
+fsp_err_t RM_MOTOR_INERTIA_ESTIMATE_Reset(motor_inertia_estimate_ctrl_t * const p_ctrl);
+
+fsp_err_t RM_MOTOR_INERTIA_ESTIMATE_InfoGet(motor_inertia_estimate_ctrl_t * const p_ctrl,
+                                            motor_inertia_estimate_info_t * const p_info);
+
+fsp_err_t RM_MOTOR_INERTIA_ESTIMATE_DataSet(motor_inertia_estimate_ctrl_t * const     p_ctrl,
+                                            motor_inertia_estimate_set_data_t * const p_set_data);
+
+fsp_err_t RM_MOTOR_INERTIA_ESTIMATE_SpeedCyclic(motor_inertia_estimate_ctrl_t * const p_ctrl);
+
+fsp_err_t RM_MOTOR_INERTIA_ESTIMATE_CurrentCyclic(motor_inertia_estimate_ctrl_t * const p_ctrl);
+
+fsp_err_t RM_MOTOR_INERTIA_ESTIMATE_ParameterUpdate(motor_inertia_estimate_ctrl_t * const      p_ctrl,
+                                                    motor_inertia_estimate_cfg_t const * const p_cfg);
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif                                 // RM_MOTOR_INERTIA_ESTIMATE_H
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup MOTOR_INERTIA_ESTIMATE)
+ **********************************************************************************************************************/
diff --git a/ra/fsp/inc/instances/rm_motor_position.h b/ra/fsp/inc/instances/rm_motor_position.h
index d7457c8c0..68ee4d534 100644
--- a/ra/fsp/inc/instances/rm_motor_position.h
+++ b/ra/fsp/inc/instances/rm_motor_position.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -255,6 +255,8 @@ fsp_err_t RM_MOTOR_POSITION_SpeedReferenceIpdControlGet(motor_position_ctrl_t *
 fsp_err_t RM_MOTOR_POSITION_SpeedReferenceFeedforwardGet(motor_position_ctrl_t * const p_ctrl,
                                                          float * const                 p_speed_ref);
 
+fsp_err_t RM_MOTOR_POSITION_InfoGet(motor_position_ctrl_t * const p_ctrl, motor_position_info_t * const p_info);
+
 fsp_err_t RM_MOTOR_POSITION_ParameterUpdate(motor_position_ctrl_t * const      p_ctrl,
                                             motor_position_cfg_t const * const p_cfg);
 
diff --git a/ra/fsp/inc/instances/rm_motor_return_origin.h b/ra/fsp/inc/instances/rm_motor_return_origin.h
new file mode 100644
index 000000000..9b241ca98
--- /dev/null
+++ b/ra/fsp/inc/instances/rm_motor_return_origin.h
@@ -0,0 +1,147 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup MOTOR_RETURN_ORIGIN
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef RM_MOTOR_RETURN_ORIGIN_H
+#define RM_MOTOR_RETURN_ORIGIN_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "rm_motor_return_origin_cfg.h"
+#include "rm_motor_return_origin_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+typedef enum e_motor_return_origin_start_flag
+{
+    MOTOR_RETURN_ORIGIN_START_FLAG_STOP  = 0,
+    MOTOR_RETURN_ORIGIN_START_FLAG_START = 1,
+} motor_return_origin_start_flag_t;
+
+/** Extended configurations for return origin function  */
+typedef struct st_motor_return_origin_extended_cfg
+{
+    float f_search_speed_rpm;           ///< Speed to search origin position [rpm]
+    float f_return_accel_rpm;           ///< Acceleration speed when return [rpm/s]
+
+    float f_speed_ctrl_period;          ///< Period of speed control [sec]
+    float f_maximum_current;            ///< Maximum current [A]
+    float f_current_limit_percent_push; ///< Percentage of current at pushing
+    float f_pushing_time;               ///< Keep pushing time [sec]
+    float f_over_degree;                ///< Angle to judge search impossible [degree]
+    float f_return_degree;              ///< Return angle from pushing position [degree]
+    float f_mechanical_gear_ratio;      ///< Mechanical gear ratio
+} motor_return_origin_extended_cfg_t;
+
+/** Variables for rerutn origin with pushing */
+typedef struct st_motor_return_origin_pushing
+{
+    uint32_t u4_time_counter;          ///< Counter of speed cyclic (to judge the time)
+    float    f_sum_position;           ///< Summary of position data
+    uint32_t u4_sum_counter;           ///< Counter of summary
+    float    f_move_amount;            ///< Movement amount [degree]
+
+    float f_judge_iq;                  ///< q-axis current to judge pushing
+    float f_pushing_counts;            ///< Counts to measure pushing time
+} motor_return_origin_pushing_t;
+
+/** Return origin function instance control block */
+typedef struct st_motor_return_origin_instance_ctrl
+{
+    uint32_t open;                               ///< Used to determine if the module is configured
+
+    motor_return_origin_start_flag_t start_flag; ///< start/stop flag
+
+    motor_return_origin_state_t state;           ///< State number of return origin process
+    int8_t s1_direction;                         ///< Moving direction
+    float  f_angle_degree_on_edge;               ///< Rotor angle on the edge [degree]
+    float  f_current_speed;                      ///< Current speed
+    float  f_origin_position_angle_degree;       ///< Searched origin position [degree]
+    float  f_search_speed;                       ///< Speed to search origin position [rad / sampling time]
+    float  f_accel_speed;                        ///< Speed accelaration
+    float  f_position_reference_degree;          ///< Position reference [degree]
+
+    motor_return_origin_pushing_t st_pushing;    ///< Variables for pushing
+
+    motor_return_origin_set_data_t receive_data; ///< Received data from speed(position) & current
+
+    motor_return_origin_cfg_t const * p_cfg;     ///< Pointer of configuration structure
+} motor_return_origin_instance_ctrl_t;
+
+/**********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/** @cond INC_HEADER_DEFS_SEC */
+/** Filled in interface API structure for this instance. */
+extern const motor_return_origin_api_t g_motor_return_origin_on_motor_return_origin;
+
+/** @endcond */
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Public Function Prototypes
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_RETURN_ORIGIN_Open(motor_return_origin_ctrl_t * const      p_ctrl,
+                                      motor_return_origin_cfg_t const * const p_cfg);
+
+fsp_err_t RM_MOTOR_RETURN_ORIGIN_Close(motor_return_origin_ctrl_t * const p_ctrl);
+
+fsp_err_t RM_MOTOR_RETURN_ORIGIN_Start(motor_return_origin_ctrl_t * const p_ctrl);
+
+fsp_err_t RM_MOTOR_RETURN_ORIGIN_Stop(motor_return_origin_ctrl_t * const p_ctrl);
+
+fsp_err_t RM_MOTOR_RETURN_ORIGIN_Reset(motor_return_origin_ctrl_t * const p_ctrl);
+
+fsp_err_t RM_MOTOR_RETURN_ORIGIN_InfoGet(motor_return_origin_ctrl_t * const p_ctrl,
+                                         motor_return_origin_info_t * const p_info);
+
+fsp_err_t RM_MOTOR_RETURN_ORIGIN_DataSet(motor_return_origin_ctrl_t * const     p_ctrl,
+                                         motor_return_origin_set_data_t * const p_set_data);
+
+fsp_err_t RM_MOTOR_RETURN_ORIGIN_SpeedCyclic(motor_return_origin_ctrl_t * const p_ctrl);
+
+fsp_err_t RM_MOTOR_RETURN_ORIGIN_ParameterUpdate(motor_return_origin_ctrl_t * const      p_ctrl,
+                                                 motor_return_origin_cfg_t const * const p_cfg);
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif                                 // RM_MOTOR_RETURN_ORIGIN_H
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup MOTOR_RETURN_ORIGIN)
+ **********************************************************************************************************************/
diff --git a/ra/fsp/inc/instances/rm_motor_sense_encoder.h b/ra/fsp/inc/instances/rm_motor_sense_encoder.h
index ce8073bdc..df4964b48 100644
--- a/ra/fsp/inc/instances/rm_motor_sense_encoder.h
+++ b/ra/fsp/inc/instances/rm_motor_sense_encoder.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_motor_sense_hall.h b/ra/fsp/inc/instances/rm_motor_sense_hall.h
index 23271501b..ac9809054 100644
--- a/ra/fsp/inc/instances/rm_motor_sense_hall.h
+++ b/ra/fsp/inc/instances/rm_motor_sense_hall.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_motor_sense_induction.h b/ra/fsp/inc/instances/rm_motor_sense_induction.h
index 94f2dc531..32904b330 100644
--- a/ra/fsp/inc/instances/rm_motor_sense_induction.h
+++ b/ra/fsp/inc/instances/rm_motor_sense_induction.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_motor_sensorless.h b/ra/fsp/inc/instances/rm_motor_sensorless.h
index e18af6867..855520c75 100644
--- a/ra/fsp/inc/instances/rm_motor_sensorless.h
+++ b/ra/fsp/inc/instances/rm_motor_sensorless.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -72,7 +72,7 @@ typedef struct st_motor_sensorless_extended_cfg
 {
     float f_overcurrent_limit;         ///< Over-current limit [A]
     float f_overvoltage_limit;         ///< Over-voltage limit [V]
-    float f_overspeed_limit;           ///< Over-speed limit [rad/s]
+    float f_overspeed_limit;           ///< Over-speed limit [rpm]
     float f_lowvoltage_limit;          ///< Low-voltage limit [V]
 } motor_sensorless_extended_cfg_t;
 
@@ -137,6 +137,8 @@ fsp_err_t RM_MOTOR_SENSORLESS_PositionSet(motor_ctrl_t * const
 
 fsp_err_t RM_MOTOR_SENSORLESS_WaitStopFlagGet(motor_ctrl_t * const p_ctrl, motor_wait_stop_flag_t * const p_flag);
 
+fsp_err_t RM_MOTOR_SENSORLESS_FunctionSelect(motor_ctrl_t * const p_ctrl, motor_function_select_t const function);
+
 /*******************************************************************************************************************//**
  * @} (end addtogroup MOTOR_SENSORLESS)
  **********************************************************************************************************************/
diff --git a/ra/fsp/inc/instances/rm_motor_speed.h b/ra/fsp/inc/instances/rm_motor_speed.h
index c38527d78..7a7a3f0cb 100644
--- a/ra/fsp/inc/instances/rm_motor_speed.h
+++ b/ra/fsp/inc/instances/rm_motor_speed.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -192,6 +192,12 @@ typedef enum  e_motor_speed_observer_switch
     MOTOR_SPEED_OBSERVER_SWITCH_ENABLE  = 1  ///< Enable speed observer
 } motor_speed_observer_switch_t;
 
+typedef enum  e_motor_speed_observer_select
+{
+    MOTOR_SPEED_OBSERVER_SELECT_NORMAL      = 0, ///< Normal speed observer
+    MOTOR_SPEED_OBSERVER_SELECT_DISTURBANCE = 1, ///< Disturbance speed observer
+} motor_speed_observer_select_t;
+
 typedef struct st_motor_speed_observer
 {
     float f4_speed_rad;                 ///< speed observer output speed [rad/s] (electrical)
@@ -210,11 +216,22 @@ typedef struct st_motor_speed_observer
     motor_speed_2nd_order_lpf_t st_lpf; ///< second order LPF structure
 } motor_speed_observer_t;
 
+typedef struct st_motor_speed_disturbance_observer
+{
+    float             f4_gain_distubance_estimate; ///< Gain of disturbance estimator
+    float             f4_gain_speed_estimate;      ///< Gain of speed estimator
+    float             f4_estimated_distubance;     ///< Estimated disturbance
+    float             f4_estimated_speed;          ///< Estimated speed
+    float             f4_inertia;                  ///< Total inertia of system [kgm^2]
+    float             f4_ctrl_period;              ///< Interval of estimator execution
+    motor_speed_lpf_t st_lpf;                      ///< Structure for LPF
+} motor_speed_disturbance_observer_t;
+
 typedef struct st_motor_speed_extended_cfg
 {
     uint8_t u1_ctrl_method;                             ///< Feedback control method
 
-    float f_speed_ctrl_period;                          ///< Speed control period [usec]
+    float f_speed_ctrl_period;                          ///< Speed control period [sec]
     float f_limit_speed_change;                         ///< Reference speed max change limit [rad/s]
     float f_max_speed_rad;                              ///< Maximum speed command value [rad/s]
     float f_omega_t;                                    ///< Speed LPF design value
@@ -223,10 +240,13 @@ typedef struct st_motor_speed_extended_cfg
 
     float f_ol_fb_speed_limit_rate;                     ///< Rate of reference speed for feedback speed limitter
 
+    float f_natural_frequency;                          ///< Natural frequency for disturbance observer [Hz]
+
     motor_speed_openloop_damping_t u1_openloop_damping; ///< Openloop damping active flag
     motor_speed_flux_weaken_t      u1_flux_weakening;   ///< Flux weakening active flag
     motor_speed_less_switch_t      u1_less_switch;      ///< Soft switching active flag
     motor_speed_observer_switch_t  u1_observer_swtich;  ///< Speed observer active flag
+    motor_speed_observer_select_t  observer_select;     ///< Selection of speed observer type
 
     motor_speed_oldamp_t          ol_param;             ///< Parameter for open-loop damping
     motor_speed_oldamp_sub_t      ol_sub_param;         ///< Sub parameter for open-loop damping
@@ -246,47 +266,49 @@ typedef struct st_motor_speed_instance_ctrl
 {
     uint32_t open;
 
-    uint8_t u1_active;                                     ///< Flag to set active/inactive the speed control
-    uint8_t u1_state_speed_ref;                            ///< The speed control status
-    uint8_t u1_flag_get_iref;                              ///< Flag to get d/q-axis current reference
-    uint8_t u1_state_id_ref;                               ///< The d-axis current command status
-    uint8_t u1_state_iq_ref;                               ///< The q-axis current command status
-    float   f_id_ref;                                      ///< D-axis current reference [A] for calculation
-    float   f_iq_ref;                                      ///< Q-axis current reference [A] for calculation
-    float   f_rpm2rad;                                     ///< Coeficient to translate [rpm] to [rad/s]
-    float   f_ref_speed_rad_ctrl;                          ///< Command speed value for speed PI control[rad/s]
-    float   f_ref_speed_rad;                               ///< Reference speed value [rad/s]
-    float   f_speed_lpf_rad;                               ///< Speed processed by LPF
+    uint8_t u1_active;                                          ///< Flag to set active/inactive the speed control
+    uint8_t u1_state_speed_ref;                                 ///< The speed control status
+    uint8_t u1_flag_get_iref;                                   ///< Flag to get d/q-axis current reference
+    uint8_t u1_state_id_ref;                                    ///< The d-axis current command status
+    uint8_t u1_state_iq_ref;                                    ///< The q-axis current command status
+    float   f_id_ref;                                           ///< D-axis current reference [A] for calculation
+    float   f_iq_ref;                                           ///< Q-axis current reference [A] for calculation
+    float   f_rpm2rad;                                          ///< Coeficient to translate [rpm] to [rad/s]
+    float   f_ref_speed_rad_ctrl;                               ///< Command speed value for speed PI control[rad/s]
+    float   f_ref_speed_rad;                                    ///< Reference speed value [rad/s]
+    float   f_speed_lpf_rad;                                    ///< Speed processed by LPF
     motor_speed_ctrl_status_t e_status;
 
     /* Openloop damping related valiable */
-    uint8_t u1_flag_down_to_ol;                            ///< The open-loop drive flag
-    float   f_ol_iq_down_step;                             ///< The q-axis current reference ramping down rate [A/ms]
-    float   f_phase_err_rad_lpf;                           ///< LPF value of phase error[rad]
-    float   f_init_phase_err_rad;                          ///< Initialization value of phase error rate
-    float   f_opl_torque_current;                          ///< The torque current (Iq) in sensor-less switching
-    float   f_damp_comp_speed;                             ///< The speed for open-loop damping
-    float   f_damp_comp_gain;                              ///< The gain for open-loop damping
-    float   f_fb_speed_limit_rate;                         ///< The limit of speed feed-back rate
+    uint8_t u1_flag_down_to_ol;                                 ///< The open-loop drive flag
+    float   f_ol_iq_down_step;                                  ///< The q-axis current reference ramping down rate [A/ms]
+    float   f_phase_err_rad_lpf;                                ///< LPF value of phase error[rad]
+    float   f_init_phase_err_rad;                               ///< Initialization value of phase error rate
+    float   f_opl_torque_current;                               ///< The torque current (Iq) in sensor-less switching
+    float   f_damp_comp_speed;                                  ///< The speed for open-loop damping
+    float   f_damp_comp_gain;                                   ///< The gain for open-loop damping
+    float   f_fb_speed_limit_rate;                              ///< The limit of speed feed-back rate
 
     /* Flux Weakening related valiable */
-    uint8_t u1_enable_flux_weakning;                       ///< The flag for enable/disable flux weakening process
-    motor_speed_flux_weakening_t st_flxwkn;                ///< Data for flux-weakening control
+    uint8_t u1_enable_flux_weakning;                            ///< The flag for enable/disable flux weakening process
+    motor_speed_flux_weakening_t st_flxwkn;                     ///< Data for flux-weakening control
 
     motor_speed_cfg_t const * p_cfg;
-    motor_speed_pi_params_t   pi_param;                    ///< Data for flux-weakening control
-    motor_speed_input_t       st_input;                    ///< Input data buffer
-    motor_speed_lpf_t         st_speed_lpf;                ///< Speed LPF structure
-    motor_speed_lpf_t         st_phase_err_lpf;            ///< Phase error LPF structure
-    motor_speed_observer_t    st_observer;                 ///< Speed observer structure
+    motor_speed_pi_params_t   pi_param;                         ///< Data for flux-weakening control
+    motor_speed_input_t       st_input;                         ///< Input data buffer
+    motor_speed_lpf_t         st_speed_lpf;                     ///< Speed LPF structure
+    motor_speed_lpf_t         st_phase_err_lpf;                 ///< Phase error LPF structure
+
+    motor_speed_observer_t             st_observer;             ///< Speed observer structure
+    motor_speed_disturbance_observer_t st_disturbance_observer; ///< Disturbance speed observer structure
 
-    motor_speed_position_data_t st_position_data;          ///< Data for position control
+    motor_speed_position_data_t st_position_data;               ///< Data for position control
 
     /* cyclic timer callback */
-    timer_callback_args_t timer_args;                      ///< Cyclic timer callback
+    timer_callback_args_t timer_args;                           ///< Cyclic timer callback
 
 #if MOTOR_SPEED_CFG_POSITION_SUPPORTED == 1
-    motor_position_instance_t const * p_position_instance; ///< Position module instance
+    motor_position_instance_t const * p_position_instance;      ///< Position module instance
 #endif
 } motor_speed_instance_ctrl_t;
 
diff --git a/ra/fsp/inc/instances/rm_ob1203.h b/ra/fsp/inc/instances/rm_ob1203.h
index 8fd47e555..4366ab143 100644
--- a/ra/fsp/inc/instances/rm_ob1203.h
+++ b/ra/fsp/inc/instances/rm_ob1203.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_touch.h b/ra/fsp/inc/instances/rm_touch.h
index 3819183c5..4792ed364 100644
--- a/ra/fsp/inc/instances/rm_touch.h
+++ b/ra/fsp/inc/instances/rm_touch.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_vee_flash.h b/ra/fsp/inc/instances/rm_vee_flash.h
index 760066902..f62439114 100644
--- a/ra/fsp/inc/instances/rm_vee_flash.h
+++ b/ra/fsp/inc/instances/rm_vee_flash.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_wifi_onchip_da16200.h b/ra/fsp/inc/instances/rm_wifi_onchip_da16200.h
index 13f783e18..29897132e 100644
--- a/ra/fsp/inc/instances/rm_wifi_onchip_da16200.h
+++ b/ra/fsp/inc/instances/rm_wifi_onchip_da16200.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_wifi_onchip_silex.h b/ra/fsp/inc/instances/rm_wifi_onchip_silex.h
index df39c517f..711abbaad 100644
--- a/ra/fsp/inc/instances/rm_wifi_onchip_silex.h
+++ b/ra/fsp/inc/instances/rm_wifi_onchip_silex.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/inc/instances/rm_zmod4xxx.h b/ra/fsp/inc/instances/rm_zmod4xxx.h
index 781adbc62..77212eb67 100644
--- a/ra/fsp/inc/instances/rm_zmod4xxx.h
+++ b/ra/fsp/inc/instances/rm_zmod4xxx.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h
index f4131f022..6d1cbbae1 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h
@@ -831,7 +831,8 @@ typedef struct
             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
             uint8_t            : 1;
             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
-            uint8_t            : 2;
+            uint8_t            : 1;
+            __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
         } RTCCR_b;
     };
     __IM uint8_t RESERVED;
@@ -1003,6 +1004,213 @@ typedef struct
     };
 } R_USB_FS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
 
+/**
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
+            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
+            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
+            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
+            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
+            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
+        } AGTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
+            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
+            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
+            uint8_t              : 1;
+        } AGTMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+                                        *   ratio                                                                     */
+            uint8_t           : 4;
+            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
+        } AGTMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+                                        *   mode.                                                                     */
+            uint8_t             : 1;
+            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
+            uint8_t             : 1;
+            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
+            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
+        } AGTIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
+            uint8_t            : 5;
+        } AGTISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
+
+        struct
+        {
+            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
+            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
+            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
+            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
+            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
+            uint8_t              : 1;
+        } AGTCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_b;
+    };
+} R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
+
+        struct
+        {
+            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IM uint16_t                 RESERVED;
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
+} R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
+
+        struct
+        {
+            __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
+} R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_clusters */
 
 /* =========================================================================================================================== */
@@ -1456,16 +1664,17 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
 
     union
     {
-        __IM uint16_t ADDR[28];        /*!< (@ 0x00000020) A/D Data Register                                          */
+        __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
 
         struct
         {
             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
                                         *   storing the result of A/D conversion.                                     */
-        } ADDR_b[28];
+        } ADDR_b[29];
     };
-    __IM uint32_t RESERVED1[2];
-    __IM uint16_t RESERVED2;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+    __IM uint16_t RESERVED3;
 
     union
     {
@@ -1658,7 +1867,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint16_t                : 3;
         } ADSWTSTR2_b;
     };
-    __IM uint16_t RESERVED3;
+    __IM uint16_t RESERVED4;
 
     union
     {
@@ -1720,7 +1929,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 6;
         } ADACSR_b;
     };
-    __IM uint8_t RESERVED4;
+    __IM uint8_t RESERVED5;
 
     union
     {
@@ -1790,7 +1999,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
         } ADSER_b;
     };
-    __IM uint8_t RESERVED5;
+    __IM uint8_t RESERVED6;
 
     union
     {
@@ -1806,7 +2015,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
         } ADHVREFCNT_b;
     };
-    __IM uint8_t RESERVED6;
+    __IM uint8_t RESERVED7;
 
     union
     {
@@ -1824,8 +2033,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t              : 2;
         } ADWINMON_b;
     };
-    __IM uint8_t  RESERVED7;
-    __IM uint16_t RESERVED8;
+    __IM uint8_t  RESERVED8;
+    __IM uint16_t RESERVED9;
 
     union
     {
@@ -2001,7 +2210,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 6;
         } ADCMPSER_b;
     };
-    __IM uint8_t RESERVED9;
+    __IM uint8_t RESERVED10;
 
     union
     {
@@ -2016,7 +2225,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
         } ADCMPBNSR_b;
     };
-    __IM uint8_t RESERVED10;
+    __IM uint8_t RESERVED11;
 
     union
     {
@@ -2055,8 +2264,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 7;
         } ADCMPBSR_b;
     };
-    __IM uint8_t  RESERVED11;
-    __IM uint16_t RESERVED12;
+    __IM uint8_t  RESERVED12;
+    __IM uint16_t RESERVED13;
 
     union
     {
@@ -2260,7 +2469,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 7;
         } ADBUFEN_b;
     };
-    __IM uint8_t RESERVED13;
+    __IM uint8_t RESERVED14;
 
     union
     {
@@ -2274,9 +2483,9 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 3;
         } ADBUFPTR_b;
     };
-    __IM uint8_t  RESERVED14;
-    __IM uint32_t RESERVED15[2];
-    __IM uint8_t  RESERVED16;
+    __IM uint8_t  RESERVED15;
+    __IM uint32_t RESERVED16[2];
+    __IM uint8_t  RESERVED17;
 
     union
     {
@@ -2343,7 +2552,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
         } ADCALEXE_b;
     };
-    __IM uint8_t RESERVED17;
+    __IM uint8_t RESERVED18;
 
     union
     {
@@ -2360,8 +2569,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
         } VREFAMPCNT_b;
     };
-    __IM uint8_t  RESERVED18;
-    __IM uint16_t RESERVED19;
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -2383,8 +2592,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 6;
         } ADRST_b;
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint32_t RESERVED21[41];
+    __IM uint8_t  RESERVED21;
+    __IM uint32_t RESERVED22[41];
 
     union
     {
@@ -2442,7 +2651,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
         } ADPGAGS0_b;
     };
-    __IM uint32_t RESERVED22[3];
+    __IM uint32_t RESERVED23[3];
 
     union
     {
@@ -2469,7 +2678,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
         } ADPGADCR0_b;
     };
-    __IM uint16_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -2498,8 +2707,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 7;
         } ADPGADBS1_b;
     };
-    __IM uint16_t RESERVED24;
-    __IM uint32_t RESERVED25[10];
+    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED26[10];
 
     union
     {
@@ -2515,156 +2724,6 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
     };
 } R_ADC0_Type;                         /*!< Size = 484 (0x1e4)                                                        */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Asynchronous General Purpose Timer (R_AGT0)
- */
-
-typedef struct                         /*!< (@ 0x40084000) R_AGT0 Structure                                           */
-{
-    union
-    {
-        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
-
-        struct
-        {
-            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written
-                                        *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
-                                        *   is forcibly stopped and set to FFFFH.                                     */
-        } AGT_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCRn register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMA_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCR register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMB_b;
-    };
-    __IM uint16_t RESERVED;
-
-    union
-    {
-        __IOM uint8_t AGTCR;           /*!< (@ 0x00000008) AGT Control Register                                       */
-
-        struct
-        {
-            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
-            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
-            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
-            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
-            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
-            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
-        } AGTCR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000009) AGT Mode Register 1                                        */
-
-        struct
-        {
-            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
-            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
-            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
-            uint8_t              : 1;
-        } AGTMR1_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000A) AGT Mode Register 2                                        */
-
-        struct
-        {
-            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
-                                        *   ratio                                                                     */
-            uint8_t           : 4;
-            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
-        } AGTMR2_b;
-    };
-    __IM uint8_t RESERVED1;
-
-    union
-    {
-        __IOM uint8_t AGTIOC;          /*!< (@ 0x0000000C) AGT I/O Control Register                                   */
-
-        struct
-        {
-            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
-                                        *   mode.                                                                     */
-            uint8_t             : 1;
-            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
-            uint8_t             : 1;
-            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
-            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
-        } AGTIOC_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTISR;          /*!< (@ 0x0000000D) AGT Event Pin Select Register                              */
-
-        struct
-        {
-            uint8_t            : 2;
-            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
-            uint8_t            : 5;
-        } AGTISR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTCMSR;         /*!< (@ 0x0000000E) AGT Compare Match Function Select Register                 */
-
-        struct
-        {
-            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
-            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
-            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
-            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
-            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
-            uint8_t              : 1;
-        } AGTCMSR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x0000000F) AGT Pin Select Register                                    */
-
-        struct
-        {
-            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
-            uint8_t            : 2;
-            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
-            uint8_t            : 3;
-        } AGTIOSEL_b;
-    };
-} R_AGT0_Type;                         /*!< Size = 16 (0x10)                                                          */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -4682,46 +4741,99 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            uint32_t : 18;
         } GTSTR_b;
     };
 
@@ -4773,7 +4885,60 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
                                          *   1 means counter stop.                                                     */
-            uint32_t : 18;
+            __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
         } GTSTP_b;
     };
 
@@ -4797,7 +4962,24 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
-            uint32_t             : 18;
+            __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
         } GTCLR_b;
     };
 
@@ -5118,16 +5300,23 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+        __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
 
         struct
         {
-            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
-            uint32_t            : 15;
-            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
-            uint32_t            : 5;
-            __IOM uint32_t TPCS : 3;   /*!< [26..24] Timer Prescaler Select                                           */
-            uint32_t            : 5;
+            __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
+            uint32_t               : 7;
+            __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
+            __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
+            __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
+            __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
+            uint32_t               : 2;
+            __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
+            __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
+            uint32_t               : 4;
+            __IOM uint32_t TPCS    : 3; /*!< [26..24] Timer Prescaler Select                                           */
+            __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
+            uint32_t               : 3;
         } GTCR_b;
     };
 
@@ -5198,13 +5387,36 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
         struct
         {
-            uint32_t               : 24;
-            __IOM uint32_t GRP     : 2; /*!< [25..24] Output Disable Source Select                                     */
+            uint32_t            : 8;
+            __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
+            __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            uint32_t               : 4;
+            __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
             uint32_t               : 2;
-            __IOM uint32_t GRPDTE  : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
-            __IOM uint32_t GRPABH  : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable               */
-            __IOM uint32_t GRPABL  : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
-            __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
+            __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
+            __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
         } GTINTAD_b;
     };
 
@@ -5247,32 +5459,36 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTBER;          /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
 
         struct
         {
-            __IOM uint32_t BD0    : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
-            __IOM uint32_t BD1    : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
-            __IOM uint32_t BD2    : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
-            __IOM uint32_t BD3    : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
-            uint32_t              : 12;
-            __IOM uint32_t CCRA   : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
-            __IOM uint32_t CCRB   : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
-            __IOM uint32_t PR     : 2; /*!< [21..20] GTPR Buffer Operation                                            */
-            __OM uint32_t  CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
-                                        *   is read as 0.                                                             */
+            __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
+            __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+                                         *   is read as 0.                                                             */
             uint32_t             : 1;
-            __IOM uint32_t ADTTA : 2;  /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDA : 1;  /*!< [26..26] GTADTRA Double Buffer Operation                                  */
+            __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
             uint32_t             : 1;
-            __IOM uint32_t ADTTB : 2;  /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDB : 1;  /*!< [30..30] GTADTRB Double Buffer Operation                                  */
+            __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
             uint32_t             : 1;
         } GTBER_b;
     };
@@ -5496,7 +5712,126 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             uint32_t            : 31;
         } GTSOTR_b;
     };
-    __IM uint32_t RESERVED[5];
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
 
     union
     {
@@ -5530,7 +5865,7 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             uint32_t            : 4;
         } GTPC_b;
     };
-    __IM uint32_t RESERVED1[4];
+    __IM uint32_t RESERVED[4];
 
     union
     {
@@ -5572,17 +5907,137 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
         {
             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 4;
             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
-            uint32_t             : 7;
+            __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
+            uint32_t             : 6;
             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
-            uint32_t             : 7;
+            __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
+            uint32_t             : 6;
         } GTSECR_b;
     };
-} R_GPT0_Type;                         /*!< Size = 216 (0xd8)                                                         */
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
+            __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
+                                        *   Disable                                                                   */
+            uint32_t             : 2;
+            __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t             : 1;
+            __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
+                                        *   Transfer Disable                                                          */
+            uint32_t             : 2;
+            __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
+            __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
+            __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
+            __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
+            uint32_t             : 2;
+        } GTBER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
+
+        struct
+        {
+            __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
+            uint32_t              : 11;
+            __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
+            uint32_t              : 11;
+        } GTOLBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
+                                        *                  Capture Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
+            __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
+                                        *   Other Channel GTCCRb Input Capture Source Enable                          */
+            __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
+        } GTICCR_b;
+    };
+} R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_OPS                                         ================ */
@@ -9333,8 +9788,18 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } IICCKDIVCR_b;
         };
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint16_t RESERVED21;
+
+    union
+    {
+        __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
+
+        struct
+        {
+            __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
+            uint8_t                : 5;
+        } I3CCKDIVCR_b;
+    };
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -9461,8 +9926,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
         } I3CCKCR_b;
     };
-    __IM uint16_t RESERVED22;
-    __IM uint32_t RESERVED23[3];
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
 
     union
     {
@@ -9476,8 +9941,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                 : 29;
         } SNZREQCR1_b;
     };
-    __IM uint32_t RESERVED24;
-    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -9492,7 +9957,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
         } SNZCR_b;
     };
-    __IM uint8_t RESERVED26;
+    __IM uint8_t RESERVED25;
 
     union
     {
@@ -9522,7 +9987,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } SNZEDCR1_b;
     };
-    __IM uint16_t RESERVED27;
+    __IM uint16_t RESERVED26;
 
     union
     {
@@ -9565,7 +10030,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 1;
         } SNZREQCR_b;
     };
-    __IM uint16_t RESERVED28;
+    __IM uint16_t RESERVED27;
 
     union
     {
@@ -9603,7 +10068,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 3;
         } OPCCR_b;
     };
-    __IM uint8_t RESERVED29;
+    __IM uint8_t RESERVED28;
 
     union
     {
@@ -9615,7 +10080,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } MOSCWTCR_b;
     };
-    __IM uint8_t RESERVED30[2];
+    __IM uint8_t RESERVED29[2];
 
     union
     {
@@ -9628,7 +10093,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t : 5;
         } HOCOWTCR_b;
     };
-    __IM uint16_t RESERVED31[2];
+    __IM uint16_t RESERVED30[2];
 
     union
     {
@@ -9642,8 +10107,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 3;
         } SOPCCR_b;
     };
-    __IM uint8_t  RESERVED32;
-    __IM uint32_t RESERVED33[5];
+    __IM uint8_t  RESERVED31;
+    __IM uint32_t RESERVED32[5];
 
     union
     {
@@ -9677,8 +10142,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
         } RSTSR1_b;
     };
-    __IM uint16_t RESERVED34;
-    __IM uint32_t RESERVED35[3];
+    __IM uint16_t RESERVED33;
+    __IM uint32_t RESERVED34[3];
 
     union
     {
@@ -9704,8 +10169,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
         } SDADCCKCR_b;
     };
-    __IM uint16_t RESERVED36;
-    __IM uint32_t RESERVED37[3];
+    __IM uint16_t RESERVED35;
+    __IM uint32_t RESERVED36[3];
 
     union
     {
@@ -9760,7 +10225,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t          : 6;
         } LVD2SR_b;
     };
-    __IM uint32_t RESERVED38[183];
+    __IM uint32_t RESERVED37[183];
 
     union
     {
@@ -9788,7 +10253,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 14;
         } CGFSAR_b;
     };
-    __IM uint32_t RESERVED39;
+    __IM uint32_t RESERVED38;
 
     union
     {
@@ -9857,7 +10322,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 8;
         } BBFSAR_b;
     };
-    __IM uint32_t RESERVED40[3];
+    __IM uint32_t RESERVED39[3];
 
     union
     {
@@ -9919,8 +10384,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 4;
         } DPFSAR_b;
     };
-    __IM uint32_t RESERVED41[6];
-    __IM uint16_t RESERVED42;
+    __IM uint32_t RESERVED40[6];
+    __IM uint16_t RESERVED41;
 
     union
     {
@@ -10138,7 +10603,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 3;
         } DPSIEGR2_b;
     };
-    __IM uint8_t RESERVED43;
+    __IM uint8_t RESERVED42;
 
     union
     {
@@ -10196,7 +10661,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } RSTSR2_b;
     };
-    __IM uint8_t RESERVED44;
+    __IM uint8_t RESERVED43;
 
     union
     {
@@ -10213,7 +10678,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                           *   Enable                                                                    */
         } MOMCR_b;
     };
-    __IM uint16_t RESERVED45;
+    __IM uint16_t RESERVED44;
 
     union
     {
@@ -10283,7 +10748,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } LVD2CMPCR_b;
         };
     };
-    __IM uint8_t RESERVED46;
+    __IM uint8_t RESERVED45;
 
     union
     {
@@ -10316,7 +10781,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
         } LVD2CR0_b;
     };
-    __IM uint8_t RESERVED47;
+    __IM uint8_t RESERVED46;
 
     union
     {
@@ -10351,7 +10816,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 7;
         } VBTCR1_b;
     };
-    __IM uint32_t RESERVED48[8];
+    __IM uint32_t RESERVED47[8];
 
     union
     {
@@ -10394,7 +10859,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 6;
         } VCCSEL_b;
     };
-    __IM uint16_t RESERVED49;
+    __IM uint16_t RESERVED48;
 
     union
     {
@@ -10406,9 +10871,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } PL2LDOSCR_b;
     };
-    __IM uint8_t  RESERVED50;
-    __IM uint16_t RESERVED51;
-    __IM uint32_t RESERVED52[14];
+    __IM uint8_t  RESERVED49;
+    __IM uint16_t RESERVED50;
+    __IM uint32_t RESERVED51[14];
 
     union
     {
@@ -10431,8 +10896,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 6;
         } SOMCR_b;
     };
-    __IM uint16_t RESERVED53;
-    __IM uint32_t RESERVED54[3];
+    __IM uint16_t RESERVED52;
+    __IM uint32_t RESERVED53[3];
 
     union
     {
@@ -10444,7 +10909,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 7;
         } LOCOCR_b;
     };
-    __IM uint8_t RESERVED55;
+    __IM uint8_t RESERVED54;
 
     union
     {
@@ -10459,8 +10924,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                          *   trimming bits                                                             */
         } LOCOUTCR_b;
     };
-    __IM uint8_t  RESERVED56;
-    __IM uint32_t RESERVED57[7];
+    __IM uint8_t  RESERVED55;
+    __IM uint32_t RESERVED56[7];
 
     union
     {
@@ -10499,7 +10964,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 7;
         } VBTCMPCR_b;
     };
-    __IM uint8_t RESERVED58;
+    __IM uint8_t RESERVED57;
 
     union
     {
@@ -10513,7 +10978,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                  : 6;
         } VBTLVDICR_b;
     };
-    __IM uint8_t RESERVED59;
+    __IM uint8_t RESERVED58;
 
     union
     {
@@ -10525,7 +10990,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } VBTWCTLR_b;
     };
-    __IM uint8_t RESERVED60;
+    __IM uint8_t RESERVED59;
 
     union
     {
@@ -10660,9 +11125,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } VBTBER_b;
     };
-    __IM uint8_t  RESERVED61;
-    __IM uint16_t RESERVED62;
-    __IM uint32_t RESERVED63[15];
+    __IM uint8_t  RESERVED60;
+    __IM uint16_t RESERVED61;
+    __IM uint32_t RESERVED62[15];
 
     union
     {
@@ -11859,6 +12324,23 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
     __IM uint16_t RESERVED3;
 } R_WDT_Type;                          /*!< Size = 12 (0xc)                                                           */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
+ */
+
+typedef struct                          /*!< (@ 0x40084000) R_AGTX0 Structure                                          */
+{
+    union
+    {
+        __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
+        __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
+    };
+} R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_peripherals */
 
 /* =========================================================================================================================== */
@@ -11878,12 +12360,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_ACMPLP_BASE       0x40085E00UL
  #define R_ADC0_BASE         0x4005C000UL
  #define R_ADC1_BASE         0x4005C200UL
- #define R_AGT0_BASE         0x40084000UL
- #define R_AGT1_BASE         0x40084100UL
- #define R_AGT2_BASE         0x40084200UL
- #define R_AGT3_BASE         0x40084300UL
- #define R_AGT4_BASE         0x40084400UL
- #define R_AGT5_BASE         0x40084500UL
  #define R_BUS_BASE          0x40003000UL
  #define R_CAC_BASE          0x40044600UL
  #define R_CAN0_BASE         0x40050000UL
@@ -11963,6 +12439,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_TSN_BASE          0x407EC000UL
  #define R_USB_FS0_BASE      0x40090000UL
  #define R_WDT_BASE          0x40044200UL
+ #define R_AGTX0_BASE        0x40084000UL
+ #define R_AGTX1_BASE        0x40084100UL
+ #define R_AGTX2_BASE        0x40084200UL
+ #define R_AGTX3_BASE        0x40084300UL
+ #define R_AGTX4_BASE        0x40084400UL
+ #define R_AGTX5_BASE        0x40084500UL
+ #define R_AGTX6_BASE        0x40084600UL
+ #define R_AGTX7_BASE        0x40084700UL
+ #define R_AGTX8_BASE        0x40084800UL
+ #define R_AGTX9_BASE        0x40084900UL
 
 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
 
@@ -11983,12 +12469,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_ACMPLP       ((R_ACMPLP_Type *) R_ACMPLP_BASE)
  #define R_ADC0         ((R_ADC0_Type *) R_ADC0_BASE)
  #define R_ADC1         ((R_ADC0_Type *) R_ADC1_BASE)
- #define R_AGT0         ((R_AGT0_Type *) R_AGT0_BASE)
- #define R_AGT1         ((R_AGT0_Type *) R_AGT1_BASE)
- #define R_AGT2         ((R_AGT0_Type *) R_AGT2_BASE)
- #define R_AGT3         ((R_AGT0_Type *) R_AGT3_BASE)
- #define R_AGT4         ((R_AGT0_Type *) R_AGT4_BASE)
- #define R_AGT5         ((R_AGT0_Type *) R_AGT5_BASE)
  #define R_BUS          ((R_BUS_Type *) R_BUS_BASE)
  #define R_CAC          ((R_CAC_Type *) R_CAC_BASE)
  #define R_CAN0         ((R_CAN0_Type *) R_CAN0_BASE)
@@ -12068,6 +12548,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_TSN          ((R_TSN_Type *) R_TSN_BASE)
  #define R_USB_FS0      ((R_USB_FS0_Type *) R_USB_FS0_BASE)
  #define R_WDT          ((R_WDT_Type *) R_WDT_BASE)
+ #define R_AGTX0        ((R_AGTX0_Type *) R_AGTX0_BASE)
+ #define R_AGTX1        ((R_AGTX0_Type *) R_AGTX1_BASE)
+ #define R_AGTX2        ((R_AGTX0_Type *) R_AGTX2_BASE)
+ #define R_AGTX3        ((R_AGTX0_Type *) R_AGTX3_BASE)
+ #define R_AGTX4        ((R_AGTX0_Type *) R_AGTX4_BASE)
+ #define R_AGTX5        ((R_AGTX0_Type *) R_AGTX5_BASE)
+ #define R_AGTX6        ((R_AGTX0_Type *) R_AGTX6_BASE)
+ #define R_AGTX7        ((R_AGTX0_Type *) R_AGTX7_BASE)
+ #define R_AGTX8        ((R_AGTX0_Type *) R_AGTX8_BASE)
+ #define R_AGTX9        ((R_AGTX0_Type *) R_AGTX9_BASE)
 
 /** @} */ /* End of group Device_Peripheral_declaration */
 
@@ -12443,6 +12933,8 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 /* =========================================================================================================================== */
 
 /* =========================================================  RTCCR  ========================================================= */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
@@ -12507,6 +12999,101 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
 
+/* =========================================================================================================================== */
+/* ================                                           CTRL                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  AGTCR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AGTMR1  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
+/* ========================================================  AGTMR2  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
+/* =====================================================  AGTIOSEL_ALT  ====================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+/* ========================================================  AGTIOC  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AGTISR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AGTCMSR  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
+/* =======================================================  AGTIOSEL  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT16                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT32                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
+
 /** @} */ /* End of group PosMask_clusters */
 
 /* =========================================================================================================================== */
@@ -13098,77 +13685,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_ADC0_ADREFMON_MONSEL_Pos         (16UL)      /*!< MONSEL (Bit 16)                                       */
  #define R_ADC0_ADREFMON_MONSEL_Msk         (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f)                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/* ==========================================================  AGT  ========================================================== */
- #define R_AGT0_AGT_AGT_Pos           (0UL)      /*!< AGT (Bit 0)                                           */
- #define R_AGT0_AGT_AGT_Msk           (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
-/* ========================================================  AGTCMA  ========================================================= */
- #define R_AGT0_AGTCMA_AGTCMA_Pos     (0UL)      /*!< AGTCMA (Bit 0)                                        */
- #define R_AGT0_AGTCMA_AGTCMA_Msk     (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
-/* ========================================================  AGTCMB  ========================================================= */
- #define R_AGT0_AGTCMB_AGTCMB_Pos     (0UL)      /*!< AGTCMB (Bit 0)                                        */
- #define R_AGT0_AGTCMB_AGTCMB_Msk     (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
-/* =========================================================  AGTCR  ========================================================= */
- #define R_AGT0_AGTCR_TCMBF_Pos       (7UL)      /*!< TCMBF (Bit 7)                                         */
- #define R_AGT0_AGTCR_TCMBF_Msk       (0x80UL)   /*!< TCMBF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCMAF_Pos       (6UL)      /*!< TCMAF (Bit 6)                                         */
- #define R_AGT0_AGTCR_TCMAF_Msk       (0x40UL)   /*!< TCMAF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TUNDF_Pos       (5UL)      /*!< TUNDF (Bit 5)                                         */
- #define R_AGT0_AGTCR_TUNDF_Msk       (0x20UL)   /*!< TUNDF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TEDGF_Pos       (4UL)      /*!< TEDGF (Bit 4)                                         */
- #define R_AGT0_AGTCR_TEDGF_Msk       (0x10UL)   /*!< TEDGF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTOP_Pos       (2UL)      /*!< TSTOP (Bit 2)                                         */
- #define R_AGT0_AGTCR_TSTOP_Msk       (0x4UL)    /*!< TSTOP (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCSTF_Pos       (1UL)      /*!< TCSTF (Bit 1)                                         */
- #define R_AGT0_AGTCR_TCSTF_Msk       (0x2UL)    /*!< TCSTF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTART_Pos      (0UL)      /*!< TSTART (Bit 0)                                        */
- #define R_AGT0_AGTCR_TSTART_Msk      (0x1UL)    /*!< TSTART (Bitfield-Mask: 0x01)                          */
-/* ========================================================  AGTMR1  ========================================================= */
- #define R_AGT0_AGTMR1_TCK_Pos        (4UL)      /*!< TCK (Bit 4)                                           */
- #define R_AGT0_AGTMR1_TCK_Msk        (0x70UL)   /*!< TCK (Bitfield-Mask: 0x07)                             */
- #define R_AGT0_AGTMR1_TEDGPL_Pos     (3UL)      /*!< TEDGPL (Bit 3)                                        */
- #define R_AGT0_AGTMR1_TEDGPL_Msk     (0x8UL)    /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTMR1_TMOD_Pos       (0UL)      /*!< TMOD (Bit 0)                                          */
- #define R_AGT0_AGTMR1_TMOD_Msk       (0x7UL)    /*!< TMOD (Bitfield-Mask: 0x07)                            */
-/* ========================================================  AGTMR2  ========================================================= */
- #define R_AGT0_AGTMR2_LPM_Pos        (7UL)      /*!< LPM (Bit 7)                                           */
- #define R_AGT0_AGTMR2_LPM_Msk        (0x80UL)   /*!< LPM (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTMR2_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
- #define R_AGT0_AGTMR2_CKS_Msk        (0x7UL)    /*!< CKS (Bitfield-Mask: 0x07)                             */
-/* ========================================================  AGTIOC  ========================================================= */
- #define R_AGT0_AGTIOC_TIOGT_Pos      (6UL)      /*!< TIOGT (Bit 6)                                         */
- #define R_AGT0_AGTIOC_TIOGT_Msk      (0xc0UL)   /*!< TIOGT (Bitfield-Mask: 0x03)                           */
- #define R_AGT0_AGTIOC_TIPF_Pos       (4UL)      /*!< TIPF (Bit 4)                                          */
- #define R_AGT0_AGTIOC_TIPF_Msk       (0x30UL)   /*!< TIPF (Bitfield-Mask: 0x03)                            */
- #define R_AGT0_AGTIOC_TOE_Pos        (2UL)      /*!< TOE (Bit 2)                                           */
- #define R_AGT0_AGTIOC_TOE_Msk        (0x4UL)    /*!< TOE (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTIOC_TEDGSEL_Pos    (0UL)      /*!< TEDGSEL (Bit 0)                                       */
- #define R_AGT0_AGTIOC_TEDGSEL_Msk    (0x1UL)    /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
-/* ========================================================  AGTISR  ========================================================= */
- #define R_AGT0_AGTISR_EEPS_Pos       (2UL)      /*!< EEPS (Bit 2)                                          */
- #define R_AGT0_AGTISR_EEPS_Msk       (0x4UL)    /*!< EEPS (Bitfield-Mask: 0x01)                            */
-/* ========================================================  AGTCMSR  ======================================================== */
- #define R_AGT0_AGTCMSR_TOPOLB_Pos    (6UL)      /*!< TOPOLB (Bit 6)                                        */
- #define R_AGT0_AGTCMSR_TOPOLB_Msk    (0x40UL)   /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEB_Pos      (5UL)      /*!< TOEB (Bit 5)                                          */
- #define R_AGT0_AGTCMSR_TOEB_Msk      (0x20UL)   /*!< TOEB (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEB_Pos     (4UL)      /*!< TCMEB (Bit 4)                                         */
- #define R_AGT0_AGTCMSR_TCMEB_Msk     (0x10UL)   /*!< TCMEB (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCMSR_TOPOLA_Pos    (2UL)      /*!< TOPOLA (Bit 2)                                        */
- #define R_AGT0_AGTCMSR_TOPOLA_Msk    (0x4UL)    /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEA_Pos      (1UL)      /*!< TOEA (Bit 1)                                          */
- #define R_AGT0_AGTCMSR_TOEA_Msk      (0x2UL)    /*!< TOEA (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEA_Pos     (0UL)      /*!< TCMEA (Bit 0)                                         */
- #define R_AGT0_AGTCMSR_TCMEA_Msk     (0x1UL)    /*!< TCMEA (Bitfield-Mask: 0x01)                           */
-/* =======================================================  AGTIOSEL  ======================================================== */
- #define R_AGT0_AGTIOSEL_TIES_Pos     (4UL)      /*!< TIES (Bit 4)                                          */
- #define R_AGT0_AGTIOSEL_TIES_Msk     (0x10UL)   /*!< TIES (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTIOSEL_SEL_Pos      (0UL)      /*!< SEL (Bit 0)                                           */
- #define R_AGT0_AGTIOSEL_SEL_Msk      (0x3UL)    /*!< SEL (Bitfield-Mask: 0x03)                             */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -14350,10 +14866,22 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
 /* =========================================================  GTCR  ========================================================== */
+ #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
+ #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTCR_TPCS_Pos              (24UL)         /*!< TPCS (Bit 24)                                         */
  #define R_GPT0_GTCR_TPCS_Msk              (0x7000000UL)  /*!< TPCS (Bitfield-Mask: 0x07)                            */
  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
- #define R_GPT0_GTCR_MD_Msk                (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
+ #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
+ #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
+ #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
+ #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
 /* =======================================================  GTUDDTYC  ======================================================== */
@@ -14411,6 +14939,8 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
 /* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
+ #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
@@ -14419,8 +14949,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
- #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
- #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
+ #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
+ #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
+ #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
 /* =========================================================  GTST  ========================================================== */
  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
@@ -14477,6 +15015,8 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
+ #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
@@ -14566,6 +15106,67 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 /* ========================================================  GTSOTR  ========================================================= */
  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
 /* ========================================================  GTICLF  ========================================================= */
  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
@@ -14608,14 +15209,113 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
+ #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
+ #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTBER2  ========================================================= */
+ #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
+ #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
+ #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
+ #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
+ #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
+ #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
+ #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
+ #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
+ #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
+ #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
+ #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
+ #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
+ #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
+ #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
+ #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
+ #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
+ #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
+ #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
+ #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
+ #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTOLBR  ========================================================= */
+ #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
+ #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
+ #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
+ #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  GTICCR  ========================================================= */
+ #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
+ #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
+ #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
+ #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
+ #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
+ #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
+ #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
+ #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
+ #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
+ #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
+ #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
+ #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
+ #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
+ #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
+ #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
+ #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
+ #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
+ #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
+ #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
+ #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
+ #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_OPS                                         ================ */
@@ -16925,6 +17625,9 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 /* ======================================================  CECCKDIVCR  ======================================================= */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  I3CCKDIVCR  ======================================================= */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
 /* ======================================================  IICCKDIVCR  ======================================================= */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
@@ -17730,6 +18433,10 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_WDT_WDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
  #define R_WDT_WDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
 /** @} */ /* End of group PosMask_peripherals */
 
  #ifdef __cplusplus
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h
index 43672279d..37262f4d4 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h
@@ -738,7 +738,8 @@ typedef struct
             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
             uint8_t            : 1;
             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
-            uint8_t            : 2;
+            uint8_t            : 1;
+            __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
         } RTCCR_b;
     };
     __IM uint8_t RESERVED;
@@ -881,6 +882,213 @@ typedef struct
     __IM uint8_t RESERVED5[3];
 } R_RTC_CP_Type;                       /*!< Size = 16 (0x10)                                                          */
 
+/**
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
+            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
+            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
+            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
+            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
+            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
+        } AGTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
+            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
+            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
+            uint8_t              : 1;
+        } AGTMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+                                        *   ratio                                                                     */
+            uint8_t           : 4;
+            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
+        } AGTMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+                                        *   mode.                                                                     */
+            uint8_t             : 1;
+            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
+            uint8_t             : 1;
+            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
+            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
+        } AGTIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
+            uint8_t            : 5;
+        } AGTISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
+
+        struct
+        {
+            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
+            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
+            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
+            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
+            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
+            uint8_t              : 1;
+        } AGTCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_b;
+    };
+} R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
+
+        struct
+        {
+            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IM uint16_t                 RESERVED;
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
+} R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
+
+        struct
+        {
+            __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
+} R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_clusters */
 
 /* =========================================================================================================================== */
@@ -1259,16 +1467,17 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
 
     union
     {
-        __IM uint16_t ADDR[28];        /*!< (@ 0x00000020) A/D Data Register                                          */
+        __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
 
         struct
         {
             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
                                         *   storing the result of A/D conversion.                                     */
-        } ADDR_b[28];
+        } ADDR_b[29];
     };
-    __IM uint32_t RESERVED1[2];
-    __IM uint16_t RESERVED2;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+    __IM uint16_t RESERVED3;
 
     union
     {
@@ -1461,7 +1670,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint16_t                : 3;
         } ADSWTSTR2_b;
     };
-    __IM uint16_t RESERVED3;
+    __IM uint16_t RESERVED4;
 
     union
     {
@@ -1523,7 +1732,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 6;
         } ADACSR_b;
     };
-    __IM uint8_t RESERVED4;
+    __IM uint8_t RESERVED5;
 
     union
     {
@@ -1593,7 +1802,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
         } ADSER_b;
     };
-    __IM uint8_t RESERVED5;
+    __IM uint8_t RESERVED6;
 
     union
     {
@@ -1609,7 +1818,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
         } ADHVREFCNT_b;
     };
-    __IM uint8_t RESERVED6;
+    __IM uint8_t RESERVED7;
 
     union
     {
@@ -1627,8 +1836,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t              : 2;
         } ADWINMON_b;
     };
-    __IM uint8_t  RESERVED7;
-    __IM uint16_t RESERVED8;
+    __IM uint8_t  RESERVED8;
+    __IM uint16_t RESERVED9;
 
     union
     {
@@ -1804,7 +2013,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 6;
         } ADCMPSER_b;
     };
-    __IM uint8_t RESERVED9;
+    __IM uint8_t RESERVED10;
 
     union
     {
@@ -1819,7 +2028,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
         } ADCMPBNSR_b;
     };
-    __IM uint8_t RESERVED10;
+    __IM uint8_t RESERVED11;
 
     union
     {
@@ -1858,8 +2067,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 7;
         } ADCMPBSR_b;
     };
-    __IM uint8_t  RESERVED11;
-    __IM uint16_t RESERVED12;
+    __IM uint8_t  RESERVED12;
+    __IM uint16_t RESERVED13;
 
     union
     {
@@ -2063,7 +2272,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 7;
         } ADBUFEN_b;
     };
-    __IM uint8_t RESERVED13;
+    __IM uint8_t RESERVED14;
 
     union
     {
@@ -2077,9 +2286,9 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 3;
         } ADBUFPTR_b;
     };
-    __IM uint8_t  RESERVED14;
-    __IM uint32_t RESERVED15[2];
-    __IM uint8_t  RESERVED16;
+    __IM uint8_t  RESERVED15;
+    __IM uint32_t RESERVED16[2];
+    __IM uint8_t  RESERVED17;
 
     union
     {
@@ -2146,7 +2355,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
         } ADCALEXE_b;
     };
-    __IM uint8_t RESERVED17;
+    __IM uint8_t RESERVED18;
 
     union
     {
@@ -2163,8 +2372,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
         } VREFAMPCNT_b;
     };
-    __IM uint8_t  RESERVED18;
-    __IM uint16_t RESERVED19;
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -2186,8 +2395,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 6;
         } ADRST_b;
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint32_t RESERVED21[41];
+    __IM uint8_t  RESERVED21;
+    __IM uint32_t RESERVED22[41];
 
     union
     {
@@ -2245,7 +2454,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
         } ADPGAGS0_b;
     };
-    __IM uint32_t RESERVED22[3];
+    __IM uint32_t RESERVED23[3];
 
     union
     {
@@ -2272,7 +2481,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
         } ADPGADCR0_b;
     };
-    __IM uint16_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -2301,8 +2510,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 7;
         } ADPGADBS1_b;
     };
-    __IM uint16_t RESERVED24;
-    __IM uint32_t RESERVED25[10];
+    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED26[10];
 
     union
     {
@@ -2318,156 +2527,6 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
     };
 } R_ADC0_Type;                         /*!< Size = 484 (0x1e4)                                                        */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Asynchronous General Purpose Timer (R_AGT0)
- */
-
-typedef struct                         /*!< (@ 0x40084000) R_AGT0 Structure                                           */
-{
-    union
-    {
-        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
-
-        struct
-        {
-            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written
-                                        *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
-                                        *   is forcibly stopped and set to FFFFH.                                     */
-        } AGT_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCRn register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMA_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCR register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMB_b;
-    };
-    __IM uint16_t RESERVED;
-
-    union
-    {
-        __IOM uint8_t AGTCR;           /*!< (@ 0x00000008) AGT Control Register                                       */
-
-        struct
-        {
-            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
-            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
-            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
-            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
-            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
-            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
-        } AGTCR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000009) AGT Mode Register 1                                        */
-
-        struct
-        {
-            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
-            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
-            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
-            uint8_t              : 1;
-        } AGTMR1_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000A) AGT Mode Register 2                                        */
-
-        struct
-        {
-            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
-                                        *   ratio                                                                     */
-            uint8_t           : 4;
-            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
-        } AGTMR2_b;
-    };
-    __IM uint8_t RESERVED1;
-
-    union
-    {
-        __IOM uint8_t AGTIOC;          /*!< (@ 0x0000000C) AGT I/O Control Register                                   */
-
-        struct
-        {
-            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
-                                        *   mode.                                                                     */
-            uint8_t             : 1;
-            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
-            uint8_t             : 1;
-            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
-            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
-        } AGTIOC_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTISR;          /*!< (@ 0x0000000D) AGT Event Pin Select Register                              */
-
-        struct
-        {
-            uint8_t            : 2;
-            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
-            uint8_t            : 5;
-        } AGTISR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTCMSR;         /*!< (@ 0x0000000E) AGT Compare Match Function Select Register                 */
-
-        struct
-        {
-            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
-            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
-            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
-            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
-            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
-            uint8_t              : 1;
-        } AGTCMSR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x0000000F) AGT Pin Select Register                                    */
-
-        struct
-        {
-            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
-            uint8_t            : 2;
-            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
-            uint8_t            : 3;
-        } AGTIOSEL_b;
-    };
-} R_AGT0_Type;                         /*!< Size = 16 (0x10)                                                          */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -4077,46 +4136,99 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            uint32_t : 18;
         } GTSTR_b;
     };
 
@@ -4168,7 +4280,60 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
                                          *   1 means counter stop.                                                     */
-            uint32_t : 18;
+            __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
         } GTSTP_b;
     };
 
@@ -4192,7 +4357,24 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
-            uint32_t             : 18;
+            __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
         } GTCLR_b;
     };
 
@@ -4513,16 +4695,23 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+        __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
 
         struct
         {
-            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
-            uint32_t            : 15;
-            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
-            uint32_t            : 5;
-            __IOM uint32_t TPCS : 3;   /*!< [26..24] Timer Prescaler Select                                           */
-            uint32_t            : 5;
+            __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
+            uint32_t               : 7;
+            __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
+            __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
+            __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
+            __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
+            uint32_t               : 2;
+            __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
+            __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
+            uint32_t               : 4;
+            __IOM uint32_t TPCS    : 3; /*!< [26..24] Timer Prescaler Select                                           */
+            __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
+            uint32_t               : 3;
         } GTCR_b;
     };
 
@@ -4593,13 +4782,36 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
         struct
         {
-            uint32_t               : 24;
-            __IOM uint32_t GRP     : 2; /*!< [25..24] Output Disable Source Select                                     */
+            uint32_t            : 8;
+            __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
+            __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            uint32_t               : 4;
+            __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
             uint32_t               : 2;
-            __IOM uint32_t GRPDTE  : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
-            __IOM uint32_t GRPABH  : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable               */
-            __IOM uint32_t GRPABL  : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
-            __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
+            __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
+            __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
         } GTINTAD_b;
     };
 
@@ -4642,32 +4854,36 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTBER;          /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
 
         struct
         {
-            __IOM uint32_t BD0    : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
-            __IOM uint32_t BD1    : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
-            __IOM uint32_t BD2    : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
-            __IOM uint32_t BD3    : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
-            uint32_t              : 12;
-            __IOM uint32_t CCRA   : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
-            __IOM uint32_t CCRB   : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
-            __IOM uint32_t PR     : 2; /*!< [21..20] GTPR Buffer Operation                                            */
-            __OM uint32_t  CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
-                                        *   is read as 0.                                                             */
+            __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
+            __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+                                         *   is read as 0.                                                             */
             uint32_t             : 1;
-            __IOM uint32_t ADTTA : 2;  /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDA : 1;  /*!< [26..26] GTADTRA Double Buffer Operation                                  */
+            __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
             uint32_t             : 1;
-            __IOM uint32_t ADTTB : 2;  /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDB : 1;  /*!< [30..30] GTADTRB Double Buffer Operation                                  */
+            __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
             uint32_t             : 1;
         } GTBER_b;
     };
@@ -4891,7 +5107,126 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             uint32_t            : 31;
         } GTSOTR_b;
     };
-    __IM uint32_t RESERVED[5];
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
 
     union
     {
@@ -4925,7 +5260,7 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             uint32_t            : 4;
         } GTPC_b;
     };
-    __IM uint32_t RESERVED1[4];
+    __IM uint32_t RESERVED[4];
 
     union
     {
@@ -4967,17 +5302,137 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
         {
             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 4;
             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
-            uint32_t             : 7;
+            __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
+            uint32_t             : 6;
             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
-            uint32_t             : 7;
+            __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
+            uint32_t             : 6;
         } GTSECR_b;
     };
-} R_GPT0_Type;                         /*!< Size = 216 (0xd8)                                                         */
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
+            __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
+                                        *   Disable                                                                   */
+            uint32_t             : 2;
+            __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t             : 1;
+            __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
+                                        *   Transfer Disable                                                          */
+            uint32_t             : 2;
+            __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
+            __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
+            __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
+            __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
+            uint32_t             : 2;
+        } GTBER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
+
+        struct
+        {
+            __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
+            uint32_t              : 11;
+            __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
+            uint32_t              : 11;
+        } GTOLBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
+                                        *                  Capture Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
+            __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
+                                        *   Other Channel GTCCRb Input Capture Source Enable                          */
+            __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
+        } GTICCR_b;
+    };
+} R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_OPS                                         ================ */
@@ -8401,8 +8856,18 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } IICCKDIVCR_b;
         };
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint16_t RESERVED21;
+
+    union
+    {
+        __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
+
+        struct
+        {
+            __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
+            uint8_t                : 5;
+        } I3CCKDIVCR_b;
+    };
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -8529,8 +8994,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
         } I3CCKCR_b;
     };
-    __IM uint16_t RESERVED22;
-    __IM uint32_t RESERVED23[3];
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
 
     union
     {
@@ -8544,8 +9009,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                 : 29;
         } SNZREQCR1_b;
     };
-    __IM uint32_t RESERVED24;
-    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -8560,7 +9025,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
         } SNZCR_b;
     };
-    __IM uint8_t RESERVED26;
+    __IM uint8_t RESERVED25;
 
     union
     {
@@ -8590,7 +9055,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } SNZEDCR1_b;
     };
-    __IM uint16_t RESERVED27;
+    __IM uint16_t RESERVED26;
 
     union
     {
@@ -8633,7 +9098,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 1;
         } SNZREQCR_b;
     };
-    __IM uint16_t RESERVED28;
+    __IM uint16_t RESERVED27;
 
     union
     {
@@ -8671,7 +9136,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 3;
         } OPCCR_b;
     };
-    __IM uint8_t RESERVED29;
+    __IM uint8_t RESERVED28;
 
     union
     {
@@ -8683,7 +9148,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } MOSCWTCR_b;
     };
-    __IM uint8_t RESERVED30[2];
+    __IM uint8_t RESERVED29[2];
 
     union
     {
@@ -8696,7 +9161,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t : 5;
         } HOCOWTCR_b;
     };
-    __IM uint16_t RESERVED31[2];
+    __IM uint16_t RESERVED30[2];
 
     union
     {
@@ -8710,8 +9175,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 3;
         } SOPCCR_b;
     };
-    __IM uint8_t  RESERVED32;
-    __IM uint32_t RESERVED33[5];
+    __IM uint8_t  RESERVED31;
+    __IM uint32_t RESERVED32[5];
 
     union
     {
@@ -8745,8 +9210,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
         } RSTSR1_b;
     };
-    __IM uint16_t RESERVED34;
-    __IM uint32_t RESERVED35[3];
+    __IM uint16_t RESERVED33;
+    __IM uint32_t RESERVED34[3];
 
     union
     {
@@ -8772,8 +9237,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
         } SDADCCKCR_b;
     };
-    __IM uint16_t RESERVED36;
-    __IM uint32_t RESERVED37[3];
+    __IM uint16_t RESERVED35;
+    __IM uint32_t RESERVED36[3];
 
     union
     {
@@ -8828,7 +9293,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t          : 6;
         } LVD2SR_b;
     };
-    __IM uint32_t RESERVED38[183];
+    __IM uint32_t RESERVED37[183];
 
     union
     {
@@ -8856,7 +9321,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 14;
         } CGFSAR_b;
     };
-    __IM uint32_t RESERVED39;
+    __IM uint32_t RESERVED38;
 
     union
     {
@@ -8925,7 +9390,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 8;
         } BBFSAR_b;
     };
-    __IM uint32_t RESERVED40[3];
+    __IM uint32_t RESERVED39[3];
 
     union
     {
@@ -8987,8 +9452,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 4;
         } DPFSAR_b;
     };
-    __IM uint32_t RESERVED41[6];
-    __IM uint16_t RESERVED42;
+    __IM uint32_t RESERVED40[6];
+    __IM uint16_t RESERVED41;
 
     union
     {
@@ -9206,7 +9671,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 3;
         } DPSIEGR2_b;
     };
-    __IM uint8_t RESERVED43;
+    __IM uint8_t RESERVED42;
 
     union
     {
@@ -9264,7 +9729,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } RSTSR2_b;
     };
-    __IM uint8_t RESERVED44;
+    __IM uint8_t RESERVED43;
 
     union
     {
@@ -9281,7 +9746,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                           *   Enable                                                                    */
         } MOMCR_b;
     };
-    __IM uint16_t RESERVED45;
+    __IM uint16_t RESERVED44;
 
     union
     {
@@ -9351,7 +9816,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } LVD2CMPCR_b;
         };
     };
-    __IM uint8_t RESERVED46;
+    __IM uint8_t RESERVED45;
 
     union
     {
@@ -9384,7 +9849,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
         } LVD2CR0_b;
     };
-    __IM uint8_t RESERVED47;
+    __IM uint8_t RESERVED46;
 
     union
     {
@@ -9419,7 +9884,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 7;
         } VBTCR1_b;
     };
-    __IM uint32_t RESERVED48[8];
+    __IM uint32_t RESERVED47[8];
 
     union
     {
@@ -9462,7 +9927,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 6;
         } VCCSEL_b;
     };
-    __IM uint16_t RESERVED49;
+    __IM uint16_t RESERVED48;
 
     union
     {
@@ -9474,9 +9939,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } PL2LDOSCR_b;
     };
-    __IM uint8_t  RESERVED50;
-    __IM uint16_t RESERVED51;
-    __IM uint32_t RESERVED52[14];
+    __IM uint8_t  RESERVED49;
+    __IM uint16_t RESERVED50;
+    __IM uint32_t RESERVED51[14];
 
     union
     {
@@ -9499,8 +9964,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 6;
         } SOMCR_b;
     };
-    __IM uint16_t RESERVED53;
-    __IM uint32_t RESERVED54[3];
+    __IM uint16_t RESERVED52;
+    __IM uint32_t RESERVED53[3];
 
     union
     {
@@ -9512,7 +9977,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 7;
         } LOCOCR_b;
     };
-    __IM uint8_t RESERVED55;
+    __IM uint8_t RESERVED54;
 
     union
     {
@@ -9527,8 +9992,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                          *   trimming bits                                                             */
         } LOCOUTCR_b;
     };
-    __IM uint8_t  RESERVED56;
-    __IM uint32_t RESERVED57[7];
+    __IM uint8_t  RESERVED55;
+    __IM uint32_t RESERVED56[7];
 
     union
     {
@@ -9567,7 +10032,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 7;
         } VBTCMPCR_b;
     };
-    __IM uint8_t RESERVED58;
+    __IM uint8_t RESERVED57;
 
     union
     {
@@ -9581,7 +10046,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                  : 6;
         } VBTLVDICR_b;
     };
-    __IM uint8_t RESERVED59;
+    __IM uint8_t RESERVED58;
 
     union
     {
@@ -9593,7 +10058,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } VBTWCTLR_b;
     };
-    __IM uint8_t RESERVED60;
+    __IM uint8_t RESERVED59;
 
     union
     {
@@ -9728,9 +10193,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } VBTBER_b;
     };
-    __IM uint8_t  RESERVED61;
-    __IM uint16_t RESERVED62;
-    __IM uint32_t RESERVED63[15];
+    __IM uint8_t  RESERVED60;
+    __IM uint16_t RESERVED61;
+    __IM uint32_t RESERVED62[15];
 
     union
     {
@@ -9858,6 +10323,23 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
     __IM uint16_t RESERVED3;
 } R_WDT_Type;                          /*!< Size = 12 (0xc)                                                           */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
+ */
+
+typedef struct                          /*!< (@ 0x40084000) R_AGTX0 Structure                                          */
+{
+    union
+    {
+        __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
+        __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
+    };
+} R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_peripherals */
 
 /* =========================================================================================================================== */
@@ -9871,12 +10353,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_ACMPLP_BASE       0x40085E00UL
  #define R_ADC0_BASE         0x4005C000UL
  #define R_ADC1_BASE         0x4005C200UL
- #define R_AGT0_BASE         0x40084000UL
- #define R_AGT1_BASE         0x40084100UL
- #define R_AGT2_BASE         0x40084200UL
- #define R_AGT3_BASE         0x40084300UL
- #define R_AGT4_BASE         0x40084400UL
- #define R_AGT5_BASE         0x40084500UL
  #define R_BUS_BASE          0x40003000UL
  #define R_CAC_BASE          0x40044600UL
  #define R_CRC_BASE          0x40074000UL
@@ -9948,6 +10424,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_SYSTEM_BASE       0x4001E000UL
  #define R_TSN_BASE          0x407EC000UL
  #define R_WDT_BASE          0x40044200UL
+ #define R_AGTX0_BASE        0x40084000UL
+ #define R_AGTX1_BASE        0x40084100UL
+ #define R_AGTX2_BASE        0x40084200UL
+ #define R_AGTX3_BASE        0x40084300UL
+ #define R_AGTX4_BASE        0x40084400UL
+ #define R_AGTX5_BASE        0x40084500UL
+ #define R_AGTX6_BASE        0x40084600UL
+ #define R_AGTX7_BASE        0x40084700UL
+ #define R_AGTX8_BASE        0x40084800UL
+ #define R_AGTX9_BASE        0x40084900UL
 
 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
 
@@ -9962,12 +10448,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_ACMPLP       ((R_ACMPLP_Type *) R_ACMPLP_BASE)
  #define R_ADC0         ((R_ADC0_Type *) R_ADC0_BASE)
  #define R_ADC1         ((R_ADC0_Type *) R_ADC1_BASE)
- #define R_AGT0         ((R_AGT0_Type *) R_AGT0_BASE)
- #define R_AGT1         ((R_AGT0_Type *) R_AGT1_BASE)
- #define R_AGT2         ((R_AGT0_Type *) R_AGT2_BASE)
- #define R_AGT3         ((R_AGT0_Type *) R_AGT3_BASE)
- #define R_AGT4         ((R_AGT0_Type *) R_AGT4_BASE)
- #define R_AGT5         ((R_AGT0_Type *) R_AGT5_BASE)
  #define R_BUS          ((R_BUS_Type *) R_BUS_BASE)
  #define R_CAC          ((R_CAC_Type *) R_CAC_BASE)
  #define R_CRC          ((R_CRC_Type *) R_CRC_BASE)
@@ -10039,6 +10519,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_SYSTEM       ((R_SYSTEM_Type *) R_SYSTEM_BASE)
  #define R_TSN          ((R_TSN_Type *) R_TSN_BASE)
  #define R_WDT          ((R_WDT_Type *) R_WDT_BASE)
+ #define R_AGTX0        ((R_AGTX0_Type *) R_AGTX0_BASE)
+ #define R_AGTX1        ((R_AGTX0_Type *) R_AGTX1_BASE)
+ #define R_AGTX2        ((R_AGTX0_Type *) R_AGTX2_BASE)
+ #define R_AGTX3        ((R_AGTX0_Type *) R_AGTX3_BASE)
+ #define R_AGTX4        ((R_AGTX0_Type *) R_AGTX4_BASE)
+ #define R_AGTX5        ((R_AGTX0_Type *) R_AGTX5_BASE)
+ #define R_AGTX6        ((R_AGTX0_Type *) R_AGTX6_BASE)
+ #define R_AGTX7        ((R_AGTX0_Type *) R_AGTX7_BASE)
+ #define R_AGTX8        ((R_AGTX0_Type *) R_AGTX8_BASE)
+ #define R_AGTX9        ((R_AGTX0_Type *) R_AGTX9_BASE)
 
 /** @} */ /* End of group Device_Peripheral_declaration */
 
@@ -10370,6 +10860,8 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 /* =========================================================================================================================== */
 
 /* =========================================================  RTCCR  ========================================================= */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
@@ -10421,6 +10913,101 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_RTC_CP_RMON_MON1_Pos        (0UL)    /*!< MON1 (Bit 0)                                          */
  #define R_RTC_CP_RMON_MON1_Msk        (0xfUL)  /*!< MON1 (Bitfield-Mask: 0x0f)                            */
 
+/* =========================================================================================================================== */
+/* ================                                           CTRL                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  AGTCR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AGTMR1  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
+/* ========================================================  AGTMR2  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
+/* =====================================================  AGTIOSEL_ALT  ====================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+/* ========================================================  AGTIOC  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AGTISR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AGTCMSR  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
+/* =======================================================  AGTIOSEL  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT16                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT32                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
+
 /** @} */ /* End of group PosMask_clusters */
 
 /* =========================================================================================================================== */
@@ -10980,77 +11567,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_ADC0_ADREFMON_MONSEL_Pos         (16UL)      /*!< MONSEL (Bit 16)                                       */
  #define R_ADC0_ADREFMON_MONSEL_Msk         (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f)                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/* ==========================================================  AGT  ========================================================== */
- #define R_AGT0_AGT_AGT_Pos           (0UL)      /*!< AGT (Bit 0)                                           */
- #define R_AGT0_AGT_AGT_Msk           (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
-/* ========================================================  AGTCMA  ========================================================= */
- #define R_AGT0_AGTCMA_AGTCMA_Pos     (0UL)      /*!< AGTCMA (Bit 0)                                        */
- #define R_AGT0_AGTCMA_AGTCMA_Msk     (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
-/* ========================================================  AGTCMB  ========================================================= */
- #define R_AGT0_AGTCMB_AGTCMB_Pos     (0UL)      /*!< AGTCMB (Bit 0)                                        */
- #define R_AGT0_AGTCMB_AGTCMB_Msk     (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
-/* =========================================================  AGTCR  ========================================================= */
- #define R_AGT0_AGTCR_TCMBF_Pos       (7UL)      /*!< TCMBF (Bit 7)                                         */
- #define R_AGT0_AGTCR_TCMBF_Msk       (0x80UL)   /*!< TCMBF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCMAF_Pos       (6UL)      /*!< TCMAF (Bit 6)                                         */
- #define R_AGT0_AGTCR_TCMAF_Msk       (0x40UL)   /*!< TCMAF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TUNDF_Pos       (5UL)      /*!< TUNDF (Bit 5)                                         */
- #define R_AGT0_AGTCR_TUNDF_Msk       (0x20UL)   /*!< TUNDF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TEDGF_Pos       (4UL)      /*!< TEDGF (Bit 4)                                         */
- #define R_AGT0_AGTCR_TEDGF_Msk       (0x10UL)   /*!< TEDGF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTOP_Pos       (2UL)      /*!< TSTOP (Bit 2)                                         */
- #define R_AGT0_AGTCR_TSTOP_Msk       (0x4UL)    /*!< TSTOP (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCSTF_Pos       (1UL)      /*!< TCSTF (Bit 1)                                         */
- #define R_AGT0_AGTCR_TCSTF_Msk       (0x2UL)    /*!< TCSTF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTART_Pos      (0UL)      /*!< TSTART (Bit 0)                                        */
- #define R_AGT0_AGTCR_TSTART_Msk      (0x1UL)    /*!< TSTART (Bitfield-Mask: 0x01)                          */
-/* ========================================================  AGTMR1  ========================================================= */
- #define R_AGT0_AGTMR1_TCK_Pos        (4UL)      /*!< TCK (Bit 4)                                           */
- #define R_AGT0_AGTMR1_TCK_Msk        (0x70UL)   /*!< TCK (Bitfield-Mask: 0x07)                             */
- #define R_AGT0_AGTMR1_TEDGPL_Pos     (3UL)      /*!< TEDGPL (Bit 3)                                        */
- #define R_AGT0_AGTMR1_TEDGPL_Msk     (0x8UL)    /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTMR1_TMOD_Pos       (0UL)      /*!< TMOD (Bit 0)                                          */
- #define R_AGT0_AGTMR1_TMOD_Msk       (0x7UL)    /*!< TMOD (Bitfield-Mask: 0x07)                            */
-/* ========================================================  AGTMR2  ========================================================= */
- #define R_AGT0_AGTMR2_LPM_Pos        (7UL)      /*!< LPM (Bit 7)                                           */
- #define R_AGT0_AGTMR2_LPM_Msk        (0x80UL)   /*!< LPM (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTMR2_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
- #define R_AGT0_AGTMR2_CKS_Msk        (0x7UL)    /*!< CKS (Bitfield-Mask: 0x07)                             */
-/* ========================================================  AGTIOC  ========================================================= */
- #define R_AGT0_AGTIOC_TIOGT_Pos      (6UL)      /*!< TIOGT (Bit 6)                                         */
- #define R_AGT0_AGTIOC_TIOGT_Msk      (0xc0UL)   /*!< TIOGT (Bitfield-Mask: 0x03)                           */
- #define R_AGT0_AGTIOC_TIPF_Pos       (4UL)      /*!< TIPF (Bit 4)                                          */
- #define R_AGT0_AGTIOC_TIPF_Msk       (0x30UL)   /*!< TIPF (Bitfield-Mask: 0x03)                            */
- #define R_AGT0_AGTIOC_TOE_Pos        (2UL)      /*!< TOE (Bit 2)                                           */
- #define R_AGT0_AGTIOC_TOE_Msk        (0x4UL)    /*!< TOE (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTIOC_TEDGSEL_Pos    (0UL)      /*!< TEDGSEL (Bit 0)                                       */
- #define R_AGT0_AGTIOC_TEDGSEL_Msk    (0x1UL)    /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
-/* ========================================================  AGTISR  ========================================================= */
- #define R_AGT0_AGTISR_EEPS_Pos       (2UL)      /*!< EEPS (Bit 2)                                          */
- #define R_AGT0_AGTISR_EEPS_Msk       (0x4UL)    /*!< EEPS (Bitfield-Mask: 0x01)                            */
-/* ========================================================  AGTCMSR  ======================================================== */
- #define R_AGT0_AGTCMSR_TOPOLB_Pos    (6UL)      /*!< TOPOLB (Bit 6)                                        */
- #define R_AGT0_AGTCMSR_TOPOLB_Msk    (0x40UL)   /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEB_Pos      (5UL)      /*!< TOEB (Bit 5)                                          */
- #define R_AGT0_AGTCMSR_TOEB_Msk      (0x20UL)   /*!< TOEB (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEB_Pos     (4UL)      /*!< TCMEB (Bit 4)                                         */
- #define R_AGT0_AGTCMSR_TCMEB_Msk     (0x10UL)   /*!< TCMEB (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCMSR_TOPOLA_Pos    (2UL)      /*!< TOPOLA (Bit 2)                                        */
- #define R_AGT0_AGTCMSR_TOPOLA_Msk    (0x4UL)    /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEA_Pos      (1UL)      /*!< TOEA (Bit 1)                                          */
- #define R_AGT0_AGTCMSR_TOEA_Msk      (0x2UL)    /*!< TOEA (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEA_Pos     (0UL)      /*!< TCMEA (Bit 0)                                         */
- #define R_AGT0_AGTCMSR_TCMEA_Msk     (0x1UL)    /*!< TCMEA (Bitfield-Mask: 0x01)                           */
-/* =======================================================  AGTIOSEL  ======================================================== */
- #define R_AGT0_AGTIOSEL_TIES_Pos     (4UL)      /*!< TIES (Bit 4)                                          */
- #define R_AGT0_AGTIOSEL_TIES_Msk     (0x10UL)   /*!< TIES (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTIOSEL_SEL_Pos      (0UL)      /*!< SEL (Bit 0)                                           */
- #define R_AGT0_AGTIOSEL_SEL_Msk      (0x3UL)    /*!< SEL (Bitfield-Mask: 0x03)                             */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -12023,10 +12539,22 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
 /* =========================================================  GTCR  ========================================================== */
+ #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
+ #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTCR_TPCS_Pos              (24UL)         /*!< TPCS (Bit 24)                                         */
  #define R_GPT0_GTCR_TPCS_Msk              (0x7000000UL)  /*!< TPCS (Bitfield-Mask: 0x07)                            */
  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
- #define R_GPT0_GTCR_MD_Msk                (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
+ #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
+ #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
+ #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
+ #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
 /* =======================================================  GTUDDTYC  ======================================================== */
@@ -12084,6 +12612,8 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
 /* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
+ #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
@@ -12092,8 +12622,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
- #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
- #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
+ #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
+ #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
+ #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
 /* =========================================================  GTST  ========================================================== */
  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
@@ -12150,6 +12688,8 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
+ #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
@@ -12239,6 +12779,67 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 /* ========================================================  GTSOTR  ========================================================= */
  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
 /* ========================================================  GTICLF  ========================================================= */
  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
@@ -12281,14 +12882,113 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
+ #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
+ #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTBER2  ========================================================= */
+ #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
+ #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
+ #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
+ #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
+ #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
+ #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
+ #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
+ #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
+ #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
+ #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
+ #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
+ #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
+ #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
+ #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
+ #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
+ #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
+ #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
+ #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
+ #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
+ #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTOLBR  ========================================================= */
+ #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
+ #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
+ #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
+ #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  GTICCR  ========================================================= */
+ #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
+ #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
+ #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
+ #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
+ #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
+ #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
+ #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
+ #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
+ #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
+ #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
+ #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
+ #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
+ #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
+ #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
+ #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
+ #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
+ #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
+ #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
+ #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
+ #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
+ #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_OPS                                         ================ */
@@ -14468,6 +15168,9 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 /* ======================================================  CECCKDIVCR  ======================================================= */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  I3CCKDIVCR  ======================================================= */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
 /* ======================================================  IICCKDIVCR  ======================================================= */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
@@ -14720,6 +15423,10 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_WDT_WDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
  #define R_WDT_WDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
 /** @} */ /* End of group PosMask_peripherals */
 
  #ifdef __cplusplus
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h
index ea320beb6..858bb5cc2 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h
@@ -723,6 +723,213 @@ typedef struct
     __IOM uint16_t PMSAR;              /*!< (@ 0x00000000) Port Security Attribution Register                         */
 } R_PMISC_PMSAR_Type;                  /*!< Size = 2 (0x2)                                                            */
 
+/**
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
+            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
+            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
+            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
+            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
+            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
+        } AGTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
+            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
+            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
+            uint8_t              : 1;
+        } AGTMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+                                        *   ratio                                                                     */
+            uint8_t           : 4;
+            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
+        } AGTMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+                                        *   mode.                                                                     */
+            uint8_t             : 1;
+            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
+            uint8_t             : 1;
+            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
+            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
+        } AGTIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
+            uint8_t            : 5;
+        } AGTISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
+
+        struct
+        {
+            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
+            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
+            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
+            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
+            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
+            uint8_t              : 1;
+        } AGTCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_b;
+    };
+} R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
+
+        struct
+        {
+            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IM uint16_t                 RESERVED;
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
+} R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
+
+        struct
+        {
+            __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
+} R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_clusters */
 
 /* =========================================================================================================================== */
@@ -1015,16 +1222,17 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
 
     union
     {
-        __IM uint16_t ADDR[28];        /*!< (@ 0x00000020) A/D Data Register                                          */
+        __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
 
         struct
         {
             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
                                         *   storing the result of A/D conversion.                                     */
-        } ADDR_b[28];
+        } ADDR_b[29];
     };
-    __IM uint32_t RESERVED1[2];
-    __IM uint16_t RESERVED2;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+    __IM uint16_t RESERVED3;
 
     union
     {
@@ -1217,7 +1425,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint16_t                : 3;
         } ADSWTSTR2_b;
     };
-    __IM uint16_t RESERVED3;
+    __IM uint16_t RESERVED4;
 
     union
     {
@@ -1279,7 +1487,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 6;
         } ADACSR_b;
     };
-    __IM uint8_t RESERVED4;
+    __IM uint8_t RESERVED5;
 
     union
     {
@@ -1349,7 +1557,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
         } ADSER_b;
     };
-    __IM uint8_t RESERVED5;
+    __IM uint8_t RESERVED6;
 
     union
     {
@@ -1365,7 +1573,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
         } ADHVREFCNT_b;
     };
-    __IM uint8_t RESERVED6;
+    __IM uint8_t RESERVED7;
 
     union
     {
@@ -1383,8 +1591,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t              : 2;
         } ADWINMON_b;
     };
-    __IM uint8_t  RESERVED7;
-    __IM uint16_t RESERVED8;
+    __IM uint8_t  RESERVED8;
+    __IM uint16_t RESERVED9;
 
     union
     {
@@ -1560,7 +1768,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 6;
         } ADCMPSER_b;
     };
-    __IM uint8_t RESERVED9;
+    __IM uint8_t RESERVED10;
 
     union
     {
@@ -1575,7 +1783,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
         } ADCMPBNSR_b;
     };
-    __IM uint8_t RESERVED10;
+    __IM uint8_t RESERVED11;
 
     union
     {
@@ -1614,8 +1822,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 7;
         } ADCMPBSR_b;
     };
-    __IM uint8_t  RESERVED11;
-    __IM uint16_t RESERVED12;
+    __IM uint8_t  RESERVED12;
+    __IM uint16_t RESERVED13;
 
     union
     {
@@ -1819,7 +2027,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 7;
         } ADBUFEN_b;
     };
-    __IM uint8_t RESERVED13;
+    __IM uint8_t RESERVED14;
 
     union
     {
@@ -1833,9 +2041,9 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 3;
         } ADBUFPTR_b;
     };
-    __IM uint8_t  RESERVED14;
-    __IM uint32_t RESERVED15[2];
-    __IM uint8_t  RESERVED16;
+    __IM uint8_t  RESERVED15;
+    __IM uint32_t RESERVED16[2];
+    __IM uint8_t  RESERVED17;
 
     union
     {
@@ -1902,7 +2110,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
         } ADCALEXE_b;
     };
-    __IM uint8_t RESERVED17;
+    __IM uint8_t RESERVED18;
 
     union
     {
@@ -1919,8 +2127,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
         } VREFAMPCNT_b;
     };
-    __IM uint8_t  RESERVED18;
-    __IM uint16_t RESERVED19;
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -1942,8 +2150,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 6;
         } ADRST_b;
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint32_t RESERVED21[41];
+    __IM uint8_t  RESERVED21;
+    __IM uint32_t RESERVED22[41];
 
     union
     {
@@ -2001,7 +2209,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
         } ADPGAGS0_b;
     };
-    __IM uint32_t RESERVED22[3];
+    __IM uint32_t RESERVED23[3];
 
     union
     {
@@ -2028,7 +2236,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
         } ADPGADCR0_b;
     };
-    __IM uint16_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -2057,8 +2265,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 7;
         } ADPGADBS1_b;
     };
-    __IM uint16_t RESERVED24;
-    __IM uint32_t RESERVED25[10];
+    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED26[10];
 
     union
     {
@@ -2074,154 +2282,6 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
     };
 } R_ADC0_Type;                         /*!< Size = 484 (0x1e4)                                                        */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGTW0                                          ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Asynchronous General Purpose Timer (R_AGTW0)
- */
-
-typedef struct                         /*!< (@ 0x40084000) R_AGTW0 Structure                                          */
-{
-    union
-    {
-        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
-
-        struct
-        {
-            __IOM uint32_t AGT : 32;   /*!< [31..0] 16bit counter and reload registerNOTE : When 1 is written
-                                        *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
-                                        *   is forcibly stopped and set to FFFFH.                                     */
-        } AGT_b;
-    };
-
-    union
-    {
-        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
-
-        struct
-        {
-            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCRn register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMA_b;
-    };
-
-    union
-    {
-        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
-
-        struct
-        {
-            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCR register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMB_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTCR;           /*!< (@ 0x0000000C) AGT Control Register                                       */
-
-        struct
-        {
-            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
-            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
-            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
-            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
-            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
-            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
-        } AGTCR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR1;          /*!< (@ 0x0000000D) AGT Mode Register 1                                        */
-
-        struct
-        {
-            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
-            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
-            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
-            uint8_t              : 1;
-        } AGTMR1_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000E) AGT Mode Register 2                                        */
-
-        struct
-        {
-            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
-                                        *   ratio                                                                     */
-            uint8_t           : 4;
-            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
-        } AGTMR2_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x0000000F) AGT Pin Select Register                                    */
-
-        struct
-        {
-            uint8_t            : 4;
-            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
-            uint8_t            : 3;
-        } AGTIOSEL_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000010) AGT I/O Control Register                                   */
-
-        struct
-        {
-            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
-                                        *   mode.                                                                     */
-            uint8_t             : 1;
-            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
-            uint8_t             : 1;
-            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
-            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
-        } AGTIOC_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTISR;          /*!< (@ 0x00000011) AGT Event Pin Select Register                              */
-
-        struct
-        {
-            uint8_t            : 2;
-            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
-            uint8_t            : 5;
-        } AGTISR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000012) AGT Compare Match Function Select Register                 */
-
-        struct
-        {
-            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
-            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
-            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
-            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
-            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
-            uint8_t              : 1;
-        } AGTCMSR_b;
-    };
-    __IM uint8_t RESERVED;
-} R_AGTW0_Type;                        /*!< Size = 20 (0x14)                                                          */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -3258,46 +3318,99 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            uint32_t : 18;
         } GTSTR_b;
     };
 
@@ -3349,7 +3462,60 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
                                          *   1 means counter stop.                                                     */
-            uint32_t : 18;
+            __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
         } GTSTP_b;
     };
 
@@ -3373,7 +3539,24 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
-            uint32_t             : 18;
+            __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
         } GTCLR_b;
     };
 
@@ -3694,16 +3877,23 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+        __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
 
         struct
         {
-            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
-            uint32_t            : 15;
-            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
-            uint32_t            : 5;
-            __IOM uint32_t TPCS : 3;   /*!< [26..24] Timer Prescaler Select                                           */
-            uint32_t            : 5;
+            __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
+            uint32_t               : 7;
+            __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
+            __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
+            __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
+            __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
+            uint32_t               : 2;
+            __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
+            __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
+            uint32_t               : 4;
+            __IOM uint32_t TPCS    : 3; /*!< [26..24] Timer Prescaler Select                                           */
+            __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
+            uint32_t               : 3;
         } GTCR_b;
     };
 
@@ -3774,13 +3964,36 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
         struct
         {
-            uint32_t               : 24;
-            __IOM uint32_t GRP     : 2; /*!< [25..24] Output Disable Source Select                                     */
+            uint32_t            : 8;
+            __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
+            __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            uint32_t               : 4;
+            __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
             uint32_t               : 2;
-            __IOM uint32_t GRPDTE  : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
-            __IOM uint32_t GRPABH  : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable               */
-            __IOM uint32_t GRPABL  : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
-            __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
+            __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
+            __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
         } GTINTAD_b;
     };
 
@@ -3823,32 +4036,36 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTBER;          /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
 
         struct
         {
-            __IOM uint32_t BD0    : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
-            __IOM uint32_t BD1    : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
-            __IOM uint32_t BD2    : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
-            __IOM uint32_t BD3    : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
-            uint32_t              : 12;
-            __IOM uint32_t CCRA   : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
-            __IOM uint32_t CCRB   : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
-            __IOM uint32_t PR     : 2; /*!< [21..20] GTPR Buffer Operation                                            */
-            __OM uint32_t  CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
-                                        *   is read as 0.                                                             */
+            __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
+            __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+                                         *   is read as 0.                                                             */
             uint32_t             : 1;
-            __IOM uint32_t ADTTA : 2;  /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDA : 1;  /*!< [26..26] GTADTRA Double Buffer Operation                                  */
+            __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
             uint32_t             : 1;
-            __IOM uint32_t ADTTB : 2;  /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDB : 1;  /*!< [30..30] GTADTRB Double Buffer Operation                                  */
+            __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
             uint32_t             : 1;
         } GTBER_b;
     };
@@ -4072,7 +4289,126 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             uint32_t            : 31;
         } GTSOTR_b;
     };
-    __IM uint32_t RESERVED[5];
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
 
     union
     {
@@ -4106,7 +4442,7 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             uint32_t            : 4;
         } GTPC_b;
     };
-    __IM uint32_t RESERVED1[4];
+    __IM uint32_t RESERVED[4];
 
     union
     {
@@ -4148,17 +4484,137 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
         {
             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 4;
             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
-            uint32_t             : 7;
+            __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
+            uint32_t             : 6;
             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
-            uint32_t             : 7;
+            __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
+            uint32_t             : 6;
         } GTSECR_b;
     };
-} R_GPT0_Type;                         /*!< Size = 216 (0xd8)                                                         */
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
+            __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
+                                        *   Disable                                                                   */
+            uint32_t             : 2;
+            __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t             : 1;
+            __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
+                                        *   Transfer Disable                                                          */
+            uint32_t             : 2;
+            __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
+            __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
+            __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
+            __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
+            uint32_t             : 2;
+        } GTBER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
+
+        struct
+        {
+            __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
+            uint32_t              : 11;
+            __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
+            uint32_t              : 11;
+        } GTOLBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
+                                        *                  Capture Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
+            __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
+                                        *   Other Channel GTCCRb Input Capture Source Enable                          */
+            __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
+        } GTICCR_b;
+    };
+} R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_OPS                                         ================ */
@@ -8219,8 +8675,18 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } IICCKDIVCR_b;
         };
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint16_t RESERVED21;
+
+    union
+    {
+        __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
+
+        struct
+        {
+            __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
+            uint8_t                : 5;
+        } I3CCKDIVCR_b;
+    };
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -8347,8 +8813,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
         } I3CCKCR_b;
     };
-    __IM uint16_t RESERVED22;
-    __IM uint32_t RESERVED23[3];
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
 
     union
     {
@@ -8362,8 +8828,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                 : 29;
         } SNZREQCR1_b;
     };
-    __IM uint32_t RESERVED24;
-    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -8378,7 +8844,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
         } SNZCR_b;
     };
-    __IM uint8_t RESERVED26;
+    __IM uint8_t RESERVED25;
 
     union
     {
@@ -8408,7 +8874,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } SNZEDCR1_b;
     };
-    __IM uint16_t RESERVED27;
+    __IM uint16_t RESERVED26;
 
     union
     {
@@ -8451,7 +8917,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 1;
         } SNZREQCR_b;
     };
-    __IM uint16_t RESERVED28;
+    __IM uint16_t RESERVED27;
 
     union
     {
@@ -8489,7 +8955,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 3;
         } OPCCR_b;
     };
-    __IM uint8_t RESERVED29;
+    __IM uint8_t RESERVED28;
 
     union
     {
@@ -8501,7 +8967,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } MOSCWTCR_b;
     };
-    __IM uint8_t RESERVED30[2];
+    __IM uint8_t RESERVED29[2];
 
     union
     {
@@ -8514,7 +8980,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t : 5;
         } HOCOWTCR_b;
     };
-    __IM uint16_t RESERVED31[2];
+    __IM uint16_t RESERVED30[2];
 
     union
     {
@@ -8528,8 +8994,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 3;
         } SOPCCR_b;
     };
-    __IM uint8_t  RESERVED32;
-    __IM uint32_t RESERVED33[5];
+    __IM uint8_t  RESERVED31;
+    __IM uint32_t RESERVED32[5];
 
     union
     {
@@ -8563,8 +9029,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
         } RSTSR1_b;
     };
-    __IM uint16_t RESERVED34;
-    __IM uint32_t RESERVED35[3];
+    __IM uint16_t RESERVED33;
+    __IM uint32_t RESERVED34[3];
 
     union
     {
@@ -8590,8 +9056,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
         } SDADCCKCR_b;
     };
-    __IM uint16_t RESERVED36;
-    __IM uint32_t RESERVED37[3];
+    __IM uint16_t RESERVED35;
+    __IM uint32_t RESERVED36[3];
 
     union
     {
@@ -8646,7 +9112,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t          : 6;
         } LVD2SR_b;
     };
-    __IM uint32_t RESERVED38[183];
+    __IM uint32_t RESERVED37[183];
 
     union
     {
@@ -8674,7 +9140,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 14;
         } CGFSAR_b;
     };
-    __IM uint32_t RESERVED39;
+    __IM uint32_t RESERVED38;
 
     union
     {
@@ -8743,7 +9209,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 8;
         } BBFSAR_b;
     };
-    __IM uint32_t RESERVED40[3];
+    __IM uint32_t RESERVED39[3];
 
     union
     {
@@ -8805,8 +9271,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 4;
         } DPFSAR_b;
     };
-    __IM uint32_t RESERVED41[6];
-    __IM uint16_t RESERVED42;
+    __IM uint32_t RESERVED40[6];
+    __IM uint16_t RESERVED41;
 
     union
     {
@@ -9024,7 +9490,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 3;
         } DPSIEGR2_b;
     };
-    __IM uint8_t RESERVED43;
+    __IM uint8_t RESERVED42;
 
     union
     {
@@ -9082,7 +9548,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } RSTSR2_b;
     };
-    __IM uint8_t RESERVED44;
+    __IM uint8_t RESERVED43;
 
     union
     {
@@ -9099,7 +9565,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                           *   Enable                                                                    */
         } MOMCR_b;
     };
-    __IM uint16_t RESERVED45;
+    __IM uint16_t RESERVED44;
 
     union
     {
@@ -9169,7 +9635,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } LVD2CMPCR_b;
         };
     };
-    __IM uint8_t RESERVED46;
+    __IM uint8_t RESERVED45;
 
     union
     {
@@ -9202,7 +9668,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
         } LVD2CR0_b;
     };
-    __IM uint8_t RESERVED47;
+    __IM uint8_t RESERVED46;
 
     union
     {
@@ -9237,7 +9703,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 7;
         } VBTCR1_b;
     };
-    __IM uint32_t RESERVED48[8];
+    __IM uint32_t RESERVED47[8];
 
     union
     {
@@ -9280,7 +9746,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 6;
         } VCCSEL_b;
     };
-    __IM uint16_t RESERVED49;
+    __IM uint16_t RESERVED48;
 
     union
     {
@@ -9292,9 +9758,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } PL2LDOSCR_b;
     };
-    __IM uint8_t  RESERVED50;
-    __IM uint16_t RESERVED51;
-    __IM uint32_t RESERVED52[14];
+    __IM uint8_t  RESERVED49;
+    __IM uint16_t RESERVED50;
+    __IM uint32_t RESERVED51[14];
 
     union
     {
@@ -9317,8 +9783,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 6;
         } SOMCR_b;
     };
-    __IM uint16_t RESERVED53;
-    __IM uint32_t RESERVED54[3];
+    __IM uint16_t RESERVED52;
+    __IM uint32_t RESERVED53[3];
 
     union
     {
@@ -9330,7 +9796,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 7;
         } LOCOCR_b;
     };
-    __IM uint8_t RESERVED55;
+    __IM uint8_t RESERVED54;
 
     union
     {
@@ -9345,8 +9811,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                          *   trimming bits                                                             */
         } LOCOUTCR_b;
     };
-    __IM uint8_t  RESERVED56;
-    __IM uint32_t RESERVED57[7];
+    __IM uint8_t  RESERVED55;
+    __IM uint32_t RESERVED56[7];
 
     union
     {
@@ -9385,7 +9851,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 7;
         } VBTCMPCR_b;
     };
-    __IM uint8_t RESERVED58;
+    __IM uint8_t RESERVED57;
 
     union
     {
@@ -9399,7 +9865,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                  : 6;
         } VBTLVDICR_b;
     };
-    __IM uint8_t RESERVED59;
+    __IM uint8_t RESERVED58;
 
     union
     {
@@ -9411,7 +9877,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } VBTWCTLR_b;
     };
-    __IM uint8_t RESERVED60;
+    __IM uint8_t RESERVED59;
 
     union
     {
@@ -9546,9 +10012,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } VBTBER_b;
     };
-    __IM uint8_t  RESERVED61;
-    __IM uint16_t RESERVED62;
-    __IM uint32_t RESERVED63[15];
+    __IM uint8_t  RESERVED60;
+    __IM uint16_t RESERVED61;
+    __IM uint32_t RESERVED62[15];
 
     union
     {
@@ -9676,6 +10142,23 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
     __IM uint16_t RESERVED3;
 } R_WDT_Type;                          /*!< Size = 12 (0xc)                                                           */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
+ */
+
+typedef struct                          /*!< (@ 0x40084000) R_AGTX0 Structure                                          */
+{
+    union
+    {
+        __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
+        __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
+    };
+} R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_peripherals */
 
 /* =========================================================================================================================== */
@@ -9688,8 +10171,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 
  #define R_ADC0_BASE         0x4005C000UL
  #define R_ADC1_BASE         0x4005C200UL
- #define R_AGTW0_BASE        0x40084000UL
- #define R_AGTW1_BASE        0x40084100UL
  #define R_BUS_BASE          0x40003000UL
  #define R_CAC_BASE          0x40044600UL
  #define R_CRC_BASE          0x40074000UL
@@ -9760,6 +10241,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_SYSTEM_BASE       0x4001E000UL
  #define R_TSN_BASE          0x407EC000UL
  #define R_WDT_BASE          0x40044200UL
+ #define R_AGTX0_BASE        0x40084000UL
+ #define R_AGTX1_BASE        0x40084100UL
+ #define R_AGTX2_BASE        0x40084200UL
+ #define R_AGTX3_BASE        0x40084300UL
+ #define R_AGTX4_BASE        0x40084400UL
+ #define R_AGTX5_BASE        0x40084500UL
+ #define R_AGTX6_BASE        0x40084600UL
+ #define R_AGTX7_BASE        0x40084700UL
+ #define R_AGTX8_BASE        0x40084800UL
+ #define R_AGTX9_BASE        0x40084900UL
 
 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
 
@@ -9773,8 +10264,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 
  #define R_ADC0         ((R_ADC0_Type *) R_ADC0_BASE)
  #define R_ADC1         ((R_ADC0_Type *) R_ADC1_BASE)
- #define R_AGTW0        ((R_AGTW0_Type *) R_AGTW0_BASE)
- #define R_AGTW1        ((R_AGTW0_Type *) R_AGTW1_BASE)
  #define R_BUS          ((R_BUS_Type *) R_BUS_BASE)
  #define R_CAC          ((R_CAC_Type *) R_CAC_BASE)
  #define R_CRC          ((R_CRC_Type *) R_CRC_BASE)
@@ -9845,6 +10334,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_SYSTEM       ((R_SYSTEM_Type *) R_SYSTEM_BASE)
  #define R_TSN          ((R_TSN_Type *) R_TSN_BASE)
  #define R_WDT          ((R_WDT_Type *) R_WDT_BASE)
+ #define R_AGTX0        ((R_AGTX0_Type *) R_AGTX0_BASE)
+ #define R_AGTX1        ((R_AGTX0_Type *) R_AGTX1_BASE)
+ #define R_AGTX2        ((R_AGTX0_Type *) R_AGTX2_BASE)
+ #define R_AGTX3        ((R_AGTX0_Type *) R_AGTX3_BASE)
+ #define R_AGTX4        ((R_AGTX0_Type *) R_AGTX4_BASE)
+ #define R_AGTX5        ((R_AGTX0_Type *) R_AGTX5_BASE)
+ #define R_AGTX6        ((R_AGTX0_Type *) R_AGTX6_BASE)
+ #define R_AGTX7        ((R_AGTX0_Type *) R_AGTX7_BASE)
+ #define R_AGTX8        ((R_AGTX0_Type *) R_AGTX8_BASE)
+ #define R_AGTX9        ((R_AGTX0_Type *) R_AGTX9_BASE)
 
 /** @} */ /* End of group Device_Peripheral_declaration */
 
@@ -10171,6 +10670,101 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 
 /* =========================================================  PMSAR  ========================================================= */
 
+/* =========================================================================================================================== */
+/* ================                                           CTRL                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  AGTCR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AGTMR1  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
+/* ========================================================  AGTMR2  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
+/* =====================================================  AGTIOSEL_ALT  ====================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+/* ========================================================  AGTIOC  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AGTISR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AGTCMSR  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
+/* =======================================================  AGTIOSEL  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT16                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT32                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
+
 /** @} */ /* End of group PosMask_clusters */
 
 /* =========================================================================================================================== */
@@ -10672,75 +11266,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_ADC0_ADREFMON_MONSEL_Pos         (16UL)      /*!< MONSEL (Bit 16)                                       */
  #define R_ADC0_ADREFMON_MONSEL_Msk         (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f)                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGTW0                                          ================ */
-/* =========================================================================================================================== */
-
-/* ==========================================================  AGT  ========================================================== */
- #define R_AGTW0_AGT_AGT_Pos           (0UL)          /*!< AGT (Bit 0)                                           */
- #define R_AGTW0_AGT_AGT_Msk           (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
-/* ========================================================  AGTCMA  ========================================================= */
- #define R_AGTW0_AGTCMA_AGTCMA_Pos     (0UL)          /*!< AGTCMA (Bit 0)                                        */
- #define R_AGTW0_AGTCMA_AGTCMA_Msk     (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
-/* ========================================================  AGTCMB  ========================================================= */
- #define R_AGTW0_AGTCMB_AGTCMB_Pos     (0UL)          /*!< AGTCMB (Bit 0)                                        */
- #define R_AGTW0_AGTCMB_AGTCMB_Msk     (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
-/* =========================================================  AGTCR  ========================================================= */
- #define R_AGTW0_AGTCR_TCMBF_Pos       (7UL)          /*!< TCMBF (Bit 7)                                         */
- #define R_AGTW0_AGTCR_TCMBF_Msk       (0x80UL)       /*!< TCMBF (Bitfield-Mask: 0x01)                           */
- #define R_AGTW0_AGTCR_TCMAF_Pos       (6UL)          /*!< TCMAF (Bit 6)                                         */
- #define R_AGTW0_AGTCR_TCMAF_Msk       (0x40UL)       /*!< TCMAF (Bitfield-Mask: 0x01)                           */
- #define R_AGTW0_AGTCR_TUNDF_Pos       (5UL)          /*!< TUNDF (Bit 5)                                         */
- #define R_AGTW0_AGTCR_TUNDF_Msk       (0x20UL)       /*!< TUNDF (Bitfield-Mask: 0x01)                           */
- #define R_AGTW0_AGTCR_TEDGF_Pos       (4UL)          /*!< TEDGF (Bit 4)                                         */
- #define R_AGTW0_AGTCR_TEDGF_Msk       (0x10UL)       /*!< TEDGF (Bitfield-Mask: 0x01)                           */
- #define R_AGTW0_AGTCR_TSTOP_Pos       (2UL)          /*!< TSTOP (Bit 2)                                         */
- #define R_AGTW0_AGTCR_TSTOP_Msk       (0x4UL)        /*!< TSTOP (Bitfield-Mask: 0x01)                           */
- #define R_AGTW0_AGTCR_TCSTF_Pos       (1UL)          /*!< TCSTF (Bit 1)                                         */
- #define R_AGTW0_AGTCR_TCSTF_Msk       (0x2UL)        /*!< TCSTF (Bitfield-Mask: 0x01)                           */
- #define R_AGTW0_AGTCR_TSTART_Pos      (0UL)          /*!< TSTART (Bit 0)                                        */
- #define R_AGTW0_AGTCR_TSTART_Msk      (0x1UL)        /*!< TSTART (Bitfield-Mask: 0x01)                          */
-/* ========================================================  AGTMR1  ========================================================= */
- #define R_AGTW0_AGTMR1_TCK_Pos        (4UL)          /*!< TCK (Bit 4)                                           */
- #define R_AGTW0_AGTMR1_TCK_Msk        (0x70UL)       /*!< TCK (Bitfield-Mask: 0x07)                             */
- #define R_AGTW0_AGTMR1_TEDGPL_Pos     (3UL)          /*!< TEDGPL (Bit 3)                                        */
- #define R_AGTW0_AGTMR1_TEDGPL_Msk     (0x8UL)        /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
- #define R_AGTW0_AGTMR1_TMOD_Pos       (0UL)          /*!< TMOD (Bit 0)                                          */
- #define R_AGTW0_AGTMR1_TMOD_Msk       (0x7UL)        /*!< TMOD (Bitfield-Mask: 0x07)                            */
-/* ========================================================  AGTMR2  ========================================================= */
- #define R_AGTW0_AGTMR2_LPM_Pos        (7UL)          /*!< LPM (Bit 7)                                           */
- #define R_AGTW0_AGTMR2_LPM_Msk        (0x80UL)       /*!< LPM (Bitfield-Mask: 0x01)                             */
- #define R_AGTW0_AGTMR2_CKS_Pos        (0UL)          /*!< CKS (Bit 0)                                           */
- #define R_AGTW0_AGTMR2_CKS_Msk        (0x7UL)        /*!< CKS (Bitfield-Mask: 0x07)                             */
-/* ========================================================  AGTIOC  ========================================================= */
- #define R_AGTW0_AGTIOC_TIOGT_Pos      (6UL)          /*!< TIOGT (Bit 6)                                         */
- #define R_AGTW0_AGTIOC_TIOGT_Msk      (0xc0UL)       /*!< TIOGT (Bitfield-Mask: 0x03)                           */
- #define R_AGTW0_AGTIOC_TIPF_Pos       (4UL)          /*!< TIPF (Bit 4)                                          */
- #define R_AGTW0_AGTIOC_TIPF_Msk       (0x30UL)       /*!< TIPF (Bitfield-Mask: 0x03)                            */
- #define R_AGTW0_AGTIOC_TOE_Pos        (2UL)          /*!< TOE (Bit 2)                                           */
- #define R_AGTW0_AGTIOC_TOE_Msk        (0x4UL)        /*!< TOE (Bitfield-Mask: 0x01)                             */
- #define R_AGTW0_AGTIOC_TEDGSEL_Pos    (0UL)          /*!< TEDGSEL (Bit 0)                                       */
- #define R_AGTW0_AGTIOC_TEDGSEL_Msk    (0x1UL)        /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
-/* ========================================================  AGTISR  ========================================================= */
- #define R_AGTW0_AGTISR_EEPS_Pos       (2UL)          /*!< EEPS (Bit 2)                                          */
- #define R_AGTW0_AGTISR_EEPS_Msk       (0x4UL)        /*!< EEPS (Bitfield-Mask: 0x01)                            */
-/* ========================================================  AGTCMSR  ======================================================== */
- #define R_AGTW0_AGTCMSR_TOPOLB_Pos    (6UL)          /*!< TOPOLB (Bit 6)                                        */
- #define R_AGTW0_AGTCMSR_TOPOLB_Msk    (0x40UL)       /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
- #define R_AGTW0_AGTCMSR_TOEB_Pos      (5UL)          /*!< TOEB (Bit 5)                                          */
- #define R_AGTW0_AGTCMSR_TOEB_Msk      (0x20UL)       /*!< TOEB (Bitfield-Mask: 0x01)                            */
- #define R_AGTW0_AGTCMSR_TCMEB_Pos     (4UL)          /*!< TCMEB (Bit 4)                                         */
- #define R_AGTW0_AGTCMSR_TCMEB_Msk     (0x10UL)       /*!< TCMEB (Bitfield-Mask: 0x01)                           */
- #define R_AGTW0_AGTCMSR_TOPOLA_Pos    (2UL)          /*!< TOPOLA (Bit 2)                                        */
- #define R_AGTW0_AGTCMSR_TOPOLA_Msk    (0x4UL)        /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
- #define R_AGTW0_AGTCMSR_TOEA_Pos      (1UL)          /*!< TOEA (Bit 1)                                          */
- #define R_AGTW0_AGTCMSR_TOEA_Msk      (0x2UL)        /*!< TOEA (Bitfield-Mask: 0x01)                            */
- #define R_AGTW0_AGTCMSR_TCMEA_Pos     (0UL)          /*!< TCMEA (Bit 0)                                         */
- #define R_AGTW0_AGTCMSR_TCMEA_Msk     (0x1UL)        /*!< TCMEA (Bitfield-Mask: 0x01)                           */
-/* =======================================================  AGTIOSEL  ======================================================== */
- #define R_AGTW0_AGTIOSEL_TIES_Pos     (4UL)          /*!< TIES (Bit 4)                                          */
- #define R_AGTW0_AGTIOSEL_TIES_Msk     (0x10UL)       /*!< TIES (Bitfield-Mask: 0x01)                            */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -11336,10 +11861,22 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
 /* =========================================================  GTCR  ========================================================== */
+ #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
+ #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTCR_TPCS_Pos              (24UL)         /*!< TPCS (Bit 24)                                         */
  #define R_GPT0_GTCR_TPCS_Msk              (0x7000000UL)  /*!< TPCS (Bitfield-Mask: 0x07)                            */
  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
- #define R_GPT0_GTCR_MD_Msk                (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
+ #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
+ #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
+ #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
+ #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
 /* =======================================================  GTUDDTYC  ======================================================== */
@@ -11397,6 +11934,8 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
 /* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
+ #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
@@ -11405,8 +11944,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
- #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
- #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
+ #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
+ #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
+ #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
 /* =========================================================  GTST  ========================================================== */
  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
@@ -11463,6 +12010,8 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
+ #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
@@ -11552,6 +12101,67 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 /* ========================================================  GTSOTR  ========================================================= */
  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
 /* ========================================================  GTICLF  ========================================================= */
  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
@@ -11594,14 +12204,113 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
+ #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
+ #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTBER2  ========================================================= */
+ #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
+ #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
+ #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
+ #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
+ #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
+ #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
+ #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
+ #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
+ #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
+ #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
+ #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
+ #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
+ #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
+ #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
+ #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
+ #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
+ #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
+ #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
+ #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
+ #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTOLBR  ========================================================= */
+ #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
+ #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
+ #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
+ #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  GTICCR  ========================================================= */
+ #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
+ #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
+ #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
+ #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
+ #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
+ #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
+ #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
+ #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
+ #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
+ #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
+ #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
+ #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
+ #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
+ #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
+ #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
+ #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
+ #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
+ #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
+ #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
+ #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
+ #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_OPS                                         ================ */
@@ -14227,6 +14936,9 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 /* ======================================================  CECCKDIVCR  ======================================================= */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  I3CCKDIVCR  ======================================================= */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
 /* ======================================================  IICCKDIVCR  ======================================================= */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
@@ -14479,6 +15191,10 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_WDT_WDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
  #define R_WDT_WDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
 /** @} */ /* End of group PosMask_peripherals */
 
  #ifdef __cplusplus
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h
index 8debb83dd..b0386d400 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h
@@ -797,7 +797,8 @@ typedef struct
             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
             uint8_t            : 1;
             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
-            uint8_t            : 2;
+            uint8_t            : 1;
+            __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
         } RTCCR_b;
     };
     __IM uint8_t RESERVED;
@@ -940,6 +941,213 @@ typedef struct
     __IM uint8_t RESERVED5[3];
 } R_RTC_CP_Type;                       /*!< Size = 16 (0x10)                                                          */
 
+/**
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
+            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
+            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
+            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
+            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
+            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
+        } AGTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
+            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
+            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
+            uint8_t              : 1;
+        } AGTMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+                                        *   ratio                                                                     */
+            uint8_t           : 4;
+            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
+        } AGTMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+                                        *   mode.                                                                     */
+            uint8_t             : 1;
+            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
+            uint8_t             : 1;
+            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
+            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
+        } AGTIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
+            uint8_t            : 5;
+        } AGTISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
+
+        struct
+        {
+            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
+            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
+            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
+            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
+            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
+            uint8_t              : 1;
+        } AGTCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_b;
+    };
+} R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
+
+        struct
+        {
+            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IM uint16_t                 RESERVED;
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
+} R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
+
+        struct
+        {
+            __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
+} R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_clusters */
 
 /* =========================================================================================================================== */
@@ -1318,16 +1526,17 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
 
     union
     {
-        __IM uint16_t ADDR[28];        /*!< (@ 0x00000020) A/D Data Register                                          */
+        __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
 
         struct
         {
             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
                                         *   storing the result of A/D conversion.                                     */
-        } ADDR_b[28];
+        } ADDR_b[29];
     };
-    __IM uint32_t RESERVED1[2];
-    __IM uint16_t RESERVED2;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+    __IM uint16_t RESERVED3;
 
     union
     {
@@ -1520,7 +1729,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint16_t                : 3;
         } ADSWTSTR2_b;
     };
-    __IM uint16_t RESERVED3;
+    __IM uint16_t RESERVED4;
 
     union
     {
@@ -1582,7 +1791,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 6;
         } ADACSR_b;
     };
-    __IM uint8_t RESERVED4;
+    __IM uint8_t RESERVED5;
 
     union
     {
@@ -1652,7 +1861,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
         } ADSER_b;
     };
-    __IM uint8_t RESERVED5;
+    __IM uint8_t RESERVED6;
 
     union
     {
@@ -1668,7 +1877,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
         } ADHVREFCNT_b;
     };
-    __IM uint8_t RESERVED6;
+    __IM uint8_t RESERVED7;
 
     union
     {
@@ -1686,8 +1895,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t              : 2;
         } ADWINMON_b;
     };
-    __IM uint8_t  RESERVED7;
-    __IM uint16_t RESERVED8;
+    __IM uint8_t  RESERVED8;
+    __IM uint16_t RESERVED9;
 
     union
     {
@@ -1863,7 +2072,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 6;
         } ADCMPSER_b;
     };
-    __IM uint8_t RESERVED9;
+    __IM uint8_t RESERVED10;
 
     union
     {
@@ -1878,7 +2087,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
         } ADCMPBNSR_b;
     };
-    __IM uint8_t RESERVED10;
+    __IM uint8_t RESERVED11;
 
     union
     {
@@ -1917,8 +2126,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 7;
         } ADCMPBSR_b;
     };
-    __IM uint8_t  RESERVED11;
-    __IM uint16_t RESERVED12;
+    __IM uint8_t  RESERVED12;
+    __IM uint16_t RESERVED13;
 
     union
     {
@@ -2122,7 +2331,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 7;
         } ADBUFEN_b;
     };
-    __IM uint8_t RESERVED13;
+    __IM uint8_t RESERVED14;
 
     union
     {
@@ -2136,9 +2345,9 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 3;
         } ADBUFPTR_b;
     };
-    __IM uint8_t  RESERVED14;
-    __IM uint32_t RESERVED15[2];
-    __IM uint8_t  RESERVED16;
+    __IM uint8_t  RESERVED15;
+    __IM uint32_t RESERVED16[2];
+    __IM uint8_t  RESERVED17;
 
     union
     {
@@ -2205,7 +2414,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
         } ADCALEXE_b;
     };
-    __IM uint8_t RESERVED17;
+    __IM uint8_t RESERVED18;
 
     union
     {
@@ -2222,8 +2431,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
         } VREFAMPCNT_b;
     };
-    __IM uint8_t  RESERVED18;
-    __IM uint16_t RESERVED19;
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -2245,8 +2454,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 6;
         } ADRST_b;
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint32_t RESERVED21[41];
+    __IM uint8_t  RESERVED21;
+    __IM uint32_t RESERVED22[41];
 
     union
     {
@@ -2304,7 +2513,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
         } ADPGAGS0_b;
     };
-    __IM uint32_t RESERVED22[3];
+    __IM uint32_t RESERVED23[3];
 
     union
     {
@@ -2331,7 +2540,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
         } ADPGADCR0_b;
     };
-    __IM uint16_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -2360,8 +2569,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 7;
         } ADPGADBS1_b;
     };
-    __IM uint16_t RESERVED24;
-    __IM uint32_t RESERVED25[10];
+    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED26[10];
 
     union
     {
@@ -2377,156 +2586,6 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
     };
 } R_ADC0_Type;                         /*!< Size = 484 (0x1e4)                                                        */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Asynchronous General Purpose Timer (R_AGT0)
- */
-
-typedef struct                         /*!< (@ 0x40084000) R_AGT0 Structure                                           */
-{
-    union
-    {
-        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
-
-        struct
-        {
-            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written
-                                        *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
-                                        *   is forcibly stopped and set to FFFFH.                                     */
-        } AGT_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCRn register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMA_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCR register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMB_b;
-    };
-    __IM uint16_t RESERVED;
-
-    union
-    {
-        __IOM uint8_t AGTCR;           /*!< (@ 0x00000008) AGT Control Register                                       */
-
-        struct
-        {
-            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
-            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
-            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
-            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
-            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
-            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
-        } AGTCR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000009) AGT Mode Register 1                                        */
-
-        struct
-        {
-            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
-            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
-            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
-            uint8_t              : 1;
-        } AGTMR1_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000A) AGT Mode Register 2                                        */
-
-        struct
-        {
-            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
-                                        *   ratio                                                                     */
-            uint8_t           : 4;
-            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
-        } AGTMR2_b;
-    };
-    __IM uint8_t RESERVED1;
-
-    union
-    {
-        __IOM uint8_t AGTIOC;          /*!< (@ 0x0000000C) AGT I/O Control Register                                   */
-
-        struct
-        {
-            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
-                                        *   mode.                                                                     */
-            uint8_t             : 1;
-            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
-            uint8_t             : 1;
-            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
-            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
-        } AGTIOC_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTISR;          /*!< (@ 0x0000000D) AGT Event Pin Select Register                              */
-
-        struct
-        {
-            uint8_t            : 2;
-            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
-            uint8_t            : 5;
-        } AGTISR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTCMSR;         /*!< (@ 0x0000000E) AGT Compare Match Function Select Register                 */
-
-        struct
-        {
-            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
-            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
-            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
-            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
-            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
-            uint8_t              : 1;
-        } AGTCMSR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x0000000F) AGT Pin Select Register                                    */
-
-        struct
-        {
-            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
-            uint8_t            : 2;
-            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
-            uint8_t            : 3;
-        } AGTIOSEL_b;
-    };
-} R_AGT0_Type;                         /*!< Size = 16 (0x10)                                                          */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -4751,46 +4810,99 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            uint32_t : 18;
         } GTSTR_b;
     };
 
@@ -4842,7 +4954,60 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
                                          *   1 means counter stop.                                                     */
-            uint32_t : 18;
+            __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
         } GTSTP_b;
     };
 
@@ -4866,7 +5031,24 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
-            uint32_t             : 18;
+            __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
         } GTCLR_b;
     };
 
@@ -5187,16 +5369,23 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+        __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
 
         struct
         {
-            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
-            uint32_t            : 15;
-            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
-            uint32_t            : 5;
-            __IOM uint32_t TPCS : 3;   /*!< [26..24] Timer Prescaler Select                                           */
-            uint32_t            : 5;
+            __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
+            uint32_t               : 7;
+            __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
+            __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
+            __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
+            __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
+            uint32_t               : 2;
+            __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
+            __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
+            uint32_t               : 4;
+            __IOM uint32_t TPCS    : 3; /*!< [26..24] Timer Prescaler Select                                           */
+            __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
+            uint32_t               : 3;
         } GTCR_b;
     };
 
@@ -5267,13 +5456,36 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
         struct
         {
-            uint32_t               : 24;
-            __IOM uint32_t GRP     : 2; /*!< [25..24] Output Disable Source Select                                     */
+            uint32_t            : 8;
+            __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
+            __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            uint32_t               : 4;
+            __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
             uint32_t               : 2;
-            __IOM uint32_t GRPDTE  : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
-            __IOM uint32_t GRPABH  : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable               */
-            __IOM uint32_t GRPABL  : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
-            __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
+            __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
+            __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
         } GTINTAD_b;
     };
 
@@ -5316,32 +5528,36 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTBER;          /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
 
         struct
         {
-            __IOM uint32_t BD0    : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
-            __IOM uint32_t BD1    : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
-            __IOM uint32_t BD2    : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
-            __IOM uint32_t BD3    : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
-            uint32_t              : 12;
-            __IOM uint32_t CCRA   : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
-            __IOM uint32_t CCRB   : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
-            __IOM uint32_t PR     : 2; /*!< [21..20] GTPR Buffer Operation                                            */
-            __OM uint32_t  CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
-                                        *   is read as 0.                                                             */
+            __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
+            __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+                                         *   is read as 0.                                                             */
             uint32_t             : 1;
-            __IOM uint32_t ADTTA : 2;  /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDA : 1;  /*!< [26..26] GTADTRA Double Buffer Operation                                  */
+            __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
             uint32_t             : 1;
-            __IOM uint32_t ADTTB : 2;  /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDB : 1;  /*!< [30..30] GTADTRB Double Buffer Operation                                  */
+            __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
             uint32_t             : 1;
         } GTBER_b;
     };
@@ -5565,7 +5781,126 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             uint32_t            : 31;
         } GTSOTR_b;
     };
-    __IM uint32_t RESERVED[5];
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
 
     union
     {
@@ -5599,7 +5934,7 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             uint32_t            : 4;
         } GTPC_b;
     };
-    __IM uint32_t RESERVED1[4];
+    __IM uint32_t RESERVED[4];
 
     union
     {
@@ -5641,17 +5976,137 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
         {
             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 4;
             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
-            uint32_t             : 7;
+            __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
+            uint32_t             : 6;
             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
-            uint32_t             : 7;
+            __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
+            uint32_t             : 6;
         } GTSECR_b;
     };
-} R_GPT0_Type;                         /*!< Size = 216 (0xd8)                                                         */
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
+            __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
+                                        *   Disable                                                                   */
+            uint32_t             : 2;
+            __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t             : 1;
+            __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
+                                        *   Transfer Disable                                                          */
+            uint32_t             : 2;
+            __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
+            __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
+            __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
+            __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
+            uint32_t             : 2;
+        } GTBER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
+
+        struct
+        {
+            __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
+            uint32_t              : 11;
+            __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
+            uint32_t              : 11;
+        } GTOLBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
+                                        *                  Capture Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
+            __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
+                                        *   Other Channel GTCCRb Input Capture Source Enable                          */
+            __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
+        } GTICCR_b;
+    };
+} R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_OPS                                         ================ */
@@ -9075,8 +9530,18 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } IICCKDIVCR_b;
         };
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint16_t RESERVED21;
+
+    union
+    {
+        __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
+
+        struct
+        {
+            __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
+            uint8_t                : 5;
+        } I3CCKDIVCR_b;
+    };
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -9203,8 +9668,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
         } I3CCKCR_b;
     };
-    __IM uint16_t RESERVED22;
-    __IM uint32_t RESERVED23[3];
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
 
     union
     {
@@ -9218,8 +9683,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                 : 29;
         } SNZREQCR1_b;
     };
-    __IM uint32_t RESERVED24;
-    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -9234,7 +9699,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
         } SNZCR_b;
     };
-    __IM uint8_t RESERVED26;
+    __IM uint8_t RESERVED25;
 
     union
     {
@@ -9264,7 +9729,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } SNZEDCR1_b;
     };
-    __IM uint16_t RESERVED27;
+    __IM uint16_t RESERVED26;
 
     union
     {
@@ -9307,7 +9772,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 1;
         } SNZREQCR_b;
     };
-    __IM uint16_t RESERVED28;
+    __IM uint16_t RESERVED27;
 
     union
     {
@@ -9345,7 +9810,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 3;
         } OPCCR_b;
     };
-    __IM uint8_t RESERVED29;
+    __IM uint8_t RESERVED28;
 
     union
     {
@@ -9357,7 +9822,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } MOSCWTCR_b;
     };
-    __IM uint8_t RESERVED30[2];
+    __IM uint8_t RESERVED29[2];
 
     union
     {
@@ -9370,7 +9835,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t : 5;
         } HOCOWTCR_b;
     };
-    __IM uint16_t RESERVED31[2];
+    __IM uint16_t RESERVED30[2];
 
     union
     {
@@ -9384,8 +9849,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 3;
         } SOPCCR_b;
     };
-    __IM uint8_t  RESERVED32;
-    __IM uint32_t RESERVED33[5];
+    __IM uint8_t  RESERVED31;
+    __IM uint32_t RESERVED32[5];
 
     union
     {
@@ -9419,8 +9884,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
         } RSTSR1_b;
     };
-    __IM uint16_t RESERVED34;
-    __IM uint32_t RESERVED35[3];
+    __IM uint16_t RESERVED33;
+    __IM uint32_t RESERVED34[3];
 
     union
     {
@@ -9446,8 +9911,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
         } SDADCCKCR_b;
     };
-    __IM uint16_t RESERVED36;
-    __IM uint32_t RESERVED37[3];
+    __IM uint16_t RESERVED35;
+    __IM uint32_t RESERVED36[3];
 
     union
     {
@@ -9502,7 +9967,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t          : 6;
         } LVD2SR_b;
     };
-    __IM uint32_t RESERVED38[183];
+    __IM uint32_t RESERVED37[183];
 
     union
     {
@@ -9530,7 +9995,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 14;
         } CGFSAR_b;
     };
-    __IM uint32_t RESERVED39;
+    __IM uint32_t RESERVED38;
 
     union
     {
@@ -9599,7 +10064,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 8;
         } BBFSAR_b;
     };
-    __IM uint32_t RESERVED40[3];
+    __IM uint32_t RESERVED39[3];
 
     union
     {
@@ -9661,8 +10126,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 4;
         } DPFSAR_b;
     };
-    __IM uint32_t RESERVED41[6];
-    __IM uint16_t RESERVED42;
+    __IM uint32_t RESERVED40[6];
+    __IM uint16_t RESERVED41;
 
     union
     {
@@ -9880,7 +10345,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 3;
         } DPSIEGR2_b;
     };
-    __IM uint8_t RESERVED43;
+    __IM uint8_t RESERVED42;
 
     union
     {
@@ -9938,7 +10403,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } RSTSR2_b;
     };
-    __IM uint8_t RESERVED44;
+    __IM uint8_t RESERVED43;
 
     union
     {
@@ -9955,7 +10420,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                           *   Enable                                                                    */
         } MOMCR_b;
     };
-    __IM uint16_t RESERVED45;
+    __IM uint16_t RESERVED44;
 
     union
     {
@@ -10025,7 +10490,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } LVD2CMPCR_b;
         };
     };
-    __IM uint8_t RESERVED46;
+    __IM uint8_t RESERVED45;
 
     union
     {
@@ -10058,7 +10523,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
         } LVD2CR0_b;
     };
-    __IM uint8_t RESERVED47;
+    __IM uint8_t RESERVED46;
 
     union
     {
@@ -10093,7 +10558,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 7;
         } VBTCR1_b;
     };
-    __IM uint32_t RESERVED48[8];
+    __IM uint32_t RESERVED47[8];
 
     union
     {
@@ -10136,7 +10601,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 6;
         } VCCSEL_b;
     };
-    __IM uint16_t RESERVED49;
+    __IM uint16_t RESERVED48;
 
     union
     {
@@ -10148,9 +10613,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } PL2LDOSCR_b;
     };
-    __IM uint8_t  RESERVED50;
-    __IM uint16_t RESERVED51;
-    __IM uint32_t RESERVED52[14];
+    __IM uint8_t  RESERVED49;
+    __IM uint16_t RESERVED50;
+    __IM uint32_t RESERVED51[14];
 
     union
     {
@@ -10173,8 +10638,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 6;
         } SOMCR_b;
     };
-    __IM uint16_t RESERVED53;
-    __IM uint32_t RESERVED54[3];
+    __IM uint16_t RESERVED52;
+    __IM uint32_t RESERVED53[3];
 
     union
     {
@@ -10186,7 +10651,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 7;
         } LOCOCR_b;
     };
-    __IM uint8_t RESERVED55;
+    __IM uint8_t RESERVED54;
 
     union
     {
@@ -10201,8 +10666,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                          *   trimming bits                                                             */
         } LOCOUTCR_b;
     };
-    __IM uint8_t  RESERVED56;
-    __IM uint32_t RESERVED57[7];
+    __IM uint8_t  RESERVED55;
+    __IM uint32_t RESERVED56[7];
 
     union
     {
@@ -10241,7 +10706,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 7;
         } VBTCMPCR_b;
     };
-    __IM uint8_t RESERVED58;
+    __IM uint8_t RESERVED57;
 
     union
     {
@@ -10255,7 +10720,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                  : 6;
         } VBTLVDICR_b;
     };
-    __IM uint8_t RESERVED59;
+    __IM uint8_t RESERVED58;
 
     union
     {
@@ -10267,7 +10732,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } VBTWCTLR_b;
     };
-    __IM uint8_t RESERVED60;
+    __IM uint8_t RESERVED59;
 
     union
     {
@@ -10402,9 +10867,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } VBTBER_b;
     };
-    __IM uint8_t  RESERVED61;
-    __IM uint16_t RESERVED62;
-    __IM uint32_t RESERVED63[15];
+    __IM uint8_t  RESERVED60;
+    __IM uint16_t RESERVED61;
+    __IM uint32_t RESERVED62[15];
 
     union
     {
@@ -10532,6 +10997,23 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
     __IM uint16_t RESERVED3;
 } R_WDT_Type;                          /*!< Size = 12 (0xc)                                                           */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
+ */
+
+typedef struct                          /*!< (@ 0x40084000) R_AGTX0 Structure                                          */
+{
+    union
+    {
+        __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
+        __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
+    };
+} R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_peripherals */
 
 /* =========================================================================================================================== */
@@ -10545,12 +11027,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_ACMPLP_BASE       0x40085E00UL
  #define R_ADC0_BASE         0x4005C000UL
  #define R_ADC1_BASE         0x4005C200UL
- #define R_AGT0_BASE         0x40084000UL
- #define R_AGT1_BASE         0x40084100UL
- #define R_AGT2_BASE         0x40084200UL
- #define R_AGT3_BASE         0x40084300UL
- #define R_AGT4_BASE         0x40084400UL
- #define R_AGT5_BASE         0x40084500UL
  #define R_BUS_BASE          0x40003000UL
  #define R_CAC_BASE          0x40044600UL
  #define R_CAN0_BASE         0x40050000UL
@@ -10625,6 +11101,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_SYSTEM_BASE       0x4001E000UL
  #define R_TSN_BASE          0x407EC000UL
  #define R_WDT_BASE          0x40044200UL
+ #define R_AGTX0_BASE        0x40084000UL
+ #define R_AGTX1_BASE        0x40084100UL
+ #define R_AGTX2_BASE        0x40084200UL
+ #define R_AGTX3_BASE        0x40084300UL
+ #define R_AGTX4_BASE        0x40084400UL
+ #define R_AGTX5_BASE        0x40084500UL
+ #define R_AGTX6_BASE        0x40084600UL
+ #define R_AGTX7_BASE        0x40084700UL
+ #define R_AGTX8_BASE        0x40084800UL
+ #define R_AGTX9_BASE        0x40084900UL
 
 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
 
@@ -10639,12 +11125,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_ACMPLP       ((R_ACMPLP_Type *) R_ACMPLP_BASE)
  #define R_ADC0         ((R_ADC0_Type *) R_ADC0_BASE)
  #define R_ADC1         ((R_ADC0_Type *) R_ADC1_BASE)
- #define R_AGT0         ((R_AGT0_Type *) R_AGT0_BASE)
- #define R_AGT1         ((R_AGT0_Type *) R_AGT1_BASE)
- #define R_AGT2         ((R_AGT0_Type *) R_AGT2_BASE)
- #define R_AGT3         ((R_AGT0_Type *) R_AGT3_BASE)
- #define R_AGT4         ((R_AGT0_Type *) R_AGT4_BASE)
- #define R_AGT5         ((R_AGT0_Type *) R_AGT5_BASE)
  #define R_BUS          ((R_BUS_Type *) R_BUS_BASE)
  #define R_CAC          ((R_CAC_Type *) R_CAC_BASE)
  #define R_CAN0         ((R_CAN0_Type *) R_CAN0_BASE)
@@ -10719,6 +11199,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_SYSTEM       ((R_SYSTEM_Type *) R_SYSTEM_BASE)
  #define R_TSN          ((R_TSN_Type *) R_TSN_BASE)
  #define R_WDT          ((R_WDT_Type *) R_WDT_BASE)
+ #define R_AGTX0        ((R_AGTX0_Type *) R_AGTX0_BASE)
+ #define R_AGTX1        ((R_AGTX0_Type *) R_AGTX1_BASE)
+ #define R_AGTX2        ((R_AGTX0_Type *) R_AGTX2_BASE)
+ #define R_AGTX3        ((R_AGTX0_Type *) R_AGTX3_BASE)
+ #define R_AGTX4        ((R_AGTX0_Type *) R_AGTX4_BASE)
+ #define R_AGTX5        ((R_AGTX0_Type *) R_AGTX5_BASE)
+ #define R_AGTX6        ((R_AGTX0_Type *) R_AGTX6_BASE)
+ #define R_AGTX7        ((R_AGTX0_Type *) R_AGTX7_BASE)
+ #define R_AGTX8        ((R_AGTX0_Type *) R_AGTX8_BASE)
+ #define R_AGTX9        ((R_AGTX0_Type *) R_AGTX9_BASE)
 
 /** @} */ /* End of group Device_Peripheral_declaration */
 
@@ -11075,6 +11565,8 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 /* =========================================================================================================================== */
 
 /* =========================================================  RTCCR  ========================================================= */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
@@ -11126,6 +11618,101 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_RTC_CP_RMON_MON1_Pos        (0UL)    /*!< MON1 (Bit 0)                                          */
  #define R_RTC_CP_RMON_MON1_Msk        (0xfUL)  /*!< MON1 (Bitfield-Mask: 0x0f)                            */
 
+/* =========================================================================================================================== */
+/* ================                                           CTRL                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  AGTCR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AGTMR1  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
+/* ========================================================  AGTMR2  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
+/* =====================================================  AGTIOSEL_ALT  ====================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+/* ========================================================  AGTIOC  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AGTISR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AGTCMSR  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
+/* =======================================================  AGTIOSEL  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT16                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT32                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
+
 /** @} */ /* End of group PosMask_clusters */
 
 /* =========================================================================================================================== */
@@ -11685,77 +12272,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_ADC0_ADREFMON_MONSEL_Pos         (16UL)      /*!< MONSEL (Bit 16)                                       */
  #define R_ADC0_ADREFMON_MONSEL_Msk         (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f)                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/* ==========================================================  AGT  ========================================================== */
- #define R_AGT0_AGT_AGT_Pos           (0UL)      /*!< AGT (Bit 0)                                           */
- #define R_AGT0_AGT_AGT_Msk           (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
-/* ========================================================  AGTCMA  ========================================================= */
- #define R_AGT0_AGTCMA_AGTCMA_Pos     (0UL)      /*!< AGTCMA (Bit 0)                                        */
- #define R_AGT0_AGTCMA_AGTCMA_Msk     (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
-/* ========================================================  AGTCMB  ========================================================= */
- #define R_AGT0_AGTCMB_AGTCMB_Pos     (0UL)      /*!< AGTCMB (Bit 0)                                        */
- #define R_AGT0_AGTCMB_AGTCMB_Msk     (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
-/* =========================================================  AGTCR  ========================================================= */
- #define R_AGT0_AGTCR_TCMBF_Pos       (7UL)      /*!< TCMBF (Bit 7)                                         */
- #define R_AGT0_AGTCR_TCMBF_Msk       (0x80UL)   /*!< TCMBF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCMAF_Pos       (6UL)      /*!< TCMAF (Bit 6)                                         */
- #define R_AGT0_AGTCR_TCMAF_Msk       (0x40UL)   /*!< TCMAF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TUNDF_Pos       (5UL)      /*!< TUNDF (Bit 5)                                         */
- #define R_AGT0_AGTCR_TUNDF_Msk       (0x20UL)   /*!< TUNDF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TEDGF_Pos       (4UL)      /*!< TEDGF (Bit 4)                                         */
- #define R_AGT0_AGTCR_TEDGF_Msk       (0x10UL)   /*!< TEDGF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTOP_Pos       (2UL)      /*!< TSTOP (Bit 2)                                         */
- #define R_AGT0_AGTCR_TSTOP_Msk       (0x4UL)    /*!< TSTOP (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCSTF_Pos       (1UL)      /*!< TCSTF (Bit 1)                                         */
- #define R_AGT0_AGTCR_TCSTF_Msk       (0x2UL)    /*!< TCSTF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTART_Pos      (0UL)      /*!< TSTART (Bit 0)                                        */
- #define R_AGT0_AGTCR_TSTART_Msk      (0x1UL)    /*!< TSTART (Bitfield-Mask: 0x01)                          */
-/* ========================================================  AGTMR1  ========================================================= */
- #define R_AGT0_AGTMR1_TCK_Pos        (4UL)      /*!< TCK (Bit 4)                                           */
- #define R_AGT0_AGTMR1_TCK_Msk        (0x70UL)   /*!< TCK (Bitfield-Mask: 0x07)                             */
- #define R_AGT0_AGTMR1_TEDGPL_Pos     (3UL)      /*!< TEDGPL (Bit 3)                                        */
- #define R_AGT0_AGTMR1_TEDGPL_Msk     (0x8UL)    /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTMR1_TMOD_Pos       (0UL)      /*!< TMOD (Bit 0)                                          */
- #define R_AGT0_AGTMR1_TMOD_Msk       (0x7UL)    /*!< TMOD (Bitfield-Mask: 0x07)                            */
-/* ========================================================  AGTMR2  ========================================================= */
- #define R_AGT0_AGTMR2_LPM_Pos        (7UL)      /*!< LPM (Bit 7)                                           */
- #define R_AGT0_AGTMR2_LPM_Msk        (0x80UL)   /*!< LPM (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTMR2_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
- #define R_AGT0_AGTMR2_CKS_Msk        (0x7UL)    /*!< CKS (Bitfield-Mask: 0x07)                             */
-/* ========================================================  AGTIOC  ========================================================= */
- #define R_AGT0_AGTIOC_TIOGT_Pos      (6UL)      /*!< TIOGT (Bit 6)                                         */
- #define R_AGT0_AGTIOC_TIOGT_Msk      (0xc0UL)   /*!< TIOGT (Bitfield-Mask: 0x03)                           */
- #define R_AGT0_AGTIOC_TIPF_Pos       (4UL)      /*!< TIPF (Bit 4)                                          */
- #define R_AGT0_AGTIOC_TIPF_Msk       (0x30UL)   /*!< TIPF (Bitfield-Mask: 0x03)                            */
- #define R_AGT0_AGTIOC_TOE_Pos        (2UL)      /*!< TOE (Bit 2)                                           */
- #define R_AGT0_AGTIOC_TOE_Msk        (0x4UL)    /*!< TOE (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTIOC_TEDGSEL_Pos    (0UL)      /*!< TEDGSEL (Bit 0)                                       */
- #define R_AGT0_AGTIOC_TEDGSEL_Msk    (0x1UL)    /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
-/* ========================================================  AGTISR  ========================================================= */
- #define R_AGT0_AGTISR_EEPS_Pos       (2UL)      /*!< EEPS (Bit 2)                                          */
- #define R_AGT0_AGTISR_EEPS_Msk       (0x4UL)    /*!< EEPS (Bitfield-Mask: 0x01)                            */
-/* ========================================================  AGTCMSR  ======================================================== */
- #define R_AGT0_AGTCMSR_TOPOLB_Pos    (6UL)      /*!< TOPOLB (Bit 6)                                        */
- #define R_AGT0_AGTCMSR_TOPOLB_Msk    (0x40UL)   /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEB_Pos      (5UL)      /*!< TOEB (Bit 5)                                          */
- #define R_AGT0_AGTCMSR_TOEB_Msk      (0x20UL)   /*!< TOEB (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEB_Pos     (4UL)      /*!< TCMEB (Bit 4)                                         */
- #define R_AGT0_AGTCMSR_TCMEB_Msk     (0x10UL)   /*!< TCMEB (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCMSR_TOPOLA_Pos    (2UL)      /*!< TOPOLA (Bit 2)                                        */
- #define R_AGT0_AGTCMSR_TOPOLA_Msk    (0x4UL)    /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEA_Pos      (1UL)      /*!< TOEA (Bit 1)                                          */
- #define R_AGT0_AGTCMSR_TOEA_Msk      (0x2UL)    /*!< TOEA (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEA_Pos     (0UL)      /*!< TCMEA (Bit 0)                                         */
- #define R_AGT0_AGTCMSR_TCMEA_Msk     (0x1UL)    /*!< TCMEA (Bitfield-Mask: 0x01)                           */
-/* =======================================================  AGTIOSEL  ======================================================== */
- #define R_AGT0_AGTIOSEL_TIES_Pos     (4UL)      /*!< TIES (Bit 4)                                          */
- #define R_AGT0_AGTIOSEL_TIES_Msk     (0x10UL)   /*!< TIES (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTIOSEL_SEL_Pos      (0UL)      /*!< SEL (Bit 0)                                           */
- #define R_AGT0_AGTIOSEL_SEL_Msk      (0x3UL)    /*!< SEL (Bitfield-Mask: 0x03)                             */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -13168,10 +13684,22 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
 /* =========================================================  GTCR  ========================================================== */
+ #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
+ #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTCR_TPCS_Pos              (24UL)         /*!< TPCS (Bit 24)                                         */
  #define R_GPT0_GTCR_TPCS_Msk              (0x7000000UL)  /*!< TPCS (Bitfield-Mask: 0x07)                            */
  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
- #define R_GPT0_GTCR_MD_Msk                (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
+ #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
+ #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
+ #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
+ #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
 /* =======================================================  GTUDDTYC  ======================================================== */
@@ -13229,6 +13757,8 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
 /* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
+ #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
@@ -13237,8 +13767,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
- #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
- #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
+ #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
+ #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
+ #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
 /* =========================================================  GTST  ========================================================== */
  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
@@ -13295,6 +13833,8 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
+ #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
@@ -13384,6 +13924,67 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 /* ========================================================  GTSOTR  ========================================================= */
  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
 /* ========================================================  GTICLF  ========================================================= */
  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
@@ -13426,14 +14027,113 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
+ #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
+ #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTBER2  ========================================================= */
+ #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
+ #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
+ #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
+ #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
+ #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
+ #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
+ #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
+ #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
+ #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
+ #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
+ #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
+ #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
+ #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
+ #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
+ #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
+ #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
+ #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
+ #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
+ #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
+ #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTOLBR  ========================================================= */
+ #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
+ #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
+ #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
+ #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  GTICCR  ========================================================= */
+ #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
+ #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
+ #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
+ #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
+ #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
+ #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
+ #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
+ #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
+ #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
+ #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
+ #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
+ #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
+ #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
+ #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
+ #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
+ #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
+ #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
+ #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
+ #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
+ #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
+ #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_OPS                                         ================ */
@@ -15613,6 +16313,9 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 /* ======================================================  CECCKDIVCR  ======================================================= */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  I3CCKDIVCR  ======================================================= */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
 /* ======================================================  IICCKDIVCR  ======================================================= */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
@@ -15865,6 +16568,10 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_WDT_WDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
  #define R_WDT_WDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
 /** @} */ /* End of group PosMask_peripherals */
 
  #ifdef __cplusplus
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h
index cf7960318..78b20da2e 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h
@@ -799,7 +799,8 @@ typedef struct
             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
             uint8_t            : 1;
             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
-            uint8_t            : 2;
+            uint8_t            : 1;
+            __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
         } RTCCR_b;
     };
     __IM uint8_t RESERVED;
@@ -1144,6 +1145,213 @@ typedef struct
     };
 } R_USB_FS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
 
+/**
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
+            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
+            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
+            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
+            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
+            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
+        } AGTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
+            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
+            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
+            uint8_t              : 1;
+        } AGTMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+                                        *   ratio                                                                     */
+            uint8_t           : 4;
+            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
+        } AGTMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+                                        *   mode.                                                                     */
+            uint8_t             : 1;
+            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
+            uint8_t             : 1;
+            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
+            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
+        } AGTIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
+            uint8_t            : 5;
+        } AGTISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
+
+        struct
+        {
+            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
+            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
+            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
+            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
+            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
+            uint8_t              : 1;
+        } AGTCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_b;
+    };
+} R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
+
+        struct
+        {
+            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IM uint16_t                 RESERVED;
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
+} R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
+
+        struct
+        {
+            __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
+} R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_clusters */
 
 /* =========================================================================================================================== */
@@ -1436,16 +1644,17 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
 
     union
     {
-        __IM uint16_t ADDR[28];        /*!< (@ 0x00000020) A/D Data Register                                          */
+        __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
 
         struct
         {
             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
                                         *   storing the result of A/D conversion.                                     */
-        } ADDR_b[28];
+        } ADDR_b[29];
     };
-    __IM uint32_t RESERVED1[2];
-    __IM uint16_t RESERVED2;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+    __IM uint16_t RESERVED3;
 
     union
     {
@@ -1638,7 +1847,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint16_t                : 3;
         } ADSWTSTR2_b;
     };
-    __IM uint16_t RESERVED3;
+    __IM uint16_t RESERVED4;
 
     union
     {
@@ -1700,7 +1909,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 6;
         } ADACSR_b;
     };
-    __IM uint8_t RESERVED4;
+    __IM uint8_t RESERVED5;
 
     union
     {
@@ -1770,7 +1979,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
         } ADSER_b;
     };
-    __IM uint8_t RESERVED5;
+    __IM uint8_t RESERVED6;
 
     union
     {
@@ -1786,7 +1995,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
         } ADHVREFCNT_b;
     };
-    __IM uint8_t RESERVED6;
+    __IM uint8_t RESERVED7;
 
     union
     {
@@ -1804,8 +2013,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t              : 2;
         } ADWINMON_b;
     };
-    __IM uint8_t  RESERVED7;
-    __IM uint16_t RESERVED8;
+    __IM uint8_t  RESERVED8;
+    __IM uint16_t RESERVED9;
 
     union
     {
@@ -1981,7 +2190,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 6;
         } ADCMPSER_b;
     };
-    __IM uint8_t RESERVED9;
+    __IM uint8_t RESERVED10;
 
     union
     {
@@ -1996,7 +2205,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
         } ADCMPBNSR_b;
     };
-    __IM uint8_t RESERVED10;
+    __IM uint8_t RESERVED11;
 
     union
     {
@@ -2035,8 +2244,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 7;
         } ADCMPBSR_b;
     };
-    __IM uint8_t  RESERVED11;
-    __IM uint16_t RESERVED12;
+    __IM uint8_t  RESERVED12;
+    __IM uint16_t RESERVED13;
 
     union
     {
@@ -2240,7 +2449,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 7;
         } ADBUFEN_b;
     };
-    __IM uint8_t RESERVED13;
+    __IM uint8_t RESERVED14;
 
     union
     {
@@ -2254,9 +2463,9 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 3;
         } ADBUFPTR_b;
     };
-    __IM uint8_t  RESERVED14;
-    __IM uint32_t RESERVED15[2];
-    __IM uint8_t  RESERVED16;
+    __IM uint8_t  RESERVED15;
+    __IM uint32_t RESERVED16[2];
+    __IM uint8_t  RESERVED17;
 
     union
     {
@@ -2323,7 +2532,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
         } ADCALEXE_b;
     };
-    __IM uint8_t RESERVED17;
+    __IM uint8_t RESERVED18;
 
     union
     {
@@ -2340,8 +2549,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
         } VREFAMPCNT_b;
     };
-    __IM uint8_t  RESERVED18;
-    __IM uint16_t RESERVED19;
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -2363,8 +2572,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 6;
         } ADRST_b;
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint32_t RESERVED21[41];
+    __IM uint8_t  RESERVED21;
+    __IM uint32_t RESERVED22[41];
 
     union
     {
@@ -2422,7 +2631,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
         } ADPGAGS0_b;
     };
-    __IM uint32_t RESERVED22[3];
+    __IM uint32_t RESERVED23[3];
 
     union
     {
@@ -2449,7 +2658,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
         } ADPGADCR0_b;
     };
-    __IM uint16_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -2478,8 +2687,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 7;
         } ADPGADBS1_b;
     };
-    __IM uint16_t RESERVED24;
-    __IM uint32_t RESERVED25[10];
+    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED26[10];
 
     union
     {
@@ -2643,63 +2852,63 @@ typedef struct                         /*!< (@ 0x400E0000) R_PSCU Structure
 
     union
     {
-        __IM uint32_t CFSAMONA;        /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
+        __IOM uint32_t CFSAMONA;       /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
                                         *                  A                                                          */
 
         struct
         {
-            uint32_t           : 15;
-            __IM uint32_t CFS2 : 9;    /*!< [23..15] Code Flash Secure area 2                                         */
-            uint32_t           : 8;
+            uint32_t            : 15;
+            __IOM uint32_t CFS2 : 9;   /*!< [23..15] Code Flash Secure area 2                                         */
+            uint32_t            : 8;
         } CFSAMONA_b;
     };
 
     union
     {
-        __IM uint32_t CFSAMONB;        /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
+        __IOM uint32_t CFSAMONB;       /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
                                         *                  B                                                          */
 
         struct
         {
-            uint32_t           : 10;
-            __IM uint32_t CFS1 : 14;   /*!< [23..10] Code Flash Secure area 1                                         */
-            uint32_t           : 8;
+            uint32_t            : 10;
+            __IOM uint32_t CFS1 : 14;  /*!< [23..10] Code Flash Secure area 1                                         */
+            uint32_t            : 8;
         } CFSAMONB_b;
     };
 
     union
     {
-        __IM uint32_t DFSAMON;         /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register           */
+        __IOM uint32_t DFSAMON;        /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register           */
 
         struct
         {
-            uint32_t          : 10;
-            __IM uint32_t DFS : 6;     /*!< [15..10] Data flash Secure area                                           */
-            uint32_t          : 16;
+            uint32_t           : 10;
+            __IOM uint32_t DFS : 6;    /*!< [15..10] Data flash Secure area                                           */
+            uint32_t           : 16;
         } DFSAMON_b;
     };
 
     union
     {
-        __IM uint32_t SSAMONA;         /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A               */
+        __IOM uint32_t SSAMONA;        /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A               */
 
         struct
         {
-            uint32_t          : 13;
-            __IM uint32_t SS2 : 8;     /*!< [20..13] SRAM Secure area 2                                               */
-            uint32_t          : 11;
+            uint32_t           : 13;
+            __IOM uint32_t SS2 : 8;    /*!< [20..13] SRAM Secure area 2                                               */
+            uint32_t           : 11;
         } SSAMONA_b;
     };
 
     union
     {
-        __IM uint32_t SSAMONB;         /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B               */
+        __IOM uint32_t SSAMONB;        /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B               */
 
         struct
         {
-            uint32_t          : 10;
-            __IM uint32_t SS1 : 11;    /*!< [20..10] SRAM secure area 1                                               */
-            uint32_t          : 11;
+            uint32_t           : 10;
+            __IOM uint32_t SS1 : 11;   /*!< [20..10] SRAM secure area 1                                               */
+            uint32_t           : 11;
         } SSAMONB_b;
     };
 
@@ -2715,156 +2924,6 @@ typedef struct                         /*!< (@ 0x400E0000) R_PSCU Structure
     };
 } R_PSCU_Type;                         /*!< Size = 48 (0x30)                                                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Asynchronous General Purpose Timer (R_AGT0)
- */
-
-typedef struct                         /*!< (@ 0x400E8000) R_AGT0 Structure                                           */
-{
-    union
-    {
-        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
-
-        struct
-        {
-            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written
-                                        *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
-                                        *   is forcibly stopped and set to FFFFH.                                     */
-        } AGT_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCRn register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMA_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCR register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMB_b;
-    };
-    __IM uint16_t RESERVED;
-
-    union
-    {
-        __IOM uint8_t AGTCR;           /*!< (@ 0x00000008) AGT Control Register                                       */
-
-        struct
-        {
-            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
-            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
-            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
-            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
-            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
-            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
-        } AGTCR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000009) AGT Mode Register 1                                        */
-
-        struct
-        {
-            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
-            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
-            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
-            uint8_t              : 1;
-        } AGTMR1_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000A) AGT Mode Register 2                                        */
-
-        struct
-        {
-            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
-                                        *   ratio                                                                     */
-            uint8_t           : 4;
-            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
-        } AGTMR2_b;
-    };
-    __IM uint8_t RESERVED1;
-
-    union
-    {
-        __IOM uint8_t AGTIOC;          /*!< (@ 0x0000000C) AGT I/O Control Register                                   */
-
-        struct
-        {
-            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
-                                        *   mode.                                                                     */
-            uint8_t             : 1;
-            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
-            uint8_t             : 1;
-            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
-            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
-        } AGTIOC_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTISR;          /*!< (@ 0x0000000D) AGT Event Pin Select Register                              */
-
-        struct
-        {
-            uint8_t            : 2;
-            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
-            uint8_t            : 5;
-        } AGTISR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTCMSR;         /*!< (@ 0x0000000E) AGT Compare Match Function Select Register                 */
-
-        struct
-        {
-            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
-            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
-            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
-            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
-            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
-            uint8_t              : 1;
-        } AGTCMSR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x0000000F) AGT Pin Select Register                                    */
-
-        struct
-        {
-            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
-            uint8_t            : 2;
-            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
-            uint8_t            : 3;
-        } AGTIOSEL_b;
-    };
-} R_AGT0_Type;                         /*!< Size = 16 (0x10)                                                          */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -4724,46 +4783,99 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            uint32_t : 18;
         } GTSTR_b;
     };
 
@@ -4815,7 +4927,60 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
                                          *   1 means counter stop.                                                     */
-            uint32_t : 18;
+            __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
         } GTSTP_b;
     };
 
@@ -4839,7 +5004,24 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
-            uint32_t             : 18;
+            __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
         } GTCLR_b;
     };
 
@@ -5160,16 +5342,23 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+        __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
 
         struct
         {
-            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
-            uint32_t            : 15;
-            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
-            uint32_t            : 4;
-            __IOM uint32_t TPCS : 4;   /*!< [26..23] Timer Prescaler Select                                           */
-            uint32_t            : 5;
+            __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
+            uint32_t               : 7;
+            __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
+            __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
+            __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
+            __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
+            uint32_t               : 2;
+            __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
+            __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
+            uint32_t               : 3;
+            __IOM uint32_t TPCS    : 4; /*!< [26..23] Timer Prescaler Select                                           */
+            __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
+            uint32_t               : 3;
         } GTCR_b;
     };
 
@@ -5240,13 +5429,36 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
         struct
         {
-            uint32_t               : 24;
-            __IOM uint32_t GRP     : 2; /*!< [25..24] Output Disable Source Select                                     */
+            uint32_t            : 8;
+            __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
+            __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            uint32_t               : 4;
+            __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
             uint32_t               : 2;
-            __IOM uint32_t GRPDTE  : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
-            __IOM uint32_t GRPABH  : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable               */
-            __IOM uint32_t GRPABL  : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
-            __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
+            __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
+            __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
         } GTINTAD_b;
     };
 
@@ -5289,32 +5501,36 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTBER;          /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
 
         struct
         {
-            __IOM uint32_t BD0    : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
-            __IOM uint32_t BD1    : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
-            __IOM uint32_t BD2    : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
-            __IOM uint32_t BD3    : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
-            uint32_t              : 12;
-            __IOM uint32_t CCRA   : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
-            __IOM uint32_t CCRB   : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
-            __IOM uint32_t PR     : 2; /*!< [21..20] GTPR Buffer Operation                                            */
-            __OM uint32_t  CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
-                                        *   is read as 0.                                                             */
+            __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
+            __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+                                         *   is read as 0.                                                             */
             uint32_t             : 1;
-            __IOM uint32_t ADTTA : 2;  /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDA : 1;  /*!< [26..26] GTADTRA Double Buffer Operation                                  */
+            __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
             uint32_t             : 1;
-            __IOM uint32_t ADTTB : 2;  /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDB : 1;  /*!< [30..30] GTADTRB Double Buffer Operation                                  */
+            __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
             uint32_t             : 1;
         } GTBER_b;
     };
@@ -5538,7 +5754,126 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             uint32_t            : 31;
         } GTSOTR_b;
     };
-    __IM uint32_t RESERVED[5];
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
 
     union
     {
@@ -5572,7 +5907,7 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             uint32_t            : 4;
         } GTPC_b;
     };
-    __IM uint32_t RESERVED1[4];
+    __IM uint32_t RESERVED[4];
 
     union
     {
@@ -5614,17 +5949,137 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
         {
             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 4;
             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
-            uint32_t             : 7;
+            __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
+            uint32_t             : 6;
             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
-            uint32_t             : 7;
+            __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
+            uint32_t             : 6;
         } GTSECR_b;
     };
-} R_GPT0_Type;                         /*!< Size = 216 (0xd8)                                                         */
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
+            __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
+                                        *   Disable                                                                   */
+            uint32_t             : 2;
+            __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t             : 1;
+            __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
+                                        *   Transfer Disable                                                          */
+            uint32_t             : 2;
+            __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
+            __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
+            __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
+            __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
+            uint32_t             : 2;
+        } GTBER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
+
+        struct
+        {
+            __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
+            uint32_t              : 11;
+            __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
+            uint32_t              : 11;
+        } GTOLBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
+                                        *                  Capture Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
+            __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
+                                        *   Other Channel GTCCRb Input Capture Source Enable                          */
+            __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
+        } GTICCR_b;
+    };
+} R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
 
 /* =========================================================================================================================== */
 /* ================                                        R_GPT_POEG0                                        ================ */
@@ -9463,8 +9918,18 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } IICCKDIVCR_b;
         };
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint16_t RESERVED21;
+
+    union
+    {
+        __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
+
+        struct
+        {
+            __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
+            uint8_t                : 5;
+        } I3CCKDIVCR_b;
+    };
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -9591,8 +10056,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
         } I3CCKCR_b;
     };
-    __IM uint16_t RESERVED22;
-    __IM uint32_t RESERVED23[3];
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
 
     union
     {
@@ -9606,8 +10071,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                 : 29;
         } SNZREQCR1_b;
     };
-    __IM uint32_t RESERVED24;
-    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -9622,7 +10087,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
         } SNZCR_b;
     };
-    __IM uint8_t RESERVED26;
+    __IM uint8_t RESERVED25;
 
     union
     {
@@ -9652,7 +10117,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } SNZEDCR1_b;
     };
-    __IM uint16_t RESERVED27;
+    __IM uint16_t RESERVED26;
 
     union
     {
@@ -9695,7 +10160,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 1;
         } SNZREQCR_b;
     };
-    __IM uint16_t RESERVED28;
+    __IM uint16_t RESERVED27;
 
     union
     {
@@ -9733,7 +10198,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 3;
         } OPCCR_b;
     };
-    __IM uint8_t RESERVED29;
+    __IM uint8_t RESERVED28;
 
     union
     {
@@ -9745,7 +10210,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } MOSCWTCR_b;
     };
-    __IM uint8_t RESERVED30[2];
+    __IM uint8_t RESERVED29[2];
 
     union
     {
@@ -9758,7 +10223,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t : 5;
         } HOCOWTCR_b;
     };
-    __IM uint16_t RESERVED31[2];
+    __IM uint16_t RESERVED30[2];
 
     union
     {
@@ -9772,8 +10237,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 3;
         } SOPCCR_b;
     };
-    __IM uint8_t  RESERVED32;
-    __IM uint32_t RESERVED33[5];
+    __IM uint8_t  RESERVED31;
+    __IM uint32_t RESERVED32[5];
 
     union
     {
@@ -9807,8 +10272,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
         } RSTSR1_b;
     };
-    __IM uint16_t RESERVED34;
-    __IM uint32_t RESERVED35[3];
+    __IM uint16_t RESERVED33;
+    __IM uint32_t RESERVED34[3];
 
     union
     {
@@ -9834,8 +10299,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
         } SDADCCKCR_b;
     };
-    __IM uint16_t RESERVED36;
-    __IM uint32_t RESERVED37[3];
+    __IM uint16_t RESERVED35;
+    __IM uint32_t RESERVED36[3];
 
     union
     {
@@ -9890,7 +10355,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t          : 6;
         } LVD2SR_b;
     };
-    __IM uint32_t RESERVED38[183];
+    __IM uint32_t RESERVED37[183];
 
     union
     {
@@ -9918,7 +10383,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 14;
         } CGFSAR_b;
     };
-    __IM uint32_t RESERVED39;
+    __IM uint32_t RESERVED38;
 
     union
     {
@@ -9987,7 +10452,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 8;
         } BBFSAR_b;
     };
-    __IM uint32_t RESERVED40[3];
+    __IM uint32_t RESERVED39[3];
 
     union
     {
@@ -10049,8 +10514,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 4;
         } DPFSAR_b;
     };
-    __IM uint32_t RESERVED41[6];
-    __IM uint16_t RESERVED42;
+    __IM uint32_t RESERVED40[6];
+    __IM uint16_t RESERVED41;
 
     union
     {
@@ -10268,7 +10733,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 3;
         } DPSIEGR2_b;
     };
-    __IM uint8_t RESERVED43;
+    __IM uint8_t RESERVED42;
 
     union
     {
@@ -10326,7 +10791,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } RSTSR2_b;
     };
-    __IM uint8_t RESERVED44;
+    __IM uint8_t RESERVED43;
 
     union
     {
@@ -10343,7 +10808,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                           *   Enable                                                                    */
         } MOMCR_b;
     };
-    __IM uint16_t RESERVED45;
+    __IM uint16_t RESERVED44;
 
     union
     {
@@ -10413,7 +10878,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } LVD2CMPCR_b;
         };
     };
-    __IM uint8_t RESERVED46;
+    __IM uint8_t RESERVED45;
 
     union
     {
@@ -10446,7 +10911,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
         } LVD2CR0_b;
     };
-    __IM uint8_t RESERVED47;
+    __IM uint8_t RESERVED46;
 
     union
     {
@@ -10481,7 +10946,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 7;
         } VBTCR1_b;
     };
-    __IM uint32_t RESERVED48[8];
+    __IM uint32_t RESERVED47[8];
 
     union
     {
@@ -10524,7 +10989,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 6;
         } VCCSEL_b;
     };
-    __IM uint16_t RESERVED49;
+    __IM uint16_t RESERVED48;
 
     union
     {
@@ -10536,9 +11001,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } PL2LDOSCR_b;
     };
-    __IM uint8_t  RESERVED50;
-    __IM uint16_t RESERVED51;
-    __IM uint32_t RESERVED52[14];
+    __IM uint8_t  RESERVED49;
+    __IM uint16_t RESERVED50;
+    __IM uint32_t RESERVED51[14];
 
     union
     {
@@ -10561,8 +11026,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 6;
         } SOMCR_b;
     };
-    __IM uint16_t RESERVED53;
-    __IM uint32_t RESERVED54[3];
+    __IM uint16_t RESERVED52;
+    __IM uint32_t RESERVED53[3];
 
     union
     {
@@ -10574,7 +11039,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 7;
         } LOCOCR_b;
     };
-    __IM uint8_t RESERVED55;
+    __IM uint8_t RESERVED54;
 
     union
     {
@@ -10589,8 +11054,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                          *   trimming bits                                                             */
         } LOCOUTCR_b;
     };
-    __IM uint8_t  RESERVED56;
-    __IM uint32_t RESERVED57[7];
+    __IM uint8_t  RESERVED55;
+    __IM uint32_t RESERVED56[7];
 
     union
     {
@@ -10629,7 +11094,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 7;
         } VBTCMPCR_b;
     };
-    __IM uint8_t RESERVED58;
+    __IM uint8_t RESERVED57;
 
     union
     {
@@ -10643,7 +11108,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                  : 6;
         } VBTLVDICR_b;
     };
-    __IM uint8_t RESERVED59;
+    __IM uint8_t RESERVED58;
 
     union
     {
@@ -10655,7 +11120,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } VBTWCTLR_b;
     };
-    __IM uint8_t RESERVED60;
+    __IM uint8_t RESERVED59;
 
     union
     {
@@ -10790,9 +11255,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } VBTBER_b;
     };
-    __IM uint8_t  RESERVED61;
-    __IM uint16_t RESERVED62;
-    __IM uint32_t RESERVED63[15];
+    __IM uint8_t  RESERVED60;
+    __IM uint16_t RESERVED61;
+    __IM uint32_t RESERVED62[15];
 
     union
     {
@@ -12319,6 +12784,23 @@ typedef struct                           /*!< (@ 0x40008000) R_CPSCU Structure
     };
 } R_CPSCU_Type;                        /*!< Size = 1540 (0x604)                                                       */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
+ */
+
+typedef struct                          /*!< (@ 0x400E8000) R_AGTX0 Structure                                          */
+{
+    union
+    {
+        __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
+        __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
+    };
+} R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
 /* =========================================================================================================================== */
 /* ================                                          R_FLAD                                           ================ */
 /* =========================================================================================================================== */
@@ -12355,12 +12837,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_ADC0_BASE           0x40170000UL
  #define R_ADC1_BASE           0x40170200UL
  #define R_PSCU_BASE           0x400E0000UL
- #define R_AGT0_BASE           0x400E8000UL
- #define R_AGT1_BASE           0x400E8100UL
- #define R_AGT2_BASE           0x400E8200UL
- #define R_AGT3_BASE           0x400E8300UL
- #define R_AGT4_BASE           0x400E8400UL
- #define R_AGT5_BASE           0x400E8500UL
  #define R_BUS_BASE            0x40003000UL
  #define R_CAC_BASE            0x40083600UL
  #define R_CAN0_BASE           0x400A8000UL
@@ -12447,6 +12923,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_WDT_BASE            0x40083400UL
  #define R_TZF_BASE            0x40000E00UL
  #define R_CPSCU_BASE          0x40008000UL
+ #define R_AGTX0_BASE          0x400E8000UL
+ #define R_AGTX1_BASE          0x400E8100UL
+ #define R_AGTX2_BASE          0x400E8200UL
+ #define R_AGTX3_BASE          0x400E8300UL
+ #define R_AGTX4_BASE          0x400E8400UL
+ #define R_AGTX5_BASE          0x400E8500UL
+ #define R_AGTX6_BASE          0x400E8600UL
+ #define R_AGTX7_BASE          0x400E8700UL
+ #define R_AGTX8_BASE          0x400E8800UL
+ #define R_AGTX9_BASE          0x400E8900UL
  #define R_FLAD_BASE           0x407FC000UL
 
 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
@@ -12462,12 +12948,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_ADC0           ((R_ADC0_Type *) R_ADC0_BASE)
  #define R_ADC1           ((R_ADC0_Type *) R_ADC1_BASE)
  #define R_PSCU           ((R_PSCU_Type *) R_PSCU_BASE)
- #define R_AGT0           ((R_AGT0_Type *) R_AGT0_BASE)
- #define R_AGT1           ((R_AGT0_Type *) R_AGT1_BASE)
- #define R_AGT2           ((R_AGT0_Type *) R_AGT2_BASE)
- #define R_AGT3           ((R_AGT0_Type *) R_AGT3_BASE)
- #define R_AGT4           ((R_AGT0_Type *) R_AGT4_BASE)
- #define R_AGT5           ((R_AGT0_Type *) R_AGT5_BASE)
 
 /* #define R_BUS                       ((R_BUS_Type*)             R_BUS_BASE) */
  #define R_CAC            ((R_CAC_Type *) R_CAC_BASE)
@@ -12555,6 +13035,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_WDT            ((R_WDT_Type *) R_WDT_BASE)
  #define R_TZF            ((R_TZF_Type *) R_TZF_BASE)
  #define R_CPSCU          ((R_CPSCU_Type *) R_CPSCU_BASE)
+ #define R_AGTX0          ((R_AGTX0_Type *) R_AGTX0_BASE)
+ #define R_AGTX1          ((R_AGTX0_Type *) R_AGTX1_BASE)
+ #define R_AGTX2          ((R_AGTX0_Type *) R_AGTX2_BASE)
+ #define R_AGTX3          ((R_AGTX0_Type *) R_AGTX3_BASE)
+ #define R_AGTX4          ((R_AGTX0_Type *) R_AGTX4_BASE)
+ #define R_AGTX5          ((R_AGTX0_Type *) R_AGTX5_BASE)
+ #define R_AGTX6          ((R_AGTX0_Type *) R_AGTX6_BASE)
+ #define R_AGTX7          ((R_AGTX0_Type *) R_AGTX7_BASE)
+ #define R_AGTX8          ((R_AGTX0_Type *) R_AGTX8_BASE)
+ #define R_AGTX9          ((R_AGTX0_Type *) R_AGTX9_BASE)
  #define R_FLAD           ((R_FLAD_Type *) R_FLAD_BASE)
 
 /** @} */ /* End of group Device_Peripheral_declaration */
@@ -12912,6 +13402,8 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* =========================================================================================================================== */
 
 /* =========================================================  RTCCR  ========================================================= */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
@@ -13059,6 +13551,101 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
 
+/* =========================================================================================================================== */
+/* ================                                           CTRL                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  AGTCR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AGTMR1  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
+/* ========================================================  AGTMR2  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
+/* =====================================================  AGTIOSEL_ALT  ====================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+/* ========================================================  AGTIOC  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AGTISR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AGTCMSR  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
+/* =======================================================  AGTIOSEL  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT16                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT32                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
+
 /** @} */ /* End of group PosMask_clusters */
 
 /* =========================================================================================================================== */
@@ -13724,77 +14311,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_PSCU_DLMMON_DLMMON_Pos    (0UL)          /*!< DLMMON (Bit 0)                                        */
  #define R_PSCU_DLMMON_DLMMON_Msk    (0xfUL)        /*!< DLMMON (Bitfield-Mask: 0x0f)                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/* ==========================================================  AGT  ========================================================== */
- #define R_AGT0_AGT_AGT_Pos           (0UL)      /*!< AGT (Bit 0)                                           */
- #define R_AGT0_AGT_AGT_Msk           (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
-/* ========================================================  AGTCMA  ========================================================= */
- #define R_AGT0_AGTCMA_AGTCMA_Pos     (0UL)      /*!< AGTCMA (Bit 0)                                        */
- #define R_AGT0_AGTCMA_AGTCMA_Msk     (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
-/* ========================================================  AGTCMB  ========================================================= */
- #define R_AGT0_AGTCMB_AGTCMB_Pos     (0UL)      /*!< AGTCMB (Bit 0)                                        */
- #define R_AGT0_AGTCMB_AGTCMB_Msk     (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
-/* =========================================================  AGTCR  ========================================================= */
- #define R_AGT0_AGTCR_TCMBF_Pos       (7UL)      /*!< TCMBF (Bit 7)                                         */
- #define R_AGT0_AGTCR_TCMBF_Msk       (0x80UL)   /*!< TCMBF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCMAF_Pos       (6UL)      /*!< TCMAF (Bit 6)                                         */
- #define R_AGT0_AGTCR_TCMAF_Msk       (0x40UL)   /*!< TCMAF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TUNDF_Pos       (5UL)      /*!< TUNDF (Bit 5)                                         */
- #define R_AGT0_AGTCR_TUNDF_Msk       (0x20UL)   /*!< TUNDF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TEDGF_Pos       (4UL)      /*!< TEDGF (Bit 4)                                         */
- #define R_AGT0_AGTCR_TEDGF_Msk       (0x10UL)   /*!< TEDGF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTOP_Pos       (2UL)      /*!< TSTOP (Bit 2)                                         */
- #define R_AGT0_AGTCR_TSTOP_Msk       (0x4UL)    /*!< TSTOP (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCSTF_Pos       (1UL)      /*!< TCSTF (Bit 1)                                         */
- #define R_AGT0_AGTCR_TCSTF_Msk       (0x2UL)    /*!< TCSTF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTART_Pos      (0UL)      /*!< TSTART (Bit 0)                                        */
- #define R_AGT0_AGTCR_TSTART_Msk      (0x1UL)    /*!< TSTART (Bitfield-Mask: 0x01)                          */
-/* ========================================================  AGTMR1  ========================================================= */
- #define R_AGT0_AGTMR1_TCK_Pos        (4UL)      /*!< TCK (Bit 4)                                           */
- #define R_AGT0_AGTMR1_TCK_Msk        (0x70UL)   /*!< TCK (Bitfield-Mask: 0x07)                             */
- #define R_AGT0_AGTMR1_TEDGPL_Pos     (3UL)      /*!< TEDGPL (Bit 3)                                        */
- #define R_AGT0_AGTMR1_TEDGPL_Msk     (0x8UL)    /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTMR1_TMOD_Pos       (0UL)      /*!< TMOD (Bit 0)                                          */
- #define R_AGT0_AGTMR1_TMOD_Msk       (0x7UL)    /*!< TMOD (Bitfield-Mask: 0x07)                            */
-/* ========================================================  AGTMR2  ========================================================= */
- #define R_AGT0_AGTMR2_LPM_Pos        (7UL)      /*!< LPM (Bit 7)                                           */
- #define R_AGT0_AGTMR2_LPM_Msk        (0x80UL)   /*!< LPM (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTMR2_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
- #define R_AGT0_AGTMR2_CKS_Msk        (0x7UL)    /*!< CKS (Bitfield-Mask: 0x07)                             */
-/* ========================================================  AGTIOC  ========================================================= */
- #define R_AGT0_AGTIOC_TIOGT_Pos      (6UL)      /*!< TIOGT (Bit 6)                                         */
- #define R_AGT0_AGTIOC_TIOGT_Msk      (0xc0UL)   /*!< TIOGT (Bitfield-Mask: 0x03)                           */
- #define R_AGT0_AGTIOC_TIPF_Pos       (4UL)      /*!< TIPF (Bit 4)                                          */
- #define R_AGT0_AGTIOC_TIPF_Msk       (0x30UL)   /*!< TIPF (Bitfield-Mask: 0x03)                            */
- #define R_AGT0_AGTIOC_TOE_Pos        (2UL)      /*!< TOE (Bit 2)                                           */
- #define R_AGT0_AGTIOC_TOE_Msk        (0x4UL)    /*!< TOE (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTIOC_TEDGSEL_Pos    (0UL)      /*!< TEDGSEL (Bit 0)                                       */
- #define R_AGT0_AGTIOC_TEDGSEL_Msk    (0x1UL)    /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
-/* ========================================================  AGTISR  ========================================================= */
- #define R_AGT0_AGTISR_EEPS_Pos       (2UL)      /*!< EEPS (Bit 2)                                          */
- #define R_AGT0_AGTISR_EEPS_Msk       (0x4UL)    /*!< EEPS (Bitfield-Mask: 0x01)                            */
-/* ========================================================  AGTCMSR  ======================================================== */
- #define R_AGT0_AGTCMSR_TOPOLB_Pos    (6UL)      /*!< TOPOLB (Bit 6)                                        */
- #define R_AGT0_AGTCMSR_TOPOLB_Msk    (0x40UL)   /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEB_Pos      (5UL)      /*!< TOEB (Bit 5)                                          */
- #define R_AGT0_AGTCMSR_TOEB_Msk      (0x20UL)   /*!< TOEB (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEB_Pos     (4UL)      /*!< TCMEB (Bit 4)                                         */
- #define R_AGT0_AGTCMSR_TCMEB_Msk     (0x10UL)   /*!< TCMEB (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCMSR_TOPOLA_Pos    (2UL)      /*!< TOPOLA (Bit 2)                                        */
- #define R_AGT0_AGTCMSR_TOPOLA_Msk    (0x4UL)    /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEA_Pos      (1UL)      /*!< TOEA (Bit 1)                                          */
- #define R_AGT0_AGTCMSR_TOEA_Msk      (0x2UL)    /*!< TOEA (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEA_Pos     (0UL)      /*!< TCMEA (Bit 0)                                         */
- #define R_AGT0_AGTCMSR_TCMEA_Msk     (0x1UL)    /*!< TCMEA (Bitfield-Mask: 0x01)                           */
-/* =======================================================  AGTIOSEL  ======================================================== */
- #define R_AGT0_AGTIOSEL_TIES_Pos     (4UL)      /*!< TIES (Bit 4)                                          */
- #define R_AGT0_AGTIOSEL_TIES_Msk     (0x10UL)   /*!< TIES (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTIOSEL_SEL_Pos      (0UL)      /*!< SEL (Bit 0)                                           */
- #define R_AGT0_AGTIOSEL_SEL_Msk      (0x3UL)    /*!< SEL (Bitfield-Mask: 0x03)                             */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -14918,10 +15434,22 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
 /* =========================================================  GTCR  ========================================================== */
+ #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
+ #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTCR_TPCS_Pos              (23UL)         /*!< TPCS (Bit 23)                                         */
  #define R_GPT0_GTCR_TPCS_Msk              (0x7800000UL)  /*!< TPCS (Bitfield-Mask: 0x0f)                            */
  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
- #define R_GPT0_GTCR_MD_Msk                (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
+ #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
+ #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
+ #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
+ #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
 /* =======================================================  GTUDDTYC  ======================================================== */
@@ -14979,6 +15507,8 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
 /* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
+ #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
@@ -14987,8 +15517,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
- #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
- #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
+ #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
+ #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
+ #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
 /* =========================================================  GTST  ========================================================== */
  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
@@ -15045,6 +15583,8 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
+ #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
@@ -15134,6 +15674,67 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* ========================================================  GTSOTR  ========================================================= */
  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
 /* ========================================================  GTICLF  ========================================================= */
  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
@@ -15176,14 +15777,113 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
+ #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
+ #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTBER2  ========================================================= */
+ #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
+ #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
+ #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
+ #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
+ #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
+ #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
+ #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
+ #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
+ #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
+ #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
+ #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
+ #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
+ #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
+ #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
+ #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
+ #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
+ #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
+ #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
+ #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
+ #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTOLBR  ========================================================= */
+ #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
+ #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
+ #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
+ #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  GTICCR  ========================================================= */
+ #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
+ #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
+ #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
+ #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
+ #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
+ #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
+ #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
+ #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
+ #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
+ #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
+ #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
+ #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
+ #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
+ #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
+ #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
+ #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
+ #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
+ #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
+ #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
+ #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
+ #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
 
 /* =========================================================================================================================== */
 /* ================                                        R_GPT_POEG0                                        ================ */
@@ -17476,6 +18176,9 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* ======================================================  CECCKDIVCR  ======================================================= */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  I3CCKDIVCR  ======================================================= */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
 /* ======================================================  IICCKDIVCR  ======================================================= */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
@@ -18415,6 +19118,10 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_CPSCU_TEVTRCR_TEVTE_Pos           (0UL)          /*!< TEVTE (Bit 0)                                         */
  #define R_CPSCU_TEVTRCR_TEVTE_Msk           (0x1UL)        /*!< TEVTE (Bitfield-Mask: 0x01)                           */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
 /* =========================================================================================================================== */
 /* ================                                          R_FLAD                                           ================ */
 /* =========================================================================================================================== */
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E2B9.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E2B9.h
new file mode 100644
index 000000000..e5ca38716
--- /dev/null
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E2B9.h
@@ -0,0 +1,21864 @@
+/*
+ * This software is supplied by Renesas Electronics Corporation and is only intended for
+ * use with Renesas products. No other uses are authorized. This software is owned by
+ * Renesas Electronics Corporation and is protected under all applicable laws, including
+ * copyright laws.
+ *
+ * THIS SOFTWARE IS PROVIDED 'AS IS' AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT
+ * PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED
+ * COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL
+ * DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ *
+ * Renesas reserves the right, without notice, to make changes to this software and to
+ * discontinue the availability of this software. By using this software, you agree to
+ * the additional terms and conditions found by accessing the following link:
+ * http://www.renesas.com/disclaimer
+ *
+ *
+ * @file     ./out/R7FA4E2B9.h
+ * @brief    CMSIS HeaderFile
+ * @version  1.00.00
+ */
+
+/** @addtogroup Renesas Electronics Corporation
+ * @{
+ */
+
+/** @addtogroup R7FA4E2B9
+ * @{
+ */
+
+#ifndef R7FA4E2B9_H
+ #define R7FA4E2B9_H
+
+ #ifdef __cplusplus
+extern "C" {
+ #endif
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                Interrupt Number Definition                                ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                           Processor and Core Peripheral Section                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================  Configuration of the ARM Cortex-M33 Processor and Core Peripherals  =========================== */
+ #define __CM33_REV                0x0004U /*!< CM33 Core Revision                                                        */
+ #define __NVIC_PRIO_BITS          4       /*!< Number of Bits used for Priority Levels                                   */
+ #define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used                              */
+ #define __VTOR_PRESENT            1       /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
+ #define __MPU_PRESENT             1       /*!< MPU present                                                               */
+ #define __FPU_PRESENT             1       /*!< FPU present                                                               */
+ #define __FPU_DP                  0       /*!< Double Precision FPU                                                      */
+ #define __DSP_PRESENT             1       /*!< DSP extension present                                                     */
+ #define __SAUREGION_PRESENT       0       /*!< SAU region present                                                        */
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+ #include "core_cm33.h"                    /*!< ARM Cortex-M33 processor and core peripherals                             */
+ #include "system.h"                       /*!< R7FA4E2B9 System                                                          */
+
+ #ifndef __IM                              /*!< Fallback for older CMSIS versions                                         */
+  #define __IM     __I
+ #endif
+ #ifndef __OM                              /*!< Fallback for older CMSIS versions                                         */
+  #define __OM     __O
+ #endif
+ #ifndef __IOM                             /*!< Fallback for older CMSIS versions                                         */
+  #define __IOM    __IO
+ #endif
+
+/* ========================================  Start of section using anonymous unions  ======================================== */
+ #if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+ #elif defined(__ICCARM__)
+  #pragma language=extended
+ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wc11-extensions"
+  #pragma clang diagnostic ignored "-Wreserved-id-macro"
+  #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
+  #pragma clang diagnostic ignored "-Wnested-anon-types"
+ #elif defined(__GNUC__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TMS470__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TASKING__)
+  #pragma warning 586
+ #elif defined(__CSMC__)
+
+/* anonymous unions are enabled by default */
+ #else
+  #warning Not supported compiler type
+ #endif
+
+/* =========================================================================================================================== */
+/* ================                              Device Specific Cluster Section                              ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_clusters
+ * @{
+ */
+
+/**
+ * @brief R_BUS_CSa [CSa] (CS Registers)
+ */
+typedef struct
+{
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t MOD;            /*!< (@ 0x00000002) Mode Register                                              */
+
+        struct
+        {
+            __IOM uint16_t WRMOD : 1;  /*!< [0..0] Write Access Mode Select                                           */
+            uint16_t             : 2;
+            __IOM uint16_t EWENB : 1;  /*!< [3..3] External Wait Enable                                               */
+            uint16_t             : 4;
+            __IOM uint16_t PRENB : 1;  /*!< [8..8] Page Read Access Enable                                            */
+            __IOM uint16_t PWENB : 1;  /*!< [9..9] Page Write Access Enable                                           */
+            uint16_t             : 5;
+            __IOM uint16_t PRMOD : 1;  /*!< [15..15] Page Read Access Mode Select                                     */
+        } MOD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t WCR1;             /*!< (@ 0x00000004) Wait Control Register 1                                    */
+
+        struct
+        {
+            __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value
+                                          *   is valid only when the PWENB bit in CSnMOD is set to 1.                   */
+            uint32_t                : 5;
+            __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value
+                                          *   is valid only when the PRENB bit in CSnMOD is set to 1.                   */
+            uint32_t               : 5;
+            __IOM uint32_t CSWWAIT : 5;  /*!< [20..16] Normal Write Cycle Wait Select                                   */
+            uint32_t               : 3;
+            __IOM uint32_t CSRWAIT : 5;  /*!< [28..24] Normal Read Cycle Wait Select                                    */
+            uint32_t               : 3;
+        } WCR1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t WCR2;           /*!< (@ 0x00000008) Wait Control Register 2                                    */
+
+        struct
+        {
+            __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select                              */
+            uint32_t              : 1;
+            __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select                             */
+            uint32_t              : 1;
+            __IOM uint32_t WDOFF  : 3; /*!< [10..8] Write Data Output Extension Cycle Select                          */
+            uint32_t              : 1;
+            __IOM uint32_t AWAIT  : 2; /*!< [13..12] CS Assert Wait Select                                            */
+            uint32_t              : 2;
+            __IOM uint32_t RDON   : 3; /*!< [18..16] RD Assert Wait Select                                            */
+            uint32_t              : 1;
+            __IOM uint32_t WRON   : 3; /*!< [22..20] WR Assert Wait Select                                            */
+            uint32_t              : 1;
+            __IOM uint32_t WDON   : 3; /*!< [26..24] Write Data Output Wait Select                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CSON   : 3; /*!< [30..28] CS Assert Wait Select                                            */
+            uint32_t              : 1;
+        } WCR2_b;
+    };
+    __IM uint32_t RESERVED1;
+} R_BUS_CSa_Type;                      /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_BUS_CSb [CSb] (CS Registers)
+ */
+typedef struct
+{
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t CR;             /*!< (@ 0x00000002) Control Register                                           */
+
+        struct
+        {
+            __IOM uint16_t EXENB : 1;  /*!< [0..0] Operation Enable                                                   */
+            uint16_t             : 3;
+            __IOM uint16_t BSIZE : 2;  /*!< [5..4] External Bus Width Select                                          */
+            uint16_t             : 2;
+            __IOM uint16_t EMODE : 1;  /*!< [8..8] Endian Mode                                                        */
+            uint16_t             : 3;
+            __IOM uint16_t MPXEN : 1;  /*!< [12..12] Address/Data Multiplexed I/O Interface Select                    */
+            uint16_t             : 3;
+        } CR_b;
+    };
+    __IM uint16_t RESERVED1[3];
+
+    union
+    {
+        __IOM uint16_t REC;            /*!< (@ 0x0000000A) Recovery Cycle Register                                    */
+
+        struct
+        {
+            __IOM uint16_t RRCV : 4;   /*!< [3..0] Read Recovery                                                      */
+            uint16_t            : 4;
+            __IOM uint16_t WRCV : 4;   /*!< [11..8] Write Recovery                                                    */
+            uint16_t            : 4;
+        } REC_b;
+    };
+    __IM uint16_t RESERVED2[2];
+} R_BUS_CSb_Type;                      /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t SDCCR;           /*!< (@ 0x00000000) SDC Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t EXENB : 1;   /*!< [0..0] Operation Enable                                                   */
+            uint8_t             : 3;
+            __IOM uint8_t BSIZE : 2;   /*!< [5..4] SDRAM Bus Width Select                                             */
+            uint8_t             : 2;
+        } SDCCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SDCMOD;          /*!< (@ 0x00000001) SDC Mode Register                                          */
+
+        struct
+        {
+            __IOM uint8_t EMODE : 1;   /*!< [0..0] Endian Mode                                                        */
+            uint8_t             : 7;
+        } SDCMOD_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SDAMOD;          /*!< (@ 0x00000002) SDRAM Access Mode Register                                 */
+
+        struct
+        {
+            __IOM uint8_t BE : 1;      /*!< [0..0] Continuous Access Enable                                           */
+            uint8_t          : 7;
+        } SDAMOD_b;
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint32_t RESERVED1[3];
+
+    union
+    {
+        __IOM uint8_t SDSELF;          /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t SFEN : 1;    /*!< [0..0] SDRAM Self-Refresh Enable                                          */
+            uint8_t            : 7;
+        } SDSELF_b;
+    };
+    __IM uint8_t  RESERVED2;
+    __IM uint16_t RESERVED3;
+
+    union
+    {
+        __IOM uint16_t SDRFCR;         /*!< (@ 0x00000014) SDRAM Refresh Control Register                             */
+
+        struct
+        {
+            __IOM uint16_t RFC  : 12;  /*!< [11..0] Auto-Refresh Request Interval Setting                             */
+            __IOM uint16_t REFW : 4;   /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count
+                                        *   Setting. ( REFW+1 Cycles )                                                */
+        } SDRFCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SDRFEN;          /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t RFEN : 1;    /*!< [0..0] Auto-Refresh Operation Enable                                      */
+            uint8_t            : 7;
+        } SDRFEN_b;
+    };
+    __IM uint8_t  RESERVED4;
+    __IM uint32_t RESERVED5[2];
+
+    union
+    {
+        __IOM uint8_t SDICR;           /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register             */
+
+        struct
+        {
+            __IOM uint8_t INIRQ : 1;   /*!< [0..0] Initialization Sequence Start                                      */
+            uint8_t             : 7;
+        } SDICR_b;
+    };
+    __IM uint8_t  RESERVED6;
+    __IM uint16_t RESERVED7;
+
+    union
+    {
+        __IOM uint16_t SDIR;           /*!< (@ 0x00000024) SDRAM Initialization Register                              */
+
+        struct
+        {
+            __IOM uint16_t ARFI : 4;   /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles )              */
+            __IOM uint16_t ARFC : 4;   /*!< [7..4] Initialization Auto-Refresh Count                                  */
+            __IOM uint16_t PRC  : 3;   /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles
+                                        *   )                                                                         */
+            uint16_t : 5;
+        } SDIR_b;
+    };
+    __IM uint16_t RESERVED8;
+    __IM uint32_t RESERVED9[6];
+
+    union
+    {
+        __IOM uint8_t SDADR;           /*!< (@ 0x00000040) SDRAM Address Register                                     */
+
+        struct
+        {
+            __IOM uint8_t MXC : 2;     /*!< [1..0] Address Multiplex Select                                           */
+            uint8_t           : 6;
+        } SDADR_b;
+    };
+    __IM uint8_t  RESERVED10;
+    __IM uint16_t RESERVED11;
+
+    union
+    {
+        __IOM uint32_t SDTR;           /*!< (@ 0x00000044) SDRAM Timing Register                                      */
+
+        struct
+        {
+            __IOM uint32_t CL  : 3;    /*!< [2..0] SDRAMC Column Latency                                              */
+            uint32_t           : 5;
+            __IOM uint32_t WR  : 1;    /*!< [8..8] Write Recovery Interval                                            */
+            __IOM uint32_t RP  : 3;    /*!< [11..9] Row Precharge Interval ( RP+1 cycles )                            */
+            __IOM uint32_t RCD : 2;    /*!< [13..12] Row Column Latency ( RCD+1 cycles )                              */
+            uint32_t           : 2;
+            __IOM uint32_t RAS : 3;    /*!< [18..16] Row Active Interval                                              */
+            uint32_t           : 13;
+        } SDTR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t SDMOD;          /*!< (@ 0x00000048) SDRAM Mode Register                                        */
+
+        struct
+        {
+            __IOM uint16_t MR : 15;    /*!< [14..0] Mode Register SettingWriting to these bits: Mode register
+                                        *   set command is issued.                                                    */
+            uint16_t : 1;
+        } SDMOD_b;
+    };
+    __IM uint16_t RESERVED12;
+    __IM uint32_t RESERVED13;
+
+    union
+    {
+        __IM uint8_t SDSR;             /*!< (@ 0x00000050) SDRAM Status Register                                      */
+
+        struct
+        {
+            __IM uint8_t MRSST : 1;    /*!< [0..0] Mode Register Setting Status                                       */
+            uint8_t            : 2;
+            __IM uint8_t INIST : 1;    /*!< [3..3] Initialization Status                                              */
+            __IM uint8_t SRFST : 1;    /*!< [4..4] Self-Refresh Transition/Recovery Status                            */
+            uint8_t            : 3;
+        } SDSR_b;
+    };
+    __IM uint8_t  RESERVED14;
+    __IM uint16_t RESERVED15;
+} R_BUS_SDRAM_Type;                    /*!< Size = 84 (0x54)                                                          */
+
+/**
+ * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IM uint32_t ADD;             /*!< (@ 0x00000000) Bus Error Address Register                                 */
+
+        struct
+        {
+            __IM uint32_t BERAD : 32;  /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores
+                                        *   an error address.                                                         */
+        } ADD_b;
+    };
+
+    union
+    {
+        __IM uint8_t STAT;             /*!< (@ 0x00000004) Bus Error Status Register                                  */
+
+        struct
+        {
+            __IM uint8_t ACCSTAT : 1;  /*!< [0..0] Error access statusThe status at the time of the error             */
+            uint8_t              : 6;
+            __IM uint8_t ERRSTAT : 1;  /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs.          */
+        } STAT_b;
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2[2];
+} R_BUS_BUSERR_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t CNT;            /*!< (@ 0x00000000) Master Bus Control Register                                */
+
+        struct
+        {
+            uint16_t             : 15;
+            __IOM uint16_t IERES : 1;  /*!< [15..15] Ignore Error Responses                                           */
+        } CNT_b;
+    };
+    __IM uint16_t RESERVED;
+} R_BUS_BUSM_Type;                     /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t CNT;            /*!< (@ 0x00000000) Slave Bus Control Register                                 */
+
+        struct
+        {
+            uint16_t              : 4;
+            __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups              */
+            uint16_t              : 10;
+        } CNT_b;
+    };
+    __IM uint16_t RESERVED;
+} R_BUS_BUSS_Type;                     /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t NCFG;            /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register             */
+
+        struct
+        {
+            __IOM uint32_t NBRP   : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler                                */
+            __IOM uint32_t NSJW   : 7;  /*!< [16..10] Resynchronization Jump Width                                     */
+            __IOM uint32_t NTSEG1 : 8;  /*!< [24..17] Timing Segment 1                                                 */
+            __IOM uint32_t NTSEG2 : 7;  /*!< [31..25] Timing Segment 2                                                 */
+        } NCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CTR;             /*!< (@ 0x00000004) Channel Control Registers                                  */
+
+        struct
+        {
+            __IOM uint32_t CHMDC   : 2; /*!< [1..0] Channel Mode Control                                               */
+            __IOM uint32_t CSLPR   : 1; /*!< [2..2] Channel Sleep Request                                              */
+            __IOM uint32_t RTBO    : 1; /*!< [3..3] Return from Bus-Off                                                */
+            uint32_t               : 4;
+            __IOM uint32_t BEIE    : 1; /*!< [8..8] Bus Error Interrupt Enable                                         */
+            __IOM uint32_t EWIE    : 1; /*!< [9..9] Error Warning Interrupt Enable                                     */
+            __IOM uint32_t EPIE    : 1; /*!< [10..10] Error Passive Interrupt Enable                                   */
+            __IOM uint32_t BOEIE   : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable                                   */
+            __IOM uint32_t BORIE   : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable                                */
+            __IOM uint32_t OLIE    : 1; /*!< [13..13] Overload Interrupt Enable                                        */
+            __IOM uint32_t BLIE    : 1; /*!< [14..14] Bus Lock Interrupt Enable                                        */
+            __IOM uint32_t ALIE    : 1; /*!< [15..15] Arbitration Lost Interrupt Enable                                */
+            __IOM uint32_t TAIE    : 1; /*!< [16..16] Transmission abort Interrupt Enable                              */
+            __IOM uint32_t EOCOIE  : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable               */
+            __IOM uint32_t SOCOIE  : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable          */
+            __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt
+                                         *   enable                                                                    */
+            uint32_t            : 1;
+            __IOM uint32_t BOM  : 2;    /*!< [22..21] Channel Bus-Off Mode                                             */
+            __IOM uint32_t ERRD : 1;    /*!< [23..23] Channel Error Display                                            */
+            __IOM uint32_t CTME : 1;    /*!< [24..24] Channel Test Mode Enable                                         */
+            __IOM uint32_t CTMS : 2;    /*!< [26..25] Channel Test Mode Select                                         */
+            uint32_t            : 3;
+            __IOM uint32_t CRCT : 1;    /*!< [30..30] CRC Error Test                                                   */
+            __IOM uint32_t ROM  : 1;    /*!< [31..31] Restricted Operation Mode                                        */
+        } CTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STS;             /*!< (@ 0x00000008) Channel Status Registers                                   */
+
+        struct
+        {
+            __IM uint32_t  CRSTSTS : 1; /*!< [0..0] Channel RESET Status                                               */
+            __IM uint32_t  CHLTSTS : 1; /*!< [1..1] Channel HALT Status                                                */
+            __IM uint32_t  CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status                                               */
+            __IM uint32_t  EPSTS   : 1; /*!< [3..3] Channel Error Passive Status                                       */
+            __IM uint32_t  BOSTS   : 1; /*!< [4..4] Channel Bus-Off Status                                             */
+            __IM uint32_t  TRMSTS  : 1; /*!< [5..5] Channel Transmit Status                                            */
+            __IM uint32_t  RECSTS  : 1; /*!< [6..6] Channel Receive Status                                             */
+            __IM uint32_t  COMSTS  : 1; /*!< [7..7] Channel Communication Status                                       */
+            __IOM uint32_t ESIF    : 1; /*!< [8..8] Error State Indication Flag                                        */
+            uint32_t               : 7;
+            __IM uint32_t  REC     : 8; /*!< [23..16] Reception Error Count                                            */
+            __IOM uint32_t TEC     : 8; /*!< [31..24] Transmission Error Count                                         */
+        } STS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ERFL;           /*!< (@ 0x0000000C) Channel Error Flag Registers                               */
+
+        struct
+        {
+            __IOM uint32_t BEF   : 1;  /*!< [0..0] Bus Error Flag                                                     */
+            __IOM uint32_t EWF   : 1;  /*!< [1..1] Error Warning Flag                                                 */
+            __IOM uint32_t EPF   : 1;  /*!< [2..2] Error Passive Flag                                                 */
+            __IOM uint32_t BOEF  : 1;  /*!< [3..3] Bus-Off Entry Flag                                                 */
+            __IOM uint32_t BORF  : 1;  /*!< [4..4] Bus-Off Recovery Flag                                              */
+            __IOM uint32_t OVLF  : 1;  /*!< [5..5] Overload Flag                                                      */
+            __IOM uint32_t BLF   : 1;  /*!< [6..6] Bus Lock Flag                                                      */
+            __IOM uint32_t ALF   : 1;  /*!< [7..7] Arbitration Lost Flag                                              */
+            __IOM uint32_t SERR  : 1;  /*!< [8..8] Stuff Error                                                        */
+            __IOM uint32_t FERR  : 1;  /*!< [9..9] Form Error                                                         */
+            __IOM uint32_t AERR  : 1;  /*!< [10..10] Acknowledge Error                                                */
+            __IOM uint32_t CERR  : 1;  /*!< [11..11] CRC Error                                                        */
+            __IOM uint32_t B1ERR : 1;  /*!< [12..12] Bit 1 Error                                                      */
+            __IOM uint32_t B0ERR : 1;  /*!< [13..13] Bit 0 Error                                                      */
+            __IOM uint32_t ADERR : 1;  /*!< [14..14] Acknowledge Delimiter Error                                      */
+            uint32_t             : 1;
+            __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value                                               */
+            uint32_t             : 1;
+        } ERFL_b;
+    };
+} R_CANFD_CFDC_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t DCFG;           /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register                */
+
+        struct
+        {
+            __IOM uint32_t DBRP   : 8; /*!< [7..0] Channel Data Baud Rate Prescaler                                   */
+            __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1                                                  */
+            uint32_t              : 3;
+            __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2                                                 */
+            uint32_t              : 4;
+            __IOM uint32_t DSJW   : 4; /*!< [27..24] Resynchronization Jump Width                                     */
+            uint32_t              : 4;
+        } DCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDCFG;          /*!< (@ 0x00000004) Channel CAN-FD Configuration Register                      */
+
+        struct
+        {
+            __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration                             */
+            uint32_t              : 5;
+            __IOM uint32_t TDCOC  : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration                */
+            __IOM uint32_t TDCE   : 1; /*!< [9..9] Transceiver Delay Compensation Enable                              */
+            __IOM uint32_t ESIC   : 1; /*!< [10..10] Error State Indication Configuration                             */
+            uint32_t              : 5;
+            __IOM uint32_t TDCO   : 8; /*!< [23..16] Transceiver Delay Compensation Offset                            */
+            uint32_t              : 4;
+            __IOM uint32_t FDOE   : 1; /*!< [28..28] FD only enable                                                   */
+            __IOM uint32_t REFE   : 1; /*!< [29..29] RX edge filter enable                                            */
+            __IOM uint32_t CLOE   : 1; /*!< [30..30] Classical CAN only enable                                        */
+            uint32_t              : 1;
+        } FDCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) Channel CAN-FD Control Register                            */
+
+        struct
+        {
+            __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear                                     */
+            __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear                                */
+            uint32_t              : 30;
+        } FDCTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDSTS;          /*!< (@ 0x0000000C) Channel CAN-FD Status Register                             */
+
+        struct
+        {
+            __IM uint32_t  TDCR  : 8;  /*!< [7..0] Transceiver Delay Compensation Result                              */
+            __IOM uint32_t EOCO  : 1;  /*!< [8..8] Error occurrence counter overflow                                  */
+            __IOM uint32_t SOCO  : 1;  /*!< [9..9] Successful occurrence counter overflow                             */
+            uint32_t             : 5;
+            __IOM uint32_t TDCVF : 1;  /*!< [15..15] Transceiver Delay Compensation Violation Flag                    */
+            __IM uint32_t  EOC   : 8;  /*!< [23..16] Error occurrence counter register                                */
+            __IM uint32_t  SOC   : 8;  /*!< [31..24] Successful occurrence counter register                           */
+        } FDSTS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDCRC;          /*!< (@ 0x00000010) Channel CAN-FD CRC Register                                */
+
+        struct
+        {
+            __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value                                                */
+            uint32_t             : 3;
+            __IM uint32_t SCNT   : 4;  /*!< [27..24] Stuff bit count                                                  */
+            uint32_t             : 4;
+        } FDCRC_b;
+    };
+    __IM uint32_t RESERVED[3];
+} R_CANFD_CFDC2_Type;                  /*!< Size = 32 (0x20)                                                          */
+
+/**
+ * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t ID;               /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers                 */
+
+        struct
+        {
+            __IOM uint32_t GAFLID  : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field                      */
+            __IOM uint32_t GAFLLB  : 1;  /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration       */
+            __IOM uint32_t GAFLRTR : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Field                    */
+            __IOM uint32_t GAFLIDE : 1;  /*!< [31..31] Global Acceptance Filter List Entry IDE Field                    */
+        } ID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t M;                 /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers               */
+
+        struct
+        {
+            __IOM uint32_t GAFLIDM  : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field                       */
+            __IOM uint32_t GAFLIFL1 : 1;  /*!< [29..29] Global Acceptance Filter List Information Label 1                */
+            __IOM uint32_t GAFLRTRM : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Mask                     */
+            __IOM uint32_t GAFLIDEM : 1;  /*!< [31..31] Global Acceptance Filter List IDE Mask                           */
+        } M_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0;               /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers          */
+
+        struct
+        {
+            __IOM uint32_t GAFLDLC  : 4; /*!< [3..0] Global Acceptance Filter List DLC Field                            */
+            uint32_t                : 3;
+            __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0                  */
+            __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction
+                                          *   Pointer                                                                   */
+            uint32_t               : 2;
+            __IOM uint32_t GAFLRMV : 1;  /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid            */
+            __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field                      */
+        } P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1;              /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers          */
+
+        struct
+        {
+            __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer               */
+            uint32_t               : 23;
+        } P1_b;
+    };
+} R_CANFD_CFDGAFL_Type;                 /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List)
+ */
+typedef struct
+{
+    union
+    {
+        __IM uint32_t ACC0;            /*!< (@ 0x00000000) Channel TX History List Access Registers 0                 */
+
+        struct
+        {
+            __IM uint32_t BT   : 3;    /*!< [2..0] Buffer Type                                                        */
+            __IM uint32_t BN   : 7;    /*!< [9..3] Buffer No.                                                         */
+            uint32_t           : 6;
+            __IM uint32_t TMTS : 16;   /*!< [31..16] Transmit Timestamp                                               */
+        } ACC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ACC1;           /*!< (@ 0x00000004) Channel TX History List Access Registers 1                 */
+
+        struct
+        {
+            __IM uint32_t TID  : 16;   /*!< [15..0] Transmit ID                                                       */
+            __IM uint32_t TIFL : 2;    /*!< [17..16] Transmit Information Label                                       */
+            uint32_t           : 14;
+        } ACC1_b;
+    };
+} R_CANFD_CFDTHL_Type;                 /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IM uint32_t ID;              /*!< (@ 0x00000000) RX FIFO Access ID Register                                 */
+
+        struct
+        {
+            __IM uint32_t RFID  : 29;  /*!< [28..0] RX FIFO Buffer ID Field                                           */
+            uint32_t            : 1;
+            __IM uint32_t RFRTR : 1;   /*!< [30..30] RX FIFO Buffer RTR Frame                                         */
+            __IM uint32_t RFIDE : 1;   /*!< [31..31] RX FIFO Buffer IDE Bit                                           */
+        } ID_b;
+    };
+
+    union
+    {
+        __IM uint32_t PTR;             /*!< (@ 0x00000004) RX FIFO Access Pointer Register                            */
+
+        struct
+        {
+            __IM uint32_t RFTS  : 16;  /*!< [15..0] RX FIFO Timestamp Field                                           */
+            uint32_t            : 12;
+            __IM uint32_t RFDLC : 4;   /*!< [31..28] RX FIFO Buffer DLC Field                                         */
+        } PTR_b;
+    };
+
+    union
+    {
+        __IM uint32_t FDSTS;           /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register                      */
+
+        struct
+        {
+            __IM uint32_t RFESI : 1;   /*!< [0..0] Error State Indicator bit                                          */
+            __IM uint32_t RFBRS : 1;   /*!< [1..1] Bit Rate Switch bit                                                */
+            __IM uint32_t RFFDF : 1;   /*!< [2..2] CAN FD Format bit                                                  */
+            uint32_t            : 5;
+            __IM uint32_t RFIFL : 2;   /*!< [9..8] RX FIFO Buffer Information Label Field                             */
+            uint32_t            : 6;
+            __IM uint32_t RFPTR : 16;  /*!< [31..16] RX FIFO Buffer Pointer Field                                     */
+        } FDSTS_b;
+    };
+
+    union
+    {
+        __IM uint8_t DF[64];           /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers                        */
+
+        struct
+        {
+            __IM uint8_t RFDB : 8;     /*!< [7..0] RX FIFO Buffer Data Byte                                           */
+        } DF_b[64];
+    };
+} R_CANFD_CFDRF_Type;                  /*!< Size = 76 (0x4c)                                                          */
+
+/**
+ * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t ID;             /*!< (@ 0x00000000) Common FIFO Access ID Register                             */
+
+        struct
+        {
+            __IOM uint32_t CFID  : 29; /*!< [28..0] Common FIFO Buffer ID Field                                       */
+            uint32_t             : 1;
+            __IOM uint32_t CFRTR : 1;  /*!< [30..30] Common FIFO Buffer RTR Frame                                     */
+            __IOM uint32_t CFIDE : 1;  /*!< [31..31] Common FIFO Buffer IDE Bit                                       */
+        } ID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTR;            /*!< (@ 0x00000004) Common FIFO Access Pointer Register                        */
+
+        struct
+        {
+            __IOM uint32_t CFTS  : 16; /*!< [15..0] Common FIFO Timestamp Field                                       */
+            uint32_t             : 12;
+            __IOM uint32_t CFDLC : 4;  /*!< [31..28] Common FIFO Buffer DLC Field                                     */
+        } PTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDSTS;          /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register                  */
+
+        struct
+        {
+            __IOM uint32_t CFESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
+            __IOM uint32_t CFBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
+            __IOM uint32_t CFFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
+            uint32_t             : 5;
+            __IOM uint32_t CFIFL : 2;  /*!< [9..8] Common FIFO Buffer Information Label Field                         */
+            uint32_t             : 6;
+            __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field                                 */
+        } FDSTS_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DF[64];          /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers                    */
+
+        struct
+        {
+            __IOM uint8_t CFDB : 8;    /*!< [7..0] Common FIFO Buffer Data Byte                                       */
+        } DF_b[64];
+    };
+} R_CANFD_CFDCF_Type;                  /*!< Size = 76 (0x4c)                                                          */
+
+/**
+ * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t ID;             /*!< (@ 0x00000000) TX Message Buffer ID Register                              */
+
+        struct
+        {
+            __IOM uint32_t TMID  : 29; /*!< [28..0] TX Message Buffer ID Field                                        */
+            uint32_t             : 1;
+            __IOM uint32_t TMRTR : 1;  /*!< [30..30] TX Message Buffer RTR Frame                                      */
+            __IOM uint32_t TMIDE : 1;  /*!< [31..31] TX Message Buffer IDE Bit                                        */
+        } ID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTR;            /*!< (@ 0x00000004) TX Message Buffer Pointer Register                         */
+
+        struct
+        {
+            __IOM uint32_t TMTS  : 16; /*!< [15..0] TX Message Buffer Timestamp Field                                 */
+            uint32_t             : 12;
+            __IOM uint32_t TMDLC : 4;  /*!< [31..28] TX Message Buffer DLC Field                                      */
+        } PTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register                  */
+
+        struct
+        {
+            __IOM uint32_t TMESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
+            __IOM uint32_t TMBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
+            __IOM uint32_t TMFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
+            uint32_t             : 5;
+            __IOM uint32_t TMIFL : 2;  /*!< [9..8] TX Message Buffer Information Label Field                          */
+            uint32_t             : 6;
+            __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field                                  */
+        } FDCTR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DF[64];          /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers                     */
+
+        struct
+        {
+            __IOM uint8_t TMDB : 8;    /*!< [7..0] TX Message Buffer Data Byte                                        */
+        } DF_b[64];
+    };
+} R_CANFD_CFDTM_Type;                  /*!< Size = 76 (0x4c)                                                          */
+
+/**
+ * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IM uint32_t ID;              /*!< (@ 0x00000000) RX Message Buffer ID Register                              */
+
+        struct
+        {
+            __IM uint32_t RMID  : 29;  /*!< [28..0] RX Message Buffer ID Field                                        */
+            uint32_t            : 1;
+            __IM uint32_t RMRTR : 1;   /*!< [30..30] RX Message Buffer RTR Frame                                      */
+            __IM uint32_t RMIDE : 1;   /*!< [31..31] RX Message Buffer IDE Bit                                        */
+        } ID_b;
+    };
+
+    union
+    {
+        __IM uint32_t PTR;             /*!< (@ 0x00000004) RX Message Buffer Pointer Register                         */
+
+        struct
+        {
+            __IM uint32_t RMTS  : 16;  /*!< [15..0] RX Message Buffer Timestamp Field                                 */
+            uint32_t            : 12;
+            __IM uint32_t RMDLC : 4;   /*!< [31..28] RX Message Buffer DLC Field                                      */
+        } PTR_b;
+    };
+
+    union
+    {
+        __IM uint32_t FDSTS;           /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register                   */
+
+        struct
+        {
+            __IM uint32_t RMESI : 1;   /*!< [0..0] Error State Indicator bit                                          */
+            __IM uint32_t RMBRS : 1;   /*!< [1..1] Bit Rate Switch bit                                                */
+            __IM uint32_t RMFDF : 1;   /*!< [2..2] CAN FD Format bit                                                  */
+            uint32_t            : 5;
+            __IM uint32_t RMIFL : 2;   /*!< [9..8] RX Message Buffer Information Label Field                          */
+            uint32_t            : 6;
+            __IM uint32_t RMPTR : 16;  /*!< [31..16] RX Message Buffer Pointer Field                                  */
+        } FDSTS_b;
+    };
+
+    union
+    {
+        __IM uint8_t DF[64];           /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers                     */
+
+        struct
+        {
+            __IM uint8_t RMDB : 8;     /*!< [7..0] RX Message Buffer Data Byte                                        */
+        } DF_b[64];
+    };
+} R_CANFD_CFDRM_RM_Type;               /*!< Size = 76 (0x4c)                                                          */
+
+/**
+ * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters)
+ */
+typedef struct
+{
+    __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers                         */
+    __IM uint32_t               RESERVED[104];
+} R_CANFD_CFDRM_Type;                  /*!< Size = 1024 (0x400)                                                       */
+
+/**
+ * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t BY;              /*!< (@ 0x00000000) Event Link Software Event Generation Register              */
+
+        struct
+        {
+            __OM uint8_t SEG : 1;      /*!< [0..0] Software Event Generation                                          */
+            uint8_t          : 5;
+            __IOM uint8_t WE : 1;      /*!< [6..6] SEG Bit Write Enable                                               */
+            __OM uint8_t  WI : 1;      /*!< [7..7] ELSEGR Register Write Disable                                      */
+        } BY_b;
+    };
+    __IM uint8_t RESERVED;
+} R_ELC_ELSEGR_Type;                   /*!< Size = 2 (0x2)                                                            */
+
+/**
+ * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22])
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t HA;             /*!< (@ 0x00000000) Event Link Setting Register                                */
+
+        struct
+        {
+            __IOM uint16_t ELS : 9;    /*!< [8..0] Event Link Select                                                  */
+            uint16_t           : 7;
+        } HA_b;
+    };
+    __IM uint16_t RESERVED;
+} R_ELC_ELSR_Type;                     /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_IIC0_SAR [SAR] (Slave Address Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t L;               /*!< (@ 0x00000000) Slave Address Register L                                   */
+
+        struct
+        {
+            __IOM uint8_t SVA : 8;     /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit
+                                        *   Address = { SVA9,SVA8,SVA[7:0] }                                          */
+        } L_b;
+    };
+
+    union
+    {
+        __IOM uint8_t U;               /*!< (@ 0x00000001) Slave Address Register U                                   */
+
+        struct
+        {
+            __IOM uint8_t FS   : 1;    /*!< [0..0] 7-Bit/10-Bit Address Format Selection                              */
+            __IOM uint8_t SVA8 : 1;    /*!< [1..1] 10-Bit Address(bit8)                                               */
+            __IOM uint8_t SVA9 : 1;    /*!< [2..2] 10-Bit Address(bit9)                                               */
+            uint8_t            : 5;
+        } U_b;
+    };
+} R_IIC0_SAR_Type;                     /*!< Size = 2 (0x2)                                                            */
+
+/**
+ * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t OAD;            /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
+            uint16_t           : 7;
+            __OM uint16_t KEY  : 8;    /*!< [15..8] Write Keyword The data written to these bits are not
+                                        *   stored.                                                                   */
+        } OAD_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t CTL;            /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register              */
+
+        struct
+        {
+            __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable                                       */
+            uint16_t              : 7;
+            __IOM uint16_t ERROR  : 1; /*!< [8..8] Stack Pointer Monitor Error Flag                                   */
+            uint16_t              : 7;
+        } CTL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PT;              /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register                  */
+
+        struct
+        {
+            __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE)           */
+            uint16_t               : 7;
+            __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
+                                         *   stored.                                                                   */
+        } PT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SA;                /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register               */
+
+        struct
+        {
+            __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region
+                                           *   starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF
+                                           *   The low-order 2 bits are fixed to 0.                                      */
+        } SA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EA;                /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register                 */
+
+        struct
+        {
+            __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region
+                                           *   starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF
+                                           *   The low-order 2 bits are fixed to 1.                                      */
+        } EA_b;
+    };
+} R_MPU_SPMON_SP_Type;                    /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects)
+ */
+typedef struct
+{
+    union
+    {
+        union
+        {
+            __IOM uint32_t PmnPFS;        /*!< (@ 0x00000000) Pin Function Control Register                              */
+
+            struct
+            {
+                __IOM uint32_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
+                __IM uint32_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
+                __IOM uint32_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
+                uint32_t             : 1;
+                __IOM uint32_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
+                __IOM uint32_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
+                __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
+                uint32_t             : 3;
+                __IOM uint32_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
+                __IOM uint32_t EOFR  : 2; /*!< [13..12] Event on Falling/Rising                                          */
+                __IOM uint32_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
+                __IOM uint32_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
+                __IOM uint32_t PMR   : 1; /*!< [16..16] Port Mode Control                                                */
+                uint32_t             : 7;
+                __IOM uint32_t PSEL  : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral
+                                           *   function. For individual pin functions, see the MPC table                 */
+                uint32_t : 3;
+            } PmnPFS_b;
+        };
+
+        struct
+        {
+            union
+            {
+                struct
+                {
+                    __IM uint16_t RESERVED;
+
+                    union
+                    {
+                        __IOM uint16_t PmnPFS_HA;     /*!< (@ 0x00000002) Pin Function Control Register                              */
+
+                        struct
+                        {
+                            __IOM uint16_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
+                            __IM uint16_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
+                            __IOM uint16_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
+                            uint16_t             : 1;
+                            __IOM uint16_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
+                            __IOM uint16_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
+                            __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
+                            uint16_t             : 3;
+                            __IOM uint16_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
+                            __IOM uint16_t EOFR  : 2; /*!< [13..12] Event on Falling/Rising                                          */
+                            __IOM uint16_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
+                            __IOM uint16_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
+                        } PmnPFS_HA_b;
+                    };
+                };
+
+                struct
+                {
+                    __IM uint16_t RESERVED1;
+                    __IM uint8_t  RESERVED2;
+
+                    union
+                    {
+                        __IOM uint8_t PmnPFS_BY;     /*!< (@ 0x00000003) Pin Function Control Register                              */
+
+                        struct
+                        {
+                            __IOM uint8_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
+                            __IM uint8_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
+                            __IOM uint8_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
+                            uint8_t             : 1;
+                            __IOM uint8_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
+                            __IOM uint8_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
+                            __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
+                            uint8_t             : 1;
+                        } PmnPFS_BY_b;
+                    };
+                };
+            };
+        };
+    };
+} R_PFS_PORT_PIN_Type;                 /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_PFS_PORT [PORT] (Port [0..14])
+ */
+typedef struct
+{
+    __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects                                       */
+} R_PFS_PORT_Type;                     /*!< Size = 64 (0x40)                                                          */
+
+/**
+ * @brief R_PFS_VLSEL [VLSEL] (VLSEL)
+ */
+typedef struct
+{
+    __IM uint8_t RESERVED[389];
+
+    union
+    {
+        __IOM uint8_t VL1SEL;          /*!< (@ 0x00000185) VL1 Select Control Register                                */
+
+        struct
+        {
+            __IOM uint8_t SELVL : 1;   /*!< [0..0] VL1 Voltage Connection Switching Control                           */
+            uint8_t             : 7;
+        } VL1SEL_b;
+    };
+} R_PFS_VLSEL_Type;                    /*!< Size = 390 (0x186)                                                        */
+
+/**
+ * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register)
+ */
+typedef struct
+{
+    __IOM uint16_t PMSAR;              /*!< (@ 0x00000000) Port Security Attribution Register                         */
+} R_PMISC_PMSAR_Type;                  /*!< Size = 2 (0x2)                                                            */
+
+/**
+ * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t RTCCR;           /*!< (@ 0x00000000) Time Capture Control Register                              */
+
+        struct
+        {
+            __IOM uint8_t TCCT : 2;    /*!< [1..0] Time Capture Control                                               */
+            __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
+            uint8_t            : 1;
+            __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
+            uint8_t            : 1;
+            __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
+        } RTCCR_b;
+    };
+    __IM uint8_t RESERVED;
+} R_RTC_RTCCR_Type;                    /*!< Size = 2 (0x2)                                                            */
+
+/**
+ * @brief R_RTC_CP [CP] (Capture registers)
+ */
+typedef struct
+{
+    __IM uint8_t RESERVED[2];
+
+    union
+    {
+        union
+        {
+            __IM uint8_t RSEC;          /*!< (@ 0x00000002) Second Capture Register                                    */
+
+            struct
+            {
+                __IM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Capture Capture value for the ones place of
+                                         *   seconds                                                                   */
+                __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of
+                                         *   seconds                                                                   */
+                uint8_t : 1;
+            } RSEC_b;
+        };
+
+        union
+        {
+            __IM uint8_t BCNT0;           /*!< (@ 0x00000002) BCNT0 Capture Register                                     */
+
+            struct
+            {
+                __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0
+                                           *   value when a time capture event is detected.                              */
+            } BCNT0_b;
+        };
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        union
+        {
+            __IM uint8_t RMIN;          /*!< (@ 0x00000004) Minute Capture Register                                    */
+
+            struct
+            {
+                __IM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
+                                         *   minutes                                                                   */
+                __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of
+                                         *   minutes                                                                   */
+                uint8_t : 1;
+            } RMIN_b;
+        };
+
+        union
+        {
+            __IM uint8_t BCNT1;           /*!< (@ 0x00000004) BCNT1 Capture Register                                     */
+
+            struct
+            {
+                __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1
+                                           *   value when a time capture event is detected.                              */
+            } BCNT1_b;
+        };
+    };
+    __IM uint8_t RESERVED2;
+
+    union
+    {
+        union
+        {
+            __IM uint8_t RHR;          /*!< (@ 0x00000006) Hour Capture Register                                      */
+
+            struct
+            {
+                __IM uint8_t HR1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
+                                        *   minutes                                                                   */
+                __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of
+                                        *   minutes                                                                   */
+                __IM uint8_t PM : 1;   /*!< [6..6] A.m./p.m. select for time counter setting.                         */
+                uint8_t         : 1;
+            } RHR_b;
+        };
+
+        union
+        {
+            __IM uint8_t BCNT2;           /*!< (@ 0x00000006) BCNT2 Capture Register                                     */
+
+            struct
+            {
+                __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2
+                                           *   value when a time capture event is detected.                              */
+            } BCNT2_b;
+        };
+    };
+    __IM uint8_t RESERVED3[3];
+
+    union
+    {
+        union
+        {
+            __IM uint8_t RDAY;           /*!< (@ 0x0000000A) Date Capture Register                                      */
+
+            struct
+            {
+                __IM uint8_t DATE1  : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes          */
+                __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes         */
+                uint8_t             : 2;
+            } RDAY_b;
+        };
+
+        union
+        {
+            __IM uint8_t BCNT3;           /*!< (@ 0x0000000A) BCNT3 Capture Register                                     */
+
+            struct
+            {
+                __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3
+                                           *   value when a time capture event is detected.                              */
+            } BCNT3_b;
+        };
+    };
+    __IM uint8_t RESERVED4;
+
+    union
+    {
+        __IM uint8_t RMON;             /*!< (@ 0x0000000C) Month Capture Register                                     */
+
+        struct
+        {
+            __IM uint8_t MON1  : 4;    /*!< [3..0] 1-Month Capture Capture value for the ones place of months         */
+            __IM uint8_t MON10 : 1;    /*!< [4..4] 10-Month Capture Capture value for the tens place of
+                                        *   months                                                                    */
+            uint8_t : 3;
+        } RMON_b;
+    };
+    __IM uint8_t RESERVED5[3];
+} R_RTC_CP_Type;                       /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t E;              /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register                   */
+
+        struct
+        {
+            uint16_t             : 8;
+            __IOM uint16_t TRCLR : 1;  /*!< [8..8] Transaction Counter Clear                                          */
+            __IOM uint16_t TRENB : 1;  /*!< [9..9] Transaction Counter Enable                                         */
+            uint16_t             : 6;
+        } E_b;
+    };
+
+    union
+    {
+        __IOM uint16_t N;               /*!< (@ 0x00000002) Pipe Transaction Counter Register                          */
+
+        struct
+        {
+            __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter                                               */
+        } N_b;
+    };
+} R_USB_FS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
+            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
+            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
+            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
+            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
+            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
+        } AGTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
+            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
+            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
+            uint8_t              : 1;
+        } AGTMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+                                        *   ratio                                                                     */
+            uint8_t           : 4;
+            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
+        } AGTMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+                                        *   mode.                                                                     */
+            uint8_t             : 1;
+            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
+            uint8_t             : 1;
+            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
+            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
+        } AGTIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
+            uint8_t            : 5;
+        } AGTISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
+
+        struct
+        {
+            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
+            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
+            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
+            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
+            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
+            uint8_t              : 1;
+        } AGTCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_b;
+    };
+} R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
+
+        struct
+        {
+            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IM uint16_t                 RESERVED;
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
+} R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
+
+        struct
+        {
+            __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
+} R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
+
+/** @} */ /* End of group Device_Peripheral_clusters */
+
+/* =========================================================================================================================== */
+/* ================                            Device Specific Peripheral Section                             ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_peripherals
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ADC0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief A/D Converter (R_ADC0)
+ */
+
+typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure                                           */
+{
+    union
+    {
+        __IOM uint16_t ADCSR;          /*!< (@ 0x00000000) A/D Control Register                                       */
+
+        struct
+        {
+            __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog
+                                        *   input channel for double triggered operation. The setting
+                                        *   is only effective while double trigger mode is selected.                  */
+            uint16_t              : 1;
+            __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable                                  */
+            __IOM uint16_t DBLE   : 1; /*!< [7..7] Double Trigger Mode Select                                         */
+            __IOM uint16_t EXTRG  : 1; /*!< [8..8] Trigger Select                                                     */
+            __IOM uint16_t TRGE   : 1; /*!< [9..9] Trigger Start Enable                                               */
+            __IOM uint16_t ADHSC  : 1; /*!< [10..10] A/D Conversion Operation Mode Select                             */
+            uint16_t              : 1;
+            __IOM uint16_t ADIE   : 1; /*!< [12..12] Scan End Interrupt Enable                                        */
+            __IOM uint16_t ADCS   : 2; /*!< [14..13] Scan Mode Select                                                 */
+            __IOM uint16_t ADST   : 1; /*!< [15..15] A/D Conversion Start                                             */
+        } ADCSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADREF;           /*!< (@ 0x00000002) A/D status register                                        */
+
+        struct
+        {
+            __IOM uint8_t ADF : 1;     /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes
+                                        *   '1' while scanning.                                                       */
+            uint8_t              : 6;
+            __IM uint8_t ADSCACT : 1;  /*!< [7..7] Scanning status bit                                                */
+        } ADREF_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADEXREF;         /*!< (@ 0x00000003) A/D enhancing status register                              */
+
+        struct
+        {
+            __IOM uint8_t GBADF : 1;   /*!< [0..0] Group B scanning end flag bit.                                     */
+            uint8_t             : 7;
+        } ADEXREF_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADANSA[2];      /*!< (@ 0x00000004) A/D Channel Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t ANSA0  : 1; /*!< [0..0] AN Input Select                                                    */
+            __IOM uint16_t ANSA1  : 1; /*!< [1..1] AN Input Select                                                    */
+            __IOM uint16_t ANSA2  : 1; /*!< [2..2] AN Input Select                                                    */
+            __IOM uint16_t ANSA3  : 1; /*!< [3..3] AN Input Select                                                    */
+            __IOM uint16_t ANSA4  : 1; /*!< [4..4] AN Input Select                                                    */
+            __IOM uint16_t ANSA5  : 1; /*!< [5..5] AN Input Select                                                    */
+            __IOM uint16_t ANSA6  : 1; /*!< [6..6] AN Input Select                                                    */
+            __IOM uint16_t ANSA7  : 1; /*!< [7..7] AN Input Select                                                    */
+            __IOM uint16_t ANSA8  : 1; /*!< [8..8] AN Input Select                                                    */
+            __IOM uint16_t ANSA9  : 1; /*!< [9..9] AN Input Select                                                    */
+            __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select                                                  */
+            __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select                                                  */
+            __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select                                                  */
+            __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select                                                  */
+            __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select                                                  */
+            __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select                                                  */
+        } ADANSA_b[2];
+    };
+
+    union
+    {
+        __IOM uint16_t ADADS[2];       /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel
+                                        *                  Select Register                                            */
+
+        struct
+        {
+            __IOM uint16_t ADS0  : 1;  /*!< [0..0] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS1  : 1;  /*!< [1..1] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS2  : 1;  /*!< [2..2] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS3  : 1;  /*!< [3..3] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS4  : 1;  /*!< [4..4] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS5  : 1;  /*!< [5..5] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS6  : 1;  /*!< [6..6] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS7  : 1;  /*!< [7..7] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS8  : 1;  /*!< [8..8] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS9  : 1;  /*!< [9..9] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS10 : 1;  /*!< [10..10] A/D-Converted Value Addition/Average Channel Select              */
+            __IOM uint16_t ADS11 : 1;  /*!< [11..11] A/D-Converted Value Addition/Average Channel Select              */
+            __IOM uint16_t ADS12 : 1;  /*!< [12..12] A/D-Converted Value Addition/Average Channel Select              */
+            __IOM uint16_t ADS13 : 1;  /*!< [13..13] A/D-Converted Value Addition/Average Channel Select              */
+            __IOM uint16_t ADS14 : 1;  /*!< [14..14] A/D-Converted Value Addition/Average Channel Select              */
+            __IOM uint16_t ADS15 : 1;  /*!< [15..15] A/D-Converted Value Addition/Average Channel Select              */
+        } ADADS_b[2];
+    };
+
+    union
+    {
+        __IOM uint8_t ADADC;           /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t ADC : 3;     /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid
+                                        *   at the only setting of ADC[2:0] bits = 001b or 011b. When
+                                        *   average mode is selected by setting the ADADC.AVEE bit
+                                        *   to 1, do not set the addition count to three times (ADADC.ADC[2:0]
+                                        *   = 010b)                                                                   */
+            uint8_t            : 4;
+            __IOM uint8_t AVEE : 1;    /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected
+                                        *   by setting the ADADC.AVEE bit to 0, set the addition count
+                                        *   to 1, 2, 3, 4 or 16-time conversion. 16-time conversion
+                                        *   can only be used with 12-bit accuracy selected. NOTE: AVEE
+                                        *   bit is valid at the only setting of ADC[2:0] bits = 001b
+                                        *   or 011b. When average mode is selected by setting the ADADC.AVEE
+                                        *   bit to 1, do not set the addition count to three times
+                                        *   (ADADC.ADC[2:0] = 010b)                                                   */
+        } ADADC_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t ADCER;          /*!< (@ 0x0000000E) A/D Control Extended Register                              */
+
+        struct
+        {
+            uint16_t               : 1;
+            __IOM uint16_t ADPRC   : 2; /*!< [2..1] A/D Conversion Accuracy Specify                                    */
+            uint16_t               : 1;
+            __IOM uint16_t DCE     : 1; /*!< [4..4] Discharge Enable                                                   */
+            __IOM uint16_t ACE     : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable                        */
+            uint16_t               : 2;
+            __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select                           */
+            __IOM uint16_t DIAGLD  : 1; /*!< [10..10] Self-Diagnosis Mode Select                                       */
+            __IOM uint16_t DIAGM   : 1; /*!< [11..11] Self-Diagnosis Enable                                            */
+            uint16_t               : 2;
+            __IOM uint16_t ADINV   : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select           */
+            __IOM uint16_t ADRFMT  : 1; /*!< [15..15] A/D Data Register Format Select                                  */
+        } ADCER_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADSTRGR;        /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register               */
+
+        struct
+        {
+            __IOM uint16_t TRSB : 6;   /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect
+                                        *   the A/D conversion start trigger for group B in group scan
+                                        *   mode.                                                                     */
+            uint16_t            : 2;
+            __IOM uint16_t TRSA : 6;   /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion
+                                        *   start trigger in single scan mode and continuous mode.
+                                        *   In group scan mode, the A/D conversion start trigger for
+                                        *   group A is selected.                                                      */
+            uint16_t : 2;
+        } ADSTRGR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADEXICR;        /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register             */
+
+        struct
+        {
+            __IOM uint16_t TSSAD : 1;  /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average
+                                        *   Mode Select                                                               */
+            __IOM uint16_t OCSAD : 1;  /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average
+                                        *   Mode Select                                                               */
+            uint16_t            : 6;
+            __IOM uint16_t TSSA : 1;   /*!< [8..8] Temperature Sensor Output A/D Conversion Select                    */
+            __IOM uint16_t OCSA : 1;   /*!< [9..9] Internal Reference Voltage A/D Conversion Select                   */
+            __IOM uint16_t TSSB : 1;   /*!< [10..10] Temperature Sensor Output A/D Conversion Select for
+                                        *   Group B in group scan mode.                                               */
+            __IOM uint16_t OCSB : 1;   /*!< [11..11] Internal Reference Voltage A/D Conversion Select for
+                                        *   Group B in group scan mode.                                               */
+            uint16_t             : 2;
+            __IOM uint16_t EXSEL : 1;  /*!< [14..14] Extended Analog Input Select                                     */
+            __IOM uint16_t EXOEN : 1;  /*!< [15..15] Extended Analog Output Control                                   */
+        } ADEXICR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADANSB[2];      /*!< (@ 0x00000014) A/D Channel Select Register B                              */
+
+        struct
+        {
+            __IOM uint16_t ANSB0  : 1; /*!< [0..0] AN Input Select                                                    */
+            __IOM uint16_t ANSB1  : 1; /*!< [1..1] AN Input Select                                                    */
+            __IOM uint16_t ANSB2  : 1; /*!< [2..2] AN Input Select                                                    */
+            __IOM uint16_t ANSB3  : 1; /*!< [3..3] AN Input Select                                                    */
+            __IOM uint16_t ANSB4  : 1; /*!< [4..4] AN Input Select                                                    */
+            __IOM uint16_t ANSB5  : 1; /*!< [5..5] AN Input Select                                                    */
+            __IOM uint16_t ANSB6  : 1; /*!< [6..6] AN Input Select                                                    */
+            __IOM uint16_t ANSB7  : 1; /*!< [7..7] AN Input Select                                                    */
+            __IOM uint16_t ANSB8  : 1; /*!< [8..8] AN Input Select                                                    */
+            __IOM uint16_t ANSB9  : 1; /*!< [9..9] AN Input Select                                                    */
+            __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select                                                  */
+            __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select                                                  */
+            __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select                                                  */
+            __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select                                                  */
+            __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select                                                  */
+            __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select                                                  */
+        } ADANSB_b[2];
+    };
+
+    union
+    {
+        __IM uint16_t ADDBLDR;          /*!< (@ 0x00000018) A/D Data Duplication Register                              */
+
+        struct
+        {
+            __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
+                                         *   result of A/D conversion in response to the second trigger
+                                         *   in double trigger mode.                                                   */
+        } ADDBLDR_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADTSDR;          /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register                       */
+
+        struct
+        {
+            __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
+                                        *   A/D conversion result of temperature sensor output.                       */
+        } ADTSDR_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADOCDR;          /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register               */
+
+        struct
+        {
+            __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
+                                        *   A/D result of internal reference voltage.                                 */
+        } ADOCDR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint16_t ADRD_RIGHT;     /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified           */
+
+            struct
+            {
+                __IM uint16_t AD : 14;    /*!< [13..0] A/D-converted value (right-justified)The format for
+                                           *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
+                __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status                                            */
+            } ADRD_RIGHT_b;
+        };
+
+        union
+        {
+            __IM uint16_t ADRD_LEFT;       /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified            */
+
+            struct
+            {
+                __IM uint16_t DIAGST : 2;  /*!< [1..0] Self-Diagnosis Status                                              */
+                __IM uint16_t AD     : 14; /*!< [15..2] A/D-converted value (right-justified)The format for
+                                            *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
+            } ADRD_LEFT_b;
+        };
+    };
+
+    union
+    {
+        __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
+
+        struct
+        {
+            __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
+                                        *   storing the result of A/D conversion.                                     */
+        } ADDR_b[29];
+    };
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+    __IM uint16_t RESERVED3;
+
+    union
+    {
+        __IOM uint8_t ADAMPOFF;        /*!< (@ 0x00000062) A/D RRAMP off state register                               */
+
+        struct
+        {
+            __IOM uint8_t OPOFF : 8;   /*!< [7..0] OPOFF                                                              */
+        } ADAMPOFF_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADTSTPR;         /*!< (@ 0x00000063) A/D Test Protecting Release Register                       */
+
+        struct
+        {
+            __IOM uint8_t PRO  : 1;    /*!< [0..0] Test register protecting bit.                                      */
+            __IOM uint8_t B0WI : 1;    /*!< [1..1] Bit 0 writing permission bit.                                      */
+            uint8_t            : 6;
+        } ADTSTPR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADDDACER;       /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register                        */
+
+        struct
+        {
+            __IOM uint16_t WRION  : 5; /*!< [4..0] WRION                                                              */
+            uint16_t              : 3;
+            __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF                                                            */
+            uint16_t              : 2;
+            __IOM uint16_t ADHS   : 1; /*!< [15..15] ADHS                                                             */
+        } ADDDACER_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADSHCR;         /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register               */
+
+        struct
+        {
+            __IOM uint16_t SSTSH : 8;  /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time
+                                        *   Setting Set the sampling time (4 to 255 states)                           */
+            __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select                               */
+            __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select                               */
+            __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select                             */
+            uint16_t              : 5;
+        } ADSHCR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADEXTSTR;       /*!< (@ 0x00000068) A/D Enhancing Test Register                                */
+
+        struct
+        {
+            __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit
+                                        *   only for channel.                                                         */
+            uint16_t             : 1;
+            __IOM uint16_t SWTST : 2;  /*!< [5..4] Test selection bit for pressure switch.                            */
+            uint16_t             : 2;
+            __IOM uint16_t SHTRM : 2;  /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit
+                                        *   for adjustment to hardening of process.                                   */
+            uint16_t              : 1;
+            __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator
+                                        *   power save bit for A/D hard macro to hardening of process.                */
+            __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim
+                                        *   bit for A/D hard macro to hardening of process.                           */
+            __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim
+                                        *   bit for A/D hard macro to hardening of process.                           */
+        } ADEXTSTR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADTSTRA;           /*!< (@ 0x0000006A) A/D Test Register A                                        */
+
+        struct
+        {
+            __IOM uint16_t ATBUSSEL : 1;  /*!< [0..0] Analog test bus selection bit.                                     */
+            __IOM uint16_t TSTSWREF : 3;  /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit
+                                           *   amplifier test.Refreshing the pressure switch that opens
+                                           *   for the DAC output voltage charge period when the amplifier
+                                           *   of the S&H circuit is tested only for the channel is set.                 */
+            uint16_t            : 1;
+            __IOM uint16_t OCSW : 1;      /*!< [5..5] Internal reference voltage analog switch test control
+                                           *   bit.                                                                      */
+            __IOM uint16_t TSSW : 1;      /*!< [6..6] Temperature sensor output analogue switch test control
+                                           *   bit                                                                       */
+            uint16_t                 : 1;
+            __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog
+                                           *   module Details are described to the bit explanation.                      */
+            __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the
+                                           *   bit explanation.                                                          */
+        } ADTSTRA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADTSTRB;        /*!< (@ 0x0000006C) A/D Test Register B                                        */
+
+        struct
+        {
+            __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It
+                                        *   corresponds to ADVAL 14:0 input of A/D analog module.                     */
+            uint16_t : 1;
+        } ADTSTRB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADTSTRC;         /*!< (@ 0x0000006E) A/D Test Register C                                        */
+
+        struct
+        {
+            __IOM uint16_t ADMD : 8;    /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D
+                                         *   analog module.                                                            */
+            uint16_t               : 4;
+            __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit.              */
+            uint16_t               : 3;
+        } ADTSTRC_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADTSTRD;         /*!< (@ 0x00000070) A/D Test Register D                                        */
+
+        struct
+        {
+            __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It
+                                         *   corresponds to ADVAL 16 input of A/D analog module.                       */
+            uint16_t : 15;
+        } ADTSTRD_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADSWTSTR0;      /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0                 */
+
+        struct
+        {
+            __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit.                                   */
+            __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit.                                   */
+            __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit.                                   */
+            __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit.                                   */
+            __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit.                                   */
+            __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit.                                   */
+            uint16_t              : 10;
+        } ADSWTSTR0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADSWTSTR1;      /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1                 */
+
+        struct
+        {
+            __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit.                                   */
+            __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit.                                   */
+            __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit.                                   */
+            __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit.                                   */
+            __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit.                                   */
+            __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit.                                   */
+            uint16_t              : 10;
+        } ADSWTSTR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADSWTSTR2;        /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2                 */
+
+        struct
+        {
+            __IOM uint16_t EX0SW : 1;    /*!< [0..0] Test control of 0 enhancing input channel switches bit
+                                          *   (ANEX0 switch)                                                            */
+            __IOM uint16_t EX1SW : 1;    /*!< [1..1] Test control of one enhancing input channel switch bit
+                                          *   (ANEX1 switch).                                                           */
+            uint16_t                : 2;
+            __IOM uint16_t SHBYPS0  : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0.                          */
+            __IOM uint16_t SHBYPS1  : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1.                          */
+            __IOM uint16_t SHBYPS2  : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2.                          */
+            uint16_t                : 1;
+            __IOM uint16_t GRP0SW   : 1; /*!< [8..8] Test control of 0 group switches bit.                              */
+            __IOM uint16_t GRP1SW   : 1; /*!< [9..9] Test control of one group switch bit.                              */
+            __IOM uint16_t GRP2SW   : 1; /*!< [10..10] Test control of two group switches bit                           */
+            __IOM uint16_t GRP3SW   : 1; /*!< [11..11] Test control of two group switches bit                           */
+            __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1                */
+            uint16_t                : 3;
+        } ADSWTSTR2_b;
+    };
+    __IM uint16_t RESERVED4;
+
+    union
+    {
+        __IOM uint8_t ADDISCR;         /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register               */
+
+        struct
+        {
+            __IOM uint8_t ADNDIS : 4;  /*!< [3..0] The charging time                                                  */
+            __IOM uint8_t CHARGE : 1;  /*!< [4..4] Selection of Precharge or Discharge                                */
+            uint8_t              : 3;
+        } ADDISCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADSWCR;          /*!< (@ 0x0000007B) A/D Pressure Switch Control Register                       */
+
+        struct
+        {
+            __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing
+                                        *   the pressure switch in A/D analog module is set.                          */
+            uint8_t               : 1;
+            __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting                          */
+            uint8_t               : 1;
+        } ADSWCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADSHMSR;         /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register         */
+
+        struct
+        {
+            __IOM uint8_t SHMD : 1;    /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode
+                                        *   Select                                                                    */
+            uint8_t : 7;
+        } ADSHMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADICR;           /*!< (@ 0x0000007D) A/D Interrupt Control Register                             */
+
+        struct
+        {
+            __IOM uint8_t ADIC : 2;    /*!< [1..0] A/D Interrupt Control                                              */
+            uint8_t            : 6;
+        } ADICR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADACSR;          /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register              */
+
+        struct
+        {
+            uint8_t             : 1;
+            __IOM uint8_t ADSAC : 1;   /*!< [1..1] Successive Approximation Control Setting                           */
+            uint8_t             : 6;
+        } ADACSR_b;
+    };
+    __IM uint8_t RESERVED5;
+
+    union
+    {
+        __IOM uint16_t ADGSPCR;         /*!< (@ 0x00000080) A/D Group Scan Priority Control Register                   */
+
+        struct
+        {
+            __IOM uint16_t PGS : 1;     /*!< [0..0] Group A priority control setting bit.Note: When the PGS
+                                         *   bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be
+                                         *   set to 01b (group scan mode). If the bits are set to any
+                                         *   other values, proper operation is not guaranteed.                         */
+            __IOM uint16_t GBRSCN : 1;  /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved
+                                         *   when PGS = 0.)                                                            */
+            uint16_t               : 6;
+            __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B.                        */
+            uint16_t               : 6;
+            __IOM uint16_t GBRP    : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when
+                                         *   PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit
+                                         *   has been set to 1, single scan is performed continuously
+                                         *   for group B regardless of the setting of the GBRSCN bit.                  */
+        } ADGSPCR_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADGSCS;          /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group
+                                        *                  Scan)                                                      */
+
+        struct
+        {
+            __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan                                     */
+            __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan                                    */
+        } ADGSCS_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADDBLDRA;          /*!< (@ 0x00000084) A/D Data Duplexing Register A                              */
+
+        struct
+        {
+            __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
+                                          *   the result of A/D conversion in response to the respective
+                                          *   triggers during extended operation in double trigger mode.                */
+        } ADDBLDRA_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADDBLDRB;          /*!< (@ 0x00000086) A/D Data Duplexing Register B                              */
+
+        struct
+        {
+            __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
+                                          *   the result of A/D conversion in response to the respective
+                                          *   triggers during extended operation in double trigger mode.                */
+        } ADDBLDRB_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADSER;           /*!< (@ 0x00000088) A/D Sampling Extension Register                            */
+
+        struct
+        {
+            uint8_t             : 7;
+            __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
+        } ADSER_b;
+    };
+    __IM uint8_t RESERVED6;
+
+    union
+    {
+        __IOM uint8_t ADHVREFCNT;      /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage
+                                        *                  Control Register                                           */
+
+        struct
+        {
+            __IOM uint8_t HVSEL : 2;   /*!< [1..0] High-Potential Reference Voltage Select                            */
+            uint8_t             : 2;
+            __IOM uint8_t LVSEL : 1;   /*!< [4..4] Low-Potential Reference Voltage Select                             */
+            uint8_t             : 2;
+            __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
+        } ADHVREFCNT_b;
+    };
+    __IM uint8_t RESERVED7;
+
+    union
+    {
+        __IM uint8_t ADWINMON;         /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IM uint8_t MONCOMB : 1;  /*!< [0..0] Combination result monitorThis bit indicates the combination
+                                        *   result.This bit is valid when both window A operation and
+                                        *   window B operation are enabled.                                           */
+            uint8_t              : 3;
+            __IM uint8_t MONCMPA : 1;  /*!< [4..4] Comparison Result Monitor A                                        */
+            __IM uint8_t MONCMPB : 1;  /*!< [5..5] Comparison Result Monitor B                                        */
+            uint8_t              : 2;
+        } ADWINMON_b;
+    };
+    __IM uint8_t  RESERVED8;
+    __IM uint16_t RESERVED9;
+
+    union
+    {
+        __IOM uint16_t ADCMPCR;        /*!< (@ 0x00000090) A/D Compare Function Control Register                      */
+
+        struct
+        {
+            __IOM uint16_t CMPAB : 2;  /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits
+                                        *   are valid when both window A and window B are enabled (CMPAE
+                                        *   = 1 and CMPBE = 1).                                                       */
+            uint16_t              : 7;
+            __IOM uint16_t CMPBE  : 1; /*!< [9..9] Compare Window B Operation Enable                                  */
+            uint16_t              : 1;
+            __IOM uint16_t CMPAE  : 1; /*!< [11..11] Compare Window A Operation Enable                                */
+            uint16_t              : 1;
+            __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable                                       */
+            __IOM uint16_t WCMPE  : 1; /*!< [14..14] Window Function Setting                                          */
+            __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable                                       */
+        } ADCMPCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADCMPANSER;      /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input
+                                        *                  Select Register                                            */
+
+        struct
+        {
+            __IOM uint8_t CMPTSA : 1;  /*!< [0..0] Temperature sensor output Compare selection bit.                   */
+            __IOM uint8_t CMPOCA : 1;  /*!< [1..1] Internal reference voltage Compare selection bit.                  */
+            uint8_t              : 6;
+        } ADCMPANSER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADCMPLER;        /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input
+                                        *                  Comparison Condition Setting Register                      */
+
+        struct
+        {
+            __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison
+                                        *   Condition Select                                                          */
+            __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition
+                                        *   Select                                                                    */
+            uint8_t : 6;
+        } ADCMPLER_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPANSR[2];     /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select
+                                          *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t CMPCHA0  : 1; /*!< [0..0] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA1  : 1; /*!< [1..1] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA2  : 1; /*!< [2..2] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA3  : 1; /*!< [3..3] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA4  : 1; /*!< [4..4] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA5  : 1; /*!< [5..5] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA6  : 1; /*!< [6..6] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA7  : 1; /*!< [7..7] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA8  : 1; /*!< [8..8] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA9  : 1; /*!< [9..9] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select                                                  */
+            __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select                                                  */
+            __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select                                                  */
+            __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select                                                  */
+            __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select                                                  */
+            __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select                                                  */
+        } ADCMPANSR_b[2];
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPLR[2];        /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition
+                                           *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t CMPLCHA0  : 1; /*!< [0..0] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA1  : 1; /*!< [1..1] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA2  : 1; /*!< [2..2] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA3  : 1; /*!< [3..3] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA4  : 1; /*!< [4..4] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA5  : 1; /*!< [5..5] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA6  : 1; /*!< [6..6] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA7  : 1; /*!< [7..7] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA8  : 1; /*!< [8..8] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA9  : 1; /*!< [9..9] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input                                    */
+            __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input                                    */
+            __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input                                    */
+            __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input                                    */
+            __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input                                    */
+            __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input                                    */
+        } ADCMPLR_b[2];
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPDR0;          /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level
+                                           *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the
+                                           *   compare window A function is used. ADCMPDR0 sets the lower-side
+                                           *   level of window A.                                                        */
+        } ADCMPDR0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPDR1;          /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level
+                                           *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the
+                                           *   compare window A function is used. ADCMPDR1 sets the upper-side
+                                           *   level of window A..                                                       */
+        } ADCMPDR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPSR[2];         /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status
+                                            *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t CMPSTCHA0  : 1; /*!< [0..0] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA1  : 1; /*!< [1..1] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA2  : 1; /*!< [2..2] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA3  : 1; /*!< [3..3] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA4  : 1; /*!< [4..4] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA5  : 1; /*!< [5..5] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA6  : 1; /*!< [6..6] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA7  : 1; /*!< [7..7] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA8  : 1; /*!< [8..8] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA9  : 1; /*!< [9..9] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input                                   */
+            __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input                                   */
+            __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input                                   */
+            __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input                                   */
+            __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input                                   */
+            __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input                                   */
+        } ADCMPSR_b[2];
+    };
+
+    union
+    {
+        __IOM uint8_t ADCMPSER;         /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input
+                                         *                  Channel Status Register                                    */
+
+        struct
+        {
+            __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag
+                                         *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
+                                         *   this bit indicates the temperature sensor output comparison
+                                         *   result. When window A operation is disabled (ADCMPCR.CMPAE
+                                         *   = 0b), comparison conditions for CMPSTTSA are not met any
+                                         *   time.                                                                     */
+            __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag
+                                         *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
+                                         *   this bit indicates the temperature sensor output comparison
+                                         *   result. When window A operation is disabled (ADCMPCR.CMPAE
+                                         *   = 0b), comparison conditions for CMPSTTSA are not met any
+                                         *   time.                                                                     */
+            uint8_t : 6;
+        } ADCMPSER_b;
+    };
+    __IM uint8_t RESERVED10;
+
+    union
+    {
+        __IOM uint8_t ADCMPBNSR;       /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t CMPCHB : 6;  /*!< [5..0] Compare window B channel selection bit.The channel that
+                                        *   compares it on the condition of compare window B is selected.             */
+            uint8_t             : 1;
+            __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
+        } ADCMPBNSR_b;
+    };
+    __IM uint8_t RESERVED11;
+
+    union
+    {
+        __IOM uint16_t ADWINLLB;          /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level
+                                           *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is
+                                           *   used to set the lower level of the window B.                              */
+        } ADWINLLB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADWINULB;          /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level
+                                           *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is
+                                           *   used to set the higher level of the window B.                             */
+        } ADWINULB_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADCMPBSR;        /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register              */
+
+        struct
+        {
+            __IOM uint8_t CMPSTB : 1;  /*!< [0..0] Compare window B flag.It is a status flag that shows
+                                        *   the comparative result of CH (AN000-AN027, temperature
+                                        *   sensor, and internal reference voltage) made the object
+                                        *   of window B relation condition.                                           */
+            uint8_t : 7;
+        } ADCMPBSR_b;
+    };
+    __IM uint8_t  RESERVED12;
+    __IM uint16_t RESERVED13;
+
+    union
+    {
+        __IM uint16_t ADBUF0;          /*!< (@ 0x000000B0) A/D Data Buffer Register 0                                 */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF0_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF1;          /*!< (@ 0x000000B2) A/D Data Buffer Register 1                                 */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF1_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF2;          /*!< (@ 0x000000B4) A/D Data Buffer Register 2                                 */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF2_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF3;          /*!< (@ 0x000000B6) A/D Data Buffer Register 3                                 */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF3_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF4;          /*!< (@ 0x000000B8) A/D Data Buffer Register 4                                 */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF4_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF5;          /*!< (@ 0x000000BA) A/D Data Buffer Register 5                                 */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF5_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF6;          /*!< (@ 0x000000BC) A/D Data Buffer Register 6                                 */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF6_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF7;          /*!< (@ 0x000000BE) A/D Data Buffer Register 7                                 */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF7_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF8;          /*!< (@ 0x000000C0) A/D Data Buffer Register 8                                 */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF8_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF9;          /*!< (@ 0x000000C2) A/D Data Buffer Register 9                                 */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF9_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF10;         /*!< (@ 0x000000C4) A/D Data Buffer Register 10                                */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF10_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF11;         /*!< (@ 0x000000C6) A/D Data Buffer Register 11                                */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF11_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF12;         /*!< (@ 0x000000C8) A/D Data Buffer Register 12                                */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF12_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF13;         /*!< (@ 0x000000CA) A/D Data Buffer Register 13                                */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF13_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF14;         /*!< (@ 0x000000CC) A/D Data Buffer Register 14                                */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF14_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF15;         /*!< (@ 0x000000CE) A/D Data Buffer Register 15                                */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF15_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADBUFEN;         /*!< (@ 0x000000D0) A/D Data Buffer Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t BUFEN : 1;   /*!< [0..0] Data Buffer Enable                                                 */
+            uint8_t             : 7;
+        } ADBUFEN_b;
+    };
+    __IM uint8_t RESERVED14;
+
+    union
+    {
+        __IOM uint8_t ADBUFPTR;        /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register                           */
+
+        struct
+        {
+            __IM uint8_t BUFPTR : 4;   /*!< [3..0] Data Buffer PointerThese bits indicate the number of
+                                        *   data buffer to which the next A/D converted data is transferred.          */
+            __IM uint8_t PTROVF : 1;   /*!< [4..4] Pointer Overflow Flag                                              */
+            uint8_t             : 3;
+        } ADBUFPTR_b;
+    };
+    __IM uint8_t  RESERVED15;
+    __IM uint32_t RESERVED16[2];
+    __IM uint8_t  RESERVED17;
+
+    union
+    {
+        __IOM uint8_t ADSSTRL;         /*!< (@ 0x000000DD) A/D Sampling State Register L                              */
+
+        struct
+        {
+            __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (AN016-AN027)                                */
+        } ADSSTRL_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADSSTRT;         /*!< (@ 0x000000DE) A/D Sampling State Register T                              */
+
+        struct
+        {
+            __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (temperature sensor output)                  */
+        } ADSSTRT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADSSTRO;         /*!< (@ 0x000000DF) A/D Sampling State Register O                              */
+
+        struct
+        {
+            __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (Internal reference voltage)                 */
+        } ADSSTRO_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADSSTR[16];      /*!< (@ 0x000000E0) A/D Sampling State Registers                               */
+
+        struct
+        {
+            __IOM uint8_t SST : 8;     /*!< [7..0] Sampling time setting                                              */
+        } ADSSTR_b[16];
+    };
+
+    union
+    {
+        __IOM uint16_t ADANIM;         /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register                     */
+
+        struct
+        {
+            __IOM uint16_t ANIM0 : 1;  /*!< [0..0] Analog Channel Input Mode Select                                   */
+            __IOM uint16_t ANIM1 : 1;  /*!< [1..1] Analog Channel Input Mode Select                                   */
+            __IOM uint16_t ANIM2 : 1;  /*!< [2..2] Analog Channel Input Mode Select                                   */
+            __IOM uint16_t ANIM3 : 1;  /*!< [3..3] Analog Channel Input Mode Select                                   */
+            uint16_t             : 12;
+        } ADANIM_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADCALEXE;        /*!< (@ 0x000000F2) A/D Calibration Execution Register                         */
+
+        struct
+        {
+            uint8_t              : 6;
+            __IM uint8_t  CALMON : 1;  /*!< [6..6] Calibration Status Flag                                            */
+            __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
+        } ADCALEXE_b;
+    };
+    __IM uint8_t RESERVED18;
+
+    union
+    {
+        __IOM uint8_t VREFAMPCNT;        /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control
+                                          *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t OLDETEN   : 1; /*!< [0..0] OLDET Enable                                                       */
+            __IOM uint8_t VREFADCG  : 2; /*!< [2..1] VREFADC Output Voltage Control                                     */
+            __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable                                                    */
+            __IOM uint8_t BGREN     : 1; /*!< [4..4] BGR Enable                                                         */
+            uint8_t                 : 2;
+            __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
+        } VREFAMPCNT_b;
+    };
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
+
+    union
+    {
+        __IOM uint16_t ADRD;           /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register                           */
+
+        struct
+        {
+            __IM uint16_t AD : 16;     /*!< [15..0] Converted Value 15 to 0                                           */
+        } ADRD_b;
+    };
+
+    union
+    {
+        __IM uint8_t ADRST;            /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register                        */
+
+        struct
+        {
+            __IM uint8_t DIAGST : 2;   /*!< [1..0] Self-Diagnosis Status                                              */
+            uint8_t             : 6;
+        } ADRST_b;
+    };
+    __IM uint8_t  RESERVED21;
+    __IM uint32_t RESERVED22[41];
+
+    union
+    {
+        __IOM uint16_t ADPGACR;           /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register           */
+
+        struct
+        {
+            __IOM uint16_t P000SEL0  : 1; /*!< [0..0] A through amplifier is enable for PGA P000                         */
+            __IOM uint16_t P000SEL1  : 1; /*!< [1..1] The amplifier passing is enable for PGA P000                       */
+            __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000                                  */
+            __IOM uint16_t P000GEN   : 1; /*!< [3..3] PGA P000 gain setting and enable bit                               */
+            __IOM uint16_t P001SEL0  : 1; /*!< [4..4] A through amplifier is enable for PGA P001                         */
+            __IOM uint16_t P001SEL1  : 1; /*!< [5..5] The amplifier passing is enable for PGA P001                       */
+            __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001                                  */
+            __IOM uint16_t P001GEN   : 1; /*!< [7..7] PGA P001 gain setting and enable bit                               */
+            __IOM uint16_t P002SEL0  : 1; /*!< [8..8] A through amplifier is enable for PGA P002                         */
+            __IOM uint16_t P002SEL1  : 1; /*!< [9..9] The amplifier passing is enable for PGA P002                       */
+            __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002                                */
+            __IOM uint16_t P002GEN   : 1; /*!< [11..11] PGA P002 gain setting and enable bit                             */
+            __IOM uint16_t P003SEL0  : 1; /*!< [12..12] A through amplifier is enable for PGA P003                       */
+            __IOM uint16_t P003SEL1  : 1; /*!< [13..13] The amplifier passing is enable for PGA P003                     */
+            __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003                                */
+            __IOM uint16_t P003GEN   : 1; /*!< [15..15] PGA P003 gain setting and enable bit                             */
+        } ADPGACR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADPGAGS0;         /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting
+                                          *                  Register 0                                                 */
+
+        struct
+        {
+            __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=
+                                          *   b) when the shingle end is input and each PGA P000 is set.
+                                          *   When the differential motion is input, (ADPGSDCR0.P000GEN=1b)
+                                          *   sets the gain magnification when the differential motion
+                                          *   is input by the combination with ADPGSDCR0.P000DG 1:0.                    */
+            __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=
+                                          *   b) when the shingle end is input and each PGA P001 is set.
+                                          *   When the differential motion is input, (ADPGSDCR0.P001GEN=1b)
+                                          *   sets the gain magnification when the differential motion
+                                          *   is input by the combination with ADPGSDCR0.P001DG 1:0.                    */
+            __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of
+                                          *   (ADPGSDCR0.P002GEN=0b) when the shingle end is input and
+                                          *   each PGA P002 is set. When the differential motion is input,
+                                          *   (ADPGSDCR0.P002GEN=1b) sets the gain magnification when
+                                          *   the differential motion is input by the combination with
+                                          *   ADPGSDCR0.P002DG 1:0.                                                     */
+            __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of
+                                          *   (ADPGSDCR0.P003GEN=0b) when the shingle end is input and
+                                          *   each PGA P003 is set. When the differential motion is input,
+                                          *   (ADPGSDCR0.P003GEN=1b) sets the gain magnification when
+                                          *   the differential motion is input by the combination with
+                                          *   ADPGSDCR0.P003DG 1:0.                                                     */
+        } ADPGAGS0_b;
+    };
+    __IM uint32_t RESERVED23[3];
+
+    union
+    {
+        __IOM uint16_t ADPGADCR0;       /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential
+                                         *                  Input Control Register                                     */
+
+        struct
+        {
+            __IOM uint16_t P000DG : 2;  /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these
+                                         *   bits are used, set {P000DEN, P000GEN} to 11b.                             */
+            uint16_t               : 1;
+            __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable                                     */
+            __IOM uint16_t P001DG  : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these
+                                         *   bits are used, set {P001DEN, P001GEN} to 11b.                             */
+            uint16_t               : 1;
+            __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable                                     */
+            __IOM uint16_t P002DG  : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these
+                                         *   bits are used, set {P002DEN, P002GEN} to 11b.                             */
+            uint16_t               : 1;
+            __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable                                   */
+            __IOM uint16_t P003DG  : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these
+                                         *   bits are used, set {P003DEN, P003GEN} to 11b.                             */
+            uint16_t               : 1;
+            __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
+        } ADPGADCR0_b;
+    };
+    __IM uint16_t RESERVED24;
+
+    union
+    {
+        __IOM uint8_t ADPGADBS0;       /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential
+                                        *                  Input Bias Select Register 0                               */
+
+        struct
+        {
+            __IOM uint8_t P0BIAS : 1;  /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage
+                                        *   SelectNOTE: This bit selects the input bias voltage value
+                                        *   when differential inputs are used.                                        */
+            uint8_t : 7;
+        } ADPGADBS0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADPGADBS1;       /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential
+                                        *                  Input Bias Select Register 1                               */
+
+        struct
+        {
+            __IOM uint8_t P3BIAS : 1;  /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE:
+                                        *   This bit selects the input bias voltage value when differential
+                                        *   inputs are used.                                                          */
+            uint8_t : 7;
+        } ADPGADBS1_b;
+    };
+    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED26[10];
+
+    union
+    {
+        __IOM uint32_t ADREFMON;       /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register            */
+
+        struct
+        {
+            __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable                                          */
+            uint32_t              : 13;
+            __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit.                                    */
+            uint32_t              : 12;
+        } ADREFMON_b;
+    };
+} R_ADC0_Type;                         /*!< Size = 484 (0x1e4)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_PSCU                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Peripheral Security Control Unit (R_PSCU)
+ */
+
+typedef struct                         /*!< (@ 0x400E0000) R_PSCU Structure                                           */
+{
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t PSARB;          /*!< (@ 0x00000004) Peripheral Security Attribution Register B                 */
+
+        struct
+        {
+            uint32_t               : 1;
+            __IOM uint32_t PSARB1  : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution               */
+            __IOM uint32_t PSARB2  : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution               */
+            __IOM uint32_t PSARB3  : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution                */
+            uint32_t               : 2;
+            __IM uint32_t  PSARB6  : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution               */
+            __IOM uint32_t PSARB7  : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution               */
+            __IOM uint32_t PSARB8  : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution               */
+            __IOM uint32_t PSARB9  : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution               */
+            uint32_t               : 1;
+            __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution           */
+            __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution           */
+            uint32_t               : 2;
+            __IM uint32_t PSARB15  : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0
+                                         *   bit security attribution                                                  */
+            __IM uint32_t PSARB16  : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution            */
+            uint32_t               : 1;
+            __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution           */
+            __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution           */
+            uint32_t               : 2;
+            __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution            */
+            __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution            */
+            __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution            */
+            __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution            */
+            __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution            */
+            __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution            */
+            __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution            */
+            __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution            */
+            __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution            */
+            __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution            */
+        } PSARB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PSARC;           /*!< (@ 0x00000008) Peripheral Security Attribution Register C                 */
+
+        struct
+        {
+            __IOM uint32_t PSARC0  : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution                */
+            __IOM uint32_t PSARC1  : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution                */
+            uint32_t               : 1;
+            __IOM uint32_t PSARC3  : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution               */
+            uint32_t               : 4;
+            __IOM uint32_t PSARC8  : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution              */
+            uint32_t               : 3;
+            __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution           */
+            __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution             */
+            uint32_t               : 6;
+            __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution             */
+            uint32_t               : 6;
+            __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution          */
+            uint32_t               : 3;
+            __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution            */
+        } PSARC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PSARD;           /*!< (@ 0x0000000C) Peripheral Security Attribution Register D                 */
+
+        struct
+        {
+            __IOM uint32_t PSARD0  : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution               */
+            __IOM uint32_t PSARD1  : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution               */
+            __IOM uint32_t PSARD2  : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution               */
+            __IOM uint32_t PSARD3  : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution               */
+            uint32_t               : 7;
+            __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution            */
+            __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution            */
+            __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution            */
+            __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution            */
+            __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution            */
+            __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution            */
+            uint32_t               : 2;
+            __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution          */
+            __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution          */
+            uint32_t               : 1;
+            __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution             */
+            uint32_t               : 2;
+            __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution         */
+            __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution         */
+            __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution         */
+            __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution         */
+            uint32_t               : 3;
+        } PSARD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PSARE;           /*!< (@ 0x00000010) Peripheral Security Attribution Register E                 */
+
+        struct
+        {
+            __IOM uint32_t PSARE0  : 1; /*!< [0..0] WDT security attribution                                           */
+            __IOM uint32_t PSARE1  : 1; /*!< [1..1] IWDT security attribution                                          */
+            __IOM uint32_t PSARE2  : 1; /*!< [2..2] RTC security attribution                                           */
+            uint32_t               : 11;
+            __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution            */
+            __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution            */
+            uint32_t               : 6;
+            __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution            */
+            __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution            */
+            __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution            */
+            __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution            */
+            __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution            */
+            __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution            */
+            __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution            */
+            __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution            */
+            __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution            */
+            __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution            */
+        } PSARE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSSAR;          /*!< (@ 0x00000014) Module Stop Security Attribution Register                  */
+
+        struct
+        {
+            __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution                       */
+            __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution                       */
+            __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution                        */
+            __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution                        */
+            uint32_t              : 28;
+        } MSSAR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFSAMONA;       /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
+                                        *                  A                                                          */
+
+        struct
+        {
+            uint32_t            : 15;
+            __IOM uint32_t CFS2 : 9;   /*!< [23..15] Code Flash Secure area 2                                         */
+            uint32_t            : 8;
+        } CFSAMONA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFSAMONB;       /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
+                                        *                  B                                                          */
+
+        struct
+        {
+            uint32_t            : 10;
+            __IOM uint32_t CFS1 : 14;  /*!< [23..10] Code Flash Secure area 1                                         */
+            uint32_t            : 8;
+        } CFSAMONB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DFSAMON;        /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register           */
+
+        struct
+        {
+            uint32_t           : 10;
+            __IOM uint32_t DFS : 6;    /*!< [15..10] Data flash Secure area                                           */
+            uint32_t           : 16;
+        } DFSAMON_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SSAMONA;        /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A               */
+
+        struct
+        {
+            uint32_t           : 13;
+            __IOM uint32_t SS2 : 8;    /*!< [20..13] SRAM Secure area 2                                               */
+            uint32_t           : 11;
+        } SSAMONA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SSAMONB;        /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B               */
+
+        struct
+        {
+            uint32_t           : 10;
+            __IOM uint32_t SS1 : 11;   /*!< [20..10] SRAM secure area 1                                               */
+            uint32_t           : 11;
+        } SSAMONB_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLMMON;          /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register         */
+
+        struct
+        {
+            __IM uint32_t DLMMON : 4;  /*!< [3..0] Device Lifecycle Management State Monitor                          */
+            uint32_t             : 28;
+        } DLMMON_b;
+    };
+} R_PSCU_Type;                         /*!< Size = 48 (0x30)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_BUS                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Bus Interface (R_BUS)
+ */
+
+typedef struct                          /*!< (@ 0x40003000) R_BUS Structure                                            */
+{
+    __IOM R_BUS_CSa_Type CSa[8];        /*!< (@ 0x00000000) CS Registers                                               */
+    __IM uint32_t        RESERVED[480];
+    __IOM R_BUS_CSb_Type CSb[8];        /*!< (@ 0x00000800) CS Registers                                               */
+
+    union
+    {
+        __IOM uint16_t CSRECEN;         /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register                */
+
+        struct
+        {
+            __IOM uint16_t RCVEN0  : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN1  : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN2  : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN3  : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN4  : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN5  : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN6  : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN7  : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable                    */
+            __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable                    */
+            __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable                  */
+            __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable                  */
+            __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable                  */
+            __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable                  */
+            __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable                  */
+            __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable                  */
+        } CSRECEN_b;
+    };
+    __IM uint16_t           RESERVED1;
+    __IM uint32_t           RESERVED2[223];
+    __IOM R_BUS_SDRAM_Type  SDRAM;      /*!< (@ 0x00000C00) SDRAM Registers                                            */
+    __IM uint32_t           RESERVED3[235];
+    __IOM R_BUS_BUSM_Type   BUSM[6];    /*!< (@ 0x00001000) Master Bus Control Register Array                          */
+    __IM uint32_t           RESERVED4[58];
+    __IOM R_BUS_BUSS_Type   BUSS[16];   /*!< (@ 0x00001100) Slave Bus Control Register Array                           */
+    __IM uint32_t           RESERVED5[432];
+    __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers                                        */
+} R_BUS_Type;                           /*!< Size = 6320 (0x18b0)                                                      */
+
+/* =========================================================================================================================== */
+/* ================                                           R_CAC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC)
+ */
+
+typedef struct                         /*!< (@ 0x40083600) R_CAC Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t CACR0;           /*!< (@ 0x00000000) CAC Control Register 0                                     */
+
+        struct
+        {
+            __IOM uint8_t CFME : 1;    /*!< [0..0] Clock Frequency Measurement Enable.                                */
+            uint8_t            : 7;
+        } CACR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CACR1;           /*!< (@ 0x00000001) CAC Control Register 1                                     */
+
+        struct
+        {
+            __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable                                            */
+            __IOM uint8_t FMCS    : 3; /*!< [3..1] Measurement Target Clock Select                                    */
+            __IOM uint8_t TCSS    : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select           */
+            __IOM uint8_t EDGES   : 2; /*!< [7..6] Valid Edge Select                                                  */
+        } CACR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CACR2;           /*!< (@ 0x00000002) CAC Control Register 2                                     */
+
+        struct
+        {
+            __IOM uint8_t RPS  : 1;    /*!< [0..0] Reference Signal Select                                            */
+            __IOM uint8_t RSCS : 3;    /*!< [3..1] Measurement Reference Clock Select                                 */
+            __IOM uint8_t RCDS : 2;    /*!< [5..4] Measurement Reference Clock Frequency Division Ratio
+                                        *   Select                                                                    */
+            __IOM uint8_t DFS : 2;     /*!< [7..6] Digital Filter Selection                                           */
+        } CACR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CAICR;           /*!< (@ 0x00000003) CAC Interrupt Control Register                             */
+
+        struct
+        {
+            __IOM uint8_t FERRIE : 1;  /*!< [0..0] Frequency Error Interrupt Request Enable                           */
+            __IOM uint8_t MENDIE : 1;  /*!< [1..1] Measurement End Interrupt Request Enable                           */
+            __IOM uint8_t OVFIE  : 1;  /*!< [2..2] Overflow Interrupt Request Enable                                  */
+            uint8_t              : 1;
+            __OM uint8_t FERRFCL : 1;  /*!< [4..4] FERRF Clear                                                        */
+            __OM uint8_t MENDFCL : 1;  /*!< [5..5] MENDF Clear                                                        */
+            __OM uint8_t OVFFCL  : 1;  /*!< [6..6] OVFF Clear                                                         */
+            uint8_t              : 1;
+        } CAICR_b;
+    };
+
+    union
+    {
+        __IM uint8_t CASTR;            /*!< (@ 0x00000004) CAC Status Register                                        */
+
+        struct
+        {
+            __IM uint8_t FERRF : 1;    /*!< [0..0] Frequency Error Flag                                               */
+            __IM uint8_t MENDF : 1;    /*!< [1..1] Measurement End Flag                                               */
+            __IM uint8_t OVFF  : 1;    /*!< [2..2] Counter Overflow Flag                                              */
+            uint8_t            : 5;
+        } CASTR_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t CAULVR;          /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register                     */
+
+        struct
+        {
+            __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores
+                                         *   the upper-limit value of the frequency.                                   */
+        } CAULVR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t CALLVR;          /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register                     */
+
+        struct
+        {
+            __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores
+                                         *   the lower-limit value of the frequency.                                   */
+        } CALLVR_b;
+    };
+
+    union
+    {
+        __IM uint16_t CACNTBR;          /*!< (@ 0x0000000A) CAC Counter Buffer Register                                */
+
+        struct
+        {
+            __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains
+                                         *   the counter value at the time a valid reference signal
+                                         *   edge is input                                                             */
+        } CACNTBR_b;
+    };
+} R_CAC_Type;                           /*!< Size = 12 (0xc)                                                           */
+
+/* =========================================================================================================================== */
+/* ================                                         R_CANFD0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD0)
+ */
+
+typedef struct                         /*!< (@ 0x400B0000) R_CANFD0 Structure                                         */
+{
+    __IOM R_CANFD_CFDC_Type CFDC[1];   /*!< (@ 0x00000000) Channel Control/Status                                     */
+    __IM uint32_t           RESERVED;
+
+    union
+    {
+        __IOM uint32_t CFDGCFG;        /*!< (@ 0x00000014) Global Configuration Register                              */
+
+        struct
+        {
+            __IOM uint32_t TPRI  : 1;  /*!< [0..0] Transmission Priority                                              */
+            __IOM uint32_t DCE   : 1;  /*!< [1..1] DLC Check Enable                                                   */
+            __IOM uint32_t DRE   : 1;  /*!< [2..2] DLC Replacement Enable                                             */
+            __IOM uint32_t MME   : 1;  /*!< [3..3] Mirror Mode Enable                                                 */
+            __IOM uint32_t DCS   : 1;  /*!< [4..4] Data Link Controller Clock Select                                  */
+            __IOM uint32_t CMPOC : 1;  /*!< [5..5] CAN-FD message Payload overflow configuration                      */
+            uint32_t             : 2;
+            __IOM uint32_t TSP   : 4;  /*!< [11..8] Timestamp Prescaler                                               */
+            __IOM uint32_t TSSS  : 1;  /*!< [12..12] Timestamp Source Select                                          */
+            uint32_t             : 3;
+            __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler                         */
+        } CFDGCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGCTR;         /*!< (@ 0x00000018) Global Control Register                                    */
+
+        struct
+        {
+            __IOM uint32_t GMDC    : 2; /*!< [1..0] Global Mode Control                                                */
+            __IOM uint32_t GSLPR   : 1; /*!< [2..2] Global Sleep Request                                               */
+            uint32_t               : 5;
+            __IOM uint32_t DEIE    : 1; /*!< [8..8] DLC check Interrupt Enable                                         */
+            __IOM uint32_t MEIE    : 1; /*!< [9..9] Message lost Error Interrupt Enable                                */
+            __IOM uint32_t THLEIE  : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable                      */
+            __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable            */
+            uint32_t               : 4;
+            __IOM uint32_t TSRST   : 1; /*!< [16..16] Timestamp Reset                                                  */
+            uint32_t               : 15;
+        } CFDGCTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGSTS;         /*!< (@ 0x0000001C) Global Status Register                                     */
+
+        struct
+        {
+            __IM uint32_t GRSTSTS  : 1; /*!< [0..0] Global Reset Status                                                */
+            __IM uint32_t GHLTSTS  : 1; /*!< [1..1] Global Halt Status                                                 */
+            __IM uint32_t GSLPSTS  : 1; /*!< [2..2] Global Sleep Status                                                */
+            __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation                                          */
+            uint32_t               : 28;
+        } CFDGSTS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGERFL;       /*!< (@ 0x00000020) Global Error Flag Register                                 */
+
+        struct
+        {
+            __IOM uint32_t DEF   : 1;  /*!< [0..0] DLC Error Flag                                                     */
+            __IM uint32_t  MES   : 1;  /*!< [1..1] Message Lost Error Status                                          */
+            __IM uint32_t  THLES : 1;  /*!< [2..2] TX History List Entry Lost Error Status                            */
+            __IOM uint32_t CMPOF : 1;  /*!< [3..3] CAN-FD message payload overflow Flag                               */
+            uint32_t             : 12;
+            __IOM uint32_t EEF0  : 1;  /*!< [16..16] ECC Error Flag for Channel 0                                     */
+            uint32_t             : 15;
+        } CFDGERFL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGTSC;        /*!< (@ 0x00000024) Global Timestamp Counter Register                          */
+
+        struct
+        {
+            __IM uint32_t TS : 16;     /*!< [15..0] Timestamp Value                                                   */
+            uint32_t         : 16;
+        } CFDGTSC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGAFLECTR;    /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register       */
+
+        struct
+        {
+            __IOM uint32_t AFLPN  : 4; /*!< [3..0] Acceptance Filter List Page Number                                 */
+            uint32_t              : 4;
+            __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable                          */
+            uint32_t              : 23;
+        } CFDGAFLECTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGAFLCFG0;    /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register
+                                        *                  0                                                          */
+
+        struct
+        {
+            __IOM uint32_t RNC1 : 9;   /*!< [8..0] Rule Number for Channel 1                                          */
+            uint32_t            : 7;
+            __IOM uint32_t RNC0 : 9;   /*!< [24..16] Rule Number for Channel 0                                        */
+            uint32_t            : 7;
+        } CFDGAFLCFG0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDRMNB;        /*!< (@ 0x00000030) RX Message Buffer Number Register                          */
+
+        struct
+        {
+            __IOM uint32_t NRXMB : 8;  /*!< [7..0] Number of RX Message Buffers                                       */
+            __IOM uint32_t RMPLS : 3;  /*!< [10..8] Reception Message Buffer Payload Data Size                        */
+            uint32_t             : 21;
+        } CFDRMNB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDRMND0;       /*!< (@ 0x00000034) RX Message Buffer New Data Register 0                      */
+
+        struct
+        {
+            __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status                                 */
+        } CFDRMND0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDRMIEC;       /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t RMIE : 32;  /*!< [31..0] RX Message Buffer Interrupt Enable                                */
+        } CFDRMIEC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDRFCC[2];     /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers                  */
+
+        struct
+        {
+            __IOM uint32_t RFE    : 1; /*!< [0..0] RX FIFO Enable                                                     */
+            __IOM uint32_t RFIE   : 1; /*!< [1..1] RX FIFO Interrupt Enable                                           */
+            uint32_t              : 2;
+            __IOM uint32_t RFPLS  : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration                            */
+            uint32_t              : 1;
+            __IOM uint32_t RFDC   : 3; /*!< [10..8] RX FIFO Depth Configuration                                       */
+            uint32_t              : 1;
+            __IOM uint32_t RFIM   : 1; /*!< [12..12] RX FIFO Interrupt Mode                                           */
+            __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value                       */
+            uint32_t              : 16;
+        } CFDRFCC_b[2];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDRFSTS[2];    /*!< (@ 0x00000044) RX FIFO Status Registers                                   */
+
+        struct
+        {
+            __IM uint32_t  RFEMP : 1;  /*!< [0..0] RX FIFO Empty                                                      */
+            __IM uint32_t  RFFLL : 1;  /*!< [1..1] RX FIFO Full                                                       */
+            __IOM uint32_t RFMLT : 1;  /*!< [2..2] RX FIFO Message Lost                                               */
+            __IOM uint32_t RFIF  : 1;  /*!< [3..3] RX FIFO Interrupt Flag                                             */
+            uint32_t             : 4;
+            __IM uint32_t RFMC   : 8;  /*!< [15..8] RX FIFO Message Count                                             */
+            uint32_t             : 16;
+        } CFDRFSTS_b[2];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDRFPCTR[2];   /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers                          */
+
+        struct
+        {
+            __OM uint32_t RFPC : 8;    /*!< [7..0] RX FIFO Pointer Control                                            */
+            uint32_t           : 24;
+        } CFDRFPCTR_b[2];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDCFCC[1];     /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers              */
+
+        struct
+        {
+            __IOM uint32_t CFE    : 1; /*!< [0..0] Common FIFO Enable                                                 */
+            __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable                                    */
+            __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CFPLS  : 3; /*!< [6..4] Common FIFO Payload Data size configuration                        */
+            uint32_t              : 1;
+            __IOM uint32_t CFM    : 2; /*!< [9..8] Common FIFO Mode                                                   */
+            __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select                         */
+            __IOM uint32_t CFITR  : 1; /*!< [11..11] Common FIFO Interval Timer Resolution                            */
+            __IOM uint32_t CFIM   : 1; /*!< [12..12] Common FIFO Interrupt Mode                                       */
+            __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value                   */
+            __IOM uint32_t CFTML  : 5; /*!< [20..16] Common FIFO TX Message Buffer Link                               */
+            __IOM uint32_t CFDC   : 3; /*!< [23..21] Common FIFO Depth Configuration                                  */
+            __IOM uint32_t CFITT  : 8; /*!< [31..24] Common FIFO Interval Transmission Time                           */
+        } CFDCFCC_b[1];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDCFSTS[1];    /*!< (@ 0x00000058) Common FIFO Status Registers                               */
+
+        struct
+        {
+            __IM uint32_t  CFEMP  : 1; /*!< [0..0] Common FIFO Empty                                                  */
+            __IM uint32_t  CFFLL  : 1; /*!< [1..1] Common FIFO Full                                                   */
+            __IOM uint32_t CFMLT  : 1; /*!< [2..2] Common FIFO Message Lost                                           */
+            __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag                                      */
+            __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag                                      */
+            uint32_t              : 3;
+            __IM uint32_t CFMC    : 8; /*!< [15..8] Common FIFO Message Count                                         */
+            uint32_t              : 16;
+        } CFDCFSTS_b[1];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDCFPCTR[1];   /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers                      */
+
+        struct
+        {
+            __OM uint32_t CFPC : 8;    /*!< [7..0] Common FIFO Pointer Control                                        */
+            uint32_t           : 24;
+        } CFDCFPCTR_b[1];
+    };
+
+    union
+    {
+        __IM uint32_t CFDFESTS;        /*!< (@ 0x00000060) FIFO Empty Status Register                                 */
+
+        struct
+        {
+            __IM uint32_t RFXEMP : 2;  /*!< [1..0] RX FIF0 Empty Status                                               */
+            uint32_t             : 6;
+            __IM uint32_t CFXEMP : 1;  /*!< [8..8] Common FIF0 Empty Status                                           */
+            uint32_t             : 23;
+        } CFDFESTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDFFSTS;        /*!< (@ 0x00000064) FIFO Full Status Register                                  */
+
+        struct
+        {
+            __IM uint32_t RFXFLL : 2;  /*!< [1..0] RX FIF0 Full Status                                                */
+            uint32_t             : 6;
+            __IM uint32_t CFXFLL : 1;  /*!< [8..8] Common FIF0 Full Status                                            */
+            uint32_t             : 23;
+        } CFDFFSTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDFMSTS;        /*!< (@ 0x00000068) FIFO Message Lost Status Register                          */
+
+        struct
+        {
+            __IM uint32_t RFXMLT : 2;  /*!< [1..0] RX FIFO Msg Lost Status                                            */
+            uint32_t             : 6;
+            __IM uint32_t CFXMLT : 1;  /*!< [8..8] Common FIFO Msg Lost Status                                        */
+            uint32_t             : 23;
+        } CFDFMSTS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDRFISTS;      /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register                     */
+
+        struct
+        {
+            __IM uint32_t RFXIF : 1;   /*!< [0..0] RX FIFO[x] Interrupt Flag Status                                   */
+            uint32_t            : 31;
+        } CFDRFISTS_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CFDTMC[4];       /*!< (@ 0x00000070) TX Message Buffer Control Registers                        */
+
+        struct
+        {
+            __IOM uint8_t TMTR  : 1;   /*!< [0..0] TX Message Buffer Transmission Request                             */
+            __IOM uint8_t TMTAR : 1;   /*!< [1..1] TX Message Buffer Transmission abort Request                       */
+            __IOM uint8_t TMOM  : 1;   /*!< [2..2] TX Message Buffer One-shot Mode                                    */
+            uint8_t             : 5;
+        } CFDTMC_b[4];
+    };
+
+    union
+    {
+        __IOM uint8_t CFDTMSTS[4];     /*!< (@ 0x00000074) TX Message Buffer Status Registers                         */
+
+        struct
+        {
+            __IM uint8_t  TMTSTS : 1;  /*!< [0..0] TX Message Buffer Transmission Status                              */
+            __IOM uint8_t TMTRF  : 2;  /*!< [2..1] TX Message Buffer Transmission Result Flag                         */
+            __IM uint8_t  TMTRM  : 1;  /*!< [3..3] TX Message Buffer Transmission Request Mirrored                    */
+            __IM uint8_t  TMTARM : 1;  /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored              */
+            uint8_t              : 3;
+        } CFDTMSTS_b[4];
+    };
+
+    union
+    {
+        __IM uint32_t CFDTMTRSTS[1];       /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status
+                                            *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status                      */
+            uint32_t                  : 28;
+        } CFDTMTRSTS_b[1];
+    };
+
+    union
+    {
+        __IM uint32_t CFDTMTARSTS[1];       /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request
+                                             *                  Status Register                                            */
+
+        struct
+        {
+            __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status                */
+            uint32_t                   : 28;
+        } CFDTMTARSTS_b[1];
+    };
+
+    union
+    {
+        __IM uint32_t CFDTMTCSTS[1];       /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status
+                                            *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status                   */
+            uint32_t                  : 28;
+        } CFDTMTCSTS_b[1];
+    };
+
+    union
+    {
+        __IM uint32_t CFDTMTASTS[1];       /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register       */
+
+        struct
+        {
+            __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status                        */
+            uint32_t                  : 28;
+        } CFDTMTASTS_b[1];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDTMIEC[1];    /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t TMIEg : 4;  /*!< [3..0] TX Message Buffer Interrupt Enable                                 */
+            uint32_t             : 28;
+        } CFDTMIEC_b[1];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDTXQCC0[1];    /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0               */
+
+        struct
+        {
+            __IOM uint32_t TXQE    : 1; /*!< [0..0] TX Queue Enable                                                    */
+            uint32_t               : 4;
+            __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
+            uint32_t               : 1;
+            __IOM uint32_t TXQIM   : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
+            __IOM uint32_t TXQDC   : 2; /*!< [9..8] TX Queue Depth Configuration                                       */
+            uint32_t               : 22;
+        } CFDTXQCC0_b[1];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDTXQSTS0[1];   /*!< (@ 0x00000090) TX Queue Status Registers 0                                */
+
+        struct
+        {
+            __IM uint32_t  TXQEMP  : 1; /*!< [0..0] TX Queue Empty                                                     */
+            __IM uint32_t  TXQFLL  : 1; /*!< [1..1] TX Queue Full                                                      */
+            __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
+            uint32_t               : 5;
+            __IM uint32_t TXQMC    : 6; /*!< [13..8] TX Queue Message Count                                            */
+            uint32_t               : 18;
+        } CFDTXQSTS0_b[1];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0                       */
+
+        struct
+        {
+            __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
+            uint32_t            : 24;
+        } CFDTXQPCTR0_b[1];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDTHLCC[1];    /*!< (@ 0x00000098) TX History List Configuration / Control Register           */
+
+        struct
+        {
+            __IOM uint32_t THLE   : 1; /*!< [0..0] TX History List Enable                                             */
+            uint32_t              : 7;
+            __IOM uint32_t THLIE  : 1; /*!< [8..8] TX History List Interrupt Enable                                   */
+            __IOM uint32_t THLIM  : 1; /*!< [9..9] TX History List Interrupt Mode                                     */
+            __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable                              */
+            uint32_t              : 21;
+        } CFDTHLCC_b[1];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDTHLSTS[1];   /*!< (@ 0x0000009C) TX History List Status Register                            */
+
+        struct
+        {
+            __IM uint32_t  THLEMP : 1; /*!< [0..0] TX History List Empty                                              */
+            __IM uint32_t  THLFLL : 1; /*!< [1..1] TX History List Full                                               */
+            __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost                                         */
+            __IOM uint32_t THLIF  : 1; /*!< [3..3] TX History List Interrupt Flag                                     */
+            uint32_t              : 4;
+            __IM uint32_t THLMC   : 6; /*!< [13..8] TX History List Message Count                                     */
+            uint32_t              : 18;
+        } CFDTHLSTS_b[1];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDTHLPCTR[1];  /*!< (@ 0x000000A0) TX History List Pointer Control Registers                  */
+
+        struct
+        {
+            __OM uint32_t THLPC : 8;   /*!< [7..0] TX History List Pointer Control                                    */
+            uint32_t            : 24;
+        } CFDTHLPCTR_b[1];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGTINTSTS0;   /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0                      */
+
+        struct
+        {
+            __IM uint32_t TSIF0  : 1;  /*!< [0..0] TX Successful Interrupt Flag Channel 0                             */
+            __IM uint32_t TAIF0  : 1;  /*!< [1..1] TX Abort Interrupt Flag Channel 0                                  */
+            __IM uint32_t TQIF0  : 1;  /*!< [2..2] TX Queue Interrupt Flag Channel 0                                  */
+            __IM uint32_t CFTIF0 : 1;  /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0                       */
+            __IM uint32_t THIF0  : 1;  /*!< [4..4] TX History List Interrupt Channel 0                                */
+            uint32_t             : 27;
+        } CFDGTINTSTS0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGTSTCFG;     /*!< (@ 0x000000A8) Global Test Configuration Register                         */
+
+        struct
+        {
+            uint32_t             : 16;
+            __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select                                        */
+            uint32_t             : 6;
+        } CFDGTSTCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGTSTCTR;     /*!< (@ 0x000000AC) Global Test Control Register                               */
+
+        struct
+        {
+            uint32_t            : 2;
+            __IOM uint32_t RTME : 1;   /*!< [2..2] RAM Test Mode Enable                                               */
+            uint32_t            : 29;
+        } CFDGTSTCTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGFDCFG;      /*!< (@ 0x000000B0) Global FD Configuration register                           */
+
+        struct
+        {
+            __IOM uint32_t RPED   : 1; /*!< [0..0] RES bit Protocol exception disable                                 */
+            uint32_t              : 7;
+            __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration                                    */
+            uint32_t              : 22;
+        } CFDGFDCFG_b;
+    };
+    __IM uint32_t RESERVED1;
+
+    union
+    {
+        __IOM uint32_t CFDGLOCKK;      /*!< (@ 0x000000B8) Global Lock Key Register                                   */
+
+        struct
+        {
+            __OM uint32_t LOCK : 16;   /*!< [15..0] Lock Key                                                          */
+            uint32_t           : 16;
+        } CFDGLOCKK_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t CFDGAFLIGNENT;  /*!< (@ 0x000000C0) Global AFL Ignore Entry Register                           */
+
+        struct
+        {
+            __IOM uint32_t IRN : 5;    /*!< [4..0] Ignore Rule Number                                                 */
+            uint32_t           : 27;
+        } CFDGAFLIGNENT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGAFLIGNCTR;  /*!< (@ 0x000000C4) Global AFL Ignore Control Register                         */
+
+        struct
+        {
+            __IOM uint32_t IREN : 1;   /*!< [0..0] Ignore Rule Enable                                                 */
+            uint32_t            : 7;
+            __OM uint32_t KEY   : 8;   /*!< [15..8] Key code                                                          */
+            uint32_t            : 16;
+        } CFDGAFLIGNCTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDCDTCT;        /*!< (@ 0x000000C8) DMA Transfer Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0                                   */
+            __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1                                   */
+            uint32_t               : 6;
+            __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0                 */
+            uint32_t               : 23;
+        } CFDCDTCT_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDCDTSTS;         /*!< (@ 0x000000CC) DMA Transfer Status Register                               */
+
+        struct
+        {
+            __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0                                  */
+            __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1                                  */
+            uint32_t                : 6;
+            __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel
+                                          *   0                                                                         */
+            uint32_t : 23;
+        } CFDCDTSTS_b;
+    };
+    __IM uint32_t RESERVED3[2];
+
+    union
+    {
+        __IOM uint32_t CFDGRSTC;       /*!< (@ 0x000000D8) Global SW reset Register                                   */
+
+        struct
+        {
+            __IOM uint32_t SRST : 1;   /*!< [0..0] SW reset                                                           */
+            uint32_t            : 7;
+            __OM uint32_t KEY   : 8;   /*!< [15..8] Key code                                                          */
+            uint32_t            : 16;
+        } CFDGRSTC_b;
+    };
+    __IM uint32_t              RESERVED4[9];
+    __IOM R_CANFD_CFDC2_Type   CFDC2[1];    /*!< (@ 0x00000100) Channel Configuration Registers                            */
+    __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers                    */
+    __IM uint32_t              RESERVED5[24];
+
+    union
+    {
+        __IOM uint32_t CFDRPGACC[64];    /*!< (@ 0x00000280) RAM Test Page Access Registers                             */
+
+        struct
+        {
+            __IOM uint32_t RDTA : 32;    /*!< [31..0] RAM Data Test Access                                              */
+        } CFDRPGACC_b[64];
+    };
+    __IM uint32_t             RESERVED6[104];
+    __IOM R_CANFD_CFDRF_Type  CFDRF[2];  /*!< (@ 0x00000520) RX FIFO Access Registers                                   */
+    __IOM R_CANFD_CFDCF_Type  CFDCF[1];  /*!< (@ 0x000005B8) Common FIFO Access Registers                               */
+    __IOM R_CANFD_CFDTM_Type  CFDTM[4];  /*!< (@ 0x00000604) TX Message Buffer Access Registers                         */
+    __IM uint32_t             RESERVED7[3];
+    __IOM R_CANFD_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List                                    */
+    __IM uint32_t             RESERVED8[118];
+    __IOM R_CANFD_CFDRM_Type  CFDRM[4];  /*!< (@ 0x00000920) RX Message Buffer Access Clusters                          */
+} R_CANFD_Type;                          /*!< Size = 6432 (0x1920)                                                      */
+
+/* =========================================================================================================================== */
+/* ================                                           R_CRC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC)
+ */
+
+typedef struct                         /*!< (@ 0x40108000) R_CRC Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t CRCCR0;          /*!< (@ 0x00000000) CRC Control Register0                                      */
+
+        struct
+        {
+            __IOM uint8_t GPS    : 3;  /*!< [2..0] CRC Generating Polynomial Switching                                */
+            uint8_t              : 3;
+            __IOM uint8_t LMS    : 1;  /*!< [6..6] CRC Calculation Switching                                          */
+            __OM uint8_t  DORCLR : 1;  /*!< [7..7] CRCDOR Register Clear                                              */
+        } CRCCR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CRCCR1;          /*!< (@ 0x00000001) CRC Control Register1                                      */
+
+        struct
+        {
+            uint8_t              : 6;
+            __IOM uint8_t CRCSWR : 1;  /*!< [6..6] Snoop-on-write/read switch bit                                     */
+            __IOM uint8_t CRCSEN : 1;  /*!< [7..7] Snoop enable bit                                                   */
+        } CRCCR1_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CRCDIR;          /*!< (@ 0x00000004) CRC Data Input Register                                    */
+
+            struct
+            {
+                __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C )                 */
+            } CRCDIR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t CRCDIR_BY;         /*!< (@ 0x00000004) CRC Data Input Register (byte access)                      */
+
+            struct
+            {
+                __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT
+                                              *   )                                                                         */
+            } CRCDIR_BY_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CRCDOR;          /*!< (@ 0x00000008) CRC Data Output Register                                   */
+
+            struct
+            {
+                __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C )                */
+            } CRCDOR_b;
+        };
+
+        union
+        {
+            __IOM uint16_t CRCDOR_HA;          /*!< (@ 0x00000008) CRC Data Output Register (halfword access)                 */
+
+            struct
+            {
+                __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT
+                                                *   )                                                                         */
+            } CRCDOR_HA_b;
+        };
+
+        union
+        {
+            __IOM uint8_t CRCDOR_BY;         /*!< (@ 0x00000008) CRC Data Output Register(byte access)                      */
+
+            struct
+            {
+                __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 )                           */
+            } CRCDOR_BY_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint16_t CRCSAR;         /*!< (@ 0x0000000C) Snoop Address Register                                     */
+
+        struct
+        {
+            __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop            */
+            uint16_t             : 2;
+        } CRCSAR_b;
+    };
+    __IM uint16_t RESERVED1;
+} R_CRC_Type;                          /*!< Size = 16 (0x10)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DAC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief D/A Converter (R_DAC)
+ */
+
+typedef struct                         /*!< (@ 0x40171000) R_DAC Structure                                            */
+{
+    union
+    {
+        __IOM uint16_t DADR[2];        /*!< (@ 0x00000000) D/A Data Register                                          */
+
+        struct
+        {
+            __IOM uint16_t DADR : 16;  /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order
+                                        *   4 bits are fixed to 0: right justified format. When DADPR.DPSEL
+                                        *   = 1, the low-order 4 bits are fixed to 0: left justified
+                                        *   format.                                                                   */
+        } DADR_b[2];
+    };
+
+    union
+    {
+        __IOM uint8_t DACR;            /*!< (@ 0x00000004) D/A Control Register                                       */
+
+        struct
+        {
+            uint8_t             : 5;
+            __IOM uint8_t DAE   : 1;   /*!< [5..5] D/A Enable                                                         */
+            __IOM uint8_t DAOE0 : 1;   /*!< [6..6] D/A Output Enable 0                                                */
+            __IOM uint8_t DAOE1 : 1;   /*!< [7..7] D/A Output Enable 0                                                */
+        } DACR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DADPR;           /*!< (@ 0x00000005) DADR0 Format Select Register                               */
+
+        struct
+        {
+            uint8_t             : 7;
+            __IOM uint8_t DPSEL : 1;   /*!< [7..7] DADRm Format Select                                                */
+        } DADPR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DAADSCR;         /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register                 */
+
+        struct
+        {
+            uint8_t              : 7;
+            __IOM uint8_t DAADST : 1;  /*!< [7..7] D/A-A/D Synchronous Conversion                                     */
+        } DAADSCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DAVREFCR;        /*!< (@ 0x00000007) D/A VREF Control Register                                  */
+
+        struct
+        {
+            __IOM uint8_t REF : 3;     /*!< [2..0] D/A Reference Voltage Select                                       */
+            uint8_t           : 5;
+        } DAVREFCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DAAMPCR;         /*!< (@ 0x00000008) D/A Output Amplifier Control Register                      */
+
+        struct
+        {
+            uint8_t              : 6;
+            __IOM uint8_t DAAMP0 : 1;  /*!< [6..6] Amplifier Control                                                  */
+            __IOM uint8_t DAAMP1 : 1;  /*!< [7..7] Amplifier Control                                                  */
+        } DAAMPCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DAPC;            /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register                    */
+
+        struct
+        {
+            __IOM uint8_t PUMPEN : 1;  /*!< [0..0] Charge Pump Enable                                                 */
+            uint8_t              : 7;
+        } DAPC_b;
+    };
+    __IM uint16_t RESERVED[9];
+
+    union
+    {
+        __IOM uint8_t DAASWCR;         /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register          */
+
+        struct
+        {
+            uint8_t              : 6;
+            __IOM uint8_t DAASW0 : 1;  /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure
+                                        *   to wait for stabilization of the output amplifier of D/A
+                                        *   channel 0. When DAASW0 is set to 1, D/A conversion operates,
+                                        *   but the conversion result D/A is not output from channel
+                                        *   0. When the DAASW0 bit is 0, the stabilization wait time
+                                        *   stops, and the D/A conversion result of channel 0 is output
+                                        *   through the output amplifier.                                             */
+            __IOM uint8_t DAASW1 : 1;  /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure
+                                        *   to wait for stabilization of the output amplifier of D/A
+                                        *   channel 1. When DAASW1 is set to 1, D/A conversion operates,
+                                        *   but the conversion result D/A is not output from channel
+                                        *   1. When the DAASW1 bit is 0, the stabilization wait time
+                                        *   stops, and the D/A conversion result of channel 1 is output
+                                        *   through the output amplifier.                                             */
+        } DAASWCR_b;
+    };
+    __IM uint8_t  RESERVED1;
+    __IM uint16_t RESERVED2[2129];
+
+    union
+    {
+        __IOM uint8_t DAADUSR;          /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register                   */
+
+        struct
+        {
+            __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for
+                                         *   D/A and A/D synchronous conversions. Set bit [0] to 1 to
+                                         *   select unit 0 as the target synchronous unit for the MCU.
+                                         *   When setting the DAADSCR.DAADST bit to 1 for synchronous
+                                         *   conversions, select the target unit in this register in
+                                         *   advance. Only set the DAADUSR register while the ADCSR.ADST
+                                         *   bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
+                                         *   is set to 0.                                                              */
+            __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for
+                                         *   D/A and A/D synchronous conversions. Set bit [1] to 1 to
+                                         *   select unit 1 as the target synchronous unit for the MCU.
+                                         *   When setting the DAADSCR.DAADST bit to 1 for synchronous
+                                         *   conversions, select the target unit in this register in
+                                         *   advance. Only set the DAADUSR register while the ADCSR.ADST
+                                         *   bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
+                                         *   is set to 0.                                                              */
+            uint8_t : 6;
+        } DAADUSR_b;
+    };
+    __IM uint8_t  RESERVED3;
+    __IM uint16_t RESERVED4;
+} R_DAC_Type;                          /*!< Size = 4292 (0x10c4)                                                      */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DEBUG                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Debug Function (R_DEBUG)
+ */
+
+typedef struct                         /*!< (@ 0x4001B000) R_DEBUG Structure                                          */
+{
+    union
+    {
+        __IM uint32_t DBGSTR;          /*!< (@ 0x00000000) Debug Status Register                                      */
+
+        struct
+        {
+            uint32_t                   : 28;
+            __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request                                           */
+            __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge                                       */
+            uint32_t                   : 2;
+        } DBGSTR_b;
+    };
+    __IM uint32_t RESERVED[3];
+
+    union
+    {
+        __IOM uint32_t DBGSTOPCR;             /*!< (@ 0x00000010) Debug Stop Control Register                                */
+
+        struct
+        {
+            __IOM uint32_t DBGSTOP_IWDT  : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt                                  */
+            __IOM uint32_t DBGSTOP_WDT   : 1; /*!< [1..1] Mask bit for WDT reset/interrupt                                   */
+            uint32_t                     : 14;
+            __IOM uint32_t DBGSTOP_LVD0  : 1; /*!< [16..16] Mask bit for LVD reset/interupt                                  */
+            __IOM uint32_t DBGSTOP_LVD1  : 1; /*!< [17..17] Mask bit for LVD reset/interupt                                  */
+            __IOM uint32_t DBGSTOP_LVD2  : 1; /*!< [18..18] Mask bit for LVD reset/interupt                                  */
+            uint32_t                     : 5;
+            __IOM uint32_t DBGSTOP_RPER  : 1; /*!< [24..24] Mask bit for SRAM parity error                                   */
+            __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error                                      */
+            uint32_t                     : 5;
+            __IOM uint32_t DBGSTOP_CPER  : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt             */
+        } DBGSTOPCR_b;
+    };
+} R_DEBUG_Type;                               /*!< Size = 20 (0x14)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DMA                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief DMA Controller Common (R_DMA)
+ */
+
+typedef struct                         /*!< (@ 0x40005200) R_DMA Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t DMAST;           /*!< (@ 0x00000000) DMAC Module Activation Register                            */
+
+        struct
+        {
+            __IOM uint8_t DMST : 1;    /*!< [0..0] DMAC Operation Enable                                              */
+            uint8_t            : 7;
+        } DMAST_b;
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2[15];
+
+    union
+    {
+        __IOM uint32_t DMECHR;          /*!< (@ 0x00000040) DMAC Error Channel Register                                */
+
+        struct
+        {
+            __IM uint32_t DMECH    : 3; /*!< [2..0] DMAC Error channel                                                 */
+            uint32_t               : 5;
+            __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor                    */
+            uint32_t               : 7;
+            __IOM uint32_t DMESTA  : 1; /*!< [16..16] DMAC Error Status                                                */
+            uint32_t               : 15;
+        } DMECHR_b;
+    };
+    __IM uint32_t RESERVED3[15];
+
+    union
+    {
+        __IOM uint32_t DELSR[8];       /*!< (@ 0x00000080) DMAC Event Link Setting Register                           */
+
+        struct
+        {
+            __IOM uint32_t DELS : 9;   /*!< [8..0] DMAC Event Link Select                                             */
+            uint32_t            : 7;
+            __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
+                                        *   IR flag is prohibited.                                                    */
+            uint32_t : 15;
+        } DELSR_b[8];
+    };
+} R_DMA_Type;                          /*!< Size = 160 (0xa0)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DMAC0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief DMA Controller (R_DMAC0)
+ */
+
+typedef struct                         /*!< (@ 0x40005000) R_DMAC0 Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t DMSAR;          /*!< (@ 0x00000000) DMA Source Address Register                                */
+
+        struct
+        {
+            __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address.                      */
+        } DMSAR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DMDAR;          /*!< (@ 0x00000004) DMA Destination Address Register                           */
+
+        struct
+        {
+            __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address.                 */
+        } DMDAR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DMCRA;           /*!< (@ 0x00000008) DMA Transfer Count Register                                */
+
+        struct
+        {
+            __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count                                      */
+            __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count                                     */
+            uint32_t              : 6;
+        } DMCRA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DMCRB;           /*!< (@ 0x0000000C) DMA Block Transfer Count Register                          */
+
+        struct
+        {
+            __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block
+                                         *   transfer counter.                                                         */
+            __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or
+                                         *   repeat transfer operations.                                               */
+        } DMCRB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DMTMD;          /*!< (@ 0x00000010) DMA Transfer Mode Register                                 */
+
+        struct
+        {
+            __IOM uint16_t DCTG : 2;   /*!< [1..0] Transfer Request Source Select                                     */
+            uint16_t            : 6;
+            __IOM uint16_t SZ   : 2;   /*!< [9..8] Transfer Data Size Select                                          */
+            __IOM uint16_t TKP  : 1;   /*!< [10..10] Transfer Keeping                                                 */
+            uint16_t            : 1;
+            __IOM uint16_t DTS  : 2;   /*!< [13..12] Repeat Area Select                                               */
+            __IOM uint16_t MD   : 2;   /*!< [15..14] Transfer Mode Select                                             */
+        } DMTMD_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t DMINT;           /*!< (@ 0x00000013) DMA Interrupt Setting Register                             */
+
+        struct
+        {
+            __IOM uint8_t DARIE : 1;   /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt
+                                        *   Enable                                                                    */
+            __IOM uint8_t SARIE : 1;   /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt
+                                        *   Enable                                                                    */
+            __IOM uint8_t RPTIE : 1;   /*!< [2..2] Repeat Size End Interrupt Enable                                   */
+            __IOM uint8_t ESIE  : 1;   /*!< [3..3] Transfer Escape End Interrupt Enable                               */
+            __IOM uint8_t DTIE  : 1;   /*!< [4..4] Transfer End Interrupt Enable                                      */
+            uint8_t             : 3;
+        } DMINT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DMAMD;          /*!< (@ 0x00000014) DMA Address Mode Register                                  */
+
+        struct
+        {
+            __IOM uint16_t DARA : 5;   /*!< [4..0] Destination Address Extended Repeat Area Specifies the
+                                        *   extended repeat area on the destination address. For details
+                                        *   on the settings.                                                          */
+            __IOM uint16_t DADR : 1;   /*!< [5..5] Destination Address Update Select After Reload                     */
+            __IOM uint16_t DM   : 2;   /*!< [7..6] Destination Address Update Mode                                    */
+            __IOM uint16_t SARA : 5;   /*!< [12..8] Source Address Extended Repeat Area Specifies the extended
+                                        *   repeat area on the source address. For details on the settings.           */
+            __IOM uint16_t SADR : 1;   /*!< [13..13] Source Address Update Select After Reload                        */
+            __IOM uint16_t SM   : 2;   /*!< [15..14] Source Address Update Mode                                       */
+        } DMAMD_b;
+    };
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint32_t DMOFR;          /*!< (@ 0x00000018) DMA Offset Register                                        */
+
+        struct
+        {
+            __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected
+                                        *   as the address update mode for transfer source or destination.            */
+        } DMOFR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DMCNT;           /*!< (@ 0x0000001C) DMA Transfer Enable Register                               */
+
+        struct
+        {
+            __IOM uint8_t DTE : 1;     /*!< [0..0] DMA Transfer Enable                                                */
+            uint8_t           : 7;
+        } DMCNT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DMREQ;           /*!< (@ 0x0000001D) DMA Software Start Register                                */
+
+        struct
+        {
+            __IOM uint8_t SWREQ : 1;   /*!< [0..0] DMA Software Start                                                 */
+            uint8_t             : 3;
+            __IOM uint8_t CLRS  : 1;   /*!< [4..4] DMA Software Start Bit Auto Clear Select                           */
+            uint8_t             : 3;
+        } DMREQ_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DMSTS;            /*!< (@ 0x0000001E) DMA Status Register                                        */
+
+        struct
+        {
+            __IOM uint8_t ESIF : 1;     /*!< [0..0] Transfer Escape End Interrupt Flag                                 */
+            uint8_t            : 3;
+            __IOM uint8_t DTIF : 1;     /*!< [4..4] Transfer End Interrupt Flag                                        */
+            uint8_t            : 2;
+            __IM uint8_t ACT   : 1;     /*!< [7..7] DMA Active Flag                                                    */
+        } DMSTS_b;
+    };
+    __IM uint8_t   RESERVED2;
+    __IOM uint32_t DMSRR;               /*!< (@ 0x00000020) DMA Source Reload Address Register                         */
+    __IOM uint32_t DMDRR;               /*!< (@ 0x00000024) DMA Destination Reload Address Register                    */
+
+    union
+    {
+        __IOM uint32_t DMSBS;           /*!< (@ 0x00000028) DMA Source Buffer Size Register                            */
+
+        struct
+        {
+            __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
+                                         *   mode                                                                      */
+            __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
+                                         *   mode                                                                      */
+        } DMSBS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DMDBS;           /*!< (@ 0x0000002C) DMA Destination Buffer Size Register                       */
+
+        struct
+        {
+            __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
+                                         *   mode                                                                      */
+            __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
+                                         *   mode                                                                      */
+        } DMDBS_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DMBWR;           /*!< (@ 0x00000030) DMA Bufferable Write Enable Register                       */
+
+        struct
+        {
+            __IOM uint8_t BWE : 1;     /*!< [0..0] Bufferable Write Enable                                            */
+            uint8_t           : 7;
+        } DMBWR_b;
+    };
+    __IM uint8_t  RESERVED3;
+    __IM uint16_t RESERVED4;
+} R_DMAC0_Type;                        /*!< Size = 52 (0x34)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DOC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Data Operation Circuit (R_DOC)
+ */
+
+typedef struct                         /*!< (@ 0x40109000) R_DOC Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t DOCR;            /*!< (@ 0x00000000) DOC Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t OMS     : 2; /*!< [1..0] Operating Mode Select                                              */
+            __IOM uint8_t DCSEL   : 1; /*!< [2..2] Detection Condition Select                                         */
+            uint8_t               : 2;
+            __IM uint8_t  DOPCF   : 1; /*!< [5..5] Data Operation Circuit Flag                                        */
+            __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear                                                        */
+            uint8_t               : 1;
+        } DOCR_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t DODIR;          /*!< (@ 0x00000002) DOC Data Input Register                                    */
+
+        struct
+        {
+            __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for
+                                        *   use in the operations are stored.                                         */
+        } DODIR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DODSR;          /*!< (@ 0x00000004) DOC Data Setting Register                                  */
+
+        struct
+        {
+            __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference
+                                        *   in data comparison mode. This register also stores the
+                                        *   results of operations in data addition and data subtraction
+                                        *   modes.                                                                    */
+        } DODSR_b;
+    };
+} R_DOC_Type;                          /*!< Size = 6 (0x6)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DTC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Data Transfer Controller (R_DTC)
+ */
+
+typedef struct                         /*!< (@ 0x40005400) R_DTC Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t DTCCR;           /*!< (@ 0x00000000) DTC Control Register                                       */
+
+        struct
+        {
+            uint8_t           : 4;
+            __IOM uint8_t RRS : 1;     /*!< [4..4] DTC Transfer Information Read Skip Enable.                         */
+            uint8_t           : 3;
+        } DTCCR_b;
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint32_t DTCVBR;          /*!< (@ 0x00000004) DTC Vector Base Register                                   */
+
+        struct
+        {
+            __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set
+                                         *   in the lower-order 10 bits. These bits are fixed to 0.                    */
+        } DTCVBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t DTCST;           /*!< (@ 0x0000000C) DTC Module Start Register                                  */
+
+        struct
+        {
+            __IOM uint8_t DTCST : 1;   /*!< [0..0] DTC Module Start                                                   */
+            uint8_t             : 7;
+        } DTCST_b;
+    };
+    __IM uint8_t RESERVED3;
+
+    union
+    {
+        __IM uint16_t DTCSTS;          /*!< (@ 0x0000000E) DTC Status Register                                        */
+
+        struct
+        {
+            __IM uint16_t VECN : 8;    /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate
+                                        *   the vector number for the activating source when DTC transfer
+                                        *   is in progress.The value is only valid if DTC transfer
+                                        *   is in progress (the value of the ACT flag is 1)                           */
+            uint16_t          : 7;
+            __IM uint16_t ACT : 1;     /*!< [15..15] DTC Active Flag                                                  */
+        } DTCSTS_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DTCCR_SEC;       /*!< (@ 0x00000010) DTC Control Register for secure Region                     */
+
+        struct
+        {
+            uint8_t            : 4;
+            __IOM uint8_t RRSS : 1;    /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure               */
+            uint8_t            : 3;
+        } DTCCR_SEC_b;
+    };
+    __IM uint8_t   RESERVED4;
+    __IM uint16_t  RESERVED5;
+    __IOM uint32_t DTCVBR_SEC;         /*!< (@ 0x00000014) DTC Vector Base Register for secure Region                 */
+    __IM uint32_t  RESERVED6[2];
+
+    union
+    {
+        __IOM uint32_t DTEVR;          /*!< (@ 0x00000020) DTC Error Vector Register                                  */
+
+        struct
+        {
+            __IM uint32_t DTEV    : 8; /*!< [7..0] DTC Error Vector Number                                            */
+            __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor                                 */
+            uint32_t              : 7;
+            __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag                                            */
+            uint32_t              : 15;
+        } DTEVR_b;
+    };
+} R_DTC_Type;                          /*!< Size = 36 (0x24)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ELC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Event Link Controller (R_ELC)
+ */
+
+typedef struct                         /*!< (@ 0x40082000) R_ELC Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t ELCR;            /*!< (@ 0x00000000) Event Link Controller Register                             */
+
+        struct
+        {
+            uint8_t             : 7;
+            __IOM uint8_t ELCON : 1;   /*!< [7..7] All Event Link Enable                                              */
+        } ELCR_b;
+    };
+    __IM uint8_t            RESERVED;
+    __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register              */
+    __IM uint16_t           RESERVED1[5];
+    __IOM R_ELC_ELSR_Type   ELSR[23];  /*!< (@ 0x00000010) Event Link Setting Register [0..22]                        */
+    __IM uint16_t           RESERVED2[4];
+
+    union
+    {
+        __IOM uint16_t ELCSARA;         /*!< (@ 0x00000074) Event Link Controller Security Attribution Register
+                                         *                  A                                                          */
+
+        struct
+        {
+            __IOM uint16_t ELCR    : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution                 */
+            __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security
+                                         *   Attribution                                                               */
+            __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security
+                                         *   Attribution                                                               */
+            uint16_t : 13;
+        } ELCSARA_b;
+    };
+    __IM uint16_t RESERVED3;
+
+    union
+    {
+        __IOM uint16_t ELCSARB;        /*!< (@ 0x00000078) Event Link Controller Security Attribution Register
+                                        *                  B                                                          */
+
+        struct
+        {
+            __IOM uint16_t ELSR0  : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution                  */
+            __IOM uint16_t ELSR1  : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution                  */
+            __IOM uint16_t ELSR2  : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution                  */
+            __IOM uint16_t ELSR3  : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution                  */
+            __IOM uint16_t ELSR4  : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution                  */
+            __IOM uint16_t ELSR5  : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution                  */
+            __IOM uint16_t ELSR6  : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution                  */
+            __IOM uint16_t ELSR7  : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution                  */
+            __IOM uint16_t ELSR8  : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution                  */
+            __IOM uint16_t ELSR9  : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution                  */
+            __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution               */
+            __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution               */
+            __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution               */
+            __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution               */
+            __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution               */
+            __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution               */
+        } ELCSARB_b;
+    };
+    __IM uint16_t RESERVED4;
+
+    union
+    {
+        __IOM uint16_t ELCSARC;        /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register
+                                        *                  C                                                          */
+
+        struct
+        {
+            __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution                 */
+            __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution                 */
+            __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution                 */
+            uint16_t              : 13;
+        } ELCSARC_b;
+    };
+} R_ELC_Type;                          /*!< Size = 126 (0x7e)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                       R_FACI_HP_CMD                                       ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD)
+ */
+
+typedef struct                         /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure                                    */
+{
+    union
+    {
+        __IOM uint16_t FACI_CMD16;     /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access)                */
+        __IOM uint8_t  FACI_CMD8;      /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access)                */
+    };
+} R_FACI_HP_CMD_Type;                  /*!< Size = 2 (0x2)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_FACI_HP                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Flash Application Command Interface (R_FACI_HP)
+ */
+
+typedef struct                         /*!< (@ 0x407FE000) R_FACI_HP Structure                                        */
+{
+    __IM uint32_t RESERVED[4];
+
+    union
+    {
+        __IOM uint8_t FASTAT;          /*!< (@ 0x00000010) Flash Access Status                                        */
+
+        struct
+        {
+            uint8_t             : 3;
+            __IOM uint8_t DFAE  : 1;   /*!< [3..3] Data Flash Access Error                                            */
+            __IM uint8_t  CMDLK : 1;   /*!< [4..4] Command Lock                                                       */
+            uint8_t             : 2;
+            __IOM uint8_t CFAE  : 1;   /*!< [7..7] Code Flash Access Error                                            */
+        } FASTAT_b;
+    };
+    __IM uint8_t  RESERVED1;
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t FAEINT;          /*!< (@ 0x00000014) Flash Access Error Interrupt Enable                        */
+
+        struct
+        {
+            uint8_t               : 3;
+            __IOM uint8_t DFAEIE  : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable                           */
+            __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable                                      */
+            uint8_t               : 2;
+            __IOM uint8_t CFAEIE  : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable                           */
+        } FAEINT_b;
+    };
+    __IM uint8_t  RESERVED3;
+    __IM uint16_t RESERVED4;
+
+    union
+    {
+        __IOM uint8_t FRDYIE;          /*!< (@ 0x00000018) Flash Ready Interrupt Enable                               */
+
+        struct
+        {
+            __IOM uint8_t FRDYIE : 1;  /*!< [0..0] FRDY Interrupt Enable                                              */
+            uint8_t              : 7;
+        } FRDYIE_b;
+    };
+    __IM uint8_t  RESERVED5;
+    __IM uint16_t RESERVED6;
+    __IM uint32_t RESERVED7[5];
+
+    union
+    {
+        __IOM uint32_t FSADDR;         /*!< (@ 0x00000030) Flash Start Address                                        */
+
+        struct
+        {
+            __IOM uint32_t FSA : 32;   /*!< [31..0] Start Address of Flash Sequencer Command Target Area
+                                        *   These bits can be written when FRDY bit of FSTATR register
+                                        *   is '1'. Writing to these bits in FRDY = '0' is ignored.                   */
+        } FSADDR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FEADDR;         /*!< (@ 0x00000034) Flash End Address                                          */
+
+        struct
+        {
+            __IOM uint32_t FEA : 32;   /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies
+                                        *   end address of target area in 'Blank Check' command. These
+                                        *   bits can be written when FRDY bit of FSTATR register is
+                                        *   '1'. Writing to these bits in FRDY = '0' is ignored.                      */
+        } FEADDR_b;
+    };
+    __IM uint32_t RESERVED8[3];
+
+    union
+    {
+        __IOM uint16_t FMEPROT;        /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register                   */
+
+        struct
+        {
+            __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit
+                                        *   is only possible when the FRDY bit in the FSTATR register
+                                        *   is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing
+                                        *   to this bit is only possible when 16 bits are written and
+                                        *   the value written to the KEY bits is D9h.Written values
+                                        *   are not retained by these bits (always read as 0x00).Only
+                                        *   secure access can write to this register. Both secure access
+                                        *   and non-secure read access are allowed. Non-secure writeaccess
+                                        *   is denied, but TrustZo                                                    */
+            uint16_t          : 7;
+            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
+        } FMEPROT_b;
+    };
+    __IM uint16_t RESERVED9;
+    __IM uint32_t RESERVED10[12];
+
+    union
+    {
+        __IOM uint16_t FBPROT0;        /*!< (@ 0x00000078) Flash Block Protection Register                            */
+
+        struct
+        {
+            __IOM uint16_t BPCN0 : 1;  /*!< [0..0] Block Protection for Non-secure CancelThis bit can be
+                                        *   written when the FRDY bit in the FSTATR register is 1.
+                                        *   Writing to this bit is ignored when the FRDY bit is 0.Writing
+                                        *   to this bit is only possible when 16 bits are written and
+                                        *   the value written to the KEY[7:0] bits is 0x78.Written
+                                        *   values are not retained by these bits (always read as 0x00).              */
+            uint16_t          : 7;
+            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
+        } FBPROT0_b;
+    };
+    __IM uint16_t RESERVED11;
+
+    union
+    {
+        __IOM uint16_t FBPROT1;        /*!< (@ 0x0000007C) Flash Block Protection for Secure Register                 */
+
+        struct
+        {
+            __IOM uint16_t BPCN1 : 1;  /*!< [0..0] Block Protection for Secure CancelWriting to this bit
+                                        *   is only possible when the FRDY bit in the FSTATR register
+                                        *   is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing
+                                        *   to this bit is only possible when 16 bits are written and
+                                        *   the value written to the KEY[7:0] bits is 0xB1.Written
+                                        *   values are not retained by these bits (always read as 0x00).              */
+            uint16_t          : 7;
+            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
+        } FBPROT1_b;
+    };
+    __IM uint16_t RESERVED12;
+
+    union
+    {
+        __IM uint32_t FSTATR;          /*!< (@ 0x00000080) Flash Status                                               */
+
+        struct
+        {
+            uint32_t                 : 6;
+            __IM uint32_t FLWEERR    : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag                               */
+            uint32_t                 : 1;
+            __IM uint32_t PRGSPD     : 1; /*!< [8..8] Programming-Suspended Status                                       */
+            __IM uint32_t ERSSPD     : 1; /*!< [9..9] Erasure-Suspended Status                                           */
+            __IM uint32_t DBFULL     : 1; /*!< [10..10] Data Buffer Full                                                 */
+            __IM uint32_t SUSRDY     : 1; /*!< [11..11] Suspend Ready                                                    */
+            __IM uint32_t PRGERR     : 1; /*!< [12..12] Programming Error                                                */
+            __IM uint32_t ERSERR     : 1; /*!< [13..13] Erasure Error                                                    */
+            __IM uint32_t ILGLERR    : 1; /*!< [14..14] Illegal Command Error                                            */
+            __IM uint32_t FRDY       : 1; /*!< [15..15] Flash Ready                                                      */
+            uint32_t                 : 4;
+            __IM uint32_t  OTERR     : 1; /*!< [20..20] Other Error                                                      */
+            __IOM uint32_t SECERR    : 1; /*!< [21..21] Security Error                                                   */
+            __IM uint32_t  FESETERR  : 1; /*!< [22..22] FENTRY Setting Error                                             */
+            __IM uint32_t  ILGCOMERR : 1; /*!< [23..23] Illegal Command Error                                            */
+            uint32_t                 : 8;
+        } FSTATR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t FENTRYR;         /*!< (@ 0x00000084) Program/Erase Mode Entry                                   */
+
+        struct
+        {
+            __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when
+                                         *   FRDY bit in FSTATR register is '1'. Writing to this bit
+                                         *   in FRDY = '0' is ignored. Writing to these bits is enabled
+                                         *   only when this register is accessed in 16-bit size and
+                                         *   H'AA is written to KEY bits                                               */
+            uint16_t               : 6;
+            __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when
+                                         *   FRDY bit in FSTATR register is '1'. Writing to this bit
+                                         *   in FRDY = '0' is ignored. Writing to these bits is enabled
+                                         *   only when this register is accessed in 16-bit size and
+                                         *   H'AA is written to KEY bits.                                              */
+            __OM uint16_t KEY : 8;      /*!< [15..8] KEY Code                                                          */
+        } FENTRYR_b;
+    };
+    __IM uint16_t RESERVED13;
+    __IM uint32_t RESERVED14;
+
+    union
+    {
+        __IOM uint16_t FSUINITR;       /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize                          */
+
+        struct
+        {
+            __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY
+                                        *   bit of FSTATR register is '1'. Writing to this bit in FRDY
+                                        *   = '0' is ignored. Writing to these bits is enabled only
+                                        *   when this register is accessed in 16-bit size and H'2D
+                                        *   is written to KEY bits.                                                   */
+            uint16_t          : 7;
+            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
+        } FSUINITR_b;
+    };
+    __IM uint16_t RESERVED15;
+    __IM uint32_t RESERVED16[4];
+
+    union
+    {
+        __IM uint16_t FCMDR;           /*!< (@ 0x000000A0) Flash Sequencer Command                                    */
+
+        struct
+        {
+            __IM uint16_t PCMDR : 8;   /*!< [7..0] Previous Command Register                                          */
+            __IM uint16_t CMDR  : 8;   /*!< [15..8] Command Register                                                  */
+        } FCMDR_b;
+    };
+    __IM uint16_t RESERVED17;
+    __IM uint32_t RESERVED18[11];
+
+    union
+    {
+        __IOM uint8_t FBCCNT;          /*!< (@ 0x000000D0) Blank Check Control                                        */
+
+        struct
+        {
+            __IOM uint8_t BCDIR : 1;   /*!< [0..0] Blank Check Direction                                              */
+            uint8_t             : 7;
+        } FBCCNT_b;
+    };
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
+
+    union
+    {
+        __IM uint8_t FBCSTAT;          /*!< (@ 0x000000D4) Blank Check Status                                         */
+
+        struct
+        {
+            __IM uint8_t BCST : 1;     /*!< [0..0] Blank Check Status Bit                                             */
+            uint8_t           : 7;
+        } FBCSTAT_b;
+    };
+    __IM uint8_t  RESERVED21;
+    __IM uint16_t RESERVED22;
+
+    union
+    {
+        __IM uint32_t FPSADDR;         /*!< (@ 0x000000D8) Programmed Area Start Address                              */
+
+        struct
+        {
+            __IM uint32_t PSADR : 19;  /*!< [18..0] Programmed Area Start Address NOTE: Indicates address
+                                        *   of the first programmed data which is found in 'Blank Check'
+                                        *   command execution.                                                        */
+            uint32_t : 13;
+        } FPSADDR_b;
+    };
+
+    union
+    {
+        __IM uint32_t FAWMON;          /*!< (@ 0x000000DC) Flash Access Window Monitor                                */
+
+        struct
+        {
+            __IM uint32_t FAWS : 11;   /*!< [10..0] Start Sector Address for Access Window NOTE: These bits
+                                        *   indicate the start sector address for setting the access
+                                        *   window that is located in the configuration area.                         */
+            uint32_t           : 4;
+            __IM uint32_t FSPR : 1;    /*!< [15..15] Protection Flag of programming the Access Window, Boot
+                                        *   Flag and Temporary Boot Swap Control and 'Config Clear'
+                                        *   command execution                                                         */
+            __IM uint32_t FAWE : 11;   /*!< [26..16] End Sector Address for Access Window NOTE: These bits
+                                        *   indicate the end sector address for setting the access
+                                        *   window that is located in the configuration area.                         */
+            uint32_t            : 4;
+            __IM uint32_t BTFLG : 1;   /*!< [31..31] Flag of Start-Up area select for Boot Swap                       */
+        } FAWMON_b;
+    };
+
+    union
+    {
+        __IOM uint16_t FCPSR;           /*!< (@ 0x000000E0) FCU Process Switch                                         */
+
+        struct
+        {
+            __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode                                             */
+            uint16_t               : 15;
+        } FCPSR_b;
+    };
+    __IM uint16_t RESERVED23;
+
+    union
+    {
+        __IOM uint16_t FPCKAR;         /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification    */
+
+        struct
+        {
+            __IOM uint16_t PCKA : 8;   /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits
+                                        *   can be written when FRDY bit in FSTATR register is '1'.
+                                        *   Writing to this bit in FRDY = '0' is ignored. Writing to
+                                        *   these bits is enabled only when this register is accessed
+                                        *   in 16-bit size and H'1E is written to KEY bits.                           */
+            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
+        } FPCKAR_b;
+    };
+    __IM uint16_t RESERVED24;
+
+    union
+    {
+        __IOM uint16_t FSUACR;         /*!< (@ 0x000000E8) Flash Start-Up Area Control Register                       */
+
+        struct
+        {
+            __IOM uint16_t SAS : 2;    /*!< [1..0] Start Up Area Select These bits can be written when FRDY
+                                        *   bit in FSTATR register is '1'. Writing to this bit in FRDY
+                                        *   = '0' is ignored. Writing to these bits is enabled only
+                                        *   when this register is accessed in 16-bit size and H'66
+                                        *   is written to KEY bits.                                                   */
+            uint16_t          : 6;
+            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
+        } FSUACR_b;
+    };
+    __IM uint16_t RESERVED25;
+} R_FACI_HP_Type;                      /*!< Size = 236 (0xec)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                         R_FCACHE                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Flash Memory Cache (R_FCACHE)
+ */
+
+typedef struct                         /*!< (@ 0x4001C000) R_FCACHE Structure                                         */
+{
+    __IM uint16_t RESERVED[128];
+
+    union
+    {
+        __IOM uint16_t FCACHEE;          /*!< (@ 0x00000100) Flash Cache Enable Register                                */
+
+        struct
+        {
+            __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable                                                      */
+            uint16_t                : 15;
+        } FCACHEE_b;
+    };
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint16_t FCACHEIV;         /*!< (@ 0x00000104) Flash Cache Invalidate Register                            */
+
+        struct
+        {
+            __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register                                    */
+            uint16_t                : 15;
+        } FCACHEIV_b;
+    };
+    __IM uint16_t RESERVED2[11];
+
+    union
+    {
+        __IOM uint8_t FLWT;            /*!< (@ 0x0000011C) Flash Wait Cycle Register                                  */
+
+        struct
+        {
+            __IOM uint8_t FLWT : 3;    /*!< [2..0] Flash Wait Cycle                                                   */
+            uint8_t            : 5;
+        } FLWT_b;
+    };
+    __IM uint8_t  RESERVED3;
+    __IM uint16_t RESERVED4[17];
+
+    union
+    {
+        __IOM uint16_t FSAR;             /*!< (@ 0x00000140) Flash Security Attribution Register                        */
+
+        struct
+        {
+            __IOM uint16_t FLWTSA   : 1; /*!< [0..0] FLWT Security Attribution                                          */
+            uint16_t                : 7;
+            __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution                                        */
+            uint16_t                : 7;
+        } FSAR_b;
+    };
+} R_FCACHE_Type;                         /*!< Size = 322 (0x142)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_GPT0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief General PWM Timer (R_GPT0)
+ */
+
+typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure                                           */
+{
+    union
+    {
+        __IOM uint32_t GTWP;           /*!< (@ 0x00000000) General PWM Timer Write-Protection Register                */
+
+        struct
+        {
+            __IOM uint32_t WP    : 1;  /*!< [0..0] Register Write Disable                                             */
+            __IOM uint32_t STRWP : 1;  /*!< [1..1] GTSTR.CSTRT Bit Write Disable                                      */
+            __IOM uint32_t STPWP : 1;  /*!< [2..2] GTSTP.CSTOP Bit Write Disable                                      */
+            __IOM uint32_t CLRWP : 1;  /*!< [3..3] GTCLR.CCLR Bit Write Disable                                       */
+            __IOM uint32_t CMNWP : 1;  /*!< [4..4] Common Register Write Disabled                                     */
+            uint32_t             : 3;
+            __OM uint32_t PRKEY  : 8;  /*!< [15..8] GTWP Key Code                                                     */
+            uint32_t             : 16;
+        } GTWP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSTR;           /*!< (@ 0x00000004) General PWM Timer Software Start Register                  */
+
+        struct
+        {
+            __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+        } GTSTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSTP;           /*!< (@ 0x00000008) General PWM Timer Software Stop Register                   */
+
+        struct
+        {
+            __IOM uint32_t CSTOP0 : 1;  /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP1 : 1;  /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP2 : 1;  /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP3 : 1;  /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP4 : 1;  /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP5 : 1;  /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP6 : 1;  /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP7 : 1;  /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP8 : 1;  /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP9 : 1;  /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+        } GTSTP_b;
+    };
+
+    union
+    {
+        __OM uint32_t GTCLR;           /*!< (@ 0x0000000C) General PWM Timer Software Clear Register                  */
+
+        struct
+        {
+            __OM uint32_t CCLR0  : 1;  /*!< [0..0] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR1  : 1;  /*!< [1..1] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR2  : 1;  /*!< [2..2] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR3  : 1;  /*!< [3..3] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR4  : 1;  /*!< [4..4] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR5  : 1;  /*!< [5..5] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR6  : 1;  /*!< [6..6] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR7  : 1;  /*!< [7..7] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR8  : 1;  /*!< [8..8] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR9  : 1;  /*!< [9..9] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR10 : 1;  /*!< [10..10] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
+        } GTCLR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSSR;            /*!< (@ 0x00000010) General PWM Timer Start Source Select Register             */
+
+        struct
+        {
+            __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable                */
+            __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable               */
+            __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable                */
+            __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable               */
+            __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable                */
+            __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable               */
+            __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable                */
+            __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable               */
+            __IOM uint32_t SSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Start Enable                        */
+            uint32_t              : 7;
+            __IOM uint32_t CSTRT  : 1;   /*!< [31..31] Software Source Counter Start Enable                             */
+        } GTSSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTPSR;            /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register              */
+
+        struct
+        {
+            __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable                 */
+            __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable                */
+            __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable                 */
+            __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable                */
+            __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable                 */
+            __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable                */
+            __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable                 */
+            __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable                */
+            __IOM uint32_t PSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable                        */
+            uint32_t              : 7;
+            __IOM uint32_t CSTOP  : 1;   /*!< [31..31] Software Source Counter Stop Enable                              */
+        } GTPSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTCSR;            /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register             */
+
+        struct
+        {
+            __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable                */
+            __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable               */
+            __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable                */
+            __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable               */
+            __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable                */
+            __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable               */
+            __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable                */
+            __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable               */
+            __IOM uint32_t CSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSCMSC : 3;   /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing
+                                          *   Source Counter Clear Enable.                                              */
+            __IOM uint32_t CP1CCE : 1;   /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear
+                                          *   Enable (This bit is only available in GPT324 to GPT329.
+                                          *   In GPT320 to GPT323, this bit is read as 0. The write value
+                                          *   should be 0.)                                                             */
+            uint32_t            : 3;
+            __IOM uint32_t CCLR : 1;     /*!< [31..31] Software Source Counter Clear Enable                             */
+        } GTCSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTUPSR;           /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register          */
+
+        struct
+        {
+            __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable             */
+            __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable            */
+            __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable             */
+            __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable            */
+            __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable             */
+            __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable            */
+            __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable             */
+            __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable            */
+            __IOM uint32_t USCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USILVL : 4;   /*!< [27..24] External Input Level Source Count-Up Enable                      */
+            uint32_t              : 4;
+        } GTUPSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDNSR;           /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register        */
+
+        struct
+        {
+            __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable           */
+            __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable          */
+            __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable           */
+            __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable          */
+            __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable           */
+            __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable          */
+            __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable           */
+            __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable          */
+            __IOM uint32_t DSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSILVL : 4;   /*!< [27..24] External Input Level Source Count-Down Enable                    */
+            uint32_t              : 4;
+        } GTDNSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTICASR;          /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select
+                                          *                  Register A                                                 */
+
+        struct
+        {
+            __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
+            __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
+            __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
+            __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
+            __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t ASCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            uint32_t              : 8;
+        } GTICASR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTICBSR;          /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select
+                                          *                  Register B                                                 */
+
+        struct
+        {
+            __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
+            __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
+            __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
+            __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
+            __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t BSCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            uint32_t              : 8;
+        } GTICBSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+
+        struct
+        {
+            __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
+            uint32_t               : 7;
+            __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
+            __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
+            __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
+            __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
+            uint32_t               : 2;
+            __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
+            __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
+            uint32_t               : 3;
+            __IOM uint32_t TPCS    : 4; /*!< [26..23] Timer Prescaler Select                                           */
+            __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
+            uint32_t               : 3;
+        } GTCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTUDDTYC;       /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t UD     : 1; /*!< [0..0] Count Direction Setting                                            */
+            __IOM uint32_t UDF    : 1; /*!< [1..1] Forcible Count Direction Setting                                   */
+            uint32_t              : 14;
+            __IOM uint32_t OADTY  : 2; /*!< [17..16] GTIOCA Output Duty Setting                                       */
+            __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting                              */
+            __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100
+                                        *   percent Duty Setting                                                      */
+            uint32_t              : 4;
+            __IOM uint32_t OBDTY  : 2; /*!< [25..24] GTIOCB Output Duty Setting                                       */
+            __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting                              */
+            __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100
+                                        *   percent Duty Setting                                                      */
+            uint32_t : 4;
+        } GTUDDTYC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTIOR;          /*!< (@ 0x00000034) General PWM Timer I/O Control Register                     */
+
+        struct
+        {
+            __IOM uint32_t GTIOA  : 5; /*!< [4..0] GTIOCA Pin Function Select                                         */
+            __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous
+                                        *   Clear Disable.(This bit is only available in GPT324 to
+                                        *   GPT329. In GPT320 to GPT323, this bit is read as 0. The
+                                        *   write value should be 0.)                                                 */
+            __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop                  */
+            __IOM uint32_t OAHLD  : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count                  */
+            __IOM uint32_t OAE    : 1; /*!< [8..8] GTIOCA Pin Output Enable                                           */
+            __IOM uint32_t OADF   : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting                                  */
+            __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This
+                                        *   bit is only available in GPT324 to GPT329. In GPT320 to
+                                        *   GPT323, this bit is read as 0. The write value should be
+                                        *   0.)                                                                       */
+            __IOM uint32_t PSYE   : 1; /*!< [12..12] PWM Synchronous output Enable                                    */
+            __IOM uint32_t NFAEN  : 1; /*!< [13..13] Noise Filter A Enable                                            */
+            __IOM uint32_t NFCSA  : 2; /*!< [15..14] Noise Filter A Sampling Clock Select                             */
+            __IOM uint32_t GTIOB  : 5; /*!< [20..16] GTIOCB Pin Function Select                                       */
+            uint32_t              : 1;
+            __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop                */
+            __IOM uint32_t OBHLD  : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count                */
+            __IOM uint32_t OBE    : 1; /*!< [24..24] GTIOCB Pin Output Enable                                         */
+            __IOM uint32_t OBDF   : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting                                 */
+            __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This
+                                        *   bit is only available in GPT324 to GPT329. In GPT320 to
+                                        *   GPT323, this bit is read as 0. The write value should be
+                                        *   0.)                                                                       */
+            uint32_t             : 1;
+            __IOM uint32_t NFBEN : 1;  /*!< [29..29] Noise Filter B Enable                                            */
+            __IOM uint32_t NFCSB : 2;  /*!< [31..30] Noise Filter B Sampling Clock Select                             */
+        } GTIOR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTINTAD;        /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register        */
+
+        struct
+        {
+            uint32_t            : 8;
+            __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
+            __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            uint32_t               : 4;
+            __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
+            uint32_t               : 2;
+            __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
+            __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
+        } GTINTAD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTST;            /*!< (@ 0x0000003C) General PWM Timer Status Register                          */
+
+        struct
+        {
+            __IOM uint32_t TCFA  : 1;   /*!< [0..0] Input Capture/Compare Match Flag A                                 */
+            __IOM uint32_t TCFB  : 1;   /*!< [1..1] Input Capture/Compare Match Flag B                                 */
+            __IOM uint32_t TCFC  : 1;   /*!< [2..2] Input Compare Match Flag C                                         */
+            __IOM uint32_t TCFD  : 1;   /*!< [3..3] Input Compare Match Flag D                                         */
+            __IOM uint32_t TCFE  : 1;   /*!< [4..4] Input Compare Match Flag E                                         */
+            __IOM uint32_t TCFF  : 1;   /*!< [5..5] Input Compare Match Flag F                                         */
+            __IOM uint32_t TCFPO : 1;   /*!< [6..6] Overflow Flag                                                      */
+            __IOM uint32_t TCFPU : 1;   /*!< [7..7] Underflow Flag                                                     */
+            __IM uint32_t  ITCNT : 3;   /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter
+                                         *   for counting the number of times a timer interrupt has
+                                         *   been skipped.)                                                            */
+            uint32_t               : 4;
+            __IM uint32_t  TUCF    : 1; /*!< [15..15] Count Direction Flag                                             */
+            __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start
+                                         *   Request Interrupt Enable                                                  */
+            __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor
+                                         *   Start Request Flag                                                        */
+            __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start
+                                         *   Request Flag                                                              */
+            __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor
+                                         *   Start Request Flag                                                        */
+            uint32_t             : 4;
+            __IM uint32_t ODF    : 1;   /*!< [24..24] Output Disable Flag                                              */
+            uint32_t             : 3;
+            __IM uint32_t  DTEF  : 1;   /*!< [28..28] Dead Time Error Flag                                             */
+            __IM uint32_t  OABHF : 1;   /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IM uint32_t  OABLF : 1;   /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t PCF   : 1;   /*!< [31..31] Period Count Function Finish Flag                                */
+        } GTST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+
+        struct
+        {
+            __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
+            __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+                                         *   is read as 0.                                                             */
+            uint32_t             : 1;
+            __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
+            uint32_t             : 1;
+            __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
+            uint32_t             : 1;
+        } GTBER_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTITC;          /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter
+                                        *                  Start Request Skipping Setting Register                    */
+
+        struct
+        {
+            __IOM uint32_t ITLA  : 1;  /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link                  */
+            __IOM uint32_t ITLB  : 1;  /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link                  */
+            __IOM uint32_t ITLC  : 1;  /*!< [2..2] GTCCRC Compare Match Interrupt Link                                */
+            __IOM uint32_t ITLD  : 1;  /*!< [3..3] GTCCRD Compare Match Interrupt Link                                */
+            __IOM uint32_t ITLE  : 1;  /*!< [4..4] GTCCRE Compare Match Interrupt Link                                */
+            __IOM uint32_t ITLF  : 1;  /*!< [5..5] GTCCRF Compare Match Interrupt Link                                */
+            __IOM uint32_t IVTC  : 2;  /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select                 */
+            __IOM uint32_t IVTT  : 3;  /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select                   */
+            uint32_t             : 1;
+            __IOM uint32_t ADTAL : 1;  /*!< [12..12] GTADTRA A/D Converter Start Request Link                         */
+            uint32_t             : 1;
+            __IOM uint32_t ADTBL : 1;  /*!< [14..14] GTADTRB A/D Converter Start Request Link                         */
+            uint32_t             : 17;
+        } GTITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTCNT;          /*!< (@ 0x00000048) General PWM Timer Counter                                  */
+
+        struct
+        {
+            __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter                                                           */
+        } GTCNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTCCR[6];       /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register                 */
+
+        struct
+        {
+            __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A                                        */
+        } GTCCR_b[6];
+    };
+
+    union
+    {
+        __IOM uint32_t GTPR;           /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register                   */
+
+        struct
+        {
+            __IOM uint32_t GTPR : 32;  /*!< [31..0] Cycle Setting Register                                            */
+        } GTPR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTPBR;          /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register            */
+
+        struct
+        {
+            __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register                                     */
+        } GTPBR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTPDBR;          /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer
+                                         *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register                              */
+        } GTPDBR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADTRA;          /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A              */
+
+        struct
+        {
+            __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A                     */
+        } GTADTRA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADTBRA;          /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register
+                                           *                  A                                                          */
+
+        struct
+        {
+            __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A              */
+        } GTADTBRA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADTDBRA;          /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer
+                                            *                  Register A                                                 */
+
+        struct
+        {
+            __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
+                                            *   A                                                                         */
+        } GTADTDBRA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADTRB;          /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B              */
+
+        struct
+        {
+            __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B                     */
+        } GTADTRB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADTBRB;          /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register
+                                           *                  B                                                          */
+
+        struct
+        {
+            __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B              */
+        } GTADTBRB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADTDBRB;          /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer
+                                            *                  Register B                                                 */
+
+        struct
+        {
+            __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
+                                            *   B                                                                         */
+        } GTADTDBRB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDTCR;         /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register               */
+
+        struct
+        {
+            __IOM uint32_t TDE   : 1;  /*!< [0..0] Negative-Phase Waveform Setting                                    */
+            uint32_t             : 3;
+            __IOM uint32_t TDBUE : 1;  /*!< [4..4] GTDVU Buffer Operation Enable                                      */
+            __IOM uint32_t TDBDE : 1;  /*!< [5..5] GTDVD Buffer Operation Enable                                      */
+            uint32_t             : 2;
+            __IOM uint32_t TDFER : 1;  /*!< [8..8] GTDVD Setting                                                      */
+            uint32_t             : 23;
+        } GTDTCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDVU;          /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U               */
+
+        struct
+        {
+            __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U                                        */
+        } GTDVU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDVD;          /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D               */
+
+        struct
+        {
+            __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D                                        */
+        } GTDVD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDBU;          /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U              */
+
+        struct
+        {
+            __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U                                       */
+        } GTDBU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDBD;          /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D              */
+
+        struct
+        {
+            __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D                                       */
+        } GTDBD_b;
+    };
+
+    union
+    {
+        __IM uint32_t GTSOS;           /*!< (@ 0x0000009C) General PWM Timer Output Protection Function
+                                        *                  Status Register                                            */
+
+        struct
+        {
+            __IM uint32_t SOS : 2;     /*!< [1..0] Output Protection Function Status                                  */
+            uint32_t          : 30;
+        } GTSOS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSOTR;         /*!< (@ 0x000000A0) General PWM Timer Output Protection Function
+                                        *                  Temporary Release Register                                 */
+
+        struct
+        {
+            __IOM uint32_t SOTR : 1;   /*!< [0..0] Output Protection Function Temporary Release                       */
+            uint32_t            : 31;
+        } GTSOTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTICLF;           /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation
+                                          *                  Function Setting Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ICLFA    : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select                   */
+            uint32_t                : 1;
+            __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select                                      */
+            uint32_t                : 6;
+            __IOM uint32_t ICLFB    : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select                 */
+            uint32_t                : 1;
+            __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select                                    */
+            uint32_t                : 6;
+        } GTICLF_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTPC;           /*!< (@ 0x000000BC) General PWM Timer Period Count Register                    */
+
+        struct
+        {
+            __IOM uint32_t PCEN : 1;   /*!< [0..0] Period Count Function Enable                                       */
+            uint32_t            : 7;
+            __IOM uint32_t ASTP : 1;   /*!< [8..8] Automatic Stop Function Enable                                     */
+            uint32_t            : 7;
+            __IOM uint32_t PCNT : 12;  /*!< [27..16] Period Counter                                                   */
+            uint32_t            : 4;
+        } GTPC_b;
+    };
+    __IM uint32_t RESERVED[4];
+
+    union
+    {
+        __IOM uint32_t GTSECSR;         /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous
+                                         *                  Control Channel Select Register                            */
+
+        struct
+        {
+            __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            uint32_t : 22;
+        } GTSECSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSECR;         /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous
+                                        *                  Control Register                                           */
+
+        struct
+        {
+            __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
+            __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
+            __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
+            __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 4;
+            __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
+            __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
+            uint32_t             : 6;
+            __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
+            __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
+            uint32_t             : 6;
+        } GTSECR_b;
+    };
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
+            __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
+                                        *   Disable                                                                   */
+            uint32_t             : 2;
+            __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t             : 1;
+            __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
+                                        *   Transfer Disable                                                          */
+            uint32_t             : 2;
+            __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
+            __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
+            __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
+            __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
+            uint32_t             : 2;
+        } GTBER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
+
+        struct
+        {
+            __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
+            uint32_t              : 11;
+            __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
+            uint32_t              : 11;
+        } GTOLBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
+                                        *                  Capture Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
+            __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
+                                        *   Other Channel GTCCRb Input Capture Source Enable                          */
+            __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
+        } GTICCR_b;
+    };
+} R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                         R_GPT_OPS                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Output Phase Switching for GPT (R_GPT_OPS)
+ */
+
+typedef struct                         /*!< (@ 0x40169A00) R_GPT_OPS Structure                                        */
+{
+    union
+    {
+        __IOM uint32_t OPSCR;          /*!< (@ 0x00000000) Output Phase Switching Control Register                    */
+
+        struct
+        {
+            __IOM uint32_t UF : 1;     /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase
+                                        *   by the software settings.This bit setting is valid when
+                                        *   the OPSCR.FB bit = 1.                                                     */
+            __IOM uint32_t VF : 1;     /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase
+                                        *   by the software settings.This bit setting is valid when
+                                        *   the OPSCR.FB bit = 1.                                                     */
+            __IOM uint32_t WF : 1;     /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase
+                                        *   by the software settings.This bit setting is valid when
+                                        *   the OPSCR.FB bit = 1.                                                     */
+            uint32_t        : 1;
+            __IM uint32_t U : 1;       /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the
+                                        *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
+                                        *   e settings (UF/VF/WF)                                                     */
+            __IM uint32_t V : 1;       /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the
+                                        *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
+                                        *   e settings (UF/VF/WF)                                                     */
+            __IM uint32_t W : 1;       /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the
+                                        *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
+                                        *   e settings (UF/VF/WF)                                                     */
+            uint32_t          : 1;
+            __IOM uint32_t EN : 1;     /*!< [8..8] Enable-Phase Output Control                                        */
+            uint32_t          : 7;
+            __IOM uint32_t FB : 1;     /*!< [16..16] External Feedback Signal EnableThis bit selects the
+                                        *   input phase from the software settings and external input.                */
+            __IOM uint32_t P     : 1;  /*!< [17..17] Positive-Phase Output (P) Control                                */
+            __IOM uint32_t N     : 1;  /*!< [18..18] Negative-Phase Output (N) Control                                */
+            __IOM uint32_t INV   : 1;  /*!< [19..19] Invert-Phase Output Control                                      */
+            __IOM uint32_t RV    : 1;  /*!< [20..20] Output phase rotation direction reversal                         */
+            __IOM uint32_t ALIGN : 1;  /*!< [21..21] Input phase alignment                                            */
+            uint32_t             : 2;
+            __IOM uint32_t GRP   : 2;  /*!< [25..24] Output disabled source selection                                 */
+            __IOM uint32_t GODF  : 1;  /*!< [26..26] Group output disable function                                    */
+            uint32_t             : 2;
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] External Input Noise Filter Enable                               */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] External Input Noise Filter Clock selectionNoise filter
+                                        *   sampling clock setting of the external input.                             */
+        } OPSCR_b;
+    };
+} R_GPT_OPS_Type;                      /*!< Size = 4 (0x4)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                        R_GPT_POEG0                                        ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Port Output Enable for GPT (R_GPT_POEG0)
+ */
+
+typedef struct                         /*!< (@ 0x4008A000) R_GPT_POEG0 Structure                                      */
+{
+    union
+    {
+        __IOM uint32_t POEGG;          /*!< (@ 0x00000000) POEG Group Setting Register                                */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] Real Time Overcurrent Detection Flag                               */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection EnableNote: Can be modified only
+                                        *   once after a reset.                                                       */
+            __IOM uint32_t IOCE : 1;   /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified
+                                        *   only once after a reset.                                                  */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified
+                                        *   only once after a reset.                                                  */
+            uint32_t             : 1;
+            __IOM uint32_t CDRE0 : 1;  /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified
+                                        *   only once after a reset.                                                  */
+            __IOM uint32_t CDRE1 : 1;  /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified
+                                        *   only once after a reset.                                                  */
+            __IOM uint32_t CDRE2 : 1;  /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified
+                                        *   only once after a reset.                                                  */
+            __IOM uint32_t CDRE3 : 1;  /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified
+                                        *   only once after a reset.                                                  */
+            __IOM uint32_t CDRE4 : 1;  /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified
+                                        *   only once after a reset.                                                  */
+            __IOM uint32_t CDRE5 : 1;  /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified
+                                        *   only once after a reset.                                                  */
+            uint32_t            : 2;
+            __IM uint32_t ST    : 1;   /*!< [16..16] GTETRG Input Status Flag                                         */
+            uint32_t            : 11;
+            __IOM uint32_t INV  : 1;   /*!< [28..28] GTETRG Input Reverse                                             */
+            __IOM uint32_t NFEN : 1;   /*!< [29..29] Noise Filter Enable                                              */
+            __IOM uint32_t NFCS : 2;   /*!< [31..30] Noise Filter Clock Select                                        */
+        } POEGG_b;
+    };
+} R_GPT_POEG0_Type;                    /*!< Size = 4 (0x4)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ICU                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Interrupt Controller Unit (R_ICU)
+ */
+
+typedef struct                         /*!< (@ 0x40006000) R_ICU Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t IRQCR[16];       /*!< (@ 0x00000000) IRQ Control Register [0..15]                               */
+
+        struct
+        {
+            __IOM uint8_t IRQMD   : 2; /*!< [1..0] IRQ Detection Sense Select                                         */
+            uint8_t               : 2;
+            __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select                           */
+            uint8_t               : 1;
+            __IOM uint8_t FLTEN   : 1; /*!< [7..7] IRQ Digital Filter Enable                                          */
+        } IRQCR_b[16];
+    };
+    __IM uint32_t RESERVED[60];
+
+    union
+    {
+        __IOM uint8_t NMICR;            /*!< (@ 0x00000100) NMI Pin Interrupt Control Register                         */
+
+        struct
+        {
+            __IOM uint8_t NMIMD    : 1; /*!< [0..0] NMI Detection Set                                                  */
+            uint8_t                : 3;
+            __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select                           */
+            uint8_t                : 1;
+            __IOM uint8_t NFLTEN   : 1; /*!< [7..7] NMI Digital Filter Enable                                          */
+        } NMICR_b;
+    };
+    __IM uint8_t  RESERVED1;
+    __IM uint16_t RESERVED2;
+    __IM uint32_t RESERVED3[7];
+
+    union
+    {
+        __IOM uint16_t NMIER;           /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register                     */
+
+        struct
+        {
+            __IOM uint16_t IWDTEN  : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable                      */
+            __IOM uint16_t WDTEN   : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable                       */
+            __IOM uint16_t LVD1EN  : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable                              */
+            __IOM uint16_t LVD2EN  : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable                              */
+            __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable                                     */
+            uint16_t               : 1;
+            __IOM uint16_t OSTEN   : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable                        */
+            __IOM uint16_t NMIEN   : 1; /*!< [7..7] NMI Pin Interrupt Enable                                           */
+            __IOM uint16_t RPEEN   : 1; /*!< [8..8] RAM Parity Error Interrupt Enable                                  */
+            __IOM uint16_t RECCEN  : 1; /*!< [9..9] RAM ECC Error Interrupt Enable                                     */
+            __IOM uint16_t BUSSEN  : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable                             */
+            __IOM uint16_t BUSMEN  : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable                            */
+            __IOM uint16_t SPEEN   : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable                       */
+            __IOM uint16_t TZFEN   : 1; /*!< [13..13] TZFEN                                                            */
+            uint16_t               : 1;
+            __IOM uint16_t CPEEN   : 1; /*!< [15..15] CPEEN                                                            */
+        } NMIER_b;
+    };
+    __IM uint16_t RESERVED4;
+    __IM uint32_t RESERVED5[3];
+
+    union
+    {
+        __IOM uint16_t NMICLR;          /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register               */
+
+        struct
+        {
+            __OM uint16_t IWDTCLR  : 1; /*!< [0..0] IWDT Clear                                                         */
+            __OM uint16_t WDTCLR   : 1; /*!< [1..1] WDT Clear                                                          */
+            __OM uint16_t LVD1CLR  : 1; /*!< [2..2] LVD1 Clear                                                         */
+            __OM uint16_t LVD2CLR  : 1; /*!< [3..3] LVD2 Clear                                                         */
+            __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear                                                        */
+            uint16_t               : 1;
+            __OM uint16_t  OSTCLR  : 1; /*!< [6..6] OST Clear                                                          */
+            __OM uint16_t  NMICLR  : 1; /*!< [7..7] NMI Clear                                                          */
+            __OM uint16_t  RPECLR  : 1; /*!< [8..8] SRAM Parity Error Clear                                            */
+            __OM uint16_t  RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear                                               */
+            __OM uint16_t  BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear                                            */
+            __OM uint16_t  BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear                                           */
+            __OM uint16_t  SPECLR  : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear                        */
+            __IOM uint16_t TZFCLR  : 1; /*!< [13..13] TZFCLR                                                           */
+            uint16_t               : 1;
+            __IOM uint16_t CPECLR  : 1; /*!< [15..15] CPECLR                                                           */
+        } NMICLR_b;
+    };
+    __IM uint16_t RESERVED6;
+    __IM uint32_t RESERVED7[3];
+
+    union
+    {
+        __IM uint16_t NMISR;           /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register                     */
+
+        struct
+        {
+            __IM uint16_t IWDTST  : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag                           */
+            __IM uint16_t WDTST   : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag                            */
+            __IM uint16_t LVD1ST  : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag                         */
+            __IM uint16_t LVD2ST  : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag                         */
+            __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag                                */
+            uint16_t              : 1;
+            __IM uint16_t OSTST   : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag                   */
+            __IM uint16_t NMIST   : 1; /*!< [7..7] NMI Status Flag                                                    */
+            __IM uint16_t RPEST   : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag                             */
+            __IM uint16_t RECCST  : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag                                */
+            __IM uint16_t BUSSST  : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag                        */
+            __IM uint16_t BUSMST  : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag                       */
+            __IM uint16_t SPEST   : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag                  */
+            __IM uint16_t TZFST   : 1; /*!< [13..13] TZFST                                                            */
+            uint16_t              : 1;
+            __IM uint16_t CPEST   : 1; /*!< [15..15] CPEST                                                            */
+        } NMISR_b;
+    };
+    __IM uint16_t RESERVED8;
+    __IM uint32_t RESERVED9[23];
+
+    union
+    {
+        __IOM uint32_t WUPEN;                /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register                          */
+
+        struct
+        {
+            __IOM uint32_t IRQWUPEN0    : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN1    : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN2    : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN3    : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN4    : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN5    : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN6    : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN7    : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN8    : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN9    : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN10   : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable                         */
+            __IOM uint32_t IRQWUPEN11   : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable                         */
+            __IOM uint32_t IRQWUPEN12   : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable                         */
+            __IOM uint32_t IRQWUPEN13   : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable                         */
+            __IOM uint32_t IRQWUPEN14   : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable                         */
+            __IOM uint32_t IRQWUPEN15   : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable                         */
+            __IOM uint32_t IWDTWUPEN    : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable                        */
+            __IOM uint32_t KEYWUPEN     : 1; /*!< [17..17] Key interrupt S/W standby returns enable                         */
+            __IOM uint32_t LVD1WUPEN    : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable                        */
+            __IOM uint32_t LVD2WUPEN    : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable                        */
+            __IOM uint32_t VBATTWUPEN   : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable               */
+            uint32_t                    : 1;
+            __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit                 */
+            __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable                     */
+            __IOM uint32_t RTCALMWUPEN  : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable                   */
+            __IOM uint32_t RTCPRDWUPEN  : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable                  */
+            __IOM uint32_t USBHSWUPEN   : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit                   */
+            __IOM uint32_t USBFSWUPEN   : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable                       */
+            __IOM uint32_t AGT1UDWUPEN  : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable              */
+            __IOM uint32_t AGT1CAWUPEN  : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns
+                                              *   enable                                                                    */
+            __IOM uint32_t AGT1CBWUPEN : 1;  /*!< [30..30] AGT1 compare match B interrupt S/W standby returns
+                                              *   enable                                                                    */
+            __IOM uint32_t IIC0WUPEN : 1;    /*!< [31..31] IIC0 address match interrupt S/W standby returns enable          */
+        } WUPEN_b;
+    };
+
+    union
+    {
+        __IOM uint32_t WUPEN1;              /*!< (@ 0x000001A4) Wake Up interrupt enable register 1                        */
+
+        struct
+        {
+            __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit            */
+            __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable
+                                             *   bit                                                                       */
+            __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable
+                                             *   bit                                                                       */
+            uint32_t : 29;
+        } WUPEN1_b;
+    };
+    __IM uint32_t RESERVED10[6];
+
+    union
+    {
+        __IOM uint8_t IELEN;            /*!< (@ 0x000001C0) ICU event Enable Register                                  */
+
+        struct
+        {
+            __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit
+                                         *   = 1)                                                                      */
+            __IOM uint8_t IELEN : 1;    /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when
+                                         *   LPOPTEN bit = 1)                                                          */
+            uint8_t : 6;
+        } IELEN_b;
+    };
+    __IM uint8_t  RESERVED11;
+    __IM uint16_t RESERVED12;
+    __IM uint32_t RESERVED13[15];
+
+    union
+    {
+        __IOM uint16_t SELSR0;         /*!< (@ 0x00000200) Snooze Event Link Setting Register                         */
+
+        struct
+        {
+            __IOM uint16_t SELS : 9;   /*!< [8..0] SYS Event Link Select                                              */
+            uint16_t            : 7;
+        } SELSR0_b;
+    };
+    __IM uint16_t RESERVED14;
+    __IM uint32_t RESERVED15[31];
+
+    union
+    {
+        __IOM uint32_t DELSR[8];       /*!< (@ 0x00000280) DMAC Event Link Setting Register                           */
+
+        struct
+        {
+            __IOM uint32_t DELS : 9;   /*!< [8..0] Event selection to DMAC Start request                              */
+            uint32_t            : 7;
+            __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
+                                        *   IR flag is prohibited.                                                    */
+            uint32_t : 15;
+        } DELSR_b[8];
+    };
+    __IM uint32_t RESERVED16[24];
+
+    union
+    {
+        __IOM uint32_t IELSR[96];      /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95]                    */
+
+        struct
+        {
+            __IOM uint32_t IELS : 9;   /*!< [8..0] ICU Event selection to NVICSet the number for the event
+                                        *   signal to be linked .                                                     */
+            uint32_t            : 7;
+            __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag                                            */
+            uint32_t            : 7;
+            __IOM uint32_t DTCE : 1;   /*!< [24..24] DTC Activation Enable                                            */
+            uint32_t            : 7;
+        } IELSR_b[96];
+    };
+} R_ICU_Type;                          /*!< Size = 1152 (0x480)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_IIC0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I2C Bus Interface (R_IIC0)
+ */
+
+typedef struct                         /*!< (@ 0x4009F000) R_IIC0 Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t ICCR1;           /*!< (@ 0x00000000) I2C Bus Control Register 1                                 */
+
+        struct
+        {
+            __IM uint8_t  SDAI   : 1;  /*!< [0..0] SDA Line Monitor                                                   */
+            __IM uint8_t  SCLI   : 1;  /*!< [1..1] SCL Line Monitor                                                   */
+            __IOM uint8_t SDAO   : 1;  /*!< [2..2] SDA Output Control/Monitor                                         */
+            __IOM uint8_t SCLO   : 1;  /*!< [3..3] SCL Output Control/Monitor                                         */
+            __IOM uint8_t SOWP   : 1;  /*!< [4..4] SCLO/SDAO Write Protect                                            */
+            __IOM uint8_t CLO    : 1;  /*!< [5..5] Extra SCL Clock Cycle Output                                       */
+            __IOM uint8_t IICRST : 1;  /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset
+                                        *   is initiated using the IICRST bit for a bus hang-up occurred
+                                        *   during communication with the master device in slave mode,
+                                        *   the states may become different between the slave device
+                                        *   and the master device (due to the difference in the bit
+                                        *   counter information).                                                     */
+            __IOM uint8_t ICE : 1;     /*!< [7..7] I2C Bus Interface Enable                                           */
+        } ICCR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICCR2;           /*!< (@ 0x00000001) I2C Bus Control Register 2                                 */
+
+        struct
+        {
+            uint8_t          : 1;
+            __IOM uint8_t ST : 1;      /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start
+                                        *   condition issuance request) when the BBSY flag is set to
+                                        *   0 (bus free state).                                                       */
+            __IOM uint8_t RS : 1;      /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the
+                                        *   RS bit to 1 while issuing a stop condition.                               */
+            __IOM uint8_t SP : 1;      /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP
+                                        *   bit is not possible while the setting of the BBSY flag
+                                        *   is 0 (bus free state).Note: Do not set the SP bit to 1
+                                        *   while a restart condition is being issued.                                */
+            uint8_t            : 1;
+            __IOM uint8_t TRS  : 1;    /*!< [5..5] Transmit/Receive Mode                                              */
+            __IOM uint8_t MST  : 1;    /*!< [6..6] Master/Slave Mode                                                  */
+            __IM uint8_t  BBSY : 1;    /*!< [7..7] Bus Busy Detection Flag                                            */
+        } ICCR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICMR1;           /*!< (@ 0x00000002) I2C Bus Mode Register 1                                    */
+
+        struct
+        {
+            __IOM uint8_t BC   : 3;    /*!< [2..0] Bit Counter                                                        */
+            __OM uint8_t  BCWP : 1;    /*!< [3..3] BC Write Protect(This bit is read as 1.)                           */
+            __IOM uint8_t CKS  : 3;    /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB
+                                        *   / 2^CKS )                                                                 */
+            __IOM uint8_t MTWP : 1;    /*!< [7..7] MST/TRS Write Protect                                              */
+        } ICMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICMR2;           /*!< (@ 0x00000003) I2C Bus Mode Register 2                                    */
+
+        struct
+        {
+            __IOM uint8_t TMOS : 1;    /*!< [0..0] Timeout Detection Time Select                                      */
+            __IOM uint8_t TMOL : 1;    /*!< [1..1] Timeout L Count Control                                            */
+            __IOM uint8_t TMOH : 1;    /*!< [2..2] Timeout H Count Control                                            */
+            uint8_t            : 1;
+            __IOM uint8_t SDDL : 3;    /*!< [6..4] SDA Output Delay Counter                                           */
+            __IOM uint8_t DLCS : 1;    /*!< [7..7] SDA Output Delay Clock Source Select                               */
+        } ICMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICMR3;           /*!< (@ 0x00000004) I2C Bus Mode Register 3                                    */
+
+        struct
+        {
+            __IOM uint8_t NF    : 2;   /*!< [1..0] Noise Filter Stage Selection                                       */
+            __IM uint8_t  ACKBR : 1;   /*!< [2..2] Receive Acknowledge                                                */
+            __IOM uint8_t ACKBT : 1;   /*!< [3..3] Transmit Acknowledge                                               */
+            __IOM uint8_t ACKWP : 1;   /*!< [4..4] ACKBT Write Protect                                                */
+            __IOM uint8_t RDRFS : 1;   /*!< [5..5] RDRF Flag Set Timing Selection                                     */
+            __IOM uint8_t WAIT  : 1;   /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read,
+                                        *   be sure to read the ICDRR beforehand.                                     */
+            __IOM uint8_t SMBS : 1;    /*!< [7..7] SMBus/I2C Bus Selection                                            */
+        } ICMR3_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICFER;           /*!< (@ 0x00000005) I2C Bus Function Enable Register                           */
+
+        struct
+        {
+            __IOM uint8_t TMOE  : 1;   /*!< [0..0] Timeout Function Enable                                            */
+            __IOM uint8_t MALE  : 1;   /*!< [1..1] Master Arbitration-Lost Detection Enable                           */
+            __IOM uint8_t NALE  : 1;   /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable                */
+            __IOM uint8_t SALE  : 1;   /*!< [3..3] Slave Arbitration-Lost Detection Enable                            */
+            __IOM uint8_t NACKE : 1;   /*!< [4..4] NACK Reception Transfer Suspension Enable                          */
+            __IOM uint8_t NFE   : 1;   /*!< [5..5] Digital Noise Filter Circuit Enable                                */
+            __IOM uint8_t SCLE  : 1;   /*!< [6..6] SCL Synchronous Circuit Enable                                     */
+            __IOM uint8_t FMPE  : 1;   /*!< [7..7] Fast-mode Plus Enable                                              */
+        } ICFER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICSER;           /*!< (@ 0x00000006) I2C Bus Status Enable Register                             */
+
+        struct
+        {
+            __IOM uint8_t SAR0E : 1;   /*!< [0..0] Slave Address Register 0 Enable                                    */
+            __IOM uint8_t SAR1E : 1;   /*!< [1..1] Slave Address Register 1 Enable                                    */
+            __IOM uint8_t SAR2E : 1;   /*!< [2..2] Slave Address Register 2 Enable                                    */
+            __IOM uint8_t GCAE  : 1;   /*!< [3..3] General Call Address Enable                                        */
+            uint8_t             : 1;
+            __IOM uint8_t DIDE  : 1;   /*!< [5..5] Device-ID Address Detection Enable                                 */
+            uint8_t             : 1;
+            __IOM uint8_t HOAE  : 1;   /*!< [7..7] Host Address Enable                                                */
+        } ICSER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICIER;           /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register                          */
+
+        struct
+        {
+            __IOM uint8_t TMOIE : 1;   /*!< [0..0] Timeout Interrupt Request Enable                                   */
+            __IOM uint8_t ALIE  : 1;   /*!< [1..1] Arbitration-Lost Interrupt Request Enable                          */
+            __IOM uint8_t STIE  : 1;   /*!< [2..2] Start Condition Detection Interrupt Request Enable                 */
+            __IOM uint8_t SPIE  : 1;   /*!< [3..3] Stop Condition Detection Interrupt Request Enable                  */
+            __IOM uint8_t NAKIE : 1;   /*!< [4..4] NACK Reception Interrupt Request Enable                            */
+            __IOM uint8_t RIE   : 1;   /*!< [5..5] Receive Data Full Interrupt Request Enable                         */
+            __IOM uint8_t TEIE  : 1;   /*!< [6..6] Transmit End Interrupt Request Enable                              */
+            __IOM uint8_t TIE   : 1;   /*!< [7..7] Transmit Data Empty Interrupt Request Enable                       */
+        } ICIER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICSR1;           /*!< (@ 0x00000008) I2C Bus Status Register 1                                  */
+
+        struct
+        {
+            __IOM uint8_t AAS0 : 1;    /*!< [0..0] Slave Address 0 Detection Flag                                     */
+            __IOM uint8_t AAS1 : 1;    /*!< [1..1] Slave Address 1 Detection Flag                                     */
+            __IOM uint8_t AAS2 : 1;    /*!< [2..2] Slave Address 2 Detection Flag                                     */
+            __IOM uint8_t GCA  : 1;    /*!< [3..3] General Call Address Detection Flag                                */
+            uint8_t            : 1;
+            __IOM uint8_t DID  : 1;    /*!< [5..5] Device-ID Address Detection Flag                                   */
+            uint8_t            : 1;
+            __IOM uint8_t HOA  : 1;    /*!< [7..7] Host Address Detection Flag                                        */
+        } ICSR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICSR2;           /*!< (@ 0x00000009) I2C Bus Status Register 2                                  */
+
+        struct
+        {
+            __IOM uint8_t TMOF  : 1;   /*!< [0..0] Timeout Detection Flag                                             */
+            __IOM uint8_t AL    : 1;   /*!< [1..1] Arbitration-Lost Flag                                              */
+            __IOM uint8_t START : 1;   /*!< [2..2] Start Condition Detection Flag                                     */
+            __IOM uint8_t STOP  : 1;   /*!< [3..3] Stop Condition Detection Flag                                      */
+            __IOM uint8_t NACKF : 1;   /*!< [4..4] NACK Detection Flag                                                */
+            __IOM uint8_t RDRF  : 1;   /*!< [5..5] Receive Data Full Flag                                             */
+            __IOM uint8_t TEND  : 1;   /*!< [6..6] Transmit End Flag                                                  */
+            __IM uint8_t  TDRE  : 1;   /*!< [7..7] Transmit Data Empty Flag                                           */
+        } ICSR2_b;
+    };
+    __IOM R_IIC0_SAR_Type SAR[3];      /*!< (@ 0x0000000A) Slave Address Registers                                    */
+
+    union
+    {
+        __IOM uint8_t ICBRL;           /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register                        */
+
+        struct
+        {
+            __IOM uint8_t BRL : 5;     /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock)           */
+            uint8_t           : 3;
+        } ICBRL_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICBRH;           /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register                       */
+
+        struct
+        {
+            __IOM uint8_t BRH : 5;     /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock)         */
+            uint8_t           : 3;
+        } ICBRH_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICDRT;           /*!< (@ 0x00000012) I2C Bus Transmit Data Register                             */
+
+        struct
+        {
+            __IOM uint8_t ICDRT : 8;   /*!< [7..0] 8-bit read-write register that stores transmit data.               */
+        } ICDRT_b;
+    };
+
+    union
+    {
+        __IM uint8_t ICDRR;            /*!< (@ 0x00000013) I2C Bus Receive Data Register                              */
+
+        struct
+        {
+            __IM uint8_t ICDRR : 8;    /*!< [7..0] 8-bit register that stores the received data                       */
+        } ICDRR_b;
+    };
+    __IM uint8_t RESERVED[2];
+
+    union
+    {
+        __IOM uint8_t ICWUR;           /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register                              */
+
+        struct
+        {
+            __IOM uint8_t WUAFA : 1;   /*!< [0..0] Wakeup Analog Filter Additional Selection                          */
+            uint8_t             : 3;
+            __IOM uint8_t WUACK : 1;   /*!< [4..4] ACK bit for Wakeup Mode                                            */
+            __IOM uint8_t WUF   : 1;   /*!< [5..5] Wakeup Event Occurrence Flag                                       */
+            __IOM uint8_t WUIE  : 1;   /*!< [6..6] Wakeup Interrupt Request Enable                                    */
+            __IOM uint8_t WUE   : 1;   /*!< [7..7] Wakeup Function Enable                                             */
+        } ICWUR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICWUR2;          /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2                            */
+
+        struct
+        {
+            __IM uint8_t WUSEN  : 1;   /*!< [0..0] Wake-up Function Synchronous Enable                                */
+            __IM uint8_t WUASYF : 1;   /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag                */
+            __IM uint8_t WUSYF  : 1;   /*!< [2..2] Wake-up Function Synchronous Operation Status Flag                 */
+            uint8_t             : 5;
+        } ICWUR2_b;
+    };
+} R_IIC0_Type;                         /*!< Size = 24 (0x18)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_IWDT                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Independent Watchdog Timer (R_IWDT)
+ */
+
+typedef struct                         /*!< (@ 0x40083200) R_IWDT Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t IWDTRR;          /*!< (@ 0x00000000) IWDT Refresh Register                                      */
+
+        struct
+        {
+            __IOM uint8_t IWDTRR : 8;  /*!< [7..0] The counter is refreshed by writing 0x00 and then writing
+                                        *   0xFF to this register.                                                    */
+        } IWDTRR_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t IWDTCR;         /*!< (@ 0x00000002) IWDT Control Register                                      */
+
+        struct
+        {
+            __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
+            uint16_t            : 2;
+            __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
+            __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
+            uint16_t            : 2;
+            __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
+            uint16_t            : 2;
+        } IWDTCR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t IWDTSR;          /*!< (@ 0x00000004) IWDT Status Register                                       */
+
+        struct
+        {
+            __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
+            __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
+            __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
+        } IWDTSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t IWDTRCR;         /*!< (@ 0x00000006) IWDT Reset Control Register                                */
+
+        struct
+        {
+            uint8_t               : 7;
+            __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
+        } IWDTRCR_b;
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        __IOM uint8_t IWDTCSTPR;       /*!< (@ 0x00000008) IWDT Count Stop Control Register                           */
+
+        struct
+        {
+            uint8_t              : 7;
+            __IOM uint8_t SLCSTP : 1;  /*!< [7..7] Sleep-Mode Count Stop Control                                      */
+        } IWDTCSTPR_b;
+    };
+    __IM uint8_t  RESERVED2;
+    __IM uint16_t RESERVED3;
+} R_IWDT_Type;                         /*!< Size = 12 (0xc)                                                           */
+
+/* =========================================================================================================================== */
+/* ================                                          R_I3C0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I3C Bus Interface (R_I3C0)
+ */
+
+typedef struct                         /*!< (@ 0x4011F000) R_I3C0 Structure                                           */
+{
+    union
+    {
+        __IOM uint32_t PRTS;           /*!< (@ 0x00000000) Protocol Selection Register                                */
+
+        struct
+        {
+            __IOM uint32_t PRTMD : 1;  /*!< [0..0] Protocol Mode                                                      */
+            uint32_t             : 31;
+        } PRTS_b;
+    };
+    __IM uint32_t RESERVED[3];
+
+    union
+    {
+        __IOM uint32_t CECTL;          /*!< (@ 0x00000010) Clock Enable Control Resisters                             */
+
+        struct
+        {
+            __IOM uint32_t CLKE : 1;   /*!< [0..0] Clock Enable                                                       */
+            uint32_t            : 31;
+        } CECTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BCTL;             /*!< (@ 0x00000014) Bus Control Register                                       */
+
+        struct
+        {
+            __IOM uint32_t INCBA    : 1; /*!< [0..0] Include I3C Broadcast Address                                      */
+            uint32_t                : 6;
+            __IOM uint32_t BMDS     : 1; /*!< [7..7] Bus Mode Selection                                                 */
+            __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control                                       */
+            uint32_t                : 20;
+            __IOM uint32_t ABT      : 1; /*!< [29..29] Abort                                                            */
+            __IOM uint32_t RSM      : 1; /*!< [30..30] Resume                                                           */
+            __IOM uint32_t BUSE     : 1; /*!< [31..31] Bus Enable                                                       */
+        } BCTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSDVAD;         /*!< (@ 0x00000018) Master Device Address Register                             */
+
+        struct
+        {
+            uint32_t              : 16;
+            __IOM uint32_t MDYAD  : 7; /*!< [22..16] Master Dynamic Address                                           */
+            uint32_t              : 8;
+            __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid                                     */
+        } MSDVAD_b;
+    };
+    __IM uint32_t RESERVED1;
+
+    union
+    {
+        __IOM uint32_t RSTCTL;          /*!< (@ 0x00000020) Reset Control Register                                     */
+
+        struct
+        {
+            __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset                                                 */
+            __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset                                       */
+            __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset                                      */
+            __IOM uint32_t TDBRST  : 1; /*!< [3..3] Transmit Data Buffer Software Reset                                */
+            __IOM uint32_t RDBRST  : 1; /*!< [4..4] Receive Data Buffer Software Reset                                 */
+            __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset                                           */
+            __IOM uint32_t RSQRST  : 1; /*!< [6..6] Receive Status Queue Software Reset                                */
+            uint32_t               : 9;
+            __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset                                          */
+            uint32_t               : 15;
+        } RSTCTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PRSST;          /*!< (@ 0x00000024) Present State Register                                     */
+
+        struct
+        {
+            uint32_t              : 2;
+            __IOM uint32_t CRMS   : 1; /*!< [2..2] Current Master                                                     */
+            uint32_t              : 1;
+            __IM uint32_t TRMD    : 1; /*!< [4..4] Transmit/Receive Mode                                              */
+            uint32_t              : 2;
+            __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect                                        */
+            uint32_t              : 24;
+        } PRSST_b;
+    };
+    __IM uint32_t RESERVED2[2];
+
+    union
+    {
+        __IOM uint32_t INST;           /*!< (@ 0x00000030) Internal Status Register                                   */
+
+        struct
+        {
+            uint32_t            : 10;
+            __IOM uint32_t INEF : 1;   /*!< [10..10] Internal Error Flag                                              */
+            uint32_t            : 21;
+        } INST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t INSTE;          /*!< (@ 0x00000034) Internal Status Enable Register                            */
+
+        struct
+        {
+            uint32_t            : 10;
+            __IOM uint32_t INEE : 1;   /*!< [10..10] Internal Error Enable                                            */
+            uint32_t            : 21;
+        } INSTE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t INIE;           /*!< (@ 0x00000038) Internal Interrupt Enable Register                         */
+
+        struct
+        {
+            uint32_t             : 10;
+            __IOM uint32_t INEIE : 1;  /*!< [10..10] Internal Error Interrupt Enable                                  */
+            uint32_t             : 21;
+        } INIE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t INSTFC;         /*!< (@ 0x0000003C) Internal Status Force Register                             */
+
+        struct
+        {
+            uint32_t            : 10;
+            __OM uint32_t INEFC : 1;   /*!< [10..10] Internal Error Force                                             */
+            uint32_t            : 21;
+        } INSTFC_b;
+    };
+    __IM uint32_t RESERVED3;
+
+    union
+    {
+        __IM uint32_t DVCT;            /*!< (@ 0x00000044) Device Characteristic Table Register                       */
+
+        struct
+        {
+            uint32_t          : 19;
+            __IM uint32_t IDX : 5;     /*!< [23..19] DCT Table Index                                                  */
+            uint32_t          : 8;
+        } DVCT_b;
+    };
+    __IM uint32_t RESERVED4[4];
+
+    union
+    {
+        __IOM uint32_t IBINCTL;          /*!< (@ 0x00000058) IBI Notify Control Register                                */
+
+        struct
+        {
+            __IOM uint32_t NRHJCTL  : 1; /*!< [0..0] Notify Rejected Hot-Join Control                                   */
+            __IOM uint32_t NRMRCTL  : 1; /*!< [1..1] Notify Rejected Master Request Control                             */
+            uint32_t                : 1;
+            __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control                    */
+            uint32_t                : 28;
+        } IBINCTL_b;
+    };
+    __IM uint32_t RESERVED5;
+
+    union
+    {
+        __IOM uint32_t BFCTL;          /*!< (@ 0x00000060) Bus Function Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t MALE   : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable                           */
+            __IOM uint32_t NALE   : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable                */
+            __IOM uint32_t SALE   : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable                            */
+            uint32_t              : 5;
+            __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable                                     */
+            uint32_t              : 3;
+            __IOM uint32_t SMBS   : 1; /*!< [12..12] SMBus/I2C Bus Selection                                          */
+            uint32_t              : 1;
+            __IOM uint32_t FMPE   : 1; /*!< [14..14] Fast-mode Plus Enable                                            */
+            __IOM uint32_t HSME   : 1; /*!< [15..15] High Speed Mode Enable                                           */
+            uint32_t              : 16;
+        } BFCTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SVCTL;          /*!< (@ 0x00000064) Slave Control Register                                     */
+
+        struct
+        {
+            __IOM uint32_t GCAE  : 1;  /*!< [0..0] General Call Address Enable                                        */
+            uint32_t             : 4;
+            __IOM uint32_t HSMCE : 1;  /*!< [5..5] Hs-mode Master Code Enable                                         */
+            __IOM uint32_t DVIDE : 1;  /*!< [6..6] Device-ID Address Enable                                           */
+            uint32_t             : 8;
+            __IOM uint32_t HOAE  : 1;  /*!< [15..15] Host Address Enable                                              */
+            __IOM uint32_t SVAEn : 1;  /*!< [16..16] Slave Address Enable n (n = 0)                                   */
+            uint32_t             : 15;
+        } SVCTL_b;
+    };
+    __IM uint32_t RESERVED6[2];
+
+    union
+    {
+        __IOM uint32_t REFCKCTL;        /*!< (@ 0x00000070) Reference Clock Control Register                           */
+
+        struct
+        {
+            __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection                                 */
+            uint32_t               : 29;
+        } REFCKCTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STDBR;          /*!< (@ 0x00000074) Standard Bit Rate Register                                 */
+
+        struct
+        {
+            __IOM uint32_t SBRLO  : 8; /*!< [7..0] Count value of the Low-level period of SCL clock                   */
+            __IOM uint32_t SBRHO  : 8; /*!< [15..8] Count value of the High-level period of SCL clock                 */
+            __IOM uint32_t SBRLP  : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull                     */
+            uint32_t              : 2;
+            __IOM uint32_t SBRHP  : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull                    */
+            uint32_t              : 1;
+            __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain               */
+        } STDBR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EXTBR;          /*!< (@ 0x00000078) Extended Bit Rate Register                                 */
+
+        struct
+        {
+            __IOM uint32_t EBRLO : 8;  /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain                      */
+            __IOM uint32_t EBRHO : 8;  /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain                    */
+            __IOM uint32_t EBRLP : 6;  /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull                     */
+            uint32_t             : 2;
+            __IOM uint32_t EBRHP : 6;  /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull                     */
+            uint32_t             : 2;
+        } EXTBR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BFRECDT;        /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register                 */
+
+        struct
+        {
+            __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle                                 */
+            uint32_t              : 23;
+        } BFRECDT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BAVLCDT;        /*!< (@ 0x00000080) Bus Available Condition Detection Time Register            */
+
+        struct
+        {
+            __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle                            */
+            uint32_t              : 23;
+        } BAVLCDT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BIDLCDT;         /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register                 */
+
+        struct
+        {
+            __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle                                */
+            uint32_t              : 14;
+        } BIDLCDT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t OUTCTL;         /*!< (@ 0x00000088) Output Control Register                                    */
+
+        struct
+        {
+            __IOM uint32_t SDOC   : 1; /*!< [0..0] SDA Output Control                                                 */
+            __IOM uint32_t SCOC   : 1; /*!< [1..1] SCL Output Control                                                 */
+            __OM uint32_t  SOCWP  : 1; /*!< [2..2] SCL/SDA Output Control Write Protect                               */
+            uint32_t              : 1;
+            __IOM uint32_t EXCYC  : 1; /*!< [4..4] Extra SCL Clock Cycle Output                                       */
+            uint32_t              : 3;
+            __IOM uint32_t SDOD   : 3; /*!< [10..8] SDA Output Delay                                                  */
+            uint32_t              : 4;
+            __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection                          */
+            uint32_t              : 16;
+        } OUTCTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t INCTL;          /*!< (@ 0x0000008C) Input Control Register                                     */
+
+        struct
+        {
+            __IOM uint32_t DNFS : 4;   /*!< [3..0] Digital Noise Filter Stage Selection                               */
+            __IOM uint32_t DNFE : 1;   /*!< [4..4] Digital Noise Filter Circuit Enable                                */
+            uint32_t            : 27;
+        } INCTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TMOCTL;         /*!< (@ 0x00000090) Timeout Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t TODTS  : 2; /*!< [1..0] Timeout Detection Time Selection                                   */
+            uint32_t              : 2;
+            __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control                                            */
+            __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control                                            */
+            __IOM uint32_t TOMDS  : 2; /*!< [7..6] Timeout Operation Mode Selection                                   */
+            uint32_t              : 24;
+        } TMOCTL_b;
+    };
+    __IM uint32_t RESERVED7;
+
+    union
+    {
+        __IOM uint32_t WUCTL;           /*!< (@ 0x00000098) Wake Up Unit Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t WUACKS  : 1; /*!< [0..0] Wake-Up Acknowledge Selection                                      */
+            uint32_t               : 3;
+            __IOM uint32_t WUANFS  : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection                              */
+            uint32_t               : 1;
+            __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable                          */
+            __IOM uint32_t WUFE    : 1; /*!< [7..7] Wake-Up function Enable.                                           */
+            uint32_t               : 24;
+        } WUCTL_b;
+    };
+    __IM uint32_t RESERVED8;
+
+    union
+    {
+        __IOM uint32_t ACKCTL;         /*!< (@ 0x000000A0) Acknowledge Control Register                               */
+
+        struct
+        {
+            __IM uint32_t  ACKR   : 1; /*!< [0..0] Acknowledge Reception                                              */
+            __IOM uint32_t ACKT   : 1; /*!< [1..1] Acknowledge Transmission                                           */
+            __OM uint32_t  ACKTWP : 1; /*!< [2..2] ACKT Write Protect                                                 */
+            uint32_t              : 29;
+        } ACKCTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SCSTRCTL;       /*!< (@ 0x000000A4) SCL Stretch Control Register                               */
+
+        struct
+        {
+            __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable                               */
+            __IOM uint32_t RWE    : 1; /*!< [1..1] Receive Wait Enable                                                */
+            uint32_t              : 30;
+        } SCSTRCTL_b;
+    };
+    __IM uint32_t RESERVED9[2];
+
+    union
+    {
+        __IOM uint32_t SCSTLCTL;        /*!< (@ 0x000000B0) SCL Stalling Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle                                                    */
+            uint32_t              : 12;
+            __IOM uint32_t AAPE   : 1;  /*!< [28..28] Assigend Address Phase Enable                                    */
+            __IOM uint32_t TRAPE  : 1;  /*!< [29..29] Transition Phase Enable                                          */
+            __IOM uint32_t PARPE  : 1;  /*!< [30..30] Parity Phase Enable                                              */
+            __IOM uint32_t ACKPE  : 1;  /*!< [31..31] ACK phase Enable                                                 */
+        } SCSTLCTL_b;
+    };
+    __IM uint32_t RESERVED10[3];
+
+    union
+    {
+        __IOM uint32_t SVTDLG0;        /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0                      */
+
+        struct
+        {
+            uint32_t             : 16;
+            __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length                                       */
+        } SVTDLG0_b;
+    };
+    __IM uint32_t RESERVED11[31];
+
+    union
+    {
+        __IOM uint32_t CNDCTL;         /*!< (@ 0x00000140) Condition Control Register                                 */
+
+        struct
+        {
+            __IOM uint32_t STCND : 1;  /*!< [0..0] START (S) Condition Issuance                                       */
+            __IOM uint32_t SRCND : 1;  /*!< [1..1] Repeated START (Sr) Condition Issuance                             */
+            __IOM uint32_t SPCND : 1;  /*!< [2..2] STOP (P) Condition Issuance                                        */
+            uint32_t             : 29;
+        } CNDCTL_b;
+    };
+    __IM uint32_t  RESERVED12[3];
+    __OM uint32_t  NCMDQP;             /*!< (@ 0x00000150) Normal Command Queue Port Register                         */
+    __IM uint32_t  NRSPQP;             /*!< (@ 0x00000154) Normal Response Queue Port Register                        */
+    __IOM uint32_t NTDTBP0;            /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0                */
+    __IM uint32_t  RESERVED13[8];
+    __IOM uint32_t NIBIQP;             /*!< (@ 0x0000017C) Normal IBI Queue Port Register                             */
+    __IM uint32_t  NRSQP;              /*!< (@ 0x00000180) Normal Receive Status Queue Port Register                  */
+    __IM uint32_t  RESERVED14[3];
+
+    union
+    {
+        __IOM uint32_t NQTHCTL;         /*!< (@ 0x00000190) Normal Queue Threshold Control Register                    */
+
+        struct
+        {
+            __IOM uint32_t CMDQTH  : 8; /*!< [7..0] Normal Command Ready Queue Threshold                               */
+            __IOM uint32_t RSPQTH  : 8; /*!< [15..8] Normal Response Queue Threshold                                   */
+            __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size                                     */
+            __IOM uint32_t IBIQTH  : 8; /*!< [31..24] Normal IBI Queue Threshold                                       */
+        } NQTHCTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t NTBTHCTL0;      /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control
+                                        *                  Register 0                                                 */
+
+        struct
+        {
+            __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold                              */
+            uint32_t              : 5;
+            __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold                              */
+            uint32_t              : 5;
+            __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold                                        */
+            uint32_t              : 5;
+            __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold                                        */
+            uint32_t              : 5;
+        } NTBTHCTL0_b;
+    };
+    __IM uint32_t RESERVED15[10];
+
+    union
+    {
+        __IOM uint32_t NRQTHCTL;       /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t RSQTH : 8;  /*!< [7..0] Normal Receive Status Queue Threshold                              */
+            uint32_t             : 24;
+        } NRQTHCTL_b;
+    };
+    __IM uint32_t RESERVED16[3];
+
+    union
+    {
+        __IOM uint32_t BST;             /*!< (@ 0x000001D0) Bus Status Register                                        */
+
+        struct
+        {
+            __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag                                     */
+            __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag                                      */
+            __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag                                    */
+            uint32_t               : 1;
+            __IOM uint32_t NACKDF  : 1; /*!< [4..4] NACK Detection Flag                                                */
+            uint32_t               : 3;
+            __IOM uint32_t TENDF   : 1; /*!< [8..8] Transmit End Flag                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ALF     : 1; /*!< [16..16] Arbitration Lost Flag                                            */
+            uint32_t               : 3;
+            __IOM uint32_t TODF    : 1; /*!< [20..20] Timeout Detection Flag                                           */
+            uint32_t               : 11;
+        } BST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BSTE;            /*!< (@ 0x000001D4) Bus Status Enable Register                                 */
+
+        struct
+        {
+            __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable                                   */
+            __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable                                    */
+            __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable                                  */
+            uint32_t               : 1;
+            __IOM uint32_t NACKDE  : 1; /*!< [4..4] NACK Detection Enable                                              */
+            uint32_t               : 3;
+            __IOM uint32_t TENDE   : 1; /*!< [8..8] Transmit End Enable                                                */
+            uint32_t               : 7;
+            __IOM uint32_t ALE     : 1; /*!< [16..16] Arbitration Lost Enable                                          */
+            uint32_t               : 3;
+            __IOM uint32_t TODE    : 1; /*!< [20..20] Timeout Detection Enable                                         */
+            uint32_t               : 11;
+        } BSTE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BIE;              /*!< (@ 0x000001D8) Bus Interrupt Enable Register                              */
+
+        struct
+        {
+            __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable                         */
+            __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable                          */
+            __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable                        */
+            uint32_t                : 1;
+            __IOM uint32_t NACKDIE  : 1; /*!< [4..4] NACK Detection Interrupt Enable                                    */
+            uint32_t                : 3;
+            __IOM uint32_t TENDIE   : 1; /*!< [8..8] Transmit End Interrupt Enable                                      */
+            uint32_t                : 7;
+            __IOM uint32_t ALIE     : 1; /*!< [16..16] Arbitration Lost Interrupt Enable                                */
+            uint32_t                : 3;
+            __IOM uint32_t TODIE    : 1; /*!< [20..20] Timeout Detection Interrupt Enable                               */
+            uint32_t                : 11;
+        } BIE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BSTFC;           /*!< (@ 0x000001DC) Bus Status Force Register                                  */
+
+        struct
+        {
+            __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force                                    */
+            __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force                                     */
+            __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force                                   */
+            uint32_t               : 1;
+            __OM uint32_t NACKDFC  : 1; /*!< [4..4] NACK Detection Force                                               */
+            uint32_t               : 3;
+            __OM uint32_t TENDFC   : 1; /*!< [8..8] Transmit End Force                                                 */
+            uint32_t               : 7;
+            __OM uint32_t ALFC     : 1; /*!< [16..16] Arbitration Lost Force                                           */
+            uint32_t               : 3;
+            __OM uint32_t TODFC    : 1; /*!< [20..20] Timeout Detection Force                                          */
+            uint32_t               : 11;
+        } BSTFC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t NTST;            /*!< (@ 0x000001E0) Normal Transfer Status Register                            */
+
+        struct
+        {
+            __IOM uint32_t TDBEF0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0                           */
+            __IOM uint32_t RDBFF0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0                             */
+            __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag                                   */
+            __IOM uint32_t CMDQEF  : 1; /*!< [3..3] Normal Command Queue Empty Flag                                    */
+            __IOM uint32_t RSPQFF  : 1; /*!< [4..4] Normal Response Queue Full Flag                                    */
+            __IOM uint32_t TABTF   : 1; /*!< [5..5] Normal Transfer Abort Flag                                         */
+            uint32_t               : 3;
+            __IOM uint32_t TEF     : 1; /*!< [9..9] Normal Transfer Error Flag                                         */
+            uint32_t               : 10;
+            __IOM uint32_t RSQFF   : 1; /*!< [20..20] Normal Receive Status Queue Full Flag                            */
+            uint32_t               : 11;
+        } NTST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t NTSTE;           /*!< (@ 0x000001E4) Normal Transfer Status Enable Register                     */
+
+        struct
+        {
+            __IOM uint32_t TDBEE0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0                         */
+            __IOM uint32_t RDBFE0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0                           */
+            __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable                                 */
+            __IOM uint32_t CMDQEE  : 1; /*!< [3..3] Normal Command Queue Empty Enable                                  */
+            __IOM uint32_t RSPQFE  : 1; /*!< [4..4] Normal Response Queue Full Enable                                  */
+            __IOM uint32_t TABTE   : 1; /*!< [5..5] Normal Transfer Abort Enable                                       */
+            uint32_t               : 3;
+            __IOM uint32_t TEE     : 1; /*!< [9..9] Normal Transfer Error Enable                                       */
+            uint32_t               : 10;
+            __IOM uint32_t RSQFE   : 1; /*!< [20..20] Normal Receive Status Queue Full Enable                          */
+            uint32_t               : 11;
+        } NTSTE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t NTIE;             /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register                  */
+
+        struct
+        {
+            __IOM uint32_t TDBEIE0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0               */
+            __IOM uint32_t RDBFIE0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0                 */
+            __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable                       */
+            __IOM uint32_t CMDQEIE  : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable                        */
+            __IOM uint32_t RSPQFIE  : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable                        */
+            __IOM uint32_t TABTIE   : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable                             */
+            uint32_t                : 3;
+            __IOM uint32_t TEIE     : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable                             */
+            uint32_t                : 10;
+            __IOM uint32_t RSQFIE   : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable                */
+            uint32_t                : 11;
+        } NTIE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t NTSTFC;          /*!< (@ 0x000001EC) Normal Transfer Status Force Register                      */
+
+        struct
+        {
+            __OM uint32_t TDBEFC0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0                          */
+            __OM uint32_t RDBFFC0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0                            */
+            __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force                                  */
+            __OM uint32_t CMDQEFC  : 1; /*!< [3..3] Normal Command Queue Empty Force                                   */
+            __OM uint32_t RSPQFFC  : 1; /*!< [4..4] Normal Response Queue Full Force                                   */
+            __OM uint32_t TABTFC   : 1; /*!< [5..5] Normal Transfer Abort Force                                        */
+            uint32_t               : 3;
+            __OM uint32_t TEFC     : 1; /*!< [9..9] Normal Transfer Error Force                                        */
+            uint32_t               : 10;
+            __OM uint32_t RSQFFC   : 1; /*!< [20..20] Normal Receive Status Queue Full Force                           */
+            uint32_t               : 11;
+        } NTSTFC_b;
+    };
+    __IM uint32_t RESERVED17[8];
+
+    union
+    {
+        __IM uint32_t BCST;            /*!< (@ 0x00000210) Bus Condition Status Register                              */
+
+        struct
+        {
+            __IM uint32_t BFREF : 1;   /*!< [0..0] Bus Free Detection Flag                                            */
+            __IM uint32_t BAVLF : 1;   /*!< [1..1] Bus Available Detection Flag                                       */
+            __IM uint32_t BIDLF : 1;   /*!< [2..2] Bus Idle Detection Flag                                            */
+            uint32_t            : 29;
+        } BCST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SVST;           /*!< (@ 0x00000214) Slave Status Register                                      */
+
+        struct
+        {
+            __IOM uint32_t GCAF  : 1;  /*!< [0..0] General Call Address Detection Flag                                */
+            uint32_t             : 4;
+            __IOM uint32_t HSMCF : 1;  /*!< [5..5] Hs-mode Master Code Detection Flag                                 */
+            __IOM uint32_t DVIDF : 1;  /*!< [6..6] Device-ID Address Detection Flag                                   */
+            uint32_t             : 8;
+            __IOM uint32_t HOAF  : 1;  /*!< [15..15] Host Address Detection Flag                                      */
+            __IOM uint32_t SVAFn : 1;  /*!< [16..16] Slave Address Detection Flag n (n = 0)                           */
+            uint32_t             : 15;
+        } SVST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t WUST;            /*!< (@ 0x00000218) Wake Up Unit Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag.               */
+            uint32_t               : 31;
+        } WUST_b;
+    };
+    __IM uint32_t RESERVED18[2];
+
+    union
+    {
+        __IOM uint32_t DATBAS0;         /*!< (@ 0x00000224) Device Address Table Basic Register 0                      */
+
+        struct
+        {
+            __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
+            uint32_t               : 5;
+            __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
+            __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
+            __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
+            __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
+            __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
+            uint32_t               : 5;
+            __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
+            __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
+        } DATBAS0_b;
+    };
+    __IM uint32_t RESERVED19;
+
+    union
+    {
+        __IOM uint32_t DATBAS1;         /*!< (@ 0x0000022C) Device Address Table Basic Register 1                      */
+
+        struct
+        {
+            __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
+            uint32_t               : 5;
+            __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
+            __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
+            __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
+            __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
+            __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
+            uint32_t               : 5;
+            __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
+            __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
+        } DATBAS1_b;
+    };
+    __IM uint32_t RESERVED20;
+
+    union
+    {
+        __IOM uint32_t DATBAS2;         /*!< (@ 0x00000234) Device Address Table Basic Register 2                      */
+
+        struct
+        {
+            __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
+            uint32_t               : 5;
+            __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
+            __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
+            __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
+            __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
+            __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
+            uint32_t               : 5;
+            __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
+            __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
+        } DATBAS2_b;
+    };
+    __IM uint32_t RESERVED21;
+
+    union
+    {
+        __IOM uint32_t DATBAS3;         /*!< (@ 0x0000023C) Device Address Table Basic Register 3                      */
+
+        struct
+        {
+            __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
+            uint32_t               : 5;
+            __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
+            __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
+            __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
+            __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
+            __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
+            uint32_t               : 5;
+            __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
+            __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
+        } DATBAS3_b;
+    };
+    __IM uint32_t RESERVED22[24];
+
+    union
+    {
+        __IOM uint32_t EXDATBAS;       /*!< (@ 0x000002A0) Extended Device Address Table Basic Register               */
+
+        struct
+        {
+            __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address                                     */
+            uint32_t              : 9;
+            __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address                              */
+            uint32_t              : 5;
+            __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count                                 */
+            __IOM uint32_t EDTYP  : 1; /*!< [31..31] Extended Device Type                                             */
+        } EXDATBAS_b;
+    };
+    __IM uint32_t RESERVED23[3];
+
+    union
+    {
+        __IOM uint32_t SDATBAS0;         /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0                */
+
+        struct
+        {
+            __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
+            __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
+            uint32_t               : 1;
+            __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
+            uint32_t               : 3;
+            __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
+            uint32_t               : 9;
+        } SDATBAS0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SDATBAS1;         /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1                */
+
+        struct
+        {
+            __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
+            __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
+            uint32_t               : 1;
+            __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
+            uint32_t               : 3;
+            __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
+            uint32_t               : 9;
+        } SDATBAS1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SDATBAS2;         /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2                */
+
+        struct
+        {
+            __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
+            __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
+            uint32_t               : 1;
+            __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
+            uint32_t               : 3;
+            __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
+            uint32_t               : 9;
+        } SDATBAS2_b;
+    };
+    __IM uint32_t RESERVED24[5];
+
+    union
+    {
+        __IOM uint32_t MSDCT0;         /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0              */
+
+        struct
+        {
+            uint32_t              : 8;
+            __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
+            __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
+            __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
+            __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
+            uint32_t              : 2;
+            __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
+            uint32_t              : 16;
+        } MSDCT0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSDCT1;         /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1              */
+
+        struct
+        {
+            uint32_t              : 8;
+            __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
+            __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
+            __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
+            __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
+            uint32_t              : 2;
+            __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
+            uint32_t              : 16;
+        } MSDCT1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSDCT2;         /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2              */
+
+        struct
+        {
+            uint32_t              : 8;
+            __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
+            __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
+            __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
+            __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
+            uint32_t              : 2;
+            __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
+            uint32_t              : 16;
+        } MSDCT2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSDCT3;         /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3              */
+
+        struct
+        {
+            uint32_t              : 8;
+            __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
+            __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
+            __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
+            __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
+            uint32_t              : 2;
+            __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
+            uint32_t              : 16;
+        } MSDCT3_b;
+    };
+    __IM uint32_t RESERVED25[16];
+
+    union
+    {
+        __IOM uint32_t SVDCT;          /*!< (@ 0x00000320) Slave Device Characteristic Table Register                 */
+
+        struct
+        {
+            __IOM uint32_t TDCR   : 8; /*!< [7..0] Transfar Device Characteristic Register                            */
+            __IOM uint32_t TBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
+            __IOM uint32_t TBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
+            __IOM uint32_t TBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
+            __IOM uint32_t TBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
+            uint32_t              : 2;
+            __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role                                                      */
+            uint32_t              : 16;
+        } SVDCT_b;
+    };
+    __IOM uint32_t SDCTPIDL;           /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional
+                                        *                  ID Low Register                                            */
+    __IOM uint32_t SDCTPIDH;           /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional
+                                        *                  ID High Register                                           */
+    __IM uint32_t RESERVED26;
+
+    union
+    {
+        __IM uint32_t SVDVAD0;         /*!< (@ 0x00000330) Slave Device Address Register 0                            */
+
+        struct
+        {
+            uint32_t             : 16;
+            __IM uint32_t SVAD   : 10; /*!< [25..16] Slave Address                                                    */
+            uint32_t             : 1;
+            __IM uint32_t SADLG  : 1;  /*!< [27..27] Slave Address Length                                             */
+            uint32_t             : 2;
+            __IM uint32_t SSTADV : 1;  /*!< [30..30] Slave Static Address Valid                                       */
+            __IM uint32_t SDYADV : 1;  /*!< [31..31] Slave Dynamic Address Valid                                      */
+        } SVDVAD0_b;
+    };
+    __IM uint32_t RESERVED27[7];
+
+    union
+    {
+        __IOM uint32_t CSECMD;         /*!< (@ 0x00000350) CCC Slave Events Command Register                          */
+
+        struct
+        {
+            __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable                                    */
+            __IOM uint32_t MSRQE  : 1; /*!< [1..1] Mastership Requests Enable                                         */
+            uint32_t              : 1;
+            __IOM uint32_t HJEVE  : 1; /*!< [3..3] Hot-Join Event Enable                                              */
+            uint32_t              : 28;
+        } CSECMD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CEACTST;        /*!< (@ 0x00000354) CCC Enter Activity State Register                          */
+
+        struct
+        {
+            __IOM uint32_t ACTST : 4;  /*!< [3..0] Activity State                                                     */
+            uint32_t             : 28;
+        } CEACTST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CMWLG;          /*!< (@ 0x00000358) CCC Max Write Length Register                              */
+
+        struct
+        {
+            __IOM uint32_t MWLG : 16;  /*!< [15..0] Max Write Length                                                  */
+            uint32_t            : 16;
+        } CMWLG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CMRLG;           /*!< (@ 0x0000035C) CCC Max Read Length Register                               */
+
+        struct
+        {
+            __IOM uint32_t MRLG   : 16; /*!< [15..0] Max Read Length                                                   */
+            __IOM uint32_t IBIPSZ : 8;  /*!< [23..16] IBI Payload Size                                                 */
+            uint32_t              : 8;
+        } CMRLG_b;
+    };
+
+    union
+    {
+        __IM uint32_t CETSTMD;         /*!< (@ 0x00000360) CCC Enter Test Mode Register                               */
+
+        struct
+        {
+            __IM uint32_t TSTMD : 8;   /*!< [7..0] Test Mode                                                          */
+            uint32_t            : 24;
+        } CETSTMD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CGDVST;         /*!< (@ 0x00000364) CCC Get Device Status Register                             */
+
+        struct
+        {
+            __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t PRTE   : 1; /*!< [5..5] Protocol Error                                                     */
+            __IOM uint32_t ACTMD  : 2; /*!< [7..6] Slave Device's current Activity Mode                               */
+            __IOM uint32_t VDRSV  : 8; /*!< [15..8] Vendor Reserved                                                   */
+            uint32_t              : 16;
+        } CGDVST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CMDSPW;         /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register                      */
+
+        struct
+        {
+            __IOM uint32_t MSWDR : 3;  /*!< [2..0] Maximum Sustained Write Data Rate                                  */
+            uint32_t             : 29;
+        } CMDSPW_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CMDSPR;         /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register                       */
+
+        struct
+        {
+            __IOM uint32_t MSRDR  : 3; /*!< [2..0] Maximum Sustained Read Data Rate                                   */
+            __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO)                               */
+            uint32_t              : 26;
+        } CMDSPR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CMDSPT;          /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register                 */
+
+        struct
+        {
+            __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time                                      */
+            uint32_t              : 7;
+            __IOM uint32_t MRTE   : 1;  /*!< [31..31] Maximum Read Turnaround Time Enable                              */
+        } CMDSPT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CETSM;          /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode)
+                                        *                  Register                                                   */
+
+        struct
+        {
+            uint32_t            : 8;
+            __IOM uint32_t FREQ : 8;   /*!< [15..8] Frequency Byte                                                    */
+            __IOM uint32_t INAC : 8;   /*!< [23..16] Inaccuracy Byte                                                  */
+            uint32_t            : 8;
+        } CETSM_b;
+    };
+    __IM uint32_t RESERVED28[2];
+
+    union
+    {
+        __IOM uint32_t BITCNT;         /*!< (@ 0x00000380) Bit Count Register                                         */
+
+        struct
+        {
+            __IOM uint32_t BCNT  : 5;  /*!< [4..0] Bit Counter                                                        */
+            uint32_t             : 2;
+            __OM uint32_t BCNTWP : 1;  /*!< [7..7] BCNT Write Protect                                                 */
+            uint32_t             : 24;
+        } BITCNT_b;
+    };
+    __IM uint32_t RESERVED29[4];
+
+    union
+    {
+        __IM uint32_t NQSTLV;          /*!< (@ 0x00000394) Normal Queue Status Level Register                         */
+
+        struct
+        {
+            __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level                                    */
+            __IM uint32_t RSPQLV  : 8; /*!< [15..8] Normal Response Queue Level                                       */
+            __IM uint32_t IBIQLV  : 8; /*!< [23..16] Normal IBI Queue Level                                           */
+            __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count                                          */
+            uint32_t              : 3;
+        } NQSTLV_b;
+    };
+
+    union
+    {
+        __IM uint32_t NDBSTLV0;        /*!< (@ 0x00000398) Normal Data Buffer Status Level Register                   */
+
+        struct
+        {
+            __IM uint32_t TDBFLV : 8;  /*!< [7..0] Normal Transmit Data Buffer Free Level                             */
+            __IM uint32_t RDBLV  : 8;  /*!< [15..8] Normal Receive Data Buffer Level                                  */
+            uint32_t             : 16;
+        } NDBSTLV0_b;
+    };
+    __IM uint32_t RESERVED30[9];
+
+    union
+    {
+        __IM uint32_t NRSQSTLV;        /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register          */
+
+        struct
+        {
+            __IM uint32_t RSQLV : 8;   /*!< [7..0] Normal Receive Status Queue Level                                  */
+            uint32_t            : 24;
+        } NRSQSTLV_b;
+    };
+    __IM uint32_t RESERVED31[2];
+
+    union
+    {
+        __IM uint32_t PRSTDBG;         /*!< (@ 0x000003CC) Present State Debug Register                               */
+
+        struct
+        {
+            __IM uint32_t SCILV : 1;   /*!< [0..0] SCL Line Signal Level                                              */
+            __IM uint32_t SDILV : 1;   /*!< [1..1] SDA Line Signal Level                                              */
+            __IM uint32_t SCOLV : 1;   /*!< [2..2] SCL Output Level                                                   */
+            __IM uint32_t SDOLV : 1;   /*!< [3..3] SDA Output Level                                                   */
+            uint32_t            : 28;
+        } PRSTDBG_b;
+    };
+
+    union
+    {
+        __IM uint32_t MSERRCNT;        /*!< (@ 0x000003D0) Master Error Counters Register                             */
+
+        struct
+        {
+            __IM uint32_t M2ECNT : 8;  /*!< [7..0] M2 Error Counter                                                   */
+            uint32_t             : 24;
+        } MSERRCNT_b;
+    };
+} R_I3C0_Type;                         /*!< Size = 980 (0x3d4)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                        R_MPU_SPMON                                        ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief CPU Stack Pointer Monitor (R_MPU_SPMON)
+ */
+
+typedef struct                         /*!< (@ 0x40000D00) R_MPU_SPMON Structure                                      */
+{
+    __IOM R_MPU_SPMON_SP_Type SP[2];   /*!< (@ 0x00000000) Stack Pointer Monitor                                      */
+} R_MPU_SPMON_Type;                    /*!< Size = 32 (0x20)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MSTP                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief System-Module Stop (R_MSTP)
+ */
+
+typedef struct                          /*!< (@ 0x40084000) R_MSTP Structure                                           */
+{
+    union
+    {
+        __IOM uint32_t MSTPCRA;         /*!< (@ 0x00000000) Module Stop Control Register A                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPA0  : 1; /*!< [0..0] RAM0 Module Stop                                                   */
+            uint32_t               : 6;
+            __IOM uint32_t MSTPA7  : 1; /*!< [7..7] Standby RAM Module Stop                                            */
+            uint32_t               : 14;
+            __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop              */
+            uint32_t               : 9;
+        } MSTPCRA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRB;        /*!< (@ 0x00000004) Module Stop Control Register B                             */
+
+        struct
+        {
+            uint32_t               : 1;
+            __IOM uint32_t MSTPB1  : 1; /*!< [1..1] RCAN1 Module Stop                                                  */
+            __IOM uint32_t MSTPB2  : 1; /*!< [2..2] RCAN0 Module Stop                                                  */
+            __IOM uint32_t MSTPB3  : 1; /*!< [3..3] RCEC Module Stop                                                   */
+            uint32_t               : 1;
+            __IOM uint32_t MSTPB5  : 1; /*!< [5..5] IrDA Module Stop                                                   */
+            __IOM uint32_t MSTPB6  : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop                     */
+            __IOM uint32_t MSTPB7  : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop                                    */
+            __IOM uint32_t MSTPB8  : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop                                    */
+            __IOM uint32_t MSTPB9  : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop                                */
+            uint32_t               : 1;
+            __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop                */
+            __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop                */
+            __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop                                   */
+            __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop                                   */
+            __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop                                   */
+            __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Octa Memory Controller Module Stop                               */
+            uint32_t               : 1;
+            __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop                          */
+            __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop                        */
+            uint32_t               : 2;
+            __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop                     */
+            __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop                     */
+            __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop                     */
+            __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop                     */
+            __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop                     */
+            __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop                     */
+            __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop                     */
+            __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop                     */
+            __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop                     */
+            __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop                     */
+        } MSTPCRB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRC;         /*!< (@ 0x00000008) Module Stop Control Register C                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPC0  : 1; /*!< [0..0] CAC Module Stop                                                    */
+            __IOM uint32_t MSTPC1  : 1; /*!< [1..1] CRC Calculator Module Stop                                         */
+            __IOM uint32_t MSTPC2  : 1; /*!< [2..2] Parallel Data Capture Module Stop                                  */
+            __IOM uint32_t MSTPC3  : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop                          */
+            __IOM uint32_t MSTPC4  : 1; /*!< [4..4] Segment LCD Controller Module Stop                                 */
+            __IOM uint32_t MSTPC5  : 1; /*!< [5..5] JPEG codec engine Module Stop                                      */
+            __IOM uint32_t MSTPC6  : 1; /*!< [6..6] 2DG engine Module Stop                                             */
+            __IOM uint32_t MSTPC7  : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop                         */
+            __IOM uint32_t MSTPC8  : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop                         */
+            __IOM uint32_t MSTPC9  : 1; /*!< [9..9] Sampling Rate Converter Module Stop                                */
+            uint32_t               : 1;
+            __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop           */
+            __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop           */
+            __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop                               */
+            __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop                                */
+            __IOM uint32_t MSTPC15 : 1; /*!< [15..15] 32-bit Multiply-Accumulator Module Stop                          */
+            uint32_t               : 4;
+            __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop                          */
+            __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop                               */
+            uint32_t               : 5;
+            __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop                                                */
+            __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop                              */
+            uint32_t               : 2;
+            __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop                                                  */
+        } MSTPCRC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRD;         /*!< (@ 0x0000000C) Module Stop Control Register D                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPD0 : 1;  /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module
+                                         *   Stop                                                                      */
+            __IOM uint32_t MSTPD1 : 1;  /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module
+                                         *   Stop                                                                      */
+            __IOM uint32_t MSTPD2 : 1;  /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state
+                                         *   when the count source is either of PCLKB, PCLKB/2 or PCLKB/8.
+                                         *   In case the count source is sub-clock or LOCO, this bit
+                                         *   should be set to 1 except when accessing the registers
+                                         *   of AGT1.                                                                  */
+            __IOM uint32_t MSTPD3 : 1;  /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state
+                                         *   when the count source is either of PCLKB, PCLKB/2 or PCLKB/8.
+                                         *   In case the count source is sub-clock or LOCO, this bit
+                                         *   should be set to 1 except when accessing the registers
+                                         *   of AGT0.                                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t MSTPD5 : 1;  /*!< [5..5] GPT Lower Module Stop                                              */
+            __IOM uint32_t MSTPD6 : 1;  /*!< [6..6] GPT Higher Module Stop                                             */
+            __IOM uint32_t MSTPD7 : 1;  /*!< [7..7] 16-bit Low Power Asynchronous General Purpose Timer 7
+                                         *   Module Stop                                                               */
+            __IOM uint32_t MSTPD8 : 1;  /*!< [8..8] 16-bit Low Power Asynchronous General Purpose Timer 6
+                                         *   Module Stop                                                               */
+            __IOM uint32_t MSTPD9 : 1;  /*!< [9..9] 16-bit Low Power Asynchronous General Purpose Timer 5
+                                         *   Module Stop                                                               */
+            __IOM uint32_t MSTPD10 : 1; /*!< [10..10] 16-bit Low Power Asynchronous General Purpose Timer
+                                         *   4 Module Stop                                                             */
+            __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop                         */
+            __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop                         */
+            __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop                         */
+            __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop                                                 */
+            __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop                               */
+            __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop                                 */
+            __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop                      */
+            __IOM uint32_t MSTPD18 : 1; /*!< [18..18] 16-bit Low Power Asynchronous General Purpose Timer
+                                         *   1 Module Stop                                                             */
+            __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop                                  */
+            __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop                                 */
+            uint32_t               : 1;
+            __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop                                   */
+            __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop                                              */
+            __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop                                              */
+            __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop                                              */
+            __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop                                              */
+            __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop                                              */
+            __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop                                              */
+            __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop                                        */
+            uint32_t               : 1;
+            __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop                                */
+        } MSTPCRD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRE;        /*!< (@ 0x00000010) Module Stop Control Register E                             */
+
+        struct
+        {
+            uint32_t               : 4;
+            __IOM uint32_t MSTPE4  : 1; /*!< [4..4] KINT Module Stop                                                   */
+            uint32_t               : 9;
+            __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module
+                                         *   Stop                                                                      */
+            __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module
+                                         *   Stop                                                                      */
+            uint32_t               : 6;
+            __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop                                                 */
+            __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop                                                 */
+            __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop                                                 */
+            __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop                                                 */
+            __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop                                                 */
+            __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop                                                 */
+            __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop                                                 */
+            __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop                                                 */
+            __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop                                                 */
+            __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop                                                 */
+        } MSTPCRE_b;
+    };
+} R_MSTP_Type;                          /*!< Size = 20 (0x14)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_PORT0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I/O Ports (R_PORT0)
+ */
+
+typedef struct                         /*!< (@ 0x40080000) R_PORT0 Structure                                          */
+{
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCNTR1;        /*!< (@ 0x00000000) Port Control Register 1                                    */
+
+            struct
+            {
+                __IOM uint32_t PDR  : 16; /*!< [15..0] Pmn Direction                                                     */
+                __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data                                                  */
+            } PCNTR1_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t PODR;           /*!< (@ 0x00000000) Output data register                                       */
+
+                struct
+                {
+                    __IOM uint16_t PODR0  : 1; /*!< [0..0] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR1  : 1; /*!< [1..1] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR2  : 1; /*!< [2..2] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR3  : 1; /*!< [3..3] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR4  : 1; /*!< [4..4] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR5  : 1; /*!< [5..5] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR6  : 1; /*!< [6..6] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR7  : 1; /*!< [7..7] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR8  : 1; /*!< [8..8] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR9  : 1; /*!< [9..9] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data                                                  */
+                    __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data                                                  */
+                    __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data                                                  */
+                    __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data                                                  */
+                    __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data                                                  */
+                    __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data                                                  */
+                } PODR_b;
+            };
+
+            union
+            {
+                __IOM uint16_t PDR;           /*!< (@ 0x00000002) Data direction register                                    */
+
+                struct
+                {
+                    __IOM uint16_t PDR0  : 1; /*!< [0..0] Pmn Direction                                                      */
+                    __IOM uint16_t PDR1  : 1; /*!< [1..1] Pmn Direction                                                      */
+                    __IOM uint16_t PDR2  : 1; /*!< [2..2] Pmn Direction                                                      */
+                    __IOM uint16_t PDR3  : 1; /*!< [3..3] Pmn Direction                                                      */
+                    __IOM uint16_t PDR4  : 1; /*!< [4..4] Pmn Direction                                                      */
+                    __IOM uint16_t PDR5  : 1; /*!< [5..5] Pmn Direction                                                      */
+                    __IOM uint16_t PDR6  : 1; /*!< [6..6] Pmn Direction                                                      */
+                    __IOM uint16_t PDR7  : 1; /*!< [7..7] Pmn Direction                                                      */
+                    __IOM uint16_t PDR8  : 1; /*!< [8..8] Pmn Direction                                                      */
+                    __IOM uint16_t PDR9  : 1; /*!< [9..9] Pmn Direction                                                      */
+                    __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction                                                    */
+                    __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction                                                    */
+                    __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction                                                    */
+                    __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction                                                    */
+                    __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction                                                    */
+                    __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction                                                    */
+                } PDR_b;
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCNTR2;        /*!< (@ 0x00000004) Port Control Register 2                                    */
+
+            struct
+            {
+                __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data                                                    */
+                __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data                                             */
+            } PCNTR2_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IM uint16_t EIDR;           /*!< (@ 0x00000004) Event input data register                                  */
+
+                struct
+                {
+                    __IM uint16_t EIDR0  : 1; /*!< [0..0] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR1  : 1; /*!< [1..1] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR2  : 1; /*!< [2..2] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR3  : 1; /*!< [3..3] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR4  : 1; /*!< [4..4] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR5  : 1; /*!< [5..5] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR6  : 1; /*!< [6..6] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR7  : 1; /*!< [7..7] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR8  : 1; /*!< [8..8] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR9  : 1; /*!< [9..9] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data                                             */
+                    __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data                                             */
+                    __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data                                             */
+                    __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data                                             */
+                    __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data                                             */
+                    __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data                                             */
+                } EIDR_b;
+            };
+
+            union
+            {
+                __IM uint16_t PIDR;           /*!< (@ 0x00000006) Input data register                                        */
+
+                struct
+                {
+                    __IM uint16_t PIDR0  : 1; /*!< [0..0] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR1  : 1; /*!< [1..1] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR2  : 1; /*!< [2..2] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR3  : 1; /*!< [3..3] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR4  : 1; /*!< [4..4] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR5  : 1; /*!< [5..5] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR6  : 1; /*!< [6..6] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR7  : 1; /*!< [7..7] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR8  : 1; /*!< [8..8] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR9  : 1; /*!< [9..9] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data                                                   */
+                    __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data                                                   */
+                    __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data                                                   */
+                    __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data                                                   */
+                    __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data                                                   */
+                    __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data                                                   */
+                } PIDR_b;
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __OM uint32_t PCNTR3;        /*!< (@ 0x00000008) Port Control Register 3                                    */
+
+            struct
+            {
+                __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set                                                    */
+                __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset                                                 */
+            } PCNTR3_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __OM uint16_t PORR;           /*!< (@ 0x00000008) Output set register                                        */
+
+                struct
+                {
+                    __OM uint16_t PORR0  : 1; /*!< [0..0] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR1  : 1; /*!< [1..1] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR2  : 1; /*!< [2..2] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR3  : 1; /*!< [3..3] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR4  : 1; /*!< [4..4] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR5  : 1; /*!< [5..5] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR6  : 1; /*!< [6..6] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR7  : 1; /*!< [7..7] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR8  : 1; /*!< [8..8] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR9  : 1; /*!< [9..9] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset                                                 */
+                    __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset                                                 */
+                    __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset                                                 */
+                    __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset                                                 */
+                    __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset                                                 */
+                    __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset                                                 */
+                } PORR_b;
+            };
+
+            union
+            {
+                __OM uint16_t POSR;           /*!< (@ 0x0000000A) Output reset register                                      */
+
+                struct
+                {
+                    __OM uint16_t POSR0  : 1; /*!< [0..0] Pmn Output Set                                                     */
+                    __OM uint16_t POSR1  : 1; /*!< [1..1] Pmn Output Set                                                     */
+                    __OM uint16_t POSR2  : 1; /*!< [2..2] Pmn Output Set                                                     */
+                    __OM uint16_t POSR3  : 1; /*!< [3..3] Pmn Output Set                                                     */
+                    __OM uint16_t POSR4  : 1; /*!< [4..4] Pmn Output Set                                                     */
+                    __OM uint16_t POSR5  : 1; /*!< [5..5] Pmn Output Set                                                     */
+                    __OM uint16_t POSR6  : 1; /*!< [6..6] Pmn Output Set                                                     */
+                    __OM uint16_t POSR7  : 1; /*!< [7..7] Pmn Output Set                                                     */
+                    __OM uint16_t POSR8  : 1; /*!< [8..8] Pmn Output Set                                                     */
+                    __OM uint16_t POSR9  : 1; /*!< [9..9] Pmn Output Set                                                     */
+                    __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set                                                   */
+                    __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set                                                   */
+                    __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set                                                   */
+                    __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set                                                   */
+                    __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set                                                   */
+                    __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set                                                   */
+                } POSR_b;
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCNTR4;        /*!< (@ 0x0000000C) Port Control Register 4                                    */
+
+            struct
+            {
+                __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set                                              */
+                __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset                                           */
+            } PCNTR4_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t EORR;           /*!< (@ 0x0000000C) Event output set register                                  */
+
+                struct
+                {
+                    __IOM uint16_t EORR0  : 1; /*!< [0..0] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR1  : 1; /*!< [1..1] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR2  : 1; /*!< [2..2] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR3  : 1; /*!< [3..3] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR4  : 1; /*!< [4..4] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR5  : 1; /*!< [5..5] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR6  : 1; /*!< [6..6] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR7  : 1; /*!< [7..7] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR8  : 1; /*!< [8..8] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR9  : 1; /*!< [9..9] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset                                           */
+                    __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset                                           */
+                    __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset                                           */
+                    __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset                                           */
+                    __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset                                           */
+                    __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset                                           */
+                } EORR_b;
+            };
+
+            union
+            {
+                __IOM uint16_t EOSR;           /*!< (@ 0x0000000E) Event output reset register                                */
+
+                struct
+                {
+                    __IOM uint16_t EOSR0  : 1; /*!< [0..0] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR1  : 1; /*!< [1..1] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR2  : 1; /*!< [2..2] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR3  : 1; /*!< [3..3] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR4  : 1; /*!< [4..4] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR5  : 1; /*!< [5..5] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR6  : 1; /*!< [6..6] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR7  : 1; /*!< [7..7] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR8  : 1; /*!< [8..8] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR9  : 1; /*!< [9..9] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set                                             */
+                    __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set                                             */
+                    __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set                                             */
+                    __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set                                             */
+                    __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set                                             */
+                    __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set                                             */
+                } EOSR_b;
+            };
+        };
+    };
+} R_PORT0_Type;                        /*!< Size = 16 (0x10)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_PFS                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I/O Ports-PFS (R_PFS)
+ */
+
+typedef struct                           /*!< (@ 0x40080800) R_PFS Structure                                            */
+{
+    union
+    {
+        __IOM R_PFS_PORT_Type  PORT[15]; /*!< (@ 0x00000000) Port [0..14]                                               */
+        __IOM R_PFS_VLSEL_Type VLSEL;    /*!< (@ 0x00000000) VLSEL                                                      */
+    };
+} R_PFS_Type;                            /*!< Size = 960 (0x3c0)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_PMISC                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I/O Ports-MISC (R_PMISC)
+ */
+
+typedef struct                         /*!< (@ 0x40080D00) R_PMISC Structure                                          */
+{
+    union
+    {
+        __IOM uint8_t PFENET;          /*!< (@ 0x00000000) Ethernet Control Register                                  */
+
+        struct
+        {
+            uint8_t                : 4;
+            __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0                                          */
+            __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1                                          */
+            uint8_t                : 2;
+        } PFENET_b;
+    };
+    __IM uint8_t RESERVED[2];
+
+    union
+    {
+        __IOM uint8_t PWPR;            /*!< (@ 0x00000003) Write-Protect Register                                     */
+
+        struct
+        {
+            uint8_t             : 6;
+            __IOM uint8_t PFSWE : 1;   /*!< [6..6] PmnPFS Register Write                                              */
+            __IOM uint8_t B0WI  : 1;   /*!< [7..7] PFSWE Bit Write Disable                                            */
+        } PWPR_b;
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        __IOM uint8_t PWPRS;           /*!< (@ 0x00000005) Write-Protect Register for Secure                          */
+
+        struct
+        {
+            uint8_t             : 6;
+            __IOM uint8_t PFSWE : 1;    /*!< [6..6] PmnPFS Register Write                                              */
+            __IOM uint8_t B0WI  : 1;    /*!< [7..7] PFSWE Bit Write Disable                                            */
+        } PWPRS_b;
+    };
+    __IM uint16_t            RESERVED2[5];
+    __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register                         */
+} R_PMISC_Type;                         /*!< Size = 40 (0x28)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_RTC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Realtime Clock (R_RTC)
+ */
+
+typedef struct                         /*!< (@ 0x40083000) R_RTC Structure                                            */
+{
+    union
+    {
+        __IM uint8_t R64CNT;           /*!< (@ 0x00000000) 64-Hz Counter                                              */
+
+        struct
+        {
+            __IM uint8_t F64HZ : 1;    /*!< [0..0] 64Hz                                                               */
+            __IM uint8_t F32HZ : 1;    /*!< [1..1] 32Hz                                                               */
+            __IM uint8_t F16HZ : 1;    /*!< [2..2] 16Hz                                                               */
+            __IM uint8_t F8HZ  : 1;    /*!< [3..3] 8Hz                                                                */
+            __IM uint8_t F4HZ  : 1;    /*!< [4..4] 4Hz                                                                */
+            __IM uint8_t F2HZ  : 1;    /*!< [5..5] 2Hz                                                                */
+            __IM uint8_t F1HZ  : 1;    /*!< [6..6] 1Hz                                                                */
+            uint8_t            : 1;
+        } R64CNT_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RSECCNT;       /*!< (@ 0x00000002) Second Counter                                             */
+
+            struct
+            {
+                __IOM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When
+                                          *   a carry is generated, 1 is added to the tens place.                       */
+                __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting.         */
+                uint8_t             : 1;
+            } RSECCNT_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT0;         /*!< (@ 0x00000002) Binary Counter 0                                           */
+
+            struct
+            {
+                __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary
+                                          *   counter b7 to b0.                                                         */
+            } BCNT0_b;
+        };
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RMINCNT;       /*!< (@ 0x00000004) Minute Counter                                             */
+
+            struct
+            {
+                __IOM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When
+                                          *   a carry is generated, 1 is added to the tens place.                       */
+                __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting.         */
+                uint8_t             : 1;
+            } RMINCNT_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT1;         /*!< (@ 0x00000004) Binary Counter 1                                           */
+
+            struct
+            {
+                __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary
+                                          *   counter b15 to b8.                                                        */
+            } BCNT1_b;
+        };
+    };
+    __IM uint8_t RESERVED2;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RHRCNT;       /*!< (@ 0x00000006) Hour Counter                                               */
+
+            struct
+            {
+                __IOM uint8_t HR1 : 4;  /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a
+                                         *   carry is generated, 1 is added to the tens place.                         */
+                __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from
+                                         *   the ones place.                                                           */
+                __IOM uint8_t PM : 1;   /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
+                uint8_t          : 1;
+            } RHRCNT_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT2;         /*!< (@ 0x00000006) Binary Counter 2                                           */
+
+            struct
+            {
+                __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary
+                                          *   counter b23 to b16.                                                       */
+            } BCNT2_b;
+        };
+    };
+    __IM uint8_t RESERVED3;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RWKCNT;       /*!< (@ 0x00000008) Day-of-Week Counter                                        */
+
+            struct
+            {
+                __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
+                uint8_t            : 5;
+            } RWKCNT_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT3;         /*!< (@ 0x00000008) Binary Counter 3                                           */
+
+            struct
+            {
+                __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary
+                                          *   counter b31 to b24.                                                       */
+            } BCNT3_b;
+        };
+    };
+    __IM uint8_t RESERVED4;
+
+    union
+    {
+        __IOM uint8_t RDAYCNT;         /*!< (@ 0x0000000A) Day Counter                                                */
+
+        struct
+        {
+            __IOM uint8_t DATE1 : 4;   /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry
+                                        *   is generated, 1 is added to the tens place.                               */
+            __IOM uint8_t DATE10 : 2;  /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the
+                                        *   ones place.                                                               */
+            uint8_t : 2;
+        } RDAYCNT_b;
+    };
+    __IM uint8_t RESERVED5;
+
+    union
+    {
+        __IOM uint8_t RMONCNT;         /*!< (@ 0x0000000C) Month Counter                                              */
+
+        struct
+        {
+            __IOM uint8_t MON1 : 4;    /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When
+                                        *   a carry is generated, 1 is added to the tens place.                       */
+            __IOM uint8_t MON10 : 1;   /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from
+                                        *   the ones place.                                                           */
+            uint8_t : 3;
+        } RMONCNT_b;
+    };
+    __IM uint8_t RESERVED6;
+
+    union
+    {
+        __IOM uint16_t RYRCNT;         /*!< (@ 0x0000000E) Year Counter                                               */
+
+        struct
+        {
+            __IOM uint16_t YR1 : 4;    /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a
+                                        *   carry is generated, 1 is added to the tens place.                         */
+            __IOM uint16_t YR10 : 4;   /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from
+                                        *   ones place. When a carry is generated in the tens place,
+                                        *   1 is added to the hundreds place.                                         */
+            uint16_t : 8;
+        } RYRCNT_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RSECAR;        /*!< (@ 0x00000010) Second Alarm Register                                      */
+
+            struct
+            {
+                __OM uint8_t  SEC1  : 4; /*!< [3..0] 1-Second Value for the ones place of seconds                       */
+                __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds                     */
+                __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
+            } RSECAR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT0AR;         /*!< (@ 0x00000010) Binary Counter 0 Alarm Register                            */
+
+            struct
+            {
+                __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register
+                                            *   corresponding to 32-bit binary counter b7 to b0.                          */
+            } BCNT0AR_b;
+        };
+    };
+    __IM uint8_t RESERVED7;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RMINAR;        /*!< (@ 0x00000012) Minute Alarm Register                                      */
+
+            struct
+            {
+                __IOM uint8_t MIN1  : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes                 */
+                __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes                */
+                __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
+            } RMINAR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT1AR;         /*!< (@ 0x00000012) Binary Counter 1 Alarm Register                            */
+
+            struct
+            {
+                __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register
+                                            *   corresponding to 32-bit binary counter b15 to b8.                         */
+            } BCNT1AR_b;
+        };
+    };
+    __IM uint8_t RESERVED8;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RHRAR;        /*!< (@ 0x00000014) Hour Alarm Register                                        */
+
+            struct
+            {
+                __IOM uint8_t HR1  : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours                     */
+                __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours                    */
+                __IOM uint8_t PM   : 1; /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
+                __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
+            } RHRAR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT2AR;         /*!< (@ 0x00000014) Binary Counter 2 Alarm Register                            */
+
+            struct
+            {
+                __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary
+                                            *   counter b23 to b16.                                                       */
+            } BCNT2AR_b;
+        };
+    };
+    __IM uint8_t RESERVED9;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RWKAR;        /*!< (@ 0x00000016) Day-of-Week Alarm Register                                 */
+
+            struct
+            {
+                __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
+                uint8_t            : 4;
+                __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
+            } RWKAR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT3AR;         /*!< (@ 0x00000016) Binary Counter 3 Alarm Register                            */
+
+            struct
+            {
+                __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary
+                                            *   counter b31 to b24.                                                       */
+            } BCNT3AR_b;
+        };
+    };
+    __IM uint8_t RESERVED10;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RDAYAR;         /*!< (@ 0x00000018) Date Alarm Register                                        */
+
+            struct
+            {
+                __IOM uint8_t DATE1  : 4; /*!< [3..0] 1 Day Value for the ones place of days                             */
+                __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days                           */
+                uint8_t              : 1;
+                __IOM uint8_t ENB    : 1; /*!< [7..7] Compare enable                                                     */
+            } RDAYAR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT0AER;    /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register                     */
+
+            struct
+            {
+                __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register
+                                        *   for setting the alarm enable corresponding to 32-bit binary
+                                        *   counter b7 to b0.                                                         */
+            } BCNT0AER_b;
+        };
+    };
+    __IM uint8_t RESERVED11;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RMONAR;        /*!< (@ 0x0000001A) Month Alarm Register                                       */
+
+            struct
+            {
+                __IOM uint8_t MON1  : 4; /*!< [3..0] 1 Month Value for the ones place of months                         */
+                __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months                       */
+                uint8_t             : 2;
+                __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
+            } RMONAR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT1AER;    /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register                     */
+
+            struct
+            {
+                __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register
+                                        *   for setting the alarm enable corresponding to 32-bit binary
+                                        *   counter b15 to b8.                                                        */
+            } BCNT1AER_b;
+        };
+    };
+    __IM uint8_t RESERVED12;
+
+    union
+    {
+        union
+        {
+            __IOM uint16_t RYRAR;        /*!< (@ 0x0000001C) Year Alarm Register                                        */
+
+            struct
+            {
+                __IOM uint16_t YR1  : 4; /*!< [3..0] 1 Year Value for the ones place of years                           */
+                __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years                         */
+                uint16_t            : 8;
+            } RYRAR_b;
+        };
+
+        union
+        {
+            __IOM uint16_t BCNT2AER;    /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register                     */
+
+            struct
+            {
+                __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register
+                                         *   for setting the alarm enable corresponding to 32-bit binary
+                                         *   counter b23 to b16.                                                       */
+                uint16_t : 8;
+            } BCNT2AER_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RYRAREN;     /*!< (@ 0x0000001E) Year Alarm Enable Register                                 */
+
+            struct
+            {
+                uint8_t           : 7;
+                __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable                                                     */
+            } RYRAREN_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT3AER;    /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register                     */
+
+            struct
+            {
+                __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register
+                                        *   for setting the alarm enable corresponding to 32-bit binary
+                                        *   counter b31 to b24.                                                       */
+            } BCNT3AER_b;
+        };
+    };
+    __IM uint8_t  RESERVED13;
+    __IM uint16_t RESERVED14;
+
+    union
+    {
+        __IOM uint8_t RCR1;            /*!< (@ 0x00000022) RTC Control Register 1                                     */
+
+        struct
+        {
+            __IOM uint8_t AIE   : 1;   /*!< [0..0] Alarm Interrupt Enable                                             */
+            __IOM uint8_t CIE   : 1;   /*!< [1..1] Carry Interrupt Enable                                             */
+            __IOM uint8_t PIE   : 1;   /*!< [2..2] Periodic Interrupt Enable                                          */
+            __IOM uint8_t RTCOS : 1;   /*!< [3..3] RTCOUT Output Select                                               */
+            __IOM uint8_t PES   : 4;   /*!< [7..4] Periodic Interrupt Select                                          */
+        } RCR1_b;
+    };
+    __IM uint8_t RESERVED15;
+
+    union
+    {
+        __IOM uint8_t RCR2;            /*!< (@ 0x00000024) RTC Control Register 2                                     */
+
+        struct
+        {
+            __IOM uint8_t START : 1;   /*!< [0..0] Start                                                              */
+            __IOM uint8_t RESET : 1;   /*!< [1..1] RTC Software Reset                                                 */
+            __IOM uint8_t ADJ30 : 1;   /*!< [2..2] 30-Second Adjustment                                               */
+            __IOM uint8_t RTCOE : 1;   /*!< [3..3] RTCOUT Output Enable                                               */
+            __IOM uint8_t AADJE : 1;   /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected,
+                                        *   the setting of this bit is disabled.)                                     */
+            __IOM uint8_t AADJP : 1;   /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock
+                                        *   is selected, the setting of this bit is disabled.)                        */
+            __IOM uint8_t HR24  : 1;   /*!< [6..6] Hours Mode                                                         */
+            __IOM uint8_t CNTMD : 1;   /*!< [7..7] Count Mode Select                                                  */
+        } RCR2_b;
+    };
+    __IM uint8_t  RESERVED16;
+    __IM uint16_t RESERVED17;
+
+    union
+    {
+        __IOM uint8_t RCR4;            /*!< (@ 0x00000028) RTC Control Register 4                                     */
+
+        struct
+        {
+            __IOM uint8_t RCKSEL : 1;  /*!< [0..0] Count Source Select                                                */
+            uint8_t              : 6;
+            __IOM uint8_t ROPSEL : 1;  /*!< [7..7] RTC Operation Mode Select                                          */
+        } RCR4_b;
+    };
+    __IM uint8_t RESERVED18;
+
+    union
+    {
+        __IOM uint16_t RFRH;           /*!< (@ 0x0000002A) Frequency Register H                                       */
+
+        struct
+        {
+            __IOM uint16_t RFC16 : 1;  /*!< [0..0] Frequency Comparison Value (b16) To generate the operating
+                                        *   clock from the LOCOclock, this bit sets the comparison
+                                        *   value of the 128-Hz clock cycle.                                          */
+            uint16_t : 15;
+        } RFRH_b;
+    };
+
+    union
+    {
+        __IOM uint16_t RFRL;           /*!< (@ 0x0000002C) Frequency Register L                                       */
+
+        struct
+        {
+            __IOM uint16_t RFC : 16;   /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating
+                                        *   clock from the main clock, this bit sets the comparison
+                                        *   value of the 128-Hz clock cycle.                                          */
+        } RFRL_b;
+    };
+
+    union
+    {
+        __IOM uint8_t RADJ;            /*!< (@ 0x0000002E) Time Error Adjustment Register                             */
+
+        struct
+        {
+            __IOM uint8_t ADJ : 6;     /*!< [5..0] Adjustment Value These bits specify the adjustment value
+                                        *   from the prescaler.                                                       */
+            __IOM uint8_t PMADJ : 2;   /*!< [7..6] Plus-Minus                                                         */
+        } RADJ_b;
+    };
+    __IM uint8_t           RESERVED19;
+    __IM uint16_t          RESERVED20[8];
+    __IOM R_RTC_RTCCR_Type RTCCR[3];   /*!< (@ 0x00000040) Time Capture Control Register                              */
+    __IM uint16_t          RESERVED21[5];
+    __IOM R_RTC_CP_Type    CP[3];      /*!< (@ 0x00000050) Capture registers                                          */
+} R_RTC_Type;                          /*!< Size = 128 (0x80)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SCI0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Serial Communications Interface (R_SCI0)
+ */
+
+typedef struct                         /*!< (@ 0x40118000) R_SCI0 Structure                                           */
+{
+    union
+    {
+        union
+        {
+            __IOM uint8_t SMR;          /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0)                       */
+
+            struct
+            {
+                __IOM uint8_t CKS  : 2; /*!< [1..0] Clock Select                                                       */
+                __IOM uint8_t MP   : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode)              */
+                __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode)                   */
+                __IOM uint8_t PM   : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
+                __IOM uint8_t PE   : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
+                __IOM uint8_t CHR  : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode)                  */
+                __IOM uint8_t CM   : 1; /*!< [7..7] Communication Mode                                                 */
+            } SMR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t SMR_SMCI;    /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1)                       */
+
+            struct
+            {
+                __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select                                                       */
+                __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode)                  */
+                __IOM uint8_t PM  : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
+                __IOM uint8_t PE  : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
+                __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode                                                */
+                __IOM uint8_t GM  : 1; /*!< [7..7] GSM Mode                                                           */
+            } SMR_SMCI_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint8_t BRR;             /*!< (@ 0x00000001) Bit Rate Register                                          */
+
+        struct
+        {
+            __IOM uint8_t BRR : 8;     /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate.                */
+        } BRR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t SCR;          /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0)                    */
+
+            struct
+            {
+                __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
+                __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
+                __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous
+                                         *   mode when SMR.MP = 1)                                                     */
+                __IOM uint8_t RE  : 1;  /*!< [4..4] Receive Enable                                                     */
+                __IOM uint8_t TE  : 1;  /*!< [5..5] Transmit Enable                                                    */
+                __IOM uint8_t RIE : 1;  /*!< [6..6] Receive Interrupt Enable                                           */
+                __IOM uint8_t TIE : 1;  /*!< [7..7] Transmit Interrupt Enable                                          */
+            } SCR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t SCR_SMCI;     /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1)                     */
+
+            struct
+            {
+                __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
+                __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
+                __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable                                   */
+                __IOM uint8_t RE   : 1; /*!< [4..4] Receive Enable                                                     */
+                __IOM uint8_t TE   : 1; /*!< [5..5] Transmit Enable                                                    */
+                __IOM uint8_t RIE  : 1; /*!< [6..6] Receive Interrupt Enable                                           */
+                __IOM uint8_t TIE  : 1; /*!< [7..7] Transmit Interrupt Enable                                          */
+            } SCR_SMCI_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint8_t TDR;             /*!< (@ 0x00000003) Transmit Data Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TDR : 8;     /*!< [7..0] TDR is an 8-bit register that stores transmit data.                */
+        } TDR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t SSR;          /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)         */
+
+            struct
+            {
+                __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer                                       */
+                __IM uint8_t  MPB  : 1; /*!< [1..1] Multi-Processor                                                    */
+                __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
+                __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
+                __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
+                __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
+                __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
+                __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
+            } SSR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t SSR_FIFO;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1)         */
+
+            struct
+            {
+                __IOM uint8_t DR : 1;   /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including
+                                         *   multi-processor) and FIFO selected)                                       */
+                uint8_t            : 1;
+                __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
+                __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
+                __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
+                __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
+                __IOM uint8_t RDF  : 1; /*!< [6..6] Receive FIFO data full flag                                        */
+                __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag                                      */
+            } SSR_FIFO_b;
+        };
+
+        union
+        {
+            __IOM uint8_t SSR_SMCI;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1)                      */
+
+            struct
+            {
+                __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart
+                                         *   card interface mode.                                                      */
+                __IM uint8_t MPB : 1;   /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface
+                                         *   mode.                                                                     */
+                __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
+                __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
+                __IOM uint8_t ERS  : 1; /*!< [4..4] Error Signal Status Flag                                           */
+                __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
+                __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
+                __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
+            } SSR_SMCI_b;
+        };
+    };
+
+    union
+    {
+        __IM uint8_t RDR;              /*!< (@ 0x00000005) Receive Data Register                                      */
+
+        struct
+        {
+            __IM uint8_t RDR : 8;      /*!< [7..0] RDR is an 8-bit register that stores receive data.                 */
+        } RDR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SCMR;            /*!< (@ 0x00000006) Smart Card Mode Register                                   */
+
+        struct
+        {
+            __IOM uint8_t SMIF : 1;    /*!< [0..0] Smart Card Interface Mode Select                                   */
+            uint8_t            : 1;
+            __IOM uint8_t SINV : 1;    /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if
+                                        *   operation is to be in simple I2C mode.                                    */
+            __IOM uint8_t SDIR : 1;    /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The
+                                        *   setting is invalid and a fixed data length of 8 bits is
+                                        *   used in modes other than asynchronous mode.Set this bit
+                                        *   to 1 if operation is to be in simple I2C mode.                            */
+            __IOM uint8_t CHR1 : 1;    /*!< [4..4] Character Length 1(Only valid in asynchronous mode)                */
+            uint8_t            : 2;
+            __IOM uint8_t BCP2 : 1;    /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles
+                                        *   in combination with the SMR.BCP[1:0] bits                                 */
+        } SCMR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SEMR;            /*!< (@ 0x00000007) Serial Extended Mode Register                              */
+
+        struct
+        {
+            __IOM uint8_t ACS0 : 1;    /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in
+                                        *   asynchronous mode).                                                       */
+            __IOM uint8_t PADIS : 1;   /*!< [1..1] Preamble function Disable (Valid only in asynchronous
+                                        *   mode).                                                                    */
+            __IOM uint8_t BRME  : 1;   /*!< [2..2] Bit Rate Modulation Enable                                         */
+            __IOM uint8_t ABCSE : 1;   /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid
+                                        *   only in asynchronous mode and SCR.CKE[1]=0)                               */
+            __IOM uint8_t ABCS : 1;    /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous
+                                        *   mode)                                                                     */
+            __IOM uint8_t NFEN : 1;    /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should
+                                        *   be 0 without simple I2C mode and asynchronous mode.)In
+                                        *   asynchronous mode, for RXDn input only. In simple I2C mode,
+                                        *   for RXDn/TxDn input.                                                      */
+            __IOM uint8_t BGDM : 1;    /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid
+                                        *   the CKE[1] bit in SCR is 0 in asynchronous mode).                         */
+            __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only
+                                        *   in asynchronous mode)                                                     */
+        } SEMR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SNFR;            /*!< (@ 0x00000008) Noise Filter Setting Register                              */
+
+        struct
+        {
+            __IOM uint8_t NFCS : 3;    /*!< [2..0] Noise Filter Clock Select                                          */
+            uint8_t            : 5;
+        } SNFR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SIMR1;           /*!< (@ 0x00000009) I2C Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t IICM  : 1;   /*!< [0..0] Simple I2C Mode Select                                             */
+            uint8_t             : 2;
+            __IOM uint8_t IICDL : 5;   /*!< [7..3] SDA Delay Output SelectCycles below are of the clock
+                                        *   signal from the on-chip baud rate generator.                              */
+        } SIMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SIMR2;           /*!< (@ 0x0000000A) I2C Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select                                          */
+            __IOM uint8_t IICCSC  : 1; /*!< [1..1] Clock Synchronization                                              */
+            uint8_t               : 3;
+            __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data                                              */
+            uint8_t               : 2;
+        } SIMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SIMR3;              /*!< (@ 0x0000000B) I2C Mode Register 3                                        */
+
+        struct
+        {
+            __IOM uint8_t IICSTAREQ  : 1; /*!< [0..0] Start Condition Generation                                         */
+            __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation                                       */
+            __IOM uint8_t IICSTPREQ  : 1; /*!< [2..2] Stop Condition Generation                                          */
+            __IOM uint8_t IICSTIF    : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
+                                           *   Flag(When 0 is written to IICSTIF, it is cleared to 0.)                   */
+            __IOM uint8_t IICSDAS : 2;    /*!< [5..4] SDA Output Select                                                  */
+            __IOM uint8_t IICSCLS : 2;    /*!< [7..6] SCL Output Select                                                  */
+        } SIMR3_b;
+    };
+
+    union
+    {
+        __IM uint8_t SISR;             /*!< (@ 0x0000000C) I2C Status Register                                        */
+
+        struct
+        {
+            __IM uint8_t IICACKR : 1;  /*!< [0..0] ACK Reception Data Flag                                            */
+            uint8_t              : 7;
+        } SISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPMR;            /*!< (@ 0x0000000D) SPI Mode Register                                          */
+
+        struct
+        {
+            __IOM uint8_t SSE    : 1;  /*!< [0..0] SSn Pin Function Enable                                            */
+            __IOM uint8_t CTSE   : 1;  /*!< [1..1] CTS Enable                                                         */
+            __IOM uint8_t MSS    : 1;  /*!< [2..2] Master Slave Select                                                */
+            __IOM uint8_t CSTPEN : 1;  /*!< [3..3] CTS external pin Enable                                            */
+            __IOM uint8_t MFF    : 1;  /*!< [4..4] Mode Fault Flag                                                    */
+            uint8_t              : 1;
+            __IOM uint8_t CKPOL  : 1;  /*!< [6..6] Clock Polarity Select                                              */
+            __IOM uint8_t CKPH   : 1;  /*!< [7..7] Clock Phase Select                                                 */
+        } SPMR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint16_t TDRHL;         /*!< (@ 0x0000000E) Transmit 9-bit Data Register                               */
+
+            struct
+            {
+                __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data.             */
+            } TDRHL_b;
+        };
+
+        union
+        {
+            __OM uint16_t FTDRHL;       /*!< (@ 0x0000000E) Transmit FIFO Data Register HL                             */
+
+            struct
+            {
+                __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including
+                                         *   multi-processor) or clock synchronous mode, and FIFO selected)            */
+                __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous
+                                         *   mode and SMR.MP=1 and FIFO selected)                                      */
+                uint16_t : 6;
+            } FTDRHL_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __OM uint8_t FTDRH;         /*!< (@ 0x0000000E) Transmit FIFO Data Register H                              */
+
+                struct
+                {
+                    __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous
+                                             *   mode(including multi-processor) or clock synchronous mode,
+                                             *   and FIFO selected)                                                        */
+                    __OM uint8_t MPBT : 1;  /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous
+                                             *   mode and SMR.MP=1 and FIFO selected)                                      */
+                    uint8_t : 6;
+                } FTDRH_b;
+            };
+
+            union
+            {
+                __OM uint8_t FTDRL;         /*!< (@ 0x0000000F) Transmit FIFO Data Register L                              */
+
+                struct
+                {
+                    __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous
+                                             *   mode(including multi-processor) or clock synchronous mode,
+                                             *   and FIFO selected)                                                        */
+                } FTDRL_b;
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint16_t RDRHL;          /*!< (@ 0x00000010) Receive 9-bit Data Register                                */
+
+            struct
+            {
+                __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data.             */
+            } RDRHL_b;
+        };
+
+        union
+        {
+            __IM uint16_t FRDRHL;       /*!< (@ 0x00000010) Receive FIFO Data Register HL                              */
+
+            struct
+            {
+                __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including
+                                         *   multi-processor) or clock synchronous mode, and FIFO selected)            */
+                __IM uint16_t MPB : 1;  /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode
+                                         *   with SMR.MP=1 and FIFO selected) It can read multi-processor
+                                         *   bit corresponded to serial receive data(RDATA[8:0])                       */
+                __IM uint16_t DR   : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR)                    */
+                __IM uint16_t PER  : 1; /*!< [11..11] Parity error flag                                                */
+                __IM uint16_t FER  : 1; /*!< [12..12] Framing error flag                                               */
+                __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER)                       */
+                __IM uint16_t RDF  : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF)               */
+                uint16_t           : 1;
+            } FRDRHL_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IM uint8_t FRDRH;         /*!< (@ 0x00000010) Receive FIFO Data Register H                               */
+
+                struct
+                {
+                    __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including
+                                             *   multi-processor) or clock synchronous mode, and FIFO selected)            */
+                    __IM uint8_t MPB : 1;   /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode
+                                             *   with SMR.MP=1 and FIFO selected) It can read multi-processor
+                                             *   bit corresponded to serial receive data(RDATA[8:0])                       */
+                    __IM uint8_t DR   : 1;  /*!< [2..2] Receive data ready flag(It is same as SSR.DR)                      */
+                    __IM uint8_t PER  : 1;  /*!< [3..3] Parity error flag                                                  */
+                    __IM uint8_t FER  : 1;  /*!< [4..4] Framing error flag                                                 */
+                    __IM uint8_t ORER : 1;  /*!< [5..5] Overrun error flag(It is same as SSR.ORER)                         */
+                    __IM uint8_t RDF  : 1;  /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF)                 */
+                    uint8_t           : 1;
+                } FRDRH_b;
+            };
+
+            union
+            {
+                __IM uint8_t FRDRL;         /*!< (@ 0x00000011) Receive FIFO Data Register L                               */
+
+                struct
+                {
+                    __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including
+                                             *   multi-processor) or clock synchronous mode, and FIFO selected)NOTE:
+                                             *   When reading both of FRDRH register and FRDRL register,
+                                             *   please read by an order of the FRDRH register and the FRDRL
+                                             *   register.                                                                 */
+                } FRDRL_b;
+            };
+        };
+    };
+
+    union
+    {
+        __IOM uint8_t MDDR;            /*!< (@ 0x00000012) Modulation Duty Register                                   */
+
+        struct
+        {
+            __IOM uint8_t MDDR : 8;    /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register.           */
+        } MDDR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DCCR;            /*!< (@ 0x00000013) Data Compare Match Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t DCMF  : 1;   /*!< [0..0] Data Compare Match Flag                                            */
+            uint8_t             : 2;
+            __IOM uint8_t DPER  : 1;   /*!< [3..3] Data Compare Match Parity Error Flag                               */
+            __IOM uint8_t DFER  : 1;   /*!< [4..4] Data Compare Match Framing Error Flag                              */
+            uint8_t             : 1;
+            __IOM uint8_t IDSEL : 1;   /*!< [6..6] ID frame select(Valid only in asynchronous mode(including
+                                        *   multi-processor)                                                          */
+            __IOM uint8_t DCME : 1;    /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous
+                                        *   mode(including multi-processor)                                           */
+        } DCCR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t FCR;            /*!< (@ 0x00000014) FIFO Control Register                                      */
+
+        struct
+        {
+            __IOM uint16_t FM : 1;     /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including
+                                        *   multi-processor) or clock synchronous mode)                               */
+            __IOM uint16_t RFRST : 1;  /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1)           */
+            __IOM uint16_t TFRST : 1;  /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1)          */
+            __IOM uint16_t DRES  : 1;  /*!< [3..3] Receive data ready error select bit(When detecting a
+                                        *   reception data ready, the interrupt request is selected.)                 */
+            __IOM uint16_t TTRG : 4;   /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous
+                                        *   mode(including multi-processor) or clock synchronous mode)                */
+            __IOM uint16_t RTRG : 4;   /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous
+                                        *   mode(including multi-processor) or clock synchronous mode)                */
+            __IOM uint16_t RSTRG : 4;  /*!< [15..12] RTS Output Active Trigger Number Select(Valid only
+                                        *   in asynchronous mode(including multi-processor) or clock
+                                        *   synchronous mode)                                                         */
+        } FCR_b;
+    };
+
+    union
+    {
+        __IM uint16_t FDR;             /*!< (@ 0x00000016) FIFO Data Count Register                                   */
+
+        struct
+        {
+            __IM uint16_t R : 5;       /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive
+                                        *   data stored in FRDRH and FRDRL(Valid only in asynchronous
+                                        *   mode(including multi-processor) or clock synchronous mode,
+                                        *   while FCR.FM=1)                                                           */
+            uint16_t        : 3;
+            __IM uint16_t T : 5;       /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit
+                                        *   data stored in FTDRH and FTDRL(Valid only in asynchronous
+                                        *   mode(including multi-processor) or clock synchronous mode,
+                                        *   while FCR.FM=1)                                                           */
+            uint16_t : 3;
+        } FDR_b;
+    };
+
+    union
+    {
+        __IM uint16_t LSR;             /*!< (@ 0x00000018) Line Status Register                                       */
+
+        struct
+        {
+            __IM uint16_t ORER : 1;    /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including
+                                        *   multi-processor) or clock synchronous mode, and FIFO selected)            */
+            uint16_t           : 1;
+            __IM uint16_t FNUM : 5;    /*!< [6..2] Framing Error CountIndicates the quantity of data with
+                                        *   a framing error among the receive data stored in the receive
+                                        *   FIFO data register (FRDRH and FRDRL).                                     */
+            uint16_t           : 1;
+            __IM uint16_t PNUM : 5;    /*!< [12..8] Parity Error CountIndicates the quantity of data with
+                                        *   a parity error among the receive data stored in the receive
+                                        *   FIFO data register (FRDRH and FRDRL).                                     */
+            uint16_t : 3;
+        } LSR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t CDR;            /*!< (@ 0x0000001A) Compare Match Data Register                                */
+
+        struct
+        {
+            __IOM uint16_t CMPD : 9;   /*!< [8..0] Compare Match DataCompare data pattern for address match
+                                        *   wake-up function                                                          */
+            uint16_t : 7;
+        } CDR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPTR;            /*!< (@ 0x0000001C) Serial Port Register                                       */
+
+        struct
+        {
+            __IM uint8_t RXDMON : 1;   /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal
+                                        *   is shown.)                                                                */
+            __IOM uint8_t SPB2DT : 1;  /*!< [1..1] Serial port break data select bit(The output level of
+                                        *   TxD terminal is selected when SCR.TE = 0.)                                */
+            __IOM uint8_t SPB2IO : 1;  /*!< [2..2] Serial port break I/O bit(It's selected whether the value
+                                        *   of SPB2DT is output to TxD terminal.)                                     */
+            uint8_t            : 1;
+            __IOM uint8_t RINV : 1;    /*!< [4..4] RXD invert bit                                                     */
+            __IOM uint8_t TINV : 1;    /*!< [5..5] TXD invert bit                                                     */
+            __IOM uint8_t ASEN : 1;    /*!< [6..6] Adjust receive sampling timing enable                              */
+            __IOM uint8_t ATEN : 1;    /*!< [7..7] Adjust transmit timing enable                                      */
+        } SPTR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ACTR;            /*!< (@ 0x0000001D) Adjustment Communication Timing Register                   */
+
+        struct
+        {
+            __IOM uint8_t AST : 3;     /*!< [2..0] Adjustment value for receive Sampling Timing                       */
+            __IOM uint8_t AJD : 1;     /*!< [3..3] Adjustment Direction for receive sampling timing                   */
+            __IOM uint8_t ATT : 3;     /*!< [6..4] Adjustment value for Transmit timing                               */
+            __IOM uint8_t AET : 1;     /*!< [7..7] Adjustment edge for transmit timing                                */
+        } ACTR_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t ESMER;           /*!< (@ 0x00000020) Extended Serial Module Enable Register                     */
+
+        struct
+        {
+            __IOM uint8_t ESME : 1;    /*!< [0..0] Extended Serial Mode Enable                                        */
+            uint8_t            : 7;
+        } ESMER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CR0;             /*!< (@ 0x00000021) Control Register 0                                         */
+
+        struct
+        {
+            uint8_t             : 1;
+            __IM uint8_t  SFSF  : 1;   /*!< [1..1] Start Frame Status Flag                                            */
+            __IM uint8_t  RXDSF : 1;   /*!< [2..2] RXDXn Input Status Flag                                            */
+            __IOM uint8_t BRME  : 1;   /*!< [3..3] Bit Rate Measurement Enable                                        */
+            uint8_t             : 4;
+        } CR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CR1;             /*!< (@ 0x00000022) Control Register 1                                         */
+
+        struct
+        {
+            __IOM uint8_t BFE   : 1;   /*!< [0..0] Break Field Enable                                                 */
+            __IOM uint8_t CF0RE : 1;   /*!< [1..1] Control Field 0 Reception Enable                                   */
+            __IOM uint8_t CF1DS : 2;   /*!< [3..2] Control Field 1 Data Register Select                               */
+            __IOM uint8_t PIBE  : 1;   /*!< [4..4] Priority Interrupt Bit Enable                                      */
+            __IOM uint8_t PIBS  : 3;   /*!< [7..5] Priority Interrupt Bit Select                                      */
+        } CR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CR2;             /*!< (@ 0x00000023) Control Register 2                                         */
+
+        struct
+        {
+            __IOM uint8_t DFCS : 3;    /*!< [2..0] RXDXn Signal Digital Filter Clock Select                           */
+            uint8_t            : 1;
+            __IOM uint8_t BCCS : 2;    /*!< [5..4] Bus Collision Detection Clock Select                               */
+            __IOM uint8_t RTS  : 2;    /*!< [7..6] RXDXn Reception Sampling Timing Select                             */
+        } CR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CR3;             /*!< (@ 0x00000024) Control Register 3                                         */
+
+        struct
+        {
+            __IOM uint8_t SDST : 1;    /*!< [0..0] Start Frame Detection Start                                        */
+            uint8_t            : 7;
+        } CR3_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PCR;             /*!< (@ 0x00000025) Port Control Register                                      */
+
+        struct
+        {
+            __IOM uint8_t TXDXPS : 1;  /*!< [0..0] TXDXn Signal Polarity Select                                       */
+            __IOM uint8_t RXDXPS : 1;  /*!< [1..1] RXDXn Signal Polarity Select                                       */
+            uint8_t              : 2;
+            __IOM uint8_t SHARPS : 1;  /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select                                */
+            uint8_t              : 3;
+        } PCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICR;             /*!< (@ 0x00000026) Interrupt Control Register                                 */
+
+        struct
+        {
+            __IOM uint8_t BFDIE  : 1;  /*!< [0..0] Break Field Low Width Detected Interrupt Enable                    */
+            __IOM uint8_t CF0MIE : 1;  /*!< [1..1] Control Field 0 Match Detected Interrupt Enable                    */
+            __IOM uint8_t CF1MIE : 1;  /*!< [2..2] Control Field 1 Match Detected Interrupt Enable                    */
+            __IOM uint8_t PIBDIE : 1;  /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable                   */
+            __IOM uint8_t BCDIE  : 1;  /*!< [4..4] Bus Collision Detected Interrupt Enable                            */
+            __IOM uint8_t AEDIE  : 1;  /*!< [5..5] Valid Edge Detected Interrupt Enable                               */
+            uint8_t              : 2;
+        } ICR_b;
+    };
+
+    union
+    {
+        __IM uint8_t STR;              /*!< (@ 0x00000027) Status Register                                            */
+
+        struct
+        {
+            __IM uint8_t BFDF  : 1;    /*!< [0..0] Break Field Low Width Detection Flag                               */
+            __IM uint8_t CF0MF : 1;    /*!< [1..1] Control Field 0 Match Flag                                         */
+            __IM uint8_t CF1MF : 1;    /*!< [2..2] Control Field 1 Match Flag                                         */
+            __IM uint8_t PIBDF : 1;    /*!< [3..3] Priority Interrupt Bit Detection Flag                              */
+            __IM uint8_t BCDF  : 1;    /*!< [4..4] Bus Collision Detected Flag                                        */
+            __IM uint8_t AEDF  : 1;    /*!< [5..5] Valid Edge Detection Flag                                          */
+            uint8_t            : 2;
+        } STR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t STCR;            /*!< (@ 0x00000028) Status Clear Register                                      */
+
+        struct
+        {
+            __IOM uint8_t BFDCL  : 1;  /*!< [0..0] BFDF Clear                                                         */
+            __IOM uint8_t CF0MCL : 1;  /*!< [1..1] CF0MF Clear                                                        */
+            __IOM uint8_t CF1MCL : 1;  /*!< [2..2] CF1MF Clear                                                        */
+            __IOM uint8_t PIBDCL : 1;  /*!< [3..3] PIBDF Clear                                                        */
+            __IOM uint8_t BCDCL  : 1;  /*!< [4..4] BCDF Clear                                                         */
+            __IOM uint8_t AEDCL  : 1;  /*!< [5..5] AEDF Clear                                                         */
+            uint8_t              : 2;
+        } STCR_b;
+    };
+    __IOM uint8_t CF0DR;               /*!< (@ 0x00000029) Control Field 0 Data Register                              */
+
+    union
+    {
+        __IOM uint8_t CF0CR;           /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register                    */
+
+        struct
+        {
+            __IOM uint8_t CF0CE0 : 1;  /*!< [0..0] Control Field 0 Bit 0 Compare Enable                               */
+            __IOM uint8_t CF0CE1 : 1;  /*!< [1..1] Control Field 1 Bit 0 Compare Enable                               */
+            __IOM uint8_t CF0CE2 : 1;  /*!< [2..2] Control Field 2 Bit 0 Compare Enable                               */
+            __IOM uint8_t CF0CE3 : 1;  /*!< [3..3] Control Field 3 Bit 0 Compare Enable                               */
+            __IOM uint8_t CF0CE4 : 1;  /*!< [4..4] Control Field 4 Bit 0 Compare Enable                               */
+            __IOM uint8_t CF0CE5 : 1;  /*!< [5..5] Control Field 5 Bit 0 Compare Enable                               */
+            __IOM uint8_t CF0CE6 : 1;  /*!< [6..6] Control Field 6 Bit 0 Compare Enable                               */
+            __IOM uint8_t CF0CE7 : 1;  /*!< [7..7] Control Field 7 Bit 0 Compare Enable                               */
+        } CF0CR_b;
+    };
+    __IOM uint8_t CF0RR;               /*!< (@ 0x0000002B) Control Field 0 Receive Data Register                      */
+    __IOM uint8_t PCF1DR;              /*!< (@ 0x0000002C) Primary Control Field 1 Data Register                      */
+    __IOM uint8_t SCF1DR;              /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register                    */
+
+    union
+    {
+        __IOM uint8_t CF1CR;           /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register                    */
+
+        struct
+        {
+            __IOM uint8_t CF1CE0 : 1;  /*!< [0..0] Control Field 1 Bit 0 Compare Enable                               */
+            __IOM uint8_t CF1CE1 : 1;  /*!< [1..1] Control Field 1 Bit 1 Compare Enable                               */
+            __IOM uint8_t CF1CE2 : 1;  /*!< [2..2] Control Field 1 Bit 2 Compare Enable                               */
+            __IOM uint8_t CF1CE3 : 1;  /*!< [3..3] Control Field 1 Bit 3 Compare Enable                               */
+            __IOM uint8_t CF1CE4 : 1;  /*!< [4..4] Control Field 1 Bit 4 Compare Enable                               */
+            __IOM uint8_t CF1CE5 : 1;  /*!< [5..5] Control Field 1 Bit 5 Compare Enable                               */
+            __IOM uint8_t CF1CE6 : 1;  /*!< [6..6] Control Field 1 Bit 6 Compare Enable                               */
+            __IOM uint8_t CF1CE7 : 1;  /*!< [7..7] Control Field 1 Bit 7 Compare Enable                               */
+        } CF1CR_b;
+    };
+    __IOM uint8_t CF1RR;               /*!< (@ 0x0000002F) Control Field 1 Receive Data Register                      */
+
+    union
+    {
+        __IOM uint8_t TCR;             /*!< (@ 0x00000030) Timer Control Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TCST : 1;    /*!< [0..0] Timer Count Start                                                  */
+            uint8_t            : 7;
+        } TCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TMR;             /*!< (@ 0x00000031) Timer Mode Register                                        */
+
+        struct
+        {
+            __IOM uint8_t TOMS : 2;    /*!< [1..0] Timer Operating Mode Select                                        */
+            uint8_t            : 1;
+            __IOM uint8_t TWRC : 1;    /*!< [3..3] Counter Write Control                                              */
+            __IOM uint8_t TCSS : 3;    /*!< [6..4] Timer Count Clock Source Select                                    */
+            uint8_t            : 1;
+        } TMR_b;
+    };
+    __IOM uint8_t TPRE;                /*!< (@ 0x00000032) Timer Prescaler Register                                   */
+    __IOM uint8_t TCNT;                /*!< (@ 0x00000033) Timer Count Register                                       */
+} R_SCI0_Type;                         /*!< Size = 52 (0x34)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SPI0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Serial Peripheral Interface (R_SPI0)
+ */
+
+typedef struct                         /*!< (@ 0x4011A000) R_SPI0 Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t SPCR;            /*!< (@ 0x00000000) SPI Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t SPMS   : 1;  /*!< [0..0] SPI Mode Select                                                    */
+            __IOM uint8_t TXMD   : 1;  /*!< [1..1] Communications Operating Mode Select                               */
+            __IOM uint8_t MODFEN : 1;  /*!< [2..2] Mode Fault Error Detection Enable                                  */
+            __IOM uint8_t MSTR   : 1;  /*!< [3..3] SPI Master/Slave Mode Select                                       */
+            __IOM uint8_t SPEIE  : 1;  /*!< [4..4] SPI Error Interrupt Enable                                         */
+            __IOM uint8_t SPTIE  : 1;  /*!< [5..5] Transmit Buffer Empty Interrupt Enable                             */
+            __IOM uint8_t SPE    : 1;  /*!< [6..6] SPI Function Enable                                                */
+            __IOM uint8_t SPRIE  : 1;  /*!< [7..7] SPI Receive Buffer Full Interrupt Enable                           */
+        } SPCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SSLP;            /*!< (@ 0x00000001) SPI Slave Select Polarity Register                         */
+
+        struct
+        {
+            __IOM uint8_t SSL0P : 1;   /*!< [0..0] SSL0 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL1P : 1;   /*!< [1..1] SSL1 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL2P : 1;   /*!< [2..2] SSL2 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL3P : 1;   /*!< [3..3] SSL3 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL4P : 1;   /*!< [4..4] SSL4 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL5P : 1;   /*!< [5..5] SSL5 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL6P : 1;   /*!< [6..6] SSL6 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL7P : 1;   /*!< [7..7] SSL7 Signal Polarity Setting                                       */
+        } SSLP_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPPCR;           /*!< (@ 0x00000002) SPI Pin Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t SPLP  : 1;   /*!< [0..0] SPI Loopback                                                       */
+            __IOM uint8_t SPLP2 : 1;   /*!< [1..1] SPI Loopback 2                                                     */
+            uint8_t             : 2;
+            __IOM uint8_t MOIFV : 1;   /*!< [4..4] MOSI Idle Fixed Value                                              */
+            __IOM uint8_t MOIFE : 1;   /*!< [5..5] MOSI Idle Value Fixing Enable                                      */
+            uint8_t             : 2;
+        } SPPCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPSR;            /*!< (@ 0x00000003) SPI Status Register                                        */
+
+        struct
+        {
+            __IOM uint8_t OVRF  : 1;   /*!< [0..0] Overrun Error Flag                                                 */
+            __IM uint8_t  IDLNF : 1;   /*!< [1..1] SPI Idle Flag                                                      */
+            __IOM uint8_t MODF  : 1;   /*!< [2..2] Mode Fault Error Flag                                              */
+            __IOM uint8_t PERF  : 1;   /*!< [3..3] Parity Error Flag                                                  */
+            __IOM uint8_t UDRF  : 1;   /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.)          */
+            __IOM uint8_t SPTEF : 1;   /*!< [5..5] SPI Transmit Buffer Empty Flag                                     */
+            __IOM uint8_t CENDF : 1;   /*!< [6..6] Communication End Flag                                             */
+            __IOM uint8_t SPRF  : 1;   /*!< [7..7] SPI Receive Buffer Full Flag                                       */
+        } SPSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SPDR;           /*!< (@ 0x00000004) SPI Data Register                                          */
+        __IOM uint16_t SPDR_HA;        /*!< (@ 0x00000004) SPI Data Register ( halfword access )                      */
+        __IOM uint8_t  SPDR_BY;        /*!< (@ 0x00000004) SPI Data Register ( byte access )                          */
+    };
+
+    union
+    {
+        __IOM uint8_t SPSCR;           /*!< (@ 0x00000008) SPI Sequence Control Register                              */
+
+        struct
+        {
+            __IOM uint8_t SPSLN : 3;   /*!< [2..0] RSPI Sequence Length SpecificationThe order in which
+                                        *   the SPCMD0 to SPCMD07 registers are to be referenced is
+                                        *   changed in accordance with the sequence length that is
+                                        *   set in these bits. The relationship among the setting of
+                                        *   these bits, sequence length, and SPCMD0 to SPCMD7 registers
+                                        *   referenced by the RSPI is shown above. However, the RSPI
+                                        *   in slave mode always references SPCMD0.                                   */
+            uint8_t : 5;
+        } SPSCR_b;
+    };
+
+    union
+    {
+        __IM uint8_t SPSSR;            /*!< (@ 0x00000009) SPI Sequence Status Register                               */
+
+        struct
+        {
+            __IM uint8_t SPCP  : 3;    /*!< [2..0] RSPI Command Pointer                                               */
+            uint8_t            : 1;
+            __IM uint8_t SPECM : 3;    /*!< [6..4] RSPI Error Command                                                 */
+            uint8_t            : 1;
+        } SPSSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPBR;            /*!< (@ 0x0000000A) SPI Bit Rate Register                                      */
+
+        struct
+        {
+            __IOM uint8_t SPR : 8;     /*!< [7..0] SPBR sets the bit rate in master mode.                             */
+        } SPBR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPDCR;           /*!< (@ 0x0000000B) SPI Data Control Register                                  */
+
+        struct
+        {
+            __IOM uint8_t SPFC   : 2;  /*!< [1..0] Number of Frames Specification                                     */
+            __IOM uint8_t SLSEL  : 2;  /*!< [3..2] SSL Pin Output Select                                              */
+            __IOM uint8_t SPRDTD : 1;  /*!< [4..4] SPI Receive/Transmit Data Selection                                */
+            __IOM uint8_t SPLW   : 1;  /*!< [5..5] SPI Word Access/Halfword Access Specification                      */
+            __IOM uint8_t SPBYT  : 1;  /*!< [6..6] SPI Byte Access Specification                                      */
+            uint8_t              : 1;
+        } SPDCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPCKD;           /*!< (@ 0x0000000C) SPI Clock Delay Register                                   */
+
+        struct
+        {
+            __IOM uint8_t SCKDL : 3;   /*!< [2..0] RSPCK Delay Setting                                                */
+            uint8_t             : 5;
+        } SPCKD_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SSLND;           /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register                   */
+
+        struct
+        {
+            __IOM uint8_t SLNDL : 3;   /*!< [2..0] SSL Negation Delay Setting                                         */
+            uint8_t             : 5;
+        } SSLND_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPND;            /*!< (@ 0x0000000E) SPI Next-Access Delay Register                             */
+
+        struct
+        {
+            __IOM uint8_t SPNDL : 3;   /*!< [2..0] SPI Next-Access Delay Setting                                      */
+            uint8_t             : 5;
+        } SPND_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPCR2;           /*!< (@ 0x0000000F) SPI Control Register 2                                     */
+
+        struct
+        {
+            __IOM uint8_t SPPE   : 1;  /*!< [0..0] Parity Enable                                                      */
+            __IOM uint8_t SPOE   : 1;  /*!< [1..1] Parity Mode                                                        */
+            __IOM uint8_t SPIIE  : 1;  /*!< [2..2] SPI Idle Interrupt Enable                                          */
+            __IOM uint8_t PTE    : 1;  /*!< [3..3] Parity Self-Testing                                                */
+            __IOM uint8_t SCKASE : 1;  /*!< [4..4] RSPCK Auto-Stop Function Enable                                    */
+            __IOM uint8_t SPTDDL : 3;  /*!< [7..5] RSPI Transmit Data Delay                                           */
+        } SPCR2_b;
+    };
+
+    union
+    {
+        __IOM uint16_t SPCMD[8];       /*!< (@ 0x00000010) SPI Command Register [0..7]                                */
+
+        struct
+        {
+            __IOM uint16_t CPHA   : 1; /*!< [0..0] RSPCK Phase Setting                                                */
+            __IOM uint16_t CPOL   : 1; /*!< [1..1] RSPCK Polarity Setting                                             */
+            __IOM uint16_t BRDV   : 2; /*!< [3..2] Bit Rate Division Setting                                          */
+            __IOM uint16_t SSLA   : 3; /*!< [6..4] SSL Signal Assertion Setting                                       */
+            __IOM uint16_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Keeping                                           */
+            __IOM uint16_t SPB    : 4; /*!< [11..8] SPI Data Length Setting                                           */
+            __IOM uint16_t LSBF   : 1; /*!< [12..12] SPI LSB First                                                    */
+            __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable                                     */
+            __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
+            __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
+        } SPCMD_b[8];
+    };
+
+    union
+    {
+        __IOM uint8_t SPDCR2;          /*!< (@ 0x00000020) SPI Data Control Register 2                                */
+
+        struct
+        {
+            __IOM uint8_t BYSW : 1;    /*!< [0..0] Byte Swap Operating Mode Select                                    */
+            __IOM uint8_t SINV : 1;    /*!< [1..1] Serial data invert bit                                             */
+            uint8_t            : 6;
+        } SPDCR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPCR3;           /*!< (@ 0x00000021) RSPI Control Register 3                                    */
+
+        struct
+        {
+            __IOM uint8_t ETXMD  : 1;  /*!< [0..0] Extended Communication Mode Select                                 */
+            __IOM uint8_t BFDS   : 1;  /*!< [1..1] Between Burst Transfer Frames Delay Select                         */
+            uint8_t              : 2;
+            __IOM uint8_t CENDIE : 1;  /*!< [4..4] RSPI Communication End Interrupt Enable                            */
+            uint8_t              : 3;
+        } SPCR3_b;
+    };
+    __IM uint16_t RESERVED;
+    __IM uint32_t RESERVED1[6];
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint16_t SPPR;           /*!< (@ 0x0000003E) RSPI Parameter Read Register                               */
+
+        struct
+        {
+            uint16_t              : 4;
+            __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check                                                 */
+            uint16_t              : 3;
+            __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check                                               */
+            uint16_t              : 1;
+            __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check                                             */
+        } SPPR_b;
+    };
+} R_SPI0_Type;                         /*!< Size = 64 (0x40)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SRAM                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief SRAM (R_SRAM)
+ */
+
+typedef struct                         /*!< (@ 0x40002000) R_SRAM Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t PARIOAD;         /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register       */
+
+        struct
+        {
+            __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after Detection                                          */
+            uint8_t           : 7;
+        } PARIOAD_b;
+    };
+    __IM uint8_t RESERVED[3];
+
+    union
+    {
+        __IOM uint8_t SRAMPRCR;         /*!< (@ 0x00000004) SRAM Protection Register                                   */
+
+        struct
+        {
+            __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control                                             */
+            __OM uint8_t  KW       : 7; /*!< [7..1] Write Key Code                                                     */
+        } SRAMPRCR_b;
+    };
+    __IM uint8_t  RESERVED1[3];
+    __IOM uint8_t SRAMWTSC;             /*!< (@ 0x00000008) RAM Wait State Control Register                            */
+    __IM uint8_t  RESERVED2[3];
+
+    union
+    {
+        __IOM uint8_t SRAMPRCR2;         /*!< (@ 0x0000000C) SRAM Protection Register 2                                 */
+
+        struct
+        {
+            __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control                                             */
+            __OM uint8_t  KW        : 7; /*!< [7..1] Write Key Code                                                     */
+        } SRAMPRCR2_b;
+    };
+    __IM uint8_t RESERVED3[179];
+
+    union
+    {
+        __IOM uint8_t ECCMODE;         /*!< (@ 0x000000C0) ECC Operating Mode Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t ECCMOD : 2;  /*!< [1..0] ECC Operating Mode Select                                          */
+            uint8_t              : 6;
+        } ECCMODE_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ECC2STS;         /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register                            */
+
+        struct
+        {
+            __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status                                             */
+            uint8_t               : 7;
+        } ECC2STS_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ECC1STSEN;       /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register         */
+
+        struct
+        {
+            __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable                          */
+            uint8_t               : 7;
+        } ECC1STSEN_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ECC1STS;         /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register                            */
+
+        struct
+        {
+            __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status                                             */
+            uint8_t               : 7;
+        } ECC1STS_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ECCPRCR;         /*!< (@ 0x000000C4) ECC Protection Register                                    */
+
+        struct
+        {
+            __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control                                             */
+            __OM uint8_t  KW      : 7; /*!< [7..1] Write Key Code                                                     */
+        } ECCPRCR_b;
+    };
+    __IM uint8_t RESERVED4[11];
+
+    union
+    {
+        __IOM uint8_t ECCPRCR2;         /*!< (@ 0x000000D0) ECC Protection Register 2                                  */
+
+        struct
+        {
+            __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control                                             */
+            __OM uint8_t  KW2      : 7; /*!< [7..1] Write Key Code                                                     */
+        } ECCPRCR2_b;
+    };
+    __IM uint8_t RESERVED5[3];
+
+    union
+    {
+        __IOM uint8_t ECCETST;         /*!< (@ 0x000000D4) ECC Test Control Register                                  */
+
+        struct
+        {
+            __IOM uint8_t TSTBYP : 1;  /*!< [0..0] ECC Bypass Select                                                  */
+            uint8_t              : 7;
+        } ECCETST_b;
+    };
+    __IM uint8_t RESERVED6[3];
+
+    union
+    {
+        __IOM uint8_t ECCOAD;          /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register          */
+
+        struct
+        {
+            __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after Detection                                          */
+            uint8_t           : 7;
+        } ECCOAD_b;
+    };
+} R_SRAM_Type;                         /*!< Size = 217 (0xd9)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SSI0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0)
+ */
+
+typedef struct                         /*!< (@ 0x4009D000) R_SSI0 Structure                                           */
+{
+    union
+    {
+        __IOM uint32_t SSICR;          /*!< (@ 0x00000000) Control Register                                           */
+
+        struct
+        {
+            __IOM uint32_t REN  : 1;   /*!< [0..0] Receive Enable                                                     */
+            __IOM uint32_t TEN  : 1;   /*!< [1..1] Transmit Enable                                                    */
+            uint32_t            : 1;
+            __IOM uint32_t MUEN : 1;   /*!< [3..3] Mute EnableNOTE: When this module is muted, the value
+                                        *   of outputting serial data is rewritten to 0 but data transmission
+                                        *   is not stopped. Write dummy data to the SSIFTDR not to
+                                        *   generate a transmit underflow because the number of data
+                                        *   in the transmit FIFO is decreasing.                                       */
+            __IOM uint32_t CKDV  : 4;  /*!< [7..4] Serial Oversampling Clock Division Ratio                           */
+            __IOM uint32_t DEL   : 1;  /*!< [8..8] Serial Data Delay                                                  */
+            __IOM uint32_t PDTA  : 1;  /*!< [9..9] Parallel Data Alignment                                            */
+            __IOM uint32_t SDTA  : 1;  /*!< [10..10] Serial Data Alignment                                            */
+            __IOM uint32_t SPDP  : 1;  /*!< [11..11] Serial Padding Polarity                                          */
+            __IOM uint32_t LRCKP : 1;  /*!< [12..12] Serial WS Polarity                                               */
+            __IOM uint32_t BCKP  : 1;  /*!< [13..13] Serial Bit Clock Polarity                                        */
+            __IOM uint32_t MST   : 1;  /*!< [14..14] Serial WS Direction NOTE: Only the following settings
+                                        *   are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings
+                                        *   are prohibited.                                                           */
+            uint32_t           : 1;
+            __IOM uint32_t SWL : 3;    /*!< [18..16] System Word LengthSet the system word length to the
+                                        *   bit clock frequency/2 fs.                                                 */
+            __IOM uint32_t DWL   : 3;  /*!< [21..19] Data Word Length                                                 */
+            __IOM uint32_t FRM   : 2;  /*!< [23..22] Channels                                                         */
+            uint32_t             : 1;
+            __IOM uint32_t IIEN  : 1;  /*!< [25..25] Idle Mode Interrupt Enable                                       */
+            __IOM uint32_t ROIEN : 1;  /*!< [26..26] Receive Overflow Interrupt Enable                                */
+            __IOM uint32_t RUIEN : 1;  /*!< [27..27] Receive Underflow Interrupt Enable                               */
+            __IOM uint32_t TOIEN : 1;  /*!< [28..28] Transmit Overflow Interrupt Enable                               */
+            __IOM uint32_t TUIEN : 1;  /*!< [29..29] Transmit Underflow Interrupt Enable                              */
+            __IOM uint32_t CKS   : 1;  /*!< [30..30] Oversampling Clock Select                                        */
+            uint32_t             : 1;
+        } SSICR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SSISR;          /*!< (@ 0x00000004) Status Register                                            */
+
+        struct
+        {
+            __IM uint32_t IDST   : 1;  /*!< [0..0] Idle Mode Status Flag                                              */
+            __IM uint32_t RSWNO  : 1;  /*!< [1..1] Receive Serial Word Number                                         */
+            __IM uint32_t RCHNO  : 2;  /*!< [3..2] Receive Channel Number.These bits are read as 00b.                 */
+            __IM uint32_t TSWNO  : 1;  /*!< [4..4] Transmit Serial Word Number                                        */
+            __IM uint32_t TCHNO  : 2;  /*!< [6..5] Transmit Channel Number                                            */
+            uint32_t             : 18;
+            __IM uint32_t  IIRQ  : 1;  /*!< [25..25] Idle Mode Interrupt Status Flag                                  */
+            __IOM uint32_t ROIRQ : 1;  /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE:
+                                        *   Writable only to clear the flag. Confirm the value is 1
+                                        *   and then write 0.                                                         */
+            __IOM uint32_t RUIRQ : 1;  /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE:
+                                        *   Writable only to clear the flag. Confirm the value is 1
+                                        *   and then write 0.                                                         */
+            __IOM uint32_t TOIRQ : 1;  /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE:
+                                        *   Writable only to clear the flag. Confirm the value is 1
+                                        *   and then write 0.                                                         */
+            __IOM uint32_t TUIRQ : 1;  /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE:
+                                        *   Writable only to clear the flag. Confirm the value is 1
+                                        *   and then write 0.                                                         */
+            uint32_t : 2;
+        } SSISR_b;
+    };
+    __IM uint32_t RESERVED[2];
+
+    union
+    {
+        __IOM uint32_t SSIFCR;         /*!< (@ 0x00000010) FIFO Control Register                                      */
+
+        struct
+        {
+            __IOM uint32_t RFRST : 1;  /*!< [0..0] Receive FIFO Data Register Reset                                   */
+            __IOM uint32_t TFRST : 1;  /*!< [1..1] Transmit FIFO Data Register Reset                                  */
+            __IOM uint32_t RIE   : 1;  /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by
+                                        *   clearing either the RDF flag (see the description of the
+                                        *   RDF bit for details) or RIE bit.                                          */
+            __IOM uint32_t TIE : 1;    /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by
+                                        *   clearing either the TDE flag (see the description of the
+                                        *   TDE bit for details) or TIE bit.                                          */
+            __IOM uint32_t RTRG : 2;   /*!< [5..4] Receive Data Trigger Number                                        */
+            __IOM uint32_t TTRG : 2;   /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis
+                                        *   are the number of empty stages in SSIFTDR at which the
+                                        *   TDE flag is set.                                                          */
+            uint32_t              : 3;
+            __IOM uint32_t BSW    : 1; /*!< [11..11] Byte Swap Enable                                                 */
+            uint32_t              : 4;
+            __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset                                              */
+            uint32_t              : 14;
+            __IOM uint32_t AUCKE  : 1; /*!< [31..31] Oversampling Clock Enable                                        */
+        } SSIFCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SSIFSR;         /*!< (@ 0x00000014) FIFO Status Register                                       */
+
+        struct
+        {
+            __IOM uint32_t RDF : 1;    /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register
+                                        *   is a 32-byte FIFO register, the maximum number of data
+                                        *   bytes that can be read from it while the RDF flag is 1
+                                        *   is indicated in the RDC[3:0] flags. If reading data from
+                                        *   the SSIFRDR register is continued after all the data is
+                                        *   read, undefined values will be read.                                      */
+            uint32_t          : 7;
+            __IM uint32_t RDC : 6;     /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data
+                                        *   units stored in SSIFRDR)                                                  */
+            uint32_t           : 2;
+            __IOM uint32_t TDE : 1;    /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register
+                                        *   is a 32-byte FIFO register, the maximum number of bytes
+                                        *   that can be written to it while the TDE flag is 1 is 8
+                                        *   - TDC[3:0]. If writing data to the SSIFTDR register is
+                                        *   continued after all the data is written, writing will be
+                                        *   invalid and an overflow occurs.                                           */
+            uint32_t          : 7;
+            __IM uint32_t TDC : 6;     /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of
+                                        *   data units stored in SSIFTDR)                                             */
+            uint32_t : 2;
+        } SSIFSR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __OM uint32_t SSIFTDR;          /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
+
+            struct
+            {
+                __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of
+                                             *   eight stages of 32-bit registers for storing data to be
+                                             *   serially transmitted. NOTE: that when the SSIFTDR register
+                                             *   is full of data (32 bytes), the next data cannot be written
+                                             *   to it. If writing is attempted, it will be ignored and
+                                             *   an overflow occurs.                                                       */
+            } SSIFTDR_b;
+        };
+        __OM uint16_t SSIFTDR16;            /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
+        __OM uint8_t  SSIFTDR8;             /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t SSIFRDR;          /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
+
+            struct
+            {
+                __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight
+                                             *   stages of 32-bit registers for storing serially received
+                                             *   data.                                                                     */
+            } SSIFRDR_b;
+        };
+        __IM uint16_t SSIFRDR16;            /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
+        __IM uint8_t  SSIFRDR8;             /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
+    };
+
+    union
+    {
+        __IOM uint32_t SSIOFR;          /*!< (@ 0x00000020) Audio Format Register                                      */
+
+        struct
+        {
+            __IOM uint32_t OMOD    : 2; /*!< [1..0] Audio Format Select                                                */
+            uint32_t               : 6;
+            __IOM uint32_t LRCONT  : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation                             */
+            __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in
+                                         *   Idle Status                                                               */
+            uint32_t : 22;
+        } SSIOFR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SSISCR;         /*!< (@ 0x00000024) Status Control Register                                    */
+
+        struct
+        {
+            __IOM uint32_t RDFS : 5;   /*!< [4..0] RDF Setting Condition Select                                       */
+            uint32_t            : 3;
+            __IOM uint32_t TDES : 5;   /*!< [12..8] TDE Setting Condition Select                                      */
+            uint32_t            : 19;
+        } SSISCR_b;
+    };
+} R_SSI0_Type;                         /*!< Size = 40 (0x28)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SYSTEM                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief System Pins (R_SYSTEM)
+ */
+
+typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure                                         */
+{
+    __IM uint32_t RESERVED[3];
+
+    union
+    {
+        __IOM uint16_t SBYCR;          /*!< (@ 0x0000000C) Standby Control Register                                   */
+
+        struct
+        {
+            uint16_t            : 14;
+            __IOM uint16_t OPE  : 1;   /*!< [14..14] Output Port Enable                                               */
+            __IOM uint16_t SSBY : 1;   /*!< [15..15] Software Standby                                                 */
+        } SBYCR_b;
+    };
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2[3];
+
+    union
+    {
+        __IOM uint32_t MSTPCRA;         /*!< (@ 0x0000001C) Module Stop Control Register A                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPA0  : 1; /*!< [0..0] RAM0 Module Stop                                                   */
+            __IOM uint32_t MSTPA1  : 1; /*!< [1..1] RAM1 Module Stop                                                   */
+            uint32_t               : 3;
+            __IOM uint32_t MSTPA5  : 1; /*!< [5..5] High-Speed RAM Module Stop                                         */
+            __IOM uint32_t MSTPA6  : 1; /*!< [6..6] ECCRAM Module Stop                                                 */
+            __IOM uint32_t MSTPA7  : 1; /*!< [7..7] Standby RAM Module Stop                                            */
+            uint32_t               : 14;
+            __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop              */
+            uint32_t               : 9;
+        } MSTPCRA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SCKDIVCR;       /*!< (@ 0x00000020) System Clock Division Control Register                     */
+
+        struct
+        {
+            __IOM uint32_t PCKD : 3;   /*!< [2..0] Peripheral Module Clock D (PCLKD) Select                           */
+            uint32_t            : 1;
+            __IOM uint32_t PCKC : 3;   /*!< [6..4] Peripheral Module Clock C (PCLKC) Select                           */
+            uint32_t            : 1;
+            __IOM uint32_t PCKB : 3;   /*!< [10..8] Peripheral Module Clock B (PCLKB) Select                          */
+            uint32_t            : 1;
+            __IOM uint32_t PCKA : 3;   /*!< [14..12] Peripheral Module Clock A (PCLKA) Select                         */
+            uint32_t            : 1;
+            __IOM uint32_t BCK  : 3;   /*!< [18..16] External Bus Clock (BCLK) Select                                 */
+            uint32_t            : 5;
+            __IOM uint32_t ICK  : 3;   /*!< [26..24] System Clock (ICLK) Select                                       */
+            uint32_t            : 1;
+            __IOM uint32_t FCK  : 3;   /*!< [30..28] Flash IF Clock (FCLK) Select                                     */
+            uint32_t            : 1;
+        } SCKDIVCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SCKDIVCR2;       /*!< (@ 0x00000024) System Clock Division Control Register 2                   */
+
+        struct
+        {
+            uint8_t           : 4;
+            __IOM uint8_t UCK : 3;     /*!< [6..4] USB Clock (UCLK) Select                                            */
+            uint8_t           : 1;
+        } SCKDIVCR2_b;
+    };
+    __IM uint8_t RESERVED3;
+
+    union
+    {
+        __IOM uint8_t SCKSCR;          /*!< (@ 0x00000026) System Clock Source Control Register                       */
+
+        struct
+        {
+            __IOM uint8_t CKSEL : 3;   /*!< [2..0] Clock Source Select                                                */
+            uint8_t             : 5;
+        } SCKSCR_b;
+    };
+    __IM uint8_t RESERVED4;
+
+    union
+    {
+        __IOM uint16_t PLLCCR;           /*!< (@ 0x00000028) PLL Clock Control Register                                 */
+
+        struct
+        {
+            __IOM uint16_t PLIDIV   : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select                          */
+            uint16_t                : 2;
+            __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select                                            */
+            uint16_t                : 3;
+            __IOM uint16_t PLLMUL   : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency
+                                          *   Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 -
+                                          *   0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0
+                                          *   : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5
+                                          *   111011: x30.0                                                             */
+            uint16_t : 2;
+        } PLLCCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PLLCR;           /*!< (@ 0x0000002A) PLL Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t PLLSTP : 1;  /*!< [0..0] PLL Stop Control                                                   */
+            uint8_t              : 7;
+        } PLLCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PLLCCR2;         /*!< (@ 0x0000002B) PLL Clock Control Register2                                */
+
+        struct
+        {
+            __IOM uint8_t PLLMUL : 5;  /*!< [4..0] PLL Frequency Multiplication Factor Select                         */
+            uint8_t              : 1;
+            __IOM uint8_t PLODIV : 2;  /*!< [7..6] PLL Output Frequency Division Ratio Select                         */
+        } PLLCCR2_b;
+    };
+    __IM uint32_t RESERVED5;
+
+    union
+    {
+        __IOM uint8_t BCKCR;           /*!< (@ 0x00000030) External Bus Clock Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select                                             */
+            uint8_t               : 7;
+        } BCKCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t MEMWAIT;         /*!< (@ 0x00000031) Memory Wait Cycle Control Register                         */
+
+        struct
+        {
+            __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT
+                                        *   is prohibited when SCKDIVCR.ICK selects division by 1 and
+                                        *   SCKSCR.CKSEL[2:0] bits select thesystem clock source that
+                                        *   is faster than 32 MHz (ICLK > 32 MHz).                                    */
+            uint8_t : 7;
+        } MEMWAIT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t MOSCCR;          /*!< (@ 0x00000032) Main Clock Oscillator Control Register                     */
+
+        struct
+        {
+            __IOM uint8_t MOSTP : 1;   /*!< [0..0] Main Clock Oscillator Stop                                         */
+            uint8_t             : 7;
+        } MOSCCR_b;
+    };
+    __IM uint8_t  RESERVED6;
+    __IM uint16_t RESERVED7;
+
+    union
+    {
+        __IOM uint8_t HOCOCR;          /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register             */
+
+        struct
+        {
+            __IOM uint8_t HCSTP : 1;   /*!< [0..0] HOCO Stop                                                          */
+            uint8_t             : 7;
+        } HOCOCR_b;
+    };
+    __IM uint8_t RESERVED8;
+
+    union
+    {
+        __IOM uint8_t MOCOCR;          /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register           */
+
+        struct
+        {
+            __IOM uint8_t MCSTP : 1;   /*!< [0..0] MOCO Stop                                                          */
+            uint8_t             : 7;
+        } MOCOCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t FLLCR1;          /*!< (@ 0x00000039) FLL Control Register 1                                     */
+
+        struct
+        {
+            __IOM uint8_t FLLEN : 1;   /*!< [0..0] FLL Enable                                                         */
+            uint8_t             : 7;
+        } FLLCR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t FLLCR2;           /*!< (@ 0x0000003A) FLL Control Register 2                                     */
+
+        struct
+        {
+            __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the
+                                          *   FLL reference clock select                                                */
+            uint16_t : 5;
+        } FLLCR2_b;
+    };
+
+    union
+    {
+        __IM uint8_t OSCSF;            /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register                    */
+
+        struct
+        {
+            __IM uint8_t HOCOSF : 1;   /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF
+                                        *   bit value after a reset is 1 when the OFS1.HOCOEN bit is
+                                        *   0. It is 0 when the OFS1.HOCOEN bit is 1.                                 */
+            uint8_t             : 2;
+            __IM uint8_t MOSCSF : 1;   /*!< [3..3] Main Clock Oscillation Stabilization Flag                          */
+            uint8_t             : 1;
+            __IM uint8_t PLLSF  : 1;   /*!< [5..5] PLL Clock Oscillation Stabilization Flag                           */
+            __IM uint8_t PLL2SF : 1;   /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag                          */
+            uint8_t             : 1;
+        } OSCSF_b;
+    };
+    __IM uint8_t RESERVED9;
+
+    union
+    {
+        __IOM uint8_t CKOCR;           /*!< (@ 0x0000003E) Clock Out Control Register                                 */
+
+        struct
+        {
+            __IOM uint8_t CKOSEL : 3;  /*!< [2..0] Clock out source select                                            */
+            uint8_t              : 1;
+            __IOM uint8_t CKODIV : 3;  /*!< [6..4] Clock out input frequency Division Select                          */
+            __IOM uint8_t CKOEN  : 1;  /*!< [7..7] Clock out enable                                                   */
+        } CKOCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TRCKCR;          /*!< (@ 0x0000003F) Trace Clock Control Register                               */
+
+        struct
+        {
+            __IOM uint8_t TRCK   : 4;  /*!< [3..0] Trace Clock operating frequency select                             */
+            uint8_t              : 3;
+            __IOM uint8_t TRCKEN : 1;  /*!< [7..7] Trace Clock operating Enable                                       */
+        } TRCKCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t OSTDCR;          /*!< (@ 0x00000040) Oscillation Stop Detection Control Register                */
+
+        struct
+        {
+            __IOM uint8_t OSTDIE : 1;  /*!< [0..0] Oscillation Stop Detection Interrupt Enable                        */
+            uint8_t              : 6;
+            __IOM uint8_t OSTDE  : 1;  /*!< [7..7] Oscillation Stop Detection Function Enable                         */
+        } OSTDCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t OSTDSR;          /*!< (@ 0x00000041) Oscillation Stop Detection Status Register                 */
+
+        struct
+        {
+            __IOM uint8_t OSTDF : 1;   /*!< [0..0] Oscillation Stop Detection Flag                                    */
+            uint8_t             : 7;
+        } OSTDSR_b;
+    };
+    __IM uint16_t RESERVED10;
+    __IM uint32_t RESERVED11;
+
+    union
+    {
+        __IOM uint16_t PLL2CCR;           /*!< (@ 0x00000048) PLL2 Clock Control Register                                */
+
+        struct
+        {
+            __IOM uint16_t PL2IDIV   : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select                         */
+            uint16_t                 : 2;
+            __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select                                           */
+            uint16_t                 : 3;
+            __IOM uint16_t PLL2MUL   : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select                       */
+            uint16_t                 : 2;
+        } PLL2CCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PLL2CR;          /*!< (@ 0x0000004A) PLL2 Control Register                                      */
+
+        struct
+        {
+            __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control                                                  */
+            uint8_t               : 7;
+        } PLL2CR_b;
+    };
+    __IM uint8_t RESERVED12;
+
+    union
+    {
+        __IOM uint8_t LPOPT;             /*!< (@ 0x0000004C) Lower Power Operation Control Register                     */
+
+        struct
+        {
+            __IOM uint8_t MPUDIS : 1;    /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock
+                                          *   (valid only when LPOPTEN = 1)                                             */
+            __IOM uint8_t DCLKDIS   : 2; /*!< [2..1] Debug Clock Disable Control                                        */
+            __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W
+                                          *   clock (valid only when LPOPT.LPOPTEN = 1)                                 */
+            uint8_t               : 3;
+            __IOM uint8_t LPOPTEN : 1;   /*!< [7..7] Lower Power Operation Enable                                       */
+        } LPOPT_b;
+    };
+    __IM uint8_t  RESERVED13;
+    __IM uint16_t RESERVED14;
+
+    union
+    {
+        __IOM uint8_t SLCDSCKCR;         /*!< (@ 0x00000050) Segment LCD Source Clock Control Register                  */
+
+        struct
+        {
+            __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select                                */
+            uint8_t                 : 4;
+            __IOM uint8_t LCDSCKEN  : 1; /*!< [7..7] LCD Source Clock Out Enable                                        */
+        } SLCDSCKCR_b;
+    };
+    __IM uint8_t RESERVED15;
+
+    union
+    {
+        __IOM uint8_t EBCKOCR;         /*!< (@ 0x00000052) External Bus Clock Output Control Register                 */
+
+        struct
+        {
+            __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control                                            */
+            uint8_t               : 7;
+        } EBCKOCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SDCKOCR;         /*!< (@ 0x00000053) SDRAM Clock Output Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control                                           */
+            uint8_t               : 7;
+        } SDCKOCR_b;
+    };
+    __IM uint32_t RESERVED16[3];
+    __IM uint8_t  RESERVED17;
+
+    union
+    {
+        __IOM uint8_t MOCOUTCR;         /*!< (@ 0x00000061) MOCO User Trimming Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127
+                                         *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
+                                         *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
+                                         +126 0111_1111 : +127These bits are added to original MOCO
+                                         *   trimming bits                                                             */
+        } MOCOUTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t HOCOUTCR;         /*!< (@ 0x00000062) HOCO User Trimming Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127
+                                         *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
+                                         *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
+                                         +126 0111_1111 : +127These bits are added to original HOCO
+                                         *   trimming bits                                                             */
+        } HOCOUTCR_b;
+    };
+    __IM uint8_t  RESERVED18;
+    __IM uint32_t RESERVED19[2];
+
+    union
+    {
+        __IOM uint8_t USBCKDIVCR;       /*!< (@ 0x0000006C) USB Clock Division Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select                                 */
+            uint8_t                : 5;
+        } USBCKDIVCR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t OCTACKDIVCR;       /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register                  */
+
+            struct
+            {
+                __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select                          */
+                uint8_t                 : 5;
+            } OCTACKDIVCR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t SCISPICKDIVCR;       /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register                    */
+
+            struct
+            {
+                __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select                          */
+                uint8_t                   : 5;
+            } SCISPICKDIVCR_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint8_t CANFDCKDIVCR;       /*!< (@ 0x0000006E) CANFD Clock Division Control Register                      */
+
+        struct
+        {
+            __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select                             */
+            uint8_t                  : 5;
+        } CANFDCKDIVCR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t GPTCKDIVCR;       /*!< (@ 0x0000006F) GPT Clock Division Control Register                        */
+
+            struct
+            {
+                __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select                                 */
+                uint8_t                : 5;
+            } GPTCKDIVCR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t USB60CKDIVCR;       /*!< (@ 0x0000006F) USB60 Clock Division Control Register                      */
+
+            struct
+            {
+                __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select                               */
+                uint8_t                  : 5;
+            } USB60CKDIVCR_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t CECCKDIVCR;       /*!< (@ 0x00000070) CEC Clock Division Control Register                        */
+
+            struct
+            {
+                __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select                                 */
+                uint8_t                : 5;
+            } CECCKDIVCR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t IICCKDIVCR;       /*!< (@ 0x00000070) IIC Clock Division Control Register                        */
+
+            struct
+            {
+                __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select                                 */
+                uint8_t                : 5;
+            } IICCKDIVCR_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
+
+        struct
+        {
+            __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
+            uint8_t                : 5;
+        } I3CCKDIVCR_b;
+    };
+    __IM uint16_t RESERVED20;
+
+    union
+    {
+        __IOM uint8_t USBCKCR;           /*!< (@ 0x00000074) USB Clock Control Register                                 */
+
+        struct
+        {
+            __IOM uint8_t USBCKSEL  : 3; /*!< [2..0] USB Clock (USBCLK) Source Select                                   */
+            uint8_t                 : 3;
+            __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request                               */
+            __IM uint8_t  USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag                      */
+        } USBCKCR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t OCTACKCR;           /*!< (@ 0x00000075) Octal-SPI Clock Control Register                           */
+
+            struct
+            {
+                __IOM uint8_t OCTACKSEL  : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select                            */
+                uint8_t                  : 3;
+                __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request                        */
+                __IM uint8_t  OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag               */
+            } OCTACKCR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t SCISPICKCR;           /*!< (@ 0x00000075) SCI SPI Clock Control Register                             */
+
+            struct
+            {
+                __IOM uint8_t SCISPICKSEL  : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select                            */
+                uint8_t                    : 3;
+                __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request                        */
+                __IM uint8_t  SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag               */
+            } SCISPICKCR_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint8_t CANFDCKCR;           /*!< (@ 0x00000076) CANFD Clock Control Register                               */
+
+        struct
+        {
+            __IOM uint8_t CANFDCKSEL  : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select                               */
+            uint8_t                   : 3;
+            __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request                           */
+            __IM uint8_t  CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag                  */
+        } CANFDCKCR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t GPTCKCR;           /*!< (@ 0x00000077) GPT Clock Control Register                                 */
+
+            struct
+            {
+                __IOM uint8_t GPTCKSEL  : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select                                   */
+                uint8_t                 : 3;
+                __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request                               */
+                __IM uint8_t  GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag                      */
+            } GPTCKCR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t USB60CKCR;           /*!< (@ 0x00000077) USB60 clock control register                               */
+
+            struct
+            {
+                __IOM uint8_t USB60CKSEL  : 4; /*!< [3..0] USB clock (USB60CLK) Source Select                                 */
+                uint8_t                   : 2;
+                __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request                             */
+                __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag                    */
+            } USB60CKCR_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t CECCKCR;           /*!< (@ 0x00000078) CEC Clock Control Register                                 */
+
+            struct
+            {
+                __IOM uint8_t CECCKSEL  : 3; /*!< [2..0] CEC clock (CECCLK) Source Select                                   */
+                uint8_t                 : 3;
+                __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request                               */
+                __IM uint8_t  CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag                      */
+            } CECCKCR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t IICCKCR;           /*!< (@ 0x00000078) IIC Clock Control Register                                 */
+
+            struct
+            {
+                __IOM uint8_t IICCKSEL  : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select                                   */
+                uint8_t                 : 3;
+                __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request                               */
+                __IM uint8_t  IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag                      */
+            } IICCKCR_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint8_t I3CCKCR;           /*!< (@ 0x00000079) I3C Clock Control Register                                 */
+
+        struct
+        {
+            __IOM uint8_t I3CCKSEL  : 3; /*!< [2..0] I3C clock (I3CCLK) source select                                   */
+            uint8_t                 : 3;
+            __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request                               */
+            __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
+        } I3CCKCR_b;
+    };
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
+
+    union
+    {
+        __IOM uint32_t SNZREQCR1;         /*!< (@ 0x00000088) Snooze Request Control Register 1                          */
+
+        struct
+        {
+            __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request                               */
+            __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request                               */
+            __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request                               */
+            uint32_t                 : 29;
+        } SNZREQCR1_b;
+    };
+    __IM uint32_t RESERVED23;
+    __IM uint16_t RESERVED24;
+
+    union
+    {
+        __IOM uint8_t SNZCR;            /*!< (@ 0x00000092) Snooze Control Register                                    */
+
+        struct
+        {
+            __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other
+                                         *   than in asynchronous mode.                                                */
+            __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode                                          */
+            uint8_t                : 5;
+            __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
+        } SNZCR_b;
+    };
+    __IM uint8_t RESERVED25;
+
+    union
+    {
+        __IOM uint8_t SNZEDCR;           /*!< (@ 0x00000094) Snooze End Control Register                                */
+
+        struct
+        {
+            __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable                                   */
+            __IOM uint8_t DTCZRED   : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable                 */
+            __IOM uint8_t DTCNZRED  : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable             */
+            __IOM uint8_t AD0MATED  : 1; /*!< [3..3] AD compare match 0 Snooze End Enable                               */
+            __IOM uint8_t AD0UMTED  : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable                            */
+            __IOM uint8_t AD1MATED  : 1; /*!< [5..5] AD compare match 1 Snooze End Enable                               */
+            __IOM uint8_t AD1UMTED  : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable                            */
+            __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set
+                                          *   to 1 other than in asynchronous mode.                                     */
+        } SNZEDCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SNZEDCR1;          /*!< (@ 0x00000095) Snooze End Control Register 1                              */
+
+        struct
+        {
+            __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable                                   */
+            uint8_t                 : 7;
+        } SNZEDCR1_b;
+    };
+    __IM uint16_t RESERVED26;
+
+    union
+    {
+        __IOM uint32_t SNZREQCR;           /*!< (@ 0x00000098) Snooze Request Control Register                            */
+
+        struct
+        {
+            __IOM uint32_t SNZREQEN0  : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request             */
+            __IOM uint32_t SNZREQEN1  : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request             */
+            __IOM uint32_t SNZREQEN2  : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request             */
+            __IOM uint32_t SNZREQEN3  : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request             */
+            __IOM uint32_t SNZREQEN4  : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request             */
+            __IOM uint32_t SNZREQEN5  : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request             */
+            __IOM uint32_t SNZREQEN6  : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request             */
+            __IOM uint32_t SNZREQEN7  : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request             */
+            __IOM uint32_t SNZREQEN8  : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request             */
+            __IOM uint32_t SNZREQEN9  : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request             */
+            __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request          */
+            __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request          */
+            __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request          */
+            __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request          */
+            __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request          */
+            __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request          */
+            uint32_t                  : 1;
+            __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request                 */
+            uint32_t                  : 4;
+            __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze
+                                            *   request                                                                   */
+            __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze
+                                            *   request                                                                   */
+            __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request          */
+            __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request         */
+            uint32_t                  : 2;
+            __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze
+                                            *   request                                                                   */
+            __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A
+                                            *   snooze request                                                            */
+            __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B
+                                            *   snooze request                                                            */
+            uint32_t : 1;
+        } SNZREQCR_b;
+    };
+    __IM uint16_t RESERVED27;
+
+    union
+    {
+        __IOM uint8_t FLSTOP;          /*!< (@ 0x0000009E) Flash Operation Control Register                           */
+
+        struct
+        {
+            __IOM uint8_t FLSTOP : 1;  /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation                     */
+            uint8_t              : 3;
+            __IOM uint8_t FLSTPF : 1;  /*!< [4..4] Flash Memory Operation Status Flag                                 */
+            uint8_t              : 3;
+        } FLSTOP_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PSMCR;           /*!< (@ 0x0000009F) Power Save Memory Control Register                         */
+
+        struct
+        {
+            __IOM uint8_t PSMC : 2;    /*!< [1..0] Power save memory control.                                         */
+            uint8_t            : 6;
+        } PSMCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t OPCCR;           /*!< (@ 0x000000A0) Operating Power Control Register                           */
+
+        struct
+        {
+            __IOM uint8_t OPCM   : 2;  /*!< [1..0] Operating Power Control Mode Select                                */
+            uint8_t              : 2;
+            __IM uint8_t OPCMTSF : 1;  /*!< [4..4] Operating Power Control Mode Transition Status Flag                */
+            uint8_t              : 3;
+        } OPCCR_b;
+    };
+    __IM uint8_t RESERVED28;
+
+    union
+    {
+        __IOM uint8_t MOSCWTCR;        /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register                */
+
+        struct
+        {
+            __IOM uint8_t MSTS : 4;    /*!< [3..0] Main clock oscillator wait time setting                            */
+            uint8_t            : 4;
+        } MOSCWTCR_b;
+    };
+    __IM uint8_t RESERVED29[2];
+
+    union
+    {
+        __IOM uint8_t HOCOWTCR;        /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register        */
+
+        struct
+        {
+            __IOM uint8_t HSTS : 3;    /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of
+                                        *   the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed)                     */
+            uint8_t : 5;
+        } HOCOWTCR_b;
+    };
+    __IM uint16_t RESERVED30[2];
+
+    union
+    {
+        __IOM uint8_t SOPCCR;          /*!< (@ 0x000000AA) Sub Operating Power Control Register                       */
+
+        struct
+        {
+            __IOM uint8_t SOPCM   : 1; /*!< [0..0] Sub Operating Power Control Mode Select                            */
+            uint8_t               : 3;
+            __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag            */
+            uint8_t               : 3;
+        } SOPCCR_b;
+    };
+    __IM uint8_t  RESERVED31;
+    __IM uint32_t RESERVED32[5];
+
+    union
+    {
+        __IOM uint16_t RSTSR1;         /*!< (@ 0x000000C0) Reset Status Register 1                                    */
+
+        struct
+        {
+            __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable
+                                        *   only to clear the flag. Confirm the value is 1 and then
+                                        *   write 0.                                                                  */
+            __IOM uint16_t WDTRF : 1;  /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to
+                                        *   clear the flag. Confirm the value is 1 and then write 0.                  */
+            __IOM uint16_t SWRF : 1;   /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear
+                                        *   the flag. Confirm the value is 1 and then write 0.                        */
+            uint16_t             : 5;
+            __IOM uint16_t RPERF : 1;  /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only
+                                        *   to clear the flag. Confirm the value is 1 and then write
+                                        *   0.                                                                        */
+            __IOM uint16_t REERF : 1;  /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to
+                                        *   clear the flag. Confirm the value is 1 and then write 0.                  */
+            __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only
+                                        *   to clear the flag. Confirm the value is 1 and then write
+                                        *   0.                                                                        */
+            __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only
+                                        *   to clear the flag. Confirm the value is 1 and then write
+                                        *   0.                                                                        */
+            __IOM uint16_t SPERF : 1;  /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear
+                                        *   the flag. Confirm the value is 1 and then write 0.                        */
+            __IOM uint16_t TZERF : 1;  /*!< [13..13] Trust Zone Error Reset Detect Flag                               */
+            uint16_t             : 1;
+            __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
+        } RSTSR1_b;
+    };
+    __IM uint16_t RESERVED33;
+    __IM uint32_t RESERVED34[3];
+
+    union
+    {
+        __IOM uint8_t USBCKCR_ALT;       /*!< (@ 0x000000D0) USB Clock Control Register                                 */
+
+        struct
+        {
+            __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock
+                                          *   (UCLK).                                                                   */
+            uint8_t : 7;
+        } USBCKCR_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SDADCCKCR;          /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control
+                                           *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select                      */
+            uint8_t                  : 6;
+            __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
+        } SDADCCKCR_b;
+    };
+    __IM uint16_t RESERVED35;
+    __IM uint32_t RESERVED36[3];
+
+    union
+    {
+        __IOM uint8_t LVD1CR1;         /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1               */
+
+        struct
+        {
+            __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
+            __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
+            uint8_t              : 5;
+        } LVD1CR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t LVD1SR;          /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register                  */
+
+        struct
+        {
+            __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
+                                        *   0 can be written to this bit. After writing 0 to this bit,
+                                        *   it takes 2 system clock cycles for the bit to be read as
+                                        *   0.                                                                        */
+            __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag                              */
+            uint8_t          : 6;
+        } LVD1SR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t LVD2CR1;         /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1               */
+
+        struct
+        {
+            __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
+            __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
+            uint8_t              : 5;
+        } LVD2CR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t LVD2SR;          /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register                  */
+
+        struct
+        {
+            __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
+                                        *   0 can be written to this bit. After writing 0 to this bit,
+                                        *   it takes 2 system clock cycles for the bit to be read as
+                                        *   0.                                                                        */
+            __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag                              */
+            uint8_t          : 6;
+        } LVD2SR_b;
+    };
+    __IM uint32_t RESERVED37[183];
+
+    union
+    {
+        __IOM uint32_t CGFSAR;           /*!< (@ 0x000003C0) Clock Generation Function Security Attribute
+                                          *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00                                        */
+            uint32_t                : 1;
+            __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02                                        */
+            __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03                                        */
+            __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04                                        */
+            __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05                                        */
+            __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06                                        */
+            __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07                                        */
+            __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08                                        */
+            __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09                                        */
+            uint32_t                : 1;
+            __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11                                      */
+            __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12                                      */
+            uint32_t                : 3;
+            __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16                                      */
+            __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17                                      */
+            uint32_t                : 14;
+        } CGFSAR_b;
+    };
+    __IM uint32_t RESERVED38;
+
+    union
+    {
+        __IOM uint32_t LPMSAR;          /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register               */
+
+        struct
+        {
+            __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
+            uint32_t               : 1;
+            __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
+            uint32_t               : 1;
+            __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4                                         */
+            uint32_t               : 3;
+            __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8                                         */
+            __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9                                         */
+            uint32_t               : 22;
+        } LPMSAR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t LVDSAR;          /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register        */
+
+            struct
+            {
+                __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
+                __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
+                uint32_t               : 30;
+            } LVDSAR_b;
+        };
+
+        union
+        {
+            __IOM uint32_t RSTSAR;          /*!< (@ 0x000003CC) Reset Security Attribution Register                        */
+
+            struct
+            {
+                __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
+                __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
+                __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
+                uint32_t               : 29;
+            } RSTSAR_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint32_t BBFSAR;           /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register        */
+
+        struct
+        {
+            __IOM uint32_t NONSEC0  : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
+            __IOM uint32_t NONSEC1  : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
+            __IOM uint32_t NONSEC2  : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
+            uint32_t                : 13;
+            __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16                                      */
+            __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17                                      */
+            __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18                                      */
+            __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19                                      */
+            __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20                                      */
+            __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21                                      */
+            __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22                                      */
+            __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23                                      */
+            uint32_t                : 8;
+        } BBFSAR_b;
+    };
+    __IM uint32_t RESERVED39[3];
+
+    union
+    {
+        __IOM uint32_t DPFSAR;          /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution
+                                         *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t DPFSA0 : 1;  /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   0                                                                         */
+            __IOM uint32_t DPFSA1 : 1;  /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   1                                                                         */
+            __IOM uint32_t DPFSA2 : 1;  /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   2                                                                         */
+            __IOM uint32_t DPFSA3 : 1;  /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   3                                                                         */
+            __IOM uint32_t DPFSA4 : 1;  /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   4                                                                         */
+            __IOM uint32_t DPFSA5 : 1;  /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   5                                                                         */
+            __IOM uint32_t DPFSA6 : 1;  /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   6                                                                         */
+            __IOM uint32_t DPFSA7 : 1;  /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   7                                                                         */
+            __IOM uint32_t DPFSA8 : 1;  /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   8                                                                         */
+            __IOM uint32_t DPFSA9 : 1;  /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   9                                                                         */
+            __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   10                                                                        */
+            __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   11                                                                        */
+            __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   12                                                                        */
+            __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   13                                                                        */
+            __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   14                                                                        */
+            __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   15                                                                        */
+            __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   16                                                                        */
+            __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   17                                                                        */
+            __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   18                                                                        */
+            __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   19                                                                        */
+            __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   20                                                                        */
+            uint32_t               : 3;
+            __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   24                                                                        */
+            uint32_t               : 1;
+            __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   26                                                                        */
+            __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   27                                                                        */
+            uint32_t : 4;
+        } DPFSAR_b;
+    };
+    __IM uint32_t RESERVED40[6];
+    __IM uint16_t RESERVED41;
+
+    union
+    {
+        __IOM uint16_t PRCR;           /*!< (@ 0x000003FE) Protect Register                                           */
+
+        struct
+        {
+            __IOM uint16_t PRC0 : 1;   /*!< [0..0] Enables writing to the registers related to the clock
+                                        *   generation circuit.                                                       */
+            __IOM uint16_t PRC1 : 1;   /*!< [1..1] Enables writing to the registers related to the operating
+                                        *   modes, the low power consumption modes and the battery
+                                        *   backup function.                                                          */
+            uint16_t            : 1;
+            __IOM uint16_t PRC3 : 1;   /*!< [3..3] Enables writing to the registers related to the LVD.               */
+            __IOM uint16_t PRC4 : 1;   /*!< [4..4] PRC4                                                               */
+            uint16_t            : 3;
+            __OM uint16_t PRKEY : 8;   /*!< [15..8] PRKEY Key Code                                                    */
+        } PRCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSBYCR;         /*!< (@ 0x00000400) Deep Standby Control Register                              */
+
+        struct
+        {
+            __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control                                               */
+            uint8_t               : 4;
+            __IOM uint8_t IOKEEP  : 1; /*!< [6..6] I/O Port Retention                                                 */
+            __IOM uint8_t DPSBY   : 1; /*!< [7..7] Deep Software Standby                                              */
+        } DPSBYCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSWCR;          /*!< (@ 0x00000401) Deep Standby Wait Control Register                         */
+
+        struct
+        {
+            __IOM uint8_t WTSTS : 6;   /*!< [5..0] Deep Software Wait Standby Time Setting Bit                        */
+            uint8_t             : 2;
+        } DPSWCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIER0;         /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0                   */
+
+        struct
+        {
+            __IOM uint8_t DIRQ0E : 1;  /*!< [0..0] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ1E : 1;  /*!< [1..1] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ2E : 1;  /*!< [2..2] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ3E : 1;  /*!< [3..3] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ4E : 1;  /*!< [4..4] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ5E : 1;  /*!< [5..5] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ6E : 1;  /*!< [6..6] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ7E : 1;  /*!< [7..7] IRQ-DS Pin Enable                                                  */
+        } DPSIER0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIER1;         /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1                   */
+
+        struct
+        {
+            __IOM uint8_t DIRQ8E  : 1; /*!< [0..0] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ9E  : 1; /*!< [1..1] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable                                                  */
+        } DPSIER1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIER2;          /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2                   */
+
+        struct
+        {
+            __IOM uint8_t DLVD1IE  : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable                             */
+            __IOM uint8_t DLVD2IE  : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable                             */
+            __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable           */
+            __IOM uint8_t DRTCAIE  : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable              */
+            __IOM uint8_t DNMIE    : 1; /*!< [4..4] NMI Pin Enable                                                     */
+            uint8_t                : 3;
+        } DPSIER2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIER3;          /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3                   */
+
+        struct
+        {
+            __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable             */
+            __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable             */
+            __IOM uint8_t DAGT1IE  : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable                   */
+            __IOM uint8_t DAGT3IE  : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable                   */
+            uint8_t                : 4;
+        } DPSIER3_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIFR0;         /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0                     */
+
+        struct
+        {
+            __IOM uint8_t DIRQ0F : 1;  /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ1F : 1;  /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ2F : 1;  /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ3F : 1;  /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ4F : 1;  /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ5F : 1;  /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ6F : 1;  /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ7F : 1;  /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag                                */
+        } DPSIFR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIFR1;         /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1                     */
+
+        struct
+        {
+            __IOM uint8_t DIRQ8F  : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ9F  : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag                                */
+        } DPSIFR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIFR2;          /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2                     */
+
+        struct
+        {
+            __IOM uint8_t DLVD1IF  : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag                                      */
+            __IOM uint8_t DLVD2IF  : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag                                      */
+            __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag                    */
+            __IOM uint8_t DRTCAIF  : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag                       */
+            __IOM uint8_t DNMIF    : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag                                   */
+            uint8_t                : 3;
+        } DPSIFR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIFR3;          /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3                     */
+
+        struct
+        {
+            __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag                      */
+            __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag                      */
+            __IOM uint8_t DAGT1IF  : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag                            */
+            __IOM uint8_t DAGT3IF  : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag                            */
+            uint8_t                : 4;
+        } DPSIFR3_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIEGR0;        /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0                     */
+
+        struct
+        {
+            __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select                                             */
+        } DPSIEGR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIEGR1;        /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1                     */
+
+        struct
+        {
+            __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select                                             */
+        } DPSIEGR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIEGR2;         /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2                     */
+
+        struct
+        {
+            __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select                                                   */
+            __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select                                                   */
+            uint8_t                : 2;
+            __IOM uint8_t DNMIEG   : 1; /*!< [4..4] NMI Pin Edge Select                                                */
+            uint8_t                : 3;
+        } DPSIEGR2_b;
+    };
+    __IM uint8_t RESERVED42;
+
+    union
+    {
+        __IOM uint8_t SYOCDCR;         /*!< (@ 0x0000040E) System Control OCD Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t DOCDF : 1;   /*!< [0..0] Deep Standby OCD flag                                              */
+            uint8_t             : 6;
+            __IOM uint8_t DBGEN : 1;   /*!< [7..7] Debugger Enable bit                                                */
+        } SYOCDCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t STCONR;          /*!< (@ 0x0000040F) Standby Condition Register                                 */
+
+        struct
+        {
+            __IOM uint8_t STCON : 2;   /*!< [1..0] SSTBY condition bit                                                */
+            uint8_t             : 6;
+        } STCONR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t RSTSR0;          /*!< (@ 0x00000410) Reset Status Register 0                                    */
+
+        struct
+        {
+            __IOM uint8_t PORF : 1;    /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear
+                                        *   the flag. Confirm the value is 1 and then write 0.                        */
+            __IOM uint8_t LVD0RF : 1;  /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only
+                                        *   to clear the flag. Confirm the value is 1 and then write
+                                        *   0.                                                                        */
+            __IOM uint8_t LVD1RF : 1;  /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only
+                                        *   to clear the flag. Confirm the value is 1 and then write
+                                        *   0.                                                                        */
+            __IOM uint8_t LVD2RF : 1;  /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only
+                                        *   to clear the flag. Confirm the value is 1 and then write
+                                        *   0.                                                                        */
+            uint8_t               : 3;
+            __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to
+                                        *   clear the flag. Confirm the value is 1 and then write 0.                  */
+        } RSTSR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t RSTSR2;          /*!< (@ 0x00000411) Reset Status Register 2                                    */
+
+        struct
+        {
+            __IOM uint8_t CWSF : 1;    /*!< [0..0] Cold/Warm Start Determination Flag                                 */
+            uint8_t            : 7;
+        } RSTSR2_b;
+    };
+    __IM uint8_t RESERVED43;
+
+    union
+    {
+        __IOM uint8_t MOMCR;           /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control
+                                        *                  Register                                                   */
+
+        struct
+        {
+            uint8_t                 : 3;
+            __IOM uint8_t MODRV1    : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching                 */
+            __IOM uint8_t MODRV0    : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching                 */
+            __IOM uint8_t MOSEL     : 1; /*!< [6..6] Main Clock Oscillator Switching                                    */
+            __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching
+                                          *   Enable                                                                    */
+        } MOMCR_b;
+    };
+    __IM uint16_t RESERVED44;
+
+    union
+    {
+        __IOM uint8_t FWEPROR;         /*!< (@ 0x00000416) Flash P/E Protect Register                                 */
+
+        struct
+        {
+            __IOM uint8_t FLWE : 2;    /*!< [1..0] Flash Programming and Erasure                                      */
+            uint8_t            : 6;
+        } FWEPROR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t LVCMPCR;     /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register                   */
+
+            struct
+            {
+                uint8_t             : 5;
+                __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable                                         */
+                __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable                                         */
+                uint8_t             : 1;
+            } LVCMPCR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t LVD1CMPCR;       /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register           */
+
+            struct
+            {
+                __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during
+                                            *   drop in voltage)                                                          */
+                uint8_t             : 2;
+                __IOM uint8_t LVD1E : 1;   /*!< [7..7] Voltage Detection 1 Enable                                         */
+            } LVD1CMPCR_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t LVDLVLR;         /*!< (@ 0x00000418) Voltage Detection Level Select Register                    */
+
+            struct
+            {
+                __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during
+                                            *   fall in voltage)                                                          */
+                __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during
+                                            *   fall in voltage)                                                          */
+            } LVDLVLR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t LVD2CMPCR;       /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register           */
+
+            struct
+            {
+                __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during
+                                            *   drop in voltage)                                                          */
+                uint8_t             : 4;
+                __IOM uint8_t LVD2E : 1;   /*!< [7..7] Voltage Detection 2 Enable                                         */
+            } LVD2CMPCR_b;
+        };
+    };
+    __IM uint8_t RESERVED45;
+
+    union
+    {
+        __IOM uint8_t LVD1CR0;         /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0               */
+
+        struct
+        {
+            __IOM uint8_t RIE   : 1;   /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
+            __IOM uint8_t DFDIS : 1;   /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select                 */
+            __IOM uint8_t CMPE  : 1;   /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
+            uint8_t             : 1;
+            __IOM uint8_t FSAMP : 2;   /*!< [5..4] Sampling Clock Select                                              */
+            __IOM uint8_t RI    : 1;   /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
+            __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
+        } LVD1CR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t LVD2CR0;         /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0               */
+
+        struct
+        {
+            __IOM uint8_t RIE   : 1;   /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
+            __IOM uint8_t DFDIS : 1;   /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select                 */
+            __IOM uint8_t CMPE  : 1;   /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
+            uint8_t             : 1;
+            __IOM uint8_t FSAMP : 2;   /*!< [5..4] Sampling Clock Select                                              */
+            __IOM uint8_t RI    : 1;   /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
+            __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
+        } LVD2CR0_b;
+    };
+    __IM uint8_t RESERVED46;
+
+    union
+    {
+        __IOM uint8_t VBATTMNSELR;        /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select
+                                           *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit                       */
+            uint8_t                  : 7;
+        } VBATTMNSELR_b;
+    };
+
+    union
+    {
+        __IM uint8_t VBATTMONR;        /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register                    */
+
+        struct
+        {
+            __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit                                          */
+            uint8_t               : 7;
+        } VBATTMONR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTCR1;           /*!< (@ 0x0000041F) VBATT Control Register1                                    */
+
+        struct
+        {
+            __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop                                   */
+            uint8_t                : 7;
+        } VBTCR1_b;
+    };
+    __IM uint32_t RESERVED47[8];
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t DCDCCTL;         /*!< (@ 0x00000440) DCDC/LDO Control Register                                  */
+
+            struct
+            {
+                __IOM uint8_t DCDCON  : 1; /*!< [0..0] LDO/DCDC on/off Control bit                                        */
+                __IOM uint8_t OCPEN   : 1; /*!< [1..1] DCDC OCP Function Enable bit                                       */
+                uint8_t               : 2;
+                __IOM uint8_t STOPZA  : 1; /*!< [4..4] DCDC IO Buffer Power Control bit                                   */
+                __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit                                       */
+                __IOM uint8_t FST     : 1; /*!< [6..6] DCDC Fast Startup                                                  */
+                __IOM uint8_t PD      : 1; /*!< [7..7] DCDC VREF Generate Disable bit                                     */
+            } DCDCCTL_b;
+        };
+
+        union
+        {
+            __IOM uint8_t LDOSCR;          /*!< (@ 0x00000440) LDO Stop Control Register                                  */
+
+            struct
+            {
+                __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop                                                          */
+                __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop                                                          */
+                uint8_t               : 6;
+            } LDOSCR_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint8_t VCCSEL;          /*!< (@ 0x00000441) Voltage Level Selection Control Register                   */
+
+        struct
+        {
+            __IOM uint8_t VCCSEL : 2;  /*!< [1..0] DCDC Working Voltage Level Selection                               */
+            uint8_t              : 6;
+        } VCCSEL_b;
+    };
+    __IM uint16_t RESERVED48;
+
+    union
+    {
+        __IOM uint8_t PL2LDOSCR;         /*!< (@ 0x00000444) PLL2-LDO Stop Control Register                             */
+
+        struct
+        {
+            __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop                                                          */
+            uint8_t                 : 7;
+        } PL2LDOSCR_b;
+    };
+    __IM uint8_t  RESERVED49;
+    __IM uint16_t RESERVED50;
+    __IM uint32_t RESERVED51[14];
+
+    union
+    {
+        __IOM uint8_t SOSCCR;          /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register                      */
+
+        struct
+        {
+            __IOM uint8_t SOSTP : 1;   /*!< [0..0] Sub-Clock Oscillator Stop                                          */
+            uint8_t             : 7;
+        } SOSCCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SOMCR;           /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register                 */
+
+        struct
+        {
+            __IOM uint8_t SODRV : 2;   /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching                    */
+            uint8_t             : 6;
+        } SOMCR_b;
+    };
+    __IM uint16_t RESERVED52;
+    __IM uint32_t RESERVED53[3];
+
+    union
+    {
+        __IOM uint8_t LOCOCR;          /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register              */
+
+        struct
+        {
+            __IOM uint8_t LCSTP : 1;   /*!< [0..0] LOCO Stop                                                          */
+            uint8_t             : 7;
+        } LOCOCR_b;
+    };
+    __IM uint8_t RESERVED54;
+
+    union
+    {
+        __IOM uint8_t LOCOUTCR;         /*!< (@ 0x00000492) LOCO User Trimming Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127
+                                         *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
+                                         *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
+                                         +126 0111_1111 : +127These bits are added to original LOCO
+                                         *   trimming bits                                                             */
+        } LOCOUTCR_b;
+    };
+    __IM uint8_t  RESERVED55;
+    __IM uint32_t RESERVED56[7];
+
+    union
+    {
+        __IOM uint8_t VBTCR2;          /*!< (@ 0x000004B0) VBATT Control Register2                                    */
+
+        struct
+        {
+            uint8_t                 : 4;
+            __IOM uint8_t VBTLVDEN  : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit                            */
+            uint8_t                 : 1;
+            __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit              */
+        } VBTCR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTSR;           /*!< (@ 0x000004B1) VBATT Status Register                                      */
+
+        struct
+        {
+            __IOM uint8_t VBTRDF  : 1; /*!< [0..0] VBAT_R Reset Detect Flag                                           */
+            __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag                              */
+            uint8_t               : 2;
+            __IM uint8_t VBTRVLD  : 1; /*!< [4..4] VBATT_R Valid                                                      */
+            uint8_t               : 3;
+        } VBTSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTCMPCR;        /*!< (@ 0x000004B2) VBATT Comparator Control Register                          */
+
+        struct
+        {
+            __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable                 */
+            uint8_t               : 7;
+        } VBTCMPCR_b;
+    };
+    __IM uint8_t RESERVED57;
+
+    union
+    {
+        __IOM uint8_t VBTLVDICR;          /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control
+                                           *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t VBTLVDIE   : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit                  */
+            __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit                        */
+            uint8_t                  : 6;
+        } VBTLVDICR_b;
+    };
+    __IM uint8_t RESERVED58;
+
+    union
+    {
+        __IOM uint8_t VBTWCTLR;        /*!< (@ 0x000004B6) VBATT Wakeup function Control Register                     */
+
+        struct
+        {
+            __IOM uint8_t VWEN : 1;    /*!< [0..0] VBATT wakeup enable                                                */
+            uint8_t            : 7;
+        } VBTWCTLR_b;
+    };
+    __IM uint8_t RESERVED59;
+
+    union
+    {
+        __IOM uint8_t VBTWCH0OTSR;     /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register          */
+
+        struct
+        {
+            uint8_t                  : 1;
+            __IOM uint8_t CH0VCH1TE  : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable                            */
+            __IOM uint8_t CH0VCH2TE  : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable                            */
+            __IOM uint8_t CH0VRTCTE  : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable                         */
+            __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable                            */
+            __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable                        */
+            uint8_t                  : 2;
+        } VBTWCH0OTSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTWCH1OTSR;        /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register          */
+
+        struct
+        {
+            __IOM uint8_t CH1VCH0TE  : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable                            */
+            uint8_t                  : 1;
+            __IOM uint8_t CH1VCH2TE  : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable                            */
+            __IOM uint8_t CH1VRTCTE  : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable                         */
+            __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable                            */
+            __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable                        */
+            uint8_t                  : 2;
+        } VBTWCH1OTSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTWCH2OTSR;        /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register          */
+
+        struct
+        {
+            __IOM uint8_t CH2VCH0TE  : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable                            */
+            __IOM uint8_t CH2VCH1TE  : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable                            */
+            uint8_t                  : 1;
+            __IOM uint8_t CH2VRTCTE  : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable                         */
+            __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable                            */
+            __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable                        */
+            uint8_t                  : 2;
+        } VBTWCH2OTSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTICTLR;         /*!< (@ 0x000004BB) VBATT Input Control Register                               */
+
+        struct
+        {
+            __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable                                                */
+            __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable                                                */
+            __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable                                                */
+            uint8_t                : 5;
+        } VBTICTLR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTOCTLR;          /*!< (@ 0x000004BC) VBATT Output Control Register                              */
+
+        struct
+        {
+            __IOM uint8_t VCH0OEN   : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable                                   */
+            __IOM uint8_t VCH1OEN   : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable                                   */
+            __IOM uint8_t VCH2OEN   : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable                                   */
+            __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection                          */
+            __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection                          */
+            __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection                          */
+            uint8_t                 : 2;
+        } VBTOCTLR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTWTER;         /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register                */
+
+        struct
+        {
+            __IOM uint8_t VCH0E  : 1;  /*!< [0..0] VBATWIO0 Pin Enable                                                */
+            __IOM uint8_t VCH1E  : 1;  /*!< [1..1] VBATWIO1 Pin Enable                                                */
+            __IOM uint8_t VCH2E  : 1;  /*!< [2..2] VBATWIO2 Pin Enable                                                */
+            __IOM uint8_t VRTCIE : 1;  /*!< [3..3] RTC Periodic Signal Enable                                         */
+            __IOM uint8_t VRTCAE : 1;  /*!< [4..4] RTC Alarm Signal Enable                                            */
+            __IOM uint8_t VAGTUE : 1;  /*!< [5..5] AGT(ch1) underflow Signal Enable                                   */
+            uint8_t              : 2;
+        } VBTWTER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTWEGR;         /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register                  */
+
+        struct
+        {
+            __IOM uint8_t VCH0EG : 1;  /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select                         */
+            __IOM uint8_t VCH1EG : 1;  /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select                         */
+            __IOM uint8_t VCH2EG : 1;  /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select                         */
+            uint8_t              : 5;
+        } VBTWEGR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTWFR;          /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register                  */
+
+        struct
+        {
+            __IOM uint8_t VCH0F  : 1;  /*!< [0..0] VBATWIO0 Wakeup Trigger Flag                                       */
+            __IOM uint8_t VCH1F  : 1;  /*!< [1..1] VBATWIO1 Wakeup Trigger Flag                                       */
+            __IOM uint8_t VCH2F  : 1;  /*!< [2..2] VBATWIO2 Wakeup Trigger Flag                                       */
+            __IOM uint8_t VRTCIF : 1;  /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag                             */
+            __IOM uint8_t VRTCAF : 1;  /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag                                */
+            __IOM uint8_t VAGTUF : 1;  /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag                       */
+            uint8_t              : 2;
+        } VBTWFR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTBER;          /*!< (@ 0x000004C0) VBATT Backup Enable Register                               */
+
+        struct
+        {
+            uint8_t            : 3;
+            __IOM uint8_t VBAE : 1;    /*!< [3..3] VBATT backup register access enable bit                            */
+            uint8_t            : 4;
+        } VBTBER_b;
+    };
+    __IM uint8_t  RESERVED60;
+    __IM uint16_t RESERVED61;
+    __IM uint32_t RESERVED62[15];
+
+    union
+    {
+        __IOM uint8_t VBTBKR[512];     /*!< (@ 0x00000500) VBATT Backup Register [0..511]                             */
+
+        struct
+        {
+            __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store
+                                        *   data powered by VBATT.The value of this register is retained
+                                        *   even when VCC is not powered but VBATT is powered.VBTBKR
+                                        *   is initialized by VBATT selected voltage power-on-reset.                  */
+        } VBTBKR_b[512];
+    };
+} R_SYSTEM_Type;                       /*!< Size = 1792 (0x700)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                         R_TSN_CAL                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Temperature Sensor (R_TSN_CAL)
+ */
+
+typedef struct                         /*!< (@ 0x407FB17C) R_TSN_CAL Structure                                        */
+{
+    union
+    {
+        __IM uint32_t TSCDR;           /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register        */
+
+        struct
+        {
+            __IM uint32_t TSCDR : 32;  /*!< [31..0] The 32 bit TSCDR register stores temperature sensor
+                                        *   calibration converted value.                                              */
+        } TSCDR_b;
+    };
+} R_TSN_CAL_Type;                      /*!< Size = 4 (0x4)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                        R_TSN_CTRL                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Temperature Sensor (R_TSN_CTRL)
+ */
+
+typedef struct                         /*!< (@ 0x400F3000) R_TSN_CTRL Structure                                       */
+{
+    union
+    {
+        __IOM uint8_t TSCR;            /*!< (@ 0x00000000) Temperature Sensor Control Register                        */
+
+        struct
+        {
+            uint8_t            : 4;
+            __IOM uint8_t TSOE : 1;    /*!< [4..4] Temperature Sensor Enable                                          */
+            uint8_t            : 2;
+            __IOM uint8_t TSEN : 1;    /*!< [7..7] Temperature Sensor Output Enable                                   */
+        } TSCR_b;
+    };
+} R_TSN_CTRL_Type;                     /*!< Size = 1 (0x1)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_USB_FS0                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief USB 2.0 Module (R_USB_FS0)
+ */
+
+typedef struct                         /*!< (@ 0x40090000) R_USB_FS0 Structure                                        */
+{
+    union
+    {
+        __IOM uint16_t SYSCFG;         /*!< (@ 0x00000000) System Configuration Control Register                      */
+
+        struct
+        {
+            __IOM uint16_t USBE  : 1;  /*!< [0..0] USB Operation Enable                                               */
+            uint16_t             : 2;
+            __IOM uint16_t DMRPU : 1;  /*!< [3..3] D- Line Resistor Control                                           */
+            __IOM uint16_t DPRPU : 1;  /*!< [4..4] D+ Line Resistor Control                                           */
+            __IOM uint16_t DRPD  : 1;  /*!< [5..5] D+/D- Line Resistor Control                                        */
+            __IOM uint16_t DCFM  : 1;  /*!< [6..6] Controller Function Select                                         */
+            uint16_t             : 1;
+            __IOM uint16_t CNEN  : 1;  /*!< [8..8] CNEN Single End Receiver Enable                                    */
+            uint16_t             : 1;
+            __IOM uint16_t SCKE  : 1;  /*!< [10..10] USB Clock Enable                                                 */
+            uint16_t             : 5;
+        } SYSCFG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t BUSWAIT;        /*!< (@ 0x00000002) CPU Bus Wait Register                                      */
+
+        struct
+        {
+            __IOM uint16_t BWAIT : 4;  /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
+                                        *   access cycles)                                                            */
+            uint16_t : 12;
+        } BUSWAIT_b;
+    };
+
+    union
+    {
+        __IM uint16_t SYSSTS0;         /*!< (@ 0x00000004) System Configuration Status Register 0                     */
+
+        struct
+        {
+            __IM uint16_t LNST  : 2;   /*!< [1..0] USB Data Line Status Monitor                                       */
+            __IM uint16_t IDMON : 1;   /*!< [2..2] External ID0 Input Pin Monitor                                     */
+            uint16_t            : 2;
+            __IM uint16_t SOFEA : 1;   /*!< [5..5] SOF Active Monitor While Host Controller Function is
+                                        *   Selected.                                                                 */
+            __IM uint16_t HTACT  : 1;  /*!< [6..6] USB Host Sequencer Status Monitor                                  */
+            uint16_t             : 7;
+            __IM uint16_t OVCMON : 2;  /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe
+                                        *   OCVMON[1] bit indicates the status of the USBHS_OVRCURA
+                                        *   pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
+                                        *   pin.                                                                      */
+        } SYSSTS0_b;
+    };
+
+    union
+    {
+        __IM uint16_t PLLSTA;          /*!< (@ 0x00000006) PLL Status Register                                        */
+
+        struct
+        {
+            __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag                                                      */
+            uint16_t              : 15;
+        } PLLSTA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DVSTCTR0;        /*!< (@ 0x00000008) Device State Control Register 0                            */
+
+        struct
+        {
+            __IM uint16_t RHST     : 3; /*!< [2..0] USB Bus Reset Status                                               */
+            uint16_t               : 1;
+            __IOM uint16_t UACT    : 1; /*!< [4..4] USB Bus Enable                                                     */
+            __IOM uint16_t RESUME  : 1; /*!< [5..5] Resume Output                                                      */
+            __IOM uint16_t USBRST  : 1; /*!< [6..6] USB Bus Reset Output                                               */
+            __IOM uint16_t RWUPE   : 1; /*!< [7..7] Wakeup Detection Enable                                            */
+            __IOM uint16_t WKUP    : 1; /*!< [8..8] Wakeup Output                                                      */
+            __IOM uint16_t VBUSEN  : 1; /*!< [9..9] USB_VBUSEN Output Pin Control                                      */
+            __IOM uint16_t EXICEN  : 1; /*!< [10..10] USB_EXICEN Output Pin Control                                    */
+            __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is
+                                         *   used when switching from device B to device A while in
+                                         *   OTG mode. If the HNPBTOA bit is 1, the internal function
+                                         *   control keeps the suspended state until the HNP processing
+                                         *   ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is
+                                         *   set.                                                                      */
+            uint16_t : 4;
+        } DVSTCTR0_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t TESTMODE;       /*!< (@ 0x0000000C) USB Test Mode Register                                     */
+
+        struct
+        {
+            __IOM uint16_t UTST : 4;   /*!< [3..0] Test Mode                                                          */
+            uint16_t            : 12;
+        } TESTMODE_b;
+    };
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t CFIFO;          /*!< (@ 0x00000014) CFIFO Port Register                                        */
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t CFIFOL;  /*!< (@ 0x00000014) CFIFO Port Register L                                      */
+                __IOM uint8_t  CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL                                     */
+            };
+
+            union
+            {
+                __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H                                      */
+
+                struct
+                {
+                    __IM uint8_t  RESERVED3;
+                    __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH                                     */
+                };
+            };
+        };
+    };
+
+    union
+    {
+        __IOM uint32_t D0FIFO;         /*!< (@ 0x00000018) D0FIFO Port Register                                       */
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t D0FIFOL;  /*!< (@ 0x00000018) D0FIFO Port Register L                                     */
+                __IOM uint8_t  D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL                                    */
+            };
+
+            union
+            {
+                __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H                                     */
+
+                struct
+                {
+                    __IM uint8_t  RESERVED4;
+                    __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH                                    */
+                };
+            };
+        };
+    };
+
+    union
+    {
+        __IOM uint32_t D1FIFO;         /*!< (@ 0x0000001C) D1FIFO Port Register                                       */
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t D1FIFOL;  /*!< (@ 0x0000001C) D1FIFO Port Register L                                     */
+                __IOM uint8_t  D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL                                    */
+            };
+
+            union
+            {
+                __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H                                     */
+
+                struct
+                {
+                    __IM uint8_t  RESERVED5;
+                    __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH                                    */
+                };
+            };
+        };
+    };
+
+    union
+    {
+        __IOM uint16_t CFIFOSEL;        /*!< (@ 0x00000020) CFIFO Port Select Register                                 */
+
+        struct
+        {
+            __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification                               */
+            uint16_t               : 1;
+            __IOM uint16_t ISEL    : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected                   */
+            uint16_t               : 2;
+            __IOM uint16_t BIGEND  : 1; /*!< [8..8] CFIFO Port Endian Control                                          */
+            uint16_t               : 1;
+            __IOM uint16_t MBW     : 2; /*!< [11..10] CFIFO Port Access Bit Width                                      */
+            uint16_t               : 2;
+            __IOM uint16_t REW     : 1; /*!< [14..14] Buffer Pointer Rewind                                            */
+            __IOM uint16_t RCNT    : 1; /*!< [15..15] Read Count Mode                                                  */
+        } CFIFOSEL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t CFIFOCTR;       /*!< (@ 0x00000022) CFIFO Port Control Register                                */
+
+        struct
+        {
+            __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
+                                        *   data.                                                                     */
+            uint16_t            : 1;
+            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
+            __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
+            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
+        } CFIFOCTR_b;
+    };
+    __IM uint32_t RESERVED6;
+
+    union
+    {
+        __IOM uint16_t D0FIFOSEL;       /*!< (@ 0x00000028) D0FIFO Port Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
+            uint16_t               : 4;
+            __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
+            uint16_t               : 1;
+            __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
+            __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
+            __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
+                                         *   Pipe Data is Read                                                         */
+            __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read.                   */
+            __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
+        } D0FIFOSEL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t D0FIFOCTR;      /*!< (@ 0x0000002A) D0FIFO Port Control Register                               */
+
+        struct
+        {
+            __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
+                                        *   data.                                                                     */
+            uint16_t            : 1;
+            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
+            __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
+            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
+        } D0FIFOCTR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t D1FIFOSEL;       /*!< (@ 0x0000002C) D1FIFO Port Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
+            uint16_t               : 4;
+            __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
+            uint16_t               : 1;
+            __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
+            __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
+            __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
+                                         *   Pipe Data is Read                                                         */
+            __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
+            __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
+        } D1FIFOSEL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t D1FIFOCTR;      /*!< (@ 0x0000002E) D1FIFO Port Control Register                               */
+
+        struct
+        {
+            __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
+                                        *   data.                                                                     */
+            uint16_t            : 1;
+            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
+            __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
+            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
+        } D1FIFOCTR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTENB0;        /*!< (@ 0x00000030) Interrupt Enable Register 0                                */
+
+        struct
+        {
+            uint16_t             : 8;
+            __IOM uint16_t BRDYE : 1;  /*!< [8..8] Buffer Ready Interrupt Enable                                      */
+            __IOM uint16_t NRDYE : 1;  /*!< [9..9] Buffer Not Ready Response Interrupt Enable                         */
+            __IOM uint16_t BEMPE : 1;  /*!< [10..10] Buffer Empty Interrupt Enable                                    */
+            __IOM uint16_t CTRE  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Enable               */
+            __IOM uint16_t DVSE  : 1;  /*!< [12..12] Device State Transition Interrupt Enable                         */
+            __IOM uint16_t SOFE  : 1;  /*!< [13..13] Frame Number Update Interrupt Enable                             */
+            __IOM uint16_t RSME  : 1;  /*!< [14..14] Resume Interrupt Enable                                          */
+            __IOM uint16_t VBSE  : 1;  /*!< [15..15] VBUS Interrupt Enable                                            */
+        } INTENB0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTENB1;            /*!< (@ 0x00000032) Interrupt Enable Register 1                                */
+
+        struct
+        {
+            __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable                               */
+            uint16_t                  : 3;
+            __IOM uint16_t SACKE      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable                 */
+            __IOM uint16_t SIGNE      : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable                           */
+            __IOM uint16_t EOFERRE    : 1; /*!< [6..6] EOF Error Detection Interrupt Enable                               */
+            uint16_t                  : 4;
+            __IOM uint16_t ATTCHE     : 1; /*!< [11..11] Connection Detection Interrupt Enable                            */
+            __IOM uint16_t DTCHE      : 1; /*!< [12..12] Disconnection Detection Interrupt Enable                         */
+            uint16_t                  : 1;
+            __IOM uint16_t BCHGE      : 1; /*!< [14..14] USB Bus Change Interrupt Enable                                  */
+            __IOM uint16_t OVRCRE     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable                        */
+        } INTENB1_b;
+    };
+    __IM uint16_t RESERVED7;
+
+    union
+    {
+        __IOM uint16_t BRDYENB;            /*!< (@ 0x00000036) BRDY Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE                                     */
+            uint16_t                  : 6;
+        } BRDYENB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t NRDYENB;            /*!< (@ 0x00000038) NRDY Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE                                     */
+            uint16_t                  : 6;
+        } NRDYENB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t BEMPENB;            /*!< (@ 0x0000003A) BEMP Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE                                     */
+            uint16_t                  : 6;
+        } BEMPENB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t SOFCFG;         /*!< (@ 0x0000003C) SOF Output Configuration Register                          */
+
+        struct
+        {
+            uint16_t                : 4;
+            __IM uint16_t  EDGESTS  : 1; /*!< [4..4] Edge Interrupt Output Status Monitor                               */
+            __IOM uint16_t INTL     : 1; /*!< [5..5] Interrupt Output Sense Select                                      */
+            __IOM uint16_t BRDYM    : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing                                 */
+            uint16_t                : 1;
+            __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select                                    */
+            uint16_t                : 7;
+        } SOFCFG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PHYSET;           /*!< (@ 0x0000003E) PHY Setting Register                                       */
+
+        struct
+        {
+            __IOM uint16_t DIRPD    : 1; /*!< [0..0] Power-Down Control                                                 */
+            __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control                                                  */
+            uint16_t                : 1;
+            __IOM uint16_t CDPEN    : 1; /*!< [3..3] Charging Downstream Port Enable                                    */
+            __IOM uint16_t CLKSEL   : 2; /*!< [5..4] Input System Clock Frequency                                       */
+            uint16_t                : 2;
+            __IOM uint16_t REPSEL   : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle                            */
+            uint16_t                : 1;
+            __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment                 */
+            uint16_t                : 3;
+            __IOM uint16_t HSEB     : 1; /*!< [15..15] CL-Only Mode                                                     */
+        } PHYSET_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTSTS0;        /*!< (@ 0x00000040) Interrupt Status Register 0                                */
+
+        struct
+        {
+            __IM uint16_t  CTSQ  : 3;  /*!< [2..0] Control Transfer Stage                                             */
+            __IOM uint16_t VALID : 1;  /*!< [3..3] USB Request Reception                                              */
+            __IM uint16_t  DVSQ  : 3;  /*!< [6..4] Device State                                                       */
+            __IM uint16_t  VBSTS : 1;  /*!< [7..7] VBUS Input Status                                                  */
+            __IM uint16_t  BRDY  : 1;  /*!< [8..8] Buffer Ready Interrupt Status                                      */
+            __IM uint16_t  NRDY  : 1;  /*!< [9..9] Buffer Not Ready Interrupt Status                                  */
+            __IM uint16_t  BEMP  : 1;  /*!< [10..10] Buffer Empty Interrupt Status                                    */
+            __IOM uint16_t CTRT  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Status               */
+            __IOM uint16_t DVST  : 1;  /*!< [12..12] Device State Transition Interrupt Status                         */
+            __IOM uint16_t SOFR  : 1;  /*!< [13..13] Frame Number Refresh Interrupt Status                            */
+            __IOM uint16_t RESM  : 1;  /*!< [14..14] Resume Interrupt Status                                          */
+            __IOM uint16_t VBINT : 1;  /*!< [15..15] VBUS Interrupt Status                                            */
+        } INTSTS0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTSTS1;           /*!< (@ 0x00000042) Interrupt Status Register 1                                */
+
+        struct
+        {
+            __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status                                  */
+            uint16_t                 : 3;
+            __IOM uint16_t SACK      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status                 */
+            __IOM uint16_t SIGN      : 1; /*!< [5..5] Setup Transaction Error Interrupt Status                           */
+            __IOM uint16_t EOFERR    : 1; /*!< [6..6] EOF Error Detection Interrupt Status                               */
+            uint16_t                 : 1;
+            __IOM uint16_t LPMEND    : 1; /*!< [8..8] LPM Transaction End Interrupt Status                               */
+            __IOM uint16_t L1RSMEND  : 1; /*!< [9..9] L1 Resume End Interrupt Status                                     */
+            uint16_t                 : 1;
+            __IOM uint16_t ATTCH     : 1; /*!< [11..11] ATTCH Interrupt Status                                           */
+            __IOM uint16_t DTCH      : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status                     */
+            uint16_t                 : 1;
+            __IOM uint16_t BCHG      : 1; /*!< [14..14] USB Bus Change Interrupt Status                                  */
+            __IOM uint16_t OVRCR     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status                        */
+        } INTSTS1_b;
+    };
+    __IM uint16_t RESERVED8;
+
+    union
+    {
+        __IOM uint16_t BRDYSTS;           /*!< (@ 0x00000046) BRDY Interrupt Status Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE                                     */
+            uint16_t                 : 6;
+        } BRDYSTS_b;
+    };
+
+    union
+    {
+        __IOM uint16_t NRDYSTS;           /*!< (@ 0x00000048) NRDY Interrupt Status Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE                                     */
+            uint16_t                 : 6;
+        } NRDYSTS_b;
+    };
+
+    union
+    {
+        __IOM uint16_t BEMPSTS;           /*!< (@ 0x0000004A) BEMP Interrupt Status Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE                                     */
+            uint16_t                 : 6;
+        } BEMPSTS_b;
+    };
+
+    union
+    {
+        __IOM uint16_t FRMNUM;         /*!< (@ 0x0000004C) Frame Number Register                                      */
+
+        struct
+        {
+            __IM uint16_t FRNM  : 11;  /*!< [10..0] Frame NumberLatest frame number                                   */
+            uint16_t            : 3;
+            __IOM uint16_t CRCE : 1;   /*!< [14..14] Receive Data Error                                               */
+            __IOM uint16_t OVRN : 1;   /*!< [15..15] Overrun/Underrun Detection Status                                */
+        } FRMNUM_b;
+    };
+
+    union
+    {
+        __IOM uint16_t UFRMNUM;        /*!< (@ 0x0000004E) uFrame Number Register                                     */
+
+        struct
+        {
+            __IM uint16_t UFRNM  : 3;  /*!< [2..0] MicroframeIndicate the microframe number.                          */
+            uint16_t             : 12;
+            __IOM uint16_t DVCHG : 1;  /*!< [15..15] Device State Change                                              */
+        } UFRMNUM_b;
+    };
+
+    union
+    {
+        __IOM uint16_t USBADDR;           /*!< (@ 0x00000050) USB Address Register                                       */
+
+        struct
+        {
+            __IM uint16_t USBADDR : 7;    /*!< [6..0] USB Address In device controller mode, these flags indicate
+                                           *   the USB address assigned by the host when the USBHS processed
+                                           *   the SET_ADDRESS request successfully.                                     */
+            uint16_t                 : 1;
+            __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery                                                   */
+            uint16_t                 : 5;
+        } USBADDR_b;
+    };
+    __IM uint16_t RESERVED9;
+
+    union
+    {
+        __IOM uint16_t USBREQ;                /*!< (@ 0x00000054) USB Request Type Register                                  */
+
+        struct
+        {
+            __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType
+                                               *   value.                                                                    */
+            __IOM uint16_t BREQUEST : 8;      /*!< [15..8] RequestThese bits store the USB request bRequest value.           */
+        } USBREQ_b;
+    };
+
+    union
+    {
+        __IOM uint16_t USBVAL;          /*!< (@ 0x00000056) USB Request Value Register                                 */
+
+        struct
+        {
+            __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value.                */
+        } USBVAL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t USBINDX;         /*!< (@ 0x00000058) USB Request Index Register                                 */
+
+        struct
+        {
+            __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value.               */
+        } USBINDX_b;
+    };
+
+    union
+    {
+        __IOM uint16_t USBLENG;          /*!< (@ 0x0000005A) USB Request Length Register                                */
+
+        struct
+        {
+            __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value.             */
+        } USBLENG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DCPCFG;         /*!< (@ 0x0000005C) DCP Configuration Register                                 */
+
+        struct
+        {
+            uint16_t              : 4;
+            __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
+            uint16_t              : 2;
+            __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
+            __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
+            uint16_t              : 7;
+        } DCPCFG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DCPMAXP;        /*!< (@ 0x0000005E) DCP Maximum Packet Size Register                           */
+
+        struct
+        {
+            __IOM uint16_t MXPS : 7;   /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount
+                                        *   of data (maximum packet size) in payloads for the DCP.                    */
+            uint16_t              : 5;
+            __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
+        } DCPMAXP_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DCPCTR;           /*!< (@ 0x00000060) DCP Control Register                                       */
+
+        struct
+        {
+            __IOM uint16_t PID      : 2; /*!< [1..0] Response PID                                                       */
+            __IOM uint16_t CCPL     : 1; /*!< [2..2] Control Transfer End Enable                                        */
+            uint16_t                : 2;
+            __IM uint16_t  PBUSY    : 1; /*!< [5..5] Pipe Busy                                                          */
+            __IM uint16_t  SQMON    : 1; /*!< [6..6] Sequence Toggle Bit Monitor                                        */
+            __IOM uint16_t SQSET    : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
+            __IOM uint16_t SQCLR    : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
+            uint16_t                : 2;
+            __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear                                                  */
+            uint16_t                : 2;
+            __IOM uint16_t SUREQ    : 1; /*!< [14..14] Setup Token Transmission                                         */
+            __IM uint16_t  BSTS     : 1; /*!< [15..15] Buffer Status                                                    */
+        } DCPCTR_b;
+    };
+    __IM uint16_t RESERVED10;
+
+    union
+    {
+        __IOM uint16_t PIPESEL;         /*!< (@ 0x00000064) Pipe Window Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select                                                 */
+            uint16_t               : 12;
+        } PIPESEL_b;
+    };
+    __IM uint16_t RESERVED11;
+
+    union
+    {
+        __IOM uint16_t PIPECFG;        /*!< (@ 0x00000068) Pipe Configuration Register                                */
+
+        struct
+        {
+            __IOM uint16_t EPNUM : 4;  /*!< [3..0] Endpoint NumberThese bits specify the endpoint number
+                                        *   for the selected pipe.Setting 0000b means unused pipe.                    */
+            __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
+            uint16_t              : 2;
+            __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
+            uint16_t              : 1;
+            __IOM uint16_t DBLB   : 1; /*!< [9..9] Double Buffer Mode                                                 */
+            __IOM uint16_t BFRE   : 1; /*!< [10..10] BRDY Interrupt Operation Specification                           */
+            uint16_t              : 3;
+            __IOM uint16_t TYPE   : 2; /*!< [15..14] Transfer Type                                                    */
+        } PIPECFG_b;
+    };
+    __IM uint16_t RESERVED12;
+
+    union
+    {
+        __IOM uint16_t PIPEMAXP;       /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register                          */
+
+        struct
+        {
+            __IOM uint16_t MXPS : 9;   /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to
+                                        *   256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes
+                                        *   (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and
+                                        *   [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to
+                                        *   64 bytes (040h) (Bits [8:7] are not provided.)                            */
+            uint16_t              : 3;
+            __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
+        } PIPEMAXP_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PIPEPERI;       /*!< (@ 0x0000006E) Pipe Cycle Control Register                                */
+
+        struct
+        {
+            __IOM uint16_t IITV : 3;   /*!< [2..0] Interval Error Detection IntervalSpecifies the interval
+                                        *   error detection timing for the selected pipe in terms of
+                                        *   frames, which is expressed as nth power of 2.                             */
+            uint16_t            : 9;
+            __IOM uint16_t IFIS : 1;   /*!< [12..12] Isochronous IN Buffer Flush                                      */
+            uint16_t            : 3;
+        } PIPEPERI_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PIPE_CTR[9];    /*!< (@ 0x00000070) Pipe [0..8] Control Register                               */
+
+        struct
+        {
+            __IOM uint16_t PID    : 2; /*!< [1..0] Response PID                                                       */
+            uint16_t              : 3;
+            __IM uint16_t  PBUSY  : 1; /*!< [5..5] Pipe Busy                                                          */
+            __IM uint16_t  SQMON  : 1; /*!< [6..6] Sequence Toggle Bit Confirmation                                   */
+            __IOM uint16_t SQSET  : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
+            __IOM uint16_t SQCLR  : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
+            __IOM uint16_t ACLRM  : 1; /*!< [9..9] Auto Buffer Clear Mode                                             */
+            __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode                                               */
+            uint16_t              : 1;
+            __IM uint16_t CSSTS   : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
+                                        *   Split Transaction of the relevant pipe                                    */
+            __IOM uint16_t CSCLR : 1;  /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
+                                        *   the CSSTS bit of the relevant pipe                                        */
+            __IM uint16_t INBUFM : 1;  /*!< [14..14] Transmit Buffer Monitor                                          */
+            __IM uint16_t BSTS   : 1;  /*!< [15..15] Buffer Status                                                    */
+        } PIPE_CTR_b[9];
+    };
+    __IM uint16_t                RESERVED13;
+    __IM uint32_t                RESERVED14[3];
+    __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers                         */
+    __IM uint32_t                RESERVED15[3];
+
+    union
+    {
+        __IOM uint16_t USBBCCTRL0;         /*!< (@ 0x000000B0) BC Control Register 0                                      */
+
+        struct
+        {
+            __IOM uint16_t RPDME0     : 1; /*!< [0..0] D- Pin Pull-Down Control                                           */
+            __IOM uint16_t IDPSRCE0   : 1; /*!< [1..1] D+ Pin IDPSRC Output Control                                       */
+            __IOM uint16_t IDMSINKE0  : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control         */
+            __IOM uint16_t VDPSRCE0   : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control                               */
+            __IOM uint16_t IDPSINKE0  : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control         */
+            __IOM uint16_t VDMSRCE0   : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control                               */
+            uint16_t                  : 1;
+            __IOM uint16_t BATCHGE0   : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control           */
+            __IM uint16_t  CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status                                */
+            __IM uint16_t  PDDETSTS0  : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status                                */
+            uint16_t                  : 6;
+        } USBBCCTRL0_b;
+    };
+    __IM uint16_t RESERVED16;
+    __IM uint32_t RESERVED17[4];
+
+    union
+    {
+        __IOM uint16_t UCKSEL;          /*!< (@ 0x000000C4) USB Clock Selection Register                               */
+
+        struct
+        {
+            __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection                                                */
+            uint16_t               : 15;
+        } UCKSEL_b;
+    };
+    __IM uint16_t RESERVED18;
+    __IM uint32_t RESERVED19;
+
+    union
+    {
+        __IOM uint16_t USBMC;           /*!< (@ 0x000000CC) USB Module Control Register                                */
+
+        struct
+        {
+            __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control                  */
+            uint16_t               : 6;
+            __IOM uint16_t VDCEN   : 1; /*!< [7..7] USB Regulator On/Off Control                                       */
+            uint16_t               : 8;
+        } USBMC_b;
+    };
+    __IM uint16_t RESERVED20;
+
+    union
+    {
+        __IOM uint16_t DEVADD[10];     /*!< (@ 0x000000D0) Device Address Configuration Register                      */
+
+        struct
+        {
+            uint16_t               : 6;
+            __IOM uint16_t USBSPD  : 2; /*!< [7..6] Transfer Speed of Communication Target Device                      */
+            __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port                          */
+            __IOM uint16_t UPPHUB  : 4; /*!< [14..11] Communication Target Connecting Hub Register                     */
+            uint16_t               : 1;
+        } DEVADD_b[10];
+    };
+    __IM uint32_t RESERVED21[3];
+
+    union
+    {
+        __IOM uint32_t PHYSLEW;         /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register                        */
+
+        struct
+        {
+            __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00                                 */
+            __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01                                 */
+            __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00                                 */
+            __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01                                 */
+            uint32_t               : 28;
+        } PHYSLEW_b;
+    };
+    __IM uint32_t RESERVED22[3];
+
+    union
+    {
+        __IOM uint16_t LPCTRL;         /*!< (@ 0x00000100) Low Power Control Register                                 */
+
+        struct
+        {
+            uint16_t             : 7;
+            __IOM uint16_t HWUPM : 1;  /*!< [7..7] Resume Return Mode Setting                                         */
+            uint16_t             : 8;
+        } LPCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t LPSTS;          /*!< (@ 0x00000102) Low Power Status Register                                  */
+
+        struct
+        {
+            uint16_t                : 14;
+            __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control                                            */
+            uint16_t                : 1;
+        } LPSTS_b;
+    };
+    __IM uint32_t RESERVED23[15];
+
+    union
+    {
+        __IOM uint16_t BCCTRL;           /*!< (@ 0x00000140) Battery Charging Control Register                          */
+
+        struct
+        {
+            __IOM uint16_t IDPSRCE  : 1; /*!< [0..0] IDPSRC Control                                                     */
+            __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control                                                    */
+            __IOM uint16_t VDPSRCE  : 1; /*!< [2..2] VDPSRC Control                                                     */
+            __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control                                                    */
+            __IOM uint16_t VDMSRCE  : 1; /*!< [4..4] VDMSRC Control                                                     */
+            __IOM uint16_t DCPMODE  : 1; /*!< [5..5] DCP Mode Control                                                   */
+            uint16_t                : 2;
+            __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status                                                      */
+            __IM uint16_t PDDETSTS  : 1; /*!< [9..9] PDDET Status                                                       */
+            uint16_t                : 6;
+        } BCCTRL_b;
+    };
+    __IM uint16_t RESERVED24;
+
+    union
+    {
+        __IOM uint16_t PL1CTRL1;         /*!< (@ 0x00000144) Function L1 Control Register 1                             */
+
+        struct
+        {
+            __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable                                                 */
+            __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode                                                   */
+            __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
+                                          *   only when the L1RESPMD[1:0] value is 2'b11.                               */
+            __IM uint16_t DVSQ : 4;      /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
+                                          *   the L1 state together with the device state bits DVSQ[2:0].               */
+            __IOM uint16_t HIRDTHR : 4;  /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
+                                          *   value used for L1NEGOMD.The format is the same as the HIRD
+                                          *   field in HL1CTRL.                                                         */
+            uint16_t               : 2;
+            __IOM uint16_t L1EXTMD : 1;  /*!< [14..14] PHY Control Mode at L1 Return                                    */
+            uint16_t               : 1;
+        } PL1CTRL1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PL1CTRL2;       /*!< (@ 0x00000146) Function L1 Control Register 2                             */
+
+        struct
+        {
+            uint16_t               : 8;
+            __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor                                                */
+            __IOM uint16_t RWEMON  : 1; /*!< [12..12] RWE Value Monitor                                                */
+            uint16_t               : 3;
+        } PL1CTRL2_b;
+    };
+
+    union
+    {
+        __IOM uint16_t HL1CTRL1;         /*!< (@ 0x00000148) Host L1 Control Register 1                                 */
+
+        struct
+        {
+            __IOM uint16_t L1REQ    : 1; /*!< [0..0] L1 Transition Request                                              */
+            __IM uint16_t  L1STATUS : 2; /*!< [2..1] L1 Request Completion Status                                       */
+            uint16_t                : 13;
+        } HL1CTRL1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t HL1CTRL2;       /*!< (@ 0x0000014A) Host L1 Control Register 2                                 */
+
+        struct
+        {
+            __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
+                                        *   be set in the ADDR field of LPM token.                                    */
+            uint16_t             : 4;
+            __IOM uint16_t HIRD  : 4;  /*!< [11..8] LPM Token HIRD                                                    */
+            __IOM uint16_t L1RWE : 1;  /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
+                                        *   value to be set in the RWE field of LPM token.                            */
+            uint16_t            : 2;
+            __IOM uint16_t BESL : 1;   /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
+                                        *   period at the time of L1 Resume.                                          */
+        } HL1CTRL2_b;
+    };
+    __IM uint32_t RESERVED25[5];
+
+    union
+    {
+        __IM uint32_t DPUSR0R;         /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
+                                        *                  Register                                                   */
+
+        struct
+        {
+            uint32_t              : 20;
+            __IM uint32_t DOVCAHM : 1;  /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
+                                         *   HS side of USB port.                                                      */
+            __IM uint32_t DOVCBHM : 1;  /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
+                                         *   HS side of USB port.                                                      */
+            uint32_t               : 1;
+            __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
+                                         *   of USB port.                                                              */
+            uint32_t : 8;
+        } DPUSR0R_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DPUSR1R;        /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register         */
+
+        struct
+        {
+            uint32_t                : 4;
+            __IOM uint32_t DOVCAHE  : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear                                     */
+            __IOM uint32_t DOVCBHE  : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear                                     */
+            uint32_t                : 1;
+            __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear                                        */
+            uint32_t                : 12;
+            __IM uint32_t DOVCAH    : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source               */
+            __IM uint32_t DOVCBH    : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source               */
+            uint32_t                : 1;
+            __IM uint32_t DVBSTSH   : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source                  */
+            uint32_t                : 8;
+        } DPUSR1R_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DPUSR2R;        /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register         */
+
+        struct
+        {
+            __IM uint16_t DPINT : 1;   /*!< [0..0] Indication of Return from DP Interrupt Source                      */
+            __IM uint16_t DMINT : 1;   /*!< [1..1] Indication of Return from DM Interrupt Source                      */
+            uint16_t            : 2;
+            __IM uint16_t DPVAL : 1;   /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
+                                        *   port.                                                                     */
+            __IM uint16_t DMVAL : 1;   /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
+                                        *   port.                                                                     */
+            uint16_t              : 2;
+            __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear                                          */
+            __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear                                          */
+            uint16_t              : 6;
+        } DPUSR2R_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DPUSRCR;          /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register           */
+
+        struct
+        {
+            __IOM uint16_t FIXPHY   : 1; /*!< [0..0] USB Transceiver Control Fix                                        */
+            __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL                                */
+            uint16_t                : 14;
+        } DPUSRCR_b;
+    };
+    __IM uint32_t RESERVED26[165];
+
+    union
+    {
+        __IOM uint32_t DPUSR0R_FS;      /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin
+                                         *                  Monitor Register                                           */
+
+        struct
+        {
+            __IOM uint32_t SRPC0   : 1; /*!< [0..0] USB Single End Receiver Control                                    */
+            __IOM uint32_t RPUE0   : 1; /*!< [1..1] DP Pull-Up Resistor Control                                        */
+            uint32_t               : 1;
+            __IOM uint32_t DRPD0   : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control                                   */
+            __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix                                         */
+            uint32_t               : 11;
+            __IM uint32_t DP0      : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB.           */
+            __IM uint32_t DM0      : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB.             */
+            uint32_t               : 2;
+            __IM uint32_t DOVCA0   : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal
+                                         *   of the USB.                                                               */
+            __IM uint32_t DOVCB0 : 1;   /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal
+                                         *   of the USB.                                                               */
+            uint32_t              : 1;
+            __IM uint32_t DVBSTS0 : 1;  /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the
+                                         *   USB.                                                                      */
+            uint32_t : 8;
+        } DPUSR0R_FS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DPUSR1R_FS;        /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt
+                                           *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t DPINTE0   : 1; /*!< [0..0] USB DP Interrupt Enable/Clear                                      */
+            __IOM uint32_t DMINTE0   : 1; /*!< [1..1] USB DM Interrupt Enable/Clear                                      */
+            uint32_t                 : 2;
+            __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear                                 */
+            __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear                                 */
+            uint32_t                 : 1;
+            __IOM uint32_t DVBSE0    : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear                                    */
+            uint32_t                 : 8;
+            __IM uint32_t DPINT0     : 1; /*!< [16..16] USB DP Interrupt Source Recovery                                 */
+            __IM uint32_t DMINT0     : 1; /*!< [17..17] USB DM Interrupt Source Recovery                                 */
+            uint32_t                 : 2;
+            __IM uint32_t DOVRCRA0   : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery                            */
+            __IM uint32_t DOVRCRB0   : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery                            */
+            uint32_t                 : 1;
+            __IM uint32_t DVBINT0    : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery                               */
+            uint32_t                 : 8;
+        } DPUSR1R_FS_b;
+    };
+} R_USB_FS0_Type;                         /*!< Size = 1032 (0x408)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                           R_WDT                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Watchdog Timer (R_WDT)
+ */
+
+typedef struct                         /*!< (@ 0x40083400) R_WDT Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t WDTRR;           /*!< (@ 0x00000000) WDT Refresh Register                                       */
+
+        struct
+        {
+            __IOM uint8_t WDTRR : 8;   /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter
+                                        *   of the WDT.                                                               */
+        } WDTRR_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t WDTCR;          /*!< (@ 0x00000002) WDT Control Register                                       */
+
+        struct
+        {
+            __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
+            uint16_t            : 2;
+            __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
+            __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
+            uint16_t            : 2;
+            __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
+            uint16_t            : 2;
+        } WDTCR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t WDTSR;           /*!< (@ 0x00000004) WDT Status Register                                        */
+
+        struct
+        {
+            __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
+            __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
+            __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
+        } WDTSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t WDTRCR;          /*!< (@ 0x00000006) WDT Reset Control Register                                 */
+
+        struct
+        {
+            uint8_t               : 7;
+            __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
+        } WDTRCR_b;
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        __IOM uint8_t WDTCSTPR;        /*!< (@ 0x00000008) WDT Count Stop Control Register                            */
+
+        struct
+        {
+            uint8_t              : 7;
+            __IOM uint8_t SLCSTP : 1;  /*!< [7..7] Sleep-Mode Count Stop Control                                      */
+        } WDTCSTPR_b;
+    };
+    __IM uint8_t  RESERVED2;
+    __IM uint16_t RESERVED3;
+} R_WDT_Type;                          /*!< Size = 12 (0xc)                                                           */
+
+/* =========================================================================================================================== */
+/* ================                                           R_TZF                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief TrustZone Filter (R_TZF)
+ */
+
+typedef struct                         /*!< (@ 0x40000E00) R_TZF Structure                                            */
+{
+    union
+    {
+        __IOM uint16_t TZFOAD;         /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register        */
+
+        struct
+        {
+            __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
+            uint16_t           : 7;
+            __OM uint16_t KEY  : 8;    /*!< [15..8] KeyCode                                                           */
+        } TZFOAD_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t TZFPT;           /*!< (@ 0x00000004) TrustZone Filter Protect Register                          */
+
+        struct
+        {
+            __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
+            uint16_t               : 7;
+            __OM uint16_t KEY      : 8; /*!< [15..8] KeyCode                                                           */
+        } TZFPT_b;
+    };
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2[94];
+
+    union
+    {
+        __IOM uint32_t TZFSAR;         /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register             */
+
+        struct
+        {
+            __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter              */
+            uint32_t              : 31;
+        } TZFSAR_b;
+    };
+} R_TZF_Type;                          /*!< Size = 388 (0x184)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CACHE                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief R_CACHE (R_CACHE)
+ */
+
+typedef struct                         /*!< (@ 0x40007000) R_CACHE Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t CCACTL;         /*!< (@ 0x00000000) C-Cache Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ENC : 1;    /*!< [0..0] C-Cache Enable                                                     */
+            uint32_t           : 31;
+        } CCACTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCAFCT;         /*!< (@ 0x00000004) C-Cache Flush Control Register                             */
+
+        struct
+        {
+            __IOM uint32_t FC : 1;     /*!< [0..0] C-Cache Flush                                                      */
+            uint32_t          : 31;
+        } CCAFCT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCALCF;         /*!< (@ 0x00000008) C-Cache Line Configuration Register                        */
+
+        struct
+        {
+            __IOM uint32_t CC : 2;     /*!< [1..0] C-Cache Line Size                                                  */
+            uint32_t          : 30;
+        } CCALCF_b;
+    };
+    __IM uint32_t RESERVED[13];
+
+    union
+    {
+        __IOM uint32_t SCACTL;         /*!< (@ 0x00000040) S-Cache Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ENS : 1;    /*!< [0..0] S-Cache Enable                                                     */
+            uint32_t           : 31;
+        } SCACTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SCAFCT;         /*!< (@ 0x00000044) S-Cache Flush Control Register                             */
+
+        struct
+        {
+            __IOM uint32_t FS : 1;     /*!< [0..0] S-Cache Flush                                                      */
+            uint32_t          : 31;
+        } SCAFCT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SCALCF;         /*!< (@ 0x00000048) S-Cache Line Configuration Register                        */
+
+        struct
+        {
+            __IOM uint32_t CS : 2;     /*!< [1..0] S-Cache Line Size                                                  */
+            uint32_t          : 30;
+        } SCALCF_b;
+    };
+    __IM uint32_t RESERVED1[109];
+
+    union
+    {
+        __IOM uint32_t CAPOAD;         /*!< (@ 0x00000200) Cache Parity Error Operation After Detection
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t OAD : 1;    /*!< [0..0] Operation after Detection                                          */
+            uint32_t           : 31;
+        } CAPOAD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CAPRCR;         /*!< (@ 0x00000204) Cache Protection Register                                  */
+
+        struct
+        {
+            __IOM uint32_t PRCR : 1;   /*!< [0..0] Register Write Control                                             */
+            __IOM uint32_t KW   : 7;   /*!< [7..1] Write key code                                                     */
+            uint32_t            : 24;
+        } CAPRCR_b;
+    };
+} R_CACHE_Type;                        /*!< Size = 520 (0x208)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CPSCU                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief CPU System Security Control Unit (R_CPSCU)
+ */
+
+typedef struct                           /*!< (@ 0x40008000) R_CPSCU Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t CSAR;             /*!< (@ 0x00000000) Cache Security Attribution Register                        */
+
+        struct
+        {
+            __IOM uint32_t CACHESA  : 1; /*!< [0..0] Security Attributes of Registers for Cache Control                 */
+            __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration      */
+            __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error                   */
+            uint32_t                : 29;
+        } CSAR_b;
+    };
+    __IM uint32_t RESERVED[3];
+
+    union
+    {
+        __IOM uint32_t SRAMSAR;         /*!< (@ 0x00000010) SRAM Security Attribution Register                         */
+
+        struct
+        {
+            __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection               */
+            __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection
+                                         *   2                                                                         */
+            __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation                  */
+            uint32_t               : 29;
+        } SRAMSAR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STBRAMSAR;       /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register           */
+
+        struct
+        {
+            __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM                 */
+            uint32_t               : 28;
+        } STBRAMSAR_b;
+    };
+    __IM uint32_t RESERVED1[6];
+
+    union
+    {
+        __IOM uint32_t DTCSAR;          /*!< (@ 0x00000030) DTC Controller Security Attribution Register               */
+
+        struct
+        {
+            __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution                                           */
+            uint32_t               : 31;
+        } DTCSAR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DMACSAR;         /*!< (@ 0x00000034) DMAC Controller Security Attribution Register              */
+
+        struct
+        {
+            __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution                                         */
+            uint32_t               : 31;
+        } DMACSAR_b;
+    };
+    __IM uint32_t RESERVED2[2];
+
+    union
+    {
+        __IOM uint32_t ICUSARA;           /*!< (@ 0x00000040) ICU Security Attribution Register A                        */
+
+        struct
+        {
+            __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers         */
+            uint32_t                : 16;
+        } ICUSARA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ICUSARB;        /*!< (@ 0x00000044) ICU Security Attribution Register B                        */
+
+        struct
+        {
+            __IOM uint32_t SANMI : 1;  /*!< [0..0] Security Attributes of nonmaskable interrupt                       */
+            uint32_t             : 31;
+        } ICUSARB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ICUSARC;         /*!< (@ 0x00000048) ICU Security Attribution Register C                        */
+
+        struct
+        {
+            __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel                  */
+            uint32_t               : 24;
+        } ICUSARC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ICUSARD;          /*!< (@ 0x0000004C) ICU Security Attribution Register D                        */
+
+        struct
+        {
+            __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0                        */
+            uint32_t                : 31;
+        } ICUSARD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ICUSARE;        /*!< (@ 0x00000050) ICU Security Attribution Register E                        */
+
+        struct
+        {
+            uint32_t                   : 16;
+            __IOM uint32_t SAIWDTWUP   : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16                 */
+            uint32_t                   : 1;
+            __IOM uint32_t SALVD1WUP   : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18                 */
+            __IOM uint32_t SALVD2WUP   : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19                 */
+            __IOM uint32_t SAVBATTWUP  : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20                 */
+            uint32_t                   : 3;
+            __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24                 */
+            __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25                 */
+            uint32_t                   : 1;
+            __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27                 */
+            __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28                 */
+            __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29                 */
+            __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30                 */
+            __IOM uint32_t SAIIC0WUP   : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31                 */
+        } ICUSARE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ICUSARF;              /*!< (@ 0x00000054) ICU Security Attribution Register F                        */
+
+        struct
+        {
+            __IOM uint32_t SAAGT3UDWUP  : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0                    */
+            __IOM uint32_t SAAGT3CAWUP  : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1                    */
+            __IOM uint32_t SAAGT3CBWUP  : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2                    */
+            __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3                    */
+            uint32_t                    : 4;
+            __IOM uint32_t SAULP0UWUP   : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8                    */
+            __IOM uint32_t SAULP0AWUP   : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9                    */
+            __IOM uint32_t SAULP0BWUP   : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10                 */
+            __IOM uint32_t SAI3CWUP     : 1; /*!< [11..11] Security Attributes of registers for WUPEN1.b 11                 */
+            __IOM uint32_t SAULP1UWUP   : 1; /*!< [12..12] Security Attributes of registers for WUPEN1.b 12                 */
+            __IOM uint32_t SAULP1AWUP   : 1; /*!< [13..13] Security Attributes of registers for WUPEN1.b 13                 */
+            __IOM uint32_t SAULP1BWUP   : 1; /*!< [14..14] Security Attributes of registers for WUPEN1.b 14                 */
+            uint32_t                    : 17;
+        } ICUSARF_b;
+    };
+    __IM uint32_t RESERVED3[6];
+
+    union
+    {
+        __IOM uint32_t ICUSARG;           /*!< (@ 0x00000070) ICU Security Attribution Register G                        */
+
+        struct
+        {
+            __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0            */
+        } ICUSARG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ICUSARH;           /*!< (@ 0x00000074) ICU Security Attribution Register H                        */
+
+        struct
+        {
+            __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32           */
+        } ICUSARH_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ICUSARI;           /*!< (@ 0x00000078) ICU Security Attribution Register I                        */
+
+        struct
+        {
+            __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64           */
+        } ICUSARI_b;
+    };
+    __IM uint32_t RESERVED4[33];
+
+    union
+    {
+        __IOM uint32_t BUSSARA;        /*!< (@ 0x00000100) Bus Security Attribution Register A                        */
+
+        struct
+        {
+            __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0                                        */
+            uint32_t              : 31;
+        } BUSSARA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BUSSARB;        /*!< (@ 0x00000104) Bus Security Attribution Register B                        */
+
+        struct
+        {
+            __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0                                        */
+            uint32_t              : 31;
+        } BUSSARB_b;
+    };
+    __IM uint32_t RESERVED5[10];
+
+    union
+    {
+        __IOM uint32_t MMPUSARA;         /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution
+                                          *                  Register A                                                 */
+
+        struct
+        {
+            __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7)                           */
+            uint32_t                : 24;
+        } MMPUSARA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMPUSARB;         /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution
+                                          *                  Register B                                                 */
+
+        struct
+        {
+            __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution                                        */
+            uint32_t                : 31;
+        } MMPUSARB_b;
+    };
+    __IM uint32_t RESERVED6[26];
+
+    union
+    {
+        __IOM uint32_t DMASARA;          /*!< (@ 0x000001A0) ICU Security Attribution Register C                        */
+
+        struct
+        {
+            __IOM uint32_t DMASARAn : 8; /*!< [7..0] Security attributes of output and registers for DMAC
+                                          *   channel                                                                   */
+            uint32_t : 24;
+        } DMASARA_b;
+    };
+    __IM uint32_t RESERVED7[3];
+
+    union
+    {
+        __IOM uint32_t CPUDSAR;         /*!< (@ 0x000001B0) CPU Debug Security Attribution Register                    */
+
+        struct
+        {
+            __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0                                   */
+            uint32_t               : 31;
+        } CPUDSAR_b;
+    };
+    __IM uint32_t RESERVED8[275];
+
+    union
+    {
+        __IOM uint32_t TEVTRCR;        /*!< (@ 0x00000600) Trusted Event Route Control Register                       */
+
+        struct
+        {
+            __IOM uint32_t TEVTE : 1;  /*!< [0..0] Trusted Event Route Control Register for IELSRn, DELSRn
+                                        *   and ELCSRn                                                                */
+            uint32_t : 31;
+        } TEVTRCR_b;
+    };
+} R_CPSCU_Type;                        /*!< Size = 1540 (0x604)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                           R_CEC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Consumer Electronics Control (R_CEC)
+ */
+
+typedef struct                         /*!< (@ 0x400AC000) R_CEC Structure                                            */
+{
+    union
+    {
+        __IOM uint16_t CADR;           /*!< (@ 0x00000000) CEC Local Address Setting Register                         */
+
+        struct
+        {
+            __IOM uint16_t ADR00 : 1;  /*!< [0..0] Local Address at Address 0 (TV)                                    */
+            __IOM uint16_t ADR01 : 1;  /*!< [1..1] Local Address Setting at Address 1 (recording device
+                                        *   1)                                                                        */
+            __IOM uint16_t ADR02 : 1;  /*!< [2..2] Local Address Setting at Address 2 (recording device
+                                        *   2)                                                                        */
+            __IOM uint16_t ADR03 : 1;  /*!< [3..3] Local Address Setting at Address 3 (tuner 1)                       */
+            __IOM uint16_t ADR04 : 1;  /*!< [4..4] Local Address Setting at Address 4 (playback device 1)             */
+            __IOM uint16_t ADR05 : 1;  /*!< [5..5] Local Address Setting at Address 5 (audio system)                  */
+            __IOM uint16_t ADR06 : 1;  /*!< [6..6] Local Address Setting at Address 6 (tuner 2)                       */
+            __IOM uint16_t ADR07 : 1;  /*!< [7..7] Local Address Setting at Address 7 (tuner 3)                       */
+            __IOM uint16_t ADR08 : 1;  /*!< [8..8] Local Address Setting at Address 8 (playback device 2)             */
+            __IOM uint16_t ADR09 : 1;  /*!< [9..9] Local Address Setting at Address 9 (recording device
+                                        *   3)                                                                        */
+            __IOM uint16_t ADR10 : 1;  /*!< [10..10] Local Address Setting at Address 10 (tuner 4)                    */
+            __IOM uint16_t ADR11 : 1;  /*!< [11..11] Local Address Setting at Address 11 (playback device
+                                        *   3)                                                                        */
+            __IOM uint16_t ADR12 : 1;  /*!< [12..12] Local Address Setting at Address 12 (reserved)                   */
+            __IOM uint16_t ADR13 : 1;  /*!< [13..13] Local Address Setting at Address 13 (reserved)                   */
+            __IOM uint16_t ADR14 : 1;  /*!< [14..14] Local Address Setting at Address 14 (specific use)               */
+            uint16_t             : 1;
+        } CADR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CECCTL1;         /*!< (@ 0x00000002) CEC Control Register 1                                     */
+
+        struct
+        {
+            __IOM uint8_t SFT   : 2;   /*!< [1..0] Signal-Free Time Data Bit Width Select                             */
+            __IOM uint8_t CESEL : 2;   /*!< [3..2] Communication Complete Interrupt (INTCE) Generation Timing
+                                        *   Select                                                                    */
+            __IOM uint8_t STERRD : 1;  /*!< [4..4] Start Bit Error Detection Select                                   */
+            __IOM uint8_t BLERRD : 1;  /*!< [5..5] Bus Lock Detection Select                                          */
+            __IOM uint8_t CINTMK : 1;  /*!< [6..6] CEC Data Interrupt (INTDA) Generation Select                       */
+            __IOM uint8_t CDFC   : 1;  /*!< [7..7] Digital Filter Select                                              */
+        } CECCTL1_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t STATB;          /*!< (@ 0x00000004) CEC Transmission Start Bit Width Setting Register          */
+
+        struct
+        {
+            __IOM uint16_t STATB : 9;  /*!< [8..0] CEC Transmission Start Bit Width Setting                           */
+            uint16_t             : 7;
+        } STATB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t STATL;          /*!< (@ 0x00000006) CEC Transmission Start Bit Low Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t STATL : 9;  /*!< [8..0] CEC Transmission Start Bit Low Width Setting                       */
+            uint16_t             : 7;
+        } STATL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t LGC0L;          /*!< (@ 0x00000008) CEC Transmission Logical 0 Low Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t LGC0L : 9;  /*!< [8..0] CEC Transmission Logical 0 Low Width Setting                       */
+            uint16_t             : 7;
+        } LGC0L_b;
+    };
+
+    union
+    {
+        __IOM uint16_t LGC1L;          /*!< (@ 0x0000000A) CEC Transmission Logical 1 Low Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t LGC1L : 9;  /*!< [8..0] CEC Transmission Logical 1 Low Width Setting                       */
+            uint16_t             : 7;
+        } LGC1L_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DATB;           /*!< (@ 0x0000000C) CEC Transmission Data Bit Width Setting Register           */
+
+        struct
+        {
+            __IOM uint16_t DATB : 9;   /*!< [8..0] CEC Transmission Data Bit Width Setting                            */
+            uint16_t            : 7;
+        } DATB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t NOMT;           /*!< (@ 0x0000000E) CEC Reception Data Sampling Time Setting Register          */
+
+        struct
+        {
+            __IOM uint16_t NOMT : 9;   /*!< [8..0] CEC Reception Data Sampling Time Setting,                          */
+            uint16_t            : 7;
+        } NOMT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t STATLL;         /*!< (@ 0x00000010) CEC Reception Start Bit Minimum Low Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t STATLL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Low Width Setting                  */
+            uint16_t              : 7;
+        } STATLL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t STATLH;         /*!< (@ 0x00000012) CEC Reception Start Bit Maximum Low Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t STATLH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting                  */
+            uint16_t              : 7;
+        } STATLH_b;
+    };
+
+    union
+    {
+        __IOM uint16_t STATBL;         /*!< (@ 0x00000014) CEC Reception Start Bit Minimum Bit Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t STATBL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Bit Width Setting                  */
+            uint16_t              : 7;
+        } STATBL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t STATBH;         /*!< (@ 0x00000016) CEC Reception Start Bit Maximum Bit Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t STATBH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting                  */
+            uint16_t              : 7;
+        } STATBH_b;
+    };
+
+    union
+    {
+        __IOM uint16_t LGC0LL;         /*!< (@ 0x00000018) CEC Reception Logical 0 Minimum Low Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t LGC0LL : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting                  */
+            uint16_t              : 7;
+        } LGC0LL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t LGC0LH;         /*!< (@ 0x0000001A) CEC Reception Logical 0 Maximum Low Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t LGC0LH : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting                  */
+            uint16_t              : 7;
+        } LGC0LH_b;
+    };
+
+    union
+    {
+        __IOM uint16_t LGC1LL;         /*!< (@ 0x0000001C) CEC Reception Logical 1 Minimum Low Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t LGC1LL : 9; /*!< [8..0] CEC Reception Logical 1 Minimum Low Width Setting                  */
+            uint16_t              : 7;
+        } LGC1LL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t LGC1LH;         /*!< (@ 0x0000001E) CEC Reception Logical 1 Maximum Low Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t LGC1LH : 9; /*!< [8..0] CEC Reception Logical 1 Maximum Low Width Setting                  */
+            uint16_t              : 7;
+        } LGC1LH_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DATBL;          /*!< (@ 0x00000020) CEC Reception Data Bit Minimum Bit Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t DATBL : 9;  /*!< [8..0] CEC Reception Data Bit Minimum Bit Width Setting                   */
+            uint16_t             : 7;
+        } DATBL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DATBH;          /*!< (@ 0x00000022) CEC Reception Data Bit Maximum Bit Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t DATBH : 9;  /*!< [8..0] CEC Reception Data Bit Maximum Bit Width Setting                   */
+            uint16_t             : 7;
+        } DATBH_b;
+    };
+
+    union
+    {
+        __IOM uint16_t NOMP;           /*!< (@ 0x00000024) CEC Data Bit Reference Width Setting Register              */
+
+        struct
+        {
+            __IOM uint16_t NOMP : 9;   /*!< [8..0] CEC Data Bit Reference Width Setting                               */
+            uint16_t            : 7;
+        } NOMP_b;
+    };
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint8_t CECEXMD;         /*!< (@ 0x00000028) CEC Extension Mode Register                                */
+
+        struct
+        {
+            uint8_t                  : 4;
+            __IOM uint8_t LERPLEN    : 1; /*!< [4..4] Pulse Output Function Enable by Long Bit Width Error               */
+            __IOM uint8_t RERCVEN    : 1; /*!< [5..5] Start Detection Reception Restart Enable                           */
+            uint8_t                  : 1;
+            __IOM uint8_t RCVINTDSEL : 1; /*!< [7..7] INTDA Reception Interrupt Timing Change                            */
+        } CECEXMD_b;
+    };
+    __IM uint8_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t CECEXMON;        /*!< (@ 0x0000002A) CEC Extension Monitor Register                             */
+
+        struct
+        {
+            __IM uint8_t CECLNMON : 1; /*!< [0..0] CEC Line Monitor                                                   */
+            __IM uint8_t ACKF     : 1; /*!< [1..1] ACK Flag                                                           */
+            uint8_t               : 6;
+        } CECEXMON_b;
+    };
+    __IM uint8_t  RESERVED3;
+    __IM uint16_t RESERVED4[10];
+    __IOM uint8_t CTXD;                /*!< (@ 0x00000040) CEC Transmission Buffer Register                           */
+    __IOM uint8_t CRXD;                /*!< (@ 0x00000041) CEC Reception Buffer Register                              */
+
+    union
+    {
+        __IOM uint8_t CECES;           /*!< (@ 0x00000042) CEC Communication Error Status Register                    */
+
+        struct
+        {
+            __IM uint8_t OERR   : 1;   /*!< [0..0] Overrun Error Detection Flag                                       */
+            __IM uint8_t UERR   : 1;   /*!< [1..1] Underrun Error Detection Flag                                      */
+            __IM uint8_t ACKERR : 1;   /*!< [2..2] ACK Error Detection Flag                                           */
+            __IM uint8_t TERR   : 1;   /*!< [3..3] Timing Error Detection Flag                                        */
+            __IM uint8_t TXERR  : 1;   /*!< [4..4] Transmission Error Detection Flag                                  */
+            __IM uint8_t AERR   : 1;   /*!< [5..5] Arbitration Loss Detection Flag                                    */
+            __IM uint8_t BLERR  : 1;   /*!< [6..6] Bus Lock Error Detection Flag                                      */
+            uint8_t             : 1;
+        } CECES_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CECS;            /*!< (@ 0x00000043) CEC Communication Status Register                          */
+
+        struct
+        {
+            __IM uint8_t ADRF  : 1;    /*!< [0..0] Address Match Detection Flag                                       */
+            __IM uint8_t BUSST : 1;    /*!< [1..1] Bus Busy Detection Flag                                            */
+            __IM uint8_t TXST  : 1;    /*!< [2..2] Transmission Status Flag                                           */
+            __IM uint8_t EOMF  : 1;    /*!< [3..3] EOM Flag                                                           */
+            __IM uint8_t ITCEF : 1;    /*!< [4..4] INTCE Generation Source Flag                                       */
+            uint8_t            : 2;
+            __IM uint8_t SFTST : 1;    /*!< [7..7] Signal-Free Time Rewrite Disable Report Flag                       */
+        } CECS_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CECFC;           /*!< (@ 0x00000044) CEC Communication Error Flag Clear Trigger Register        */
+
+        struct
+        {
+            __OM uint8_t OCTRG   : 1;  /*!< [0..0] Overrun Error Detection Flag Clear Trigger                         */
+            __OM uint8_t UCTRG   : 1;  /*!< [1..1] Underrun Error Detection Flag Clear Trigger                        */
+            __OM uint8_t ACKCTRG : 1;  /*!< [2..2] ACK Error Detection Flag Clear Trigger                             */
+            __OM uint8_t TCTRG   : 1;  /*!< [3..3] Timing Error Detection Flag Clear Trigger                          */
+            __OM uint8_t TXCTRG  : 1;  /*!< [4..4] Transmission Error Detection Flag Clear Trigger                    */
+            __OM uint8_t ACTRG   : 1;  /*!< [5..5] Arbitration Loss Detection Flag Clear Trigger                      */
+            __OM uint8_t BLCTRG  : 1;  /*!< [6..6] Bus Lock Error Detection Flag Clear Trigger                        */
+            uint8_t              : 1;
+        } CECFC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CECCTL0;         /*!< (@ 0x00000045) CEC Control Register 0                                     */
+
+        struct
+        {
+            __IOM uint8_t EOM     : 1; /*!< [0..0] EOM Setting                                                        */
+            __IOM uint8_t CECRXEN : 1; /*!< [1..1] Reception Enable Control                                           */
+            __OM uint8_t  TXTRG   : 1; /*!< [2..2] Transmission Start Trigger                                         */
+            __IOM uint8_t CCL     : 3; /*!< [5..3] CEC Clock (CECCLK) Select                                          */
+            __IOM uint8_t ACKTEN  : 1; /*!< [6..6] ACK Bit Timing Error (Bit Width) Check Enable                      */
+            __IOM uint8_t CECE    : 1; /*!< [7..7] CEC Operation Enable Flag                                          */
+        } CECCTL0_b;
+    };
+} R_CEC_Type;                          /*!< Size = 70 (0x46)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
+ */
+
+typedef struct                          /*!< (@ 0x400E8000) R_AGTX0 Structure                                          */
+{
+    union
+    {
+        __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
+        __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
+    };
+} R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_FLAD                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Data Flash (R_FLAD)
+ */
+
+typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure                                           */
+{
+    __IM uint8_t RESERVED[64];
+
+    union
+    {
+        __IOM uint8_t FCKMHZ;          /*!< (@ 0x00000040) Data Flash Access Frequency Register                       */
+
+        struct
+        {
+            __IOM uint8_t FCKMHZ : 8;  /*!< [7..0] Data Flash Access Frequency Register                               */
+        } FCKMHZ_b;
+    };
+} R_FLAD_Type;                         /*!< Size = 65 (0x41)                                                          */
+
+/** @} */ /* End of group Device_Peripheral_peripherals */
+
+/* =========================================================================================================================== */
+/* ================                          Device Specific Peripheral Address Map                           ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_peripheralAddr
+ * @{
+ */
+
+ #define R_ADC0_BASE           0x40170000UL
+ #define R_ADC1_BASE           0x40170200UL
+ #define R_PSCU_BASE           0x400E0000UL
+ #define R_BUS_BASE            0x40003000UL
+ #define R_CAC_BASE            0x40083600UL
+ #define R_CANFD_BASE          0x400B0000UL
+ #define R_CANFD1_BASE         0x400B2000UL
+ #define R_CRC_BASE            0x40108000UL
+ #define R_DAC_BASE            0x40171000UL
+ #define R_DEBUG_BASE          0x4001B000UL
+ #define R_DMA_BASE            0x40005200UL
+ #define R_DMAC0_BASE          0x40005000UL
+ #define R_DMAC1_BASE          0x40005040UL
+ #define R_DMAC2_BASE          0x40005080UL
+ #define R_DMAC3_BASE          0x400050C0UL
+ #define R_DMAC4_BASE          0x40005100UL
+ #define R_DMAC5_BASE          0x40005140UL
+ #define R_DMAC6_BASE          0x40005180UL
+ #define R_DMAC7_BASE          0x400051C0UL
+ #define R_DOC_BASE            0x40109000UL
+ #define R_DTC_BASE            0x40005400UL
+ #define R_ELC_BASE            0x40082000UL
+ #define R_FACI_HP_CMD_BASE    0x407E0000UL
+ #define R_FACI_HP_BASE        0x407FE000UL
+ #define R_FCACHE_BASE         0x4001C000UL
+ #define R_GPT0_BASE           0x40169000UL
+ #define R_GPT1_BASE           0x40169100UL
+ #define R_GPT2_BASE           0x40169200UL
+ #define R_GPT3_BASE           0x40169300UL
+ #define R_GPT4_BASE           0x40169400UL
+ #define R_GPT5_BASE           0x40169500UL
+ #define R_GPT6_BASE           0x40169600UL
+ #define R_GPT7_BASE           0x40169700UL
+ #define R_GPT8_BASE           0x40169800UL
+ #define R_GPT9_BASE           0x40169900UL
+ #define R_GPT10_BASE          0x40169A00UL
+ #define R_GPT11_BASE          0x40169B00UL
+ #define R_GPT12_BASE          0x40169C00UL
+ #define R_GPT13_BASE          0x40169D00UL
+ #define R_GPT_OPS_BASE        0x40169A00UL
+ #define R_GPT_POEG0_BASE      0x4008A000UL
+ #define R_GPT_POEG1_BASE      0x4008A100UL
+ #define R_GPT_POEG2_BASE      0x4008A200UL
+ #define R_GPT_POEG3_BASE      0x4008A300UL
+ #define R_ICU_BASE            0x40006000UL
+ #define R_IIC0_BASE           0x4009F000UL
+ #define R_IIC1_BASE           0x4009F100UL
+ #define R_IIC2_BASE           0x4009F200UL
+ #define R_IWDT_BASE           0x40083200UL
+ #define R_I3C0_BASE           0x4011F000UL
+ #define R_I3C1_BASE           0x4011F400UL
+ #define R_MPU_SPMON_BASE      0x40000D00UL
+ #define R_MSTP_BASE           0x40084000UL
+ #define R_PORT0_BASE          0x40080000UL
+ #define R_PORT1_BASE          0x40080020UL
+ #define R_PORT2_BASE          0x40080040UL
+ #define R_PORT3_BASE          0x40080060UL
+ #define R_PORT4_BASE          0x40080080UL
+ #define R_PORT5_BASE          0x400800A0UL
+ #define R_PORT6_BASE          0x400800C0UL
+ #define R_PORT7_BASE          0x400800E0UL
+ #define R_PORT8_BASE          0x40080100UL
+ #define R_PORT9_BASE          0x40080120UL
+ #define R_PORT10_BASE         0x40080140UL
+ #define R_PORT11_BASE         0x40080160UL
+ #define R_PORT12_BASE         0x40080180UL
+ #define R_PORT13_BASE         0x400801A0UL
+ #define R_PORT14_BASE         0x400801C0UL
+ #define R_PFS_BASE            0x40080800UL
+ #define R_PMISC_BASE          0x40080D00UL
+ #define R_RTC_BASE            0x40083000UL
+ #define R_SCI0_BASE           0x40118000UL
+ #define R_SCI1_BASE           0x40118100UL
+ #define R_SCI2_BASE           0x40118200UL
+ #define R_SCI3_BASE           0x40118300UL
+ #define R_SCI4_BASE           0x40118400UL
+ #define R_SCI5_BASE           0x40118500UL
+ #define R_SCI6_BASE           0x40118600UL
+ #define R_SCI7_BASE           0x40118700UL
+ #define R_SCI8_BASE           0x40118800UL
+ #define R_SCI9_BASE           0x40118900UL
+ #define R_SPI0_BASE           0x4011A000UL
+ #define R_SPI1_BASE           0x4011A100UL
+ #define R_SRAM_BASE           0x40002000UL
+ #define R_SSI0_BASE           0x4009D000UL
+ #define R_SSI1_BASE           0x4009D100UL
+ #define R_SYSTEM_BASE         0x4001E000UL
+ #define R_TSN_CAL_BASE        0x407FB17CUL
+ #define R_TSN_CTRL_BASE       0x400F3000UL
+ #define R_USB_FS0_BASE        0x40090000UL
+ #define R_WDT_BASE            0x40083400UL
+ #define R_TZF_BASE            0x40000E00UL
+ #define R_CACHE_BASE          0x40007000UL
+ #define R_CPSCU_BASE          0x40008000UL
+ #define R_CEC_BASE            0x400AC000UL
+ #define R_AGTX0_BASE          0x400E8000UL
+ #define R_AGTX1_BASE          0x400E8100UL
+ #define R_AGTX2_BASE          0x400E8200UL
+ #define R_AGTX3_BASE          0x400E8300UL
+ #define R_AGTX4_BASE          0x400E8400UL
+ #define R_AGTX5_BASE          0x400E8500UL
+ #define R_AGTX6_BASE          0x400E8600UL
+ #define R_AGTX7_BASE          0x400E8700UL
+ #define R_AGTX8_BASE          0x400E8800UL
+ #define R_AGTX9_BASE          0x400E8900UL
+ #define R_FLAD_BASE           0x407FC000UL
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+/* =========================================================================================================================== */
+/* ================                                  Peripheral declaration                                   ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_declaration
+ * @{
+ */
+
+ #define R_ADC0           ((R_ADC0_Type *) R_ADC0_BASE)
+ #define R_ADC1           ((R_ADC0_Type *) R_ADC1_BASE)
+ #define R_PSCU           ((R_PSCU_Type *) R_PSCU_BASE)
+ #define R_BUS            ((R_BUS_Type *) R_BUS_BASE)
+ #define R_CAC            ((R_CAC_Type *) R_CAC_BASE)
+ #define R_CANFD          ((R_CANFD_Type *) R_CANFD_BASE)
+ #define R_CANFD0         ((R_CANFD_Type *) R_CANFD_BASE)
+ #define R_CANFD1         ((R_CANFD_Type *) R_CANFD1_BASE)
+ #define R_CRC            ((R_CRC_Type *) R_CRC_BASE)
+ #define R_DAC            ((R_DAC_Type *) R_DAC_BASE)
+ #define R_DEBUG          ((R_DEBUG_Type *) R_DEBUG_BASE)
+ #define R_DMA            ((R_DMA_Type *) R_DMA_BASE)
+ #define R_DMAC0          ((R_DMAC0_Type *) R_DMAC0_BASE)
+ #define R_DMAC1          ((R_DMAC0_Type *) R_DMAC1_BASE)
+ #define R_DMAC2          ((R_DMAC0_Type *) R_DMAC2_BASE)
+ #define R_DMAC3          ((R_DMAC0_Type *) R_DMAC3_BASE)
+ #define R_DMAC4          ((R_DMAC0_Type *) R_DMAC4_BASE)
+ #define R_DMAC5          ((R_DMAC0_Type *) R_DMAC5_BASE)
+ #define R_DMAC6          ((R_DMAC0_Type *) R_DMAC6_BASE)
+ #define R_DMAC7          ((R_DMAC0_Type *) R_DMAC7_BASE)
+ #define R_DOC            ((R_DOC_Type *) R_DOC_BASE)
+ #define R_DTC            ((R_DTC_Type *) R_DTC_BASE)
+ #define R_ELC            ((R_ELC_Type *) R_ELC_BASE)
+ #define R_FACI_HP_CMD    ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
+ #define R_FACI_HP        ((R_FACI_HP_Type *) R_FACI_HP_BASE)
+ #define R_FCACHE         ((R_FCACHE_Type *) R_FCACHE_BASE)
+ #define R_GPT0           ((R_GPT0_Type *) R_GPT0_BASE)
+ #define R_GPT1           ((R_GPT0_Type *) R_GPT1_BASE)
+ #define R_GPT2           ((R_GPT0_Type *) R_GPT2_BASE)
+ #define R_GPT3           ((R_GPT0_Type *) R_GPT3_BASE)
+ #define R_GPT4           ((R_GPT0_Type *) R_GPT4_BASE)
+ #define R_GPT5           ((R_GPT0_Type *) R_GPT5_BASE)
+ #define R_GPT6           ((R_GPT0_Type *) R_GPT6_BASE)
+ #define R_GPT7           ((R_GPT0_Type *) R_GPT7_BASE)
+ #define R_GPT8           ((R_GPT0_Type *) R_GPT8_BASE)
+ #define R_GPT9           ((R_GPT0_Type *) R_GPT9_BASE)
+ #define R_GPT10          ((R_GPT0_Type *) R_GPT10_BASE)
+ #define R_GPT11          ((R_GPT0_Type *) R_GPT11_BASE)
+ #define R_GPT12          ((R_GPT0_Type *) R_GPT12_BASE)
+ #define R_GPT13          ((R_GPT0_Type *) R_GPT13_BASE)
+ #define R_GPT_OPS        ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
+ #define R_GPT_POEG0      ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
+ #define R_GPT_POEG1      ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
+ #define R_GPT_POEG2      ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
+ #define R_GPT_POEG3      ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
+ #define R_ICU            ((R_ICU_Type *) R_ICU_BASE)
+ #define R_IIC0           ((R_IIC0_Type *) R_IIC0_BASE)
+ #define R_IIC1           ((R_IIC0_Type *) R_IIC1_BASE)
+ #define R_IIC2           ((R_IIC0_Type *) R_IIC2_BASE)
+ #define R_IWDT           ((R_IWDT_Type *) R_IWDT_BASE)
+ #define R_I3C0           ((R_I3C0_Type *) R_I3C0_BASE)
+ #define R_I3C1           ((R_I3C0_Type *) R_I3C1_BASE)
+ #define R_MPU_SPMON      ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE)
+ #define R_MSTP           ((R_MSTP_Type *) R_MSTP_BASE)
+ #define R_PORT0          ((R_PORT0_Type *) R_PORT0_BASE)
+ #define R_PORT1          ((R_PORT0_Type *) R_PORT1_BASE)
+ #define R_PORT2          ((R_PORT0_Type *) R_PORT2_BASE)
+ #define R_PORT3          ((R_PORT0_Type *) R_PORT3_BASE)
+ #define R_PORT4          ((R_PORT0_Type *) R_PORT4_BASE)
+ #define R_PORT5          ((R_PORT0_Type *) R_PORT5_BASE)
+ #define R_PORT6          ((R_PORT0_Type *) R_PORT6_BASE)
+ #define R_PORT7          ((R_PORT0_Type *) R_PORT7_BASE)
+ #define R_PORT8          ((R_PORT0_Type *) R_PORT8_BASE)
+ #define R_PORT9          ((R_PORT0_Type *) R_PORT9_BASE)
+ #define R_PORT10         ((R_PORT0_Type *) R_PORT10_BASE)
+ #define R_PORT11         ((R_PORT0_Type *) R_PORT11_BASE)
+ #define R_PORT12         ((R_PORT0_Type *) R_PORT12_BASE)
+ #define R_PORT13         ((R_PORT0_Type *) R_PORT13_BASE)
+ #define R_PORT14         ((R_PORT0_Type *) R_PORT14_BASE)
+ #define R_PFS            ((R_PFS_Type *) R_PFS_BASE)
+ #define R_PMISC          ((R_PMISC_Type *) R_PMISC_BASE)
+ #define R_RTC            ((R_RTC_Type *) R_RTC_BASE)
+ #define R_SCI0           ((R_SCI0_Type *) R_SCI0_BASE)
+ #define R_SCI1           ((R_SCI0_Type *) R_SCI1_BASE)
+ #define R_SCI2           ((R_SCI0_Type *) R_SCI2_BASE)
+ #define R_SCI3           ((R_SCI0_Type *) R_SCI3_BASE)
+ #define R_SCI4           ((R_SCI0_Type *) R_SCI4_BASE)
+ #define R_SCI5           ((R_SCI0_Type *) R_SCI5_BASE)
+ #define R_SCI6           ((R_SCI0_Type *) R_SCI6_BASE)
+ #define R_SCI7           ((R_SCI0_Type *) R_SCI7_BASE)
+ #define R_SCI8           ((R_SCI0_Type *) R_SCI8_BASE)
+ #define R_SCI9           ((R_SCI0_Type *) R_SCI9_BASE)
+ #define R_SPI0           ((R_SPI0_Type *) R_SPI0_BASE)
+ #define R_SPI1           ((R_SPI0_Type *) R_SPI1_BASE)
+ #define R_SRAM           ((R_SRAM_Type *) R_SRAM_BASE)
+ #define R_SSI0           ((R_SSI0_Type *) R_SSI0_BASE)
+ #define R_SSI1           ((R_SSI0_Type *) R_SSI1_BASE)
+ #define R_SYSTEM         ((R_SYSTEM_Type *) R_SYSTEM_BASE)
+ #define R_TSN_CAL        ((R_TSN_CAL_Type *) R_TSN_CAL_BASE)
+ #define R_TSN_CTRL       ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
+ #define R_USB_FS0        ((R_USB_FS0_Type *) R_USB_FS0_BASE)
+ #define R_WDT            ((R_WDT_Type *) R_WDT_BASE)
+ #define R_TZF            ((R_TZF_Type *) R_TZF_BASE)
+ #define R_CACHE          ((R_CACHE_Type *) R_CACHE_BASE)
+ #define R_CPSCU          ((R_CPSCU_Type *) R_CPSCU_BASE)
+ #define R_CEC            ((R_CEC_Type *) R_CEC_BASE)
+ #define R_AGTX0          ((R_AGTX0_Type *) R_AGTX0_BASE)
+ #define R_AGTX1          ((R_AGTX0_Type *) R_AGTX1_BASE)
+ #define R_AGTX2          ((R_AGTX0_Type *) R_AGTX2_BASE)
+ #define R_AGTX3          ((R_AGTX0_Type *) R_AGTX3_BASE)
+ #define R_AGTX4          ((R_AGTX0_Type *) R_AGTX4_BASE)
+ #define R_AGTX5          ((R_AGTX0_Type *) R_AGTX5_BASE)
+ #define R_AGTX6          ((R_AGTX0_Type *) R_AGTX6_BASE)
+ #define R_AGTX7          ((R_AGTX0_Type *) R_AGTX7_BASE)
+ #define R_AGTX8          ((R_AGTX0_Type *) R_AGTX8_BASE)
+ #define R_AGTX9          ((R_AGTX0_Type *) R_AGTX9_BASE)
+ #define R_FLAD           ((R_FLAD_Type *) R_FLAD_BASE)
+
+/** @} */ /* End of group Device_Peripheral_declaration */
+
+/* =========================================  End of section using anonymous unions  ========================================= */
+ #if defined(__CC_ARM)
+  #pragma pop
+ #elif defined(__ICCARM__)
+
+/* leave anonymous unions enabled */
+ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic pop
+ #elif defined(__GNUC__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TMS470__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TASKING__)
+  #pragma warning restore
+ #elif defined(__CSMC__)
+
+/* anonymous unions are enabled by default */
+ #endif
+
+/* =========================================================================================================================== */
+/* ================                                 Pos/Mask Cluster Section                                  ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup PosMask_clusters
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                            CSa                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  MOD  ========================================================== */
+ #define R_BUS_CSa_MOD_PRMOD_Pos        (15UL)         /*!< PRMOD (Bit 15)                                        */
+ #define R_BUS_CSa_MOD_PRMOD_Msk        (0x8000UL)     /*!< PRMOD (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_CSa_MOD_PWENB_Pos        (9UL)          /*!< PWENB (Bit 9)                                         */
+ #define R_BUS_CSa_MOD_PWENB_Msk        (0x200UL)      /*!< PWENB (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_CSa_MOD_PRENB_Pos        (8UL)          /*!< PRENB (Bit 8)                                         */
+ #define R_BUS_CSa_MOD_PRENB_Msk        (0x100UL)      /*!< PRENB (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_CSa_MOD_EWENB_Pos        (3UL)          /*!< EWENB (Bit 3)                                         */
+ #define R_BUS_CSa_MOD_EWENB_Msk        (0x8UL)        /*!< EWENB (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_CSa_MOD_WRMOD_Pos        (0UL)          /*!< WRMOD (Bit 0)                                         */
+ #define R_BUS_CSa_MOD_WRMOD_Msk        (0x1UL)        /*!< WRMOD (Bitfield-Mask: 0x01)                           */
+/* =========================================================  WCR1  ========================================================== */
+ #define R_BUS_CSa_WCR1_CSRWAIT_Pos     (24UL)         /*!< CSRWAIT (Bit 24)                                      */
+ #define R_BUS_CSa_WCR1_CSRWAIT_Msk     (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f)                         */
+ #define R_BUS_CSa_WCR1_CSWWAIT_Pos     (16UL)         /*!< CSWWAIT (Bit 16)                                      */
+ #define R_BUS_CSa_WCR1_CSWWAIT_Msk     (0x1f0000UL)   /*!< CSWWAIT (Bitfield-Mask: 0x1f)                         */
+ #define R_BUS_CSa_WCR1_CSPRWAIT_Pos    (8UL)          /*!< CSPRWAIT (Bit 8)                                      */
+ #define R_BUS_CSa_WCR1_CSPRWAIT_Msk    (0x700UL)      /*!< CSPRWAIT (Bitfield-Mask: 0x07)                        */
+ #define R_BUS_CSa_WCR1_CSPWWAIT_Pos    (0UL)          /*!< CSPWWAIT (Bit 0)                                      */
+ #define R_BUS_CSa_WCR1_CSPWWAIT_Msk    (0x7UL)        /*!< CSPWWAIT (Bitfield-Mask: 0x07)                        */
+/* =========================================================  WCR2  ========================================================== */
+ #define R_BUS_CSa_WCR2_CSON_Pos        (28UL)         /*!< CSON (Bit 28)                                         */
+ #define R_BUS_CSa_WCR2_CSON_Msk        (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07)                            */
+ #define R_BUS_CSa_WCR2_WDON_Pos        (24UL)         /*!< WDON (Bit 24)                                         */
+ #define R_BUS_CSa_WCR2_WDON_Msk        (0x7000000UL)  /*!< WDON (Bitfield-Mask: 0x07)                            */
+ #define R_BUS_CSa_WCR2_WRON_Pos        (20UL)         /*!< WRON (Bit 20)                                         */
+ #define R_BUS_CSa_WCR2_WRON_Msk        (0x700000UL)   /*!< WRON (Bitfield-Mask: 0x07)                            */
+ #define R_BUS_CSa_WCR2_RDON_Pos        (16UL)         /*!< RDON (Bit 16)                                         */
+ #define R_BUS_CSa_WCR2_RDON_Msk        (0x70000UL)    /*!< RDON (Bitfield-Mask: 0x07)                            */
+ #define R_BUS_CSa_WCR2_AWAIT_Pos       (12UL)         /*!< AWAIT (Bit 12)                                        */
+ #define R_BUS_CSa_WCR2_AWAIT_Msk       (0x3000UL)     /*!< AWAIT (Bitfield-Mask: 0x03)                           */
+ #define R_BUS_CSa_WCR2_WDOFF_Pos       (8UL)          /*!< WDOFF (Bit 8)                                         */
+ #define R_BUS_CSa_WCR2_WDOFF_Msk       (0x700UL)      /*!< WDOFF (Bitfield-Mask: 0x07)                           */
+ #define R_BUS_CSa_WCR2_CSWOFF_Pos      (4UL)          /*!< CSWOFF (Bit 4)                                        */
+ #define R_BUS_CSa_WCR2_CSWOFF_Msk      (0x70UL)       /*!< CSWOFF (Bitfield-Mask: 0x07)                          */
+ #define R_BUS_CSa_WCR2_CSROFF_Pos      (0UL)          /*!< CSROFF (Bit 0)                                        */
+ #define R_BUS_CSa_WCR2_CSROFF_Msk      (0x7UL)        /*!< CSROFF (Bitfield-Mask: 0x07)                          */
+
+/* =========================================================================================================================== */
+/* ================                                            CSb                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+ #define R_BUS_CSb_CR_MPXEN_Pos    (12UL)     /*!< MPXEN (Bit 12)                                        */
+ #define R_BUS_CSb_CR_MPXEN_Msk    (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_CSb_CR_EMODE_Pos    (8UL)      /*!< EMODE (Bit 8)                                         */
+ #define R_BUS_CSb_CR_EMODE_Msk    (0x100UL)  /*!< EMODE (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_CSb_CR_BSIZE_Pos    (4UL)      /*!< BSIZE (Bit 4)                                         */
+ #define R_BUS_CSb_CR_BSIZE_Msk    (0x30UL)   /*!< BSIZE (Bitfield-Mask: 0x03)                           */
+ #define R_BUS_CSb_CR_EXENB_Pos    (0UL)      /*!< EXENB (Bit 0)                                         */
+ #define R_BUS_CSb_CR_EXENB_Msk    (0x1UL)    /*!< EXENB (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  REC  ========================================================== */
+ #define R_BUS_CSb_REC_WRCV_Pos    (8UL)      /*!< WRCV (Bit 8)                                          */
+ #define R_BUS_CSb_REC_WRCV_Msk    (0xf00UL)  /*!< WRCV (Bitfield-Mask: 0x0f)                            */
+ #define R_BUS_CSb_REC_RRCV_Pos    (0UL)      /*!< RRCV (Bit 0)                                          */
+ #define R_BUS_CSb_REC_RRCV_Msk    (0xfUL)    /*!< RRCV (Bitfield-Mask: 0x0f)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           SDRAM                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SDCCR  ========================================================= */
+ #define R_BUS_SDRAM_SDCCR_BSIZE_Pos     (4UL)       /*!< BSIZE (Bit 4)                                         */
+ #define R_BUS_SDRAM_SDCCR_BSIZE_Msk     (0x30UL)    /*!< BSIZE (Bitfield-Mask: 0x03)                           */
+ #define R_BUS_SDRAM_SDCCR_EXENB_Pos     (0UL)       /*!< EXENB (Bit 0)                                         */
+ #define R_BUS_SDRAM_SDCCR_EXENB_Msk     (0x1UL)     /*!< EXENB (Bitfield-Mask: 0x01)                           */
+/* ========================================================  SDCMOD  ========================================================= */
+ #define R_BUS_SDRAM_SDCMOD_EMODE_Pos    (0UL)       /*!< EMODE (Bit 0)                                         */
+ #define R_BUS_SDRAM_SDCMOD_EMODE_Msk    (0x1UL)     /*!< EMODE (Bitfield-Mask: 0x01)                           */
+/* ========================================================  SDAMOD  ========================================================= */
+ #define R_BUS_SDRAM_SDAMOD_BE_Pos       (0UL)       /*!< BE (Bit 0)                                            */
+ #define R_BUS_SDRAM_SDAMOD_BE_Msk       (0x1UL)     /*!< BE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  SDSELF  ========================================================= */
+ #define R_BUS_SDRAM_SDSELF_SFEN_Pos     (0UL)       /*!< SFEN (Bit 0)                                          */
+ #define R_BUS_SDRAM_SDSELF_SFEN_Msk     (0x1UL)     /*!< SFEN (Bitfield-Mask: 0x01)                            */
+/* ========================================================  SDRFCR  ========================================================= */
+ #define R_BUS_SDRAM_SDRFCR_REFW_Pos     (12UL)      /*!< REFW (Bit 12)                                         */
+ #define R_BUS_SDRAM_SDRFCR_REFW_Msk     (0xf000UL)  /*!< REFW (Bitfield-Mask: 0x0f)                            */
+ #define R_BUS_SDRAM_SDRFCR_RFC_Pos      (0UL)       /*!< RFC (Bit 0)                                           */
+ #define R_BUS_SDRAM_SDRFCR_RFC_Msk      (0xfffUL)   /*!< RFC (Bitfield-Mask: 0xfff)                            */
+/* ========================================================  SDRFEN  ========================================================= */
+ #define R_BUS_SDRAM_SDRFEN_RFEN_Pos     (0UL)       /*!< RFEN (Bit 0)                                          */
+ #define R_BUS_SDRAM_SDRFEN_RFEN_Msk     (0x1UL)     /*!< RFEN (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SDICR  ========================================================= */
+ #define R_BUS_SDRAM_SDICR_INIRQ_Pos     (0UL)       /*!< INIRQ (Bit 0)                                         */
+ #define R_BUS_SDRAM_SDICR_INIRQ_Msk     (0x1UL)     /*!< INIRQ (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SDIR  ========================================================== */
+ #define R_BUS_SDRAM_SDIR_PRC_Pos        (8UL)       /*!< PRC (Bit 8)                                           */
+ #define R_BUS_SDRAM_SDIR_PRC_Msk        (0x700UL)   /*!< PRC (Bitfield-Mask: 0x07)                             */
+ #define R_BUS_SDRAM_SDIR_ARFC_Pos       (4UL)       /*!< ARFC (Bit 4)                                          */
+ #define R_BUS_SDRAM_SDIR_ARFC_Msk       (0xf0UL)    /*!< ARFC (Bitfield-Mask: 0x0f)                            */
+ #define R_BUS_SDRAM_SDIR_ARFI_Pos       (0UL)       /*!< ARFI (Bit 0)                                          */
+ #define R_BUS_SDRAM_SDIR_ARFI_Msk       (0xfUL)     /*!< ARFI (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  SDADR  ========================================================= */
+ #define R_BUS_SDRAM_SDADR_MXC_Pos       (0UL)       /*!< MXC (Bit 0)                                           */
+ #define R_BUS_SDRAM_SDADR_MXC_Msk       (0x3UL)     /*!< MXC (Bitfield-Mask: 0x03)                             */
+/* =========================================================  SDTR  ========================================================== */
+ #define R_BUS_SDRAM_SDTR_RAS_Pos        (16UL)      /*!< RAS (Bit 16)                                          */
+ #define R_BUS_SDRAM_SDTR_RAS_Msk        (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07)                             */
+ #define R_BUS_SDRAM_SDTR_RCD_Pos        (12UL)      /*!< RCD (Bit 12)                                          */
+ #define R_BUS_SDRAM_SDTR_RCD_Msk        (0x3000UL)  /*!< RCD (Bitfield-Mask: 0x03)                             */
+ #define R_BUS_SDRAM_SDTR_RP_Pos         (9UL)       /*!< RP (Bit 9)                                            */
+ #define R_BUS_SDRAM_SDTR_RP_Msk         (0xe00UL)   /*!< RP (Bitfield-Mask: 0x07)                              */
+ #define R_BUS_SDRAM_SDTR_WR_Pos         (8UL)       /*!< WR (Bit 8)                                            */
+ #define R_BUS_SDRAM_SDTR_WR_Msk         (0x100UL)   /*!< WR (Bitfield-Mask: 0x01)                              */
+ #define R_BUS_SDRAM_SDTR_CL_Pos         (0UL)       /*!< CL (Bit 0)                                            */
+ #define R_BUS_SDRAM_SDTR_CL_Msk         (0x7UL)     /*!< CL (Bitfield-Mask: 0x07)                              */
+/* =========================================================  SDMOD  ========================================================= */
+ #define R_BUS_SDRAM_SDMOD_MR_Pos        (0UL)       /*!< MR (Bit 0)                                            */
+ #define R_BUS_SDRAM_SDMOD_MR_Msk        (0x7fffUL)  /*!< MR (Bitfield-Mask: 0x7fff)                            */
+/* =========================================================  SDSR  ========================================================== */
+ #define R_BUS_SDRAM_SDSR_SRFST_Pos      (4UL)       /*!< SRFST (Bit 4)                                         */
+ #define R_BUS_SDRAM_SDSR_SRFST_Msk      (0x10UL)    /*!< SRFST (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_SDRAM_SDSR_INIST_Pos      (3UL)       /*!< INIST (Bit 3)                                         */
+ #define R_BUS_SDRAM_SDSR_INIST_Msk      (0x8UL)     /*!< INIST (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_SDRAM_SDSR_MRSST_Pos      (0UL)       /*!< MRSST (Bit 0)                                         */
+ #define R_BUS_SDRAM_SDSR_MRSST_Msk      (0x1UL)     /*!< MRSST (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                          BUSERR                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ADD  ========================================================== */
+ #define R_BUS_BUSERR_ADD_BERAD_Pos       (0UL)          /*!< BERAD (Bit 0)                                         */
+ #define R_BUS_BUSERR_ADD_BERAD_Msk       (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  STAT  ========================================================== */
+ #define R_BUS_BUSERR_STAT_ERRSTAT_Pos    (7UL)          /*!< ERRSTAT (Bit 7)                                       */
+ #define R_BUS_BUSERR_STAT_ERRSTAT_Msk    (0x80UL)       /*!< ERRSTAT (Bitfield-Mask: 0x01)                         */
+ #define R_BUS_BUSERR_STAT_ACCSTAT_Pos    (0UL)          /*!< ACCSTAT (Bit 0)                                       */
+ #define R_BUS_BUSERR_STAT_ACCSTAT_Msk    (0x1UL)        /*!< ACCSTAT (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                           BUSM                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CNT  ========================================================== */
+ #define R_BUS_BUSM_CNT_IERES_Pos    (15UL)     /*!< IERES (Bit 15)                                        */
+ #define R_BUS_BUSM_CNT_IERES_Msk    (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                           BUSS                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CNT  ========================================================== */
+ #define R_BUS_BUSS_CNT_ARBMET_Pos    (4UL)    /*!< ARBMET (Bit 4)                                        */
+ #define R_BUS_BUSS_CNT_ARBMET_Msk    (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03)                          */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDC                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  NCFG  ========================================================== */
+ #define R_CANFD_CFDC_NCFG_NBRP_Pos      (0UL)          /*!< NBRP (Bit 0)                                          */
+ #define R_CANFD_CFDC_NCFG_NBRP_Msk      (0x3ffUL)      /*!< NBRP (Bitfield-Mask: 0x3ff)                           */
+ #define R_CANFD_CFDC_NCFG_NSJW_Pos      (10UL)         /*!< NSJW (Bit 10)                                         */
+ #define R_CANFD_CFDC_NCFG_NSJW_Msk      (0x1fc00UL)    /*!< NSJW (Bitfield-Mask: 0x7f)                            */
+ #define R_CANFD_CFDC_NCFG_NTSEG1_Pos    (17UL)         /*!< NTSEG1 (Bit 17)                                       */
+ #define R_CANFD_CFDC_NCFG_NTSEG1_Msk    (0x1fe0000UL)  /*!< NTSEG1 (Bitfield-Mask: 0xff)                          */
+ #define R_CANFD_CFDC_NCFG_NTSEG2_Pos    (25UL)         /*!< NTSEG2 (Bit 25)                                       */
+ #define R_CANFD_CFDC_NCFG_NTSEG2_Msk    (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f)                          */
+/* ==========================================================  CTR  ========================================================== */
+ #define R_CANFD_CFDC_CTR_CHMDC_Pos      (0UL)          /*!< CHMDC (Bit 0)                                         */
+ #define R_CANFD_CFDC_CTR_CHMDC_Msk      (0x3UL)        /*!< CHMDC (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDC_CTR_CSLPR_Pos      (2UL)          /*!< CSLPR (Bit 2)                                         */
+ #define R_CANFD_CFDC_CTR_CSLPR_Msk      (0x4UL)        /*!< CSLPR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_CTR_RTBO_Pos       (3UL)          /*!< RTBO (Bit 3)                                          */
+ #define R_CANFD_CFDC_CTR_RTBO_Msk       (0x8UL)        /*!< RTBO (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_BEIE_Pos       (8UL)          /*!< BEIE (Bit 8)                                          */
+ #define R_CANFD_CFDC_CTR_BEIE_Msk       (0x100UL)      /*!< BEIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_EWIE_Pos       (9UL)          /*!< EWIE (Bit 9)                                          */
+ #define R_CANFD_CFDC_CTR_EWIE_Msk       (0x200UL)      /*!< EWIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_EPIE_Pos       (10UL)         /*!< EPIE (Bit 10)                                         */
+ #define R_CANFD_CFDC_CTR_EPIE_Msk       (0x400UL)      /*!< EPIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_BOEIE_Pos      (11UL)         /*!< BOEIE (Bit 11)                                        */
+ #define R_CANFD_CFDC_CTR_BOEIE_Msk      (0x800UL)      /*!< BOEIE (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_CTR_BORIE_Pos      (12UL)         /*!< BORIE (Bit 12)                                        */
+ #define R_CANFD_CFDC_CTR_BORIE_Msk      (0x1000UL)     /*!< BORIE (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_CTR_OLIE_Pos       (13UL)         /*!< OLIE (Bit 13)                                         */
+ #define R_CANFD_CFDC_CTR_OLIE_Msk       (0x2000UL)     /*!< OLIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_BLIE_Pos       (14UL)         /*!< BLIE (Bit 14)                                         */
+ #define R_CANFD_CFDC_CTR_BLIE_Msk       (0x4000UL)     /*!< BLIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_ALIE_Pos       (15UL)         /*!< ALIE (Bit 15)                                         */
+ #define R_CANFD_CFDC_CTR_ALIE_Msk       (0x8000UL)     /*!< ALIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_TAIE_Pos       (16UL)         /*!< TAIE (Bit 16)                                         */
+ #define R_CANFD_CFDC_CTR_TAIE_Msk       (0x10000UL)    /*!< TAIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_EOCOIE_Pos     (17UL)         /*!< EOCOIE (Bit 17)                                       */
+ #define R_CANFD_CFDC_CTR_EOCOIE_Msk     (0x20000UL)    /*!< EOCOIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC_CTR_SOCOIE_Pos     (18UL)         /*!< SOCOIE (Bit 18)                                       */
+ #define R_CANFD_CFDC_CTR_SOCOIE_Msk     (0x40000UL)    /*!< SOCOIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC_CTR_TDCVFIE_Pos    (19UL)         /*!< TDCVFIE (Bit 19)                                      */
+ #define R_CANFD_CFDC_CTR_TDCVFIE_Msk    (0x80000UL)    /*!< TDCVFIE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDC_CTR_BOM_Pos        (21UL)         /*!< BOM (Bit 21)                                          */
+ #define R_CANFD_CFDC_CTR_BOM_Msk        (0x600000UL)   /*!< BOM (Bitfield-Mask: 0x03)                             */
+ #define R_CANFD_CFDC_CTR_ERRD_Pos       (23UL)         /*!< ERRD (Bit 23)                                         */
+ #define R_CANFD_CFDC_CTR_ERRD_Msk       (0x800000UL)   /*!< ERRD (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_CTME_Pos       (24UL)         /*!< CTME (Bit 24)                                         */
+ #define R_CANFD_CFDC_CTR_CTME_Msk       (0x1000000UL)  /*!< CTME (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_CTMS_Pos       (25UL)         /*!< CTMS (Bit 25)                                         */
+ #define R_CANFD_CFDC_CTR_CTMS_Msk       (0x6000000UL)  /*!< CTMS (Bitfield-Mask: 0x03)                            */
+ #define R_CANFD_CFDC_CTR_CRCT_Pos       (30UL)         /*!< CRCT (Bit 30)                                         */
+ #define R_CANFD_CFDC_CTR_CRCT_Msk       (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_ROM_Pos        (31UL)         /*!< ROM (Bit 31)                                          */
+ #define R_CANFD_CFDC_CTR_ROM_Msk        (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01)                             */
+/* ==========================================================  STS  ========================================================== */
+ #define R_CANFD_CFDC_STS_CRSTSTS_Pos    (0UL)          /*!< CRSTSTS (Bit 0)                                       */
+ #define R_CANFD_CFDC_STS_CRSTSTS_Msk    (0x1UL)        /*!< CRSTSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDC_STS_CHLTSTS_Pos    (1UL)          /*!< CHLTSTS (Bit 1)                                       */
+ #define R_CANFD_CFDC_STS_CHLTSTS_Msk    (0x2UL)        /*!< CHLTSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDC_STS_CSLPSTS_Pos    (2UL)          /*!< CSLPSTS (Bit 2)                                       */
+ #define R_CANFD_CFDC_STS_CSLPSTS_Msk    (0x4UL)        /*!< CSLPSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDC_STS_EPSTS_Pos      (3UL)          /*!< EPSTS (Bit 3)                                         */
+ #define R_CANFD_CFDC_STS_EPSTS_Msk      (0x8UL)        /*!< EPSTS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_STS_BOSTS_Pos      (4UL)          /*!< BOSTS (Bit 4)                                         */
+ #define R_CANFD_CFDC_STS_BOSTS_Msk      (0x10UL)       /*!< BOSTS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_STS_TRMSTS_Pos     (5UL)          /*!< TRMSTS (Bit 5)                                        */
+ #define R_CANFD_CFDC_STS_TRMSTS_Msk     (0x20UL)       /*!< TRMSTS (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC_STS_RECSTS_Pos     (6UL)          /*!< RECSTS (Bit 6)                                        */
+ #define R_CANFD_CFDC_STS_RECSTS_Msk     (0x40UL)       /*!< RECSTS (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC_STS_COMSTS_Pos     (7UL)          /*!< COMSTS (Bit 7)                                        */
+ #define R_CANFD_CFDC_STS_COMSTS_Msk     (0x80UL)       /*!< COMSTS (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC_STS_ESIF_Pos       (8UL)          /*!< ESIF (Bit 8)                                          */
+ #define R_CANFD_CFDC_STS_ESIF_Msk       (0x100UL)      /*!< ESIF (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_STS_REC_Pos        (16UL)         /*!< REC (Bit 16)                                          */
+ #define R_CANFD_CFDC_STS_REC_Msk        (0xff0000UL)   /*!< REC (Bitfield-Mask: 0xff)                             */
+ #define R_CANFD_CFDC_STS_TEC_Pos        (24UL)         /*!< TEC (Bit 24)                                          */
+ #define R_CANFD_CFDC_STS_TEC_Msk        (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff)                             */
+/* =========================================================  ERFL  ========================================================== */
+ #define R_CANFD_CFDC_ERFL_BEF_Pos       (0UL)          /*!< BEF (Bit 0)                                           */
+ #define R_CANFD_CFDC_ERFL_BEF_Msk       (0x1UL)        /*!< BEF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDC_ERFL_EWF_Pos       (1UL)          /*!< EWF (Bit 1)                                           */
+ #define R_CANFD_CFDC_ERFL_EWF_Msk       (0x2UL)        /*!< EWF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDC_ERFL_EPF_Pos       (2UL)          /*!< EPF (Bit 2)                                           */
+ #define R_CANFD_CFDC_ERFL_EPF_Msk       (0x4UL)        /*!< EPF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDC_ERFL_BOEF_Pos      (3UL)          /*!< BOEF (Bit 3)                                          */
+ #define R_CANFD_CFDC_ERFL_BOEF_Msk      (0x8UL)        /*!< BOEF (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_BORF_Pos      (4UL)          /*!< BORF (Bit 4)                                          */
+ #define R_CANFD_CFDC_ERFL_BORF_Msk      (0x10UL)       /*!< BORF (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_OVLF_Pos      (5UL)          /*!< OVLF (Bit 5)                                          */
+ #define R_CANFD_CFDC_ERFL_OVLF_Msk      (0x20UL)       /*!< OVLF (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_BLF_Pos       (6UL)          /*!< BLF (Bit 6)                                           */
+ #define R_CANFD_CFDC_ERFL_BLF_Msk       (0x40UL)       /*!< BLF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDC_ERFL_ALF_Pos       (7UL)          /*!< ALF (Bit 7)                                           */
+ #define R_CANFD_CFDC_ERFL_ALF_Msk       (0x80UL)       /*!< ALF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDC_ERFL_SERR_Pos      (8UL)          /*!< SERR (Bit 8)                                          */
+ #define R_CANFD_CFDC_ERFL_SERR_Msk      (0x100UL)      /*!< SERR (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_FERR_Pos      (9UL)          /*!< FERR (Bit 9)                                          */
+ #define R_CANFD_CFDC_ERFL_FERR_Msk      (0x200UL)      /*!< FERR (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_AERR_Pos      (10UL)         /*!< AERR (Bit 10)                                         */
+ #define R_CANFD_CFDC_ERFL_AERR_Msk      (0x400UL)      /*!< AERR (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_CERR_Pos      (11UL)         /*!< CERR (Bit 11)                                         */
+ #define R_CANFD_CFDC_ERFL_CERR_Msk      (0x800UL)      /*!< CERR (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_B1ERR_Pos     (12UL)         /*!< B1ERR (Bit 12)                                        */
+ #define R_CANFD_CFDC_ERFL_B1ERR_Msk     (0x1000UL)     /*!< B1ERR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_ERFL_B0ERR_Pos     (13UL)         /*!< B0ERR (Bit 13)                                        */
+ #define R_CANFD_CFDC_ERFL_B0ERR_Msk     (0x2000UL)     /*!< B0ERR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_ERFL_ADERR_Pos     (14UL)         /*!< ADERR (Bit 14)                                        */
+ #define R_CANFD_CFDC_ERFL_ADERR_Msk     (0x4000UL)     /*!< ADERR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_ERFL_CRCREG_Pos    (16UL)         /*!< CRCREG (Bit 16)                                       */
+ #define R_CANFD_CFDC_ERFL_CRCREG_Msk    (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDC2                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DCFG  ========================================================== */
+ #define R_CANFD_CFDC2_DCFG_DBRP_Pos       (0UL)          /*!< DBRP (Bit 0)                                          */
+ #define R_CANFD_CFDC2_DCFG_DBRP_Msk       (0xffUL)       /*!< DBRP (Bitfield-Mask: 0xff)                            */
+ #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos     (8UL)          /*!< DTSEG1 (Bit 8)                                        */
+ #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk     (0x1f00UL)     /*!< DTSEG1 (Bitfield-Mask: 0x1f)                          */
+ #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos     (16UL)         /*!< DTSEG2 (Bit 16)                                       */
+ #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk     (0xf0000UL)    /*!< DTSEG2 (Bitfield-Mask: 0x0f)                          */
+ #define R_CANFD_CFDC2_DCFG_DSJW_Pos       (24UL)         /*!< DSJW (Bit 24)                                         */
+ #define R_CANFD_CFDC2_DCFG_DSJW_Msk       (0xf000000UL)  /*!< DSJW (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  FDCFG  ========================================================= */
+ #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos    (0UL)          /*!< EOCCFG (Bit 0)                                        */
+ #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk    (0x7UL)        /*!< EOCCFG (Bitfield-Mask: 0x07)                          */
+ #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos     (8UL)          /*!< TDCOC (Bit 8)                                         */
+ #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk     (0x100UL)      /*!< TDCOC (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC2_FDCFG_TDCE_Pos      (9UL)          /*!< TDCE (Bit 9)                                          */
+ #define R_CANFD_CFDC2_FDCFG_TDCE_Msk      (0x200UL)      /*!< TDCE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDCFG_ESIC_Pos      (10UL)         /*!< ESIC (Bit 10)                                         */
+ #define R_CANFD_CFDC2_FDCFG_ESIC_Msk      (0x400UL)      /*!< ESIC (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDCFG_TDCO_Pos      (16UL)         /*!< TDCO (Bit 16)                                         */
+ #define R_CANFD_CFDC2_FDCFG_TDCO_Msk      (0xff0000UL)   /*!< TDCO (Bitfield-Mask: 0xff)                            */
+ #define R_CANFD_CFDC2_FDCFG_FDOE_Pos      (28UL)         /*!< FDOE (Bit 28)                                         */
+ #define R_CANFD_CFDC2_FDCFG_FDOE_Msk      (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDCFG_REFE_Pos      (29UL)         /*!< REFE (Bit 29)                                         */
+ #define R_CANFD_CFDC2_FDCFG_REFE_Msk      (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDCFG_CLOE_Pos      (30UL)         /*!< CLOE (Bit 30)                                         */
+ #define R_CANFD_CFDC2_FDCFG_CLOE_Msk      (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  FDCTR  ========================================================= */
+ #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos    (0UL)          /*!< EOCCLR (Bit 0)                                        */
+ #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk    (0x1UL)        /*!< EOCCLR (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos    (1UL)          /*!< SOCCLR (Bit 1)                                        */
+ #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk    (0x2UL)        /*!< SOCCLR (Bitfield-Mask: 0x01)                          */
+/* =========================================================  FDSTS  ========================================================= */
+ #define R_CANFD_CFDC2_FDSTS_TDCR_Pos      (0UL)          /*!< TDCR (Bit 0)                                          */
+ #define R_CANFD_CFDC2_FDSTS_TDCR_Msk      (0xffUL)       /*!< TDCR (Bitfield-Mask: 0xff)                            */
+ #define R_CANFD_CFDC2_FDSTS_EOCO_Pos      (8UL)          /*!< EOCO (Bit 8)                                          */
+ #define R_CANFD_CFDC2_FDSTS_EOCO_Msk      (0x100UL)      /*!< EOCO (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDSTS_SOCO_Pos      (9UL)          /*!< SOCO (Bit 9)                                          */
+ #define R_CANFD_CFDC2_FDSTS_SOCO_Msk      (0x200UL)      /*!< SOCO (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos     (15UL)         /*!< TDCVF (Bit 15)                                        */
+ #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk     (0x8000UL)     /*!< TDCVF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC2_FDSTS_EOC_Pos       (16UL)         /*!< EOC (Bit 16)                                          */
+ #define R_CANFD_CFDC2_FDSTS_EOC_Msk       (0xff0000UL)   /*!< EOC (Bitfield-Mask: 0xff)                             */
+ #define R_CANFD_CFDC2_FDSTS_SOC_Pos       (24UL)         /*!< SOC (Bit 24)                                          */
+ #define R_CANFD_CFDC2_FDSTS_SOC_Msk       (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff)                             */
+/* =========================================================  FDCRC  ========================================================= */
+ #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos    (0UL)          /*!< CRCREG (Bit 0)                                        */
+ #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk    (0x1fffffUL)   /*!< CRCREG (Bitfield-Mask: 0x1fffff)                      */
+ #define R_CANFD_CFDC2_FDCRC_SCNT_Pos      (24UL)         /*!< SCNT (Bit 24)                                         */
+ #define R_CANFD_CFDC2_FDCRC_SCNT_Msk      (0xf000000UL)  /*!< SCNT (Bitfield-Mask: 0x0f)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          CFDGAFL                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CANFD_CFDGAFL_ID_GAFLID_Pos      (0UL)          /*!< GAFLID (Bit 0)                                        */
+ #define R_CANFD_CFDGAFL_ID_GAFLID_Msk      (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff)                    */
+ #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos      (29UL)         /*!< GAFLLB (Bit 29)                                       */
+ #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk      (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos     (30UL)         /*!< GAFLRTR (Bit 30)                                      */
+ #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk     (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos     (31UL)         /*!< GAFLIDE (Bit 31)                                      */
+ #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk     (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01)                         */
+/* ===========================================================  M  =========================================================== */
+ #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos      (0UL)          /*!< GAFLIDM (Bit 0)                                       */
+ #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk      (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff)                   */
+ #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos     (29UL)         /*!< GAFLIFL1 (Bit 29)                                     */
+ #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk     (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos     (30UL)         /*!< GAFLRTRM (Bit 30)                                     */
+ #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk     (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos     (31UL)         /*!< GAFLIDEM (Bit 31)                                     */
+ #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk     (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01)                        */
+/* ==========================================================  P0  =========================================================== */
+ #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos     (0UL)          /*!< GAFLDLC (Bit 0)                                       */
+ #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk     (0xfUL)        /*!< GAFLDLC (Bitfield-Mask: 0x0f)                         */
+ #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos    (7UL)          /*!< GAFLIFL0 (Bit 7)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk    (0x80UL)       /*!< GAFLIFL0 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos    (8UL)          /*!< GAFLRMDP (Bit 8)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk    (0x1f00UL)     /*!< GAFLRMDP (Bitfield-Mask: 0x1f)                        */
+ #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos     (15UL)         /*!< GAFLRMV (Bit 15)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk     (0x8000UL)     /*!< GAFLRMV (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos     (16UL)         /*!< GAFLPTR (Bit 16)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk     (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff)                       */
+/* ==========================================================  P1  =========================================================== */
+ #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos     (0UL)          /*!< GAFLFDP (Bit 0)                                       */
+ #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk     (0x1ffUL)      /*!< GAFLFDP (Bitfield-Mask: 0x1ff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                          CFDTHL                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ACC0  ========================================================== */
+ #define R_CANFD_CFDTHL_ACC0_BT_Pos      (0UL)          /*!< BT (Bit 0)                                            */
+ #define R_CANFD_CFDTHL_ACC0_BT_Msk      (0x7UL)        /*!< BT (Bitfield-Mask: 0x07)                              */
+ #define R_CANFD_CFDTHL_ACC0_BN_Pos      (3UL)          /*!< BN (Bit 3)                                            */
+ #define R_CANFD_CFDTHL_ACC0_BN_Msk      (0x3f8UL)      /*!< BN (Bitfield-Mask: 0x7f)                              */
+ #define R_CANFD_CFDTHL_ACC0_TMTS_Pos    (16UL)         /*!< TMTS (Bit 16)                                         */
+ #define R_CANFD_CFDTHL_ACC0_TMTS_Msk    (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  ACC1  ========================================================== */
+ #define R_CANFD_CFDTHL_ACC1_TID_Pos     (0UL)          /*!< TID (Bit 0)                                           */
+ #define R_CANFD_CFDTHL_ACC1_TID_Msk     (0xffffUL)     /*!< TID (Bitfield-Mask: 0xffff)                           */
+ #define R_CANFD_CFDTHL_ACC1_TIFL_Pos    (16UL)         /*!< TIFL (Bit 16)                                         */
+ #define R_CANFD_CFDTHL_ACC1_TIFL_Msk    (0x30000UL)    /*!< TIFL (Bitfield-Mask: 0x03)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDRF                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CANFD_CFDRF_ID_RFID_Pos        (0UL)          /*!< RFID (Bit 0)                                          */
+ #define R_CANFD_CFDRF_ID_RFID_Msk        (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff)                      */
+ #define R_CANFD_CFDRF_ID_RFRTR_Pos       (30UL)         /*!< RFRTR (Bit 30)                                        */
+ #define R_CANFD_CFDRF_ID_RFRTR_Msk       (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRF_ID_RFIDE_Pos       (31UL)         /*!< RFIDE (Bit 31)                                        */
+ #define R_CANFD_CFDRF_ID_RFIDE_Msk       (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  PTR  ========================================================== */
+ #define R_CANFD_CFDRF_PTR_RFTS_Pos       (0UL)          /*!< RFTS (Bit 0)                                          */
+ #define R_CANFD_CFDRF_PTR_RFTS_Msk       (0xffffUL)     /*!< RFTS (Bitfield-Mask: 0xffff)                          */
+ #define R_CANFD_CFDRF_PTR_RFDLC_Pos      (28UL)         /*!< RFDLC (Bit 28)                                        */
+ #define R_CANFD_CFDRF_PTR_RFDLC_Msk      (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f)                           */
+/* =========================================================  FDSTS  ========================================================= */
+ #define R_CANFD_CFDRF_FDSTS_RFESI_Pos    (0UL)          /*!< RFESI (Bit 0)                                         */
+ #define R_CANFD_CFDRF_FDSTS_RFESI_Msk    (0x1UL)        /*!< RFESI (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos    (1UL)          /*!< RFBRS (Bit 1)                                         */
+ #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk    (0x2UL)        /*!< RFBRS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos    (2UL)          /*!< RFFDF (Bit 2)                                         */
+ #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk    (0x4UL)        /*!< RFFDF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos    (8UL)          /*!< RFIFL (Bit 8)                                         */
+ #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk    (0x300UL)      /*!< RFIFL (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos    (16UL)         /*!< RFPTR (Bit 16)                                        */
+ #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk    (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff)                         */
+/* ==========================================================  DF  =========================================================== */
+ #define R_CANFD_CFDRF_DF_RFDB_Pos        (0UL)          /*!< RFDB (Bit 0)                                          */
+ #define R_CANFD_CFDRF_DF_RFDB_Msk        (0xffUL)       /*!< RFDB (Bitfield-Mask: 0xff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDCF                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CANFD_CFDCF_ID_CFID_Pos        (0UL)          /*!< CFID (Bit 0)                                          */
+ #define R_CANFD_CFDCF_ID_CFID_Msk        (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff)                      */
+ #define R_CANFD_CFDCF_ID_CFRTR_Pos       (30UL)         /*!< CFRTR (Bit 30)                                        */
+ #define R_CANFD_CFDCF_ID_CFRTR_Msk       (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCF_ID_CFIDE_Pos       (31UL)         /*!< CFIDE (Bit 31)                                        */
+ #define R_CANFD_CFDCF_ID_CFIDE_Msk       (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  PTR  ========================================================== */
+ #define R_CANFD_CFDCF_PTR_CFTS_Pos       (0UL)          /*!< CFTS (Bit 0)                                          */
+ #define R_CANFD_CFDCF_PTR_CFTS_Msk       (0xffffUL)     /*!< CFTS (Bitfield-Mask: 0xffff)                          */
+ #define R_CANFD_CFDCF_PTR_CFDLC_Pos      (28UL)         /*!< CFDLC (Bit 28)                                        */
+ #define R_CANFD_CFDCF_PTR_CFDLC_Msk      (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f)                           */
+/* =========================================================  FDSTS  ========================================================= */
+ #define R_CANFD_CFDCF_FDSTS_CFESI_Pos    (0UL)          /*!< CFESI (Bit 0)                                         */
+ #define R_CANFD_CFDCF_FDSTS_CFESI_Msk    (0x1UL)        /*!< CFESI (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos    (1UL)          /*!< CFBRS (Bit 1)                                         */
+ #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk    (0x2UL)        /*!< CFBRS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos    (2UL)          /*!< CFFDF (Bit 2)                                         */
+ #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk    (0x4UL)        /*!< CFFDF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos    (8UL)          /*!< CFIFL (Bit 8)                                         */
+ #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk    (0x300UL)      /*!< CFIFL (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos    (16UL)         /*!< CFPTR (Bit 16)                                        */
+ #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk    (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff)                         */
+/* ==========================================================  DF  =========================================================== */
+ #define R_CANFD_CFDCF_DF_CFDB_Pos        (0UL)          /*!< CFDB (Bit 0)                                          */
+ #define R_CANFD_CFDCF_DF_CFDB_Msk        (0xffUL)       /*!< CFDB (Bitfield-Mask: 0xff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDTM                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CANFD_CFDTM_ID_TMID_Pos        (0UL)          /*!< TMID (Bit 0)                                          */
+ #define R_CANFD_CFDTM_ID_TMID_Msk        (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff)                      */
+ #define R_CANFD_CFDTM_ID_TMRTR_Pos       (30UL)         /*!< TMRTR (Bit 30)                                        */
+ #define R_CANFD_CFDTM_ID_TMRTR_Msk       (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTM_ID_TMIDE_Pos       (31UL)         /*!< TMIDE (Bit 31)                                        */
+ #define R_CANFD_CFDTM_ID_TMIDE_Msk       (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  PTR  ========================================================== */
+ #define R_CANFD_CFDTM_PTR_TMTS_Pos       (0UL)          /*!< TMTS (Bit 0)                                          */
+ #define R_CANFD_CFDTM_PTR_TMTS_Msk       (0xffffUL)     /*!< TMTS (Bitfield-Mask: 0xffff)                          */
+ #define R_CANFD_CFDTM_PTR_TMDLC_Pos      (28UL)         /*!< TMDLC (Bit 28)                                        */
+ #define R_CANFD_CFDTM_PTR_TMDLC_Msk      (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f)                           */
+/* =========================================================  FDCTR  ========================================================= */
+ #define R_CANFD_CFDTM_FDCTR_TMESI_Pos    (0UL)          /*!< TMESI (Bit 0)                                         */
+ #define R_CANFD_CFDTM_FDCTR_TMESI_Msk    (0x1UL)        /*!< TMESI (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos    (1UL)          /*!< TMBRS (Bit 1)                                         */
+ #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk    (0x2UL)        /*!< TMBRS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos    (2UL)          /*!< TMFDF (Bit 2)                                         */
+ #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk    (0x4UL)        /*!< TMFDF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos    (8UL)          /*!< TMIFL (Bit 8)                                         */
+ #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk    (0x300UL)      /*!< TMIFL (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos    (16UL)         /*!< TMPTR (Bit 16)                                        */
+ #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk    (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff)                         */
+/* ==========================================================  DF  =========================================================== */
+ #define R_CANFD_CFDTM_DF_TMDB_Pos        (0UL)          /*!< TMDB (Bit 0)                                          */
+ #define R_CANFD_CFDTM_DF_TMDB_Msk        (0xffUL)       /*!< TMDB (Bitfield-Mask: 0xff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                            RM                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CANFD_CFDRM_RM_ID_RMID_Pos        (0UL)          /*!< RMID (Bit 0)                                          */
+ #define R_CANFD_CFDRM_RM_ID_RMID_Msk        (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff)                      */
+ #define R_CANFD_CFDRM_RM_ID_RMRTR_Pos       (30UL)         /*!< RMRTR (Bit 30)                                        */
+ #define R_CANFD_CFDRM_RM_ID_RMRTR_Msk       (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRM_RM_ID_RMIDE_Pos       (31UL)         /*!< RMIDE (Bit 31)                                        */
+ #define R_CANFD_CFDRM_RM_ID_RMIDE_Msk       (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  PTR  ========================================================== */
+ #define R_CANFD_CFDRM_RM_PTR_RMTS_Pos       (0UL)          /*!< RMTS (Bit 0)                                          */
+ #define R_CANFD_CFDRM_RM_PTR_RMTS_Msk       (0xffffUL)     /*!< RMTS (Bitfield-Mask: 0xffff)                          */
+ #define R_CANFD_CFDRM_RM_PTR_RMDLC_Pos      (28UL)         /*!< RMDLC (Bit 28)                                        */
+ #define R_CANFD_CFDRM_RM_PTR_RMDLC_Msk      (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f)                           */
+/* =========================================================  FDSTS  ========================================================= */
+ #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Pos    (0UL)          /*!< RMESI (Bit 0)                                         */
+ #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Msk    (0x1UL)        /*!< RMESI (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Pos    (1UL)          /*!< RMBRS (Bit 1)                                         */
+ #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Msk    (0x2UL)        /*!< RMBRS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Pos    (2UL)          /*!< RMFDF (Bit 2)                                         */
+ #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Msk    (0x4UL)        /*!< RMFDF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Pos    (8UL)          /*!< RMIFL (Bit 8)                                         */
+ #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Msk    (0x300UL)      /*!< RMIFL (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Pos    (16UL)         /*!< RMPTR (Bit 16)                                        */
+ #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Msk    (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff)                         */
+/* ==========================================================  DF  =========================================================== */
+ #define R_CANFD_CFDRM_RM_DF_RMDB_Pos        (0UL)          /*!< RMDB (Bit 0)                                          */
+ #define R_CANFD_CFDRM_RM_DF_RMDB_Msk        (0xffUL)       /*!< RMDB (Bitfield-Mask: 0xff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDRM                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          ELSEGR                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  BY  =========================================================== */
+ #define R_ELC_ELSEGR_BY_WI_Pos     (7UL)    /*!< WI (Bit 7)                                            */
+ #define R_ELC_ELSEGR_BY_WI_Msk     (0x80UL) /*!< WI (Bitfield-Mask: 0x01)                              */
+ #define R_ELC_ELSEGR_BY_WE_Pos     (6UL)    /*!< WE (Bit 6)                                            */
+ #define R_ELC_ELSEGR_BY_WE_Msk     (0x40UL) /*!< WE (Bitfield-Mask: 0x01)                              */
+ #define R_ELC_ELSEGR_BY_SEG_Pos    (0UL)    /*!< SEG (Bit 0)                                           */
+ #define R_ELC_ELSEGR_BY_SEG_Msk    (0x1UL)  /*!< SEG (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           ELSR                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  HA  =========================================================== */
+ #define R_ELC_ELSR_HA_ELS_Pos    (0UL)     /*!< ELS (Bit 0)                                           */
+ #define R_ELC_ELSR_HA_ELS_Msk    (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                            SAR                                            ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  L  =========================================================== */
+ #define R_IIC0_SAR_L_SVA_Pos     (0UL)    /*!< SVA (Bit 0)                                           */
+ #define R_IIC0_SAR_L_SVA_Msk     (0xffUL) /*!< SVA (Bitfield-Mask: 0xff)                             */
+/* ===========================================================  U  =========================================================== */
+ #define R_IIC0_SAR_U_SVA9_Pos    (2UL)    /*!< SVA9 (Bit 2)                                          */
+ #define R_IIC0_SAR_U_SVA9_Msk    (0x4UL)  /*!< SVA9 (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_SAR_U_SVA8_Pos    (1UL)    /*!< SVA8 (Bit 1)                                          */
+ #define R_IIC0_SAR_U_SVA8_Msk    (0x2UL)  /*!< SVA8 (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_SAR_U_FS_Pos      (0UL)    /*!< FS (Bit 0)                                            */
+ #define R_IIC0_SAR_U_FS_Msk      (0x1UL)  /*!< FS (Bitfield-Mask: 0x01)                              */
+
+/* =========================================================================================================================== */
+/* ================                                            SP                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  OAD  ========================================================== */
+ #define R_MPU_SPMON_SP_OAD_KEY_Pos        (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_MPU_SPMON_SP_OAD_KEY_Msk        (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_MPU_SPMON_SP_OAD_OAD_Pos        (0UL)          /*!< OAD (Bit 0)                                           */
+ #define R_MPU_SPMON_SP_OAD_OAD_Msk        (0x1UL)        /*!< OAD (Bitfield-Mask: 0x01)                             */
+/* ==========================================================  CTL  ========================================================== */
+ #define R_MPU_SPMON_SP_CTL_ERROR_Pos      (8UL)          /*!< ERROR (Bit 8)                                         */
+ #define R_MPU_SPMON_SP_CTL_ERROR_Msk      (0x100UL)      /*!< ERROR (Bitfield-Mask: 0x01)                           */
+ #define R_MPU_SPMON_SP_CTL_ENABLE_Pos     (0UL)          /*!< ENABLE (Bit 0)                                        */
+ #define R_MPU_SPMON_SP_CTL_ENABLE_Msk     (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+/* ==========================================================  PT  =========================================================== */
+ #define R_MPU_SPMON_SP_PT_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_MPU_SPMON_SP_PT_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_MPU_SPMON_SP_PT_PROTECT_Pos     (0UL)          /*!< PROTECT (Bit 0)                                       */
+ #define R_MPU_SPMON_SP_PT_PROTECT_Msk     (0x1UL)        /*!< PROTECT (Bitfield-Mask: 0x01)                         */
+/* ==========================================================  SA  =========================================================== */
+ #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos    (0UL)          /*!< MSPMPUSA (Bit 0)                                      */
+ #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk    (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff)                  */
+/* ==========================================================  EA  =========================================================== */
+ #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos    (0UL)          /*!< MSPMPUEA (Bit 0)                                      */
+ #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk    (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff)                  */
+
+/* =========================================================================================================================== */
+/* ================                                            PIN                                            ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  PmnPFS_BY  ======================================================= */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos      (5UL)          /*!< PIM (Bit 5)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk      (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
+/* =======================================================  PmnPFS_HA  ======================================================= */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos      (5UL)          /*!< PIM (Bit 5)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk      (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos     (15UL)         /*!< ASEL (Bit 15)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk     (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos     (14UL)         /*!< ISEL (Bit 14)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk     (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos     (12UL)         /*!< EOFR (Bit 12)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk     (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos     (10UL)         /*!< DSCR (Bit 10)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk     (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
+/* ========================================================  PmnPFS  ========================================================= */
+ #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos       (6UL)          /*!< NCODR (Bit 6)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk       (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
+ #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos         (5UL)          /*!< PIM (Bit 5)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk         (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos         (4UL)          /*!< PCR (Bit 4)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk         (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos         (2UL)          /*!< PDR (Bit 2)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk         (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos        (1UL)          /*!< PIDR (Bit 1)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk        (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos        (0UL)          /*!< PODR (Bit 0)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk        (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos        (15UL)         /*!< ASEL (Bit 15)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk        (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos        (14UL)         /*!< ISEL (Bit 14)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk        (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos        (12UL)         /*!< EOFR (Bit 12)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk        (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos        (10UL)         /*!< DSCR (Bit 10)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk        (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos        (24UL)         /*!< PSEL (Bit 24)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk        (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos         (16UL)         /*!< PMR (Bit 16)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk         (0x10000UL)    /*!< PMR (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           PORT                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                           VLSEL                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  VL1SEL  ========================================================= */
+ #define R_PFS_VLSEL_VL1SEL_SELVL_Pos    (0UL)   /*!< SELVL (Bit 0)                                         */
+ #define R_PFS_VLSEL_VL1SEL_SELVL_Msk    (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                           PMSAR                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  PMSAR  ========================================================= */
+
+/* =========================================================================================================================== */
+/* ================                                           RTCCR                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  RTCCR  ========================================================= */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
+ #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
+ #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCST_Msk    (0x4UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
+ #define R_RTC_RTCCR_RTCCR_TCCT_Pos    (0UL)    /*!< TCCT (Bit 0)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCCT_Msk    (0x3UL)  /*!< TCCT (Bitfield-Mask: 0x03)                            */
+
+/* =========================================================================================================================== */
+/* ================                                            CP                                             ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  RSEC  ========================================================== */
+ #define R_RTC_CP_RSEC_SEC10_Pos       (4UL)    /*!< SEC10 (Bit 4)                                         */
+ #define R_RTC_CP_RSEC_SEC10_Msk       (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07)                           */
+ #define R_RTC_CP_RSEC_SEC1_Pos        (0UL)    /*!< SEC1 (Bit 0)                                          */
+ #define R_RTC_CP_RSEC_SEC1_Msk        (0xfUL)  /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  BCNT0  ========================================================= */
+ #define R_RTC_CP_BCNT0_BCNT0CP_Pos    (0UL)    /*!< BCNT0CP (Bit 0)                                       */
+ #define R_RTC_CP_BCNT0_BCNT0CP_Msk    (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff)                         */
+/* =========================================================  RMIN  ========================================================== */
+ #define R_RTC_CP_RMIN_MIN10_Pos       (4UL)    /*!< MIN10 (Bit 4)                                         */
+ #define R_RTC_CP_RMIN_MIN10_Msk       (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07)                           */
+ #define R_RTC_CP_RMIN_MIN1_Pos        (0UL)    /*!< MIN1 (Bit 0)                                          */
+ #define R_RTC_CP_RMIN_MIN1_Msk        (0xfUL)  /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  BCNT1  ========================================================= */
+ #define R_RTC_CP_BCNT1_BCNT1CP_Pos    (0UL)    /*!< BCNT1CP (Bit 0)                                       */
+ #define R_RTC_CP_BCNT1_BCNT1CP_Msk    (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff)                         */
+/* ==========================================================  RHR  ========================================================== */
+ #define R_RTC_CP_RHR_PM_Pos           (6UL)    /*!< PM (Bit 6)                                            */
+ #define R_RTC_CP_RHR_PM_Msk           (0x40UL) /*!< PM (Bitfield-Mask: 0x01)                              */
+ #define R_RTC_CP_RHR_HR10_Pos         (4UL)    /*!< HR10 (Bit 4)                                          */
+ #define R_RTC_CP_RHR_HR10_Msk         (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03)                            */
+ #define R_RTC_CP_RHR_HR1_Pos          (0UL)    /*!< HR1 (Bit 0)                                           */
+ #define R_RTC_CP_RHR_HR1_Msk          (0xfUL)  /*!< HR1 (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  BCNT2  ========================================================= */
+ #define R_RTC_CP_BCNT2_BCNT2CP_Pos    (0UL)    /*!< BCNT2CP (Bit 0)                                       */
+ #define R_RTC_CP_BCNT2_BCNT2CP_Msk    (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff)                         */
+/* =========================================================  RDAY  ========================================================== */
+ #define R_RTC_CP_RDAY_DATE10_Pos      (4UL)    /*!< DATE10 (Bit 4)                                        */
+ #define R_RTC_CP_RDAY_DATE10_Msk      (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03)                          */
+ #define R_RTC_CP_RDAY_DATE1_Pos       (0UL)    /*!< DATE1 (Bit 0)                                         */
+ #define R_RTC_CP_RDAY_DATE1_Msk       (0xfUL)  /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
+/* =========================================================  BCNT3  ========================================================= */
+ #define R_RTC_CP_BCNT3_BCNT3CP_Pos    (0UL)    /*!< BCNT3CP (Bit 0)                                       */
+ #define R_RTC_CP_BCNT3_BCNT3CP_Msk    (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff)                         */
+/* =========================================================  RMON  ========================================================== */
+ #define R_RTC_CP_RMON_MON10_Pos       (4UL)    /*!< MON10 (Bit 4)                                         */
+ #define R_RTC_CP_RMON_MON10_Msk       (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_CP_RMON_MON1_Pos        (0UL)    /*!< MON1 (Bit 0)                                          */
+ #define R_RTC_CP_RMON_MON1_Msk        (0xfUL)  /*!< MON1 (Bitfield-Mask: 0x0f)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          PIPE_TR                                          ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  E  =========================================================== */
+ #define R_USB_FS0_PIPE_TR_E_TRENB_Pos     (9UL)      /*!< TRENB (Bit 9)                                         */
+ #define R_USB_FS0_PIPE_TR_E_TRENB_Msk     (0x200UL)  /*!< TRENB (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos     (8UL)      /*!< TRCLR (Bit 8)                                         */
+ #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk     (0x100UL)  /*!< TRCLR (Bitfield-Mask: 0x01)                           */
+/* ===========================================================  N  =========================================================== */
+ #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
+ #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           CTRL                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  AGTCR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AGTMR1  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
+/* ========================================================  AGTMR2  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
+/* =====================================================  AGTIOSEL_ALT  ====================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+/* ========================================================  AGTIOC  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AGTISR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AGTCMSR  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
+/* =======================================================  AGTIOSEL  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT16                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT32                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
+
+/** @} */ /* End of group PosMask_clusters */
+
+/* =========================================================================================================================== */
+/* ================                                Pos/Mask Peripheral Section                                ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup PosMask_peripherals
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ADC0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ADCSR  ========================================================= */
+ #define R_ADC0_ADCSR_ADST_Pos              (15UL)      /*!< ADST (Bit 15)                                         */
+ #define R_ADC0_ADCSR_ADST_Msk              (0x8000UL)  /*!< ADST (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADCSR_ADCS_Pos              (13UL)      /*!< ADCS (Bit 13)                                         */
+ #define R_ADC0_ADCSR_ADCS_Msk              (0x6000UL)  /*!< ADCS (Bitfield-Mask: 0x03)                            */
+ #define R_ADC0_ADCSR_ADHSC_Pos             (10UL)      /*!< ADHSC (Bit 10)                                        */
+ #define R_ADC0_ADCSR_ADHSC_Msk             (0x400UL)   /*!< ADHSC (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCSR_TRGE_Pos              (9UL)       /*!< TRGE (Bit 9)                                          */
+ #define R_ADC0_ADCSR_TRGE_Msk              (0x200UL)   /*!< TRGE (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADCSR_EXTRG_Pos             (8UL)       /*!< EXTRG (Bit 8)                                         */
+ #define R_ADC0_ADCSR_EXTRG_Msk             (0x100UL)   /*!< EXTRG (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCSR_DBLE_Pos              (7UL)       /*!< DBLE (Bit 7)                                          */
+ #define R_ADC0_ADCSR_DBLE_Msk              (0x80UL)    /*!< DBLE (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADCSR_GBADIE_Pos            (6UL)       /*!< GBADIE (Bit 6)                                        */
+ #define R_ADC0_ADCSR_GBADIE_Msk            (0x40UL)    /*!< GBADIE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCSR_DBLANS_Pos            (0UL)       /*!< DBLANS (Bit 0)                                        */
+ #define R_ADC0_ADCSR_DBLANS_Msk            (0x1fUL)    /*!< DBLANS (Bitfield-Mask: 0x1f)                          */
+ #define R_ADC0_ADCSR_ADIE_Pos              (12UL)      /*!< ADIE (Bit 12)                                         */
+ #define R_ADC0_ADCSR_ADIE_Msk              (0x1000UL)  /*!< ADIE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  ADANSA  ========================================================= */
+ #define R_ADC0_ADANSA_ANSA_Pos             (0UL)       /*!< ANSA (Bit 0)                                          */
+ #define R_ADC0_ADANSA_ANSA_Msk             (0x1UL)     /*!< ANSA (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ADADS  ========================================================= */
+ #define R_ADC0_ADADS_ADS_Pos               (0UL)       /*!< ADS (Bit 0)                                           */
+ #define R_ADC0_ADADS_ADS_Msk               (0x1UL)     /*!< ADS (Bitfield-Mask: 0x01)                             */
+/* =========================================================  ADADC  ========================================================= */
+ #define R_ADC0_ADADC_ADC_Pos               (0UL)       /*!< ADC (Bit 0)                                           */
+ #define R_ADC0_ADADC_ADC_Msk               (0x7UL)     /*!< ADC (Bitfield-Mask: 0x07)                             */
+ #define R_ADC0_ADADC_AVEE_Pos              (7UL)       /*!< AVEE (Bit 7)                                          */
+ #define R_ADC0_ADADC_AVEE_Msk              (0x80UL)    /*!< AVEE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ADCER  ========================================================= */
+ #define R_ADC0_ADCER_ADRFMT_Pos            (15UL)      /*!< ADRFMT (Bit 15)                                       */
+ #define R_ADC0_ADCER_ADRFMT_Msk            (0x8000UL)  /*!< ADRFMT (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCER_ADINV_Pos             (14UL)      /*!< ADINV (Bit 14)                                        */
+ #define R_ADC0_ADCER_ADINV_Msk             (0x4000UL)  /*!< ADINV (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCER_DIAGM_Pos             (11UL)      /*!< DIAGM (Bit 11)                                        */
+ #define R_ADC0_ADCER_DIAGM_Msk             (0x800UL)   /*!< DIAGM (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCER_DIAGLD_Pos            (10UL)      /*!< DIAGLD (Bit 10)                                       */
+ #define R_ADC0_ADCER_DIAGLD_Msk            (0x400UL)   /*!< DIAGLD (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCER_DIAGVAL_Pos           (8UL)       /*!< DIAGVAL (Bit 8)                                       */
+ #define R_ADC0_ADCER_DIAGVAL_Msk           (0x300UL)   /*!< DIAGVAL (Bitfield-Mask: 0x03)                         */
+ #define R_ADC0_ADCER_ACE_Pos               (5UL)       /*!< ACE (Bit 5)                                           */
+ #define R_ADC0_ADCER_ACE_Msk               (0x20UL)    /*!< ACE (Bitfield-Mask: 0x01)                             */
+ #define R_ADC0_ADCER_ADPRC_Pos             (1UL)       /*!< ADPRC (Bit 1)                                         */
+ #define R_ADC0_ADCER_ADPRC_Msk             (0x6UL)     /*!< ADPRC (Bitfield-Mask: 0x03)                           */
+ #define R_ADC0_ADCER_DCE_Pos               (4UL)       /*!< DCE (Bit 4)                                           */
+ #define R_ADC0_ADCER_DCE_Msk               (0x10UL)    /*!< DCE (Bitfield-Mask: 0x01)                             */
+/* ========================================================  ADSTRGR  ======================================================== */
+ #define R_ADC0_ADSTRGR_TRSA_Pos            (8UL)       /*!< TRSA (Bit 8)                                          */
+ #define R_ADC0_ADSTRGR_TRSA_Msk            (0x3f00UL)  /*!< TRSA (Bitfield-Mask: 0x3f)                            */
+ #define R_ADC0_ADSTRGR_TRSB_Pos            (0UL)       /*!< TRSB (Bit 0)                                          */
+ #define R_ADC0_ADSTRGR_TRSB_Msk            (0x3fUL)    /*!< TRSB (Bitfield-Mask: 0x3f)                            */
+/* ========================================================  ADEXICR  ======================================================== */
+ #define R_ADC0_ADEXICR_OCSB_Pos            (11UL)      /*!< OCSB (Bit 11)                                         */
+ #define R_ADC0_ADEXICR_OCSB_Msk            (0x800UL)   /*!< OCSB (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADEXICR_TSSB_Pos            (10UL)      /*!< TSSB (Bit 10)                                         */
+ #define R_ADC0_ADEXICR_TSSB_Msk            (0x400UL)   /*!< TSSB (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADEXICR_OCSA_Pos            (9UL)       /*!< OCSA (Bit 9)                                          */
+ #define R_ADC0_ADEXICR_OCSA_Msk            (0x200UL)   /*!< OCSA (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADEXICR_TSSA_Pos            (8UL)       /*!< TSSA (Bit 8)                                          */
+ #define R_ADC0_ADEXICR_TSSA_Msk            (0x100UL)   /*!< TSSA (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADEXICR_OCSAD_Pos           (1UL)       /*!< OCSAD (Bit 1)                                         */
+ #define R_ADC0_ADEXICR_OCSAD_Msk           (0x2UL)     /*!< OCSAD (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADEXICR_TSSAD_Pos           (0UL)       /*!< TSSAD (Bit 0)                                         */
+ #define R_ADC0_ADEXICR_TSSAD_Msk           (0x1UL)     /*!< TSSAD (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADEXICR_EXSEL_Pos           (14UL)      /*!< EXSEL (Bit 14)                                        */
+ #define R_ADC0_ADEXICR_EXSEL_Msk           (0x4000UL)  /*!< EXSEL (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADEXICR_EXOEN_Pos           (15UL)      /*!< EXOEN (Bit 15)                                        */
+ #define R_ADC0_ADEXICR_EXOEN_Msk           (0x8000UL)  /*!< EXOEN (Bitfield-Mask: 0x01)                           */
+/* ========================================================  ADANSB  ========================================================= */
+ #define R_ADC0_ADANSB_ANSB_Pos             (0UL)       /*!< ANSB (Bit 0)                                          */
+ #define R_ADC0_ADANSB_ANSB_Msk             (0x1UL)     /*!< ANSB (Bitfield-Mask: 0x01)                            */
+/* ========================================================  ADDBLDR  ======================================================== */
+ #define R_ADC0_ADDBLDR_ADDBLDR_Pos         (0UL)       /*!< ADDBLDR (Bit 0)                                       */
+ #define R_ADC0_ADDBLDR_ADDBLDR_Msk         (0xffffUL)  /*!< ADDBLDR (Bitfield-Mask: 0xffff)                       */
+/* ========================================================  ADTSDR  ========================================================= */
+ #define R_ADC0_ADTSDR_ADTSDR_Pos           (0UL)       /*!< ADTSDR (Bit 0)                                        */
+ #define R_ADC0_ADTSDR_ADTSDR_Msk           (0xffffUL)  /*!< ADTSDR (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  ADOCDR  ========================================================= */
+ #define R_ADC0_ADOCDR_ADOCDR_Pos           (0UL)       /*!< ADOCDR (Bit 0)                                        */
+ #define R_ADC0_ADOCDR_ADOCDR_Msk           (0xffffUL)  /*!< ADOCDR (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  ADRD_RIGHT  ======================================================= */
+ #define R_ADC0_ADRD_RIGHT_DIAGST_Pos       (14UL)      /*!< DIAGST (Bit 14)                                       */
+ #define R_ADC0_ADRD_RIGHT_DIAGST_Msk       (0xc000UL)  /*!< DIAGST (Bitfield-Mask: 0x03)                          */
+ #define R_ADC0_ADRD_RIGHT_AD_Pos           (0UL)       /*!< AD (Bit 0)                                            */
+ #define R_ADC0_ADRD_RIGHT_AD_Msk           (0x3fffUL)  /*!< AD (Bitfield-Mask: 0x3fff)                            */
+/* =======================================================  ADRD_LEFT  ======================================================= */
+ #define R_ADC0_ADRD_LEFT_AD_Pos            (2UL)       /*!< AD (Bit 2)                                            */
+ #define R_ADC0_ADRD_LEFT_AD_Msk            (0xfffcUL)  /*!< AD (Bitfield-Mask: 0x3fff)                            */
+ #define R_ADC0_ADRD_LEFT_DIAGST_Pos        (0UL)       /*!< DIAGST (Bit 0)                                        */
+ #define R_ADC0_ADRD_LEFT_DIAGST_Msk        (0x3UL)     /*!< DIAGST (Bitfield-Mask: 0x03)                          */
+/* =========================================================  ADDR  ========================================================== */
+ #define R_ADC0_ADDR_ADDR_Pos               (0UL)       /*!< ADDR (Bit 0)                                          */
+ #define R_ADC0_ADDR_ADDR_Msk               (0xffffUL)  /*!< ADDR (Bitfield-Mask: 0xffff)                          */
+/* ========================================================  ADSHCR  ========================================================= */
+ #define R_ADC0_ADSHCR_SHANS2_Pos           (10UL)      /*!< SHANS2 (Bit 10)                                       */
+ #define R_ADC0_ADSHCR_SHANS2_Msk           (0x400UL)   /*!< SHANS2 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSHCR_SHANS1_Pos           (9UL)       /*!< SHANS1 (Bit 9)                                        */
+ #define R_ADC0_ADSHCR_SHANS1_Msk           (0x200UL)   /*!< SHANS1 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSHCR_SHANS0_Pos           (8UL)       /*!< SHANS0 (Bit 8)                                        */
+ #define R_ADC0_ADSHCR_SHANS0_Msk           (0x100UL)   /*!< SHANS0 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSHCR_SSTSH_Pos            (0UL)       /*!< SSTSH (Bit 0)                                         */
+ #define R_ADC0_ADSHCR_SSTSH_Msk            (0xffUL)    /*!< SSTSH (Bitfield-Mask: 0xff)                           */
+/* ========================================================  ADDISCR  ======================================================== */
+ #define R_ADC0_ADDISCR_CHARGE_Pos          (4UL)       /*!< CHARGE (Bit 4)                                        */
+ #define R_ADC0_ADDISCR_CHARGE_Msk          (0x10UL)    /*!< CHARGE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADDISCR_ADNDIS_Pos          (0UL)       /*!< ADNDIS (Bit 0)                                        */
+ #define R_ADC0_ADDISCR_ADNDIS_Msk          (0xfUL)     /*!< ADNDIS (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  ADSHMSR  ======================================================== */
+ #define R_ADC0_ADSHMSR_SHMD_Pos            (0UL)       /*!< SHMD (Bit 0)                                          */
+ #define R_ADC0_ADSHMSR_SHMD_Msk            (0x1UL)     /*!< SHMD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  ADACSR  ========================================================= */
+ #define R_ADC0_ADACSR_ADSAC_Pos            (1UL)       /*!< ADSAC (Bit 1)                                         */
+ #define R_ADC0_ADACSR_ADSAC_Msk            (0x2UL)     /*!< ADSAC (Bitfield-Mask: 0x01)                           */
+/* ========================================================  ADGSPCR  ======================================================== */
+ #define R_ADC0_ADGSPCR_GBRP_Pos            (15UL)      /*!< GBRP (Bit 15)                                         */
+ #define R_ADC0_ADGSPCR_GBRP_Msk            (0x8000UL)  /*!< GBRP (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADGSPCR_GBRSCN_Pos          (1UL)       /*!< GBRSCN (Bit 1)                                        */
+ #define R_ADC0_ADGSPCR_GBRSCN_Msk          (0x2UL)     /*!< GBRSCN (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADGSPCR_PGS_Pos             (0UL)       /*!< PGS (Bit 0)                                           */
+ #define R_ADC0_ADGSPCR_PGS_Msk             (0x1UL)     /*!< PGS (Bitfield-Mask: 0x01)                             */
+ #define R_ADC0_ADGSPCR_GBEXTRG_Pos         (8UL)       /*!< GBEXTRG (Bit 8)                                       */
+ #define R_ADC0_ADGSPCR_GBEXTRG_Msk         (0x100UL)   /*!< GBEXTRG (Bitfield-Mask: 0x01)                         */
+/* =========================================================  ADICR  ========================================================= */
+ #define R_ADC0_ADICR_ADIC_Pos              (0UL)       /*!< ADIC (Bit 0)                                          */
+ #define R_ADC0_ADICR_ADIC_Msk              (0x3UL)     /*!< ADIC (Bitfield-Mask: 0x03)                            */
+/* =======================================================  ADDBLDRA  ======================================================== */
+ #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos       (0UL)       /*!< ADDBLDRA (Bit 0)                                      */
+ #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk       (0xffffUL)  /*!< ADDBLDRA (Bitfield-Mask: 0xffff)                      */
+/* =======================================================  ADDBLDRB  ======================================================== */
+ #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos       (0UL)       /*!< ADDBLDRB (Bit 0)                                      */
+ #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk       (0xffffUL)  /*!< ADDBLDRB (Bitfield-Mask: 0xffff)                      */
+/* ======================================================  ADHVREFCNT  ======================================================= */
+ #define R_ADC0_ADHVREFCNT_ADSLP_Pos        (7UL)       /*!< ADSLP (Bit 7)                                         */
+ #define R_ADC0_ADHVREFCNT_ADSLP_Msk        (0x80UL)    /*!< ADSLP (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADHVREFCNT_LVSEL_Pos        (4UL)       /*!< LVSEL (Bit 4)                                         */
+ #define R_ADC0_ADHVREFCNT_LVSEL_Msk        (0x10UL)    /*!< LVSEL (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADHVREFCNT_HVSEL_Pos        (0UL)       /*!< HVSEL (Bit 0)                                         */
+ #define R_ADC0_ADHVREFCNT_HVSEL_Msk        (0x3UL)     /*!< HVSEL (Bitfield-Mask: 0x03)                           */
+/* =======================================================  ADWINMON  ======================================================== */
+ #define R_ADC0_ADWINMON_MONCMPB_Pos        (5UL)       /*!< MONCMPB (Bit 5)                                       */
+ #define R_ADC0_ADWINMON_MONCMPB_Msk        (0x20UL)    /*!< MONCMPB (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADWINMON_MONCMPA_Pos        (4UL)       /*!< MONCMPA (Bit 4)                                       */
+ #define R_ADC0_ADWINMON_MONCMPA_Msk        (0x10UL)    /*!< MONCMPA (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADWINMON_MONCOMB_Pos        (0UL)       /*!< MONCOMB (Bit 0)                                       */
+ #define R_ADC0_ADWINMON_MONCOMB_Msk        (0x1UL)     /*!< MONCOMB (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ADCMPCR  ======================================================== */
+ #define R_ADC0_ADCMPCR_CMPAIE_Pos          (15UL)      /*!< CMPAIE (Bit 15)                                       */
+ #define R_ADC0_ADCMPCR_CMPAIE_Msk          (0x8000UL)  /*!< CMPAIE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCMPCR_WCMPE_Pos           (14UL)      /*!< WCMPE (Bit 14)                                        */
+ #define R_ADC0_ADCMPCR_WCMPE_Msk           (0x4000UL)  /*!< WCMPE (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCMPCR_CMPBIE_Pos          (13UL)      /*!< CMPBIE (Bit 13)                                       */
+ #define R_ADC0_ADCMPCR_CMPBIE_Msk          (0x2000UL)  /*!< CMPBIE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCMPCR_CMPAE_Pos           (11UL)      /*!< CMPAE (Bit 11)                                        */
+ #define R_ADC0_ADCMPCR_CMPAE_Msk           (0x800UL)   /*!< CMPAE (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCMPCR_CMPBE_Pos           (9UL)       /*!< CMPBE (Bit 9)                                         */
+ #define R_ADC0_ADCMPCR_CMPBE_Msk           (0x200UL)   /*!< CMPBE (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCMPCR_CMPAB_Pos           (0UL)       /*!< CMPAB (Bit 0)                                         */
+ #define R_ADC0_ADCMPCR_CMPAB_Msk           (0x3UL)     /*!< CMPAB (Bitfield-Mask: 0x03)                           */
+/* ======================================================  ADCMPANSER  ======================================================= */
+ #define R_ADC0_ADCMPANSER_CMPOCA_Pos       (1UL)       /*!< CMPOCA (Bit 1)                                        */
+ #define R_ADC0_ADCMPANSER_CMPOCA_Msk       (0x2UL)     /*!< CMPOCA (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCMPANSER_CMPTSA_Pos       (0UL)       /*!< CMPTSA (Bit 0)                                        */
+ #define R_ADC0_ADCMPANSER_CMPTSA_Msk       (0x1UL)     /*!< CMPTSA (Bitfield-Mask: 0x01)                          */
+/* =======================================================  ADCMPLER  ======================================================== */
+ #define R_ADC0_ADCMPLER_CMPLOCA_Pos        (1UL)       /*!< CMPLOCA (Bit 1)                                       */
+ #define R_ADC0_ADCMPLER_CMPLOCA_Msk        (0x2UL)     /*!< CMPLOCA (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADCMPLER_CMPLTSA_Pos        (0UL)       /*!< CMPLTSA (Bit 0)                                       */
+ #define R_ADC0_ADCMPLER_CMPLTSA_Msk        (0x1UL)     /*!< CMPLTSA (Bitfield-Mask: 0x01)                         */
+/* =======================================================  ADCMPANSR  ======================================================= */
+ #define R_ADC0_ADCMPANSR_CMPCHA_Pos        (0UL)       /*!< CMPCHA (Bit 0)                                        */
+ #define R_ADC0_ADCMPANSR_CMPCHA_Msk        (0x1UL)     /*!< CMPCHA (Bitfield-Mask: 0x01)                          */
+/* ========================================================  ADCMPLR  ======================================================== */
+ #define R_ADC0_ADCMPLR_CMPLCHA_Pos         (0UL)       /*!< CMPLCHA (Bit 0)                                       */
+ #define R_ADC0_ADCMPLR_CMPLCHA_Msk         (0x1UL)     /*!< CMPLCHA (Bitfield-Mask: 0x01)                         */
+/* =======================================================  ADCMPDR0  ======================================================== */
+ #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos       (0UL)       /*!< ADCMPDR0 (Bit 0)                                      */
+ #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk       (0xffffUL)  /*!< ADCMPDR0 (Bitfield-Mask: 0xffff)                      */
+/* =======================================================  ADCMPDR1  ======================================================== */
+ #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos       (0UL)       /*!< ADCMPDR1 (Bit 0)                                      */
+ #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk       (0xffffUL)  /*!< ADCMPDR1 (Bitfield-Mask: 0xffff)                      */
+/* ========================================================  ADCMPSR  ======================================================== */
+ #define R_ADC0_ADCMPSR_CMPSTCHA_Pos        (0UL)       /*!< CMPSTCHA (Bit 0)                                      */
+ #define R_ADC0_ADCMPSR_CMPSTCHA_Msk        (0x1UL)     /*!< CMPSTCHA (Bitfield-Mask: 0x01)                        */
+/* =======================================================  ADCMPSER  ======================================================== */
+ #define R_ADC0_ADCMPSER_CMPSTOCA_Pos       (1UL)       /*!< CMPSTOCA (Bit 1)                                      */
+ #define R_ADC0_ADCMPSER_CMPSTOCA_Msk       (0x2UL)     /*!< CMPSTOCA (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADCMPSER_CMPSTTSA_Pos       (0UL)       /*!< CMPSTTSA (Bit 0)                                      */
+ #define R_ADC0_ADCMPSER_CMPSTTSA_Msk       (0x1UL)     /*!< CMPSTTSA (Bitfield-Mask: 0x01)                        */
+/* =======================================================  ADCMPBNSR  ======================================================= */
+ #define R_ADC0_ADCMPBNSR_CMPLB_Pos         (7UL)       /*!< CMPLB (Bit 7)                                         */
+ #define R_ADC0_ADCMPBNSR_CMPLB_Msk         (0x80UL)    /*!< CMPLB (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCMPBNSR_CMPCHB_Pos        (0UL)       /*!< CMPCHB (Bit 0)                                        */
+ #define R_ADC0_ADCMPBNSR_CMPCHB_Msk        (0x3fUL)    /*!< CMPCHB (Bitfield-Mask: 0x3f)                          */
+/* =======================================================  ADWINLLB  ======================================================== */
+ #define R_ADC0_ADWINLLB_ADWINLLB_Pos       (0UL)       /*!< ADWINLLB (Bit 0)                                      */
+ #define R_ADC0_ADWINLLB_ADWINLLB_Msk       (0xffffUL)  /*!< ADWINLLB (Bitfield-Mask: 0xffff)                      */
+/* =======================================================  ADWINULB  ======================================================== */
+ #define R_ADC0_ADWINULB_ADWINULB_Pos       (0UL)       /*!< ADWINULB (Bit 0)                                      */
+ #define R_ADC0_ADWINULB_ADWINULB_Msk       (0xffffUL)  /*!< ADWINULB (Bitfield-Mask: 0xffff)                      */
+/* =======================================================  ADCMPBSR  ======================================================== */
+ #define R_ADC0_ADCMPBSR_CMPSTB_Pos         (0UL)       /*!< CMPSTB (Bit 0)                                        */
+ #define R_ADC0_ADCMPBSR_CMPSTB_Msk         (0x1UL)     /*!< CMPSTB (Bitfield-Mask: 0x01)                          */
+/* ========================================================  ADSSTRL  ======================================================== */
+ #define R_ADC0_ADSSTRL_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
+ #define R_ADC0_ADSSTRL_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
+/* ========================================================  ADSSTRT  ======================================================== */
+ #define R_ADC0_ADSSTRT_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
+ #define R_ADC0_ADSSTRT_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
+/* ========================================================  ADSSTRO  ======================================================== */
+ #define R_ADC0_ADSSTRO_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
+ #define R_ADC0_ADSSTRO_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
+/* ========================================================  ADSSTR  ========================================================= */
+ #define R_ADC0_ADSSTR_SST_Pos              (0UL)       /*!< SST (Bit 0)                                           */
+ #define R_ADC0_ADSSTR_SST_Msk              (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
+/* ========================================================  ADPGACR  ======================================================== */
+ #define R_ADC0_ADPGACR_P002GEN_Pos         (11UL)      /*!< P002GEN (Bit 11)                                      */
+ #define R_ADC0_ADPGACR_P002GEN_Msk         (0x800UL)   /*!< P002GEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADPGACR_P002ENAMP_Pos       (10UL)      /*!< P002ENAMP (Bit 10)                                    */
+ #define R_ADC0_ADPGACR_P002ENAMP_Msk       (0x400UL)   /*!< P002ENAMP (Bitfield-Mask: 0x01)                       */
+ #define R_ADC0_ADPGACR_P002SEL1_Pos        (9UL)       /*!< P002SEL1 (Bit 9)                                      */
+ #define R_ADC0_ADPGACR_P002SEL1_Msk        (0x200UL)   /*!< P002SEL1 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P002SEL0_Pos        (8UL)       /*!< P002SEL0 (Bit 8)                                      */
+ #define R_ADC0_ADPGACR_P002SEL0_Msk        (0x100UL)   /*!< P002SEL0 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P001GEN_Pos         (7UL)       /*!< P001GEN (Bit 7)                                       */
+ #define R_ADC0_ADPGACR_P001GEN_Msk         (0x80UL)    /*!< P001GEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADPGACR_P001ENAMP_Pos       (6UL)       /*!< P001ENAMP (Bit 6)                                     */
+ #define R_ADC0_ADPGACR_P001ENAMP_Msk       (0x40UL)    /*!< P001ENAMP (Bitfield-Mask: 0x01)                       */
+ #define R_ADC0_ADPGACR_P001SEL1_Pos        (5UL)       /*!< P001SEL1 (Bit 5)                                      */
+ #define R_ADC0_ADPGACR_P001SEL1_Msk        (0x20UL)    /*!< P001SEL1 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P001SEL0_Pos        (4UL)       /*!< P001SEL0 (Bit 4)                                      */
+ #define R_ADC0_ADPGACR_P001SEL0_Msk        (0x10UL)    /*!< P001SEL0 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P000GEN_Pos         (3UL)       /*!< P000GEN (Bit 3)                                       */
+ #define R_ADC0_ADPGACR_P000GEN_Msk         (0x8UL)     /*!< P000GEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADPGACR_P000ENAMP_Pos       (2UL)       /*!< P000ENAMP (Bit 2)                                     */
+ #define R_ADC0_ADPGACR_P000ENAMP_Msk       (0x4UL)     /*!< P000ENAMP (Bitfield-Mask: 0x01)                       */
+ #define R_ADC0_ADPGACR_P000SEL1_Pos        (1UL)       /*!< P000SEL1 (Bit 1)                                      */
+ #define R_ADC0_ADPGACR_P000SEL1_Msk        (0x2UL)     /*!< P000SEL1 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P000SEL0_Pos        (0UL)       /*!< P000SEL0 (Bit 0)                                      */
+ #define R_ADC0_ADPGACR_P000SEL0_Msk        (0x1UL)     /*!< P000SEL0 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P003SEL0_Pos        (12UL)      /*!< P003SEL0 (Bit 12)                                     */
+ #define R_ADC0_ADPGACR_P003SEL0_Msk        (0x1000UL)  /*!< P003SEL0 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P003SEL1_Pos        (13UL)      /*!< P003SEL1 (Bit 13)                                     */
+ #define R_ADC0_ADPGACR_P003SEL1_Msk        (0x2000UL)  /*!< P003SEL1 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P003ENAMP_Pos       (14UL)      /*!< P003ENAMP (Bit 14)                                    */
+ #define R_ADC0_ADPGACR_P003ENAMP_Msk       (0x4000UL)  /*!< P003ENAMP (Bitfield-Mask: 0x01)                       */
+ #define R_ADC0_ADPGACR_P003GEN_Pos         (15UL)      /*!< P003GEN (Bit 15)                                      */
+ #define R_ADC0_ADPGACR_P003GEN_Msk         (0x8000UL)  /*!< P003GEN (Bitfield-Mask: 0x01)                         */
+/* =========================================================  ADRD  ========================================================== */
+ #define R_ADC0_ADRD_AD_Pos                 (0UL)       /*!< AD (Bit 0)                                            */
+ #define R_ADC0_ADRD_AD_Msk                 (0xffffUL)  /*!< AD (Bitfield-Mask: 0xffff)                            */
+/* =========================================================  ADRST  ========================================================= */
+ #define R_ADC0_ADRST_DIAGST_Pos            (0UL)       /*!< DIAGST (Bit 0)                                        */
+ #define R_ADC0_ADRST_DIAGST_Msk            (0x3UL)     /*!< DIAGST (Bitfield-Mask: 0x03)                          */
+/* ======================================================  VREFAMPCNT  ======================================================= */
+ #define R_ADC0_VREFAMPCNT_VREFADCG_Pos     (1UL)       /*!< VREFADCG (Bit 1)                                      */
+ #define R_ADC0_VREFAMPCNT_VREFADCG_Msk     (0x6UL)     /*!< VREFADCG (Bitfield-Mask: 0x03)                        */
+ #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos    (3UL)       /*!< VREFADCEN (Bit 3)                                     */
+ #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk    (0x8UL)     /*!< VREFADCEN (Bitfield-Mask: 0x01)                       */
+ #define R_ADC0_VREFAMPCNT_ADSLP_Pos        (7UL)       /*!< ADSLP (Bit 7)                                         */
+ #define R_ADC0_VREFAMPCNT_ADSLP_Msk        (0x80UL)    /*!< ADSLP (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_VREFAMPCNT_OLDETEN_Pos      (0UL)       /*!< OLDETEN (Bit 0)                                       */
+ #define R_ADC0_VREFAMPCNT_OLDETEN_Msk      (0x1UL)     /*!< OLDETEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_VREFAMPCNT_BGREN_Pos        (4UL)       /*!< BGREN (Bit 4)                                         */
+ #define R_ADC0_VREFAMPCNT_BGREN_Msk        (0x10UL)    /*!< BGREN (Bitfield-Mask: 0x01)                           */
+/* =======================================================  ADCALEXE  ======================================================== */
+ #define R_ADC0_ADCALEXE_CALEXE_Pos         (7UL)       /*!< CALEXE (Bit 7)                                        */
+ #define R_ADC0_ADCALEXE_CALEXE_Msk         (0x80UL)    /*!< CALEXE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCALEXE_CALMON_Pos         (6UL)       /*!< CALMON (Bit 6)                                        */
+ #define R_ADC0_ADCALEXE_CALMON_Msk         (0x40UL)    /*!< CALMON (Bitfield-Mask: 0x01)                          */
+/* ========================================================  ADANIM  ========================================================= */
+ #define R_ADC0_ADANIM_ANIM_Pos             (0UL)       /*!< ANIM (Bit 0)                                          */
+ #define R_ADC0_ADANIM_ANIM_Msk             (0x1UL)     /*!< ANIM (Bitfield-Mask: 0x01)                            */
+/* =======================================================  ADPGAGS0  ======================================================== */
+ #define R_ADC0_ADPGAGS0_P002GAIN_Pos       (8UL)       /*!< P002GAIN (Bit 8)                                      */
+ #define R_ADC0_ADPGAGS0_P002GAIN_Msk       (0xf00UL)   /*!< P002GAIN (Bitfield-Mask: 0x0f)                        */
+ #define R_ADC0_ADPGAGS0_P001GAIN_Pos       (4UL)       /*!< P001GAIN (Bit 4)                                      */
+ #define R_ADC0_ADPGAGS0_P001GAIN_Msk       (0xf0UL)    /*!< P001GAIN (Bitfield-Mask: 0x0f)                        */
+ #define R_ADC0_ADPGAGS0_P000GAIN_Pos       (0UL)       /*!< P000GAIN (Bit 0)                                      */
+ #define R_ADC0_ADPGAGS0_P000GAIN_Msk       (0xfUL)     /*!< P000GAIN (Bitfield-Mask: 0x0f)                        */
+ #define R_ADC0_ADPGAGS0_P003GAIN_Pos       (12UL)      /*!< P003GAIN (Bit 12)                                     */
+ #define R_ADC0_ADPGAGS0_P003GAIN_Msk       (0xf000UL)  /*!< P003GAIN (Bitfield-Mask: 0x0f)                        */
+/* =======================================================  ADPGADCR0  ======================================================= */
+ #define R_ADC0_ADPGADCR0_P003DG_Pos        (12UL)      /*!< P003DG (Bit 12)                                       */
+ #define R_ADC0_ADPGADCR0_P003DG_Msk        (0x3000UL)  /*!< P003DG (Bitfield-Mask: 0x03)                          */
+ #define R_ADC0_ADPGADCR0_P002DEN_Pos       (11UL)      /*!< P002DEN (Bit 11)                                      */
+ #define R_ADC0_ADPGADCR0_P002DEN_Msk       (0x800UL)   /*!< P002DEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADPGADCR0_P002DG_Pos        (8UL)       /*!< P002DG (Bit 8)                                        */
+ #define R_ADC0_ADPGADCR0_P002DG_Msk        (0x300UL)   /*!< P002DG (Bitfield-Mask: 0x03)                          */
+ #define R_ADC0_ADPGADCR0_P001DEN_Pos       (7UL)       /*!< P001DEN (Bit 7)                                       */
+ #define R_ADC0_ADPGADCR0_P001DEN_Msk       (0x80UL)    /*!< P001DEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADPGADCR0_P001DG_Pos        (4UL)       /*!< P001DG (Bit 4)                                        */
+ #define R_ADC0_ADPGADCR0_P001DG_Msk        (0x30UL)    /*!< P001DG (Bitfield-Mask: 0x03)                          */
+ #define R_ADC0_ADPGADCR0_P000DEN_Pos       (3UL)       /*!< P000DEN (Bit 3)                                       */
+ #define R_ADC0_ADPGADCR0_P000DEN_Msk       (0x8UL)     /*!< P000DEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADPGADCR0_P000DG_Pos        (0UL)       /*!< P000DG (Bit 0)                                        */
+ #define R_ADC0_ADPGADCR0_P000DG_Msk        (0x3UL)     /*!< P000DG (Bitfield-Mask: 0x03)                          */
+ #define R_ADC0_ADPGADCR0_P003DEN_Pos       (15UL)      /*!< P003DEN (Bit 15)                                      */
+ #define R_ADC0_ADPGADCR0_P003DEN_Msk       (0x8000UL)  /*!< P003DEN (Bitfield-Mask: 0x01)                         */
+/* =========================================================  ADREF  ========================================================= */
+ #define R_ADC0_ADREF_ADF_Pos               (0UL)       /*!< ADF (Bit 0)                                           */
+ #define R_ADC0_ADREF_ADF_Msk               (0x1UL)     /*!< ADF (Bitfield-Mask: 0x01)                             */
+ #define R_ADC0_ADREF_ADSCACT_Pos           (7UL)       /*!< ADSCACT (Bit 7)                                       */
+ #define R_ADC0_ADREF_ADSCACT_Msk           (0x80UL)    /*!< ADSCACT (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ADEXREF  ======================================================== */
+ #define R_ADC0_ADEXREF_GBADF_Pos           (0UL)       /*!< GBADF (Bit 0)                                         */
+ #define R_ADC0_ADEXREF_GBADF_Msk           (0x1UL)     /*!< GBADF (Bitfield-Mask: 0x01)                           */
+/* =======================================================  ADAMPOFF  ======================================================== */
+ #define R_ADC0_ADAMPOFF_OPOFF_Pos          (0UL)       /*!< OPOFF (Bit 0)                                         */
+ #define R_ADC0_ADAMPOFF_OPOFF_Msk          (0xffUL)    /*!< OPOFF (Bitfield-Mask: 0xff)                           */
+/* ========================================================  ADTSTPR  ======================================================== */
+ #define R_ADC0_ADTSTPR_PRO_Pos             (0UL)       /*!< PRO (Bit 0)                                           */
+ #define R_ADC0_ADTSTPR_PRO_Msk             (0x1UL)     /*!< PRO (Bitfield-Mask: 0x01)                             */
+ #define R_ADC0_ADTSTPR_B0WI_Pos            (1UL)       /*!< B0WI (Bit 1)                                          */
+ #define R_ADC0_ADTSTPR_B0WI_Msk            (0x2UL)     /*!< B0WI (Bitfield-Mask: 0x01)                            */
+/* =======================================================  ADDDACER  ======================================================== */
+ #define R_ADC0_ADDDACER_WRION_Pos          (0UL)       /*!< WRION (Bit 0)                                         */
+ #define R_ADC0_ADDDACER_WRION_Msk          (0x1fUL)    /*!< WRION (Bitfield-Mask: 0x1f)                           */
+ #define R_ADC0_ADDDACER_WRIOFF_Pos         (8UL)       /*!< WRIOFF (Bit 8)                                        */
+ #define R_ADC0_ADDDACER_WRIOFF_Msk         (0x1f00UL)  /*!< WRIOFF (Bitfield-Mask: 0x1f)                          */
+ #define R_ADC0_ADDDACER_ADHS_Pos           (15UL)      /*!< ADHS (Bit 15)                                         */
+ #define R_ADC0_ADDDACER_ADHS_Msk           (0x8000UL)  /*!< ADHS (Bitfield-Mask: 0x01)                            */
+/* =======================================================  ADEXTSTR  ======================================================== */
+ #define R_ADC0_ADEXTSTR_SHTEST_Pos         (0UL)       /*!< SHTEST (Bit 0)                                        */
+ #define R_ADC0_ADEXTSTR_SHTEST_Msk         (0x7UL)     /*!< SHTEST (Bitfield-Mask: 0x07)                          */
+ #define R_ADC0_ADEXTSTR_SWTST_Pos          (4UL)       /*!< SWTST (Bit 4)                                         */
+ #define R_ADC0_ADEXTSTR_SWTST_Msk          (0x30UL)    /*!< SWTST (Bitfield-Mask: 0x03)                           */
+ #define R_ADC0_ADEXTSTR_SHTRM_Pos          (8UL)       /*!< SHTRM (Bit 8)                                         */
+ #define R_ADC0_ADEXTSTR_SHTRM_Msk          (0x300UL)   /*!< SHTRM (Bitfield-Mask: 0x03)                           */
+ #define R_ADC0_ADEXTSTR_ADTRM3_Pos         (11UL)      /*!< ADTRM3 (Bit 11)                                       */
+ #define R_ADC0_ADEXTSTR_ADTRM3_Msk         (0x800UL)   /*!< ADTRM3 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADEXTSTR_ADTRM2_Pos         (12UL)      /*!< ADTRM2 (Bit 12)                                       */
+ #define R_ADC0_ADEXTSTR_ADTRM2_Msk         (0x3000UL)  /*!< ADTRM2 (Bitfield-Mask: 0x03)                          */
+ #define R_ADC0_ADEXTSTR_ADTRM1_Pos         (14UL)      /*!< ADTRM1 (Bit 14)                                       */
+ #define R_ADC0_ADEXTSTR_ADTRM1_Msk         (0xc000UL)  /*!< ADTRM1 (Bitfield-Mask: 0x03)                          */
+/* ========================================================  ADTSTRA  ======================================================== */
+ #define R_ADC0_ADTSTRA_ATBUSSEL_Pos        (0UL)       /*!< ATBUSSEL (Bit 0)                                      */
+ #define R_ADC0_ADTSTRA_ATBUSSEL_Msk        (0x1UL)     /*!< ATBUSSEL (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADTSTRA_TSTSWREF_Pos        (1UL)       /*!< TSTSWREF (Bit 1)                                      */
+ #define R_ADC0_ADTSTRA_TSTSWREF_Msk        (0xeUL)     /*!< TSTSWREF (Bitfield-Mask: 0x07)                        */
+ #define R_ADC0_ADTSTRA_OCSW_Pos            (5UL)       /*!< OCSW (Bit 5)                                          */
+ #define R_ADC0_ADTSTRA_OCSW_Msk            (0x20UL)    /*!< OCSW (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADTSTRA_TSSW_Pos            (6UL)       /*!< TSSW (Bit 6)                                          */
+ #define R_ADC0_ADTSTRA_TSSW_Msk            (0x40UL)    /*!< TSSW (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADTSTRA_ADTEST_AD_Pos       (8UL)       /*!< ADTEST_AD (Bit 8)                                     */
+ #define R_ADC0_ADTSTRA_ADTEST_AD_Msk       (0xf00UL)   /*!< ADTEST_AD (Bitfield-Mask: 0x0f)                       */
+ #define R_ADC0_ADTSTRA_ADTEST_IO_Pos       (12UL)      /*!< ADTEST_IO (Bit 12)                                    */
+ #define R_ADC0_ADTSTRA_ADTEST_IO_Msk       (0xf000UL)  /*!< ADTEST_IO (Bitfield-Mask: 0x0f)                       */
+/* ========================================================  ADTSTRB  ======================================================== */
+ #define R_ADC0_ADTSTRB_ADVAL_Pos           (0UL)       /*!< ADVAL (Bit 0)                                         */
+ #define R_ADC0_ADTSTRB_ADVAL_Msk           (0x7fffUL)  /*!< ADVAL (Bitfield-Mask: 0x7fff)                         */
+/* ========================================================  ADTSTRC  ======================================================== */
+ #define R_ADC0_ADTSTRC_ADMD_Pos            (0UL)       /*!< ADMD (Bit 0)                                          */
+ #define R_ADC0_ADTSTRC_ADMD_Msk            (0xffUL)    /*!< ADMD (Bitfield-Mask: 0xff)                            */
+ #define R_ADC0_ADTSTRC_SYNCERR_Pos         (12UL)      /*!< SYNCERR (Bit 12)                                      */
+ #define R_ADC0_ADTSTRC_SYNCERR_Msk         (0x1000UL)  /*!< SYNCERR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ADTSTRD  ======================================================== */
+ #define R_ADC0_ADTSTRD_ADVAL16_Pos         (0UL)       /*!< ADVAL16 (Bit 0)                                       */
+ #define R_ADC0_ADTSTRD_ADVAL16_Msk         (0x1UL)     /*!< ADVAL16 (Bitfield-Mask: 0x01)                         */
+/* =======================================================  ADSWTSTR0  ======================================================= */
+ #define R_ADC0_ADSWTSTR0_CHSW00_Pos        (0UL)       /*!< CHSW00 (Bit 0)                                        */
+ #define R_ADC0_ADSWTSTR0_CHSW00_Msk        (0x1UL)     /*!< CHSW00 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR0_CHSW01_Pos        (1UL)       /*!< CHSW01 (Bit 1)                                        */
+ #define R_ADC0_ADSWTSTR0_CHSW01_Msk        (0x2UL)     /*!< CHSW01 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR0_CHSW02_Pos        (2UL)       /*!< CHSW02 (Bit 2)                                        */
+ #define R_ADC0_ADSWTSTR0_CHSW02_Msk        (0x4UL)     /*!< CHSW02 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR0_CHSW03_Pos        (3UL)       /*!< CHSW03 (Bit 3)                                        */
+ #define R_ADC0_ADSWTSTR0_CHSW03_Msk        (0x8UL)     /*!< CHSW03 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR0_CHSW04_Pos        (4UL)       /*!< CHSW04 (Bit 4)                                        */
+ #define R_ADC0_ADSWTSTR0_CHSW04_Msk        (0x10UL)    /*!< CHSW04 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR0_CHSW05_Pos        (5UL)       /*!< CHSW05 (Bit 5)                                        */
+ #define R_ADC0_ADSWTSTR0_CHSW05_Msk        (0x20UL)    /*!< CHSW05 (Bitfield-Mask: 0x01)                          */
+/* =======================================================  ADSWTSTR1  ======================================================= */
+ #define R_ADC0_ADSWTSTR1_CHSW16_Pos        (0UL)       /*!< CHSW16 (Bit 0)                                        */
+ #define R_ADC0_ADSWTSTR1_CHSW16_Msk        (0x1UL)     /*!< CHSW16 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR1_CHSW17_Pos        (1UL)       /*!< CHSW17 (Bit 1)                                        */
+ #define R_ADC0_ADSWTSTR1_CHSW17_Msk        (0x2UL)     /*!< CHSW17 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR1_CHSW18_Pos        (2UL)       /*!< CHSW18 (Bit 2)                                        */
+ #define R_ADC0_ADSWTSTR1_CHSW18_Msk        (0x4UL)     /*!< CHSW18 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR1_CHSW19_Pos        (3UL)       /*!< CHSW19 (Bit 3)                                        */
+ #define R_ADC0_ADSWTSTR1_CHSW19_Msk        (0x8UL)     /*!< CHSW19 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR1_CHSW20_Pos        (4UL)       /*!< CHSW20 (Bit 4)                                        */
+ #define R_ADC0_ADSWTSTR1_CHSW20_Msk        (0x10UL)    /*!< CHSW20 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR1_CHSW21_Pos        (5UL)       /*!< CHSW21 (Bit 5)                                        */
+ #define R_ADC0_ADSWTSTR1_CHSW21_Msk        (0x20UL)    /*!< CHSW21 (Bitfield-Mask: 0x01)                          */
+/* =======================================================  ADSWTSTR2  ======================================================= */
+ #define R_ADC0_ADSWTSTR2_EX0SW_Pos         (0UL)       /*!< EX0SW (Bit 0)                                         */
+ #define R_ADC0_ADSWTSTR2_EX0SW_Msk         (0x1UL)     /*!< EX0SW (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADSWTSTR2_EX1SW_Pos         (1UL)       /*!< EX1SW (Bit 1)                                         */
+ #define R_ADC0_ADSWTSTR2_EX1SW_Msk         (0x2UL)     /*!< EX1SW (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos       (4UL)       /*!< SHBYPS0 (Bit 4)                                       */
+ #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk       (0x10UL)    /*!< SHBYPS0 (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos       (5UL)       /*!< SHBYPS1 (Bit 5)                                       */
+ #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk       (0x20UL)    /*!< SHBYPS1 (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos       (6UL)       /*!< SHBYPS2 (Bit 6)                                       */
+ #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk       (0x40UL)    /*!< SHBYPS2 (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADSWTSTR2_GRP0SW_Pos        (8UL)       /*!< GRP0SW (Bit 8)                                        */
+ #define R_ADC0_ADSWTSTR2_GRP0SW_Msk        (0x100UL)   /*!< GRP0SW (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR2_GRP1SW_Pos        (9UL)       /*!< GRP1SW (Bit 9)                                        */
+ #define R_ADC0_ADSWTSTR2_GRP1SW_Msk        (0x200UL)   /*!< GRP1SW (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR2_GRP2SW_Pos        (10UL)      /*!< GRP2SW (Bit 10)                                       */
+ #define R_ADC0_ADSWTSTR2_GRP2SW_Msk        (0x400UL)   /*!< GRP2SW (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR2_GRP3SW_Pos        (11UL)      /*!< GRP3SW (Bit 11)                                       */
+ #define R_ADC0_ADSWTSTR2_GRP3SW_Msk        (0x800UL)   /*!< GRP3SW (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos      (12UL)      /*!< GRPEX1SW (Bit 12)                                     */
+ #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk      (0x1000UL)  /*!< GRPEX1SW (Bitfield-Mask: 0x01)                        */
+/* ========================================================  ADSWCR  ========================================================= */
+ #define R_ADC0_ADSWCR_ADSWREF_Pos          (0UL)       /*!< ADSWREF (Bit 0)                                       */
+ #define R_ADC0_ADSWCR_ADSWREF_Msk          (0x7UL)     /*!< ADSWREF (Bitfield-Mask: 0x07)                         */
+ #define R_ADC0_ADSWCR_SHSWREF_Pos          (4UL)       /*!< SHSWREF (Bit 4)                                       */
+ #define R_ADC0_ADSWCR_SHSWREF_Msk          (0x70UL)    /*!< SHSWREF (Bitfield-Mask: 0x07)                         */
+/* ========================================================  ADGSCS  ========================================================= */
+ #define R_ADC0_ADGSCS_CHSELGB_Pos          (0UL)       /*!< CHSELGB (Bit 0)                                       */
+ #define R_ADC0_ADGSCS_CHSELGB_Msk          (0xffUL)    /*!< CHSELGB (Bitfield-Mask: 0xff)                         */
+ #define R_ADC0_ADGSCS_CHSELGA_Pos          (8UL)       /*!< CHSELGA (Bit 8)                                       */
+ #define R_ADC0_ADGSCS_CHSELGA_Msk          (0xff00UL)  /*!< CHSELGA (Bitfield-Mask: 0xff)                         */
+/* =========================================================  ADSER  ========================================================= */
+ #define R_ADC0_ADSER_SMPEX_Pos             (7UL)       /*!< SMPEX (Bit 7)                                         */
+ #define R_ADC0_ADSER_SMPEX_Msk             (0x80UL)    /*!< SMPEX (Bitfield-Mask: 0x01)                           */
+/* ========================================================  ADBUF0  ========================================================= */
+ #define R_ADC0_ADBUF0_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF0_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF1  ========================================================= */
+ #define R_ADC0_ADBUF1_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF1_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF2  ========================================================= */
+ #define R_ADC0_ADBUF2_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF2_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF3  ========================================================= */
+ #define R_ADC0_ADBUF3_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF3_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF4  ========================================================= */
+ #define R_ADC0_ADBUF4_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF4_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF5  ========================================================= */
+ #define R_ADC0_ADBUF5_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF5_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF6  ========================================================= */
+ #define R_ADC0_ADBUF6_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF6_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF7  ========================================================= */
+ #define R_ADC0_ADBUF7_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF7_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF8  ========================================================= */
+ #define R_ADC0_ADBUF8_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF8_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF9  ========================================================= */
+ #define R_ADC0_ADBUF9_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF9_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF10  ======================================================== */
+ #define R_ADC0_ADBUF10_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF10_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF11  ======================================================== */
+ #define R_ADC0_ADBUF11_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF11_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF12  ======================================================== */
+ #define R_ADC0_ADBUF12_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF12_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF13  ======================================================== */
+ #define R_ADC0_ADBUF13_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF13_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF14  ======================================================== */
+ #define R_ADC0_ADBUF14_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF14_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF15  ======================================================== */
+ #define R_ADC0_ADBUF15_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF15_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUFEN  ======================================================== */
+ #define R_ADC0_ADBUFEN_BUFEN_Pos           (0UL)       /*!< BUFEN (Bit 0)                                         */
+ #define R_ADC0_ADBUFEN_BUFEN_Msk           (0x1UL)     /*!< BUFEN (Bitfield-Mask: 0x01)                           */
+/* =======================================================  ADBUFPTR  ======================================================== */
+ #define R_ADC0_ADBUFPTR_BUFPTR_Pos         (0UL)       /*!< BUFPTR (Bit 0)                                        */
+ #define R_ADC0_ADBUFPTR_BUFPTR_Msk         (0xfUL)     /*!< BUFPTR (Bitfield-Mask: 0x0f)                          */
+ #define R_ADC0_ADBUFPTR_PTROVF_Pos         (4UL)       /*!< PTROVF (Bit 4)                                        */
+ #define R_ADC0_ADBUFPTR_PTROVF_Msk         (0x10UL)    /*!< PTROVF (Bitfield-Mask: 0x01)                          */
+/* =======================================================  ADPGADBS0  ======================================================= */
+ #define R_ADC0_ADPGADBS0_P0BIAS_Pos        (0UL)       /*!< P0BIAS (Bit 0)                                        */
+ #define R_ADC0_ADPGADBS0_P0BIAS_Msk        (0x1UL)     /*!< P0BIAS (Bitfield-Mask: 0x01)                          */
+/* =======================================================  ADPGADBS1  ======================================================= */
+ #define R_ADC0_ADPGADBS1_P3BIAS_Pos        (0UL)       /*!< P3BIAS (Bit 0)                                        */
+ #define R_ADC0_ADPGADBS1_P3BIAS_Msk        (0x1UL)     /*!< P3BIAS (Bitfield-Mask: 0x01)                          */
+/* =======================================================  ADREFMON  ======================================================== */
+ #define R_ADC0_ADREFMON_PGAMON_Pos         (0UL)       /*!< PGAMON (Bit 0)                                        */
+ #define R_ADC0_ADREFMON_PGAMON_Msk         (0x7UL)     /*!< PGAMON (Bitfield-Mask: 0x07)                          */
+ #define R_ADC0_ADREFMON_MONSEL_Pos         (16UL)      /*!< MONSEL (Bit 16)                                       */
+ #define R_ADC0_ADREFMON_MONSEL_Msk         (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f)                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_PSCU                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  PSARB  ========================================================= */
+ #define R_PSCU_PSARB_PSARB1_Pos     (1UL)          /*!< PSARB1 (Bit 1)                                        */
+ #define R_PSCU_PSARB_PSARB1_Msk     (0x2UL)        /*!< PSARB1 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARB_PSARB2_Pos     (2UL)          /*!< PSARB2 (Bit 2)                                        */
+ #define R_PSCU_PSARB_PSARB2_Msk     (0x4UL)        /*!< PSARB2 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARB_PSARB3_Pos     (3UL)          /*!< PSARB3 (Bit 3)                                        */
+ #define R_PSCU_PSARB_PSARB3_Msk     (0x8UL)        /*!< PSARB3 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARB_PSARB6_Pos     (6UL)          /*!< PSARB6 (Bit 6)                                        */
+ #define R_PSCU_PSARB_PSARB6_Msk     (0x40UL)       /*!< PSARB6 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARB_PSARB7_Pos     (7UL)          /*!< PSARB7 (Bit 7)                                        */
+ #define R_PSCU_PSARB_PSARB7_Msk     (0x80UL)       /*!< PSARB7 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARB_PSARB8_Pos     (8UL)          /*!< PSARB8 (Bit 8)                                        */
+ #define R_PSCU_PSARB_PSARB8_Msk     (0x100UL)      /*!< PSARB8 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARB_PSARB9_Pos     (9UL)          /*!< PSARB9 (Bit 9)                                        */
+ #define R_PSCU_PSARB_PSARB9_Msk     (0x200UL)      /*!< PSARB9 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARB_PSARB11_Pos    (11UL)         /*!< PSARB11 (Bit 11)                                      */
+ #define R_PSCU_PSARB_PSARB11_Msk    (0x800UL)      /*!< PSARB11 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB12_Pos    (12UL)         /*!< PSARB12 (Bit 12)                                      */
+ #define R_PSCU_PSARB_PSARB12_Msk    (0x1000UL)     /*!< PSARB12 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB15_Pos    (15UL)         /*!< PSARB15 (Bit 15)                                      */
+ #define R_PSCU_PSARB_PSARB15_Msk    (0x8000UL)     /*!< PSARB15 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB16_Pos    (16UL)         /*!< PSARB16 (Bit 16)                                      */
+ #define R_PSCU_PSARB_PSARB16_Msk    (0x10000UL)    /*!< PSARB16 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB18_Pos    (18UL)         /*!< PSARB18 (Bit 18)                                      */
+ #define R_PSCU_PSARB_PSARB18_Msk    (0x40000UL)    /*!< PSARB18 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB19_Pos    (19UL)         /*!< PSARB19 (Bit 19)                                      */
+ #define R_PSCU_PSARB_PSARB19_Msk    (0x80000UL)    /*!< PSARB19 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB22_Pos    (22UL)         /*!< PSARB22 (Bit 22)                                      */
+ #define R_PSCU_PSARB_PSARB22_Msk    (0x400000UL)   /*!< PSARB22 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB23_Pos    (23UL)         /*!< PSARB23 (Bit 23)                                      */
+ #define R_PSCU_PSARB_PSARB23_Msk    (0x800000UL)   /*!< PSARB23 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB24_Pos    (24UL)         /*!< PSARB24 (Bit 24)                                      */
+ #define R_PSCU_PSARB_PSARB24_Msk    (0x1000000UL)  /*!< PSARB24 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB25_Pos    (25UL)         /*!< PSARB25 (Bit 25)                                      */
+ #define R_PSCU_PSARB_PSARB25_Msk    (0x2000000UL)  /*!< PSARB25 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB26_Pos    (26UL)         /*!< PSARB26 (Bit 26)                                      */
+ #define R_PSCU_PSARB_PSARB26_Msk    (0x4000000UL)  /*!< PSARB26 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB27_Pos    (27UL)         /*!< PSARB27 (Bit 27)                                      */
+ #define R_PSCU_PSARB_PSARB27_Msk    (0x8000000UL)  /*!< PSARB27 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB28_Pos    (28UL)         /*!< PSARB28 (Bit 28)                                      */
+ #define R_PSCU_PSARB_PSARB28_Msk    (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB29_Pos    (29UL)         /*!< PSARB29 (Bit 29)                                      */
+ #define R_PSCU_PSARB_PSARB29_Msk    (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB30_Pos    (30UL)         /*!< PSARB30 (Bit 30)                                      */
+ #define R_PSCU_PSARB_PSARB30_Msk    (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB31_Pos    (31UL)         /*!< PSARB31 (Bit 31)                                      */
+ #define R_PSCU_PSARB_PSARB31_Msk    (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01)                         */
+/* =========================================================  PSARC  ========================================================= */
+ #define R_PSCU_PSARC_PSARC0_Pos     (0UL)          /*!< PSARC0 (Bit 0)                                        */
+ #define R_PSCU_PSARC_PSARC0_Msk     (0x1UL)        /*!< PSARC0 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARC_PSARC1_Pos     (1UL)          /*!< PSARC1 (Bit 1)                                        */
+ #define R_PSCU_PSARC_PSARC1_Msk     (0x2UL)        /*!< PSARC1 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARC_PSARC3_Pos     (3UL)          /*!< PSARC3 (Bit 3)                                        */
+ #define R_PSCU_PSARC_PSARC3_Msk     (0x8UL)        /*!< PSARC3 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARC_PSARC8_Pos     (8UL)          /*!< PSARC8 (Bit 8)                                        */
+ #define R_PSCU_PSARC_PSARC8_Msk     (0x100UL)      /*!< PSARC8 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARC_PSARC12_Pos    (12UL)         /*!< PSARC12 (Bit 12)                                      */
+ #define R_PSCU_PSARC_PSARC12_Msk    (0x1000UL)     /*!< PSARC12 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARC_PSARC13_Pos    (13UL)         /*!< PSARC13 (Bit 13)                                      */
+ #define R_PSCU_PSARC_PSARC13_Msk    (0x2000UL)     /*!< PSARC13 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARC_PSARC20_Pos    (20UL)         /*!< PSARC20 (Bit 20)                                      */
+ #define R_PSCU_PSARC_PSARC20_Msk    (0x100000UL)   /*!< PSARC20 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARC_PSARC27_Pos    (27UL)         /*!< PSARC27 (Bit 27)                                      */
+ #define R_PSCU_PSARC_PSARC27_Msk    (0x8000000UL)  /*!< PSARC27 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARC_PSARC31_Pos    (31UL)         /*!< PSARC31 (Bit 31)                                      */
+ #define R_PSCU_PSARC_PSARC31_Msk    (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01)                         */
+/* =========================================================  PSARD  ========================================================= */
+ #define R_PSCU_PSARD_PSARD0_Pos     (0UL)          /*!< PSARD0 (Bit 0)                                        */
+ #define R_PSCU_PSARD_PSARD0_Msk     (0x1UL)        /*!< PSARD0 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARD_PSARD1_Pos     (1UL)          /*!< PSARD1 (Bit 1)                                        */
+ #define R_PSCU_PSARD_PSARD1_Msk     (0x2UL)        /*!< PSARD1 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARD_PSARD2_Pos     (2UL)          /*!< PSARD2 (Bit 2)                                        */
+ #define R_PSCU_PSARD_PSARD2_Msk     (0x4UL)        /*!< PSARD2 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARD_PSARD3_Pos     (3UL)          /*!< PSARD3 (Bit 3)                                        */
+ #define R_PSCU_PSARD_PSARD3_Msk     (0x8UL)        /*!< PSARD3 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARD_PSARD11_Pos    (11UL)         /*!< PSARD11 (Bit 11)                                      */
+ #define R_PSCU_PSARD_PSARD11_Msk    (0x800UL)      /*!< PSARD11 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD12_Pos    (12UL)         /*!< PSARD12 (Bit 12)                                      */
+ #define R_PSCU_PSARD_PSARD12_Msk    (0x1000UL)     /*!< PSARD12 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD13_Pos    (13UL)         /*!< PSARD13 (Bit 13)                                      */
+ #define R_PSCU_PSARD_PSARD13_Msk    (0x2000UL)     /*!< PSARD13 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD14_Pos    (14UL)         /*!< PSARD14 (Bit 14)                                      */
+ #define R_PSCU_PSARD_PSARD14_Msk    (0x4000UL)     /*!< PSARD14 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD15_Pos    (15UL)         /*!< PSARD15 (Bit 15)                                      */
+ #define R_PSCU_PSARD_PSARD15_Msk    (0x8000UL)     /*!< PSARD15 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD16_Pos    (16UL)         /*!< PSARD16 (Bit 16)                                      */
+ #define R_PSCU_PSARD_PSARD16_Msk    (0x10000UL)    /*!< PSARD16 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD19_Pos    (19UL)         /*!< PSARD19 (Bit 19)                                      */
+ #define R_PSCU_PSARD_PSARD19_Msk    (0x80000UL)    /*!< PSARD19 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD20_Pos    (20UL)         /*!< PSARD20 (Bit 20)                                      */
+ #define R_PSCU_PSARD_PSARD20_Msk    (0x100000UL)   /*!< PSARD20 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD22_Pos    (22UL)         /*!< PSARD22 (Bit 22)                                      */
+ #define R_PSCU_PSARD_PSARD22_Msk    (0x400000UL)   /*!< PSARD22 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD25_Pos    (25UL)         /*!< PSARD25 (Bit 25)                                      */
+ #define R_PSCU_PSARD_PSARD25_Msk    (0x2000000UL)  /*!< PSARD25 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD26_Pos    (26UL)         /*!< PSARD26 (Bit 26)                                      */
+ #define R_PSCU_PSARD_PSARD26_Msk    (0x4000000UL)  /*!< PSARD26 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD27_Pos    (27UL)         /*!< PSARD27 (Bit 27)                                      */
+ #define R_PSCU_PSARD_PSARD27_Msk    (0x8000000UL)  /*!< PSARD27 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD28_Pos    (28UL)         /*!< PSARD28 (Bit 28)                                      */
+ #define R_PSCU_PSARD_PSARD28_Msk    (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01)                         */
+/* =========================================================  PSARE  ========================================================= */
+ #define R_PSCU_PSARE_PSARE0_Pos     (0UL)          /*!< PSARE0 (Bit 0)                                        */
+ #define R_PSCU_PSARE_PSARE0_Msk     (0x1UL)        /*!< PSARE0 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARE_PSARE1_Pos     (1UL)          /*!< PSARE1 (Bit 1)                                        */
+ #define R_PSCU_PSARE_PSARE1_Msk     (0x2UL)        /*!< PSARE1 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARE_PSARE2_Pos     (2UL)          /*!< PSARE2 (Bit 2)                                        */
+ #define R_PSCU_PSARE_PSARE2_Msk     (0x4UL)        /*!< PSARE2 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARE_PSARE14_Pos    (14UL)         /*!< PSARE14 (Bit 14)                                      */
+ #define R_PSCU_PSARE_PSARE14_Msk    (0x4000UL)     /*!< PSARE14 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE15_Pos    (15UL)         /*!< PSARE15 (Bit 15)                                      */
+ #define R_PSCU_PSARE_PSARE15_Msk    (0x8000UL)     /*!< PSARE15 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE22_Pos    (22UL)         /*!< PSARE22 (Bit 22)                                      */
+ #define R_PSCU_PSARE_PSARE22_Msk    (0x400000UL)   /*!< PSARE22 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE23_Pos    (23UL)         /*!< PSARE23 (Bit 23)                                      */
+ #define R_PSCU_PSARE_PSARE23_Msk    (0x800000UL)   /*!< PSARE23 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE24_Pos    (24UL)         /*!< PSARE24 (Bit 24)                                      */
+ #define R_PSCU_PSARE_PSARE24_Msk    (0x1000000UL)  /*!< PSARE24 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE25_Pos    (25UL)         /*!< PSARE25 (Bit 25)                                      */
+ #define R_PSCU_PSARE_PSARE25_Msk    (0x2000000UL)  /*!< PSARE25 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE26_Pos    (26UL)         /*!< PSARE26 (Bit 26)                                      */
+ #define R_PSCU_PSARE_PSARE26_Msk    (0x4000000UL)  /*!< PSARE26 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE27_Pos    (27UL)         /*!< PSARE27 (Bit 27)                                      */
+ #define R_PSCU_PSARE_PSARE27_Msk    (0x8000000UL)  /*!< PSARE27 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE28_Pos    (28UL)         /*!< PSARE28 (Bit 28)                                      */
+ #define R_PSCU_PSARE_PSARE28_Msk    (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE29_Pos    (29UL)         /*!< PSARE29 (Bit 29)                                      */
+ #define R_PSCU_PSARE_PSARE29_Msk    (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE30_Pos    (30UL)         /*!< PSARE30 (Bit 30)                                      */
+ #define R_PSCU_PSARE_PSARE30_Msk    (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE31_Pos    (31UL)         /*!< PSARE31 (Bit 31)                                      */
+ #define R_PSCU_PSARE_PSARE31_Msk    (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01)                         */
+/* =========================================================  MSSAR  ========================================================= */
+ #define R_PSCU_MSSAR_MSSAR0_Pos     (0UL)          /*!< MSSAR0 (Bit 0)                                        */
+ #define R_PSCU_MSSAR_MSSAR0_Msk     (0x1UL)        /*!< MSSAR0 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_MSSAR_MSSAR1_Pos     (1UL)          /*!< MSSAR1 (Bit 1)                                        */
+ #define R_PSCU_MSSAR_MSSAR1_Msk     (0x2UL)        /*!< MSSAR1 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_MSSAR_MSSAR2_Pos     (2UL)          /*!< MSSAR2 (Bit 2)                                        */
+ #define R_PSCU_MSSAR_MSSAR2_Msk     (0x4UL)        /*!< MSSAR2 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_MSSAR_MSSAR3_Pos     (3UL)          /*!< MSSAR3 (Bit 3)                                        */
+ #define R_PSCU_MSSAR_MSSAR3_Msk     (0x8UL)        /*!< MSSAR3 (Bitfield-Mask: 0x01)                          */
+/* =======================================================  CFSAMONA  ======================================================== */
+ #define R_PSCU_CFSAMONA_CFS2_Pos    (15UL)         /*!< CFS2 (Bit 15)                                         */
+ #define R_PSCU_CFSAMONA_CFS2_Msk    (0xff8000UL)   /*!< CFS2 (Bitfield-Mask: 0x1ff)                           */
+/* =======================================================  CFSAMONB  ======================================================== */
+ #define R_PSCU_CFSAMONB_CFS1_Pos    (10UL)         /*!< CFS1 (Bit 10)                                         */
+ #define R_PSCU_CFSAMONB_CFS1_Msk    (0xfffc00UL)   /*!< CFS1 (Bitfield-Mask: 0x3fff)                          */
+/* ========================================================  DFSAMON  ======================================================== */
+ #define R_PSCU_DFSAMON_DFS_Pos      (10UL)         /*!< DFS (Bit 10)                                          */
+ #define R_PSCU_DFSAMON_DFS_Msk      (0xfc00UL)     /*!< DFS (Bitfield-Mask: 0x3f)                             */
+/* ========================================================  SSAMONA  ======================================================== */
+ #define R_PSCU_SSAMONA_SS2_Pos      (13UL)         /*!< SS2 (Bit 13)                                          */
+ #define R_PSCU_SSAMONA_SS2_Msk      (0x1fe000UL)   /*!< SS2 (Bitfield-Mask: 0xff)                             */
+/* ========================================================  SSAMONB  ======================================================== */
+ #define R_PSCU_SSAMONB_SS1_Pos      (10UL)         /*!< SS1 (Bit 10)                                          */
+ #define R_PSCU_SSAMONB_SS1_Msk      (0x1ffc00UL)   /*!< SS1 (Bitfield-Mask: 0x7ff)                            */
+/* ========================================================  DLMMON  ========================================================= */
+ #define R_PSCU_DLMMON_DLMMON_Pos    (0UL)          /*!< DLMMON (Bit 0)                                        */
+ #define R_PSCU_DLMMON_DLMMON_Msk    (0xfUL)        /*!< DLMMON (Bitfield-Mask: 0x0f)                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_BUS                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CSRECEN  ======================================================== */
+ #define R_BUS_CSRECEN_RCVENM_Pos    (8UL)     /*!< RCVENM (Bit 8)                                        */
+ #define R_BUS_CSRECEN_RCVENM_Msk    (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01)                          */
+ #define R_BUS_CSRECEN_RCVEN_Pos     (0UL)     /*!< RCVEN (Bit 0)                                         */
+ #define R_BUS_CSRECEN_RCVEN_Msk     (0x1UL)   /*!< RCVEN (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                           R_CAC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  CACR0  ========================================================= */
+ #define R_CAC_CACR0_CFME_Pos         (0UL)      /*!< CFME (Bit 0)                                          */
+ #define R_CAC_CACR0_CFME_Msk         (0x1UL)    /*!< CFME (Bitfield-Mask: 0x01)                            */
+/* =========================================================  CACR1  ========================================================= */
+ #define R_CAC_CACR1_EDGES_Pos        (6UL)      /*!< EDGES (Bit 6)                                         */
+ #define R_CAC_CACR1_EDGES_Msk        (0xc0UL)   /*!< EDGES (Bitfield-Mask: 0x03)                           */
+ #define R_CAC_CACR1_TCSS_Pos         (4UL)      /*!< TCSS (Bit 4)                                          */
+ #define R_CAC_CACR1_TCSS_Msk         (0x30UL)   /*!< TCSS (Bitfield-Mask: 0x03)                            */
+ #define R_CAC_CACR1_FMCS_Pos         (1UL)      /*!< FMCS (Bit 1)                                          */
+ #define R_CAC_CACR1_FMCS_Msk         (0xeUL)    /*!< FMCS (Bitfield-Mask: 0x07)                            */
+ #define R_CAC_CACR1_CACREFE_Pos      (0UL)      /*!< CACREFE (Bit 0)                                       */
+ #define R_CAC_CACR1_CACREFE_Msk      (0x1UL)    /*!< CACREFE (Bitfield-Mask: 0x01)                         */
+/* =========================================================  CACR2  ========================================================= */
+ #define R_CAC_CACR2_DFS_Pos          (6UL)      /*!< DFS (Bit 6)                                           */
+ #define R_CAC_CACR2_DFS_Msk          (0xc0UL)   /*!< DFS (Bitfield-Mask: 0x03)                             */
+ #define R_CAC_CACR2_RCDS_Pos         (4UL)      /*!< RCDS (Bit 4)                                          */
+ #define R_CAC_CACR2_RCDS_Msk         (0x30UL)   /*!< RCDS (Bitfield-Mask: 0x03)                            */
+ #define R_CAC_CACR2_RSCS_Pos         (1UL)      /*!< RSCS (Bit 1)                                          */
+ #define R_CAC_CACR2_RSCS_Msk         (0xeUL)    /*!< RSCS (Bitfield-Mask: 0x07)                            */
+ #define R_CAC_CACR2_RPS_Pos          (0UL)      /*!< RPS (Bit 0)                                           */
+ #define R_CAC_CACR2_RPS_Msk          (0x1UL)    /*!< RPS (Bitfield-Mask: 0x01)                             */
+/* =========================================================  CAICR  ========================================================= */
+ #define R_CAC_CAICR_OVFFCL_Pos       (6UL)      /*!< OVFFCL (Bit 6)                                        */
+ #define R_CAC_CAICR_OVFFCL_Msk       (0x40UL)   /*!< OVFFCL (Bitfield-Mask: 0x01)                          */
+ #define R_CAC_CAICR_MENDFCL_Pos      (5UL)      /*!< MENDFCL (Bit 5)                                       */
+ #define R_CAC_CAICR_MENDFCL_Msk      (0x20UL)   /*!< MENDFCL (Bitfield-Mask: 0x01)                         */
+ #define R_CAC_CAICR_FERRFCL_Pos      (4UL)      /*!< FERRFCL (Bit 4)                                       */
+ #define R_CAC_CAICR_FERRFCL_Msk      (0x10UL)   /*!< FERRFCL (Bitfield-Mask: 0x01)                         */
+ #define R_CAC_CAICR_OVFIE_Pos        (2UL)      /*!< OVFIE (Bit 2)                                         */
+ #define R_CAC_CAICR_OVFIE_Msk        (0x4UL)    /*!< OVFIE (Bitfield-Mask: 0x01)                           */
+ #define R_CAC_CAICR_MENDIE_Pos       (1UL)      /*!< MENDIE (Bit 1)                                        */
+ #define R_CAC_CAICR_MENDIE_Msk       (0x2UL)    /*!< MENDIE (Bitfield-Mask: 0x01)                          */
+ #define R_CAC_CAICR_FERRIE_Pos       (0UL)      /*!< FERRIE (Bit 0)                                        */
+ #define R_CAC_CAICR_FERRIE_Msk       (0x1UL)    /*!< FERRIE (Bitfield-Mask: 0x01)                          */
+/* =========================================================  CASTR  ========================================================= */
+ #define R_CAC_CASTR_OVFF_Pos         (2UL)      /*!< OVFF (Bit 2)                                          */
+ #define R_CAC_CASTR_OVFF_Msk         (0x4UL)    /*!< OVFF (Bitfield-Mask: 0x01)                            */
+ #define R_CAC_CASTR_MENDF_Pos        (1UL)      /*!< MENDF (Bit 1)                                         */
+ #define R_CAC_CASTR_MENDF_Msk        (0x2UL)    /*!< MENDF (Bitfield-Mask: 0x01)                           */
+ #define R_CAC_CASTR_FERRF_Pos        (0UL)      /*!< FERRF (Bit 0)                                         */
+ #define R_CAC_CASTR_FERRF_Msk        (0x1UL)    /*!< FERRF (Bitfield-Mask: 0x01)                           */
+/* ========================================================  CAULVR  ========================================================= */
+ #define R_CAC_CAULVR_CAULVR_Pos      (0UL)      /*!< CAULVR (Bit 0)                                        */
+ #define R_CAC_CAULVR_CAULVR_Msk      (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  CALLVR  ========================================================= */
+ #define R_CAC_CALLVR_CALLVR_Pos      (0UL)      /*!< CALLVR (Bit 0)                                        */
+ #define R_CAC_CALLVR_CALLVR_Msk      (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  CACNTBR  ======================================================== */
+ #define R_CAC_CACNTBR_CACNTBR_Pos    (0UL)      /*!< CACNTBR (Bit 0)                                       */
+ #define R_CAC_CACNTBR_CACNTBR_Msk    (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff)                       */
+
+/* =========================================================================================================================== */
+/* ================                                         R_CANFD0                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CFDGCFG  ======================================================== */
+ #define R_CANFD_CFDGCFG_TPRI_Pos                (0UL)          /*!< TPRI (Bit 0)                                          */
+ #define R_CANFD_CFDGCFG_TPRI_Msk                (0x1UL)        /*!< TPRI (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGCFG_DCE_Pos                 (1UL)          /*!< DCE (Bit 1)                                           */
+ #define R_CANFD_CFDGCFG_DCE_Msk                 (0x2UL)        /*!< DCE (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGCFG_DRE_Pos                 (2UL)          /*!< DRE (Bit 2)                                           */
+ #define R_CANFD_CFDGCFG_DRE_Msk                 (0x4UL)        /*!< DRE (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGCFG_MME_Pos                 (3UL)          /*!< MME (Bit 3)                                           */
+ #define R_CANFD_CFDGCFG_MME_Msk                 (0x8UL)        /*!< MME (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGCFG_DCS_Pos                 (4UL)          /*!< DCS (Bit 4)                                           */
+ #define R_CANFD_CFDGCFG_DCS_Msk                 (0x10UL)       /*!< DCS (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGCFG_CMPOC_Pos               (5UL)          /*!< CMPOC (Bit 5)                                         */
+ #define R_CANFD_CFDGCFG_CMPOC_Msk               (0x20UL)       /*!< CMPOC (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGCFG_TSP_Pos                 (8UL)          /*!< TSP (Bit 8)                                           */
+ #define R_CANFD_CFDGCFG_TSP_Msk                 (0xf00UL)      /*!< TSP (Bitfield-Mask: 0x0f)                             */
+ #define R_CANFD_CFDGCFG_TSSS_Pos                (12UL)         /*!< TSSS (Bit 12)                                         */
+ #define R_CANFD_CFDGCFG_TSSS_Msk                (0x1000UL)     /*!< TSSS (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGCFG_ITRCP_Pos               (16UL)         /*!< ITRCP (Bit 16)                                        */
+ #define R_CANFD_CFDGCFG_ITRCP_Msk               (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  CFDGCTR  ======================================================== */
+ #define R_CANFD_CFDGCTR_GMDC_Pos                (0UL)          /*!< GMDC (Bit 0)                                          */
+ #define R_CANFD_CFDGCTR_GMDC_Msk                (0x3UL)        /*!< GMDC (Bitfield-Mask: 0x03)                            */
+ #define R_CANFD_CFDGCTR_GSLPR_Pos               (2UL)          /*!< GSLPR (Bit 2)                                         */
+ #define R_CANFD_CFDGCTR_GSLPR_Msk               (0x4UL)        /*!< GSLPR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGCTR_DEIE_Pos                (8UL)          /*!< DEIE (Bit 8)                                          */
+ #define R_CANFD_CFDGCTR_DEIE_Msk                (0x100UL)      /*!< DEIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGCTR_MEIE_Pos                (9UL)          /*!< MEIE (Bit 9)                                          */
+ #define R_CANFD_CFDGCTR_MEIE_Msk                (0x200UL)      /*!< MEIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGCTR_THLEIE_Pos              (10UL)         /*!< THLEIE (Bit 10)                                       */
+ #define R_CANFD_CFDGCTR_THLEIE_Msk              (0x400UL)      /*!< THLEIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDGCTR_CMPOFIE_Pos             (11UL)         /*!< CMPOFIE (Bit 11)                                      */
+ #define R_CANFD_CFDGCTR_CMPOFIE_Msk             (0x800UL)      /*!< CMPOFIE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGCTR_TSRST_Pos               (16UL)         /*!< TSRST (Bit 16)                                        */
+ #define R_CANFD_CFDGCTR_TSRST_Msk               (0x10000UL)    /*!< TSRST (Bitfield-Mask: 0x01)                           */
+/* ========================================================  CFDGSTS  ======================================================== */
+ #define R_CANFD_CFDGSTS_GRSTSTS_Pos             (0UL)          /*!< GRSTSTS (Bit 0)                                       */
+ #define R_CANFD_CFDGSTS_GRSTSTS_Msk             (0x1UL)        /*!< GRSTSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGSTS_GHLTSTS_Pos             (1UL)          /*!< GHLTSTS (Bit 1)                                       */
+ #define R_CANFD_CFDGSTS_GHLTSTS_Msk             (0x2UL)        /*!< GHLTSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGSTS_GSLPSTS_Pos             (2UL)          /*!< GSLPSTS (Bit 2)                                       */
+ #define R_CANFD_CFDGSTS_GSLPSTS_Msk             (0x4UL)        /*!< GSLPSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGSTS_GRAMINIT_Pos            (3UL)          /*!< GRAMINIT (Bit 3)                                      */
+ #define R_CANFD_CFDGSTS_GRAMINIT_Msk            (0x8UL)        /*!< GRAMINIT (Bitfield-Mask: 0x01)                        */
+/* =======================================================  CFDGERFL  ======================================================== */
+ #define R_CANFD_CFDGERFL_DEF_Pos                (0UL)          /*!< DEF (Bit 0)                                           */
+ #define R_CANFD_CFDGERFL_DEF_Msk                (0x1UL)        /*!< DEF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGERFL_MES_Pos                (1UL)          /*!< MES (Bit 1)                                           */
+ #define R_CANFD_CFDGERFL_MES_Msk                (0x2UL)        /*!< MES (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGERFL_THLES_Pos              (2UL)          /*!< THLES (Bit 2)                                         */
+ #define R_CANFD_CFDGERFL_THLES_Msk              (0x4UL)        /*!< THLES (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGERFL_CMPOF_Pos              (3UL)          /*!< CMPOF (Bit 3)                                         */
+ #define R_CANFD_CFDGERFL_CMPOF_Msk              (0x8UL)        /*!< CMPOF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGERFL_EEF0_Pos               (16UL)         /*!< EEF0 (Bit 16)                                         */
+ #define R_CANFD_CFDGERFL_EEF0_Msk               (0x10000UL)    /*!< EEF0 (Bitfield-Mask: 0x01)                            */
+/* ========================================================  CFDGTSC  ======================================================== */
+ #define R_CANFD_CFDGTSC_TS_Pos                  (0UL)          /*!< TS (Bit 0)                                            */
+ #define R_CANFD_CFDGTSC_TS_Msk                  (0xffffUL)     /*!< TS (Bitfield-Mask: 0xffff)                            */
+/* ======================================================  CFDGAFLECTR  ====================================================== */
+ #define R_CANFD_CFDGAFLECTR_AFLPN_Pos           (0UL)          /*!< AFLPN (Bit 0)                                         */
+ #define R_CANFD_CFDGAFLECTR_AFLPN_Msk           (0xfUL)        /*!< AFLPN (Bitfield-Mask: 0x0f)                           */
+ #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos          (8UL)          /*!< AFLDAE (Bit 8)                                        */
+ #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk          (0x100UL)      /*!< AFLDAE (Bitfield-Mask: 0x01)                          */
+/* ======================================================  CFDGAFLCFG0  ====================================================== */
+ #define R_CANFD_CFDGAFLCFG0_RNC1_Pos            (0UL)          /*!< RNC1 (Bit 0)                                          */
+ #define R_CANFD_CFDGAFLCFG0_RNC1_Msk            (0x1ffUL)      /*!< RNC1 (Bitfield-Mask: 0x1ff)                           */
+ #define R_CANFD_CFDGAFLCFG0_RNC0_Pos            (16UL)         /*!< RNC0 (Bit 16)                                         */
+ #define R_CANFD_CFDGAFLCFG0_RNC0_Msk            (0x1ff0000UL)  /*!< RNC0 (Bitfield-Mask: 0x1ff)                           */
+/* ========================================================  CFDRMNB  ======================================================== */
+ #define R_CANFD_CFDRMNB_NRXMB_Pos               (0UL)          /*!< NRXMB (Bit 0)                                         */
+ #define R_CANFD_CFDRMNB_NRXMB_Msk               (0xffUL)       /*!< NRXMB (Bitfield-Mask: 0xff)                           */
+ #define R_CANFD_CFDRMNB_RMPLS_Pos               (8UL)          /*!< RMPLS (Bit 8)                                         */
+ #define R_CANFD_CFDRMNB_RMPLS_Msk               (0x700UL)      /*!< RMPLS (Bitfield-Mask: 0x07)                           */
+/* =======================================================  CFDRMND0  ======================================================== */
+ #define R_CANFD_CFDRMND0_RMNSu_Pos              (0UL)          /*!< RMNSu (Bit 0)                                         */
+ #define R_CANFD_CFDRMND0_RMNSu_Msk              (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff)                     */
+/* =======================================================  CFDRMIEC  ======================================================== */
+ #define R_CANFD_CFDRMIEC_RMIE_Pos               (0UL)          /*!< RMIE (Bit 0)                                          */
+ #define R_CANFD_CFDRMIEC_RMIE_Msk               (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff)                      */
+/* ========================================================  CFDRFCC  ======================================================== */
+ #define R_CANFD_CFDRFCC_RFE_Pos                 (0UL)          /*!< RFE (Bit 0)                                           */
+ #define R_CANFD_CFDRFCC_RFE_Msk                 (0x1UL)        /*!< RFE (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDRFCC_RFIE_Pos                (1UL)          /*!< RFIE (Bit 1)                                          */
+ #define R_CANFD_CFDRFCC_RFIE_Msk                (0x2UL)        /*!< RFIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDRFCC_RFPLS_Pos               (4UL)          /*!< RFPLS (Bit 4)                                         */
+ #define R_CANFD_CFDRFCC_RFPLS_Msk               (0x70UL)       /*!< RFPLS (Bitfield-Mask: 0x07)                           */
+ #define R_CANFD_CFDRFCC_RFDC_Pos                (8UL)          /*!< RFDC (Bit 8)                                          */
+ #define R_CANFD_CFDRFCC_RFDC_Msk                (0x700UL)      /*!< RFDC (Bitfield-Mask: 0x07)                            */
+ #define R_CANFD_CFDRFCC_RFIM_Pos                (12UL)         /*!< RFIM (Bit 12)                                         */
+ #define R_CANFD_CFDRFCC_RFIM_Msk                (0x1000UL)     /*!< RFIM (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDRFCC_RFIGCV_Pos              (13UL)         /*!< RFIGCV (Bit 13)                                       */
+ #define R_CANFD_CFDRFCC_RFIGCV_Msk              (0xe000UL)     /*!< RFIGCV (Bitfield-Mask: 0x07)                          */
+/* =======================================================  CFDRFSTS  ======================================================== */
+ #define R_CANFD_CFDRFSTS_RFEMP_Pos              (0UL)          /*!< RFEMP (Bit 0)                                         */
+ #define R_CANFD_CFDRFSTS_RFEMP_Msk              (0x1UL)        /*!< RFEMP (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRFSTS_RFFLL_Pos              (1UL)          /*!< RFFLL (Bit 1)                                         */
+ #define R_CANFD_CFDRFSTS_RFFLL_Msk              (0x2UL)        /*!< RFFLL (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRFSTS_RFMLT_Pos              (2UL)          /*!< RFMLT (Bit 2)                                         */
+ #define R_CANFD_CFDRFSTS_RFMLT_Msk              (0x4UL)        /*!< RFMLT (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRFSTS_RFIF_Pos               (3UL)          /*!< RFIF (Bit 3)                                          */
+ #define R_CANFD_CFDRFSTS_RFIF_Msk               (0x8UL)        /*!< RFIF (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDRFSTS_RFMC_Pos               (8UL)          /*!< RFMC (Bit 8)                                          */
+ #define R_CANFD_CFDRFSTS_RFMC_Msk               (0xff00UL)     /*!< RFMC (Bitfield-Mask: 0xff)                            */
+/* =======================================================  CFDRFPCTR  ======================================================= */
+ #define R_CANFD_CFDRFPCTR_RFPC_Pos              (0UL)          /*!< RFPC (Bit 0)                                          */
+ #define R_CANFD_CFDRFPCTR_RFPC_Msk              (0xffUL)       /*!< RFPC (Bitfield-Mask: 0xff)                            */
+/* ========================================================  CFDCFCC  ======================================================== */
+ #define R_CANFD_CFDCFCC_CFE_Pos                 (0UL)          /*!< CFE (Bit 0)                                           */
+ #define R_CANFD_CFDCFCC_CFE_Msk                 (0x1UL)        /*!< CFE (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDCFCC_CFRXIE_Pos              (1UL)          /*!< CFRXIE (Bit 1)                                        */
+ #define R_CANFD_CFDCFCC_CFRXIE_Msk              (0x2UL)        /*!< CFRXIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFCC_CFTXIE_Pos              (2UL)          /*!< CFTXIE (Bit 2)                                        */
+ #define R_CANFD_CFDCFCC_CFTXIE_Msk              (0x4UL)        /*!< CFTXIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFCC_CFPLS_Pos               (4UL)          /*!< CFPLS (Bit 4)                                         */
+ #define R_CANFD_CFDCFCC_CFPLS_Msk               (0x70UL)       /*!< CFPLS (Bitfield-Mask: 0x07)                           */
+ #define R_CANFD_CFDCFCC_CFM_Pos                 (8UL)          /*!< CFM (Bit 8)                                           */
+ #define R_CANFD_CFDCFCC_CFM_Msk                 (0x300UL)      /*!< CFM (Bitfield-Mask: 0x03)                             */
+ #define R_CANFD_CFDCFCC_CFITSS_Pos              (10UL)         /*!< CFITSS (Bit 10)                                       */
+ #define R_CANFD_CFDCFCC_CFITSS_Msk              (0x400UL)      /*!< CFITSS (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFCC_CFITR_Pos               (11UL)         /*!< CFITR (Bit 11)                                        */
+ #define R_CANFD_CFDCFCC_CFITR_Msk               (0x800UL)      /*!< CFITR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCFCC_CFIM_Pos                (12UL)         /*!< CFIM (Bit 12)                                         */
+ #define R_CANFD_CFDCFCC_CFIM_Msk                (0x1000UL)     /*!< CFIM (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDCFCC_CFIGCV_Pos              (13UL)         /*!< CFIGCV (Bit 13)                                       */
+ #define R_CANFD_CFDCFCC_CFIGCV_Msk              (0xe000UL)     /*!< CFIGCV (Bitfield-Mask: 0x07)                          */
+ #define R_CANFD_CFDCFCC_CFTML_Pos               (16UL)         /*!< CFTML (Bit 16)                                        */
+ #define R_CANFD_CFDCFCC_CFTML_Msk               (0x1f0000UL)   /*!< CFTML (Bitfield-Mask: 0x1f)                           */
+ #define R_CANFD_CFDCFCC_CFDC_Pos                (21UL)         /*!< CFDC (Bit 21)                                         */
+ #define R_CANFD_CFDCFCC_CFDC_Msk                (0xe00000UL)   /*!< CFDC (Bitfield-Mask: 0x07)                            */
+ #define R_CANFD_CFDCFCC_CFITT_Pos               (24UL)         /*!< CFITT (Bit 24)                                        */
+ #define R_CANFD_CFDCFCC_CFITT_Msk               (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff)                           */
+/* =======================================================  CFDCFSTS  ======================================================== */
+ #define R_CANFD_CFDCFSTS_CFEMP_Pos              (0UL)          /*!< CFEMP (Bit 0)                                         */
+ #define R_CANFD_CFDCFSTS_CFEMP_Msk              (0x1UL)        /*!< CFEMP (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCFSTS_CFFLL_Pos              (1UL)          /*!< CFFLL (Bit 1)                                         */
+ #define R_CANFD_CFDCFSTS_CFFLL_Msk              (0x2UL)        /*!< CFFLL (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCFSTS_CFMLT_Pos              (2UL)          /*!< CFMLT (Bit 2)                                         */
+ #define R_CANFD_CFDCFSTS_CFMLT_Msk              (0x4UL)        /*!< CFMLT (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCFSTS_CFRXIF_Pos             (3UL)          /*!< CFRXIF (Bit 3)                                        */
+ #define R_CANFD_CFDCFSTS_CFRXIF_Msk             (0x8UL)        /*!< CFRXIF (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFSTS_CFTXIF_Pos             (4UL)          /*!< CFTXIF (Bit 4)                                        */
+ #define R_CANFD_CFDCFSTS_CFTXIF_Msk             (0x10UL)       /*!< CFTXIF (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFSTS_CFMC_Pos               (8UL)          /*!< CFMC (Bit 8)                                          */
+ #define R_CANFD_CFDCFSTS_CFMC_Msk               (0xff00UL)     /*!< CFMC (Bitfield-Mask: 0xff)                            */
+/* =======================================================  CFDCFPCTR  ======================================================= */
+ #define R_CANFD_CFDCFPCTR_CFPC_Pos              (0UL)          /*!< CFPC (Bit 0)                                          */
+ #define R_CANFD_CFDCFPCTR_CFPC_Msk              (0xffUL)       /*!< CFPC (Bitfield-Mask: 0xff)                            */
+/* =======================================================  CFDFESTS  ======================================================== */
+ #define R_CANFD_CFDFESTS_RFXEMP_Pos             (0UL)          /*!< RFXEMP (Bit 0)                                        */
+ #define R_CANFD_CFDFESTS_RFXEMP_Msk             (0x3UL)        /*!< RFXEMP (Bitfield-Mask: 0x03)                          */
+ #define R_CANFD_CFDFESTS_CFXEMP_Pos             (8UL)          /*!< CFXEMP (Bit 8)                                        */
+ #define R_CANFD_CFDFESTS_CFXEMP_Msk             (0x100UL)      /*!< CFXEMP (Bitfield-Mask: 0x01)                          */
+/* =======================================================  CFDFFSTS  ======================================================== */
+ #define R_CANFD_CFDFFSTS_RFXFLL_Pos             (0UL)          /*!< RFXFLL (Bit 0)                                        */
+ #define R_CANFD_CFDFFSTS_RFXFLL_Msk             (0x3UL)        /*!< RFXFLL (Bitfield-Mask: 0x03)                          */
+ #define R_CANFD_CFDFFSTS_CFXFLL_Pos             (8UL)          /*!< CFXFLL (Bit 8)                                        */
+ #define R_CANFD_CFDFFSTS_CFXFLL_Msk             (0x100UL)      /*!< CFXFLL (Bitfield-Mask: 0x01)                          */
+/* =======================================================  CFDFMSTS  ======================================================== */
+ #define R_CANFD_CFDFMSTS_RFXMLT_Pos             (0UL)          /*!< RFXMLT (Bit 0)                                        */
+ #define R_CANFD_CFDFMSTS_RFXMLT_Msk             (0x3UL)        /*!< RFXMLT (Bitfield-Mask: 0x03)                          */
+ #define R_CANFD_CFDFMSTS_CFXMLT_Pos             (8UL)          /*!< CFXMLT (Bit 8)                                        */
+ #define R_CANFD_CFDFMSTS_CFXMLT_Msk             (0x100UL)      /*!< CFXMLT (Bitfield-Mask: 0x01)                          */
+/* =======================================================  CFDRFISTS  ======================================================= */
+ #define R_CANFD_CFDRFISTS_RFXIF_Pos             (0UL)          /*!< RFXIF (Bit 0)                                         */
+ #define R_CANFD_CFDRFISTS_RFXIF_Msk             (0x1UL)        /*!< RFXIF (Bitfield-Mask: 0x01)                           */
+/* ========================================================  CFDTMC  ========================================================= */
+ #define R_CANFD_CFDTMC_TMTR_Pos                 (0UL)          /*!< TMTR (Bit 0)                                          */
+ #define R_CANFD_CFDTMC_TMTR_Msk                 (0x1UL)        /*!< TMTR (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDTMC_TMTAR_Pos                (1UL)          /*!< TMTAR (Bit 1)                                         */
+ #define R_CANFD_CFDTMC_TMTAR_Msk                (0x2UL)        /*!< TMTAR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTMC_TMOM_Pos                 (2UL)          /*!< TMOM (Bit 2)                                          */
+ #define R_CANFD_CFDTMC_TMOM_Msk                 (0x4UL)        /*!< TMOM (Bitfield-Mask: 0x01)                            */
+/* =======================================================  CFDTMSTS  ======================================================== */
+ #define R_CANFD_CFDTMSTS_TMTSTS_Pos             (0UL)          /*!< TMTSTS (Bit 0)                                        */
+ #define R_CANFD_CFDTMSTS_TMTSTS_Msk             (0x1UL)        /*!< TMTSTS (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTMSTS_TMTRF_Pos              (1UL)          /*!< TMTRF (Bit 1)                                         */
+ #define R_CANFD_CFDTMSTS_TMTRF_Msk              (0x6UL)        /*!< TMTRF (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDTMSTS_TMTRM_Pos              (3UL)          /*!< TMTRM (Bit 3)                                         */
+ #define R_CANFD_CFDTMSTS_TMTRM_Msk              (0x8UL)        /*!< TMTRM (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTMSTS_TMTARM_Pos             (4UL)          /*!< TMTARM (Bit 4)                                        */
+ #define R_CANFD_CFDTMSTS_TMTARM_Msk             (0x10UL)       /*!< TMTARM (Bitfield-Mask: 0x01)                          */
+/* ======================================================  CFDTMTRSTS  ======================================================= */
+ #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos      (0UL)          /*!< CFDTMTRSTSg (Bit 0)                                   */
+ #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk      (0xfUL)        /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f)                     */
+/* ======================================================  CFDTMTARSTS  ====================================================== */
+ #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos    (0UL)          /*!< CFDTMTARSTSg (Bit 0)                                  */
+ #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk    (0xfUL)        /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f)                    */
+/* ======================================================  CFDTMTCSTS  ======================================================= */
+ #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos      (0UL)          /*!< CFDTMTCSTSg (Bit 0)                                   */
+ #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk      (0xfUL)        /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f)                     */
+/* ======================================================  CFDTMTASTS  ======================================================= */
+ #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos      (0UL)          /*!< CFDTMTASTSg (Bit 0)                                   */
+ #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk      (0xfUL)        /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f)                     */
+/* =======================================================  CFDTMIEC  ======================================================== */
+ #define R_CANFD_CFDTMIEC_TMIEg_Pos              (0UL)          /*!< TMIEg (Bit 0)                                         */
+ #define R_CANFD_CFDTMIEC_TMIEg_Msk              (0xfUL)        /*!< TMIEg (Bitfield-Mask: 0x0f)                           */
+/* =======================================================  CFDTXQCC0  ======================================================= */
+ #define R_CANFD_CFDTXQCC0_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
+ #define R_CANFD_CFDTXQCC0_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
+ #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDTXQCC0_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
+ #define R_CANFD_CFDTXQCC0_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTXQCC0_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
+ #define R_CANFD_CFDTXQCC0_TXQDC_Msk             (0x300UL)      /*!< TXQDC (Bitfield-Mask: 0x03)                           */
+/* ======================================================  CFDTXQSTS0  ======================================================= */
+ #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
+ #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
+ #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
+ #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDTXQSTS0_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
+ #define R_CANFD_CFDTXQSTS0_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
+/* ======================================================  CFDTXQPCTR0  ====================================================== */
+ #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
+ #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
+/* =======================================================  CFDTHLCC  ======================================================== */
+ #define R_CANFD_CFDTHLCC_THLE_Pos               (0UL)          /*!< THLE (Bit 0)                                          */
+ #define R_CANFD_CFDTHLCC_THLE_Msk               (0x1UL)        /*!< THLE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDTHLCC_THLIE_Pos              (8UL)          /*!< THLIE (Bit 8)                                         */
+ #define R_CANFD_CFDTHLCC_THLIE_Msk              (0x100UL)      /*!< THLIE (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTHLCC_THLIM_Pos              (9UL)          /*!< THLIM (Bit 9)                                         */
+ #define R_CANFD_CFDTHLCC_THLIM_Msk              (0x200UL)      /*!< THLIM (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTHLCC_THLDTE_Pos             (10UL)         /*!< THLDTE (Bit 10)                                       */
+ #define R_CANFD_CFDTHLCC_THLDTE_Msk             (0x400UL)      /*!< THLDTE (Bitfield-Mask: 0x01)                          */
+/* =======================================================  CFDTHLSTS  ======================================================= */
+ #define R_CANFD_CFDTHLSTS_THLEMP_Pos            (0UL)          /*!< THLEMP (Bit 0)                                        */
+ #define R_CANFD_CFDTHLSTS_THLEMP_Msk            (0x1UL)        /*!< THLEMP (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTHLSTS_THLFLL_Pos            (1UL)          /*!< THLFLL (Bit 1)                                        */
+ #define R_CANFD_CFDTHLSTS_THLFLL_Msk            (0x2UL)        /*!< THLFLL (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTHLSTS_THLELT_Pos            (2UL)          /*!< THLELT (Bit 2)                                        */
+ #define R_CANFD_CFDTHLSTS_THLELT_Msk            (0x4UL)        /*!< THLELT (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTHLSTS_THLIF_Pos             (3UL)          /*!< THLIF (Bit 3)                                         */
+ #define R_CANFD_CFDTHLSTS_THLIF_Msk             (0x8UL)        /*!< THLIF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTHLSTS_THLMC_Pos             (8UL)          /*!< THLMC (Bit 8)                                         */
+ #define R_CANFD_CFDTHLSTS_THLMC_Msk             (0x3f00UL)     /*!< THLMC (Bitfield-Mask: 0x3f)                           */
+/* ======================================================  CFDTHLPCTR  ======================================================= */
+ #define R_CANFD_CFDTHLPCTR_THLPC_Pos            (0UL)          /*!< THLPC (Bit 0)                                         */
+ #define R_CANFD_CFDTHLPCTR_THLPC_Msk            (0xffUL)       /*!< THLPC (Bitfield-Mask: 0xff)                           */
+/* =====================================================  CFDGTINTSTS0  ====================================================== */
+ #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos          (0UL)          /*!< TSIF0 (Bit 0)                                         */
+ #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk          (0x1UL)        /*!< TSIF0 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos          (1UL)          /*!< TAIF0 (Bit 1)                                         */
+ #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk          (0x2UL)        /*!< TAIF0 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos          (2UL)          /*!< TQIF0 (Bit 2)                                         */
+ #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk          (0x4UL)        /*!< TQIF0 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos         (3UL)          /*!< CFTIF0 (Bit 3)                                        */
+ #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk         (0x8UL)        /*!< CFTIF0 (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDGTINTSTS0_THIF0_Pos          (4UL)          /*!< THIF0 (Bit 4)                                         */
+ #define R_CANFD_CFDGTINTSTS0_THIF0_Msk          (0x10UL)       /*!< THIF0 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  CFDGTSTCFG  ======================================================= */
+ #define R_CANFD_CFDGTSTCFG_RTMPS_Pos            (16UL)         /*!< RTMPS (Bit 16)                                        */
+ #define R_CANFD_CFDGTSTCFG_RTMPS_Msk            (0x3ff0000UL)  /*!< RTMPS (Bitfield-Mask: 0x3ff)                          */
+/* ======================================================  CFDGTSTCTR  ======================================================= */
+ #define R_CANFD_CFDGTSTCTR_RTME_Pos             (2UL)          /*!< RTME (Bit 2)                                          */
+ #define R_CANFD_CFDGTSTCTR_RTME_Msk             (0x4UL)        /*!< RTME (Bitfield-Mask: 0x01)                            */
+/* =======================================================  CFDGFDCFG  ======================================================= */
+ #define R_CANFD_CFDGFDCFG_RPED_Pos              (0UL)          /*!< RPED (Bit 0)                                          */
+ #define R_CANFD_CFDGFDCFG_RPED_Msk              (0x1UL)        /*!< RPED (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGFDCFG_TSCCFG_Pos            (8UL)          /*!< TSCCFG (Bit 8)                                        */
+ #define R_CANFD_CFDGFDCFG_TSCCFG_Msk            (0x300UL)      /*!< TSCCFG (Bitfield-Mask: 0x03)                          */
+/* =======================================================  CFDGLOCKK  ======================================================= */
+ #define R_CANFD_CFDGLOCKK_LOCK_Pos              (0UL)          /*!< LOCK (Bit 0)                                          */
+ #define R_CANFD_CFDGLOCKK_LOCK_Msk              (0xffffUL)     /*!< LOCK (Bitfield-Mask: 0xffff)                          */
+/* =====================================================  CFDGAFLIGNENT  ===================================================== */
+ #define R_CANFD_CFDGAFLIGNENT_IRN_Pos           (0UL)          /*!< IRN (Bit 0)                                           */
+ #define R_CANFD_CFDGAFLIGNENT_IRN_Msk           (0x1fUL)       /*!< IRN (Bitfield-Mask: 0x1f)                             */
+/* =====================================================  CFDGAFLIGNCTR  ===================================================== */
+ #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos          (0UL)          /*!< IREN (Bit 0)                                          */
+ #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk          (0x1UL)        /*!< IREN (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos           (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk           (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+/* =======================================================  CFDCDTCT  ======================================================== */
+ #define R_CANFD_CFDCDTCT_RFDMAE0_Pos            (0UL)          /*!< RFDMAE0 (Bit 0)                                       */
+ #define R_CANFD_CFDCDTCT_RFDMAE0_Msk            (0x1UL)        /*!< RFDMAE0 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_RFDMAE1_Pos            (1UL)          /*!< RFDMAE1 (Bit 1)                                       */
+ #define R_CANFD_CFDCDTCT_RFDMAE1_Msk            (0x2UL)        /*!< RFDMAE1 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_CFDMAE0_Pos            (8UL)          /*!< CFDMAE0 (Bit 8)                                       */
+ #define R_CANFD_CFDCDTCT_CFDMAE0_Msk            (0x100UL)      /*!< CFDMAE0 (Bitfield-Mask: 0x01)                         */
+/* =======================================================  CFDCDTSTS  ======================================================= */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos         (0UL)          /*!< RFDMASTS0 (Bit 0)                                     */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk         (0x1UL)        /*!< RFDMASTS0 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos         (1UL)          /*!< RFDMASTS1 (Bit 1)                                     */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk         (0x2UL)        /*!< RFDMASTS1 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos         (8UL)          /*!< CFDMASTS0 (Bit 8)                                     */
+ #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk         (0x100UL)      /*!< CFDMASTS0 (Bitfield-Mask: 0x01)                       */
+/* =======================================================  CFDGRSTC  ======================================================== */
+ #define R_CANFD_CFDGRSTC_SRST_Pos               (0UL)          /*!< SRST (Bit 0)                                          */
+ #define R_CANFD_CFDGRSTC_SRST_Msk               (0x1UL)        /*!< SRST (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGRSTC_KEY_Pos                (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_CANFD_CFDGRSTC_KEY_Msk                (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+/* =======================================================  CFDRPGACC  ======================================================= */
+ #define R_CANFD_CFDRPGACC_RDTA_Pos              (0UL)          /*!< RDTA (Bit 0)                                          */
+ #define R_CANFD_CFDRPGACC_RDTA_Msk              (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff)                      */
+
+/* =========================================================================================================================== */
+/* ================                                           R_CRC                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CRCCR0  ========================================================= */
+ #define R_CRC_CRCCR0_DORCLR_Pos          (7UL)          /*!< DORCLR (Bit 7)                                        */
+ #define R_CRC_CRCCR0_DORCLR_Msk          (0x80UL)       /*!< DORCLR (Bitfield-Mask: 0x01)                          */
+ #define R_CRC_CRCCR0_LMS_Pos             (6UL)          /*!< LMS (Bit 6)                                           */
+ #define R_CRC_CRCCR0_LMS_Msk             (0x40UL)       /*!< LMS (Bitfield-Mask: 0x01)                             */
+ #define R_CRC_CRCCR0_GPS_Pos             (0UL)          /*!< GPS (Bit 0)                                           */
+ #define R_CRC_CRCCR0_GPS_Msk             (0x7UL)        /*!< GPS (Bitfield-Mask: 0x07)                             */
+/* ========================================================  CRCCR1  ========================================================= */
+ #define R_CRC_CRCCR1_CRCSEN_Pos          (7UL)          /*!< CRCSEN (Bit 7)                                        */
+ #define R_CRC_CRCCR1_CRCSEN_Msk          (0x80UL)       /*!< CRCSEN (Bitfield-Mask: 0x01)                          */
+ #define R_CRC_CRCCR1_CRCSWR_Pos          (6UL)          /*!< CRCSWR (Bit 6)                                        */
+ #define R_CRC_CRCCR1_CRCSWR_Msk          (0x40UL)       /*!< CRCSWR (Bitfield-Mask: 0x01)                          */
+/* ========================================================  CRCDIR  ========================================================= */
+ #define R_CRC_CRCDIR_CRCDIR_Pos          (0UL)          /*!< CRCDIR (Bit 0)                                        */
+ #define R_CRC_CRCDIR_CRCDIR_Msk          (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff)                    */
+/* =======================================================  CRCDIR_BY  ======================================================= */
+ #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos    (0UL)          /*!< CRCDIR_BY (Bit 0)                                     */
+ #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk    (0xffUL)       /*!< CRCDIR_BY (Bitfield-Mask: 0xff)                       */
+/* ========================================================  CRCDOR  ========================================================= */
+ #define R_CRC_CRCDOR_CRCDOR_Pos          (0UL)          /*!< CRCDOR (Bit 0)                                        */
+ #define R_CRC_CRCDOR_CRCDOR_Msk          (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff)                    */
+/* =======================================================  CRCDOR_HA  ======================================================= */
+ #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos    (0UL)          /*!< CRCDOR_HA (Bit 0)                                     */
+ #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk    (0xffffUL)     /*!< CRCDOR_HA (Bitfield-Mask: 0xffff)                     */
+/* =======================================================  CRCDOR_BY  ======================================================= */
+ #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos    (0UL)          /*!< CRCDOR_BY (Bit 0)                                     */
+ #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk    (0xffUL)       /*!< CRCDOR_BY (Bitfield-Mask: 0xff)                       */
+/* ========================================================  CRCSAR  ========================================================= */
+ #define R_CRC_CRCSAR_CRCSA_Pos           (0UL)          /*!< CRCSA (Bit 0)                                         */
+ #define R_CRC_CRCSAR_CRCSA_Msk           (0x3fffUL)     /*!< CRCSA (Bitfield-Mask: 0x3fff)                         */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DAC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DACR  ========================================================== */
+ #define R_DAC_DACR_DAE_Pos            (5UL)      /*!< DAE (Bit 5)                                           */
+ #define R_DAC_DACR_DAE_Msk            (0x20UL)   /*!< DAE (Bitfield-Mask: 0x01)                             */
+ #define R_DAC_DACR_DAOE_Pos           (6UL)      /*!< DAOE (Bit 6)                                          */
+ #define R_DAC_DACR_DAOE_Msk           (0x40UL)   /*!< DAOE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  DADR  ========================================================== */
+ #define R_DAC_DADR_DADR_Pos           (0UL)      /*!< DADR (Bit 0)                                          */
+ #define R_DAC_DADR_DADR_Msk           (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  DADPR  ========================================================= */
+ #define R_DAC_DADPR_DPSEL_Pos         (7UL)      /*!< DPSEL (Bit 7)                                         */
+ #define R_DAC_DADPR_DPSEL_Msk         (0x80UL)   /*!< DPSEL (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DAADSCR  ======================================================== */
+ #define R_DAC_DAADSCR_DAADST_Pos      (7UL)      /*!< DAADST (Bit 7)                                        */
+ #define R_DAC_DAADSCR_DAADST_Msk      (0x80UL)   /*!< DAADST (Bitfield-Mask: 0x01)                          */
+/* =======================================================  DAVREFCR  ======================================================== */
+ #define R_DAC_DAVREFCR_REF_Pos        (0UL)      /*!< REF (Bit 0)                                           */
+ #define R_DAC_DAVREFCR_REF_Msk        (0x7UL)    /*!< REF (Bitfield-Mask: 0x07)                             */
+/* =========================================================  DAPC  ========================================================== */
+ #define R_DAC_DAPC_PUMPEN_Pos         (0UL)      /*!< PUMPEN (Bit 0)                                        */
+ #define R_DAC_DAPC_PUMPEN_Msk         (0x1UL)    /*!< PUMPEN (Bitfield-Mask: 0x01)                          */
+/* ========================================================  DAAMPCR  ======================================================== */
+ #define R_DAC_DAAMPCR_DAAMP_Pos       (6UL)      /*!< DAAMP (Bit 6)                                         */
+ #define R_DAC_DAAMPCR_DAAMP_Msk       (0x40UL)   /*!< DAAMP (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DAASWCR  ======================================================== */
+ #define R_DAC_DAASWCR_DAASW1_Pos      (7UL)      /*!< DAASW1 (Bit 7)                                        */
+ #define R_DAC_DAASWCR_DAASW1_Msk      (0x80UL)   /*!< DAASW1 (Bitfield-Mask: 0x01)                          */
+ #define R_DAC_DAASWCR_DAASW0_Pos      (6UL)      /*!< DAASW0 (Bit 6)                                        */
+ #define R_DAC_DAASWCR_DAASW0_Msk      (0x40UL)   /*!< DAASW0 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  DAADUSR  ======================================================== */
+ #define R_DAC_DAADUSR_AMADSEL0_Pos    (0UL)      /*!< AMADSEL0 (Bit 0)                                      */
+ #define R_DAC_DAADUSR_AMADSEL0_Msk    (0x1UL)    /*!< AMADSEL0 (Bitfield-Mask: 0x01)                        */
+ #define R_DAC_DAADUSR_AMADSEL1_Pos    (1UL)      /*!< AMADSEL1 (Bit 1)                                      */
+ #define R_DAC_DAADUSR_AMADSEL1_Msk    (0x2UL)    /*!< AMADSEL1 (Bitfield-Mask: 0x01)                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DEBUG                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  DBGSTR  ========================================================= */
+ #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos        (28UL)         /*!< CDBGPWRUPREQ (Bit 28)                                 */
+ #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk        (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01)                    */
+ #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos        (29UL)         /*!< CDBGPWRUPACK (Bit 29)                                 */
+ #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk        (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01)                    */
+/* =======================================================  DBGSTOPCR  ======================================================= */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos     (24UL)         /*!< DBGSTOP_RPER (Bit 24)                                 */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk     (0x1000000UL)  /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01)                    */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos      (16UL)         /*!< DBGSTOP_LVD (Bit 16)                                  */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk      (0x10000UL)    /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01)                     */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos    (25UL)         /*!< DBGSTOP_RECCR (Bit 25)                                */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk    (0x2000000UL)  /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01)                   */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos     (0UL)          /*!< DBGSTOP_IWDT (Bit 0)                                  */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk     (0x1UL)        /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01)                    */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos      (1UL)          /*!< DBGSTOP_WDT (Bit 1)                                   */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk      (0x2UL)        /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01)                     */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos     (31UL)         /*!< DBGSTOP_CPER (Bit 31)                                 */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk     (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01)                    */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DMA                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DMAST  ========================================================= */
+ #define R_DMA_DMAST_DMST_Pos         (0UL)       /*!< DMST (Bit 0)                                          */
+ #define R_DMA_DMAST_DMST_Msk         (0x1UL)     /*!< DMST (Bitfield-Mask: 0x01)                            */
+/* ========================================================  DMECHR  ========================================================= */
+ #define R_DMA_DMECHR_DMECH_Pos       (0UL)       /*!< DMECH (Bit 0)                                         */
+ #define R_DMA_DMECHR_DMECH_Msk       (0x7UL)     /*!< DMECH (Bitfield-Mask: 0x07)                           */
+ #define R_DMA_DMECHR_DMECHSAM_Pos    (8UL)       /*!< DMECHSAM (Bit 8)                                      */
+ #define R_DMA_DMECHR_DMECHSAM_Msk    (0x100UL)   /*!< DMECHSAM (Bitfield-Mask: 0x01)                        */
+ #define R_DMA_DMECHR_DMESTA_Pos      (16UL)      /*!< DMESTA (Bit 16)                                       */
+ #define R_DMA_DMECHR_DMESTA_Msk      (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01)                          */
+/* =========================================================  DELSR  ========================================================= */
+ #define R_DMA_DELSR_IR_Pos           (16UL)      /*!< IR (Bit 16)                                           */
+ #define R_DMA_DELSR_IR_Msk           (0x10000UL) /*!< IR (Bitfield-Mask: 0x01)                              */
+ #define R_DMA_DELSR_DELS_Pos         (0UL)       /*!< DELS (Bit 0)                                          */
+ #define R_DMA_DELSR_DELS_Msk         (0x1ffUL)   /*!< DELS (Bitfield-Mask: 0x1ff)                           */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DMAC0                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DMSAR  ========================================================= */
+ #define R_DMAC0_DMSAR_DMSAR_Pos     (0UL)          /*!< DMSAR (Bit 0)                                         */
+ #define R_DMAC0_DMSAR_DMSAR_Msk     (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  DMDAR  ========================================================= */
+ #define R_DMAC0_DMDAR_DMDAR_Pos     (0UL)          /*!< DMDAR (Bit 0)                                         */
+ #define R_DMAC0_DMDAR_DMDAR_Msk     (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  DMCRA  ========================================================= */
+ #define R_DMAC0_DMCRA_DMCRAH_Pos    (16UL)         /*!< DMCRAH (Bit 16)                                       */
+ #define R_DMAC0_DMCRA_DMCRAH_Msk    (0x3ff0000UL)  /*!< DMCRAH (Bitfield-Mask: 0x3ff)                         */
+ #define R_DMAC0_DMCRA_DMCRAL_Pos    (0UL)          /*!< DMCRAL (Bit 0)                                        */
+ #define R_DMAC0_DMCRA_DMCRAL_Msk    (0xffffUL)     /*!< DMCRAL (Bitfield-Mask: 0xffff)                        */
+/* =========================================================  DMCRB  ========================================================= */
+ #define R_DMAC0_DMCRB_DMCRBL_Pos    (0UL)          /*!< DMCRBL (Bit 0)                                        */
+ #define R_DMAC0_DMCRB_DMCRBL_Msk    (0xffffUL)     /*!< DMCRBL (Bitfield-Mask: 0xffff)                        */
+ #define R_DMAC0_DMCRB_DMCRBH_Pos    (16UL)         /*!< DMCRBH (Bit 16)                                       */
+ #define R_DMAC0_DMCRB_DMCRBH_Msk    (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff)                        */
+/* =========================================================  DMTMD  ========================================================= */
+ #define R_DMAC0_DMTMD_MD_Pos        (14UL)         /*!< MD (Bit 14)                                           */
+ #define R_DMAC0_DMTMD_MD_Msk        (0xc000UL)     /*!< MD (Bitfield-Mask: 0x03)                              */
+ #define R_DMAC0_DMTMD_DTS_Pos       (12UL)         /*!< DTS (Bit 12)                                          */
+ #define R_DMAC0_DMTMD_DTS_Msk       (0x3000UL)     /*!< DTS (Bitfield-Mask: 0x03)                             */
+ #define R_DMAC0_DMTMD_SZ_Pos        (8UL)          /*!< SZ (Bit 8)                                            */
+ #define R_DMAC0_DMTMD_SZ_Msk        (0x300UL)      /*!< SZ (Bitfield-Mask: 0x03)                              */
+ #define R_DMAC0_DMTMD_DCTG_Pos      (0UL)          /*!< DCTG (Bit 0)                                          */
+ #define R_DMAC0_DMTMD_DCTG_Msk      (0x3UL)        /*!< DCTG (Bitfield-Mask: 0x03)                            */
+ #define R_DMAC0_DMTMD_TKP_Pos       (10UL)         /*!< TKP (Bit 10)                                          */
+ #define R_DMAC0_DMTMD_TKP_Msk       (0x400UL)      /*!< TKP (Bitfield-Mask: 0x01)                             */
+/* =========================================================  DMINT  ========================================================= */
+ #define R_DMAC0_DMINT_DTIE_Pos      (4UL)          /*!< DTIE (Bit 4)                                          */
+ #define R_DMAC0_DMINT_DTIE_Msk      (0x10UL)       /*!< DTIE (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_DMINT_ESIE_Pos      (3UL)          /*!< ESIE (Bit 3)                                          */
+ #define R_DMAC0_DMINT_ESIE_Msk      (0x8UL)        /*!< ESIE (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_DMINT_RPTIE_Pos     (2UL)          /*!< RPTIE (Bit 2)                                         */
+ #define R_DMAC0_DMINT_RPTIE_Msk     (0x4UL)        /*!< RPTIE (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_DMINT_SARIE_Pos     (1UL)          /*!< SARIE (Bit 1)                                         */
+ #define R_DMAC0_DMINT_SARIE_Msk     (0x2UL)        /*!< SARIE (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_DMINT_DARIE_Pos     (0UL)          /*!< DARIE (Bit 0)                                         */
+ #define R_DMAC0_DMINT_DARIE_Msk     (0x1UL)        /*!< DARIE (Bitfield-Mask: 0x01)                           */
+/* =========================================================  DMAMD  ========================================================= */
+ #define R_DMAC0_DMAMD_SM_Pos        (14UL)         /*!< SM (Bit 14)                                           */
+ #define R_DMAC0_DMAMD_SM_Msk        (0xc000UL)     /*!< SM (Bitfield-Mask: 0x03)                              */
+ #define R_DMAC0_DMAMD_SARA_Pos      (8UL)          /*!< SARA (Bit 8)                                          */
+ #define R_DMAC0_DMAMD_SARA_Msk      (0x1f00UL)     /*!< SARA (Bitfield-Mask: 0x1f)                            */
+ #define R_DMAC0_DMAMD_DM_Pos        (6UL)          /*!< DM (Bit 6)                                            */
+ #define R_DMAC0_DMAMD_DM_Msk        (0xc0UL)       /*!< DM (Bitfield-Mask: 0x03)                              */
+ #define R_DMAC0_DMAMD_DARA_Pos      (0UL)          /*!< DARA (Bit 0)                                          */
+ #define R_DMAC0_DMAMD_DARA_Msk      (0x1fUL)       /*!< DARA (Bitfield-Mask: 0x1f)                            */
+ #define R_DMAC0_DMAMD_DADR_Pos      (5UL)          /*!< DADR (Bit 5)                                          */
+ #define R_DMAC0_DMAMD_DADR_Msk      (0x20UL)       /*!< DADR (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_DMAMD_SADR_Pos      (13UL)         /*!< SADR (Bit 13)                                         */
+ #define R_DMAC0_DMAMD_SADR_Msk      (0x2000UL)     /*!< SADR (Bitfield-Mask: 0x01)                            */
+/* =========================================================  DMOFR  ========================================================= */
+ #define R_DMAC0_DMOFR_DMOFR_Pos     (0UL)          /*!< DMOFR (Bit 0)                                         */
+ #define R_DMAC0_DMOFR_DMOFR_Msk     (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  DMCNT  ========================================================= */
+ #define R_DMAC0_DMCNT_DTE_Pos       (0UL)          /*!< DTE (Bit 0)                                           */
+ #define R_DMAC0_DMCNT_DTE_Msk       (0x1UL)        /*!< DTE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  DMREQ  ========================================================= */
+ #define R_DMAC0_DMREQ_CLRS_Pos      (4UL)          /*!< CLRS (Bit 4)                                          */
+ #define R_DMAC0_DMREQ_CLRS_Msk      (0x10UL)       /*!< CLRS (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_DMREQ_SWREQ_Pos     (0UL)          /*!< SWREQ (Bit 0)                                         */
+ #define R_DMAC0_DMREQ_SWREQ_Msk     (0x1UL)        /*!< SWREQ (Bitfield-Mask: 0x01)                           */
+/* =========================================================  DMSTS  ========================================================= */
+ #define R_DMAC0_DMSTS_ACT_Pos       (7UL)          /*!< ACT (Bit 7)                                           */
+ #define R_DMAC0_DMSTS_ACT_Msk       (0x80UL)       /*!< ACT (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_DMSTS_DTIF_Pos      (4UL)          /*!< DTIF (Bit 4)                                          */
+ #define R_DMAC0_DMSTS_DTIF_Msk      (0x10UL)       /*!< DTIF (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_DMSTS_ESIF_Pos      (0UL)          /*!< ESIF (Bit 0)                                          */
+ #define R_DMAC0_DMSTS_ESIF_Msk      (0x1UL)        /*!< ESIF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  DMSRR  ========================================================= */
+/* =========================================================  DMDRR  ========================================================= */
+/* =========================================================  DMSBS  ========================================================= */
+ #define R_DMAC0_DMSBS_DMSBSL_Pos    (0UL)          /*!< DMSBSL (Bit 0)                                        */
+ #define R_DMAC0_DMSBS_DMSBSL_Msk    (0xffffUL)     /*!< DMSBSL (Bitfield-Mask: 0xffff)                        */
+ #define R_DMAC0_DMSBS_DMSBSH_Pos    (16UL)         /*!< DMSBSH (Bit 16)                                       */
+ #define R_DMAC0_DMSBS_DMSBSH_Msk    (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff)                        */
+/* =========================================================  DMDBS  ========================================================= */
+ #define R_DMAC0_DMDBS_DMDBSL_Pos    (0UL)          /*!< DMDBSL (Bit 0)                                        */
+ #define R_DMAC0_DMDBS_DMDBSL_Msk    (0xffffUL)     /*!< DMDBSL (Bitfield-Mask: 0xffff)                        */
+ #define R_DMAC0_DMDBS_DMDBSH_Pos    (16UL)         /*!< DMDBSH (Bit 16)                                       */
+ #define R_DMAC0_DMDBS_DMDBSH_Msk    (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff)                        */
+/* =========================================================  DMBWR  ========================================================= */
+ #define R_DMAC0_DMBWR_BWE_Pos       (0UL)          /*!< BWE (Bit 0)                                           */
+ #define R_DMAC0_DMBWR_BWE_Msk       (0x1UL)        /*!< BWE (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DOC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DOCR  ========================================================== */
+ #define R_DOC_DOCR_DOPCFCL_Pos    (6UL)      /*!< DOPCFCL (Bit 6)                                       */
+ #define R_DOC_DOCR_DOPCFCL_Msk    (0x40UL)   /*!< DOPCFCL (Bitfield-Mask: 0x01)                         */
+ #define R_DOC_DOCR_DOPCF_Pos      (5UL)      /*!< DOPCF (Bit 5)                                         */
+ #define R_DOC_DOCR_DOPCF_Msk      (0x20UL)   /*!< DOPCF (Bitfield-Mask: 0x01)                           */
+ #define R_DOC_DOCR_DCSEL_Pos      (2UL)      /*!< DCSEL (Bit 2)                                         */
+ #define R_DOC_DOCR_DCSEL_Msk      (0x4UL)    /*!< DCSEL (Bitfield-Mask: 0x01)                           */
+ #define R_DOC_DOCR_OMS_Pos        (0UL)      /*!< OMS (Bit 0)                                           */
+ #define R_DOC_DOCR_OMS_Msk        (0x3UL)    /*!< OMS (Bitfield-Mask: 0x03)                             */
+/* =========================================================  DODIR  ========================================================= */
+ #define R_DOC_DODIR_DODIR_Pos     (0UL)      /*!< DODIR (Bit 0)                                         */
+ #define R_DOC_DODIR_DODIR_Msk     (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  DODSR  ========================================================= */
+ #define R_DOC_DODSR_DODSR_Pos     (0UL)      /*!< DODSR (Bit 0)                                         */
+ #define R_DOC_DODSR_DODSR_Msk     (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff)                         */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DTC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DTCCR  ========================================================= */
+ #define R_DTC_DTCCR_RRS_Pos         (4UL)          /*!< RRS (Bit 4)                                           */
+ #define R_DTC_DTCCR_RRS_Msk         (0x10UL)       /*!< RRS (Bitfield-Mask: 0x01)                             */
+/* ========================================================  DTCVBR  ========================================================= */
+ #define R_DTC_DTCVBR_DTCVBR_Pos     (0UL)          /*!< DTCVBR (Bit 0)                                        */
+ #define R_DTC_DTCVBR_DTCVBR_Msk     (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff)                    */
+/* =========================================================  DTCST  ========================================================= */
+ #define R_DTC_DTCST_DTCST_Pos       (0UL)          /*!< DTCST (Bit 0)                                         */
+ #define R_DTC_DTCST_DTCST_Msk       (0x1UL)        /*!< DTCST (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DTCSTS  ========================================================= */
+ #define R_DTC_DTCSTS_ACT_Pos        (15UL)         /*!< ACT (Bit 15)                                          */
+ #define R_DTC_DTCSTS_ACT_Msk        (0x8000UL)     /*!< ACT (Bitfield-Mask: 0x01)                             */
+ #define R_DTC_DTCSTS_VECN_Pos       (0UL)          /*!< VECN (Bit 0)                                          */
+ #define R_DTC_DTCSTS_VECN_Msk       (0xffUL)       /*!< VECN (Bitfield-Mask: 0xff)                            */
+/* =======================================================  DTCCR_SEC  ======================================================= */
+ #define R_DTC_DTCCR_SEC_RRSS_Pos    (4UL)          /*!< RRSS (Bit 4)                                          */
+ #define R_DTC_DTCCR_SEC_RRSS_Msk    (0x10UL)       /*!< RRSS (Bitfield-Mask: 0x01)                            */
+/* ======================================================  DTCVBR_SEC  ======================================================= */
+/* =========================================================  DTEVR  ========================================================= */
+ #define R_DTC_DTEVR_DTEV_Pos        (0UL)          /*!< DTEV (Bit 0)                                          */
+ #define R_DTC_DTEVR_DTEV_Msk        (0xffUL)       /*!< DTEV (Bitfield-Mask: 0xff)                            */
+ #define R_DTC_DTEVR_DTEVSAM_Pos     (8UL)          /*!< DTEVSAM (Bit 8)                                       */
+ #define R_DTC_DTEVR_DTEVSAM_Msk     (0x100UL)      /*!< DTEVSAM (Bitfield-Mask: 0x01)                         */
+ #define R_DTC_DTEVR_DTESTA_Pos      (16UL)         /*!< DTESTA (Bit 16)                                       */
+ #define R_DTC_DTEVR_DTESTA_Msk      (0x10000UL)    /*!< DTESTA (Bitfield-Mask: 0x01)                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ELC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ELCR  ========================================================== */
+ #define R_ELC_ELCR_ELCON_Pos         (7UL)      /*!< ELCON (Bit 7)                                         */
+ #define R_ELC_ELCR_ELCON_Msk         (0x80UL)   /*!< ELCON (Bitfield-Mask: 0x01)                           */
+/* ========================================================  ELCSARA  ======================================================== */
+ #define R_ELC_ELCSARA_ELCR_Pos       (0UL)      /*!< ELCR (Bit 0)                                          */
+ #define R_ELC_ELCSARA_ELCR_Msk       (0x1UL)    /*!< ELCR (Bitfield-Mask: 0x01)                            */
+ #define R_ELC_ELCSARA_ELSEGR0_Pos    (1UL)      /*!< ELSEGR0 (Bit 1)                                       */
+ #define R_ELC_ELCSARA_ELSEGR0_Msk    (0x2UL)    /*!< ELSEGR0 (Bitfield-Mask: 0x01)                         */
+ #define R_ELC_ELCSARA_ELSEGR1_Pos    (2UL)      /*!< ELSEGR1 (Bit 2)                                       */
+ #define R_ELC_ELCSARA_ELSEGR1_Msk    (0x4UL)    /*!< ELSEGR1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ELCSARB  ======================================================== */
+ #define R_ELC_ELCSARB_ELSR0_Pos      (0UL)      /*!< ELSR0 (Bit 0)                                         */
+ #define R_ELC_ELCSARB_ELSR0_Msk      (0x1UL)    /*!< ELSR0 (Bitfield-Mask: 0x01)                           */
+ #define R_ELC_ELCSARB_ELSR1_Pos      (1UL)      /*!< ELSR1 (Bit 1)                                         */
+ #define R_ELC_ELCSARB_ELSR1_Msk      (0x2UL)    /*!< ELSR1 (Bitfield-Mask: 0x01)                           */
+ #define R_ELC_ELCSARB_ELSR2_Pos      (2UL)      /*!< ELSR2 (Bit 2)                                         */
+ #define R_ELC_ELCSARB_ELSR2_Msk      (0x4UL)    /*!< ELSR2 (Bitfield-Mask: 0x01)                           */
+ #define R_ELC_ELCSARB_ELSR3_Pos      (3UL)      /*!< ELSR3 (Bit 3)                                         */
+ #define R_ELC_ELCSARB_ELSR3_Msk      (0x8UL)    /*!< ELSR3 (Bitfield-Mask: 0x01)                           */
+ #define R_ELC_ELCSARB_ELSR4_Pos      (4UL)      /*!< ELSR4 (Bit 4)                                         */
+ #define R_ELC_ELCSARB_ELSR4_Msk      (0x10UL)   /*!< ELSR4 (Bitfield-Mask: 0x01)                           */
+ #define R_ELC_ELCSARB_ELSR5_Pos      (5UL)      /*!< ELSR5 (Bit 5)                                         */
+ #define R_ELC_ELCSARB_ELSR5_Msk      (0x20UL)   /*!< ELSR5 (Bitfield-Mask: 0x01)                           */
+ #define R_ELC_ELCSARB_ELSR6_Pos      (6UL)      /*!< ELSR6 (Bit 6)                                         */
+ #define R_ELC_ELCSARB_ELSR6_Msk      (0x40UL)   /*!< ELSR6 (Bitfield-Mask: 0x01)                           */
+ #define R_ELC_ELCSARB_ELSR7_Pos      (7UL)      /*!< ELSR7 (Bit 7)                                         */
+ #define R_ELC_ELCSARB_ELSR7_Msk      (0x80UL)   /*!< ELSR7 (Bitfield-Mask: 0x01)                           */
+ #define R_ELC_ELCSARB_ELSR8_Pos      (8UL)      /*!< ELSR8 (Bit 8)                                         */
+ #define R_ELC_ELCSARB_ELSR8_Msk      (0x100UL)  /*!< ELSR8 (Bitfield-Mask: 0x01)                           */
+ #define R_ELC_ELCSARB_ELSR9_Pos      (9UL)      /*!< ELSR9 (Bit 9)                                         */
+ #define R_ELC_ELCSARB_ELSR9_Msk      (0x200UL)  /*!< ELSR9 (Bitfield-Mask: 0x01)                           */
+ #define R_ELC_ELCSARB_ELSR10_Pos     (10UL)     /*!< ELSR10 (Bit 10)                                       */
+ #define R_ELC_ELCSARB_ELSR10_Msk     (0x400UL)  /*!< ELSR10 (Bitfield-Mask: 0x01)                          */
+ #define R_ELC_ELCSARB_ELSR11_Pos     (11UL)     /*!< ELSR11 (Bit 11)                                       */
+ #define R_ELC_ELCSARB_ELSR11_Msk     (0x800UL)  /*!< ELSR11 (Bitfield-Mask: 0x01)                          */
+ #define R_ELC_ELCSARB_ELSR12_Pos     (12UL)     /*!< ELSR12 (Bit 12)                                       */
+ #define R_ELC_ELCSARB_ELSR12_Msk     (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01)                          */
+ #define R_ELC_ELCSARB_ELSR13_Pos     (13UL)     /*!< ELSR13 (Bit 13)                                       */
+ #define R_ELC_ELCSARB_ELSR13_Msk     (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01)                          */
+ #define R_ELC_ELCSARB_ELSR14_Pos     (14UL)     /*!< ELSR14 (Bit 14)                                       */
+ #define R_ELC_ELCSARB_ELSR14_Msk     (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01)                          */
+ #define R_ELC_ELCSARB_ELSR15_Pos     (15UL)     /*!< ELSR15 (Bit 15)                                       */
+ #define R_ELC_ELCSARB_ELSR15_Msk     (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  ELCSARC  ======================================================== */
+ #define R_ELC_ELCSARC_ELSR16_Pos     (0UL)      /*!< ELSR16 (Bit 0)                                        */
+ #define R_ELC_ELCSARC_ELSR16_Msk     (0x1UL)    /*!< ELSR16 (Bitfield-Mask: 0x01)                          */
+ #define R_ELC_ELCSARC_ELSR17_Pos     (1UL)      /*!< ELSR17 (Bit 1)                                        */
+ #define R_ELC_ELCSARC_ELSR17_Msk     (0x2UL)    /*!< ELSR17 (Bitfield-Mask: 0x01)                          */
+ #define R_ELC_ELCSARC_ELSR18_Pos     (2UL)      /*!< ELSR18 (Bit 2)                                        */
+ #define R_ELC_ELCSARC_ELSR18_Msk     (0x4UL)    /*!< ELSR18 (Bitfield-Mask: 0x01)                          */
+
+/* =========================================================================================================================== */
+/* ================                                       R_FACI_HP_CMD                                       ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================  FACI_CMD16  ======================================================= */
+/* =======================================================  FACI_CMD8  ======================================================= */
+
+/* =========================================================================================================================== */
+/* ================                                         R_FACI_HP                                         ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  FASTAT  ========================================================= */
+ #define R_FACI_HP_FASTAT_CFAE_Pos         (7UL)          /*!< CFAE (Bit 7)                                          */
+ #define R_FACI_HP_FASTAT_CFAE_Msk         (0x80UL)       /*!< CFAE (Bitfield-Mask: 0x01)                            */
+ #define R_FACI_HP_FASTAT_CMDLK_Pos        (4UL)          /*!< CMDLK (Bit 4)                                         */
+ #define R_FACI_HP_FASTAT_CMDLK_Msk        (0x10UL)       /*!< CMDLK (Bitfield-Mask: 0x01)                           */
+ #define R_FACI_HP_FASTAT_DFAE_Pos         (3UL)          /*!< DFAE (Bit 3)                                          */
+ #define R_FACI_HP_FASTAT_DFAE_Msk         (0x8UL)        /*!< DFAE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  FAEINT  ========================================================= */
+ #define R_FACI_HP_FAEINT_CFAEIE_Pos       (7UL)          /*!< CFAEIE (Bit 7)                                        */
+ #define R_FACI_HP_FAEINT_CFAEIE_Msk       (0x80UL)       /*!< CFAEIE (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FAEINT_CMDLKIE_Pos      (4UL)          /*!< CMDLKIE (Bit 4)                                       */
+ #define R_FACI_HP_FAEINT_CMDLKIE_Msk      (0x10UL)       /*!< CMDLKIE (Bitfield-Mask: 0x01)                         */
+ #define R_FACI_HP_FAEINT_DFAEIE_Pos       (3UL)          /*!< DFAEIE (Bit 3)                                        */
+ #define R_FACI_HP_FAEINT_DFAEIE_Msk       (0x8UL)        /*!< DFAEIE (Bitfield-Mask: 0x01)                          */
+/* ========================================================  FRDYIE  ========================================================= */
+ #define R_FACI_HP_FRDYIE_FRDYIE_Pos       (0UL)          /*!< FRDYIE (Bit 0)                                        */
+ #define R_FACI_HP_FRDYIE_FRDYIE_Msk       (0x1UL)        /*!< FRDYIE (Bitfield-Mask: 0x01)                          */
+/* ========================================================  FSADDR  ========================================================= */
+ #define R_FACI_HP_FSADDR_FSA_Pos          (0UL)          /*!< FSA (Bit 0)                                           */
+ #define R_FACI_HP_FSADDR_FSA_Msk          (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  FEADDR  ========================================================= */
+ #define R_FACI_HP_FEADDR_FEA_Pos          (0UL)          /*!< FEA (Bit 0)                                           */
+ #define R_FACI_HP_FEADDR_FEA_Msk          (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  FMEPROT  ======================================================== */
+ #define R_FACI_HP_FMEPROT_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_FACI_HP_FMEPROT_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_FACI_HP_FMEPROT_CEPROT_Pos      (0UL)          /*!< CEPROT (Bit 0)                                        */
+ #define R_FACI_HP_FMEPROT_CEPROT_Msk      (0x1UL)        /*!< CEPROT (Bitfield-Mask: 0x01)                          */
+/* ========================================================  FBPROT0  ======================================================== */
+ #define R_FACI_HP_FBPROT0_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_FACI_HP_FBPROT0_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_FACI_HP_FBPROT0_BPCN0_Pos       (0UL)          /*!< BPCN0 (Bit 0)                                         */
+ #define R_FACI_HP_FBPROT0_BPCN0_Msk       (0x1UL)        /*!< BPCN0 (Bitfield-Mask: 0x01)                           */
+/* ========================================================  FBPROT1  ======================================================== */
+ #define R_FACI_HP_FBPROT1_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_FACI_HP_FBPROT1_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_FACI_HP_FBPROT1_BPCN1_Pos       (0UL)          /*!< BPCN1 (Bit 0)                                         */
+ #define R_FACI_HP_FBPROT1_BPCN1_Msk       (0x1UL)        /*!< BPCN1 (Bitfield-Mask: 0x01)                           */
+/* ========================================================  FSTATR  ========================================================= */
+ #define R_FACI_HP_FSTATR_ILGCOMERR_Pos    (23UL)         /*!< ILGCOMERR (Bit 23)                                    */
+ #define R_FACI_HP_FSTATR_ILGCOMERR_Msk    (0x800000UL)   /*!< ILGCOMERR (Bitfield-Mask: 0x01)                       */
+ #define R_FACI_HP_FSTATR_FESETERR_Pos     (22UL)         /*!< FESETERR (Bit 22)                                     */
+ #define R_FACI_HP_FSTATR_FESETERR_Msk     (0x400000UL)   /*!< FESETERR (Bitfield-Mask: 0x01)                        */
+ #define R_FACI_HP_FSTATR_SECERR_Pos       (21UL)         /*!< SECERR (Bit 21)                                       */
+ #define R_FACI_HP_FSTATR_SECERR_Msk       (0x200000UL)   /*!< SECERR (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_OTERR_Pos        (20UL)         /*!< OTERR (Bit 20)                                        */
+ #define R_FACI_HP_FSTATR_OTERR_Msk        (0x100000UL)   /*!< OTERR (Bitfield-Mask: 0x01)                           */
+ #define R_FACI_HP_FSTATR_FRDY_Pos         (15UL)         /*!< FRDY (Bit 15)                                         */
+ #define R_FACI_HP_FSTATR_FRDY_Msk         (0x8000UL)     /*!< FRDY (Bitfield-Mask: 0x01)                            */
+ #define R_FACI_HP_FSTATR_ILGLERR_Pos      (14UL)         /*!< ILGLERR (Bit 14)                                      */
+ #define R_FACI_HP_FSTATR_ILGLERR_Msk      (0x4000UL)     /*!< ILGLERR (Bitfield-Mask: 0x01)                         */
+ #define R_FACI_HP_FSTATR_ERSERR_Pos       (13UL)         /*!< ERSERR (Bit 13)                                       */
+ #define R_FACI_HP_FSTATR_ERSERR_Msk       (0x2000UL)     /*!< ERSERR (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_PRGERR_Pos       (12UL)         /*!< PRGERR (Bit 12)                                       */
+ #define R_FACI_HP_FSTATR_PRGERR_Msk       (0x1000UL)     /*!< PRGERR (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_SUSRDY_Pos       (11UL)         /*!< SUSRDY (Bit 11)                                       */
+ #define R_FACI_HP_FSTATR_SUSRDY_Msk       (0x800UL)      /*!< SUSRDY (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_DBFULL_Pos       (10UL)         /*!< DBFULL (Bit 10)                                       */
+ #define R_FACI_HP_FSTATR_DBFULL_Msk       (0x400UL)      /*!< DBFULL (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_ERSSPD_Pos       (9UL)          /*!< ERSSPD (Bit 9)                                        */
+ #define R_FACI_HP_FSTATR_ERSSPD_Msk       (0x200UL)      /*!< ERSSPD (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_PRGSPD_Pos       (8UL)          /*!< PRGSPD (Bit 8)                                        */
+ #define R_FACI_HP_FSTATR_PRGSPD_Msk       (0x100UL)      /*!< PRGSPD (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_FLWEERR_Pos      (6UL)          /*!< FLWEERR (Bit 6)                                       */
+ #define R_FACI_HP_FSTATR_FLWEERR_Msk      (0x40UL)       /*!< FLWEERR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  FENTRYR  ======================================================== */
+ #define R_FACI_HP_FENTRYR_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_FACI_HP_FENTRYR_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_FACI_HP_FENTRYR_FENTRYD_Pos     (7UL)          /*!< FENTRYD (Bit 7)                                       */
+ #define R_FACI_HP_FENTRYR_FENTRYD_Msk     (0x80UL)       /*!< FENTRYD (Bitfield-Mask: 0x01)                         */
+ #define R_FACI_HP_FENTRYR_FENTRYC_Pos     (0UL)          /*!< FENTRYC (Bit 0)                                       */
+ #define R_FACI_HP_FENTRYR_FENTRYC_Msk     (0x1UL)        /*!< FENTRYC (Bitfield-Mask: 0x01)                         */
+/* =======================================================  FSUINITR  ======================================================== */
+ #define R_FACI_HP_FSUINITR_KEY_Pos        (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_FACI_HP_FSUINITR_KEY_Msk        (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_FACI_HP_FSUINITR_SUINIT_Pos     (0UL)          /*!< SUINIT (Bit 0)                                        */
+ #define R_FACI_HP_FSUINITR_SUINIT_Msk     (0x1UL)        /*!< SUINIT (Bitfield-Mask: 0x01)                          */
+/* =========================================================  FCMDR  ========================================================= */
+ #define R_FACI_HP_FCMDR_CMDR_Pos          (8UL)          /*!< CMDR (Bit 8)                                          */
+ #define R_FACI_HP_FCMDR_CMDR_Msk          (0xff00UL)     /*!< CMDR (Bitfield-Mask: 0xff)                            */
+ #define R_FACI_HP_FCMDR_PCMDR_Pos         (0UL)          /*!< PCMDR (Bit 0)                                         */
+ #define R_FACI_HP_FCMDR_PCMDR_Msk         (0xffUL)       /*!< PCMDR (Bitfield-Mask: 0xff)                           */
+/* ========================================================  FBCCNT  ========================================================= */
+ #define R_FACI_HP_FBCCNT_BCDIR_Pos        (0UL)          /*!< BCDIR (Bit 0)                                         */
+ #define R_FACI_HP_FBCCNT_BCDIR_Msk        (0x1UL)        /*!< BCDIR (Bitfield-Mask: 0x01)                           */
+/* ========================================================  FBCSTAT  ======================================================== */
+ #define R_FACI_HP_FBCSTAT_BCST_Pos        (0UL)          /*!< BCST (Bit 0)                                          */
+ #define R_FACI_HP_FBCSTAT_BCST_Msk        (0x1UL)        /*!< BCST (Bitfield-Mask: 0x01)                            */
+/* ========================================================  FPSADDR  ======================================================== */
+ #define R_FACI_HP_FPSADDR_PSADR_Pos       (0UL)          /*!< PSADR (Bit 0)                                         */
+ #define R_FACI_HP_FPSADDR_PSADR_Msk       (0x7ffffUL)    /*!< PSADR (Bitfield-Mask: 0x7ffff)                        */
+/* ========================================================  FAWMON  ========================================================= */
+ #define R_FACI_HP_FAWMON_BTFLG_Pos        (31UL)         /*!< BTFLG (Bit 31)                                        */
+ #define R_FACI_HP_FAWMON_BTFLG_Msk        (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01)                           */
+ #define R_FACI_HP_FAWMON_FAWE_Pos         (16UL)         /*!< FAWE (Bit 16)                                         */
+ #define R_FACI_HP_FAWMON_FAWE_Msk         (0x7ff0000UL)  /*!< FAWE (Bitfield-Mask: 0x7ff)                           */
+ #define R_FACI_HP_FAWMON_FSPR_Pos         (15UL)         /*!< FSPR (Bit 15)                                         */
+ #define R_FACI_HP_FAWMON_FSPR_Msk         (0x8000UL)     /*!< FSPR (Bitfield-Mask: 0x01)                            */
+ #define R_FACI_HP_FAWMON_FAWS_Pos         (0UL)          /*!< FAWS (Bit 0)                                          */
+ #define R_FACI_HP_FAWMON_FAWS_Msk         (0x7ffUL)      /*!< FAWS (Bitfield-Mask: 0x7ff)                           */
+/* =========================================================  FCPSR  ========================================================= */
+ #define R_FACI_HP_FCPSR_ESUSPMD_Pos       (0UL)          /*!< ESUSPMD (Bit 0)                                       */
+ #define R_FACI_HP_FCPSR_ESUSPMD_Msk       (0x1UL)        /*!< ESUSPMD (Bitfield-Mask: 0x01)                         */
+/* ========================================================  FPCKAR  ========================================================= */
+ #define R_FACI_HP_FPCKAR_KEY_Pos          (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_FACI_HP_FPCKAR_KEY_Msk          (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_FACI_HP_FPCKAR_PCKA_Pos         (0UL)          /*!< PCKA (Bit 0)                                          */
+ #define R_FACI_HP_FPCKAR_PCKA_Msk         (0xffUL)       /*!< PCKA (Bitfield-Mask: 0xff)                            */
+/* ========================================================  FSUACR  ========================================================= */
+ #define R_FACI_HP_FSUACR_KEY_Pos          (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_FACI_HP_FSUACR_KEY_Msk          (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_FACI_HP_FSUACR_SAS_Pos          (0UL)          /*!< SAS (Bit 0)                                           */
+ #define R_FACI_HP_FSUACR_SAS_Msk          (0x3UL)        /*!< SAS (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                         R_FCACHE                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  FCACHEE  ======================================================== */
+ #define R_FCACHE_FCACHEE_FCACHEEN_Pos     (0UL)     /*!< FCACHEEN (Bit 0)                                      */
+ #define R_FCACHE_FCACHEE_FCACHEEN_Msk     (0x1UL)   /*!< FCACHEEN (Bitfield-Mask: 0x01)                        */
+/* =======================================================  FCACHEIV  ======================================================== */
+ #define R_FCACHE_FCACHEIV_FCACHEIV_Pos    (0UL)     /*!< FCACHEIV (Bit 0)                                      */
+ #define R_FCACHE_FCACHEIV_FCACHEIV_Msk    (0x1UL)   /*!< FCACHEIV (Bitfield-Mask: 0x01)                        */
+/* =========================================================  FLWT  ========================================================== */
+ #define R_FCACHE_FLWT_FLWT_Pos            (0UL)     /*!< FLWT (Bit 0)                                          */
+ #define R_FCACHE_FLWT_FLWT_Msk            (0x7UL)   /*!< FLWT (Bitfield-Mask: 0x07)                            */
+/* =========================================================  FSAR  ========================================================== */
+ #define R_FCACHE_FSAR_FLWTSA_Pos          (0UL)     /*!< FLWTSA (Bit 0)                                        */
+ #define R_FCACHE_FSAR_FLWTSA_Msk          (0x1UL)   /*!< FLWTSA (Bitfield-Mask: 0x01)                          */
+ #define R_FCACHE_FSAR_FCKMHZSA_Pos        (8UL)     /*!< FCKMHZSA (Bit 8)                                      */
+ #define R_FCACHE_FSAR_FCKMHZSA_Msk        (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01)                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_GPT0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  GTWP  ========================================================== */
+ #define R_GPT0_GTWP_PRKEY_Pos             (8UL)          /*!< PRKEY (Bit 8)                                         */
+ #define R_GPT0_GTWP_PRKEY_Msk             (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
+ #define R_GPT0_GTWP_WP_Pos                (0UL)          /*!< WP (Bit 0)                                            */
+ #define R_GPT0_GTWP_WP_Msk                (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
+ #define R_GPT0_GTWP_STRWP_Pos             (1UL)          /*!< STRWP (Bit 1)                                         */
+ #define R_GPT0_GTWP_STRWP_Msk             (0x2UL)        /*!< STRWP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTWP_STPWP_Pos             (2UL)          /*!< STPWP (Bit 2)                                         */
+ #define R_GPT0_GTWP_STPWP_Msk             (0x4UL)        /*!< STPWP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTWP_CLRWP_Pos             (3UL)          /*!< CLRWP (Bit 3)                                         */
+ #define R_GPT0_GTWP_CLRWP_Msk             (0x8UL)        /*!< CLRWP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTWP_CMNWP_Pos             (4UL)          /*!< CMNWP (Bit 4)                                         */
+ #define R_GPT0_GTWP_CMNWP_Msk             (0x10UL)       /*!< CMNWP (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTSTR  ========================================================= */
+ #define R_GPT0_GTSTR_CSTRT_Pos            (0UL)          /*!< CSTRT (Bit 0)                                         */
+ #define R_GPT0_GTSTR_CSTRT_Msk            (0x1UL)        /*!< CSTRT (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTSTP  ========================================================= */
+ #define R_GPT0_GTSTP_CSTOP_Pos            (0UL)          /*!< CSTOP (Bit 0)                                         */
+ #define R_GPT0_GTSTP_CSTOP_Msk            (0x1UL)        /*!< CSTOP (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTCLR  ========================================================= */
+ #define R_GPT0_GTCLR_CCLR_Pos             (0UL)          /*!< CCLR (Bit 0)                                          */
+ #define R_GPT0_GTCLR_CCLR_Msk             (0x1UL)        /*!< CCLR (Bitfield-Mask: 0x01)                            */
+/* =========================================================  GTSSR  ========================================================= */
+ #define R_GPT0_GTSSR_CSTRT_Pos            (31UL)         /*!< CSTRT (Bit 31)                                        */
+ #define R_GPT0_GTSSR_CSTRT_Msk            (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSSR_SSELC_Pos            (16UL)         /*!< SSELC (Bit 16)                                        */
+ #define R_GPT0_GTSSR_SSELC_Msk            (0x10000UL)    /*!< SSELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSSR_SSCBFAH_Pos          (15UL)         /*!< SSCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTSSR_SSCBFAH_Msk          (0x8000UL)     /*!< SSCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCBFAL_Pos          (14UL)         /*!< SSCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTSSR_SSCBFAL_Msk          (0x4000UL)     /*!< SSCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCBRAH_Pos          (13UL)         /*!< SSCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTSSR_SSCBRAH_Msk          (0x2000UL)     /*!< SSCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCBRAL_Pos          (12UL)         /*!< SSCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTSSR_SSCBRAL_Msk          (0x1000UL)     /*!< SSCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCAFBH_Pos          (11UL)         /*!< SSCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTSSR_SSCAFBH_Msk          (0x800UL)      /*!< SSCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCAFBL_Pos          (10UL)         /*!< SSCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTSSR_SSCAFBL_Msk          (0x400UL)      /*!< SSCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCARBH_Pos          (9UL)          /*!< SSCARBH (Bit 9)                                       */
+ #define R_GPT0_GTSSR_SSCARBH_Msk          (0x200UL)      /*!< SSCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCARBL_Pos          (8UL)          /*!< SSCARBL (Bit 8)                                       */
+ #define R_GPT0_GTSSR_SSCARBL_Msk          (0x100UL)      /*!< SSCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSGTRGF_Pos          (1UL)          /*!< SSGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTSSR_SSGTRGF_Msk          (0x2UL)        /*!< SSGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSGTRGR_Pos          (0UL)          /*!< SSGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTSSR_SSGTRGR_Msk          (0x1UL)        /*!< SSGTRGR (Bitfield-Mask: 0x01)                         */
+/* =========================================================  GTPSR  ========================================================= */
+ #define R_GPT0_GTPSR_CSTOP_Pos            (31UL)         /*!< CSTOP (Bit 31)                                        */
+ #define R_GPT0_GTPSR_CSTOP_Msk            (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTPSR_PSELC_Pos            (16UL)         /*!< PSELC (Bit 16)                                        */
+ #define R_GPT0_GTPSR_PSELC_Msk            (0x10000UL)    /*!< PSELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTPSR_PSCBFAH_Pos          (15UL)         /*!< PSCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTPSR_PSCBFAH_Msk          (0x8000UL)     /*!< PSCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCBFAL_Pos          (14UL)         /*!< PSCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTPSR_PSCBFAL_Msk          (0x4000UL)     /*!< PSCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCBRAH_Pos          (13UL)         /*!< PSCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTPSR_PSCBRAH_Msk          (0x2000UL)     /*!< PSCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCBRAL_Pos          (12UL)         /*!< PSCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTPSR_PSCBRAL_Msk          (0x1000UL)     /*!< PSCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCAFBH_Pos          (11UL)         /*!< PSCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTPSR_PSCAFBH_Msk          (0x800UL)      /*!< PSCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCAFBL_Pos          (10UL)         /*!< PSCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTPSR_PSCAFBL_Msk          (0x400UL)      /*!< PSCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCARBH_Pos          (9UL)          /*!< PSCARBH (Bit 9)                                       */
+ #define R_GPT0_GTPSR_PSCARBH_Msk          (0x200UL)      /*!< PSCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCARBL_Pos          (8UL)          /*!< PSCARBL (Bit 8)                                       */
+ #define R_GPT0_GTPSR_PSCARBL_Msk          (0x100UL)      /*!< PSCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSGTRGF_Pos          (1UL)          /*!< PSGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTPSR_PSGTRGF_Msk          (0x2UL)        /*!< PSGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSGTRGR_Pos          (0UL)          /*!< PSGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTPSR_PSGTRGR_Msk          (0x1UL)        /*!< PSGTRGR (Bitfield-Mask: 0x01)                         */
+/* =========================================================  GTCSR  ========================================================= */
+ #define R_GPT0_GTCSR_CCLR_Pos             (31UL)         /*!< CCLR (Bit 31)                                         */
+ #define R_GPT0_GTCSR_CCLR_Msk             (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTCSR_CP1CCE_Pos           (27UL)         /*!< CP1CCE (Bit 27)                                       */
+ #define R_GPT0_GTCSR_CP1CCE_Msk           (0x8000000UL)  /*!< CP1CCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTCSR_CSCMSC_Pos           (24UL)         /*!< CSCMSC (Bit 24)                                       */
+ #define R_GPT0_GTCSR_CSCMSC_Msk           (0x7000000UL)  /*!< CSCMSC (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTCSR_CSELC_Pos            (16UL)         /*!< CSELC (Bit 16)                                        */
+ #define R_GPT0_GTCSR_CSELC_Msk            (0x10000UL)    /*!< CSELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCSR_CSCBFAH_Pos          (15UL)         /*!< CSCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTCSR_CSCBFAH_Msk          (0x8000UL)     /*!< CSCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCBFAL_Pos          (14UL)         /*!< CSCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTCSR_CSCBFAL_Msk          (0x4000UL)     /*!< CSCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCBRAH_Pos          (13UL)         /*!< CSCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTCSR_CSCBRAH_Msk          (0x2000UL)     /*!< CSCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCBRAL_Pos          (12UL)         /*!< CSCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTCSR_CSCBRAL_Msk          (0x1000UL)     /*!< CSCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCAFBH_Pos          (11UL)         /*!< CSCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTCSR_CSCAFBH_Msk          (0x800UL)      /*!< CSCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCAFBL_Pos          (10UL)         /*!< CSCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTCSR_CSCAFBL_Msk          (0x400UL)      /*!< CSCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCARBH_Pos          (9UL)          /*!< CSCARBH (Bit 9)                                       */
+ #define R_GPT0_GTCSR_CSCARBH_Msk          (0x200UL)      /*!< CSCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCARBL_Pos          (8UL)          /*!< CSCARBL (Bit 8)                                       */
+ #define R_GPT0_GTCSR_CSCARBL_Msk          (0x100UL)      /*!< CSCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSGTRGF_Pos          (1UL)          /*!< CSGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTCSR_CSGTRGF_Msk          (0x2UL)        /*!< CSGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSGTRGR_Pos          (0UL)          /*!< CSGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTCSR_CSGTRGR_Msk          (0x1UL)        /*!< CSGTRGR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTUPSR  ========================================================= */
+ #define R_GPT0_GTUPSR_USILVL_Pos          (24UL)         /*!< USILVL (Bit 24)                                       */
+ #define R_GPT0_GTUPSR_USILVL_Msk          (0xf000000UL)  /*!< USILVL (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTUPSR_USELC_Pos           (16UL)         /*!< USELC (Bit 16)                                        */
+ #define R_GPT0_GTUPSR_USELC_Msk           (0x10000UL)    /*!< USELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTUPSR_USCBFAH_Pos         (15UL)         /*!< USCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTUPSR_USCBFAH_Msk         (0x8000UL)     /*!< USCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCBFAL_Pos         (14UL)         /*!< USCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTUPSR_USCBFAL_Msk         (0x4000UL)     /*!< USCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCBRAH_Pos         (13UL)         /*!< USCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTUPSR_USCBRAH_Msk         (0x2000UL)     /*!< USCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCBRAL_Pos         (12UL)         /*!< USCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTUPSR_USCBRAL_Msk         (0x1000UL)     /*!< USCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCAFBH_Pos         (11UL)         /*!< USCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTUPSR_USCAFBH_Msk         (0x800UL)      /*!< USCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCAFBL_Pos         (10UL)         /*!< USCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTUPSR_USCAFBL_Msk         (0x400UL)      /*!< USCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCARBH_Pos         (9UL)          /*!< USCARBH (Bit 9)                                       */
+ #define R_GPT0_GTUPSR_USCARBH_Msk         (0x200UL)      /*!< USCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCARBL_Pos         (8UL)          /*!< USCARBL (Bit 8)                                       */
+ #define R_GPT0_GTUPSR_USCARBL_Msk         (0x100UL)      /*!< USCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USGTRGF_Pos         (1UL)          /*!< USGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTUPSR_USGTRGF_Msk         (0x2UL)        /*!< USGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USGTRGR_Pos         (0UL)          /*!< USGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTUPSR_USGTRGR_Msk         (0x1UL)        /*!< USGTRGR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTDNSR  ========================================================= */
+ #define R_GPT0_GTDNSR_DSILVL_Pos          (24UL)         /*!< DSILVL (Bit 24)                                       */
+ #define R_GPT0_GTDNSR_DSILVL_Msk          (0xf000000UL)  /*!< DSILVL (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTDNSR_DSELC_Pos           (16UL)         /*!< DSELC (Bit 16)                                        */
+ #define R_GPT0_GTDNSR_DSELC_Msk           (0x10000UL)    /*!< DSELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTDNSR_DSCBFAH_Pos         (15UL)         /*!< DSCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTDNSR_DSCBFAH_Msk         (0x8000UL)     /*!< DSCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCBFAL_Pos         (14UL)         /*!< DSCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTDNSR_DSCBFAL_Msk         (0x4000UL)     /*!< DSCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCBRAH_Pos         (13UL)         /*!< DSCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTDNSR_DSCBRAH_Msk         (0x2000UL)     /*!< DSCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCBRAL_Pos         (12UL)         /*!< DSCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTDNSR_DSCBRAL_Msk         (0x1000UL)     /*!< DSCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCAFBH_Pos         (11UL)         /*!< DSCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTDNSR_DSCAFBH_Msk         (0x800UL)      /*!< DSCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCAFBL_Pos         (10UL)         /*!< DSCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTDNSR_DSCAFBL_Msk         (0x400UL)      /*!< DSCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCARBH_Pos         (9UL)          /*!< DSCARBH (Bit 9)                                       */
+ #define R_GPT0_GTDNSR_DSCARBH_Msk         (0x200UL)      /*!< DSCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCARBL_Pos         (8UL)          /*!< DSCARBL (Bit 8)                                       */
+ #define R_GPT0_GTDNSR_DSCARBL_Msk         (0x100UL)      /*!< DSCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSGTRGF_Pos         (1UL)          /*!< DSGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTDNSR_DSGTRGF_Msk         (0x2UL)        /*!< DSGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSGTRGR_Pos         (0UL)          /*!< DSGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTDNSR_DSGTRGR_Msk         (0x1UL)        /*!< DSGTRGR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTICASR  ======================================================== */
+ #define R_GPT0_GTICASR_ASELC_Pos          (16UL)         /*!< ASELC (Bit 16)                                        */
+ #define R_GPT0_GTICASR_ASELC_Msk          (0x10000UL)    /*!< ASELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICASR_ASCBFAH_Pos        (15UL)         /*!< ASCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTICASR_ASCBFAH_Msk        (0x8000UL)     /*!< ASCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCBFAL_Pos        (14UL)         /*!< ASCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTICASR_ASCBFAL_Msk        (0x4000UL)     /*!< ASCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCBRAH_Pos        (13UL)         /*!< ASCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTICASR_ASCBRAH_Msk        (0x2000UL)     /*!< ASCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCBRAL_Pos        (12UL)         /*!< ASCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTICASR_ASCBRAL_Msk        (0x1000UL)     /*!< ASCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCAFBH_Pos        (11UL)         /*!< ASCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTICASR_ASCAFBH_Msk        (0x800UL)      /*!< ASCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCAFBL_Pos        (10UL)         /*!< ASCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTICASR_ASCAFBL_Msk        (0x400UL)      /*!< ASCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCARBH_Pos        (9UL)          /*!< ASCARBH (Bit 9)                                       */
+ #define R_GPT0_GTICASR_ASCARBH_Msk        (0x200UL)      /*!< ASCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCARBL_Pos        (8UL)          /*!< ASCARBL (Bit 8)                                       */
+ #define R_GPT0_GTICASR_ASCARBL_Msk        (0x100UL)      /*!< ASCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASGTRGF_Pos        (1UL)          /*!< ASGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTICASR_ASGTRGF_Msk        (0x2UL)        /*!< ASGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASGTRGR_Pos        (0UL)          /*!< ASGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTICASR_ASGTRGR_Msk        (0x1UL)        /*!< ASGTRGR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTICBSR  ======================================================== */
+ #define R_GPT0_GTICBSR_BSELC_Pos          (16UL)         /*!< BSELC (Bit 16)                                        */
+ #define R_GPT0_GTICBSR_BSELC_Msk          (0x10000UL)    /*!< BSELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICBSR_BSCBFAH_Pos        (15UL)         /*!< BSCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTICBSR_BSCBFAH_Msk        (0x8000UL)     /*!< BSCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCBFAL_Pos        (14UL)         /*!< BSCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTICBSR_BSCBFAL_Msk        (0x4000UL)     /*!< BSCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCBRAH_Pos        (13UL)         /*!< BSCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTICBSR_BSCBRAH_Msk        (0x2000UL)     /*!< BSCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCBRAL_Pos        (12UL)         /*!< BSCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTICBSR_BSCBRAL_Msk        (0x1000UL)     /*!< BSCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCAFBH_Pos        (11UL)         /*!< BSCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTICBSR_BSCAFBH_Msk        (0x800UL)      /*!< BSCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCAFBL_Pos        (10UL)         /*!< BSCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTICBSR_BSCAFBL_Msk        (0x400UL)      /*!< BSCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCARBH_Pos        (9UL)          /*!< BSCARBH (Bit 9)                                       */
+ #define R_GPT0_GTICBSR_BSCARBH_Msk        (0x200UL)      /*!< BSCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCARBL_Pos        (8UL)          /*!< BSCARBL (Bit 8)                                       */
+ #define R_GPT0_GTICBSR_BSCARBL_Msk        (0x100UL)      /*!< BSCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSGTRGF_Pos        (1UL)          /*!< BSGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTICBSR_BSGTRGF_Msk        (0x2UL)        /*!< BSGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
+/* =========================================================  GTCR  ========================================================== */
+ #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
+ #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTCR_TPCS_Pos              (23UL)         /*!< TPCS (Bit 23)                                         */
+ #define R_GPT0_GTCR_TPCS_Msk              (0x7800000UL)  /*!< TPCS (Bitfield-Mask: 0x0f)                            */
+ #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
+ #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
+ #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
+ #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
+ #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
+ #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
+ #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
+/* =======================================================  GTUDDTYC  ======================================================== */
+ #define R_GPT0_GTUDDTYC_OBDTYR_Pos        (27UL)         /*!< OBDTYR (Bit 27)                                       */
+ #define R_GPT0_GTUDDTYC_OBDTYR_Msk        (0x8000000UL)  /*!< OBDTYR (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTUDDTYC_OBDTYF_Pos        (26UL)         /*!< OBDTYF (Bit 26)                                       */
+ #define R_GPT0_GTUDDTYC_OBDTYF_Msk        (0x4000000UL)  /*!< OBDTYF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTUDDTYC_OBDTY_Pos         (24UL)         /*!< OBDTY (Bit 24)                                        */
+ #define R_GPT0_GTUDDTYC_OBDTY_Msk         (0x3000000UL)  /*!< OBDTY (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTUDDTYC_OADTYR_Pos        (19UL)         /*!< OADTYR (Bit 19)                                       */
+ #define R_GPT0_GTUDDTYC_OADTYR_Msk        (0x80000UL)    /*!< OADTYR (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTUDDTYC_OADTYF_Pos        (18UL)         /*!< OADTYF (Bit 18)                                       */
+ #define R_GPT0_GTUDDTYC_OADTYF_Msk        (0x40000UL)    /*!< OADTYF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTUDDTYC_OADTY_Pos         (16UL)         /*!< OADTY (Bit 16)                                        */
+ #define R_GPT0_GTUDDTYC_OADTY_Msk         (0x30000UL)    /*!< OADTY (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTUDDTYC_UDF_Pos           (1UL)          /*!< UDF (Bit 1)                                           */
+ #define R_GPT0_GTUDDTYC_UDF_Msk           (0x2UL)        /*!< UDF (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTUDDTYC_UD_Pos            (0UL)          /*!< UD (Bit 0)                                            */
+ #define R_GPT0_GTUDDTYC_UD_Msk            (0x1UL)        /*!< UD (Bitfield-Mask: 0x01)                              */
+/* =========================================================  GTIOR  ========================================================= */
+ #define R_GPT0_GTIOR_NFCSB_Pos            (30UL)         /*!< NFCSB (Bit 30)                                        */
+ #define R_GPT0_GTIOR_NFCSB_Msk            (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTIOR_NFBEN_Pos            (29UL)         /*!< NFBEN (Bit 29)                                        */
+ #define R_GPT0_GTIOR_NFBEN_Msk            (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTIOR_OBEOCD_Pos           (27UL)         /*!< OBEOCD (Bit 27)                                       */
+ #define R_GPT0_GTIOR_OBEOCD_Msk           (0x8000000UL)  /*!< OBEOCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTIOR_OBDF_Pos             (25UL)         /*!< OBDF (Bit 25)                                         */
+ #define R_GPT0_GTIOR_OBDF_Msk             (0x6000000UL)  /*!< OBDF (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTIOR_OBE_Pos              (24UL)         /*!< OBE (Bit 24)                                          */
+ #define R_GPT0_GTIOR_OBE_Msk              (0x1000000UL)  /*!< OBE (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTIOR_OBHLD_Pos            (23UL)         /*!< OBHLD (Bit 23)                                        */
+ #define R_GPT0_GTIOR_OBHLD_Msk            (0x800000UL)   /*!< OBHLD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTIOR_OBDFLT_Pos           (22UL)         /*!< OBDFLT (Bit 22)                                       */
+ #define R_GPT0_GTIOR_OBDFLT_Msk           (0x400000UL)   /*!< OBDFLT (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTIOR_GTIOB_Pos            (16UL)         /*!< GTIOB (Bit 16)                                        */
+ #define R_GPT0_GTIOR_GTIOB_Msk            (0x1f0000UL)   /*!< GTIOB (Bitfield-Mask: 0x1f)                           */
+ #define R_GPT0_GTIOR_NFCSA_Pos            (14UL)         /*!< NFCSA (Bit 14)                                        */
+ #define R_GPT0_GTIOR_NFCSA_Msk            (0xc000UL)     /*!< NFCSA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTIOR_NFAEN_Pos            (13UL)         /*!< NFAEN (Bit 13)                                        */
+ #define R_GPT0_GTIOR_NFAEN_Msk            (0x2000UL)     /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTIOR_PSYE_Pos             (12UL)         /*!< PSYE (Bit 12)                                         */
+ #define R_GPT0_GTIOR_PSYE_Msk             (0x1000UL)     /*!< PSYE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTIOR_OAEOCD_Pos           (11UL)         /*!< OAEOCD (Bit 11)                                       */
+ #define R_GPT0_GTIOR_OAEOCD_Msk           (0x800UL)      /*!< OAEOCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTIOR_OADF_Pos             (9UL)          /*!< OADF (Bit 9)                                          */
+ #define R_GPT0_GTIOR_OADF_Msk             (0x600UL)      /*!< OADF (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTIOR_OAE_Pos              (8UL)          /*!< OAE (Bit 8)                                           */
+ #define R_GPT0_GTIOR_OAE_Msk              (0x100UL)      /*!< OAE (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTIOR_OAHLD_Pos            (7UL)          /*!< OAHLD (Bit 7)                                         */
+ #define R_GPT0_GTIOR_OAHLD_Msk            (0x80UL)       /*!< OAHLD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTIOR_OADFLT_Pos           (6UL)          /*!< OADFLT (Bit 6)                                        */
+ #define R_GPT0_GTIOR_OADFLT_Msk           (0x40UL)       /*!< OADFLT (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTIOR_CPSCIR_Pos           (5UL)          /*!< CPSCIR (Bit 5)                                        */
+ #define R_GPT0_GTIOR_CPSCIR_Msk           (0x20UL)       /*!< CPSCIR (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
+ #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
+/* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
+ #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
+ #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
+ #define R_GPT0_GTINTAD_GRPABH_Msk         (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTINTAD_GRPDTE_Pos         (28UL)         /*!< GRPDTE (Bit 28)                                       */
+ #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
+ #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
+ #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
+ #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
+ #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
+/* =========================================================  GTST  ========================================================== */
+ #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
+ #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTST_OABHF_Pos             (29UL)         /*!< OABHF (Bit 29)                                        */
+ #define R_GPT0_GTST_OABHF_Msk             (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTST_DTEF_Pos              (28UL)         /*!< DTEF (Bit 28)                                         */
+ #define R_GPT0_GTST_DTEF_Msk              (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_ODF_Pos               (24UL)         /*!< ODF (Bit 24)                                          */
+ #define R_GPT0_GTST_ODF_Msk               (0x1000000UL)  /*!< ODF (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTST_ADTRBDF_Pos           (19UL)         /*!< ADTRBDF (Bit 19)                                      */
+ #define R_GPT0_GTST_ADTRBDF_Msk           (0x80000UL)    /*!< ADTRBDF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTST_ADTRBUF_Pos           (18UL)         /*!< ADTRBUF (Bit 18)                                      */
+ #define R_GPT0_GTST_ADTRBUF_Msk           (0x40000UL)    /*!< ADTRBUF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTST_ADTRADF_Pos           (17UL)         /*!< ADTRADF (Bit 17)                                      */
+ #define R_GPT0_GTST_ADTRADF_Msk           (0x20000UL)    /*!< ADTRADF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTST_ADTRAUF_Pos           (16UL)         /*!< ADTRAUF (Bit 16)                                      */
+ #define R_GPT0_GTST_ADTRAUF_Msk           (0x10000UL)    /*!< ADTRAUF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTST_TUCF_Pos              (15UL)         /*!< TUCF (Bit 15)                                         */
+ #define R_GPT0_GTST_TUCF_Msk              (0x8000UL)     /*!< TUCF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_ITCNT_Pos             (8UL)          /*!< ITCNT (Bit 8)                                         */
+ #define R_GPT0_GTST_ITCNT_Msk             (0x700UL)      /*!< ITCNT (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTST_TCFPU_Pos             (7UL)          /*!< TCFPU (Bit 7)                                         */
+ #define R_GPT0_GTST_TCFPU_Msk             (0x80UL)       /*!< TCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTST_TCFPO_Pos             (6UL)          /*!< TCFPO (Bit 6)                                         */
+ #define R_GPT0_GTST_TCFPO_Msk             (0x40UL)       /*!< TCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTST_TCFF_Pos              (5UL)          /*!< TCFF (Bit 5)                                          */
+ #define R_GPT0_GTST_TCFF_Msk              (0x20UL)       /*!< TCFF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_TCFE_Pos              (4UL)          /*!< TCFE (Bit 4)                                          */
+ #define R_GPT0_GTST_TCFE_Msk              (0x10UL)       /*!< TCFE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_TCFD_Pos              (3UL)          /*!< TCFD (Bit 3)                                          */
+ #define R_GPT0_GTST_TCFD_Msk              (0x8UL)        /*!< TCFD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_TCFC_Pos              (2UL)          /*!< TCFC (Bit 2)                                          */
+ #define R_GPT0_GTST_TCFC_Msk              (0x4UL)        /*!< TCFC (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_TCFB_Pos              (1UL)          /*!< TCFB (Bit 1)                                          */
+ #define R_GPT0_GTST_TCFB_Msk              (0x2UL)        /*!< TCFB (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_TCFA_Pos              (0UL)          /*!< TCFA (Bit 0)                                          */
+ #define R_GPT0_GTST_TCFA_Msk              (0x1UL)        /*!< TCFA (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_PCF_Pos               (31UL)         /*!< PCF (Bit 31)                                          */
+ #define R_GPT0_GTST_PCF_Msk               (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01)                             */
+/* =========================================================  GTBER  ========================================================= */
+ #define R_GPT0_GTBER_ADTDB_Pos            (30UL)         /*!< ADTDB (Bit 30)                                        */
+ #define R_GPT0_GTBER_ADTDB_Msk            (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER_ADTTB_Pos            (28UL)         /*!< ADTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER_ADTTB_Msk            (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER_ADTDA_Pos            (26UL)         /*!< ADTDA (Bit 26)                                        */
+ #define R_GPT0_GTBER_ADTDA_Msk            (0x4000000UL)  /*!< ADTDA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER_ADTTA_Pos            (24UL)         /*!< ADTTA (Bit 24)                                        */
+ #define R_GPT0_GTBER_ADTTA_Msk            (0x3000000UL)  /*!< ADTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER_CCRSWT_Pos           (22UL)         /*!< CCRSWT (Bit 22)                                       */
+ #define R_GPT0_GTBER_CCRSWT_Msk           (0x400000UL)   /*!< CCRSWT (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER_PR_Pos               (20UL)         /*!< PR (Bit 20)                                           */
+ #define R_GPT0_GTBER_PR_Msk               (0x300000UL)   /*!< PR (Bitfield-Mask: 0x03)                              */
+ #define R_GPT0_GTBER_CCRB_Pos             (18UL)         /*!< CCRB (Bit 18)                                         */
+ #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
+ #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
+ #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
+ #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
+ #define R_GPT0_GTBER_BD2_Msk              (0x4UL)        /*!< BD2 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTBER_BD1_Pos              (1UL)          /*!< BD1 (Bit 1)                                           */
+ #define R_GPT0_GTBER_BD1_Msk              (0x2UL)        /*!< BD1 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTBER_BD0_Pos              (0UL)          /*!< BD0 (Bit 0)                                           */
+ #define R_GPT0_GTBER_BD0_Msk              (0x1UL)        /*!< BD0 (Bitfield-Mask: 0x01)                             */
+/* =========================================================  GTITC  ========================================================= */
+ #define R_GPT0_GTITC_ADTBL_Pos            (14UL)         /*!< ADTBL (Bit 14)                                        */
+ #define R_GPT0_GTITC_ADTBL_Msk            (0x4000UL)     /*!< ADTBL (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTITC_ADTAL_Pos            (12UL)         /*!< ADTAL (Bit 12)                                        */
+ #define R_GPT0_GTITC_ADTAL_Msk            (0x1000UL)     /*!< ADTAL (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTITC_IVTT_Pos             (8UL)          /*!< IVTT (Bit 8)                                          */
+ #define R_GPT0_GTITC_IVTT_Msk             (0x700UL)      /*!< IVTT (Bitfield-Mask: 0x07)                            */
+ #define R_GPT0_GTITC_IVTC_Pos             (6UL)          /*!< IVTC (Bit 6)                                          */
+ #define R_GPT0_GTITC_IVTC_Msk             (0xc0UL)       /*!< IVTC (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTITC_ITLF_Pos             (5UL)          /*!< ITLF (Bit 5)                                          */
+ #define R_GPT0_GTITC_ITLF_Msk             (0x20UL)       /*!< ITLF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTITC_ITLE_Pos             (4UL)          /*!< ITLE (Bit 4)                                          */
+ #define R_GPT0_GTITC_ITLE_Msk             (0x10UL)       /*!< ITLE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTITC_ITLD_Pos             (3UL)          /*!< ITLD (Bit 3)                                          */
+ #define R_GPT0_GTITC_ITLD_Msk             (0x8UL)        /*!< ITLD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTITC_ITLC_Pos             (2UL)          /*!< ITLC (Bit 2)                                          */
+ #define R_GPT0_GTITC_ITLC_Msk             (0x4UL)        /*!< ITLC (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTITC_ITLB_Pos             (1UL)          /*!< ITLB (Bit 1)                                          */
+ #define R_GPT0_GTITC_ITLB_Msk             (0x2UL)        /*!< ITLB (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTITC_ITLA_Pos             (0UL)          /*!< ITLA (Bit 0)                                          */
+ #define R_GPT0_GTITC_ITLA_Msk             (0x1UL)        /*!< ITLA (Bitfield-Mask: 0x01)                            */
+/* =========================================================  GTCNT  ========================================================= */
+ #define R_GPT0_GTCNT_GTCNT_Pos            (0UL)          /*!< GTCNT (Bit 0)                                         */
+ #define R_GPT0_GTCNT_GTCNT_Msk            (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  GTCCR  ========================================================= */
+ #define R_GPT0_GTCCR_GTCCR_Pos            (0UL)          /*!< GTCCR (Bit 0)                                         */
+ #define R_GPT0_GTCCR_GTCCR_Msk            (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  GTPR  ========================================================== */
+ #define R_GPT0_GTPR_GTPR_Pos              (0UL)          /*!< GTPR (Bit 0)                                          */
+ #define R_GPT0_GTPR_GTPR_Msk              (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  GTPBR  ========================================================= */
+ #define R_GPT0_GTPBR_GTPBR_Pos            (0UL)          /*!< GTPBR (Bit 0)                                         */
+ #define R_GPT0_GTPBR_GTPBR_Msk            (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  GTPDBR  ========================================================= */
+ #define R_GPT0_GTPDBR_GTPDBR_Pos          (0UL)          /*!< GTPDBR (Bit 0)                                        */
+ #define R_GPT0_GTPDBR_GTPDBR_Msk          (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  GTADTRA  ======================================================== */
+ #define R_GPT0_GTADTRA_GTADTRA_Pos        (0UL)          /*!< GTADTRA (Bit 0)                                       */
+ #define R_GPT0_GTADTRA_GTADTRA_Msk        (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff)                   */
+/* ========================================================  GTADTRB  ======================================================== */
+ #define R_GPT0_GTADTRB_GTADTRB_Pos        (0UL)          /*!< GTADTRB (Bit 0)                                       */
+ #define R_GPT0_GTADTRB_GTADTRB_Msk        (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff)                   */
+/* =======================================================  GTADTBRA  ======================================================== */
+ #define R_GPT0_GTADTBRA_GTADTBRA_Pos      (0UL)          /*!< GTADTBRA (Bit 0)                                      */
+ #define R_GPT0_GTADTBRA_GTADTBRA_Msk      (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff)                  */
+/* =======================================================  GTADTBRB  ======================================================== */
+ #define R_GPT0_GTADTBRB_GTADTBRB_Pos      (0UL)          /*!< GTADTBRB (Bit 0)                                      */
+ #define R_GPT0_GTADTBRB_GTADTBRB_Msk      (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff)                  */
+/* =======================================================  GTADTDBRA  ======================================================= */
+ #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos    (0UL)          /*!< GTADTDBRA (Bit 0)                                     */
+ #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk    (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff)                 */
+/* =======================================================  GTADTDBRB  ======================================================= */
+ #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos    (0UL)          /*!< GTADTDBRB (Bit 0)                                     */
+ #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk    (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff)                 */
+/* ========================================================  GTDTCR  ========================================================= */
+ #define R_GPT0_GTDTCR_TDFER_Pos           (8UL)          /*!< TDFER (Bit 8)                                         */
+ #define R_GPT0_GTDTCR_TDFER_Msk           (0x100UL)      /*!< TDFER (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTDTCR_TDBDE_Pos           (5UL)          /*!< TDBDE (Bit 5)                                         */
+ #define R_GPT0_GTDTCR_TDBDE_Msk           (0x20UL)       /*!< TDBDE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTDTCR_TDBUE_Pos           (4UL)          /*!< TDBUE (Bit 4)                                         */
+ #define R_GPT0_GTDTCR_TDBUE_Msk           (0x10UL)       /*!< TDBUE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTDTCR_TDE_Pos             (0UL)          /*!< TDE (Bit 0)                                           */
+ #define R_GPT0_GTDTCR_TDE_Msk             (0x1UL)        /*!< TDE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  GTDVU  ========================================================= */
+ #define R_GPT0_GTDVU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
+ #define R_GPT0_GTDVU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  GTDVD  ========================================================= */
+ #define R_GPT0_GTDVD_GTDVD_Pos            (0UL)          /*!< GTDVD (Bit 0)                                         */
+ #define R_GPT0_GTDVD_GTDVD_Msk            (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  GTDBU  ========================================================= */
+ #define R_GPT0_GTDBU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
+ #define R_GPT0_GTDBU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  GTDBD  ========================================================= */
+ #define R_GPT0_GTDBD_GTDBD_Pos            (0UL)          /*!< GTDBD (Bit 0)                                         */
+ #define R_GPT0_GTDBD_GTDBD_Msk            (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  GTSOS  ========================================================= */
+ #define R_GPT0_GTSOS_SOS_Pos              (0UL)          /*!< SOS (Bit 0)                                           */
+ #define R_GPT0_GTSOS_SOS_Msk              (0x3UL)        /*!< SOS (Bitfield-Mask: 0x03)                             */
+/* ========================================================  GTSOTR  ========================================================= */
+ #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
+ #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
+/* ========================================================  GTICLF  ========================================================= */
+ #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
+ #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTICLF_ICLFSELC_Pos        (4UL)          /*!< ICLFSELC (Bit 4)                                      */
+ #define R_GPT0_GTICLF_ICLFSELC_Msk        (0x3f0UL)      /*!< ICLFSELC (Bitfield-Mask: 0x3f)                        */
+ #define R_GPT0_GTICLF_ICLFB_Pos           (16UL)         /*!< ICLFB (Bit 16)                                        */
+ #define R_GPT0_GTICLF_ICLFB_Msk           (0x70000UL)    /*!< ICLFB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTICLF_ICLFSELD_Pos        (20UL)         /*!< ICLFSELD (Bit 20)                                     */
+ #define R_GPT0_GTICLF_ICLFSELD_Msk        (0x3f00000UL)  /*!< ICLFSELD (Bitfield-Mask: 0x3f)                        */
+/* =========================================================  GTPC  ========================================================== */
+ #define R_GPT0_GTPC_PCEN_Pos              (0UL)          /*!< PCEN (Bit 0)                                          */
+ #define R_GPT0_GTPC_PCEN_Msk              (0x1UL)        /*!< PCEN (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTPC_ASTP_Pos              (8UL)          /*!< ASTP (Bit 8)                                          */
+ #define R_GPT0_GTPC_ASTP_Msk              (0x100UL)      /*!< ASTP (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTPC_PCNT_Pos              (16UL)         /*!< PCNT (Bit 16)                                         */
+ #define R_GPT0_GTPC_PCNT_Msk              (0xfff0000UL)  /*!< PCNT (Bitfield-Mask: 0xfff)                           */
+/* ========================================================  GTSECSR  ======================================================== */
+ #define R_GPT0_GTSECSR_SECSEL0_Pos        (0UL)          /*!< SECSEL0 (Bit 0)                                       */
+ #define R_GPT0_GTSECSR_SECSEL0_Msk        (0x1UL)        /*!< SECSEL0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSECSR_SECSEL1_Pos        (1UL)          /*!< SECSEL1 (Bit 1)                                       */
+ #define R_GPT0_GTSECSR_SECSEL1_Msk        (0x2UL)        /*!< SECSEL1 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSECSR_SECSEL2_Pos        (2UL)          /*!< SECSEL2 (Bit 2)                                       */
+ #define R_GPT0_GTSECSR_SECSEL2_Msk        (0x4UL)        /*!< SECSEL2 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSECSR_SECSEL3_Pos        (3UL)          /*!< SECSEL3 (Bit 3)                                       */
+ #define R_GPT0_GTSECSR_SECSEL3_Msk        (0x8UL)        /*!< SECSEL3 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSECSR_SECSEL4_Pos        (4UL)          /*!< SECSEL4 (Bit 4)                                       */
+ #define R_GPT0_GTSECSR_SECSEL4_Msk        (0x10UL)       /*!< SECSEL4 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSECSR_SECSEL5_Pos        (5UL)          /*!< SECSEL5 (Bit 5)                                       */
+ #define R_GPT0_GTSECSR_SECSEL5_Msk        (0x20UL)       /*!< SECSEL5 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSECSR_SECSEL6_Pos        (6UL)          /*!< SECSEL6 (Bit 6)                                       */
+ #define R_GPT0_GTSECSR_SECSEL6_Msk        (0x40UL)       /*!< SECSEL6 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSECSR_SECSEL7_Pos        (7UL)          /*!< SECSEL7 (Bit 7)                                       */
+ #define R_GPT0_GTSECSR_SECSEL7_Msk        (0x80UL)       /*!< SECSEL7 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSECSR_SECSEL8_Pos        (8UL)          /*!< SECSEL8 (Bit 8)                                       */
+ #define R_GPT0_GTSECSR_SECSEL8_Msk        (0x100UL)      /*!< SECSEL8 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSECSR_SECSEL9_Pos        (9UL)          /*!< SECSEL9 (Bit 9)                                       */
+ #define R_GPT0_GTSECSR_SECSEL9_Msk        (0x200UL)      /*!< SECSEL9 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTSECR  ========================================================= */
+ #define R_GPT0_GTSECR_SBDCE_Pos           (0UL)          /*!< SBDCE (Bit 0)                                         */
+ #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
+ #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
+ #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
+ #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
+ #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
+ #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
+ #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
+ #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTBER2  ========================================================= */
+ #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
+ #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
+ #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
+ #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
+ #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
+ #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
+ #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
+ #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
+ #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
+ #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
+ #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
+ #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
+ #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
+ #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
+ #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
+ #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
+ #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
+ #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
+ #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
+ #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTOLBR  ========================================================= */
+ #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
+ #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
+ #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
+ #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  GTICCR  ========================================================= */
+ #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
+ #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
+ #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
+ #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
+ #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
+ #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
+ #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
+ #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
+ #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
+ #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
+ #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
+ #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
+ #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
+ #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
+ #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
+ #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
+ #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
+ #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
+ #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
+ #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
+ #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
+
+/* =========================================================================================================================== */
+/* ================                                         R_GPT_OPS                                         ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  OPSCR  ========================================================= */
+ #define R_GPT_OPS_OPSCR_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_GPT_OPS_OPSCR_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+ #define R_GPT_OPS_OPSCR_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_GPT_OPS_OPSCR_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_OPS_OPSCR_GODF_Pos     (26UL)         /*!< GODF (Bit 26)                                         */
+ #define R_GPT_OPS_OPSCR_GODF_Msk     (0x4000000UL)  /*!< GODF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_OPS_OPSCR_GRP_Pos      (24UL)         /*!< GRP (Bit 24)                                          */
+ #define R_GPT_OPS_OPSCR_GRP_Msk      (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
+ #define R_GPT_OPS_OPSCR_ALIGN_Pos    (21UL)         /*!< ALIGN (Bit 21)                                        */
+ #define R_GPT_OPS_OPSCR_ALIGN_Msk    (0x200000UL)   /*!< ALIGN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT_OPS_OPSCR_RV_Pos       (20UL)         /*!< RV (Bit 20)                                           */
+ #define R_GPT_OPS_OPSCR_RV_Msk       (0x100000UL)   /*!< RV (Bitfield-Mask: 0x01)                              */
+ #define R_GPT_OPS_OPSCR_INV_Pos      (19UL)         /*!< INV (Bit 19)                                          */
+ #define R_GPT_OPS_OPSCR_INV_Msk      (0x80000UL)    /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_GPT_OPS_OPSCR_N_Pos        (18UL)         /*!< N (Bit 18)                                            */
+ #define R_GPT_OPS_OPSCR_N_Msk        (0x40000UL)    /*!< N (Bitfield-Mask: 0x01)                               */
+ #define R_GPT_OPS_OPSCR_P_Pos        (17UL)         /*!< P (Bit 17)                                            */
+ #define R_GPT_OPS_OPSCR_P_Msk        (0x20000UL)    /*!< P (Bitfield-Mask: 0x01)                               */
+ #define R_GPT_OPS_OPSCR_FB_Pos       (16UL)         /*!< FB (Bit 16)                                           */
+ #define R_GPT_OPS_OPSCR_FB_Msk       (0x10000UL)    /*!< FB (Bitfield-Mask: 0x01)                              */
+ #define R_GPT_OPS_OPSCR_EN_Pos       (8UL)          /*!< EN (Bit 8)                                            */
+ #define R_GPT_OPS_OPSCR_EN_Msk       (0x100UL)      /*!< EN (Bitfield-Mask: 0x01)                              */
+ #define R_GPT_OPS_OPSCR_W_Pos        (6UL)          /*!< W (Bit 6)                                             */
+ #define R_GPT_OPS_OPSCR_W_Msk        (0x40UL)       /*!< W (Bitfield-Mask: 0x01)                               */
+ #define R_GPT_OPS_OPSCR_V_Pos        (5UL)          /*!< V (Bit 5)                                             */
+ #define R_GPT_OPS_OPSCR_V_Msk        (0x20UL)       /*!< V (Bitfield-Mask: 0x01)                               */
+ #define R_GPT_OPS_OPSCR_U_Pos        (4UL)          /*!< U (Bit 4)                                             */
+ #define R_GPT_OPS_OPSCR_U_Msk        (0x10UL)       /*!< U (Bitfield-Mask: 0x01)                               */
+ #define R_GPT_OPS_OPSCR_WF_Pos       (2UL)          /*!< WF (Bit 2)                                            */
+ #define R_GPT_OPS_OPSCR_WF_Msk       (0x4UL)        /*!< WF (Bitfield-Mask: 0x01)                              */
+ #define R_GPT_OPS_OPSCR_VF_Pos       (1UL)          /*!< VF (Bit 1)                                            */
+ #define R_GPT_OPS_OPSCR_VF_Msk       (0x2UL)        /*!< VF (Bitfield-Mask: 0x01)                              */
+ #define R_GPT_OPS_OPSCR_UF_Pos       (0UL)          /*!< UF (Bit 0)                                            */
+ #define R_GPT_OPS_OPSCR_UF_Msk       (0x1UL)        /*!< UF (Bitfield-Mask: 0x01)                              */
+
+/* =========================================================================================================================== */
+/* ================                                        R_GPT_POEG0                                        ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  POEGG  ========================================================= */
+ #define R_GPT_POEG0_POEGG_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_GPT_POEG0_POEGG_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+ #define R_GPT_POEG0_POEGG_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_GPT_POEG0_POEGG_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_POEG0_POEGG_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_GPT_POEG0_POEGG_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_GPT_POEG0_POEGG_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_GPT_POEG0_POEGG_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_GPT_POEG0_POEGG_CDRE_Pos     (8UL)          /*!< CDRE (Bit 8)                                          */
+ #define R_GPT_POEG0_POEGG_CDRE_Msk     (0x100UL)      /*!< CDRE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_POEG0_POEGG_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_GPT_POEG0_POEGG_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT_POEG0_POEGG_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_GPT_POEG0_POEGG_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_POEG0_POEGG_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_GPT_POEG0_POEGG_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_POEG0_POEGG_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_GPT_POEG0_POEGG_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_GPT_POEG0_POEGG_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_GPT_POEG0_POEGG_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT_POEG0_POEGG_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_GPT_POEG0_POEGG_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_POEG0_POEGG_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_GPT_POEG0_POEGG_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ICU                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  IRQCR  ========================================================= */
+ #define R_ICU_IRQCR_FLTEN_Pos           (7UL)          /*!< FLTEN (Bit 7)                                         */
+ #define R_ICU_IRQCR_FLTEN_Msk           (0x80UL)       /*!< FLTEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_IRQCR_FCLKSEL_Pos         (4UL)          /*!< FCLKSEL (Bit 4)                                       */
+ #define R_ICU_IRQCR_FCLKSEL_Msk         (0x30UL)       /*!< FCLKSEL (Bitfield-Mask: 0x03)                         */
+ #define R_ICU_IRQCR_IRQMD_Pos           (0UL)          /*!< IRQMD (Bit 0)                                         */
+ #define R_ICU_IRQCR_IRQMD_Msk           (0x3UL)        /*!< IRQMD (Bitfield-Mask: 0x03)                           */
+/* =========================================================  NMISR  ========================================================= */
+ #define R_ICU_NMISR_SPEST_Pos           (12UL)         /*!< SPEST (Bit 12)                                        */
+ #define R_ICU_NMISR_SPEST_Msk           (0x1000UL)     /*!< SPEST (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMISR_BUSMST_Pos          (11UL)         /*!< BUSMST (Bit 11)                                       */
+ #define R_ICU_NMISR_BUSMST_Msk          (0x800UL)      /*!< BUSMST (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMISR_BUSSST_Pos          (10UL)         /*!< BUSSST (Bit 10)                                       */
+ #define R_ICU_NMISR_BUSSST_Msk          (0x400UL)      /*!< BUSSST (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMISR_RECCST_Pos          (9UL)          /*!< RECCST (Bit 9)                                        */
+ #define R_ICU_NMISR_RECCST_Msk          (0x200UL)      /*!< RECCST (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMISR_RPEST_Pos           (8UL)          /*!< RPEST (Bit 8)                                         */
+ #define R_ICU_NMISR_RPEST_Msk           (0x100UL)      /*!< RPEST (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMISR_NMIST_Pos           (7UL)          /*!< NMIST (Bit 7)                                         */
+ #define R_ICU_NMISR_NMIST_Msk           (0x80UL)       /*!< NMIST (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMISR_OSTST_Pos           (6UL)          /*!< OSTST (Bit 6)                                         */
+ #define R_ICU_NMISR_OSTST_Msk           (0x40UL)       /*!< OSTST (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMISR_VBATTST_Pos         (4UL)          /*!< VBATTST (Bit 4)                                       */
+ #define R_ICU_NMISR_VBATTST_Msk         (0x10UL)       /*!< VBATTST (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMISR_LVD2ST_Pos          (3UL)          /*!< LVD2ST (Bit 3)                                        */
+ #define R_ICU_NMISR_LVD2ST_Msk          (0x8UL)        /*!< LVD2ST (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMISR_LVD1ST_Pos          (2UL)          /*!< LVD1ST (Bit 2)                                        */
+ #define R_ICU_NMISR_LVD1ST_Msk          (0x4UL)        /*!< LVD1ST (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMISR_WDTST_Pos           (1UL)          /*!< WDTST (Bit 1)                                         */
+ #define R_ICU_NMISR_WDTST_Msk           (0x2UL)        /*!< WDTST (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMISR_IWDTST_Pos          (0UL)          /*!< IWDTST (Bit 0)                                        */
+ #define R_ICU_NMISR_IWDTST_Msk          (0x1UL)        /*!< IWDTST (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMISR_TZFST_Pos           (13UL)         /*!< TZFST (Bit 13)                                        */
+ #define R_ICU_NMISR_TZFST_Msk           (0x2000UL)     /*!< TZFST (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMISR_CPEST_Pos           (15UL)         /*!< CPEST (Bit 15)                                        */
+ #define R_ICU_NMISR_CPEST_Msk           (0x8000UL)     /*!< CPEST (Bitfield-Mask: 0x01)                           */
+/* =========================================================  NMIER  ========================================================= */
+ #define R_ICU_NMIER_SPEEN_Pos           (12UL)         /*!< SPEEN (Bit 12)                                        */
+ #define R_ICU_NMIER_SPEEN_Msk           (0x1000UL)     /*!< SPEEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMIER_BUSMEN_Pos          (11UL)         /*!< BUSMEN (Bit 11)                                       */
+ #define R_ICU_NMIER_BUSMEN_Msk          (0x800UL)      /*!< BUSMEN (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMIER_BUSSEN_Pos          (10UL)         /*!< BUSSEN (Bit 10)                                       */
+ #define R_ICU_NMIER_BUSSEN_Msk          (0x400UL)      /*!< BUSSEN (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMIER_RECCEN_Pos          (9UL)          /*!< RECCEN (Bit 9)                                        */
+ #define R_ICU_NMIER_RECCEN_Msk          (0x200UL)      /*!< RECCEN (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMIER_RPEEN_Pos           (8UL)          /*!< RPEEN (Bit 8)                                         */
+ #define R_ICU_NMIER_RPEEN_Msk           (0x100UL)      /*!< RPEEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMIER_NMIEN_Pos           (7UL)          /*!< NMIEN (Bit 7)                                         */
+ #define R_ICU_NMIER_NMIEN_Msk           (0x80UL)       /*!< NMIEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMIER_OSTEN_Pos           (6UL)          /*!< OSTEN (Bit 6)                                         */
+ #define R_ICU_NMIER_OSTEN_Msk           (0x40UL)       /*!< OSTEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMIER_VBATTEN_Pos         (4UL)          /*!< VBATTEN (Bit 4)                                       */
+ #define R_ICU_NMIER_VBATTEN_Msk         (0x10UL)       /*!< VBATTEN (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMIER_LVD2EN_Pos          (3UL)          /*!< LVD2EN (Bit 3)                                        */
+ #define R_ICU_NMIER_LVD2EN_Msk          (0x8UL)        /*!< LVD2EN (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMIER_LVD1EN_Pos          (2UL)          /*!< LVD1EN (Bit 2)                                        */
+ #define R_ICU_NMIER_LVD1EN_Msk          (0x4UL)        /*!< LVD1EN (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMIER_WDTEN_Pos           (1UL)          /*!< WDTEN (Bit 1)                                         */
+ #define R_ICU_NMIER_WDTEN_Msk           (0x2UL)        /*!< WDTEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMIER_IWDTEN_Pos          (0UL)          /*!< IWDTEN (Bit 0)                                        */
+ #define R_ICU_NMIER_IWDTEN_Msk          (0x1UL)        /*!< IWDTEN (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMIER_TZFEN_Pos           (13UL)         /*!< TZFEN (Bit 13)                                        */
+ #define R_ICU_NMIER_TZFEN_Msk           (0x2000UL)     /*!< TZFEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMIER_CPEEN_Pos           (15UL)         /*!< CPEEN (Bit 15)                                        */
+ #define R_ICU_NMIER_CPEEN_Msk           (0x8000UL)     /*!< CPEEN (Bitfield-Mask: 0x01)                           */
+/* ========================================================  NMICLR  ========================================================= */
+ #define R_ICU_NMICLR_SPECLR_Pos         (12UL)         /*!< SPECLR (Bit 12)                                       */
+ #define R_ICU_NMICLR_SPECLR_Msk         (0x1000UL)     /*!< SPECLR (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMICLR_BUSMCLR_Pos        (11UL)         /*!< BUSMCLR (Bit 11)                                      */
+ #define R_ICU_NMICLR_BUSMCLR_Msk        (0x800UL)      /*!< BUSMCLR (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMICLR_BUSSCLR_Pos        (10UL)         /*!< BUSSCLR (Bit 10)                                      */
+ #define R_ICU_NMICLR_BUSSCLR_Msk        (0x400UL)      /*!< BUSSCLR (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMICLR_RECCCLR_Pos        (9UL)          /*!< RECCCLR (Bit 9)                                       */
+ #define R_ICU_NMICLR_RECCCLR_Msk        (0x200UL)      /*!< RECCCLR (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMICLR_RPECLR_Pos         (8UL)          /*!< RPECLR (Bit 8)                                        */
+ #define R_ICU_NMICLR_RPECLR_Msk         (0x100UL)      /*!< RPECLR (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMICLR_NMICLR_Pos         (7UL)          /*!< NMICLR (Bit 7)                                        */
+ #define R_ICU_NMICLR_NMICLR_Msk         (0x80UL)       /*!< NMICLR (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMICLR_OSTCLR_Pos         (6UL)          /*!< OSTCLR (Bit 6)                                        */
+ #define R_ICU_NMICLR_OSTCLR_Msk         (0x40UL)       /*!< OSTCLR (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMICLR_VBATTCLR_Pos       (4UL)          /*!< VBATTCLR (Bit 4)                                      */
+ #define R_ICU_NMICLR_VBATTCLR_Msk       (0x10UL)       /*!< VBATTCLR (Bitfield-Mask: 0x01)                        */
+ #define R_ICU_NMICLR_LVD2CLR_Pos        (3UL)          /*!< LVD2CLR (Bit 3)                                       */
+ #define R_ICU_NMICLR_LVD2CLR_Msk        (0x8UL)        /*!< LVD2CLR (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMICLR_LVD1CLR_Pos        (2UL)          /*!< LVD1CLR (Bit 2)                                       */
+ #define R_ICU_NMICLR_LVD1CLR_Msk        (0x4UL)        /*!< LVD1CLR (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMICLR_WDTCLR_Pos         (1UL)          /*!< WDTCLR (Bit 1)                                        */
+ #define R_ICU_NMICLR_WDTCLR_Msk         (0x2UL)        /*!< WDTCLR (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMICLR_IWDTCLR_Pos        (0UL)          /*!< IWDTCLR (Bit 0)                                       */
+ #define R_ICU_NMICLR_IWDTCLR_Msk        (0x1UL)        /*!< IWDTCLR (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMICLR_TZFCLR_Pos         (13UL)         /*!< TZFCLR (Bit 13)                                       */
+ #define R_ICU_NMICLR_TZFCLR_Msk         (0x2000UL)     /*!< TZFCLR (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMICLR_CPECLR_Pos         (15UL)         /*!< CPECLR (Bit 15)                                       */
+ #define R_ICU_NMICLR_CPECLR_Msk         (0x8000UL)     /*!< CPECLR (Bitfield-Mask: 0x01)                          */
+/* =========================================================  NMICR  ========================================================= */
+ #define R_ICU_NMICR_NFLTEN_Pos          (7UL)          /*!< NFLTEN (Bit 7)                                        */
+ #define R_ICU_NMICR_NFLTEN_Msk          (0x80UL)       /*!< NFLTEN (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMICR_NFCLKSEL_Pos        (4UL)          /*!< NFCLKSEL (Bit 4)                                      */
+ #define R_ICU_NMICR_NFCLKSEL_Msk        (0x30UL)       /*!< NFCLKSEL (Bitfield-Mask: 0x03)                        */
+ #define R_ICU_NMICR_NMIMD_Pos           (0UL)          /*!< NMIMD (Bit 0)                                         */
+ #define R_ICU_NMICR_NMIMD_Msk           (0x1UL)        /*!< NMIMD (Bitfield-Mask: 0x01)                           */
+/* =========================================================  IELSR  ========================================================= */
+ #define R_ICU_IELSR_DTCE_Pos            (24UL)         /*!< DTCE (Bit 24)                                         */
+ #define R_ICU_IELSR_DTCE_Msk            (0x1000000UL)  /*!< DTCE (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_IELSR_IR_Pos              (16UL)         /*!< IR (Bit 16)                                           */
+ #define R_ICU_IELSR_IR_Msk              (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
+ #define R_ICU_IELSR_IELS_Pos            (0UL)          /*!< IELS (Bit 0)                                          */
+ #define R_ICU_IELSR_IELS_Msk            (0x1ffUL)      /*!< IELS (Bitfield-Mask: 0x1ff)                           */
+/* =========================================================  DELSR  ========================================================= */
+ #define R_ICU_DELSR_IR_Pos              (16UL)         /*!< IR (Bit 16)                                           */
+ #define R_ICU_DELSR_IR_Msk              (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
+ #define R_ICU_DELSR_DELS_Pos            (0UL)          /*!< DELS (Bit 0)                                          */
+ #define R_ICU_DELSR_DELS_Msk            (0x1ffUL)      /*!< DELS (Bitfield-Mask: 0x1ff)                           */
+/* ========================================================  SELSR0  ========================================================= */
+ #define R_ICU_SELSR0_SELS_Pos           (0UL)          /*!< SELS (Bit 0)                                          */
+ #define R_ICU_SELSR0_SELS_Msk           (0x1ffUL)      /*!< SELS (Bitfield-Mask: 0x1ff)                           */
+/* =========================================================  WUPEN  ========================================================= */
+ #define R_ICU_WUPEN_IIC0WUPEN_Pos       (31UL)         /*!< IIC0WUPEN (Bit 31)                                    */
+ #define R_ICU_WUPEN_IIC0WUPEN_Msk       (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01)                       */
+ #define R_ICU_WUPEN_AGT1CBWUPEN_Pos     (30UL)         /*!< AGT1CBWUPEN (Bit 30)                                  */
+ #define R_ICU_WUPEN_AGT1CBWUPEN_Msk     (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01)                     */
+ #define R_ICU_WUPEN_AGT1CAWUPEN_Pos     (29UL)         /*!< AGT1CAWUPEN (Bit 29)                                  */
+ #define R_ICU_WUPEN_AGT1CAWUPEN_Msk     (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01)                     */
+ #define R_ICU_WUPEN_AGT1UDWUPEN_Pos     (28UL)         /*!< AGT1UDWUPEN (Bit 28)                                  */
+ #define R_ICU_WUPEN_AGT1UDWUPEN_Msk     (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01)                     */
+ #define R_ICU_WUPEN_USBFSWUPEN_Pos      (27UL)         /*!< USBFSWUPEN (Bit 27)                                   */
+ #define R_ICU_WUPEN_USBFSWUPEN_Msk      (0x8000000UL)  /*!< USBFSWUPEN (Bitfield-Mask: 0x01)                      */
+ #define R_ICU_WUPEN_USBHSWUPEN_Pos      (26UL)         /*!< USBHSWUPEN (Bit 26)                                   */
+ #define R_ICU_WUPEN_USBHSWUPEN_Msk      (0x4000000UL)  /*!< USBHSWUPEN (Bitfield-Mask: 0x01)                      */
+ #define R_ICU_WUPEN_RTCPRDWUPEN_Pos     (25UL)         /*!< RTCPRDWUPEN (Bit 25)                                  */
+ #define R_ICU_WUPEN_RTCPRDWUPEN_Msk     (0x2000000UL)  /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01)                     */
+ #define R_ICU_WUPEN_RTCALMWUPEN_Pos     (24UL)         /*!< RTCALMWUPEN (Bit 24)                                  */
+ #define R_ICU_WUPEN_RTCALMWUPEN_Msk     (0x1000000UL)  /*!< RTCALMWUPEN (Bitfield-Mask: 0x01)                     */
+ #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos    (23UL)         /*!< ACMPLP0WUPEN (Bit 23)                                 */
+ #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk    (0x800000UL)   /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01)                    */
+ #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos    (22UL)         /*!< ACMPHS0WUPEN (Bit 22)                                 */
+ #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk    (0x400000UL)   /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01)                    */
+ #define R_ICU_WUPEN_VBATTWUPEN_Pos      (20UL)         /*!< VBATTWUPEN (Bit 20)                                   */
+ #define R_ICU_WUPEN_VBATTWUPEN_Msk      (0x100000UL)   /*!< VBATTWUPEN (Bitfield-Mask: 0x01)                      */
+ #define R_ICU_WUPEN_LVD2WUPEN_Pos       (19UL)         /*!< LVD2WUPEN (Bit 19)                                    */
+ #define R_ICU_WUPEN_LVD2WUPEN_Msk       (0x80000UL)    /*!< LVD2WUPEN (Bitfield-Mask: 0x01)                       */
+ #define R_ICU_WUPEN_LVD1WUPEN_Pos       (18UL)         /*!< LVD1WUPEN (Bit 18)                                    */
+ #define R_ICU_WUPEN_LVD1WUPEN_Msk       (0x40000UL)    /*!< LVD1WUPEN (Bitfield-Mask: 0x01)                       */
+ #define R_ICU_WUPEN_KEYWUPEN_Pos        (17UL)         /*!< KEYWUPEN (Bit 17)                                     */
+ #define R_ICU_WUPEN_KEYWUPEN_Msk        (0x20000UL)    /*!< KEYWUPEN (Bitfield-Mask: 0x01)                        */
+ #define R_ICU_WUPEN_IWDTWUPEN_Pos       (16UL)         /*!< IWDTWUPEN (Bit 16)                                    */
+ #define R_ICU_WUPEN_IWDTWUPEN_Msk       (0x10000UL)    /*!< IWDTWUPEN (Bitfield-Mask: 0x01)                       */
+ #define R_ICU_WUPEN_IRQWUPEN_Pos        (0UL)          /*!< IRQWUPEN (Bit 0)                                      */
+ #define R_ICU_WUPEN_IRQWUPEN_Msk        (0x1UL)        /*!< IRQWUPEN (Bitfield-Mask: 0x01)                        */
+/* ========================================================  WUPEN1  ========================================================= */
+ #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos    (0UL)          /*!< AGT3UDWUPEN (Bit 0)                                   */
+ #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk    (0x1UL)        /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01)                     */
+ #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos    (1UL)          /*!< AGT3CAWUPEN (Bit 1)                                   */
+ #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk    (0x2UL)        /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01)                     */
+ #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos    (2UL)          /*!< AGT3CBWUPEN (Bit 2)                                   */
+ #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk    (0x4UL)        /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01)                     */
+/* =========================================================  IELEN  ========================================================= */
+ #define R_ICU_IELEN_IELEN_Pos           (1UL)          /*!< IELEN (Bit 1)                                         */
+ #define R_ICU_IELEN_IELEN_Msk           (0x2UL)        /*!< IELEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_IELEN_RTCINTEN_Pos        (0UL)          /*!< RTCINTEN (Bit 0)                                      */
+ #define R_ICU_IELEN_RTCINTEN_Msk        (0x1UL)        /*!< RTCINTEN (Bitfield-Mask: 0x01)                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_IIC0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ICCR1  ========================================================= */
+ #define R_IIC0_ICCR1_ICE_Pos        (7UL)    /*!< ICE (Bit 7)                                           */
+ #define R_IIC0_ICCR1_ICE_Msk        (0x80UL) /*!< ICE (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICCR1_IICRST_Pos     (6UL)    /*!< IICRST (Bit 6)                                        */
+ #define R_IIC0_ICCR1_IICRST_Msk     (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01)                          */
+ #define R_IIC0_ICCR1_CLO_Pos        (5UL)    /*!< CLO (Bit 5)                                           */
+ #define R_IIC0_ICCR1_CLO_Msk        (0x20UL) /*!< CLO (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICCR1_SOWP_Pos       (4UL)    /*!< SOWP (Bit 4)                                          */
+ #define R_IIC0_ICCR1_SOWP_Msk       (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_SCLO_Pos       (3UL)    /*!< SCLO (Bit 3)                                          */
+ #define R_IIC0_ICCR1_SCLO_Msk       (0x8UL)  /*!< SCLO (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_SDAO_Pos       (2UL)    /*!< SDAO (Bit 2)                                          */
+ #define R_IIC0_ICCR1_SDAO_Msk       (0x4UL)  /*!< SDAO (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_SCLI_Pos       (1UL)    /*!< SCLI (Bit 1)                                          */
+ #define R_IIC0_ICCR1_SCLI_Msk       (0x2UL)  /*!< SCLI (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_SDAI_Pos       (0UL)    /*!< SDAI (Bit 0)                                          */
+ #define R_IIC0_ICCR1_SDAI_Msk       (0x1UL)  /*!< SDAI (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICCR2  ========================================================= */
+ #define R_IIC0_ICCR2_BBSY_Pos       (7UL)    /*!< BBSY (Bit 7)                                          */
+ #define R_IIC0_ICCR2_BBSY_Msk       (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR2_MST_Pos        (6UL)    /*!< MST (Bit 6)                                           */
+ #define R_IIC0_ICCR2_MST_Msk        (0x40UL) /*!< MST (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICCR2_TRS_Pos        (5UL)    /*!< TRS (Bit 5)                                           */
+ #define R_IIC0_ICCR2_TRS_Msk        (0x20UL) /*!< TRS (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICCR2_SP_Pos         (3UL)    /*!< SP (Bit 3)                                            */
+ #define R_IIC0_ICCR2_SP_Msk         (0x8UL)  /*!< SP (Bitfield-Mask: 0x01)                              */
+ #define R_IIC0_ICCR2_RS_Pos         (2UL)    /*!< RS (Bit 2)                                            */
+ #define R_IIC0_ICCR2_RS_Msk         (0x4UL)  /*!< RS (Bitfield-Mask: 0x01)                              */
+ #define R_IIC0_ICCR2_ST_Pos         (1UL)    /*!< ST (Bit 1)                                            */
+ #define R_IIC0_ICCR2_ST_Msk         (0x2UL)  /*!< ST (Bitfield-Mask: 0x01)                              */
+/* =========================================================  ICMR1  ========================================================= */
+ #define R_IIC0_ICMR1_MTWP_Pos       (7UL)    /*!< MTWP (Bit 7)                                          */
+ #define R_IIC0_ICMR1_MTWP_Msk       (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR1_CKS_Pos        (4UL)    /*!< CKS (Bit 4)                                           */
+ #define R_IIC0_ICMR1_CKS_Msk        (0x70UL) /*!< CKS (Bitfield-Mask: 0x07)                             */
+ #define R_IIC0_ICMR1_BCWP_Pos       (3UL)    /*!< BCWP (Bit 3)                                          */
+ #define R_IIC0_ICMR1_BCWP_Msk       (0x8UL)  /*!< BCWP (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR1_BC_Pos         (0UL)    /*!< BC (Bit 0)                                            */
+ #define R_IIC0_ICMR1_BC_Msk         (0x7UL)  /*!< BC (Bitfield-Mask: 0x07)                              */
+/* =========================================================  ICMR2  ========================================================= */
+ #define R_IIC0_ICMR2_DLCS_Pos       (7UL)    /*!< DLCS (Bit 7)                                          */
+ #define R_IIC0_ICMR2_DLCS_Msk       (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR2_SDDL_Pos       (4UL)    /*!< SDDL (Bit 4)                                          */
+ #define R_IIC0_ICMR2_SDDL_Msk       (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07)                            */
+ #define R_IIC0_ICMR2_TMOH_Pos       (2UL)    /*!< TMOH (Bit 2)                                          */
+ #define R_IIC0_ICMR2_TMOH_Msk       (0x4UL)  /*!< TMOH (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR2_TMOL_Pos       (1UL)    /*!< TMOL (Bit 1)                                          */
+ #define R_IIC0_ICMR2_TMOL_Msk       (0x2UL)  /*!< TMOL (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR2_TMOS_Pos       (0UL)    /*!< TMOS (Bit 0)                                          */
+ #define R_IIC0_ICMR2_TMOS_Msk       (0x1UL)  /*!< TMOS (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICMR3  ========================================================= */
+ #define R_IIC0_ICMR3_SMBS_Pos       (7UL)    /*!< SMBS (Bit 7)                                          */
+ #define R_IIC0_ICMR3_SMBS_Msk       (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR3_WAIT_Pos       (6UL)    /*!< WAIT (Bit 6)                                          */
+ #define R_IIC0_ICMR3_WAIT_Msk       (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR3_RDRFS_Pos      (5UL)    /*!< RDRFS (Bit 5)                                         */
+ #define R_IIC0_ICMR3_RDRFS_Msk      (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICMR3_ACKWP_Pos      (4UL)    /*!< ACKWP (Bit 4)                                         */
+ #define R_IIC0_ICMR3_ACKWP_Msk      (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICMR3_ACKBT_Pos      (3UL)    /*!< ACKBT (Bit 3)                                         */
+ #define R_IIC0_ICMR3_ACKBT_Msk      (0x8UL)  /*!< ACKBT (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICMR3_ACKBR_Pos      (2UL)    /*!< ACKBR (Bit 2)                                         */
+ #define R_IIC0_ICMR3_ACKBR_Msk      (0x4UL)  /*!< ACKBR (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICMR3_NF_Pos         (0UL)    /*!< NF (Bit 0)                                            */
+ #define R_IIC0_ICMR3_NF_Msk         (0x3UL)  /*!< NF (Bitfield-Mask: 0x03)                              */
+/* =========================================================  ICFER  ========================================================= */
+ #define R_IIC0_ICFER_FMPE_Pos       (7UL)    /*!< FMPE (Bit 7)                                          */
+ #define R_IIC0_ICFER_FMPE_Msk       (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_SCLE_Pos       (6UL)    /*!< SCLE (Bit 6)                                          */
+ #define R_IIC0_ICFER_SCLE_Msk       (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_NFE_Pos        (5UL)    /*!< NFE (Bit 5)                                           */
+ #define R_IIC0_ICFER_NFE_Msk        (0x20UL) /*!< NFE (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICFER_NACKE_Pos      (4UL)    /*!< NACKE (Bit 4)                                         */
+ #define R_IIC0_ICFER_NACKE_Msk      (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICFER_SALE_Pos       (3UL)    /*!< SALE (Bit 3)                                          */
+ #define R_IIC0_ICFER_SALE_Msk       (0x8UL)  /*!< SALE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_NALE_Pos       (2UL)    /*!< NALE (Bit 2)                                          */
+ #define R_IIC0_ICFER_NALE_Msk       (0x4UL)  /*!< NALE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_MALE_Pos       (1UL)    /*!< MALE (Bit 1)                                          */
+ #define R_IIC0_ICFER_MALE_Msk       (0x2UL)  /*!< MALE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_TMOE_Pos       (0UL)    /*!< TMOE (Bit 0)                                          */
+ #define R_IIC0_ICFER_TMOE_Msk       (0x1UL)  /*!< TMOE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICSER  ========================================================= */
+ #define R_IIC0_ICSER_HOAE_Pos       (7UL)    /*!< HOAE (Bit 7)                                          */
+ #define R_IIC0_ICSER_HOAE_Msk       (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSER_DIDE_Pos       (5UL)    /*!< DIDE (Bit 5)                                          */
+ #define R_IIC0_ICSER_DIDE_Msk       (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSER_GCAE_Pos       (3UL)    /*!< GCAE (Bit 3)                                          */
+ #define R_IIC0_ICSER_GCAE_Msk       (0x8UL)  /*!< GCAE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSER_SAR2E_Pos      (2UL)    /*!< SAR2E (Bit 2)                                         */
+ #define R_IIC0_ICSER_SAR2E_Msk      (0x4UL)  /*!< SAR2E (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSER_SAR1E_Pos      (1UL)    /*!< SAR1E (Bit 1)                                         */
+ #define R_IIC0_ICSER_SAR1E_Msk      (0x2UL)  /*!< SAR1E (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSER_SAR0E_Pos      (0UL)    /*!< SAR0E (Bit 0)                                         */
+ #define R_IIC0_ICSER_SAR0E_Msk      (0x1UL)  /*!< SAR0E (Bitfield-Mask: 0x01)                           */
+/* =========================================================  ICIER  ========================================================= */
+ #define R_IIC0_ICIER_TIE_Pos        (7UL)    /*!< TIE (Bit 7)                                           */
+ #define R_IIC0_ICIER_TIE_Msk        (0x80UL) /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICIER_TEIE_Pos       (6UL)    /*!< TEIE (Bit 6)                                          */
+ #define R_IIC0_ICIER_TEIE_Msk       (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICIER_RIE_Pos        (5UL)    /*!< RIE (Bit 5)                                           */
+ #define R_IIC0_ICIER_RIE_Msk        (0x20UL) /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICIER_NAKIE_Pos      (4UL)    /*!< NAKIE (Bit 4)                                         */
+ #define R_IIC0_ICIER_NAKIE_Msk      (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICIER_SPIE_Pos       (3UL)    /*!< SPIE (Bit 3)                                          */
+ #define R_IIC0_ICIER_SPIE_Msk       (0x8UL)  /*!< SPIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICIER_STIE_Pos       (2UL)    /*!< STIE (Bit 2)                                          */
+ #define R_IIC0_ICIER_STIE_Msk       (0x4UL)  /*!< STIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICIER_ALIE_Pos       (1UL)    /*!< ALIE (Bit 1)                                          */
+ #define R_IIC0_ICIER_ALIE_Msk       (0x2UL)  /*!< ALIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICIER_TMOIE_Pos      (0UL)    /*!< TMOIE (Bit 0)                                         */
+ #define R_IIC0_ICIER_TMOIE_Msk      (0x1UL)  /*!< TMOIE (Bitfield-Mask: 0x01)                           */
+/* =========================================================  ICSR1  ========================================================= */
+ #define R_IIC0_ICSR1_HOA_Pos        (7UL)    /*!< HOA (Bit 7)                                           */
+ #define R_IIC0_ICSR1_HOA_Msk        (0x80UL) /*!< HOA (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICSR1_DID_Pos        (5UL)    /*!< DID (Bit 5)                                           */
+ #define R_IIC0_ICSR1_DID_Msk        (0x20UL) /*!< DID (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICSR1_GCA_Pos        (3UL)    /*!< GCA (Bit 3)                                           */
+ #define R_IIC0_ICSR1_GCA_Msk        (0x8UL)  /*!< GCA (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICSR1_AAS2_Pos       (2UL)    /*!< AAS2 (Bit 2)                                          */
+ #define R_IIC0_ICSR1_AAS2_Msk       (0x4UL)  /*!< AAS2 (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR1_AAS1_Pos       (1UL)    /*!< AAS1 (Bit 1)                                          */
+ #define R_IIC0_ICSR1_AAS1_Msk       (0x2UL)  /*!< AAS1 (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR1_AAS0_Pos       (0UL)    /*!< AAS0 (Bit 0)                                          */
+ #define R_IIC0_ICSR1_AAS0_Msk       (0x1UL)  /*!< AAS0 (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICSR2  ========================================================= */
+ #define R_IIC0_ICSR2_TDRE_Pos       (7UL)    /*!< TDRE (Bit 7)                                          */
+ #define R_IIC0_ICSR2_TDRE_Msk       (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR2_TEND_Pos       (6UL)    /*!< TEND (Bit 6)                                          */
+ #define R_IIC0_ICSR2_TEND_Msk       (0x40UL) /*!< TEND (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR2_RDRF_Pos       (5UL)    /*!< RDRF (Bit 5)                                          */
+ #define R_IIC0_ICSR2_RDRF_Msk       (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR2_NACKF_Pos      (4UL)    /*!< NACKF (Bit 4)                                         */
+ #define R_IIC0_ICSR2_NACKF_Msk      (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSR2_STOP_Pos       (3UL)    /*!< STOP (Bit 3)                                          */
+ #define R_IIC0_ICSR2_STOP_Msk       (0x8UL)  /*!< STOP (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR2_START_Pos      (2UL)    /*!< START (Bit 2)                                         */
+ #define R_IIC0_ICSR2_START_Msk      (0x4UL)  /*!< START (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSR2_AL_Pos         (1UL)    /*!< AL (Bit 1)                                            */
+ #define R_IIC0_ICSR2_AL_Msk         (0x2UL)  /*!< AL (Bitfield-Mask: 0x01)                              */
+ #define R_IIC0_ICSR2_TMOF_Pos       (0UL)    /*!< TMOF (Bit 0)                                          */
+ #define R_IIC0_ICSR2_TMOF_Msk       (0x1UL)  /*!< TMOF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICBRL  ========================================================= */
+ #define R_IIC0_ICBRL_BRL_Pos        (0UL)    /*!< BRL (Bit 0)                                           */
+ #define R_IIC0_ICBRL_BRL_Msk        (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f)                             */
+/* =========================================================  ICBRH  ========================================================= */
+ #define R_IIC0_ICBRH_BRH_Pos        (0UL)    /*!< BRH (Bit 0)                                           */
+ #define R_IIC0_ICBRH_BRH_Msk        (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f)                             */
+/* =========================================================  ICDRT  ========================================================= */
+ #define R_IIC0_ICDRT_ICDRT_Pos      (0UL)    /*!< ICDRT (Bit 0)                                         */
+ #define R_IIC0_ICDRT_ICDRT_Msk      (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff)                           */
+/* =========================================================  ICDRR  ========================================================= */
+ #define R_IIC0_ICDRR_ICDRR_Pos      (0UL)    /*!< ICDRR (Bit 0)                                         */
+ #define R_IIC0_ICDRR_ICDRR_Msk      (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff)                           */
+/* =========================================================  ICWUR  ========================================================= */
+ #define R_IIC0_ICWUR_WUE_Pos        (7UL)    /*!< WUE (Bit 7)                                           */
+ #define R_IIC0_ICWUR_WUE_Msk        (0x80UL) /*!< WUE (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICWUR_WUIE_Pos       (6UL)    /*!< WUIE (Bit 6)                                          */
+ #define R_IIC0_ICWUR_WUIE_Msk       (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICWUR_WUF_Pos        (5UL)    /*!< WUF (Bit 5)                                           */
+ #define R_IIC0_ICWUR_WUF_Msk        (0x20UL) /*!< WUF (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICWUR_WUACK_Pos      (4UL)    /*!< WUACK (Bit 4)                                         */
+ #define R_IIC0_ICWUR_WUACK_Msk      (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICWUR_WUAFA_Pos      (0UL)    /*!< WUAFA (Bit 0)                                         */
+ #define R_IIC0_ICWUR_WUAFA_Msk      (0x1UL)  /*!< WUAFA (Bitfield-Mask: 0x01)                           */
+/* ========================================================  ICWUR2  ========================================================= */
+ #define R_IIC0_ICWUR2_WUSYF_Pos     (2UL)    /*!< WUSYF (Bit 2)                                         */
+ #define R_IIC0_ICWUR2_WUSYF_Msk     (0x4UL)  /*!< WUSYF (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICWUR2_WUASYF_Pos    (1UL)    /*!< WUASYF (Bit 1)                                        */
+ #define R_IIC0_ICWUR2_WUASYF_Msk    (0x2UL)  /*!< WUASYF (Bitfield-Mask: 0x01)                          */
+ #define R_IIC0_ICWUR2_WUSEN_Pos     (0UL)    /*!< WUSEN (Bit 0)                                         */
+ #define R_IIC0_ICWUR2_WUSEN_Msk     (0x1UL)  /*!< WUSEN (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                          R_IWDT                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  IWDTRR  ========================================================= */
+ #define R_IWDT_IWDTRR_IWDTRR_Pos       (0UL)      /*!< IWDTRR (Bit 0)                                        */
+ #define R_IWDT_IWDTRR_IWDTRR_Msk       (0xffUL)   /*!< IWDTRR (Bitfield-Mask: 0xff)                          */
+/* ========================================================  IWDTCR  ========================================================= */
+ #define R_IWDT_IWDTCR_RPSS_Pos         (12UL)     /*!< RPSS (Bit 12)                                         */
+ #define R_IWDT_IWDTCR_RPSS_Msk         (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
+ #define R_IWDT_IWDTCR_RPES_Pos         (8UL)      /*!< RPES (Bit 8)                                          */
+ #define R_IWDT_IWDTCR_RPES_Msk         (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
+ #define R_IWDT_IWDTCR_CKS_Pos          (4UL)      /*!< CKS (Bit 4)                                           */
+ #define R_IWDT_IWDTCR_CKS_Msk          (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
+ #define R_IWDT_IWDTCR_TOPS_Pos         (0UL)      /*!< TOPS (Bit 0)                                          */
+ #define R_IWDT_IWDTCR_TOPS_Msk         (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
+/* ========================================================  IWDTSR  ========================================================= */
+ #define R_IWDT_IWDTSR_REFEF_Pos        (15UL)     /*!< REFEF (Bit 15)                                        */
+ #define R_IWDT_IWDTSR_REFEF_Msk        (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
+ #define R_IWDT_IWDTSR_UNDFF_Pos        (14UL)     /*!< UNDFF (Bit 14)                                        */
+ #define R_IWDT_IWDTSR_UNDFF_Msk        (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
+ #define R_IWDT_IWDTSR_CNTVAL_Pos       (0UL)      /*!< CNTVAL (Bit 0)                                        */
+ #define R_IWDT_IWDTSR_CNTVAL_Msk       (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
+/* ========================================================  IWDTRCR  ======================================================== */
+ #define R_IWDT_IWDTRCR_RSTIRQS_Pos     (7UL)      /*!< RSTIRQS (Bit 7)                                       */
+ #define R_IWDT_IWDTRCR_RSTIRQS_Msk     (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
+/* =======================================================  IWDTCSTPR  ======================================================= */
+ #define R_IWDT_IWDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
+ #define R_IWDT_IWDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_I3C0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  PRTS  ========================================================== */
+ #define R_I3C0_PRTS_PRTMD_Pos          (0UL)          /*!< PRTMD (Bit 0)                                         */
+ #define R_I3C0_PRTS_PRTMD_Msk          (0x1UL)        /*!< PRTMD (Bitfield-Mask: 0x01)                           */
+/* =========================================================  CECTL  ========================================================= */
+ #define R_I3C0_CECTL_CLKE_Pos          (0UL)          /*!< CLKE (Bit 0)                                          */
+ #define R_I3C0_CECTL_CLKE_Msk          (0x1UL)        /*!< CLKE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  BCTL  ========================================================== */
+ #define R_I3C0_BCTL_INCBA_Pos          (0UL)          /*!< INCBA (Bit 0)                                         */
+ #define R_I3C0_BCTL_INCBA_Msk          (0x1UL)        /*!< INCBA (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_BCTL_BMDS_Pos           (7UL)          /*!< BMDS (Bit 7)                                          */
+ #define R_I3C0_BCTL_BMDS_Msk           (0x80UL)       /*!< BMDS (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_BCTL_HJACKCTL_Pos       (8UL)          /*!< HJACKCTL (Bit 8)                                      */
+ #define R_I3C0_BCTL_HJACKCTL_Msk       (0x100UL)      /*!< HJACKCTL (Bitfield-Mask: 0x01)                        */
+ #define R_I3C0_BCTL_ABT_Pos            (29UL)         /*!< ABT (Bit 29)                                          */
+ #define R_I3C0_BCTL_ABT_Msk            (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01)                             */
+ #define R_I3C0_BCTL_RSM_Pos            (30UL)         /*!< RSM (Bit 30)                                          */
+ #define R_I3C0_BCTL_RSM_Msk            (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01)                             */
+ #define R_I3C0_BCTL_BUSE_Pos           (31UL)         /*!< BUSE (Bit 31)                                         */
+ #define R_I3C0_BCTL_BUSE_Msk           (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  MSDVAD  ========================================================= */
+ #define R_I3C0_MSDVAD_MDYAD_Pos        (16UL)         /*!< MDYAD (Bit 16)                                        */
+ #define R_I3C0_MSDVAD_MDYAD_Msk        (0x7f0000UL)   /*!< MDYAD (Bitfield-Mask: 0x7f)                           */
+ #define R_I3C0_MSDVAD_MDYADV_Pos       (31UL)         /*!< MDYADV (Bit 31)                                       */
+ #define R_I3C0_MSDVAD_MDYADV_Msk       (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01)                          */
+/* ========================================================  RSTCTL  ========================================================= */
+ #define R_I3C0_RSTCTL_RI3CRST_Pos      (0UL)          /*!< RI3CRST (Bit 0)                                       */
+ #define R_I3C0_RSTCTL_RI3CRST_Msk      (0x1UL)        /*!< RI3CRST (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_RSTCTL_CMDQRST_Pos      (1UL)          /*!< CMDQRST (Bit 1)                                       */
+ #define R_I3C0_RSTCTL_CMDQRST_Msk      (0x2UL)        /*!< CMDQRST (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_RSTCTL_RSPQRST_Pos      (2UL)          /*!< RSPQRST (Bit 2)                                       */
+ #define R_I3C0_RSTCTL_RSPQRST_Msk      (0x4UL)        /*!< RSPQRST (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_RSTCTL_TDBRST_Pos       (3UL)          /*!< TDBRST (Bit 3)                                        */
+ #define R_I3C0_RSTCTL_TDBRST_Msk       (0x8UL)        /*!< TDBRST (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_RSTCTL_RDBRST_Pos       (4UL)          /*!< RDBRST (Bit 4)                                        */
+ #define R_I3C0_RSTCTL_RDBRST_Msk       (0x10UL)       /*!< RDBRST (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_RSTCTL_IBIQRST_Pos      (5UL)          /*!< IBIQRST (Bit 5)                                       */
+ #define R_I3C0_RSTCTL_IBIQRST_Msk      (0x20UL)       /*!< IBIQRST (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_RSTCTL_RSQRST_Pos       (6UL)          /*!< RSQRST (Bit 6)                                        */
+ #define R_I3C0_RSTCTL_RSQRST_Msk       (0x40UL)       /*!< RSQRST (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_RSTCTL_INTLRST_Pos      (16UL)         /*!< INTLRST (Bit 16)                                      */
+ #define R_I3C0_RSTCTL_INTLRST_Msk      (0x10000UL)    /*!< INTLRST (Bitfield-Mask: 0x01)                         */
+/* =========================================================  PRSST  ========================================================= */
+ #define R_I3C0_PRSST_CRMS_Pos          (2UL)          /*!< CRMS (Bit 2)                                          */
+ #define R_I3C0_PRSST_CRMS_Msk          (0x4UL)        /*!< CRMS (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_PRSST_TRMD_Pos          (4UL)          /*!< TRMD (Bit 4)                                          */
+ #define R_I3C0_PRSST_TRMD_Msk          (0x10UL)       /*!< TRMD (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_PRSST_PRSSTWP_Pos       (7UL)          /*!< PRSSTWP (Bit 7)                                       */
+ #define R_I3C0_PRSST_PRSSTWP_Msk       (0x80UL)       /*!< PRSSTWP (Bitfield-Mask: 0x01)                         */
+/* =========================================================  INST  ========================================================== */
+ #define R_I3C0_INST_INEF_Pos           (10UL)         /*!< INEF (Bit 10)                                         */
+ #define R_I3C0_INST_INEF_Msk           (0x400UL)      /*!< INEF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  INSTE  ========================================================= */
+ #define R_I3C0_INSTE_INEE_Pos          (10UL)         /*!< INEE (Bit 10)                                         */
+ #define R_I3C0_INSTE_INEE_Msk          (0x400UL)      /*!< INEE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  INIE  ========================================================== */
+ #define R_I3C0_INIE_INEIE_Pos          (10UL)         /*!< INEIE (Bit 10)                                        */
+ #define R_I3C0_INIE_INEIE_Msk          (0x400UL)      /*!< INEIE (Bitfield-Mask: 0x01)                           */
+/* ========================================================  INSTFC  ========================================================= */
+ #define R_I3C0_INSTFC_INEFC_Pos        (10UL)         /*!< INEFC (Bit 10)                                        */
+ #define R_I3C0_INSTFC_INEFC_Msk        (0x400UL)      /*!< INEFC (Bitfield-Mask: 0x01)                           */
+/* =========================================================  DVCT  ========================================================== */
+ #define R_I3C0_DVCT_IDX_Pos            (19UL)         /*!< IDX (Bit 19)                                          */
+ #define R_I3C0_DVCT_IDX_Msk            (0xf80000UL)   /*!< IDX (Bitfield-Mask: 0x1f)                             */
+/* ========================================================  IBINCTL  ======================================================== */
+ #define R_I3C0_IBINCTL_NRHJCTL_Pos     (0UL)          /*!< NRHJCTL (Bit 0)                                       */
+ #define R_I3C0_IBINCTL_NRHJCTL_Msk     (0x1UL)        /*!< NRHJCTL (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_IBINCTL_NRMRCTL_Pos     (1UL)          /*!< NRMRCTL (Bit 1)                                       */
+ #define R_I3C0_IBINCTL_NRMRCTL_Msk     (0x2UL)        /*!< NRMRCTL (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_IBINCTL_NRSIRCTL_Pos    (3UL)          /*!< NRSIRCTL (Bit 3)                                      */
+ #define R_I3C0_IBINCTL_NRSIRCTL_Msk    (0x8UL)        /*!< NRSIRCTL (Bitfield-Mask: 0x01)                        */
+/* =========================================================  BFCTL  ========================================================= */
+ #define R_I3C0_BFCTL_MALE_Pos          (0UL)          /*!< MALE (Bit 0)                                          */
+ #define R_I3C0_BFCTL_MALE_Msk          (0x1UL)        /*!< MALE (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_BFCTL_NALE_Pos          (1UL)          /*!< NALE (Bit 1)                                          */
+ #define R_I3C0_BFCTL_NALE_Msk          (0x2UL)        /*!< NALE (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_BFCTL_SALE_Pos          (2UL)          /*!< SALE (Bit 2)                                          */
+ #define R_I3C0_BFCTL_SALE_Msk          (0x4UL)        /*!< SALE (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_BFCTL_SCSYNE_Pos        (8UL)          /*!< SCSYNE (Bit 8)                                        */
+ #define R_I3C0_BFCTL_SCSYNE_Msk        (0x100UL)      /*!< SCSYNE (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_BFCTL_SMBS_Pos          (12UL)         /*!< SMBS (Bit 12)                                         */
+ #define R_I3C0_BFCTL_SMBS_Msk          (0x1000UL)     /*!< SMBS (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_BFCTL_FMPE_Pos          (14UL)         /*!< FMPE (Bit 14)                                         */
+ #define R_I3C0_BFCTL_FMPE_Msk          (0x4000UL)     /*!< FMPE (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_BFCTL_HSME_Pos          (15UL)         /*!< HSME (Bit 15)                                         */
+ #define R_I3C0_BFCTL_HSME_Msk          (0x8000UL)     /*!< HSME (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SVCTL  ========================================================= */
+ #define R_I3C0_SVCTL_GCAE_Pos          (0UL)          /*!< GCAE (Bit 0)                                          */
+ #define R_I3C0_SVCTL_GCAE_Msk          (0x1UL)        /*!< GCAE (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_SVCTL_HSMCE_Pos         (5UL)          /*!< HSMCE (Bit 5)                                         */
+ #define R_I3C0_SVCTL_HSMCE_Msk         (0x20UL)       /*!< HSMCE (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SVCTL_DVIDE_Pos         (6UL)          /*!< DVIDE (Bit 6)                                         */
+ #define R_I3C0_SVCTL_DVIDE_Msk         (0x40UL)       /*!< DVIDE (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SVCTL_HOAE_Pos          (15UL)         /*!< HOAE (Bit 15)                                         */
+ #define R_I3C0_SVCTL_HOAE_Msk          (0x8000UL)     /*!< HOAE (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_SVCTL_SVAEn_Pos         (16UL)         /*!< SVAEn (Bit 16)                                        */
+ #define R_I3C0_SVCTL_SVAEn_Msk         (0x10000UL)    /*!< SVAEn (Bitfield-Mask: 0x01)                           */
+/* =======================================================  REFCKCTL  ======================================================== */
+ #define R_I3C0_REFCKCTL_IREFCKS_Pos    (0UL)          /*!< IREFCKS (Bit 0)                                       */
+ #define R_I3C0_REFCKCTL_IREFCKS_Msk    (0x7UL)        /*!< IREFCKS (Bitfield-Mask: 0x07)                         */
+/* =========================================================  STDBR  ========================================================= */
+ #define R_I3C0_STDBR_SBRLO_Pos         (0UL)          /*!< SBRLO (Bit 0)                                         */
+ #define R_I3C0_STDBR_SBRLO_Msk         (0xffUL)       /*!< SBRLO (Bitfield-Mask: 0xff)                           */
+ #define R_I3C0_STDBR_SBRHO_Pos         (8UL)          /*!< SBRHO (Bit 8)                                         */
+ #define R_I3C0_STDBR_SBRHO_Msk         (0xff00UL)     /*!< SBRHO (Bitfield-Mask: 0xff)                           */
+ #define R_I3C0_STDBR_SBRLP_Pos         (16UL)         /*!< SBRLP (Bit 16)                                        */
+ #define R_I3C0_STDBR_SBRLP_Msk         (0x3f0000UL)   /*!< SBRLP (Bitfield-Mask: 0x3f)                           */
+ #define R_I3C0_STDBR_SBRHP_Pos         (24UL)         /*!< SBRHP (Bit 24)                                        */
+ #define R_I3C0_STDBR_SBRHP_Msk         (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f)                           */
+ #define R_I3C0_STDBR_DSBRPO_Pos        (31UL)         /*!< DSBRPO (Bit 31)                                       */
+ #define R_I3C0_STDBR_DSBRPO_Msk        (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01)                          */
+/* =========================================================  EXTBR  ========================================================= */
+ #define R_I3C0_EXTBR_EBRLO_Pos         (0UL)          /*!< EBRLO (Bit 0)                                         */
+ #define R_I3C0_EXTBR_EBRLO_Msk         (0xffUL)       /*!< EBRLO (Bitfield-Mask: 0xff)                           */
+ #define R_I3C0_EXTBR_EBRHO_Pos         (8UL)          /*!< EBRHO (Bit 8)                                         */
+ #define R_I3C0_EXTBR_EBRHO_Msk         (0xff00UL)     /*!< EBRHO (Bitfield-Mask: 0xff)                           */
+ #define R_I3C0_EXTBR_EBRLP_Pos         (16UL)         /*!< EBRLP (Bit 16)                                        */
+ #define R_I3C0_EXTBR_EBRLP_Msk         (0x3f0000UL)   /*!< EBRLP (Bitfield-Mask: 0x3f)                           */
+ #define R_I3C0_EXTBR_EBRHP_Pos         (24UL)         /*!< EBRHP (Bit 24)                                        */
+ #define R_I3C0_EXTBR_EBRHP_Msk         (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f)                           */
+/* ========================================================  BFRECDT  ======================================================== */
+ #define R_I3C0_BFRECDT_FRECYC_Pos      (0UL)          /*!< FRECYC (Bit 0)                                        */
+ #define R_I3C0_BFRECDT_FRECYC_Msk      (0x1ffUL)      /*!< FRECYC (Bitfield-Mask: 0x1ff)                         */
+/* ========================================================  BAVLCDT  ======================================================== */
+ #define R_I3C0_BAVLCDT_AVLCYC_Pos      (0UL)          /*!< AVLCYC (Bit 0)                                        */
+ #define R_I3C0_BAVLCDT_AVLCYC_Msk      (0x1ffUL)      /*!< AVLCYC (Bitfield-Mask: 0x1ff)                         */
+/* ========================================================  BIDLCDT  ======================================================== */
+ #define R_I3C0_BIDLCDT_IDLCYC_Pos      (0UL)          /*!< IDLCYC (Bit 0)                                        */
+ #define R_I3C0_BIDLCDT_IDLCYC_Msk      (0x3ffffUL)    /*!< IDLCYC (Bitfield-Mask: 0x3ffff)                       */
+/* ========================================================  OUTCTL  ========================================================= */
+ #define R_I3C0_OUTCTL_SDOC_Pos         (0UL)          /*!< SDOC (Bit 0)                                          */
+ #define R_I3C0_OUTCTL_SDOC_Msk         (0x1UL)        /*!< SDOC (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_OUTCTL_SCOC_Pos         (1UL)          /*!< SCOC (Bit 1)                                          */
+ #define R_I3C0_OUTCTL_SCOC_Msk         (0x2UL)        /*!< SCOC (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_OUTCTL_SOCWP_Pos        (2UL)          /*!< SOCWP (Bit 2)                                         */
+ #define R_I3C0_OUTCTL_SOCWP_Msk        (0x4UL)        /*!< SOCWP (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_OUTCTL_EXCYC_Pos        (4UL)          /*!< EXCYC (Bit 4)                                         */
+ #define R_I3C0_OUTCTL_EXCYC_Msk        (0x10UL)       /*!< EXCYC (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_OUTCTL_SDOD_Pos         (8UL)          /*!< SDOD (Bit 8)                                          */
+ #define R_I3C0_OUTCTL_SDOD_Msk         (0x700UL)      /*!< SDOD (Bitfield-Mask: 0x07)                            */
+ #define R_I3C0_OUTCTL_SDODCS_Pos       (15UL)         /*!< SDODCS (Bit 15)                                       */
+ #define R_I3C0_OUTCTL_SDODCS_Msk       (0x8000UL)     /*!< SDODCS (Bitfield-Mask: 0x01)                          */
+/* =========================================================  INCTL  ========================================================= */
+ #define R_I3C0_INCTL_DNFS_Pos          (0UL)          /*!< DNFS (Bit 0)                                          */
+ #define R_I3C0_INCTL_DNFS_Msk          (0xfUL)        /*!< DNFS (Bitfield-Mask: 0x0f)                            */
+ #define R_I3C0_INCTL_DNFE_Pos          (4UL)          /*!< DNFE (Bit 4)                                          */
+ #define R_I3C0_INCTL_DNFE_Msk          (0x10UL)       /*!< DNFE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  TMOCTL  ========================================================= */
+ #define R_I3C0_TMOCTL_TODTS_Pos        (0UL)          /*!< TODTS (Bit 0)                                         */
+ #define R_I3C0_TMOCTL_TODTS_Msk        (0x3UL)        /*!< TODTS (Bitfield-Mask: 0x03)                           */
+ #define R_I3C0_TMOCTL_TOLCTL_Pos       (4UL)          /*!< TOLCTL (Bit 4)                                        */
+ #define R_I3C0_TMOCTL_TOLCTL_Msk       (0x10UL)       /*!< TOLCTL (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_TMOCTL_TOHCTL_Pos       (5UL)          /*!< TOHCTL (Bit 5)                                        */
+ #define R_I3C0_TMOCTL_TOHCTL_Msk       (0x20UL)       /*!< TOHCTL (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_TMOCTL_TOMDS_Pos        (6UL)          /*!< TOMDS (Bit 6)                                         */
+ #define R_I3C0_TMOCTL_TOMDS_Msk        (0xc0UL)       /*!< TOMDS (Bitfield-Mask: 0x03)                           */
+/* =========================================================  WUCTL  ========================================================= */
+ #define R_I3C0_WUCTL_WUACKS_Pos        (0UL)          /*!< WUACKS (Bit 0)                                        */
+ #define R_I3C0_WUCTL_WUACKS_Msk        (0x1UL)        /*!< WUACKS (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_WUCTL_WUANFS_Pos        (4UL)          /*!< WUANFS (Bit 4)                                        */
+ #define R_I3C0_WUCTL_WUANFS_Msk        (0x10UL)       /*!< WUANFS (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_WUCTL_WUFSYNE_Pos       (6UL)          /*!< WUFSYNE (Bit 6)                                       */
+ #define R_I3C0_WUCTL_WUFSYNE_Msk       (0x40UL)       /*!< WUFSYNE (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_WUCTL_WUFE_Pos          (7UL)          /*!< WUFE (Bit 7)                                          */
+ #define R_I3C0_WUCTL_WUFE_Msk          (0x80UL)       /*!< WUFE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  ACKCTL  ========================================================= */
+ #define R_I3C0_ACKCTL_ACKR_Pos         (0UL)          /*!< ACKR (Bit 0)                                          */
+ #define R_I3C0_ACKCTL_ACKR_Msk         (0x1UL)        /*!< ACKR (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_ACKCTL_ACKT_Pos         (1UL)          /*!< ACKT (Bit 1)                                          */
+ #define R_I3C0_ACKCTL_ACKT_Msk         (0x2UL)        /*!< ACKT (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_ACKCTL_ACKTWP_Pos       (2UL)          /*!< ACKTWP (Bit 2)                                        */
+ #define R_I3C0_ACKCTL_ACKTWP_Msk       (0x4UL)        /*!< ACKTWP (Bitfield-Mask: 0x01)                          */
+/* =======================================================  SCSTRCTL  ======================================================== */
+ #define R_I3C0_SCSTRCTL_ACKTWE_Pos     (0UL)          /*!< ACKTWE (Bit 0)                                        */
+ #define R_I3C0_SCSTRCTL_ACKTWE_Msk     (0x1UL)        /*!< ACKTWE (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_SCSTRCTL_RWE_Pos        (1UL)          /*!< RWE (Bit 1)                                           */
+ #define R_I3C0_SCSTRCTL_RWE_Msk        (0x2UL)        /*!< RWE (Bitfield-Mask: 0x01)                             */
+/* =======================================================  SCSTLCTL  ======================================================== */
+ #define R_I3C0_SCSTLCTL_STLCYC_Pos     (0UL)          /*!< STLCYC (Bit 0)                                        */
+ #define R_I3C0_SCSTLCTL_STLCYC_Msk     (0xffffUL)     /*!< STLCYC (Bitfield-Mask: 0xffff)                        */
+ #define R_I3C0_SCSTLCTL_AAPE_Pos       (28UL)         /*!< AAPE (Bit 28)                                         */
+ #define R_I3C0_SCSTLCTL_AAPE_Msk       (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_SCSTLCTL_TRAPE_Pos      (29UL)         /*!< TRAPE (Bit 29)                                        */
+ #define R_I3C0_SCSTLCTL_TRAPE_Msk      (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SCSTLCTL_PARPE_Pos      (30UL)         /*!< PARPE (Bit 30)                                        */
+ #define R_I3C0_SCSTLCTL_PARPE_Msk      (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SCSTLCTL_ACKPE_Pos      (31UL)         /*!< ACKPE (Bit 31)                                        */
+ #define R_I3C0_SCSTLCTL_ACKPE_Msk      (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01)                           */
+/* ========================================================  SVTDLG0  ======================================================== */
+ #define R_I3C0_SVTDLG0_STDLG_Pos       (16UL)         /*!< STDLG (Bit 16)                                        */
+ #define R_I3C0_SVTDLG0_STDLG_Msk       (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  CNDCTL  ========================================================= */
+ #define R_I3C0_CNDCTL_STCND_Pos        (0UL)          /*!< STCND (Bit 0)                                         */
+ #define R_I3C0_CNDCTL_STCND_Msk        (0x1UL)        /*!< STCND (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_CNDCTL_SRCND_Pos        (1UL)          /*!< SRCND (Bit 1)                                         */
+ #define R_I3C0_CNDCTL_SRCND_Msk        (0x2UL)        /*!< SRCND (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_CNDCTL_SPCND_Pos        (2UL)          /*!< SPCND (Bit 2)                                         */
+ #define R_I3C0_CNDCTL_SPCND_Msk        (0x4UL)        /*!< SPCND (Bitfield-Mask: 0x01)                           */
+/* ========================================================  NCMDQP  ========================================================= */
+/* ========================================================  NRSPQP  ========================================================= */
+/* ========================================================  NTDTBP0  ======================================================== */
+/* ========================================================  NIBIQP  ========================================================= */
+/* =========================================================  NRSQP  ========================================================= */
+/* ========================================================  NQTHCTL  ======================================================== */
+ #define R_I3C0_NQTHCTL_CMDQTH_Pos      (0UL)          /*!< CMDQTH (Bit 0)                                        */
+ #define R_I3C0_NQTHCTL_CMDQTH_Msk      (0xffUL)       /*!< CMDQTH (Bitfield-Mask: 0xff)                          */
+ #define R_I3C0_NQTHCTL_RSPQTH_Pos      (8UL)          /*!< RSPQTH (Bit 8)                                        */
+ #define R_I3C0_NQTHCTL_RSPQTH_Msk      (0xff00UL)     /*!< RSPQTH (Bitfield-Mask: 0xff)                          */
+ #define R_I3C0_NQTHCTL_IBIDSSZ_Pos     (16UL)         /*!< IBIDSSZ (Bit 16)                                      */
+ #define R_I3C0_NQTHCTL_IBIDSSZ_Msk     (0xff0000UL)   /*!< IBIDSSZ (Bitfield-Mask: 0xff)                         */
+ #define R_I3C0_NQTHCTL_IBIQTH_Pos      (24UL)         /*!< IBIQTH (Bit 24)                                       */
+ #define R_I3C0_NQTHCTL_IBIQTH_Msk      (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff)                          */
+/* =======================================================  NTBTHCTL0  ======================================================= */
+ #define R_I3C0_NTBTHCTL0_TXDBTH_Pos    (0UL)          /*!< TXDBTH (Bit 0)                                        */
+ #define R_I3C0_NTBTHCTL0_TXDBTH_Msk    (0x7UL)        /*!< TXDBTH (Bitfield-Mask: 0x07)                          */
+ #define R_I3C0_NTBTHCTL0_RXDBTH_Pos    (8UL)          /*!< RXDBTH (Bit 8)                                        */
+ #define R_I3C0_NTBTHCTL0_RXDBTH_Msk    (0x700UL)      /*!< RXDBTH (Bitfield-Mask: 0x07)                          */
+ #define R_I3C0_NTBTHCTL0_TXSTTH_Pos    (16UL)         /*!< TXSTTH (Bit 16)                                       */
+ #define R_I3C0_NTBTHCTL0_TXSTTH_Msk    (0x70000UL)    /*!< TXSTTH (Bitfield-Mask: 0x07)                          */
+ #define R_I3C0_NTBTHCTL0_RXSTTH_Pos    (24UL)         /*!< RXSTTH (Bit 24)                                       */
+ #define R_I3C0_NTBTHCTL0_RXSTTH_Msk    (0x7000000UL)  /*!< RXSTTH (Bitfield-Mask: 0x07)                          */
+/* =======================================================  NRQTHCTL  ======================================================== */
+ #define R_I3C0_NRQTHCTL_RSQTH_Pos      (0UL)          /*!< RSQTH (Bit 0)                                         */
+ #define R_I3C0_NRQTHCTL_RSQTH_Msk      (0xffUL)       /*!< RSQTH (Bitfield-Mask: 0xff)                           */
+/* ==========================================================  BST  ========================================================== */
+ #define R_I3C0_BST_STCNDDF_Pos         (0UL)          /*!< STCNDDF (Bit 0)                                       */
+ #define R_I3C0_BST_STCNDDF_Msk         (0x1UL)        /*!< STCNDDF (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_BST_SPCNDDF_Pos         (1UL)          /*!< SPCNDDF (Bit 1)                                       */
+ #define R_I3C0_BST_SPCNDDF_Msk         (0x2UL)        /*!< SPCNDDF (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_BST_HDREXDF_Pos         (2UL)          /*!< HDREXDF (Bit 2)                                       */
+ #define R_I3C0_BST_HDREXDF_Msk         (0x4UL)        /*!< HDREXDF (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_BST_NACKDF_Pos          (4UL)          /*!< NACKDF (Bit 4)                                        */
+ #define R_I3C0_BST_NACKDF_Msk          (0x10UL)       /*!< NACKDF (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_BST_TENDF_Pos           (8UL)          /*!< TENDF (Bit 8)                                         */
+ #define R_I3C0_BST_TENDF_Msk           (0x100UL)      /*!< TENDF (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_BST_ALF_Pos             (16UL)         /*!< ALF (Bit 16)                                          */
+ #define R_I3C0_BST_ALF_Msk             (0x10000UL)    /*!< ALF (Bitfield-Mask: 0x01)                             */
+ #define R_I3C0_BST_TODF_Pos            (20UL)         /*!< TODF (Bit 20)                                         */
+ #define R_I3C0_BST_TODF_Msk            (0x100000UL)   /*!< TODF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  BSTE  ========================================================== */
+ #define R_I3C0_BSTE_STCNDDE_Pos        (0UL)          /*!< STCNDDE (Bit 0)                                       */
+ #define R_I3C0_BSTE_STCNDDE_Msk        (0x1UL)        /*!< STCNDDE (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_BSTE_SPCNDDE_Pos        (1UL)          /*!< SPCNDDE (Bit 1)                                       */
+ #define R_I3C0_BSTE_SPCNDDE_Msk        (0x2UL)        /*!< SPCNDDE (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_BSTE_HDREXDE_Pos        (2UL)          /*!< HDREXDE (Bit 2)                                       */
+ #define R_I3C0_BSTE_HDREXDE_Msk        (0x4UL)        /*!< HDREXDE (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_BSTE_NACKDE_Pos         (4UL)          /*!< NACKDE (Bit 4)                                        */
+ #define R_I3C0_BSTE_NACKDE_Msk         (0x10UL)       /*!< NACKDE (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_BSTE_TENDE_Pos          (8UL)          /*!< TENDE (Bit 8)                                         */
+ #define R_I3C0_BSTE_TENDE_Msk          (0x100UL)      /*!< TENDE (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_BSTE_ALE_Pos            (16UL)         /*!< ALE (Bit 16)                                          */
+ #define R_I3C0_BSTE_ALE_Msk            (0x10000UL)    /*!< ALE (Bitfield-Mask: 0x01)                             */
+ #define R_I3C0_BSTE_TODE_Pos           (20UL)         /*!< TODE (Bit 20)                                         */
+ #define R_I3C0_BSTE_TODE_Msk           (0x100000UL)   /*!< TODE (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  BIE  ========================================================== */
+ #define R_I3C0_BIE_STCNDDIE_Pos        (0UL)          /*!< STCNDDIE (Bit 0)                                      */
+ #define R_I3C0_BIE_STCNDDIE_Msk        (0x1UL)        /*!< STCNDDIE (Bitfield-Mask: 0x01)                        */
+ #define R_I3C0_BIE_SPCNDDIE_Pos        (1UL)          /*!< SPCNDDIE (Bit 1)                                      */
+ #define R_I3C0_BIE_SPCNDDIE_Msk        (0x2UL)        /*!< SPCNDDIE (Bitfield-Mask: 0x01)                        */
+ #define R_I3C0_BIE_HDREXDIE_Pos        (2UL)          /*!< HDREXDIE (Bit 2)                                      */
+ #define R_I3C0_BIE_HDREXDIE_Msk        (0x4UL)        /*!< HDREXDIE (Bitfield-Mask: 0x01)                        */
+ #define R_I3C0_BIE_NACKDIE_Pos         (4UL)          /*!< NACKDIE (Bit 4)                                       */
+ #define R_I3C0_BIE_NACKDIE_Msk         (0x10UL)       /*!< NACKDIE (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_BIE_TENDIE_Pos          (8UL)          /*!< TENDIE (Bit 8)                                        */
+ #define R_I3C0_BIE_TENDIE_Msk          (0x100UL)      /*!< TENDIE (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_BIE_ALIE_Pos            (16UL)         /*!< ALIE (Bit 16)                                         */
+ #define R_I3C0_BIE_ALIE_Msk            (0x10000UL)    /*!< ALIE (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_BIE_TODIE_Pos           (20UL)         /*!< TODIE (Bit 20)                                        */
+ #define R_I3C0_BIE_TODIE_Msk           (0x100000UL)   /*!< TODIE (Bitfield-Mask: 0x01)                           */
+/* =========================================================  BSTFC  ========================================================= */
+ #define R_I3C0_BSTFC_STCNDDFC_Pos      (0UL)          /*!< STCNDDFC (Bit 0)                                      */
+ #define R_I3C0_BSTFC_STCNDDFC_Msk      (0x1UL)        /*!< STCNDDFC (Bitfield-Mask: 0x01)                        */
+ #define R_I3C0_BSTFC_SPCNDDFC_Pos      (1UL)          /*!< SPCNDDFC (Bit 1)                                      */
+ #define R_I3C0_BSTFC_SPCNDDFC_Msk      (0x2UL)        /*!< SPCNDDFC (Bitfield-Mask: 0x01)                        */
+ #define R_I3C0_BSTFC_HDREXDFC_Pos      (2UL)          /*!< HDREXDFC (Bit 2)                                      */
+ #define R_I3C0_BSTFC_HDREXDFC_Msk      (0x4UL)        /*!< HDREXDFC (Bitfield-Mask: 0x01)                        */
+ #define R_I3C0_BSTFC_NACKDFC_Pos       (4UL)          /*!< NACKDFC (Bit 4)                                       */
+ #define R_I3C0_BSTFC_NACKDFC_Msk       (0x10UL)       /*!< NACKDFC (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_BSTFC_TENDFC_Pos        (8UL)          /*!< TENDFC (Bit 8)                                        */
+ #define R_I3C0_BSTFC_TENDFC_Msk        (0x100UL)      /*!< TENDFC (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_BSTFC_ALFC_Pos          (16UL)         /*!< ALFC (Bit 16)                                         */
+ #define R_I3C0_BSTFC_ALFC_Msk          (0x10000UL)    /*!< ALFC (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_BSTFC_TODFC_Pos         (20UL)         /*!< TODFC (Bit 20)                                        */
+ #define R_I3C0_BSTFC_TODFC_Msk         (0x100000UL)   /*!< TODFC (Bitfield-Mask: 0x01)                           */
+/* =========================================================  NTST  ========================================================== */
+ #define R_I3C0_NTST_TDBEF0_Pos         (0UL)          /*!< TDBEF0 (Bit 0)                                        */
+ #define R_I3C0_NTST_TDBEF0_Msk         (0x1UL)        /*!< TDBEF0 (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_NTST_RDBFF0_Pos         (1UL)          /*!< RDBFF0 (Bit 1)                                        */
+ #define R_I3C0_NTST_RDBFF0_Msk         (0x2UL)        /*!< RDBFF0 (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_NTST_IBIQEFF_Pos        (2UL)          /*!< IBIQEFF (Bit 2)                                       */
+ #define R_I3C0_NTST_IBIQEFF_Msk        (0x4UL)        /*!< IBIQEFF (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_NTST_CMDQEF_Pos         (3UL)          /*!< CMDQEF (Bit 3)                                        */
+ #define R_I3C0_NTST_CMDQEF_Msk         (0x8UL)        /*!< CMDQEF (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_NTST_RSPQFF_Pos         (4UL)          /*!< RSPQFF (Bit 4)                                        */
+ #define R_I3C0_NTST_RSPQFF_Msk         (0x10UL)       /*!< RSPQFF (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_NTST_TABTF_Pos          (5UL)          /*!< TABTF (Bit 5)                                         */
+ #define R_I3C0_NTST_TABTF_Msk          (0x20UL)       /*!< TABTF (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_NTST_TEF_Pos            (9UL)          /*!< TEF (Bit 9)                                           */
+ #define R_I3C0_NTST_TEF_Msk            (0x200UL)      /*!< TEF (Bitfield-Mask: 0x01)                             */
+ #define R_I3C0_NTST_RSQFF_Pos          (20UL)         /*!< RSQFF (Bit 20)                                        */
+ #define R_I3C0_NTST_RSQFF_Msk          (0x100000UL)   /*!< RSQFF (Bitfield-Mask: 0x01)                           */
+/* =========================================================  NTSTE  ========================================================= */
+ #define R_I3C0_NTSTE_TDBEE0_Pos        (0UL)          /*!< TDBEE0 (Bit 0)                                        */
+ #define R_I3C0_NTSTE_TDBEE0_Msk        (0x1UL)        /*!< TDBEE0 (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_NTSTE_RDBFE0_Pos        (1UL)          /*!< RDBFE0 (Bit 1)                                        */
+ #define R_I3C0_NTSTE_RDBFE0_Msk        (0x2UL)        /*!< RDBFE0 (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_NTSTE_IBIQEFE_Pos       (2UL)          /*!< IBIQEFE (Bit 2)                                       */
+ #define R_I3C0_NTSTE_IBIQEFE_Msk       (0x4UL)        /*!< IBIQEFE (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_NTSTE_CMDQEE_Pos        (3UL)          /*!< CMDQEE (Bit 3)                                        */
+ #define R_I3C0_NTSTE_CMDQEE_Msk        (0x8UL)        /*!< CMDQEE (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_NTSTE_RSPQFE_Pos        (4UL)          /*!< RSPQFE (Bit 4)                                        */
+ #define R_I3C0_NTSTE_RSPQFE_Msk        (0x10UL)       /*!< RSPQFE (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_NTSTE_TABTE_Pos         (5UL)          /*!< TABTE (Bit 5)                                         */
+ #define R_I3C0_NTSTE_TABTE_Msk         (0x20UL)       /*!< TABTE (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_NTSTE_TEE_Pos           (9UL)          /*!< TEE (Bit 9)                                           */
+ #define R_I3C0_NTSTE_TEE_Msk           (0x200UL)      /*!< TEE (Bitfield-Mask: 0x01)                             */
+ #define R_I3C0_NTSTE_RSQFE_Pos         (20UL)         /*!< RSQFE (Bit 20)                                        */
+ #define R_I3C0_NTSTE_RSQFE_Msk         (0x100000UL)   /*!< RSQFE (Bitfield-Mask: 0x01)                           */
+/* =========================================================  NTIE  ========================================================== */
+ #define R_I3C0_NTIE_TDBEIE0_Pos        (0UL)          /*!< TDBEIE0 (Bit 0)                                       */
+ #define R_I3C0_NTIE_TDBEIE0_Msk        (0x1UL)        /*!< TDBEIE0 (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_NTIE_RDBFIE0_Pos        (1UL)          /*!< RDBFIE0 (Bit 1)                                       */
+ #define R_I3C0_NTIE_RDBFIE0_Msk        (0x2UL)        /*!< RDBFIE0 (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_NTIE_IBIQEFIE_Pos       (2UL)          /*!< IBIQEFIE (Bit 2)                                      */
+ #define R_I3C0_NTIE_IBIQEFIE_Msk       (0x4UL)        /*!< IBIQEFIE (Bitfield-Mask: 0x01)                        */
+ #define R_I3C0_NTIE_CMDQEIE_Pos        (3UL)          /*!< CMDQEIE (Bit 3)                                       */
+ #define R_I3C0_NTIE_CMDQEIE_Msk        (0x8UL)        /*!< CMDQEIE (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_NTIE_RSPQFIE_Pos        (4UL)          /*!< RSPQFIE (Bit 4)                                       */
+ #define R_I3C0_NTIE_RSPQFIE_Msk        (0x10UL)       /*!< RSPQFIE (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_NTIE_TABTIE_Pos         (5UL)          /*!< TABTIE (Bit 5)                                        */
+ #define R_I3C0_NTIE_TABTIE_Msk         (0x20UL)       /*!< TABTIE (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_NTIE_TEIE_Pos           (9UL)          /*!< TEIE (Bit 9)                                          */
+ #define R_I3C0_NTIE_TEIE_Msk           (0x200UL)      /*!< TEIE (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_NTIE_RSQFIE_Pos         (20UL)         /*!< RSQFIE (Bit 20)                                       */
+ #define R_I3C0_NTIE_RSQFIE_Msk         (0x100000UL)   /*!< RSQFIE (Bitfield-Mask: 0x01)                          */
+/* ========================================================  NTSTFC  ========================================================= */
+ #define R_I3C0_NTSTFC_TDBEFC0_Pos      (0UL)          /*!< TDBEFC0 (Bit 0)                                       */
+ #define R_I3C0_NTSTFC_TDBEFC0_Msk      (0x1UL)        /*!< TDBEFC0 (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_NTSTFC_RDBFFC0_Pos      (1UL)          /*!< RDBFFC0 (Bit 1)                                       */
+ #define R_I3C0_NTSTFC_RDBFFC0_Msk      (0x2UL)        /*!< RDBFFC0 (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_NTSTFC_IBIQEFFC_Pos     (2UL)          /*!< IBIQEFFC (Bit 2)                                      */
+ #define R_I3C0_NTSTFC_IBIQEFFC_Msk     (0x4UL)        /*!< IBIQEFFC (Bitfield-Mask: 0x01)                        */
+ #define R_I3C0_NTSTFC_CMDQEFC_Pos      (3UL)          /*!< CMDQEFC (Bit 3)                                       */
+ #define R_I3C0_NTSTFC_CMDQEFC_Msk      (0x8UL)        /*!< CMDQEFC (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_NTSTFC_RSPQFFC_Pos      (4UL)          /*!< RSPQFFC (Bit 4)                                       */
+ #define R_I3C0_NTSTFC_RSPQFFC_Msk      (0x10UL)       /*!< RSPQFFC (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_NTSTFC_TABTFC_Pos       (5UL)          /*!< TABTFC (Bit 5)                                        */
+ #define R_I3C0_NTSTFC_TABTFC_Msk       (0x20UL)       /*!< TABTFC (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_NTSTFC_TEFC_Pos         (9UL)          /*!< TEFC (Bit 9)                                          */
+ #define R_I3C0_NTSTFC_TEFC_Msk         (0x200UL)      /*!< TEFC (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_NTSTFC_RSQFFC_Pos       (20UL)         /*!< RSQFFC (Bit 20)                                       */
+ #define R_I3C0_NTSTFC_RSQFFC_Msk       (0x100000UL)   /*!< RSQFFC (Bitfield-Mask: 0x01)                          */
+/* =========================================================  BCST  ========================================================== */
+ #define R_I3C0_BCST_BFREF_Pos          (0UL)          /*!< BFREF (Bit 0)                                         */
+ #define R_I3C0_BCST_BFREF_Msk          (0x1UL)        /*!< BFREF (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_BCST_BAVLF_Pos          (1UL)          /*!< BAVLF (Bit 1)                                         */
+ #define R_I3C0_BCST_BAVLF_Msk          (0x2UL)        /*!< BAVLF (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_BCST_BIDLF_Pos          (2UL)          /*!< BIDLF (Bit 2)                                         */
+ #define R_I3C0_BCST_BIDLF_Msk          (0x4UL)        /*!< BIDLF (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SVST  ========================================================== */
+ #define R_I3C0_SVST_GCAF_Pos           (0UL)          /*!< GCAF (Bit 0)                                          */
+ #define R_I3C0_SVST_GCAF_Msk           (0x1UL)        /*!< GCAF (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_SVST_HSMCF_Pos          (5UL)          /*!< HSMCF (Bit 5)                                         */
+ #define R_I3C0_SVST_HSMCF_Msk          (0x20UL)       /*!< HSMCF (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SVST_DVIDF_Pos          (6UL)          /*!< DVIDF (Bit 6)                                         */
+ #define R_I3C0_SVST_DVIDF_Msk          (0x40UL)       /*!< DVIDF (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SVST_HOAF_Pos           (15UL)         /*!< HOAF (Bit 15)                                         */
+ #define R_I3C0_SVST_HOAF_Msk           (0x8000UL)     /*!< HOAF (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_SVST_SVAFn_Pos          (16UL)         /*!< SVAFn (Bit 16)                                        */
+ #define R_I3C0_SVST_SVAFn_Msk          (0x10000UL)    /*!< SVAFn (Bitfield-Mask: 0x01)                           */
+/* =========================================================  WUST  ========================================================== */
+ #define R_I3C0_WUST_WUASYNF_Pos        (0UL)          /*!< WUASYNF (Bit 0)                                       */
+ #define R_I3C0_WUST_WUASYNF_Msk        (0x1UL)        /*!< WUASYNF (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DATBAS0  ======================================================== */
+ #define R_I3C0_DATBAS0_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
+ #define R_I3C0_DATBAS0_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
+ #define R_I3C0_DATBAS0_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
+ #define R_I3C0_DATBAS0_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS0_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
+ #define R_I3C0_DATBAS0_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS0_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
+ #define R_I3C0_DATBAS0_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_DATBAS0_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
+ #define R_I3C0_DATBAS0_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS0_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
+ #define R_I3C0_DATBAS0_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
+ #define R_I3C0_DATBAS0_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
+ #define R_I3C0_DATBAS0_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
+ #define R_I3C0_DATBAS0_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
+ #define R_I3C0_DATBAS0_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DATBAS1  ======================================================== */
+ #define R_I3C0_DATBAS1_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
+ #define R_I3C0_DATBAS1_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
+ #define R_I3C0_DATBAS1_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
+ #define R_I3C0_DATBAS1_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS1_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
+ #define R_I3C0_DATBAS1_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS1_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
+ #define R_I3C0_DATBAS1_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_DATBAS1_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
+ #define R_I3C0_DATBAS1_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS1_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
+ #define R_I3C0_DATBAS1_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
+ #define R_I3C0_DATBAS1_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
+ #define R_I3C0_DATBAS1_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
+ #define R_I3C0_DATBAS1_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
+ #define R_I3C0_DATBAS1_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DATBAS2  ======================================================== */
+ #define R_I3C0_DATBAS2_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
+ #define R_I3C0_DATBAS2_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
+ #define R_I3C0_DATBAS2_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
+ #define R_I3C0_DATBAS2_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS2_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
+ #define R_I3C0_DATBAS2_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS2_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
+ #define R_I3C0_DATBAS2_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_DATBAS2_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
+ #define R_I3C0_DATBAS2_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS2_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
+ #define R_I3C0_DATBAS2_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
+ #define R_I3C0_DATBAS2_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
+ #define R_I3C0_DATBAS2_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
+ #define R_I3C0_DATBAS2_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
+ #define R_I3C0_DATBAS2_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DATBAS3  ======================================================== */
+ #define R_I3C0_DATBAS3_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
+ #define R_I3C0_DATBAS3_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
+ #define R_I3C0_DATBAS3_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
+ #define R_I3C0_DATBAS3_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS3_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
+ #define R_I3C0_DATBAS3_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS3_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
+ #define R_I3C0_DATBAS3_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_DATBAS3_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
+ #define R_I3C0_DATBAS3_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS3_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
+ #define R_I3C0_DATBAS3_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
+ #define R_I3C0_DATBAS3_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
+ #define R_I3C0_DATBAS3_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
+ #define R_I3C0_DATBAS3_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
+ #define R_I3C0_DATBAS3_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
+/* =======================================================  EXDATBAS  ======================================================== */
+ #define R_I3C0_EXDATBAS_EDSTAD_Pos     (0UL)          /*!< EDSTAD (Bit 0)                                        */
+ #define R_I3C0_EXDATBAS_EDSTAD_Msk     (0x7fUL)       /*!< EDSTAD (Bitfield-Mask: 0x7f)                          */
+ #define R_I3C0_EXDATBAS_EDDYAD_Pos     (16UL)         /*!< EDDYAD (Bit 16)                                       */
+ #define R_I3C0_EXDATBAS_EDDYAD_Msk     (0xff0000UL)   /*!< EDDYAD (Bitfield-Mask: 0xff)                          */
+ #define R_I3C0_EXDATBAS_EDNACK_Pos     (29UL)         /*!< EDNACK (Bit 29)                                       */
+ #define R_I3C0_EXDATBAS_EDNACK_Msk     (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03)                          */
+ #define R_I3C0_EXDATBAS_EDTYP_Pos      (31UL)         /*!< EDTYP (Bit 31)                                        */
+ #define R_I3C0_EXDATBAS_EDTYP_Msk      (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01)                           */
+/* =======================================================  SDATBAS0  ======================================================== */
+ #define R_I3C0_SDATBAS0_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
+ #define R_I3C0_SDATBAS0_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
+ #define R_I3C0_SDATBAS0_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
+ #define R_I3C0_SDATBAS0_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_SDATBAS0_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
+ #define R_I3C0_SDATBAS0_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_SDATBAS0_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
+ #define R_I3C0_SDATBAS0_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
+/* =======================================================  SDATBAS1  ======================================================== */
+ #define R_I3C0_SDATBAS1_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
+ #define R_I3C0_SDATBAS1_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
+ #define R_I3C0_SDATBAS1_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
+ #define R_I3C0_SDATBAS1_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_SDATBAS1_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
+ #define R_I3C0_SDATBAS1_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_SDATBAS1_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
+ #define R_I3C0_SDATBAS1_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
+/* =======================================================  SDATBAS2  ======================================================== */
+ #define R_I3C0_SDATBAS2_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
+ #define R_I3C0_SDATBAS2_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
+ #define R_I3C0_SDATBAS2_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
+ #define R_I3C0_SDATBAS2_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_SDATBAS2_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
+ #define R_I3C0_SDATBAS2_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_SDATBAS2_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
+ #define R_I3C0_SDATBAS2_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
+/* ========================================================  MSDCT0  ========================================================= */
+ #define R_I3C0_MSDCT0_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
+ #define R_I3C0_MSDCT0_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT0_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
+ #define R_I3C0_MSDCT0_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT0_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
+ #define R_I3C0_MSDCT0_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT0_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
+ #define R_I3C0_MSDCT0_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT0_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
+ #define R_I3C0_MSDCT0_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
+/* ========================================================  MSDCT1  ========================================================= */
+ #define R_I3C0_MSDCT1_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
+ #define R_I3C0_MSDCT1_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT1_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
+ #define R_I3C0_MSDCT1_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT1_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
+ #define R_I3C0_MSDCT1_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT1_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
+ #define R_I3C0_MSDCT1_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT1_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
+ #define R_I3C0_MSDCT1_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
+/* ========================================================  MSDCT2  ========================================================= */
+ #define R_I3C0_MSDCT2_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
+ #define R_I3C0_MSDCT2_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT2_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
+ #define R_I3C0_MSDCT2_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT2_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
+ #define R_I3C0_MSDCT2_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT2_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
+ #define R_I3C0_MSDCT2_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT2_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
+ #define R_I3C0_MSDCT2_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
+/* ========================================================  MSDCT3  ========================================================= */
+ #define R_I3C0_MSDCT3_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
+ #define R_I3C0_MSDCT3_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT3_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
+ #define R_I3C0_MSDCT3_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT3_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
+ #define R_I3C0_MSDCT3_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT3_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
+ #define R_I3C0_MSDCT3_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT3_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
+ #define R_I3C0_MSDCT3_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
+/* =========================================================  SVDCT  ========================================================= */
+ #define R_I3C0_SVDCT_TDCR_Pos          (0UL)          /*!< TDCR (Bit 0)                                          */
+ #define R_I3C0_SVDCT_TDCR_Msk          (0xffUL)       /*!< TDCR (Bitfield-Mask: 0xff)                            */
+ #define R_I3C0_SVDCT_TBCR0_Pos         (8UL)          /*!< TBCR0 (Bit 8)                                         */
+ #define R_I3C0_SVDCT_TBCR0_Msk         (0x100UL)      /*!< TBCR0 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SVDCT_TBCR1_Pos         (9UL)          /*!< TBCR1 (Bit 9)                                         */
+ #define R_I3C0_SVDCT_TBCR1_Msk         (0x200UL)      /*!< TBCR1 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SVDCT_TBCR2_Pos         (10UL)         /*!< TBCR2 (Bit 10)                                        */
+ #define R_I3C0_SVDCT_TBCR2_Msk         (0x400UL)      /*!< TBCR2 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SVDCT_TBCR3_Pos         (11UL)         /*!< TBCR3 (Bit 11)                                        */
+ #define R_I3C0_SVDCT_TBCR3_Msk         (0x800UL)      /*!< TBCR3 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SVDCT_TBCR76_Pos        (14UL)         /*!< TBCR76 (Bit 14)                                       */
+ #define R_I3C0_SVDCT_TBCR76_Msk        (0xc000UL)     /*!< TBCR76 (Bitfield-Mask: 0x03)                          */
+/* =======================================================  SDCTPIDL  ======================================================== */
+/* =======================================================  SDCTPIDH  ======================================================== */
+/* ========================================================  SVDVAD0  ======================================================== */
+ #define R_I3C0_SVDVAD0_SVAD_Pos        (16UL)         /*!< SVAD (Bit 16)                                         */
+ #define R_I3C0_SVDVAD0_SVAD_Msk        (0x3ff0000UL)  /*!< SVAD (Bitfield-Mask: 0x3ff)                           */
+ #define R_I3C0_SVDVAD0_SADLG_Pos       (27UL)         /*!< SADLG (Bit 27)                                        */
+ #define R_I3C0_SVDVAD0_SADLG_Msk       (0x8000000UL)  /*!< SADLG (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SVDVAD0_SSTADV_Pos      (30UL)         /*!< SSTADV (Bit 30)                                       */
+ #define R_I3C0_SVDVAD0_SSTADV_Msk      (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_SVDVAD0_SDYADV_Pos      (31UL)         /*!< SDYADV (Bit 31)                                       */
+ #define R_I3C0_SVDVAD0_SDYADV_Msk      (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01)                          */
+/* ========================================================  CSECMD  ========================================================= */
+ #define R_I3C0_CSECMD_SVIRQE_Pos       (0UL)          /*!< SVIRQE (Bit 0)                                        */
+ #define R_I3C0_CSECMD_SVIRQE_Msk       (0x1UL)        /*!< SVIRQE (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_CSECMD_MSRQE_Pos        (1UL)          /*!< MSRQE (Bit 1)                                         */
+ #define R_I3C0_CSECMD_MSRQE_Msk        (0x2UL)        /*!< MSRQE (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_CSECMD_HJEVE_Pos        (3UL)          /*!< HJEVE (Bit 3)                                         */
+ #define R_I3C0_CSECMD_HJEVE_Msk        (0x8UL)        /*!< HJEVE (Bitfield-Mask: 0x01)                           */
+/* ========================================================  CEACTST  ======================================================== */
+ #define R_I3C0_CEACTST_ACTST_Pos       (0UL)          /*!< ACTST (Bit 0)                                         */
+ #define R_I3C0_CEACTST_ACTST_Msk       (0xfUL)        /*!< ACTST (Bitfield-Mask: 0x0f)                           */
+/* =========================================================  CMWLG  ========================================================= */
+ #define R_I3C0_CMWLG_MWLG_Pos          (0UL)          /*!< MWLG (Bit 0)                                          */
+ #define R_I3C0_CMWLG_MWLG_Msk          (0xffffUL)     /*!< MWLG (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  CMRLG  ========================================================= */
+ #define R_I3C0_CMRLG_MRLG_Pos          (0UL)          /*!< MRLG (Bit 0)                                          */
+ #define R_I3C0_CMRLG_MRLG_Msk          (0xffffUL)     /*!< MRLG (Bitfield-Mask: 0xffff)                          */
+ #define R_I3C0_CMRLG_IBIPSZ_Pos        (16UL)         /*!< IBIPSZ (Bit 16)                                       */
+ #define R_I3C0_CMRLG_IBIPSZ_Msk        (0xff0000UL)   /*!< IBIPSZ (Bitfield-Mask: 0xff)                          */
+/* ========================================================  CETSTMD  ======================================================== */
+ #define R_I3C0_CETSTMD_TSTMD_Pos       (0UL)          /*!< TSTMD (Bit 0)                                         */
+ #define R_I3C0_CETSTMD_TSTMD_Msk       (0xffUL)       /*!< TSTMD (Bitfield-Mask: 0xff)                           */
+/* ========================================================  CGDVST  ========================================================= */
+ #define R_I3C0_CGDVST_PNDINT_Pos       (0UL)          /*!< PNDINT (Bit 0)                                        */
+ #define R_I3C0_CGDVST_PNDINT_Msk       (0xfUL)        /*!< PNDINT (Bitfield-Mask: 0x0f)                          */
+ #define R_I3C0_CGDVST_PRTE_Pos         (5UL)          /*!< PRTE (Bit 5)                                          */
+ #define R_I3C0_CGDVST_PRTE_Msk         (0x20UL)       /*!< PRTE (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_CGDVST_ACTMD_Pos        (6UL)          /*!< ACTMD (Bit 6)                                         */
+ #define R_I3C0_CGDVST_ACTMD_Msk        (0xc0UL)       /*!< ACTMD (Bitfield-Mask: 0x03)                           */
+ #define R_I3C0_CGDVST_VDRSV_Pos        (8UL)          /*!< VDRSV (Bit 8)                                         */
+ #define R_I3C0_CGDVST_VDRSV_Msk        (0xff00UL)     /*!< VDRSV (Bitfield-Mask: 0xff)                           */
+/* ========================================================  CMDSPW  ========================================================= */
+ #define R_I3C0_CMDSPW_MSWDR_Pos        (0UL)          /*!< MSWDR (Bit 0)                                         */
+ #define R_I3C0_CMDSPW_MSWDR_Msk        (0x7UL)        /*!< MSWDR (Bitfield-Mask: 0x07)                           */
+/* ========================================================  CMDSPR  ========================================================= */
+ #define R_I3C0_CMDSPR_MSRDR_Pos        (0UL)          /*!< MSRDR (Bit 0)                                         */
+ #define R_I3C0_CMDSPR_MSRDR_Msk        (0x7UL)        /*!< MSRDR (Bitfield-Mask: 0x07)                           */
+ #define R_I3C0_CMDSPR_CDTTIM_Pos       (3UL)          /*!< CDTTIM (Bit 3)                                        */
+ #define R_I3C0_CMDSPR_CDTTIM_Msk       (0x38UL)       /*!< CDTTIM (Bitfield-Mask: 0x07)                          */
+/* ========================================================  CMDSPT  ========================================================= */
+ #define R_I3C0_CMDSPT_MRTTIM_Pos       (0UL)          /*!< MRTTIM (Bit 0)                                        */
+ #define R_I3C0_CMDSPT_MRTTIM_Msk       (0xffffffUL)   /*!< MRTTIM (Bitfield-Mask: 0xffffff)                      */
+ #define R_I3C0_CMDSPT_MRTE_Pos         (31UL)         /*!< MRTE (Bit 31)                                         */
+ #define R_I3C0_CMDSPT_MRTE_Msk         (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  CETSM  ========================================================= */
+ #define R_I3C0_CETSM_FREQ_Pos          (8UL)          /*!< FREQ (Bit 8)                                          */
+ #define R_I3C0_CETSM_FREQ_Msk          (0xff00UL)     /*!< FREQ (Bitfield-Mask: 0xff)                            */
+ #define R_I3C0_CETSM_INAC_Pos          (16UL)         /*!< INAC (Bit 16)                                         */
+ #define R_I3C0_CETSM_INAC_Msk          (0xff0000UL)   /*!< INAC (Bitfield-Mask: 0xff)                            */
+/* ========================================================  BITCNT  ========================================================= */
+ #define R_I3C0_BITCNT_BCNT_Pos         (0UL)          /*!< BCNT (Bit 0)                                          */
+ #define R_I3C0_BITCNT_BCNT_Msk         (0x1fUL)       /*!< BCNT (Bitfield-Mask: 0x1f)                            */
+ #define R_I3C0_BITCNT_BCNTWP_Pos       (7UL)          /*!< BCNTWP (Bit 7)                                        */
+ #define R_I3C0_BITCNT_BCNTWP_Msk       (0x80UL)       /*!< BCNTWP (Bitfield-Mask: 0x01)                          */
+/* ========================================================  NQSTLV  ========================================================= */
+ #define R_I3C0_NQSTLV_CMDQFLV_Pos      (0UL)          /*!< CMDQFLV (Bit 0)                                       */
+ #define R_I3C0_NQSTLV_CMDQFLV_Msk      (0xffUL)       /*!< CMDQFLV (Bitfield-Mask: 0xff)                         */
+ #define R_I3C0_NQSTLV_RSPQLV_Pos       (8UL)          /*!< RSPQLV (Bit 8)                                        */
+ #define R_I3C0_NQSTLV_RSPQLV_Msk       (0xff00UL)     /*!< RSPQLV (Bitfield-Mask: 0xff)                          */
+ #define R_I3C0_NQSTLV_IBIQLV_Pos       (16UL)         /*!< IBIQLV (Bit 16)                                       */
+ #define R_I3C0_NQSTLV_IBIQLV_Msk       (0xff0000UL)   /*!< IBIQLV (Bitfield-Mask: 0xff)                          */
+ #define R_I3C0_NQSTLV_IBISCNT_Pos      (24UL)         /*!< IBISCNT (Bit 24)                                      */
+ #define R_I3C0_NQSTLV_IBISCNT_Msk      (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f)                         */
+/* =======================================================  NDBSTLV0  ======================================================== */
+ #define R_I3C0_NDBSTLV0_TDBFLV_Pos     (0UL)          /*!< TDBFLV (Bit 0)                                        */
+ #define R_I3C0_NDBSTLV0_TDBFLV_Msk     (0xffUL)       /*!< TDBFLV (Bitfield-Mask: 0xff)                          */
+ #define R_I3C0_NDBSTLV0_RDBLV_Pos      (8UL)          /*!< RDBLV (Bit 8)                                         */
+ #define R_I3C0_NDBSTLV0_RDBLV_Msk      (0xff00UL)     /*!< RDBLV (Bitfield-Mask: 0xff)                           */
+/* =======================================================  NRSQSTLV  ======================================================== */
+ #define R_I3C0_NRSQSTLV_RSQLV_Pos      (0UL)          /*!< RSQLV (Bit 0)                                         */
+ #define R_I3C0_NRSQSTLV_RSQLV_Msk      (0xffUL)       /*!< RSQLV (Bitfield-Mask: 0xff)                           */
+/* ========================================================  PRSTDBG  ======================================================== */
+ #define R_I3C0_PRSTDBG_SCILV_Pos       (0UL)          /*!< SCILV (Bit 0)                                         */
+ #define R_I3C0_PRSTDBG_SCILV_Msk       (0x1UL)        /*!< SCILV (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_PRSTDBG_SDILV_Pos       (1UL)          /*!< SDILV (Bit 1)                                         */
+ #define R_I3C0_PRSTDBG_SDILV_Msk       (0x2UL)        /*!< SDILV (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_PRSTDBG_SCOLV_Pos       (2UL)          /*!< SCOLV (Bit 2)                                         */
+ #define R_I3C0_PRSTDBG_SCOLV_Msk       (0x4UL)        /*!< SCOLV (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_PRSTDBG_SDOLV_Pos       (3UL)          /*!< SDOLV (Bit 3)                                         */
+ #define R_I3C0_PRSTDBG_SDOLV_Msk       (0x8UL)        /*!< SDOLV (Bitfield-Mask: 0x01)                           */
+/* =======================================================  MSERRCNT  ======================================================== */
+ #define R_I3C0_MSERRCNT_M2ECNT_Pos     (0UL)          /*!< M2ECNT (Bit 0)                                        */
+ #define R_I3C0_MSERRCNT_M2ECNT_Msk     (0xffUL)       /*!< M2ECNT (Bitfield-Mask: 0xff)                          */
+
+/* =========================================================================================================================== */
+/* ================                                        R_MPU_SPMON                                        ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MSTP                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  MSTPCRA  ======================================================== */
+ #define R_MSTP_MSTPCRA_MSTPA22_Pos    (22UL)         /*!< MSTPA22 (Bit 22)                                      */
+ #define R_MSTP_MSTPCRA_MSTPA22_Msk    (0x400000UL)   /*!< MSTPA22 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRA_MSTPA7_Pos     (7UL)          /*!< MSTPA7 (Bit 7)                                        */
+ #define R_MSTP_MSTPCRA_MSTPA7_Msk     (0x80UL)       /*!< MSTPA7 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRA_MSTPA0_Pos     (0UL)          /*!< MSTPA0 (Bit 0)                                        */
+ #define R_MSTP_MSTPCRA_MSTPA0_Msk     (0x1UL)        /*!< MSTPA0 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  MSTPCRB  ======================================================== */
+ #define R_MSTP_MSTPCRB_MSTPB31_Pos    (31UL)         /*!< MSTPB31 (Bit 31)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB31_Msk    (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB30_Pos    (30UL)         /*!< MSTPB30 (Bit 30)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB30_Msk    (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB29_Pos    (29UL)         /*!< MSTPB29 (Bit 29)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB29_Msk    (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB28_Pos    (28UL)         /*!< MSTPB28 (Bit 28)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB28_Msk    (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB27_Pos    (27UL)         /*!< MSTPB27 (Bit 27)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB27_Msk    (0x8000000UL)  /*!< MSTPB27 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB26_Pos    (26UL)         /*!< MSTPB26 (Bit 26)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB26_Msk    (0x4000000UL)  /*!< MSTPB26 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB25_Pos    (25UL)         /*!< MSTPB25 (Bit 25)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB25_Msk    (0x2000000UL)  /*!< MSTPB25 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB24_Pos    (24UL)         /*!< MSTPB24 (Bit 24)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB24_Msk    (0x1000000UL)  /*!< MSTPB24 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB23_Pos    (23UL)         /*!< MSTPB23 (Bit 23)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB23_Msk    (0x800000UL)   /*!< MSTPB23 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB22_Pos    (22UL)         /*!< MSTPB22 (Bit 22)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB22_Msk    (0x400000UL)   /*!< MSTPB22 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB19_Pos    (19UL)         /*!< MSTPB19 (Bit 19)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB19_Msk    (0x80000UL)    /*!< MSTPB19 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB18_Pos    (18UL)         /*!< MSTPB18 (Bit 18)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB18_Msk    (0x40000UL)    /*!< MSTPB18 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB16_Pos    (16UL)         /*!< MSTPB16 (Bit 16)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB16_Msk    (0x10000UL)    /*!< MSTPB16 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB15_Pos    (15UL)         /*!< MSTPB15 (Bit 15)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB15_Msk    (0x8000UL)     /*!< MSTPB15 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB14_Pos    (14UL)         /*!< MSTPB14 (Bit 14)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB14_Msk    (0x4000UL)     /*!< MSTPB14 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB13_Pos    (13UL)         /*!< MSTPB13 (Bit 13)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB13_Msk    (0x2000UL)     /*!< MSTPB13 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB12_Pos    (12UL)         /*!< MSTPB12 (Bit 12)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB12_Msk    (0x1000UL)     /*!< MSTPB12 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB11_Pos    (11UL)         /*!< MSTPB11 (Bit 11)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB11_Msk    (0x800UL)      /*!< MSTPB11 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB9_Pos     (9UL)          /*!< MSTPB9 (Bit 9)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB9_Msk     (0x200UL)      /*!< MSTPB9 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRB_MSTPB8_Pos     (8UL)          /*!< MSTPB8 (Bit 8)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB8_Msk     (0x100UL)      /*!< MSTPB8 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRB_MSTPB7_Pos     (7UL)          /*!< MSTPB7 (Bit 7)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB7_Msk     (0x80UL)       /*!< MSTPB7 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRB_MSTPB6_Pos     (6UL)          /*!< MSTPB6 (Bit 6)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB6_Msk     (0x40UL)       /*!< MSTPB6 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRB_MSTPB5_Pos     (5UL)          /*!< MSTPB5 (Bit 5)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB5_Msk     (0x20UL)       /*!< MSTPB5 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRB_MSTPB3_Pos     (3UL)          /*!< MSTPB3 (Bit 3)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB3_Msk     (0x8UL)        /*!< MSTPB3 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRB_MSTPB2_Pos     (2UL)          /*!< MSTPB2 (Bit 2)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB2_Msk     (0x4UL)        /*!< MSTPB2 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRB_MSTPB1_Pos     (1UL)          /*!< MSTPB1 (Bit 1)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB1_Msk     (0x2UL)        /*!< MSTPB1 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  MSTPCRC  ======================================================== */
+ #define R_MSTP_MSTPCRC_MSTPC31_Pos    (31UL)         /*!< MSTPC31 (Bit 31)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC31_Msk    (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC28_Pos    (28UL)         /*!< MSTPC28 (Bit 28)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC28_Msk    (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC27_Pos    (27UL)         /*!< MSTPC27 (Bit 27)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC27_Msk    (0x8000000UL)  /*!< MSTPC27 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC21_Pos    (21UL)         /*!< MSTPC21 (Bit 21)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC21_Msk    (0x200000UL)   /*!< MSTPC21 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC20_Pos    (20UL)         /*!< MSTPC20 (Bit 20)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC20_Msk    (0x100000UL)   /*!< MSTPC20 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC15_Pos    (15UL)         /*!< MSTPC15 (Bit 15)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC15_Msk    (0x8000UL)     /*!< MSTPC15 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC14_Pos    (14UL)         /*!< MSTPC14 (Bit 14)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC14_Msk    (0x4000UL)     /*!< MSTPC14 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC13_Pos    (13UL)         /*!< MSTPC13 (Bit 13)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC13_Msk    (0x2000UL)     /*!< MSTPC13 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC12_Pos    (12UL)         /*!< MSTPC12 (Bit 12)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC12_Msk    (0x1000UL)     /*!< MSTPC12 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC11_Pos    (11UL)         /*!< MSTPC11 (Bit 11)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC11_Msk    (0x800UL)      /*!< MSTPC11 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC9_Pos     (9UL)          /*!< MSTPC9 (Bit 9)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC9_Msk     (0x200UL)      /*!< MSTPC9 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC8_Pos     (8UL)          /*!< MSTPC8 (Bit 8)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC8_Msk     (0x100UL)      /*!< MSTPC8 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC7_Pos     (7UL)          /*!< MSTPC7 (Bit 7)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC7_Msk     (0x80UL)       /*!< MSTPC7 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC6_Pos     (6UL)          /*!< MSTPC6 (Bit 6)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC6_Msk     (0x40UL)       /*!< MSTPC6 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC5_Pos     (5UL)          /*!< MSTPC5 (Bit 5)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC5_Msk     (0x20UL)       /*!< MSTPC5 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC4_Pos     (4UL)          /*!< MSTPC4 (Bit 4)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC4_Msk     (0x10UL)       /*!< MSTPC4 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC3_Pos     (3UL)          /*!< MSTPC3 (Bit 3)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC3_Msk     (0x8UL)        /*!< MSTPC3 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC2_Pos     (2UL)          /*!< MSTPC2 (Bit 2)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC2_Msk     (0x4UL)        /*!< MSTPC2 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC1_Pos     (1UL)          /*!< MSTPC1 (Bit 1)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC1_Msk     (0x2UL)        /*!< MSTPC1 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC0_Pos     (0UL)          /*!< MSTPC0 (Bit 0)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC0_Msk     (0x1UL)        /*!< MSTPC0 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  MSTPCRD  ======================================================== */
+ #define R_MSTP_MSTPCRD_MSTPD31_Pos    (31UL)         /*!< MSTPD31 (Bit 31)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD31_Msk    (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD29_Pos    (29UL)         /*!< MSTPD29 (Bit 29)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD29_Msk    (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD28_Pos    (28UL)         /*!< MSTPD28 (Bit 28)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD28_Msk    (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD27_Pos    (27UL)         /*!< MSTPD27 (Bit 27)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD27_Msk    (0x8000000UL)  /*!< MSTPD27 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD26_Pos    (26UL)         /*!< MSTPD26 (Bit 26)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD26_Msk    (0x4000000UL)  /*!< MSTPD26 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD25_Pos    (25UL)         /*!< MSTPD25 (Bit 25)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD25_Msk    (0x2000000UL)  /*!< MSTPD25 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD24_Pos    (24UL)         /*!< MSTPD24 (Bit 24)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD24_Msk    (0x1000000UL)  /*!< MSTPD24 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD23_Pos    (23UL)         /*!< MSTPD23 (Bit 23)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD23_Msk    (0x800000UL)   /*!< MSTPD23 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD22_Pos    (22UL)         /*!< MSTPD22 (Bit 22)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD22_Msk    (0x400000UL)   /*!< MSTPD22 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD20_Pos    (20UL)         /*!< MSTPD20 (Bit 20)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD20_Msk    (0x100000UL)   /*!< MSTPD20 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD19_Pos    (19UL)         /*!< MSTPD19 (Bit 19)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD19_Msk    (0x80000UL)    /*!< MSTPD19 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD18_Pos    (18UL)         /*!< MSTPD18 (Bit 18)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD18_Msk    (0x40000UL)    /*!< MSTPD18 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD17_Pos    (17UL)         /*!< MSTPD17 (Bit 17)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD17_Msk    (0x20000UL)    /*!< MSTPD17 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD16_Pos    (16UL)         /*!< MSTPD16 (Bit 16)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD16_Msk    (0x10000UL)    /*!< MSTPD16 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD15_Pos    (15UL)         /*!< MSTPD15 (Bit 15)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD15_Msk    (0x8000UL)     /*!< MSTPD15 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD14_Pos    (14UL)         /*!< MSTPD14 (Bit 14)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD14_Msk    (0x4000UL)     /*!< MSTPD14 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD13_Pos    (13UL)         /*!< MSTPD13 (Bit 13)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD13_Msk    (0x2000UL)     /*!< MSTPD13 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD12_Pos    (12UL)         /*!< MSTPD12 (Bit 12)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD12_Msk    (0x1000UL)     /*!< MSTPD12 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD11_Pos    (11UL)         /*!< MSTPD11 (Bit 11)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD11_Msk    (0x800UL)      /*!< MSTPD11 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD10_Pos    (10UL)         /*!< MSTPD10 (Bit 10)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD10_Msk    (0x400UL)      /*!< MSTPD10 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD9_Pos     (9UL)          /*!< MSTPD9 (Bit 9)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD9_Msk     (0x200UL)      /*!< MSTPD9 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRD_MSTPD8_Pos     (8UL)          /*!< MSTPD8 (Bit 8)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD8_Msk     (0x100UL)      /*!< MSTPD8 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRD_MSTPD7_Pos     (7UL)          /*!< MSTPD7 (Bit 7)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD7_Msk     (0x80UL)       /*!< MSTPD7 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRD_MSTPD6_Pos     (6UL)          /*!< MSTPD6 (Bit 6)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD6_Msk     (0x40UL)       /*!< MSTPD6 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRD_MSTPD5_Pos     (5UL)          /*!< MSTPD5 (Bit 5)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD5_Msk     (0x20UL)       /*!< MSTPD5 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRD_MSTPD3_Pos     (3UL)          /*!< MSTPD3 (Bit 3)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD3_Msk     (0x8UL)        /*!< MSTPD3 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRD_MSTPD2_Pos     (2UL)          /*!< MSTPD2 (Bit 2)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD2_Msk     (0x4UL)        /*!< MSTPD2 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRD_MSTPD1_Pos     (1UL)          /*!< MSTPD1 (Bit 1)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD1_Msk     (0x2UL)        /*!< MSTPD1 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRD_MSTPD0_Pos     (0UL)          /*!< MSTPD0 (Bit 0)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD0_Msk     (0x1UL)        /*!< MSTPD0 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  MSTPCRE  ======================================================== */
+ #define R_MSTP_MSTPCRE_MSTPE4_Pos     (4UL)          /*!< MSTPE4 (Bit 4)                                        */
+ #define R_MSTP_MSTPCRE_MSTPE4_Msk     (0x10UL)       /*!< MSTPE4 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRE_MSTPE14_Pos    (14UL)         /*!< MSTPE14 (Bit 14)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE14_Msk    (0x4000UL)     /*!< MSTPE14 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE15_Pos    (15UL)         /*!< MSTPE15 (Bit 15)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE15_Msk    (0x8000UL)     /*!< MSTPE15 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE22_Pos    (22UL)         /*!< MSTPE22 (Bit 22)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE22_Msk    (0x400000UL)   /*!< MSTPE22 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE23_Pos    (23UL)         /*!< MSTPE23 (Bit 23)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE23_Msk    (0x800000UL)   /*!< MSTPE23 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE24_Pos    (24UL)         /*!< MSTPE24 (Bit 24)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE24_Msk    (0x1000000UL)  /*!< MSTPE24 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE25_Pos    (25UL)         /*!< MSTPE25 (Bit 25)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE25_Msk    (0x2000000UL)  /*!< MSTPE25 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE26_Pos    (26UL)         /*!< MSTPE26 (Bit 26)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE26_Msk    (0x4000000UL)  /*!< MSTPE26 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE27_Pos    (27UL)         /*!< MSTPE27 (Bit 27)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE27_Msk    (0x8000000UL)  /*!< MSTPE27 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE28_Pos    (28UL)         /*!< MSTPE28 (Bit 28)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE28_Msk    (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE29_Pos    (29UL)         /*!< MSTPE29 (Bit 29)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE29_Msk    (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE30_Pos    (30UL)         /*!< MSTPE30 (Bit 30)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE30_Msk    (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE31_Pos    (31UL)         /*!< MSTPE31 (Bit 31)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE31_Msk    (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_PORT0                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  PCNTR1  ========================================================= */
+ #define R_PORT0_PCNTR1_PODR_Pos    (16UL)         /*!< PODR (Bit 16)                                         */
+ #define R_PORT0_PCNTR1_PODR_Msk    (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff)                          */
+ #define R_PORT0_PCNTR1_PDR_Pos     (0UL)          /*!< PDR (Bit 0)                                           */
+ #define R_PORT0_PCNTR1_PDR_Msk     (0xffffUL)     /*!< PDR (Bitfield-Mask: 0xffff)                           */
+/* =========================================================  PODR  ========================================================== */
+ #define R_PORT0_PODR_PODR_Pos      (0UL)          /*!< PODR (Bit 0)                                          */
+ #define R_PORT0_PODR_PODR_Msk      (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  PDR  ========================================================== */
+ #define R_PORT0_PDR_PDR_Pos        (0UL)          /*!< PDR (Bit 0)                                           */
+ #define R_PORT0_PDR_PDR_Msk        (0x1UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
+/* ========================================================  PCNTR2  ========================================================= */
+ #define R_PORT0_PCNTR2_EIDR_Pos    (16UL)         /*!< EIDR (Bit 16)                                         */
+ #define R_PORT0_PCNTR2_EIDR_Msk    (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff)                          */
+ #define R_PORT0_PCNTR2_PIDR_Pos    (0UL)          /*!< PIDR (Bit 0)                                          */
+ #define R_PORT0_PCNTR2_PIDR_Msk    (0xffffUL)     /*!< PIDR (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  EIDR  ========================================================== */
+ #define R_PORT0_EIDR_EIDR_Pos      (0UL)          /*!< EIDR (Bit 0)                                          */
+ #define R_PORT0_EIDR_EIDR_Msk      (0x1UL)        /*!< EIDR (Bitfield-Mask: 0x01)                            */
+/* =========================================================  PIDR  ========================================================== */
+ #define R_PORT0_PIDR_PIDR_Pos      (0UL)          /*!< PIDR (Bit 0)                                          */
+ #define R_PORT0_PIDR_PIDR_Msk      (0x1UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  PCNTR3  ========================================================= */
+ #define R_PORT0_PCNTR3_PORR_Pos    (16UL)         /*!< PORR (Bit 16)                                         */
+ #define R_PORT0_PCNTR3_PORR_Msk    (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff)                          */
+ #define R_PORT0_PCNTR3_POSR_Pos    (0UL)          /*!< POSR (Bit 0)                                          */
+ #define R_PORT0_PCNTR3_POSR_Msk    (0xffffUL)     /*!< POSR (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  PORR  ========================================================== */
+ #define R_PORT0_PORR_PORR_Pos      (0UL)          /*!< PORR (Bit 0)                                          */
+ #define R_PORT0_PORR_PORR_Msk      (0x1UL)        /*!< PORR (Bitfield-Mask: 0x01)                            */
+/* =========================================================  POSR  ========================================================== */
+ #define R_PORT0_POSR_POSR_Pos      (0UL)          /*!< POSR (Bit 0)                                          */
+ #define R_PORT0_POSR_POSR_Msk      (0x1UL)        /*!< POSR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  PCNTR4  ========================================================= */
+ #define R_PORT0_PCNTR4_EORR_Pos    (16UL)         /*!< EORR (Bit 16)                                         */
+ #define R_PORT0_PCNTR4_EORR_Msk    (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff)                          */
+ #define R_PORT0_PCNTR4_EOSR_Pos    (0UL)          /*!< EOSR (Bit 0)                                          */
+ #define R_PORT0_PCNTR4_EOSR_Msk    (0xffffUL)     /*!< EOSR (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  EORR  ========================================================== */
+ #define R_PORT0_EORR_EORR_Pos      (0UL)          /*!< EORR (Bit 0)                                          */
+ #define R_PORT0_EORR_EORR_Msk      (0x1UL)        /*!< EORR (Bitfield-Mask: 0x01)                            */
+/* =========================================================  EOSR  ========================================================== */
+ #define R_PORT0_EOSR_EOSR_Pos      (0UL)          /*!< EOSR (Bit 0)                                          */
+ #define R_PORT0_EOSR_EOSR_Msk      (0x1UL)        /*!< EOSR (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_PFS                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_PMISC                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  PFENET  ========================================================= */
+ #define R_PMISC_PFENET_PHYMODE1_Pos    (5UL)    /*!< PHYMODE1 (Bit 5)                                      */
+ #define R_PMISC_PFENET_PHYMODE1_Msk    (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01)                        */
+ #define R_PMISC_PFENET_PHYMODE0_Pos    (4UL)    /*!< PHYMODE0 (Bit 4)                                      */
+ #define R_PMISC_PFENET_PHYMODE0_Msk    (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01)                        */
+/* =========================================================  PWPR  ========================================================== */
+ #define R_PMISC_PWPR_PFSWE_Pos         (6UL)    /*!< PFSWE (Bit 6)                                         */
+ #define R_PMISC_PWPR_PFSWE_Msk         (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
+ #define R_PMISC_PWPR_B0WI_Pos          (7UL)    /*!< B0WI (Bit 7)                                          */
+ #define R_PMISC_PWPR_B0WI_Msk          (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
+/* =========================================================  PWPRS  ========================================================= */
+ #define R_PMISC_PWPRS_PFSWE_Pos        (6UL)    /*!< PFSWE (Bit 6)                                         */
+ #define R_PMISC_PWPRS_PFSWE_Msk        (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
+ #define R_PMISC_PWPRS_B0WI_Pos         (7UL)    /*!< B0WI (Bit 7)                                          */
+ #define R_PMISC_PWPRS_B0WI_Msk         (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_RTC                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  R64CNT  ========================================================= */
+ #define R_RTC_R64CNT_F1HZ_Pos        (6UL)      /*!< F1HZ (Bit 6)                                          */
+ #define R_RTC_R64CNT_F1HZ_Msk        (0x40UL)   /*!< F1HZ (Bitfield-Mask: 0x01)                            */
+ #define R_RTC_R64CNT_F2HZ_Pos        (5UL)      /*!< F2HZ (Bit 5)                                          */
+ #define R_RTC_R64CNT_F2HZ_Msk        (0x20UL)   /*!< F2HZ (Bitfield-Mask: 0x01)                            */
+ #define R_RTC_R64CNT_F4HZ_Pos        (4UL)      /*!< F4HZ (Bit 4)                                          */
+ #define R_RTC_R64CNT_F4HZ_Msk        (0x10UL)   /*!< F4HZ (Bitfield-Mask: 0x01)                            */
+ #define R_RTC_R64CNT_F8HZ_Pos        (3UL)      /*!< F8HZ (Bit 3)                                          */
+ #define R_RTC_R64CNT_F8HZ_Msk        (0x8UL)    /*!< F8HZ (Bitfield-Mask: 0x01)                            */
+ #define R_RTC_R64CNT_F16HZ_Pos       (2UL)      /*!< F16HZ (Bit 2)                                         */
+ #define R_RTC_R64CNT_F16HZ_Msk       (0x4UL)    /*!< F16HZ (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_R64CNT_F32HZ_Pos       (1UL)      /*!< F32HZ (Bit 1)                                         */
+ #define R_RTC_R64CNT_F32HZ_Msk       (0x2UL)    /*!< F32HZ (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_R64CNT_F64HZ_Pos       (0UL)      /*!< F64HZ (Bit 0)                                         */
+ #define R_RTC_R64CNT_F64HZ_Msk       (0x1UL)    /*!< F64HZ (Bitfield-Mask: 0x01)                           */
+/* ========================================================  RSECCNT  ======================================================== */
+ #define R_RTC_RSECCNT_SEC10_Pos      (4UL)      /*!< SEC10 (Bit 4)                                         */
+ #define R_RTC_RSECCNT_SEC10_Msk      (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
+ #define R_RTC_RSECCNT_SEC1_Pos       (0UL)      /*!< SEC1 (Bit 0)                                          */
+ #define R_RTC_RSECCNT_SEC1_Msk       (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  BCNT0  ========================================================= */
+ #define R_RTC_BCNT0_BCNT0_Pos        (0UL)      /*!< BCNT0 (Bit 0)                                         */
+ #define R_RTC_BCNT0_BCNT0_Msk        (0xffUL)   /*!< BCNT0 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  RMINCNT  ======================================================== */
+ #define R_RTC_RMINCNT_MIN10_Pos      (4UL)      /*!< MIN10 (Bit 4)                                         */
+ #define R_RTC_RMINCNT_MIN10_Msk      (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
+ #define R_RTC_RMINCNT_MIN1_Pos       (0UL)      /*!< MIN1 (Bit 0)                                          */
+ #define R_RTC_RMINCNT_MIN1_Msk       (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  BCNT1  ========================================================= */
+ #define R_RTC_BCNT1_BCNT1_Pos        (0UL)      /*!< BCNT1 (Bit 0)                                         */
+ #define R_RTC_BCNT1_BCNT1_Msk        (0xffUL)   /*!< BCNT1 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  RHRCNT  ========================================================= */
+ #define R_RTC_RHRCNT_PM_Pos          (6UL)      /*!< PM (Bit 6)                                            */
+ #define R_RTC_RHRCNT_PM_Msk          (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
+ #define R_RTC_RHRCNT_HR10_Pos        (4UL)      /*!< HR10 (Bit 4)                                          */
+ #define R_RTC_RHRCNT_HR10_Msk        (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
+ #define R_RTC_RHRCNT_HR1_Pos         (0UL)      /*!< HR1 (Bit 0)                                           */
+ #define R_RTC_RHRCNT_HR1_Msk         (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  BCNT2  ========================================================= */
+ #define R_RTC_BCNT2_BCNT2_Pos        (0UL)      /*!< BCNT2 (Bit 0)                                         */
+ #define R_RTC_BCNT2_BCNT2_Msk        (0xffUL)   /*!< BCNT2 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  RWKCNT  ========================================================= */
+ #define R_RTC_RWKCNT_DAYW_Pos        (0UL)      /*!< DAYW (Bit 0)                                          */
+ #define R_RTC_RWKCNT_DAYW_Msk        (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
+/* =========================================================  BCNT3  ========================================================= */
+ #define R_RTC_BCNT3_BCNT3_Pos        (0UL)      /*!< BCNT3 (Bit 0)                                         */
+ #define R_RTC_BCNT3_BCNT3_Msk        (0xffUL)   /*!< BCNT3 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  RDAYCNT  ======================================================== */
+ #define R_RTC_RDAYCNT_DATE10_Pos     (4UL)      /*!< DATE10 (Bit 4)                                        */
+ #define R_RTC_RDAYCNT_DATE10_Msk     (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
+ #define R_RTC_RDAYCNT_DATE1_Pos      (0UL)      /*!< DATE1 (Bit 0)                                         */
+ #define R_RTC_RDAYCNT_DATE1_Msk      (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
+/* ========================================================  RMONCNT  ======================================================== */
+ #define R_RTC_RMONCNT_MON10_Pos      (4UL)      /*!< MON10 (Bit 4)                                         */
+ #define R_RTC_RMONCNT_MON10_Msk      (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RMONCNT_MON1_Pos       (0UL)      /*!< MON1 (Bit 0)                                          */
+ #define R_RTC_RMONCNT_MON1_Msk       (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  RYRCNT  ========================================================= */
+ #define R_RTC_RYRCNT_YR10_Pos        (4UL)      /*!< YR10 (Bit 4)                                          */
+ #define R_RTC_RYRCNT_YR10_Msk        (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
+ #define R_RTC_RYRCNT_YR1_Pos         (0UL)      /*!< YR1 (Bit 0)                                           */
+ #define R_RTC_RYRCNT_YR1_Msk         (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
+/* ========================================================  RSECAR  ========================================================= */
+ #define R_RTC_RSECAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RSECAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RSECAR_SEC10_Pos       (4UL)      /*!< SEC10 (Bit 4)                                         */
+ #define R_RTC_RSECAR_SEC10_Msk       (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
+ #define R_RTC_RSECAR_SEC1_Pos        (0UL)      /*!< SEC1 (Bit 0)                                          */
+ #define R_RTC_RSECAR_SEC1_Msk        (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  BCNT0AR  ======================================================== */
+ #define R_RTC_BCNT0AR_BCNT0AR_Pos    (0UL)      /*!< BCNT0AR (Bit 0)                                       */
+ #define R_RTC_BCNT0AR_BCNT0AR_Msk    (0xffUL)   /*!< BCNT0AR (Bitfield-Mask: 0xff)                         */
+/* ========================================================  RMINAR  ========================================================= */
+ #define R_RTC_RMINAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RMINAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RMINAR_MIN10_Pos       (4UL)      /*!< MIN10 (Bit 4)                                         */
+ #define R_RTC_RMINAR_MIN10_Msk       (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
+ #define R_RTC_RMINAR_MIN1_Pos        (0UL)      /*!< MIN1 (Bit 0)                                          */
+ #define R_RTC_RMINAR_MIN1_Msk        (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  BCNT1AR  ======================================================== */
+ #define R_RTC_BCNT1AR_BCNT1AR_Pos    (0UL)      /*!< BCNT1AR (Bit 0)                                       */
+ #define R_RTC_BCNT1AR_BCNT1AR_Msk    (0xffUL)   /*!< BCNT1AR (Bitfield-Mask: 0xff)                         */
+/* =========================================================  RHRAR  ========================================================= */
+ #define R_RTC_RHRAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RHRAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RHRAR_PM_Pos           (6UL)      /*!< PM (Bit 6)                                            */
+ #define R_RTC_RHRAR_PM_Msk           (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
+ #define R_RTC_RHRAR_HR10_Pos         (4UL)      /*!< HR10 (Bit 4)                                          */
+ #define R_RTC_RHRAR_HR10_Msk         (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
+ #define R_RTC_RHRAR_HR1_Pos          (0UL)      /*!< HR1 (Bit 0)                                           */
+ #define R_RTC_RHRAR_HR1_Msk          (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
+/* ========================================================  BCNT2AR  ======================================================== */
+ #define R_RTC_BCNT2AR_BCNT2AR_Pos    (0UL)      /*!< BCNT2AR (Bit 0)                                       */
+ #define R_RTC_BCNT2AR_BCNT2AR_Msk    (0xffUL)   /*!< BCNT2AR (Bitfield-Mask: 0xff)                         */
+/* =========================================================  RWKAR  ========================================================= */
+ #define R_RTC_RWKAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RWKAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RWKAR_DAYW_Pos         (0UL)      /*!< DAYW (Bit 0)                                          */
+ #define R_RTC_RWKAR_DAYW_Msk         (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
+/* ========================================================  BCNT3AR  ======================================================== */
+ #define R_RTC_BCNT3AR_BCNT3AR_Pos    (0UL)      /*!< BCNT3AR (Bit 0)                                       */
+ #define R_RTC_BCNT3AR_BCNT3AR_Msk    (0xffUL)   /*!< BCNT3AR (Bitfield-Mask: 0xff)                         */
+/* ========================================================  RDAYAR  ========================================================= */
+ #define R_RTC_RDAYAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RDAYAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RDAYAR_DATE10_Pos      (4UL)      /*!< DATE10 (Bit 4)                                        */
+ #define R_RTC_RDAYAR_DATE10_Msk      (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
+ #define R_RTC_RDAYAR_DATE1_Pos       (0UL)      /*!< DATE1 (Bit 0)                                         */
+ #define R_RTC_RDAYAR_DATE1_Msk       (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
+/* =======================================================  BCNT0AER  ======================================================== */
+ #define R_RTC_BCNT0AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
+ #define R_RTC_BCNT0AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
+/* ========================================================  RMONAR  ========================================================= */
+ #define R_RTC_RMONAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RMONAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RMONAR_MON10_Pos       (4UL)      /*!< MON10 (Bit 4)                                         */
+ #define R_RTC_RMONAR_MON10_Msk       (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RMONAR_MON1_Pos        (0UL)      /*!< MON1 (Bit 0)                                          */
+ #define R_RTC_RMONAR_MON1_Msk        (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
+/* =======================================================  BCNT1AER  ======================================================== */
+ #define R_RTC_BCNT1AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
+ #define R_RTC_BCNT1AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
+/* =========================================================  RYRAR  ========================================================= */
+ #define R_RTC_RYRAR_YR10_Pos         (4UL)      /*!< YR10 (Bit 4)                                          */
+ #define R_RTC_RYRAR_YR10_Msk         (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
+ #define R_RTC_RYRAR_YR1_Pos          (0UL)      /*!< YR1 (Bit 0)                                           */
+ #define R_RTC_RYRAR_YR1_Msk          (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
+/* =======================================================  BCNT2AER  ======================================================== */
+ #define R_RTC_BCNT2AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
+ #define R_RTC_BCNT2AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
+/* ========================================================  RYRAREN  ======================================================== */
+ #define R_RTC_RYRAREN_ENB_Pos        (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RYRAREN_ENB_Msk        (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+/* =======================================================  BCNT3AER  ======================================================== */
+ #define R_RTC_BCNT3AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
+ #define R_RTC_BCNT3AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
+/* =========================================================  RCR1  ========================================================== */
+ #define R_RTC_RCR1_PES_Pos           (4UL)      /*!< PES (Bit 4)                                           */
+ #define R_RTC_RCR1_PES_Msk           (0xf0UL)   /*!< PES (Bitfield-Mask: 0x0f)                             */
+ #define R_RTC_RCR1_RTCOS_Pos         (3UL)      /*!< RTCOS (Bit 3)                                         */
+ #define R_RTC_RCR1_RTCOS_Msk         (0x8UL)    /*!< RTCOS (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR1_PIE_Pos           (2UL)      /*!< PIE (Bit 2)                                           */
+ #define R_RTC_RCR1_PIE_Msk           (0x4UL)    /*!< PIE (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RCR1_CIE_Pos           (1UL)      /*!< CIE (Bit 1)                                           */
+ #define R_RTC_RCR1_CIE_Msk           (0x2UL)    /*!< CIE (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RCR1_AIE_Pos           (0UL)      /*!< AIE (Bit 0)                                           */
+ #define R_RTC_RCR1_AIE_Msk           (0x1UL)    /*!< AIE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  RCR2  ========================================================== */
+ #define R_RTC_RCR2_CNTMD_Pos         (7UL)      /*!< CNTMD (Bit 7)                                         */
+ #define R_RTC_RCR2_CNTMD_Msk         (0x80UL)   /*!< CNTMD (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR2_HR24_Pos          (6UL)      /*!< HR24 (Bit 6)                                          */
+ #define R_RTC_RCR2_HR24_Msk          (0x40UL)   /*!< HR24 (Bitfield-Mask: 0x01)                            */
+ #define R_RTC_RCR2_AADJP_Pos         (5UL)      /*!< AADJP (Bit 5)                                         */
+ #define R_RTC_RCR2_AADJP_Msk         (0x20UL)   /*!< AADJP (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR2_AADJE_Pos         (4UL)      /*!< AADJE (Bit 4)                                         */
+ #define R_RTC_RCR2_AADJE_Msk         (0x10UL)   /*!< AADJE (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR2_RTCOE_Pos         (3UL)      /*!< RTCOE (Bit 3)                                         */
+ #define R_RTC_RCR2_RTCOE_Msk         (0x8UL)    /*!< RTCOE (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR2_ADJ30_Pos         (2UL)      /*!< ADJ30 (Bit 2)                                         */
+ #define R_RTC_RCR2_ADJ30_Msk         (0x4UL)    /*!< ADJ30 (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR2_RESET_Pos         (1UL)      /*!< RESET (Bit 1)                                         */
+ #define R_RTC_RCR2_RESET_Msk         (0x2UL)    /*!< RESET (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR2_START_Pos         (0UL)      /*!< START (Bit 0)                                         */
+ #define R_RTC_RCR2_START_Msk         (0x1UL)    /*!< START (Bitfield-Mask: 0x01)                           */
+/* =========================================================  RCR4  ========================================================== */
+ #define R_RTC_RCR4_RCKSEL_Pos        (0UL)      /*!< RCKSEL (Bit 0)                                        */
+ #define R_RTC_RCR4_RCKSEL_Msk        (0x1UL)    /*!< RCKSEL (Bitfield-Mask: 0x01)                          */
+ #define R_RTC_RCR4_ROPSEL_Pos        (7UL)      /*!< ROPSEL (Bit 7)                                        */
+ #define R_RTC_RCR4_ROPSEL_Msk        (0x80UL)   /*!< ROPSEL (Bitfield-Mask: 0x01)                          */
+/* =========================================================  RFRH  ========================================================== */
+ #define R_RTC_RFRH_RFC16_Pos         (0UL)      /*!< RFC16 (Bit 0)                                         */
+ #define R_RTC_RFRH_RFC16_Msk         (0x1UL)    /*!< RFC16 (Bitfield-Mask: 0x01)                           */
+/* =========================================================  RFRL  ========================================================== */
+ #define R_RTC_RFRL_RFC_Pos           (0UL)      /*!< RFC (Bit 0)                                           */
+ #define R_RTC_RFRL_RFC_Msk           (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff)                           */
+/* =========================================================  RADJ  ========================================================== */
+ #define R_RTC_RADJ_PMADJ_Pos         (6UL)      /*!< PMADJ (Bit 6)                                         */
+ #define R_RTC_RADJ_PMADJ_Msk         (0xc0UL)   /*!< PMADJ (Bitfield-Mask: 0x03)                           */
+ #define R_RTC_RADJ_ADJ_Pos           (0UL)      /*!< ADJ (Bit 0)                                           */
+ #define R_RTC_RADJ_ADJ_Msk           (0x3fUL)   /*!< ADJ (Bitfield-Mask: 0x3f)                             */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SCI0                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  SMR  ========================================================== */
+ #define R_SCI0_SMR_CM_Pos              (7UL)      /*!< CM (Bit 7)                                            */
+ #define R_SCI0_SMR_CM_Msk              (0x80UL)   /*!< CM (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_CHR_Pos             (6UL)      /*!< CHR (Bit 6)                                           */
+ #define R_SCI0_SMR_CHR_Msk             (0x40UL)   /*!< CHR (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SMR_PE_Pos              (5UL)      /*!< PE (Bit 5)                                            */
+ #define R_SCI0_SMR_PE_Msk              (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_PM_Pos              (4UL)      /*!< PM (Bit 4)                                            */
+ #define R_SCI0_SMR_PM_Msk              (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_STOP_Pos            (3UL)      /*!< STOP (Bit 3)                                          */
+ #define R_SCI0_SMR_STOP_Msk            (0x8UL)    /*!< STOP (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SMR_MP_Pos              (2UL)      /*!< MP (Bit 2)                                            */
+ #define R_SCI0_SMR_MP_Msk              (0x4UL)    /*!< MP (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_CKS_Pos             (0UL)      /*!< CKS (Bit 0)                                           */
+ #define R_SCI0_SMR_CKS_Msk             (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
+/* =======================================================  SMR_SMCI  ======================================================== */
+ #define R_SCI0_SMR_SMCI_GM_Pos         (7UL)      /*!< GM (Bit 7)                                            */
+ #define R_SCI0_SMR_SMCI_GM_Msk         (0x80UL)   /*!< GM (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_SMCI_BLK_Pos        (6UL)      /*!< BLK (Bit 6)                                           */
+ #define R_SCI0_SMR_SMCI_BLK_Msk        (0x40UL)   /*!< BLK (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SMR_SMCI_PE_Pos         (5UL)      /*!< PE (Bit 5)                                            */
+ #define R_SCI0_SMR_SMCI_PE_Msk         (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_SMCI_PM_Pos         (4UL)      /*!< PM (Bit 4)                                            */
+ #define R_SCI0_SMR_SMCI_PM_Msk         (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_SMCI_BCP_Pos        (2UL)      /*!< BCP (Bit 2)                                           */
+ #define R_SCI0_SMR_SMCI_BCP_Msk        (0xcUL)    /*!< BCP (Bitfield-Mask: 0x03)                             */
+ #define R_SCI0_SMR_SMCI_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
+ #define R_SCI0_SMR_SMCI_CKS_Msk        (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
+/* ==========================================================  BRR  ========================================================== */
+ #define R_SCI0_BRR_BRR_Pos             (0UL)      /*!< BRR (Bit 0)                                           */
+ #define R_SCI0_BRR_BRR_Msk             (0xffUL)   /*!< BRR (Bitfield-Mask: 0xff)                             */
+/* ==========================================================  SCR  ========================================================== */
+ #define R_SCI0_SCR_TIE_Pos             (7UL)      /*!< TIE (Bit 7)                                           */
+ #define R_SCI0_SCR_TIE_Msk             (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SCR_RIE_Pos             (6UL)      /*!< RIE (Bit 6)                                           */
+ #define R_SCI0_SCR_RIE_Msk             (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SCR_TE_Pos              (5UL)      /*!< TE (Bit 5)                                            */
+ #define R_SCI0_SCR_TE_Msk              (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SCR_RE_Pos              (4UL)      /*!< RE (Bit 4)                                            */
+ #define R_SCI0_SCR_RE_Msk              (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SCR_MPIE_Pos            (3UL)      /*!< MPIE (Bit 3)                                          */
+ #define R_SCI0_SCR_MPIE_Msk            (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCR_TEIE_Pos            (2UL)      /*!< TEIE (Bit 2)                                          */
+ #define R_SCI0_SCR_TEIE_Msk            (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCR_CKE_Pos             (0UL)      /*!< CKE (Bit 0)                                           */
+ #define R_SCI0_SCR_CKE_Msk             (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
+/* =======================================================  SCR_SMCI  ======================================================== */
+ #define R_SCI0_SCR_SMCI_TIE_Pos        (7UL)      /*!< TIE (Bit 7)                                           */
+ #define R_SCI0_SCR_SMCI_TIE_Msk        (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SCR_SMCI_RIE_Pos        (6UL)      /*!< RIE (Bit 6)                                           */
+ #define R_SCI0_SCR_SMCI_RIE_Msk        (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SCR_SMCI_TE_Pos         (5UL)      /*!< TE (Bit 5)                                            */
+ #define R_SCI0_SCR_SMCI_TE_Msk         (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SCR_SMCI_RE_Pos         (4UL)      /*!< RE (Bit 4)                                            */
+ #define R_SCI0_SCR_SMCI_RE_Msk         (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SCR_SMCI_MPIE_Pos       (3UL)      /*!< MPIE (Bit 3)                                          */
+ #define R_SCI0_SCR_SMCI_MPIE_Msk       (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCR_SMCI_TEIE_Pos       (2UL)      /*!< TEIE (Bit 2)                                          */
+ #define R_SCI0_SCR_SMCI_TEIE_Msk       (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCR_SMCI_CKE_Pos        (0UL)      /*!< CKE (Bit 0)                                           */
+ #define R_SCI0_SCR_SMCI_CKE_Msk        (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
+/* ==========================================================  TDR  ========================================================== */
+ #define R_SCI0_TDR_TDR_Pos             (0UL)      /*!< TDR (Bit 0)                                           */
+ #define R_SCI0_TDR_TDR_Msk             (0xffUL)   /*!< TDR (Bitfield-Mask: 0xff)                             */
+/* ==========================================================  SSR  ========================================================== */
+ #define R_SCI0_SSR_TDRE_Pos            (7UL)      /*!< TDRE (Bit 7)                                          */
+ #define R_SCI0_SSR_TDRE_Msk            (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_RDRF_Pos            (6UL)      /*!< RDRF (Bit 6)                                          */
+ #define R_SCI0_SSR_RDRF_Msk            (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_ORER_Pos            (5UL)      /*!< ORER (Bit 5)                                          */
+ #define R_SCI0_SSR_ORER_Msk            (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_FER_Pos             (4UL)      /*!< FER (Bit 4)                                           */
+ #define R_SCI0_SSR_FER_Msk             (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_PER_Pos             (3UL)      /*!< PER (Bit 3)                                           */
+ #define R_SCI0_SSR_PER_Msk             (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_TEND_Pos            (2UL)      /*!< TEND (Bit 2)                                          */
+ #define R_SCI0_SSR_TEND_Msk            (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_MPB_Pos             (1UL)      /*!< MPB (Bit 1)                                           */
+ #define R_SCI0_SSR_MPB_Msk             (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_MPBT_Pos            (0UL)      /*!< MPBT (Bit 0)                                          */
+ #define R_SCI0_SSR_MPBT_Msk            (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
+/* =======================================================  SSR_FIFO  ======================================================== */
+ #define R_SCI0_SSR_FIFO_TDFE_Pos       (7UL)      /*!< TDFE (Bit 7)                                          */
+ #define R_SCI0_SSR_FIFO_TDFE_Msk       (0x80UL)   /*!< TDFE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_FIFO_RDF_Pos        (6UL)      /*!< RDF (Bit 6)                                           */
+ #define R_SCI0_SSR_FIFO_RDF_Msk        (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_FIFO_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
+ #define R_SCI0_SSR_FIFO_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_FIFO_FER_Pos        (4UL)      /*!< FER (Bit 4)                                           */
+ #define R_SCI0_SSR_FIFO_FER_Msk        (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_FIFO_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
+ #define R_SCI0_SSR_FIFO_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_FIFO_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
+ #define R_SCI0_SSR_FIFO_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_FIFO_DR_Pos         (0UL)      /*!< DR (Bit 0)                                            */
+ #define R_SCI0_SSR_FIFO_DR_Msk         (0x1UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
+/* =======================================================  SSR_SMCI  ======================================================== */
+ #define R_SCI0_SSR_SMCI_TDRE_Pos       (7UL)      /*!< TDRE (Bit 7)                                          */
+ #define R_SCI0_SSR_SMCI_TDRE_Msk       (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_SMCI_RDRF_Pos       (6UL)      /*!< RDRF (Bit 6)                                          */
+ #define R_SCI0_SSR_SMCI_RDRF_Msk       (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_SMCI_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
+ #define R_SCI0_SSR_SMCI_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_SMCI_ERS_Pos        (4UL)      /*!< ERS (Bit 4)                                           */
+ #define R_SCI0_SSR_SMCI_ERS_Msk        (0x10UL)   /*!< ERS (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_SMCI_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
+ #define R_SCI0_SSR_SMCI_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_SMCI_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
+ #define R_SCI0_SSR_SMCI_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_SMCI_MPB_Pos        (1UL)      /*!< MPB (Bit 1)                                           */
+ #define R_SCI0_SSR_SMCI_MPB_Msk        (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_SMCI_MPBT_Pos       (0UL)      /*!< MPBT (Bit 0)                                          */
+ #define R_SCI0_SSR_SMCI_MPBT_Msk       (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  RDR  ========================================================== */
+ #define R_SCI0_RDR_RDR_Pos             (0UL)      /*!< RDR (Bit 0)                                           */
+ #define R_SCI0_RDR_RDR_Msk             (0xffUL)   /*!< RDR (Bitfield-Mask: 0xff)                             */
+/* =========================================================  SCMR  ========================================================== */
+ #define R_SCI0_SCMR_BCP2_Pos           (7UL)      /*!< BCP2 (Bit 7)                                          */
+ #define R_SCI0_SCMR_BCP2_Msk           (0x80UL)   /*!< BCP2 (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCMR_CHR1_Pos           (4UL)      /*!< CHR1 (Bit 4)                                          */
+ #define R_SCI0_SCMR_CHR1_Msk           (0x10UL)   /*!< CHR1 (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCMR_SDIR_Pos           (3UL)      /*!< SDIR (Bit 3)                                          */
+ #define R_SCI0_SCMR_SDIR_Msk           (0x8UL)    /*!< SDIR (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCMR_SINV_Pos           (2UL)      /*!< SINV (Bit 2)                                          */
+ #define R_SCI0_SCMR_SINV_Msk           (0x4UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCMR_SMIF_Pos           (0UL)      /*!< SMIF (Bit 0)                                          */
+ #define R_SCI0_SCMR_SMIF_Msk           (0x1UL)    /*!< SMIF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SEMR  ========================================================== */
+ #define R_SCI0_SEMR_RXDESEL_Pos        (7UL)      /*!< RXDESEL (Bit 7)                                       */
+ #define R_SCI0_SEMR_RXDESEL_Msk        (0x80UL)   /*!< RXDESEL (Bitfield-Mask: 0x01)                         */
+ #define R_SCI0_SEMR_BGDM_Pos           (6UL)      /*!< BGDM (Bit 6)                                          */
+ #define R_SCI0_SEMR_BGDM_Msk           (0x40UL)   /*!< BGDM (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SEMR_NFEN_Pos           (5UL)      /*!< NFEN (Bit 5)                                          */
+ #define R_SCI0_SEMR_NFEN_Msk           (0x20UL)   /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SEMR_ABCS_Pos           (4UL)      /*!< ABCS (Bit 4)                                          */
+ #define R_SCI0_SEMR_ABCS_Msk           (0x10UL)   /*!< ABCS (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SEMR_ABCSE_Pos          (3UL)      /*!< ABCSE (Bit 3)                                         */
+ #define R_SCI0_SEMR_ABCSE_Msk          (0x8UL)    /*!< ABCSE (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_SEMR_BRME_Pos           (2UL)      /*!< BRME (Bit 2)                                          */
+ #define R_SCI0_SEMR_BRME_Msk           (0x4UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SEMR_PADIS_Pos          (1UL)      /*!< PADIS (Bit 1)                                         */
+ #define R_SCI0_SEMR_PADIS_Msk          (0x2UL)    /*!< PADIS (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_SEMR_ACS0_Pos           (0UL)      /*!< ACS0 (Bit 0)                                          */
+ #define R_SCI0_SEMR_ACS0_Msk           (0x1UL)    /*!< ACS0 (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SNFR  ========================================================== */
+ #define R_SCI0_SNFR_NFCS_Pos           (0UL)      /*!< NFCS (Bit 0)                                          */
+ #define R_SCI0_SNFR_NFCS_Msk           (0x7UL)    /*!< NFCS (Bitfield-Mask: 0x07)                            */
+/* =========================================================  SIMR1  ========================================================= */
+ #define R_SCI0_SIMR1_IICDL_Pos         (3UL)      /*!< IICDL (Bit 3)                                         */
+ #define R_SCI0_SIMR1_IICDL_Msk         (0xf8UL)   /*!< IICDL (Bitfield-Mask: 0x1f)                           */
+ #define R_SCI0_SIMR1_IICM_Pos          (0UL)      /*!< IICM (Bit 0)                                          */
+ #define R_SCI0_SIMR1_IICM_Msk          (0x1UL)    /*!< IICM (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SIMR2  ========================================================= */
+ #define R_SCI0_SIMR2_IICACKT_Pos       (5UL)      /*!< IICACKT (Bit 5)                                       */
+ #define R_SCI0_SIMR2_IICACKT_Msk       (0x20UL)   /*!< IICACKT (Bitfield-Mask: 0x01)                         */
+ #define R_SCI0_SIMR2_IICCSC_Pos        (1UL)      /*!< IICCSC (Bit 1)                                        */
+ #define R_SCI0_SIMR2_IICCSC_Msk        (0x2UL)    /*!< IICCSC (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_SIMR2_IICINTM_Pos       (0UL)      /*!< IICINTM (Bit 0)                                       */
+ #define R_SCI0_SIMR2_IICINTM_Msk       (0x1UL)    /*!< IICINTM (Bitfield-Mask: 0x01)                         */
+/* =========================================================  SIMR3  ========================================================= */
+ #define R_SCI0_SIMR3_IICSCLS_Pos       (6UL)      /*!< IICSCLS (Bit 6)                                       */
+ #define R_SCI0_SIMR3_IICSCLS_Msk       (0xc0UL)   /*!< IICSCLS (Bitfield-Mask: 0x03)                         */
+ #define R_SCI0_SIMR3_IICSDAS_Pos       (4UL)      /*!< IICSDAS (Bit 4)                                       */
+ #define R_SCI0_SIMR3_IICSDAS_Msk       (0x30UL)   /*!< IICSDAS (Bitfield-Mask: 0x03)                         */
+ #define R_SCI0_SIMR3_IICSTIF_Pos       (3UL)      /*!< IICSTIF (Bit 3)                                       */
+ #define R_SCI0_SIMR3_IICSTIF_Msk       (0x8UL)    /*!< IICSTIF (Bitfield-Mask: 0x01)                         */
+ #define R_SCI0_SIMR3_IICSTPREQ_Pos     (2UL)      /*!< IICSTPREQ (Bit 2)                                     */
+ #define R_SCI0_SIMR3_IICSTPREQ_Msk     (0x4UL)    /*!< IICSTPREQ (Bitfield-Mask: 0x01)                       */
+ #define R_SCI0_SIMR3_IICRSTAREQ_Pos    (1UL)      /*!< IICRSTAREQ (Bit 1)                                    */
+ #define R_SCI0_SIMR3_IICRSTAREQ_Msk    (0x2UL)    /*!< IICRSTAREQ (Bitfield-Mask: 0x01)                      */
+ #define R_SCI0_SIMR3_IICSTAREQ_Pos     (0UL)      /*!< IICSTAREQ (Bit 0)                                     */
+ #define R_SCI0_SIMR3_IICSTAREQ_Msk     (0x1UL)    /*!< IICSTAREQ (Bitfield-Mask: 0x01)                       */
+/* =========================================================  SISR  ========================================================== */
+ #define R_SCI0_SISR_IICACKR_Pos        (0UL)      /*!< IICACKR (Bit 0)                                       */
+ #define R_SCI0_SISR_IICACKR_Msk        (0x1UL)    /*!< IICACKR (Bitfield-Mask: 0x01)                         */
+/* =========================================================  SPMR  ========================================================== */
+ #define R_SCI0_SPMR_CKPH_Pos           (7UL)      /*!< CKPH (Bit 7)                                          */
+ #define R_SCI0_SPMR_CKPH_Msk           (0x80UL)   /*!< CKPH (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SPMR_CKPOL_Pos          (6UL)      /*!< CKPOL (Bit 6)                                         */
+ #define R_SCI0_SPMR_CKPOL_Msk          (0x40UL)   /*!< CKPOL (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_SPMR_MFF_Pos            (4UL)      /*!< MFF (Bit 4)                                           */
+ #define R_SCI0_SPMR_MFF_Msk            (0x10UL)   /*!< MFF (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SPMR_CSTPEN_Pos         (3UL)      /*!< CSTPEN (Bit 3)                                        */
+ #define R_SCI0_SPMR_CSTPEN_Msk         (0x8UL)    /*!< CSTPEN (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_SPMR_MSS_Pos            (2UL)      /*!< MSS (Bit 2)                                           */
+ #define R_SCI0_SPMR_MSS_Msk            (0x4UL)    /*!< MSS (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SPMR_CTSE_Pos           (1UL)      /*!< CTSE (Bit 1)                                          */
+ #define R_SCI0_SPMR_CTSE_Msk           (0x2UL)    /*!< CTSE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SPMR_SSE_Pos            (0UL)      /*!< SSE (Bit 0)                                           */
+ #define R_SCI0_SPMR_SSE_Msk            (0x1UL)    /*!< SSE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TDRHL  ========================================================= */
+ #define R_SCI0_TDRHL_TDRHL_Pos         (0UL)      /*!< TDRHL (Bit 0)                                         */
+ #define R_SCI0_TDRHL_TDRHL_Msk         (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  FTDRHL  ========================================================= */
+ #define R_SCI0_FTDRHL_MPBT_Pos         (9UL)      /*!< MPBT (Bit 9)                                          */
+ #define R_SCI0_FTDRHL_MPBT_Msk         (0x200UL)  /*!< MPBT (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_FTDRHL_TDAT_Pos         (0UL)      /*!< TDAT (Bit 0)                                          */
+ #define R_SCI0_FTDRHL_TDAT_Msk         (0x1ffUL)  /*!< TDAT (Bitfield-Mask: 0x1ff)                           */
+/* =========================================================  FTDRH  ========================================================= */
+ #define R_SCI0_FTDRH_MPBT_Pos          (1UL)      /*!< MPBT (Bit 1)                                          */
+ #define R_SCI0_FTDRH_MPBT_Msk          (0x2UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_FTDRH_TDATH_Pos         (0UL)      /*!< TDATH (Bit 0)                                         */
+ #define R_SCI0_FTDRH_TDATH_Msk         (0x1UL)    /*!< TDATH (Bitfield-Mask: 0x01)                           */
+/* =========================================================  FTDRL  ========================================================= */
+ #define R_SCI0_FTDRL_TDATL_Pos         (0UL)      /*!< TDATL (Bit 0)                                         */
+ #define R_SCI0_FTDRL_TDATL_Msk         (0xffUL)   /*!< TDATL (Bitfield-Mask: 0xff)                           */
+/* =========================================================  RDRHL  ========================================================= */
+ #define R_SCI0_RDRHL_RDRHL_Pos         (0UL)      /*!< RDRHL (Bit 0)                                         */
+ #define R_SCI0_RDRHL_RDRHL_Msk         (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  FRDRHL  ========================================================= */
+ #define R_SCI0_FRDRHL_RDF_Pos          (14UL)     /*!< RDF (Bit 14)                                          */
+ #define R_SCI0_FRDRHL_RDF_Msk          (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRHL_ORER_Pos         (13UL)     /*!< ORER (Bit 13)                                         */
+ #define R_SCI0_FRDRHL_ORER_Msk         (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_FRDRHL_FER_Pos          (12UL)     /*!< FER (Bit 12)                                          */
+ #define R_SCI0_FRDRHL_FER_Msk          (0x1000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRHL_PER_Pos          (11UL)     /*!< PER (Bit 11)                                          */
+ #define R_SCI0_FRDRHL_PER_Msk          (0x800UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRHL_DR_Pos           (10UL)     /*!< DR (Bit 10)                                           */
+ #define R_SCI0_FRDRHL_DR_Msk           (0x400UL)  /*!< DR (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_FRDRHL_MPB_Pos          (9UL)      /*!< MPB (Bit 9)                                           */
+ #define R_SCI0_FRDRHL_MPB_Msk          (0x200UL)  /*!< MPB (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRHL_RDAT_Pos         (0UL)      /*!< RDAT (Bit 0)                                          */
+ #define R_SCI0_FRDRHL_RDAT_Msk         (0x1ffUL)  /*!< RDAT (Bitfield-Mask: 0x1ff)                           */
+/* =========================================================  FRDRH  ========================================================= */
+ #define R_SCI0_FRDRH_RDF_Pos           (6UL)      /*!< RDF (Bit 6)                                           */
+ #define R_SCI0_FRDRH_RDF_Msk           (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRH_ORER_Pos          (5UL)      /*!< ORER (Bit 5)                                          */
+ #define R_SCI0_FRDRH_ORER_Msk          (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_FRDRH_FER_Pos           (4UL)      /*!< FER (Bit 4)                                           */
+ #define R_SCI0_FRDRH_FER_Msk           (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRH_PER_Pos           (3UL)      /*!< PER (Bit 3)                                           */
+ #define R_SCI0_FRDRH_PER_Msk           (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRH_DR_Pos            (2UL)      /*!< DR (Bit 2)                                            */
+ #define R_SCI0_FRDRH_DR_Msk            (0x4UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_FRDRH_MPB_Pos           (1UL)      /*!< MPB (Bit 1)                                           */
+ #define R_SCI0_FRDRH_MPB_Msk           (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRH_RDATH_Pos         (0UL)      /*!< RDATH (Bit 0)                                         */
+ #define R_SCI0_FRDRH_RDATH_Msk         (0x1UL)    /*!< RDATH (Bitfield-Mask: 0x01)                           */
+/* =========================================================  FRDRL  ========================================================= */
+ #define R_SCI0_FRDRL_RDATL_Pos         (0UL)      /*!< RDATL (Bit 0)                                         */
+ #define R_SCI0_FRDRL_RDATL_Msk         (0xffUL)   /*!< RDATL (Bitfield-Mask: 0xff)                           */
+/* =========================================================  MDDR  ========================================================== */
+ #define R_SCI0_MDDR_MDDR_Pos           (0UL)      /*!< MDDR (Bit 0)                                          */
+ #define R_SCI0_MDDR_MDDR_Msk           (0xffUL)   /*!< MDDR (Bitfield-Mask: 0xff)                            */
+/* =========================================================  DCCR  ========================================================== */
+ #define R_SCI0_DCCR_DCME_Pos           (7UL)      /*!< DCME (Bit 7)                                          */
+ #define R_SCI0_DCCR_DCME_Msk           (0x80UL)   /*!< DCME (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_DCCR_IDSEL_Pos          (6UL)      /*!< IDSEL (Bit 6)                                         */
+ #define R_SCI0_DCCR_IDSEL_Msk          (0x40UL)   /*!< IDSEL (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_DCCR_DFER_Pos           (4UL)      /*!< DFER (Bit 4)                                          */
+ #define R_SCI0_DCCR_DFER_Msk           (0x10UL)   /*!< DFER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_DCCR_DPER_Pos           (3UL)      /*!< DPER (Bit 3)                                          */
+ #define R_SCI0_DCCR_DPER_Msk           (0x8UL)    /*!< DPER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_DCCR_DCMF_Pos           (0UL)      /*!< DCMF (Bit 0)                                          */
+ #define R_SCI0_DCCR_DCMF_Msk           (0x1UL)    /*!< DCMF (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  FCR  ========================================================== */
+ #define R_SCI0_FCR_RSTRG_Pos           (12UL)     /*!< RSTRG (Bit 12)                                        */
+ #define R_SCI0_FCR_RSTRG_Msk           (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f)                           */
+ #define R_SCI0_FCR_RTRG_Pos            (8UL)      /*!< RTRG (Bit 8)                                          */
+ #define R_SCI0_FCR_RTRG_Msk            (0xf00UL)  /*!< RTRG (Bitfield-Mask: 0x0f)                            */
+ #define R_SCI0_FCR_TTRG_Pos            (4UL)      /*!< TTRG (Bit 4)                                          */
+ #define R_SCI0_FCR_TTRG_Msk            (0xf0UL)   /*!< TTRG (Bitfield-Mask: 0x0f)                            */
+ #define R_SCI0_FCR_DRES_Pos            (3UL)      /*!< DRES (Bit 3)                                          */
+ #define R_SCI0_FCR_DRES_Msk            (0x8UL)    /*!< DRES (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_FCR_TFRST_Pos           (2UL)      /*!< TFRST (Bit 2)                                         */
+ #define R_SCI0_FCR_TFRST_Msk           (0x4UL)    /*!< TFRST (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_FCR_RFRST_Pos           (1UL)      /*!< RFRST (Bit 1)                                         */
+ #define R_SCI0_FCR_RFRST_Msk           (0x2UL)    /*!< RFRST (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_FCR_FM_Pos              (0UL)      /*!< FM (Bit 0)                                            */
+ #define R_SCI0_FCR_FM_Msk              (0x1UL)    /*!< FM (Bitfield-Mask: 0x01)                              */
+/* ==========================================================  FDR  ========================================================== */
+ #define R_SCI0_FDR_T_Pos               (8UL)      /*!< T (Bit 8)                                             */
+ #define R_SCI0_FDR_T_Msk               (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f)                               */
+ #define R_SCI0_FDR_R_Pos               (0UL)      /*!< R (Bit 0)                                             */
+ #define R_SCI0_FDR_R_Msk               (0x1fUL)   /*!< R (Bitfield-Mask: 0x1f)                               */
+/* ==========================================================  LSR  ========================================================== */
+ #define R_SCI0_LSR_PNUM_Pos            (8UL)      /*!< PNUM (Bit 8)                                          */
+ #define R_SCI0_LSR_PNUM_Msk            (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f)                            */
+ #define R_SCI0_LSR_FNUM_Pos            (2UL)      /*!< FNUM (Bit 2)                                          */
+ #define R_SCI0_LSR_FNUM_Msk            (0x7cUL)   /*!< FNUM (Bitfield-Mask: 0x1f)                            */
+ #define R_SCI0_LSR_ORER_Pos            (0UL)      /*!< ORER (Bit 0)                                          */
+ #define R_SCI0_LSR_ORER_Msk            (0x1UL)    /*!< ORER (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  CDR  ========================================================== */
+ #define R_SCI0_CDR_CMPD_Pos            (0UL)      /*!< CMPD (Bit 0)                                          */
+ #define R_SCI0_CDR_CMPD_Msk            (0x1ffUL)  /*!< CMPD (Bitfield-Mask: 0x1ff)                           */
+/* =========================================================  SPTR  ========================================================== */
+ #define R_SCI0_SPTR_SPB2IO_Pos         (2UL)      /*!< SPB2IO (Bit 2)                                        */
+ #define R_SCI0_SPTR_SPB2IO_Msk         (0x4UL)    /*!< SPB2IO (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_SPTR_SPB2DT_Pos         (1UL)      /*!< SPB2DT (Bit 1)                                        */
+ #define R_SCI0_SPTR_SPB2DT_Msk         (0x2UL)    /*!< SPB2DT (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_SPTR_RXDMON_Pos         (0UL)      /*!< RXDMON (Bit 0)                                        */
+ #define R_SCI0_SPTR_RXDMON_Msk         (0x1UL)    /*!< RXDMON (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_SPTR_RINV_Pos           (4UL)      /*!< RINV (Bit 4)                                          */
+ #define R_SCI0_SPTR_RINV_Msk           (0x10UL)   /*!< RINV (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SPTR_TINV_Pos           (5UL)      /*!< TINV (Bit 5)                                          */
+ #define R_SCI0_SPTR_TINV_Msk           (0x20UL)   /*!< TINV (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SPTR_ASEN_Pos           (6UL)      /*!< ASEN (Bit 6)                                          */
+ #define R_SCI0_SPTR_ASEN_Msk           (0x40UL)   /*!< ASEN (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SPTR_ATEN_Pos           (7UL)      /*!< ATEN (Bit 7)                                          */
+ #define R_SCI0_SPTR_ATEN_Msk           (0x80UL)   /*!< ATEN (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ACTR  ========================================================== */
+ #define R_SCI0_ACTR_AST_Pos            (0UL)      /*!< AST (Bit 0)                                           */
+ #define R_SCI0_ACTR_AST_Msk            (0x7UL)    /*!< AST (Bitfield-Mask: 0x07)                             */
+ #define R_SCI0_ACTR_AJD_Pos            (3UL)      /*!< AJD (Bit 3)                                           */
+ #define R_SCI0_ACTR_AJD_Msk            (0x8UL)    /*!< AJD (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_ACTR_ATT_Pos            (4UL)      /*!< ATT (Bit 4)                                           */
+ #define R_SCI0_ACTR_ATT_Msk            (0x70UL)   /*!< ATT (Bitfield-Mask: 0x07)                             */
+ #define R_SCI0_ACTR_AET_Pos            (7UL)      /*!< AET (Bit 7)                                           */
+ #define R_SCI0_ACTR_AET_Msk            (0x80UL)   /*!< AET (Bitfield-Mask: 0x01)                             */
+/* =========================================================  ESMER  ========================================================= */
+ #define R_SCI0_ESMER_ESME_Pos          (0UL)      /*!< ESME (Bit 0)                                          */
+ #define R_SCI0_ESMER_ESME_Msk          (0x1UL)    /*!< ESME (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  CR0  ========================================================== */
+ #define R_SCI0_CR0_SFSF_Pos            (1UL)      /*!< SFSF (Bit 1)                                          */
+ #define R_SCI0_CR0_SFSF_Msk            (0x2UL)    /*!< SFSF (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CR0_RXDSF_Pos           (2UL)      /*!< RXDSF (Bit 2)                                         */
+ #define R_SCI0_CR0_RXDSF_Msk           (0x4UL)    /*!< RXDSF (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_CR0_BRME_Pos            (3UL)      /*!< BRME (Bit 3)                                          */
+ #define R_SCI0_CR0_BRME_Msk            (0x8UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  CR1  ========================================================== */
+ #define R_SCI0_CR1_BFE_Pos             (0UL)      /*!< BFE (Bit 0)                                           */
+ #define R_SCI0_CR1_BFE_Msk             (0x1UL)    /*!< BFE (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_CR1_CF0RE_Pos           (1UL)      /*!< CF0RE (Bit 1)                                         */
+ #define R_SCI0_CR1_CF0RE_Msk           (0x2UL)    /*!< CF0RE (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_CR1_CF1DS_Pos           (2UL)      /*!< CF1DS (Bit 2)                                         */
+ #define R_SCI0_CR1_CF1DS_Msk           (0xcUL)    /*!< CF1DS (Bitfield-Mask: 0x03)                           */
+ #define R_SCI0_CR1_PIBE_Pos            (4UL)      /*!< PIBE (Bit 4)                                          */
+ #define R_SCI0_CR1_PIBE_Msk            (0x10UL)   /*!< PIBE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CR1_PIBS_Pos            (5UL)      /*!< PIBS (Bit 5)                                          */
+ #define R_SCI0_CR1_PIBS_Msk            (0xe0UL)   /*!< PIBS (Bitfield-Mask: 0x07)                            */
+/* ==========================================================  CR2  ========================================================== */
+ #define R_SCI0_CR2_DFCS_Pos            (0UL)      /*!< DFCS (Bit 0)                                          */
+ #define R_SCI0_CR2_DFCS_Msk            (0x7UL)    /*!< DFCS (Bitfield-Mask: 0x07)                            */
+ #define R_SCI0_CR2_BCCS_Pos            (4UL)      /*!< BCCS (Bit 4)                                          */
+ #define R_SCI0_CR2_BCCS_Msk            (0x30UL)   /*!< BCCS (Bitfield-Mask: 0x03)                            */
+ #define R_SCI0_CR2_RTS_Pos             (6UL)      /*!< RTS (Bit 6)                                           */
+ #define R_SCI0_CR2_RTS_Msk             (0xc0UL)   /*!< RTS (Bitfield-Mask: 0x03)                             */
+/* ==========================================================  CR3  ========================================================== */
+ #define R_SCI0_CR3_SDST_Pos            (0UL)      /*!< SDST (Bit 0)                                          */
+ #define R_SCI0_CR3_SDST_Msk            (0x1UL)    /*!< SDST (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  PCR  ========================================================== */
+ #define R_SCI0_PCR_TXDXPS_Pos          (0UL)      /*!< TXDXPS (Bit 0)                                        */
+ #define R_SCI0_PCR_TXDXPS_Msk          (0x1UL)    /*!< TXDXPS (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_PCR_RXDXPS_Pos          (1UL)      /*!< RXDXPS (Bit 1)                                        */
+ #define R_SCI0_PCR_RXDXPS_Msk          (0x2UL)    /*!< RXDXPS (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_PCR_SHARPS_Pos          (4UL)      /*!< SHARPS (Bit 4)                                        */
+ #define R_SCI0_PCR_SHARPS_Msk          (0x10UL)   /*!< SHARPS (Bitfield-Mask: 0x01)                          */
+/* ==========================================================  ICR  ========================================================== */
+ #define R_SCI0_ICR_BFDIE_Pos           (0UL)      /*!< BFDIE (Bit 0)                                         */
+ #define R_SCI0_ICR_BFDIE_Msk           (0x1UL)    /*!< BFDIE (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_ICR_CF0MIE_Pos          (1UL)      /*!< CF0MIE (Bit 1)                                        */
+ #define R_SCI0_ICR_CF0MIE_Msk          (0x2UL)    /*!< CF0MIE (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_ICR_CF1MIE_Pos          (2UL)      /*!< CF1MIE (Bit 2)                                        */
+ #define R_SCI0_ICR_CF1MIE_Msk          (0x4UL)    /*!< CF1MIE (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_ICR_PIBDIE_Pos          (3UL)      /*!< PIBDIE (Bit 3)                                        */
+ #define R_SCI0_ICR_PIBDIE_Msk          (0x8UL)    /*!< PIBDIE (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_ICR_BCDIE_Pos           (4UL)      /*!< BCDIE (Bit 4)                                         */
+ #define R_SCI0_ICR_BCDIE_Msk           (0x10UL)   /*!< BCDIE (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_ICR_AEDIE_Pos           (5UL)      /*!< AEDIE (Bit 5)                                         */
+ #define R_SCI0_ICR_AEDIE_Msk           (0x20UL)   /*!< AEDIE (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  STR  ========================================================== */
+ #define R_SCI0_STR_BFDF_Pos            (0UL)      /*!< BFDF (Bit 0)                                          */
+ #define R_SCI0_STR_BFDF_Msk            (0x1UL)    /*!< BFDF (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_STR_CF0MF_Pos           (1UL)      /*!< CF0MF (Bit 1)                                         */
+ #define R_SCI0_STR_CF0MF_Msk           (0x2UL)    /*!< CF0MF (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_STR_CF1MF_Pos           (2UL)      /*!< CF1MF (Bit 2)                                         */
+ #define R_SCI0_STR_CF1MF_Msk           (0x4UL)    /*!< CF1MF (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_STR_PIBDF_Pos           (3UL)      /*!< PIBDF (Bit 3)                                         */
+ #define R_SCI0_STR_PIBDF_Msk           (0x8UL)    /*!< PIBDF (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_STR_BCDF_Pos            (4UL)      /*!< BCDF (Bit 4)                                          */
+ #define R_SCI0_STR_BCDF_Msk            (0x10UL)   /*!< BCDF (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_STR_AEDF_Pos            (5UL)      /*!< AEDF (Bit 5)                                          */
+ #define R_SCI0_STR_AEDF_Msk            (0x20UL)   /*!< AEDF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  STCR  ========================================================== */
+ #define R_SCI0_STCR_BFDCL_Pos          (0UL)      /*!< BFDCL (Bit 0)                                         */
+ #define R_SCI0_STCR_BFDCL_Msk          (0x1UL)    /*!< BFDCL (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_STCR_CF0MCL_Pos         (1UL)      /*!< CF0MCL (Bit 1)                                        */
+ #define R_SCI0_STCR_CF0MCL_Msk         (0x2UL)    /*!< CF0MCL (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_STCR_CF1MCL_Pos         (2UL)      /*!< CF1MCL (Bit 2)                                        */
+ #define R_SCI0_STCR_CF1MCL_Msk         (0x4UL)    /*!< CF1MCL (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_STCR_PIBDCL_Pos         (3UL)      /*!< PIBDCL (Bit 3)                                        */
+ #define R_SCI0_STCR_PIBDCL_Msk         (0x8UL)    /*!< PIBDCL (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_STCR_BCDCL_Pos          (4UL)      /*!< BCDCL (Bit 4)                                         */
+ #define R_SCI0_STCR_BCDCL_Msk          (0x10UL)   /*!< BCDCL (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_STCR_AEDCL_Pos          (5UL)      /*!< AEDCL (Bit 5)                                         */
+ #define R_SCI0_STCR_AEDCL_Msk          (0x20UL)   /*!< AEDCL (Bitfield-Mask: 0x01)                           */
+/* =========================================================  CF0DR  ========================================================= */
+/* =========================================================  CF0CR  ========================================================= */
+ #define R_SCI0_CF0CR_CF0CE0_Pos        (0UL)      /*!< CF0CE0 (Bit 0)                                        */
+ #define R_SCI0_CF0CR_CF0CE0_Msk        (0x1UL)    /*!< CF0CE0 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF0CR_CF0CE1_Pos        (1UL)      /*!< CF0CE1 (Bit 1)                                        */
+ #define R_SCI0_CF0CR_CF0CE1_Msk        (0x2UL)    /*!< CF0CE1 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF0CR_CF0CE2_Pos        (2UL)      /*!< CF0CE2 (Bit 2)                                        */
+ #define R_SCI0_CF0CR_CF0CE2_Msk        (0x4UL)    /*!< CF0CE2 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF0CR_CF0CE3_Pos        (3UL)      /*!< CF0CE3 (Bit 3)                                        */
+ #define R_SCI0_CF0CR_CF0CE3_Msk        (0x8UL)    /*!< CF0CE3 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF0CR_CF0CE4_Pos        (4UL)      /*!< CF0CE4 (Bit 4)                                        */
+ #define R_SCI0_CF0CR_CF0CE4_Msk        (0x10UL)   /*!< CF0CE4 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF0CR_CF0CE5_Pos        (5UL)      /*!< CF0CE5 (Bit 5)                                        */
+ #define R_SCI0_CF0CR_CF0CE5_Msk        (0x20UL)   /*!< CF0CE5 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF0CR_CF0CE6_Pos        (6UL)      /*!< CF0CE6 (Bit 6)                                        */
+ #define R_SCI0_CF0CR_CF0CE6_Msk        (0x40UL)   /*!< CF0CE6 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF0CR_CF0CE7_Pos        (7UL)      /*!< CF0CE7 (Bit 7)                                        */
+ #define R_SCI0_CF0CR_CF0CE7_Msk        (0x80UL)   /*!< CF0CE7 (Bitfield-Mask: 0x01)                          */
+/* =========================================================  CF0RR  ========================================================= */
+/* ========================================================  PCF1DR  ========================================================= */
+/* ========================================================  SCF1DR  ========================================================= */
+/* =========================================================  CF1CR  ========================================================= */
+ #define R_SCI0_CF1CR_CF1CE0_Pos        (0UL)    /*!< CF1CE0 (Bit 0)                                        */
+ #define R_SCI0_CF1CR_CF1CE0_Msk        (0x1UL)  /*!< CF1CE0 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF1CR_CF1CE1_Pos        (1UL)    /*!< CF1CE1 (Bit 1)                                        */
+ #define R_SCI0_CF1CR_CF1CE1_Msk        (0x2UL)  /*!< CF1CE1 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF1CR_CF1CE2_Pos        (2UL)    /*!< CF1CE2 (Bit 2)                                        */
+ #define R_SCI0_CF1CR_CF1CE2_Msk        (0x4UL)  /*!< CF1CE2 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF1CR_CF1CE3_Pos        (3UL)    /*!< CF1CE3 (Bit 3)                                        */
+ #define R_SCI0_CF1CR_CF1CE3_Msk        (0x8UL)  /*!< CF1CE3 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF1CR_CF1CE4_Pos        (4UL)    /*!< CF1CE4 (Bit 4)                                        */
+ #define R_SCI0_CF1CR_CF1CE4_Msk        (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF1CR_CF1CE5_Pos        (5UL)    /*!< CF1CE5 (Bit 5)                                        */
+ #define R_SCI0_CF1CR_CF1CE5_Msk        (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF1CR_CF1CE6_Pos        (6UL)    /*!< CF1CE6 (Bit 6)                                        */
+ #define R_SCI0_CF1CR_CF1CE6_Msk        (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF1CR_CF1CE7_Pos        (7UL)    /*!< CF1CE7 (Bit 7)                                        */
+ #define R_SCI0_CF1CR_CF1CE7_Msk        (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01)                          */
+/* =========================================================  CF1RR  ========================================================= */
+/* ==========================================================  TCR  ========================================================== */
+ #define R_SCI0_TCR_TCST_Pos            (0UL)    /*!< TCST (Bit 0)                                          */
+ #define R_SCI0_TCR_TCST_Msk            (0x1UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  TMR  ========================================================== */
+ #define R_SCI0_TMR_TOMS_Pos            (0UL)    /*!< TOMS (Bit 0)                                          */
+ #define R_SCI0_TMR_TOMS_Msk            (0x3UL)  /*!< TOMS (Bitfield-Mask: 0x03)                            */
+ #define R_SCI0_TMR_TWRC_Pos            (3UL)    /*!< TWRC (Bit 3)                                          */
+ #define R_SCI0_TMR_TWRC_Msk            (0x8UL)  /*!< TWRC (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_TMR_TCSS_Pos            (4UL)    /*!< TCSS (Bit 4)                                          */
+ #define R_SCI0_TMR_TCSS_Msk            (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07)                            */
+/* =========================================================  TPRE  ========================================================== */
+/* =========================================================  TCNT  ========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SPI0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SPCR  ========================================================== */
+ #define R_SPI0_SPCR_SPRIE_Pos      (7UL)    /*!< SPRIE (Bit 7)                                         */
+ #define R_SPI0_SPCR_SPRIE_Msk      (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR_SPE_Pos        (6UL)    /*!< SPE (Bit 6)                                           */
+ #define R_SPI0_SPCR_SPE_Msk        (0x40UL) /*!< SPE (Bitfield-Mask: 0x01)                             */
+ #define R_SPI0_SPCR_SPTIE_Pos      (5UL)    /*!< SPTIE (Bit 5)                                         */
+ #define R_SPI0_SPCR_SPTIE_Msk      (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR_SPEIE_Pos      (4UL)    /*!< SPEIE (Bit 4)                                         */
+ #define R_SPI0_SPCR_SPEIE_Msk      (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR_MSTR_Pos       (3UL)    /*!< MSTR (Bit 3)                                          */
+ #define R_SPI0_SPCR_MSTR_Msk       (0x8UL)  /*!< MSTR (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR_MODFEN_Pos     (2UL)    /*!< MODFEN (Bit 2)                                        */
+ #define R_SPI0_SPCR_MODFEN_Msk     (0x4UL)  /*!< MODFEN (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCR_TXMD_Pos       (1UL)    /*!< TXMD (Bit 1)                                          */
+ #define R_SPI0_SPCR_TXMD_Msk       (0x2UL)  /*!< TXMD (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR_SPMS_Pos       (0UL)    /*!< SPMS (Bit 0)                                          */
+ #define R_SPI0_SPCR_SPMS_Msk       (0x1UL)  /*!< SPMS (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SSLP  ========================================================== */
+ #define R_SPI0_SSLP_SSL3P_Pos      (3UL)    /*!< SSL3P (Bit 3)                                         */
+ #define R_SPI0_SSLP_SSL3P_Msk      (0x8UL)  /*!< SSL3P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL2P_Pos      (2UL)    /*!< SSL2P (Bit 2)                                         */
+ #define R_SPI0_SSLP_SSL2P_Msk      (0x4UL)  /*!< SSL2P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL1P_Pos      (1UL)    /*!< SSL1P (Bit 1)                                         */
+ #define R_SPI0_SSLP_SSL1P_Msk      (0x2UL)  /*!< SSL1P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL0P_Pos      (0UL)    /*!< SSL0P (Bit 0)                                         */
+ #define R_SPI0_SSLP_SSL0P_Msk      (0x1UL)  /*!< SSL0P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL4P_Pos      (4UL)    /*!< SSL4P (Bit 4)                                         */
+ #define R_SPI0_SSLP_SSL4P_Msk      (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL5P_Pos      (5UL)    /*!< SSL5P (Bit 5)                                         */
+ #define R_SPI0_SSLP_SSL5P_Msk      (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL6P_Pos      (6UL)    /*!< SSL6P (Bit 6)                                         */
+ #define R_SPI0_SSLP_SSL6P_Msk      (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL7P_Pos      (7UL)    /*!< SSL7P (Bit 7)                                         */
+ #define R_SPI0_SSLP_SSL7P_Msk      (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SPPCR  ========================================================= */
+ #define R_SPI0_SPPCR_MOIFE_Pos     (5UL)    /*!< MOIFE (Bit 5)                                         */
+ #define R_SPI0_SPPCR_MOIFE_Msk     (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPPCR_MOIFV_Pos     (4UL)    /*!< MOIFV (Bit 4)                                         */
+ #define R_SPI0_SPPCR_MOIFV_Msk     (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPPCR_SPLP2_Pos     (1UL)    /*!< SPLP2 (Bit 1)                                         */
+ #define R_SPI0_SPPCR_SPLP2_Msk     (0x2UL)  /*!< SPLP2 (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPPCR_SPLP_Pos      (0UL)    /*!< SPLP (Bit 0)                                          */
+ #define R_SPI0_SPPCR_SPLP_Msk      (0x1UL)  /*!< SPLP (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SPSR  ========================================================== */
+ #define R_SPI0_SPSR_SPRF_Pos       (7UL)    /*!< SPRF (Bit 7)                                          */
+ #define R_SPI0_SPSR_SPRF_Msk       (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_SPTEF_Pos      (5UL)    /*!< SPTEF (Bit 5)                                         */
+ #define R_SPI0_SPSR_SPTEF_Msk      (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSR_UDRF_Pos       (4UL)    /*!< UDRF (Bit 4)                                          */
+ #define R_SPI0_SPSR_UDRF_Msk       (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_PERF_Pos       (3UL)    /*!< PERF (Bit 3)                                          */
+ #define R_SPI0_SPSR_PERF_Msk       (0x8UL)  /*!< PERF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_MODF_Pos       (2UL)    /*!< MODF (Bit 2)                                          */
+ #define R_SPI0_SPSR_MODF_Msk       (0x4UL)  /*!< MODF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_IDLNF_Pos      (1UL)    /*!< IDLNF (Bit 1)                                         */
+ #define R_SPI0_SPSR_IDLNF_Msk      (0x2UL)  /*!< IDLNF (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSR_OVRF_Pos       (0UL)    /*!< OVRF (Bit 0)                                          */
+ #define R_SPI0_SPSR_OVRF_Msk       (0x1UL)  /*!< OVRF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_CENDF_Pos      (6UL)    /*!< CENDF (Bit 6)                                         */
+ #define R_SPI0_SPSR_CENDF_Msk      (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SPDR  ========================================================== */
+/* ========================================================  SPDR_HA  ======================================================== */
+/* ========================================================  SPDR_BY  ======================================================== */
+/* =========================================================  SPSCR  ========================================================= */
+ #define R_SPI0_SPSCR_SPSLN_Pos     (0UL)      /*!< SPSLN (Bit 0)                                         */
+ #define R_SPI0_SPSCR_SPSLN_Msk     (0x7UL)    /*!< SPSLN (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SPBR  ========================================================== */
+ #define R_SPI0_SPBR_SPR_Pos        (0UL)      /*!< SPR (Bit 0)                                           */
+ #define R_SPI0_SPBR_SPR_Msk        (0xffUL)   /*!< SPR (Bitfield-Mask: 0xff)                             */
+/* =========================================================  SPDCR  ========================================================= */
+ #define R_SPI0_SPDCR_SPBYT_Pos     (6UL)      /*!< SPBYT (Bit 6)                                         */
+ #define R_SPI0_SPDCR_SPBYT_Msk     (0x40UL)   /*!< SPBYT (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPDCR_SPLW_Pos      (5UL)      /*!< SPLW (Bit 5)                                          */
+ #define R_SPI0_SPDCR_SPLW_Msk      (0x20UL)   /*!< SPLW (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPDCR_SPRDTD_Pos    (4UL)      /*!< SPRDTD (Bit 4)                                        */
+ #define R_SPI0_SPDCR_SPRDTD_Msk    (0x10UL)   /*!< SPRDTD (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPDCR_SPFC_Pos      (0UL)      /*!< SPFC (Bit 0)                                          */
+ #define R_SPI0_SPDCR_SPFC_Msk      (0x3UL)    /*!< SPFC (Bitfield-Mask: 0x03)                            */
+ #define R_SPI0_SPDCR_SLSEL_Pos     (2UL)      /*!< SLSEL (Bit 2)                                         */
+ #define R_SPI0_SPDCR_SLSEL_Msk     (0xcUL)    /*!< SLSEL (Bitfield-Mask: 0x03)                           */
+/* =========================================================  SPCKD  ========================================================= */
+ #define R_SPI0_SPCKD_SCKDL_Pos     (0UL)      /*!< SCKDL (Bit 0)                                         */
+ #define R_SPI0_SPCKD_SCKDL_Msk     (0x7UL)    /*!< SCKDL (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SSLND  ========================================================= */
+ #define R_SPI0_SSLND_SLNDL_Pos     (0UL)      /*!< SLNDL (Bit 0)                                         */
+ #define R_SPI0_SSLND_SLNDL_Msk     (0x7UL)    /*!< SLNDL (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SPND  ========================================================== */
+ #define R_SPI0_SPND_SPNDL_Pos      (0UL)      /*!< SPNDL (Bit 0)                                         */
+ #define R_SPI0_SPND_SPNDL_Msk      (0x7UL)    /*!< SPNDL (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SPCR2  ========================================================= */
+ #define R_SPI0_SPCR2_SCKASE_Pos    (4UL)      /*!< SCKASE (Bit 4)                                        */
+ #define R_SPI0_SPCR2_SCKASE_Msk    (0x10UL)   /*!< SCKASE (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCR2_PTE_Pos       (3UL)      /*!< PTE (Bit 3)                                           */
+ #define R_SPI0_SPCR2_PTE_Msk       (0x8UL)    /*!< PTE (Bitfield-Mask: 0x01)                             */
+ #define R_SPI0_SPCR2_SPIIE_Pos     (2UL)      /*!< SPIIE (Bit 2)                                         */
+ #define R_SPI0_SPCR2_SPIIE_Msk     (0x4UL)    /*!< SPIIE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR2_SPOE_Pos      (1UL)      /*!< SPOE (Bit 1)                                          */
+ #define R_SPI0_SPCR2_SPOE_Msk      (0x2UL)    /*!< SPOE (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR2_SPPE_Pos      (0UL)      /*!< SPPE (Bit 0)                                          */
+ #define R_SPI0_SPCR2_SPPE_Msk      (0x1UL)    /*!< SPPE (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR2_SPTDDL_Pos    (5UL)      /*!< SPTDDL (Bit 5)                                        */
+ #define R_SPI0_SPCR2_SPTDDL_Msk    (0xe0UL)   /*!< SPTDDL (Bitfield-Mask: 0x07)                          */
+/* =========================================================  SPCMD  ========================================================= */
+ #define R_SPI0_SPCMD_SCKDEN_Pos    (15UL)     /*!< SCKDEN (Bit 15)                                       */
+ #define R_SPI0_SPCMD_SCKDEN_Msk    (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCMD_SLNDEN_Pos    (14UL)     /*!< SLNDEN (Bit 14)                                       */
+ #define R_SPI0_SPCMD_SLNDEN_Msk    (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCMD_SPNDEN_Pos    (13UL)     /*!< SPNDEN (Bit 13)                                       */
+ #define R_SPI0_SPCMD_SPNDEN_Msk    (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCMD_LSBF_Pos      (12UL)     /*!< LSBF (Bit 12)                                         */
+ #define R_SPI0_SPCMD_LSBF_Msk      (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCMD_SPB_Pos       (8UL)      /*!< SPB (Bit 8)                                           */
+ #define R_SPI0_SPCMD_SPB_Msk       (0xf00UL)  /*!< SPB (Bitfield-Mask: 0x0f)                             */
+ #define R_SPI0_SPCMD_SSLKP_Pos     (7UL)      /*!< SSLKP (Bit 7)                                         */
+ #define R_SPI0_SPCMD_SSLKP_Msk     (0x80UL)   /*!< SSLKP (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCMD_SSLA_Pos      (4UL)      /*!< SSLA (Bit 4)                                          */
+ #define R_SPI0_SPCMD_SSLA_Msk      (0x70UL)   /*!< SSLA (Bitfield-Mask: 0x07)                            */
+ #define R_SPI0_SPCMD_BRDV_Pos      (2UL)      /*!< BRDV (Bit 2)                                          */
+ #define R_SPI0_SPCMD_BRDV_Msk      (0xcUL)    /*!< BRDV (Bitfield-Mask: 0x03)                            */
+ #define R_SPI0_SPCMD_CPOL_Pos      (1UL)      /*!< CPOL (Bit 1)                                          */
+ #define R_SPI0_SPCMD_CPOL_Msk      (0x2UL)    /*!< CPOL (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCMD_CPHA_Pos      (0UL)      /*!< CPHA (Bit 0)                                          */
+ #define R_SPI0_SPCMD_CPHA_Msk      (0x1UL)    /*!< CPHA (Bitfield-Mask: 0x01)                            */
+/* ========================================================  SPDCR2  ========================================================= */
+ #define R_SPI0_SPDCR2_BYSW_Pos     (0UL)      /*!< BYSW (Bit 0)                                          */
+ #define R_SPI0_SPDCR2_BYSW_Msk     (0x1UL)    /*!< BYSW (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPDCR2_SINV_Pos     (1UL)      /*!< SINV (Bit 1)                                          */
+ #define R_SPI0_SPDCR2_SINV_Msk     (0x2UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SPSSR  ========================================================= */
+ #define R_SPI0_SPSSR_SPCP_Pos      (0UL)      /*!< SPCP (Bit 0)                                          */
+ #define R_SPI0_SPSSR_SPCP_Msk      (0x7UL)    /*!< SPCP (Bitfield-Mask: 0x07)                            */
+ #define R_SPI0_SPSSR_SPECM_Pos     (4UL)      /*!< SPECM (Bit 4)                                         */
+ #define R_SPI0_SPSSR_SPECM_Msk     (0x70UL)   /*!< SPECM (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SPCR3  ========================================================= */
+ #define R_SPI0_SPCR3_ETXMD_Pos     (0UL)      /*!< ETXMD (Bit 0)                                         */
+ #define R_SPI0_SPCR3_ETXMD_Msk     (0x1UL)    /*!< ETXMD (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR3_BFDS_Pos      (1UL)      /*!< BFDS (Bit 1)                                          */
+ #define R_SPI0_SPCR3_BFDS_Msk      (0x2UL)    /*!< BFDS (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR3_CENDIE_Pos    (4UL)      /*!< CENDIE (Bit 4)                                        */
+ #define R_SPI0_SPCR3_CENDIE_Msk    (0x10UL)   /*!< CENDIE (Bitfield-Mask: 0x01)                          */
+/* =========================================================  SPPR  ========================================================== */
+ #define R_SPI0_SPPR_BUFWID_Pos     (4UL)      /*!< BUFWID (Bit 4)                                        */
+ #define R_SPI0_SPPR_BUFWID_Msk     (0x10UL)   /*!< BUFWID (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPPR_BUFNUM_Pos     (8UL)      /*!< BUFNUM (Bit 8)                                        */
+ #define R_SPI0_SPPR_BUFNUM_Msk     (0x700UL)  /*!< BUFNUM (Bitfield-Mask: 0x07)                          */
+ #define R_SPI0_SPPR_CMDNUM_Pos     (12UL)     /*!< CMDNUM (Bit 12)                                       */
+ #define R_SPI0_SPPR_CMDNUM_Msk     (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f)                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SRAM                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  PARIOAD  ======================================================== */
+ #define R_SRAM_PARIOAD_OAD_Pos            (0UL)    /*!< OAD (Bit 0)                                           */
+ #define R_SRAM_PARIOAD_OAD_Msk            (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
+/* =======================================================  SRAMPRCR  ======================================================== */
+ #define R_SRAM_SRAMPRCR_KW_Pos            (1UL)    /*!< KW (Bit 1)                                            */
+ #define R_SRAM_SRAMPRCR_KW_Msk            (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
+ #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos      (0UL)    /*!< SRAMPRCR (Bit 0)                                      */
+ #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk      (0x1UL)  /*!< SRAMPRCR (Bitfield-Mask: 0x01)                        */
+/* =======================================================  SRAMWTSC  ======================================================== */
+/* ========================================================  ECCMODE  ======================================================== */
+ #define R_SRAM_ECCMODE_ECCMOD_Pos         (0UL)    /*!< ECCMOD (Bit 0)                                        */
+ #define R_SRAM_ECCMODE_ECCMOD_Msk         (0x3UL)  /*!< ECCMOD (Bitfield-Mask: 0x03)                          */
+/* ========================================================  ECC2STS  ======================================================== */
+ #define R_SRAM_ECC2STS_ECC2ERR_Pos        (0UL)    /*!< ECC2ERR (Bit 0)                                       */
+ #define R_SRAM_ECC2STS_ECC2ERR_Msk        (0x1UL)  /*!< ECC2ERR (Bitfield-Mask: 0x01)                         */
+/* =======================================================  ECC1STSEN  ======================================================= */
+ #define R_SRAM_ECC1STSEN_E1STSEN_Pos      (0UL)    /*!< E1STSEN (Bit 0)                                       */
+ #define R_SRAM_ECC1STSEN_E1STSEN_Msk      (0x1UL)  /*!< E1STSEN (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ECC1STS  ======================================================== */
+ #define R_SRAM_ECC1STS_ECC1ERR_Pos        (0UL)    /*!< ECC1ERR (Bit 0)                                       */
+ #define R_SRAM_ECC1STS_ECC1ERR_Msk        (0x1UL)  /*!< ECC1ERR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ECCPRCR  ======================================================== */
+ #define R_SRAM_ECCPRCR_KW_Pos             (1UL)    /*!< KW (Bit 1)                                            */
+ #define R_SRAM_ECCPRCR_KW_Msk             (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
+ #define R_SRAM_ECCPRCR_ECCPRCR_Pos        (0UL)    /*!< ECCPRCR (Bit 0)                                       */
+ #define R_SRAM_ECCPRCR_ECCPRCR_Msk        (0x1UL)  /*!< ECCPRCR (Bitfield-Mask: 0x01)                         */
+/* =======================================================  ECCPRCR2  ======================================================== */
+ #define R_SRAM_ECCPRCR2_KW2_Pos           (1UL)    /*!< KW2 (Bit 1)                                           */
+ #define R_SRAM_ECCPRCR2_KW2_Msk           (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f)                             */
+ #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos      (0UL)    /*!< ECCPRCR2 (Bit 0)                                      */
+ #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk      (0x1UL)  /*!< ECCPRCR2 (Bitfield-Mask: 0x01)                        */
+/* ========================================================  ECCETST  ======================================================== */
+ #define R_SRAM_ECCETST_TSTBYP_Pos         (0UL)    /*!< TSTBYP (Bit 0)                                        */
+ #define R_SRAM_ECCETST_TSTBYP_Msk         (0x1UL)  /*!< TSTBYP (Bitfield-Mask: 0x01)                          */
+/* ========================================================  ECCOAD  ========================================================= */
+ #define R_SRAM_ECCOAD_OAD_Pos             (0UL)    /*!< OAD (Bit 0)                                           */
+ #define R_SRAM_ECCOAD_OAD_Msk             (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
+/* =======================================================  SRAMPRCR2  ======================================================= */
+ #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos    (0UL)    /*!< SRAMPRCR2 (Bit 0)                                     */
+ #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk    (0x1UL)  /*!< SRAMPRCR2 (Bitfield-Mask: 0x01)                       */
+ #define R_SRAM_SRAMPRCR2_KW_Pos           (1UL)    /*!< KW (Bit 1)                                            */
+ #define R_SRAM_SRAMPRCR2_KW_Msk           (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SSI0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SSICR  ========================================================= */
+ #define R_SSI0_SSICR_CKS_Pos          (30UL)         /*!< CKS (Bit 30)                                          */
+ #define R_SSI0_SSICR_CKS_Msk          (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSICR_TUIEN_Pos        (29UL)         /*!< TUIEN (Bit 29)                                        */
+ #define R_SSI0_SSICR_TUIEN_Msk        (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSICR_TOIEN_Pos        (28UL)         /*!< TOIEN (Bit 28)                                        */
+ #define R_SSI0_SSICR_TOIEN_Msk        (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSICR_RUIEN_Pos        (27UL)         /*!< RUIEN (Bit 27)                                        */
+ #define R_SSI0_SSICR_RUIEN_Msk        (0x8000000UL)  /*!< RUIEN (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSICR_ROIEN_Pos        (26UL)         /*!< ROIEN (Bit 26)                                        */
+ #define R_SSI0_SSICR_ROIEN_Msk        (0x4000000UL)  /*!< ROIEN (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSICR_IIEN_Pos         (25UL)         /*!< IIEN (Bit 25)                                         */
+ #define R_SSI0_SSICR_IIEN_Msk         (0x2000000UL)  /*!< IIEN (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSICR_FRM_Pos          (22UL)         /*!< FRM (Bit 22)                                          */
+ #define R_SSI0_SSICR_FRM_Msk          (0xc00000UL)   /*!< FRM (Bitfield-Mask: 0x03)                             */
+ #define R_SSI0_SSICR_DWL_Pos          (19UL)         /*!< DWL (Bit 19)                                          */
+ #define R_SSI0_SSICR_DWL_Msk          (0x380000UL)   /*!< DWL (Bitfield-Mask: 0x07)                             */
+ #define R_SSI0_SSICR_SWL_Pos          (16UL)         /*!< SWL (Bit 16)                                          */
+ #define R_SSI0_SSICR_SWL_Msk          (0x70000UL)    /*!< SWL (Bitfield-Mask: 0x07)                             */
+ #define R_SSI0_SSICR_MST_Pos          (14UL)         /*!< MST (Bit 14)                                          */
+ #define R_SSI0_SSICR_MST_Msk          (0x4000UL)     /*!< MST (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSICR_BCKP_Pos         (13UL)         /*!< BCKP (Bit 13)                                         */
+ #define R_SSI0_SSICR_BCKP_Msk         (0x2000UL)     /*!< BCKP (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSICR_LRCKP_Pos        (12UL)         /*!< LRCKP (Bit 12)                                        */
+ #define R_SSI0_SSICR_LRCKP_Msk        (0x1000UL)     /*!< LRCKP (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSICR_SPDP_Pos         (11UL)         /*!< SPDP (Bit 11)                                         */
+ #define R_SSI0_SSICR_SPDP_Msk         (0x800UL)      /*!< SPDP (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSICR_SDTA_Pos         (10UL)         /*!< SDTA (Bit 10)                                         */
+ #define R_SSI0_SSICR_SDTA_Msk         (0x400UL)      /*!< SDTA (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSICR_PDTA_Pos         (9UL)          /*!< PDTA (Bit 9)                                          */
+ #define R_SSI0_SSICR_PDTA_Msk         (0x200UL)      /*!< PDTA (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSICR_DEL_Pos          (8UL)          /*!< DEL (Bit 8)                                           */
+ #define R_SSI0_SSICR_DEL_Msk          (0x100UL)      /*!< DEL (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSICR_CKDV_Pos         (4UL)          /*!< CKDV (Bit 4)                                          */
+ #define R_SSI0_SSICR_CKDV_Msk         (0xf0UL)       /*!< CKDV (Bitfield-Mask: 0x0f)                            */
+ #define R_SSI0_SSICR_MUEN_Pos         (3UL)          /*!< MUEN (Bit 3)                                          */
+ #define R_SSI0_SSICR_MUEN_Msk         (0x8UL)        /*!< MUEN (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSICR_TEN_Pos          (1UL)          /*!< TEN (Bit 1)                                           */
+ #define R_SSI0_SSICR_TEN_Msk          (0x2UL)        /*!< TEN (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSICR_REN_Pos          (0UL)          /*!< REN (Bit 0)                                           */
+ #define R_SSI0_SSICR_REN_Msk          (0x1UL)        /*!< REN (Bitfield-Mask: 0x01)                             */
+/* =========================================================  SSISR  ========================================================= */
+ #define R_SSI0_SSISR_TUIRQ_Pos        (29UL)         /*!< TUIRQ (Bit 29)                                        */
+ #define R_SSI0_SSISR_TUIRQ_Msk        (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSISR_TOIRQ_Pos        (28UL)         /*!< TOIRQ (Bit 28)                                        */
+ #define R_SSI0_SSISR_TOIRQ_Msk        (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSISR_RUIRQ_Pos        (27UL)         /*!< RUIRQ (Bit 27)                                        */
+ #define R_SSI0_SSISR_RUIRQ_Msk        (0x8000000UL)  /*!< RUIRQ (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSISR_ROIRQ_Pos        (26UL)         /*!< ROIRQ (Bit 26)                                        */
+ #define R_SSI0_SSISR_ROIRQ_Msk        (0x4000000UL)  /*!< ROIRQ (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSISR_IIRQ_Pos         (25UL)         /*!< IIRQ (Bit 25)                                         */
+ #define R_SSI0_SSISR_IIRQ_Msk         (0x2000000UL)  /*!< IIRQ (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSISR_TCHNO_Pos        (5UL)          /*!< TCHNO (Bit 5)                                         */
+ #define R_SSI0_SSISR_TCHNO_Msk        (0x60UL)       /*!< TCHNO (Bitfield-Mask: 0x03)                           */
+ #define R_SSI0_SSISR_TSWNO_Pos        (4UL)          /*!< TSWNO (Bit 4)                                         */
+ #define R_SSI0_SSISR_TSWNO_Msk        (0x10UL)       /*!< TSWNO (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSISR_RCHNO_Pos        (2UL)          /*!< RCHNO (Bit 2)                                         */
+ #define R_SSI0_SSISR_RCHNO_Msk        (0xcUL)        /*!< RCHNO (Bitfield-Mask: 0x03)                           */
+ #define R_SSI0_SSISR_RSWNO_Pos        (1UL)          /*!< RSWNO (Bit 1)                                         */
+ #define R_SSI0_SSISR_RSWNO_Msk        (0x2UL)        /*!< RSWNO (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSISR_IDST_Pos         (0UL)          /*!< IDST (Bit 0)                                          */
+ #define R_SSI0_SSISR_IDST_Msk         (0x1UL)        /*!< IDST (Bitfield-Mask: 0x01)                            */
+/* ========================================================  SSIFCR  ========================================================= */
+ #define R_SSI0_SSIFCR_AUCKE_Pos       (31UL)         /*!< AUCKE (Bit 31)                                        */
+ #define R_SSI0_SSIFCR_AUCKE_Msk       (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSIFCR_SSIRST_Pos      (16UL)         /*!< SSIRST (Bit 16)                                       */
+ #define R_SSI0_SSIFCR_SSIRST_Msk      (0x10000UL)    /*!< SSIRST (Bitfield-Mask: 0x01)                          */
+ #define R_SSI0_SSIFCR_TTRG_Pos        (6UL)          /*!< TTRG (Bit 6)                                          */
+ #define R_SSI0_SSIFCR_TTRG_Msk        (0xc0UL)       /*!< TTRG (Bitfield-Mask: 0x03)                            */
+ #define R_SSI0_SSIFCR_RTRG_Pos        (4UL)          /*!< RTRG (Bit 4)                                          */
+ #define R_SSI0_SSIFCR_RTRG_Msk        (0x30UL)       /*!< RTRG (Bitfield-Mask: 0x03)                            */
+ #define R_SSI0_SSIFCR_TIE_Pos         (3UL)          /*!< TIE (Bit 3)                                           */
+ #define R_SSI0_SSIFCR_TIE_Msk         (0x8UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSIFCR_RIE_Pos         (2UL)          /*!< RIE (Bit 2)                                           */
+ #define R_SSI0_SSIFCR_RIE_Msk         (0x4UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSIFCR_TFRST_Pos       (1UL)          /*!< TFRST (Bit 1)                                         */
+ #define R_SSI0_SSIFCR_TFRST_Msk       (0x2UL)        /*!< TFRST (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSIFCR_RFRST_Pos       (0UL)          /*!< RFRST (Bit 0)                                         */
+ #define R_SSI0_SSIFCR_RFRST_Msk       (0x1UL)        /*!< RFRST (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSIFCR_BSW_Pos         (11UL)         /*!< BSW (Bit 11)                                          */
+ #define R_SSI0_SSIFCR_BSW_Msk         (0x800UL)      /*!< BSW (Bitfield-Mask: 0x01)                             */
+/* ========================================================  SSIFSR  ========================================================= */
+ #define R_SSI0_SSIFSR_TDC_Pos         (24UL)         /*!< TDC (Bit 24)                                          */
+ #define R_SSI0_SSIFSR_TDC_Msk         (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f)                             */
+ #define R_SSI0_SSIFSR_TDE_Pos         (16UL)         /*!< TDE (Bit 16)                                          */
+ #define R_SSI0_SSIFSR_TDE_Msk         (0x10000UL)    /*!< TDE (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSIFSR_RDC_Pos         (8UL)          /*!< RDC (Bit 8)                                           */
+ #define R_SSI0_SSIFSR_RDC_Msk         (0x3f00UL)     /*!< RDC (Bitfield-Mask: 0x3f)                             */
+ #define R_SSI0_SSIFSR_RDF_Pos         (0UL)          /*!< RDF (Bit 0)                                           */
+ #define R_SSI0_SSIFSR_RDF_Msk         (0x1UL)        /*!< RDF (Bitfield-Mask: 0x01)                             */
+/* ========================================================  SSIFTDR  ======================================================== */
+ #define R_SSI0_SSIFTDR_SSIFTDR_Pos    (0UL)          /*!< SSIFTDR (Bit 0)                                       */
+ #define R_SSI0_SSIFTDR_SSIFTDR_Msk    (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff)                   */
+/* =======================================================  SSIFTDR16  ======================================================= */
+/* =======================================================  SSIFTDR8  ======================================================== */
+/* ========================================================  SSIFRDR  ======================================================== */
+ #define R_SSI0_SSIFRDR_SSIFRDR_Pos    (0UL)          /*!< SSIFRDR (Bit 0)                                       */
+ #define R_SSI0_SSIFRDR_SSIFRDR_Msk    (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff)                   */
+/* =======================================================  SSIFRDR16  ======================================================= */
+/* =======================================================  SSIFRDR8  ======================================================== */
+/* ========================================================  SSIOFR  ========================================================= */
+ #define R_SSI0_SSIOFR_BCKASTP_Pos     (9UL)          /*!< BCKASTP (Bit 9)                                       */
+ #define R_SSI0_SSIOFR_BCKASTP_Msk     (0x200UL)      /*!< BCKASTP (Bitfield-Mask: 0x01)                         */
+ #define R_SSI0_SSIOFR_LRCONT_Pos      (8UL)          /*!< LRCONT (Bit 8)                                        */
+ #define R_SSI0_SSIOFR_LRCONT_Msk      (0x100UL)      /*!< LRCONT (Bitfield-Mask: 0x01)                          */
+ #define R_SSI0_SSIOFR_OMOD_Pos        (0UL)          /*!< OMOD (Bit 0)                                          */
+ #define R_SSI0_SSIOFR_OMOD_Msk        (0x3UL)        /*!< OMOD (Bitfield-Mask: 0x03)                            */
+/* ========================================================  SSISCR  ========================================================= */
+ #define R_SSI0_SSISCR_TDES_Pos        (8UL)          /*!< TDES (Bit 8)                                          */
+ #define R_SSI0_SSISCR_TDES_Msk        (0x1f00UL)     /*!< TDES (Bitfield-Mask: 0x1f)                            */
+ #define R_SSI0_SSISCR_RDFS_Pos        (0UL)          /*!< RDFS (Bit 0)                                          */
+ #define R_SSI0_SSISCR_RDFS_Msk        (0x1fUL)       /*!< RDFS (Bitfield-Mask: 0x1f)                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SYSTEM                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SBYCR  ========================================================= */
+ #define R_SYSTEM_SBYCR_SSBY_Pos                   (15UL)         /*!< SSBY (Bit 15)                                         */
+ #define R_SYSTEM_SBYCR_SSBY_Msk                   (0x8000UL)     /*!< SSBY (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_SBYCR_OPE_Pos                    (14UL)         /*!< OPE (Bit 14)                                          */
+ #define R_SYSTEM_SBYCR_OPE_Msk                    (0x4000UL)     /*!< OPE (Bitfield-Mask: 0x01)                             */
+/* ========================================================  MSTPCRA  ======================================================== */
+ #define R_SYSTEM_MSTPCRA_MSTPA22_Pos              (22UL)         /*!< MSTPA22 (Bit 22)                                      */
+ #define R_SYSTEM_MSTPCRA_MSTPA22_Msk              (0x400000UL)   /*!< MSTPA22 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_MSTPCRA_MSTPA7_Pos               (7UL)          /*!< MSTPA7 (Bit 7)                                        */
+ #define R_SYSTEM_MSTPCRA_MSTPA7_Msk               (0x80UL)       /*!< MSTPA7 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_MSTPCRA_MSTPA6_Pos               (6UL)          /*!< MSTPA6 (Bit 6)                                        */
+ #define R_SYSTEM_MSTPCRA_MSTPA6_Msk               (0x40UL)       /*!< MSTPA6 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_MSTPCRA_MSTPA5_Pos               (5UL)          /*!< MSTPA5 (Bit 5)                                        */
+ #define R_SYSTEM_MSTPCRA_MSTPA5_Msk               (0x20UL)       /*!< MSTPA5 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_MSTPCRA_MSTPA1_Pos               (1UL)          /*!< MSTPA1 (Bit 1)                                        */
+ #define R_SYSTEM_MSTPCRA_MSTPA1_Msk               (0x2UL)        /*!< MSTPA1 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_MSTPCRA_MSTPA0_Pos               (0UL)          /*!< MSTPA0 (Bit 0)                                        */
+ #define R_SYSTEM_MSTPCRA_MSTPA0_Msk               (0x1UL)        /*!< MSTPA0 (Bitfield-Mask: 0x01)                          */
+/* =======================================================  SCKDIVCR  ======================================================== */
+ #define R_SYSTEM_SCKDIVCR_FCK_Pos                 (28UL)         /*!< FCK (Bit 28)                                          */
+ #define R_SYSTEM_SCKDIVCR_FCK_Msk                 (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07)                             */
+ #define R_SYSTEM_SCKDIVCR_ICK_Pos                 (24UL)         /*!< ICK (Bit 24)                                          */
+ #define R_SYSTEM_SCKDIVCR_ICK_Msk                 (0x7000000UL)  /*!< ICK (Bitfield-Mask: 0x07)                             */
+ #define R_SYSTEM_SCKDIVCR_BCK_Pos                 (16UL)         /*!< BCK (Bit 16)                                          */
+ #define R_SYSTEM_SCKDIVCR_BCK_Msk                 (0x70000UL)    /*!< BCK (Bitfield-Mask: 0x07)                             */
+ #define R_SYSTEM_SCKDIVCR_PCKA_Pos                (12UL)         /*!< PCKA (Bit 12)                                         */
+ #define R_SYSTEM_SCKDIVCR_PCKA_Msk                (0x7000UL)     /*!< PCKA (Bitfield-Mask: 0x07)                            */
+ #define R_SYSTEM_SCKDIVCR_PCKB_Pos                (8UL)          /*!< PCKB (Bit 8)                                          */
+ #define R_SYSTEM_SCKDIVCR_PCKB_Msk                (0x700UL)      /*!< PCKB (Bitfield-Mask: 0x07)                            */
+ #define R_SYSTEM_SCKDIVCR_PCKC_Pos                (4UL)          /*!< PCKC (Bit 4)                                          */
+ #define R_SYSTEM_SCKDIVCR_PCKC_Msk                (0x70UL)       /*!< PCKC (Bitfield-Mask: 0x07)                            */
+ #define R_SYSTEM_SCKDIVCR_PCKD_Pos                (0UL)          /*!< PCKD (Bit 0)                                          */
+ #define R_SYSTEM_SCKDIVCR_PCKD_Msk                (0x7UL)        /*!< PCKD (Bitfield-Mask: 0x07)                            */
+/* =======================================================  SCKDIVCR2  ======================================================= */
+ #define R_SYSTEM_SCKDIVCR2_UCK_Pos                (4UL)          /*!< UCK (Bit 4)                                           */
+ #define R_SYSTEM_SCKDIVCR2_UCK_Msk                (0x70UL)       /*!< UCK (Bitfield-Mask: 0x07)                             */
+/* ========================================================  SCKSCR  ========================================================= */
+ #define R_SYSTEM_SCKSCR_CKSEL_Pos                 (0UL)          /*!< CKSEL (Bit 0)                                         */
+ #define R_SYSTEM_SCKSCR_CKSEL_Msk                 (0x7UL)        /*!< CKSEL (Bitfield-Mask: 0x07)                           */
+/* ========================================================  PLLCCR  ========================================================= */
+ #define R_SYSTEM_PLLCCR_PLLMUL_Pos                (8UL)          /*!< PLLMUL (Bit 8)                                        */
+ #define R_SYSTEM_PLLCCR_PLLMUL_Msk                (0x3f00UL)     /*!< PLLMUL (Bitfield-Mask: 0x3f)                          */
+ #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos              (4UL)          /*!< PLSRCSEL (Bit 4)                                      */
+ #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk              (0x10UL)       /*!< PLSRCSEL (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_PLLCCR_PLIDIV_Pos                (0UL)          /*!< PLIDIV (Bit 0)                                        */
+ #define R_SYSTEM_PLLCCR_PLIDIV_Msk                (0x3UL)        /*!< PLIDIV (Bitfield-Mask: 0x03)                          */
+/* =========================================================  PLLCR  ========================================================= */
+ #define R_SYSTEM_PLLCR_PLLSTP_Pos                 (0UL)          /*!< PLLSTP (Bit 0)                                        */
+ #define R_SYSTEM_PLLCR_PLLSTP_Msk                 (0x1UL)        /*!< PLLSTP (Bitfield-Mask: 0x01)                          */
+/* ========================================================  PLLCCR2  ======================================================== */
+ #define R_SYSTEM_PLLCCR2_PLODIV_Pos               (6UL)          /*!< PLODIV (Bit 6)                                        */
+ #define R_SYSTEM_PLLCCR2_PLODIV_Msk               (0xc0UL)       /*!< PLODIV (Bitfield-Mask: 0x03)                          */
+ #define R_SYSTEM_PLLCCR2_PLLMUL_Pos               (0UL)          /*!< PLLMUL (Bit 0)                                        */
+ #define R_SYSTEM_PLLCCR2_PLLMUL_Msk               (0x1fUL)       /*!< PLLMUL (Bitfield-Mask: 0x1f)                          */
+/* =========================================================  BCKCR  ========================================================= */
+ #define R_SYSTEM_BCKCR_BCLKDIV_Pos                (0UL)          /*!< BCLKDIV (Bit 0)                                       */
+ #define R_SYSTEM_BCKCR_BCLKDIV_Msk                (0x1UL)        /*!< BCLKDIV (Bitfield-Mask: 0x01)                         */
+/* ========================================================  MEMWAIT  ======================================================== */
+ #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos              (0UL)          /*!< MEMWAIT (Bit 0)                                       */
+ #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk              (0x1UL)        /*!< MEMWAIT (Bitfield-Mask: 0x01)                         */
+/* ========================================================  MOSCCR  ========================================================= */
+ #define R_SYSTEM_MOSCCR_MOSTP_Pos                 (0UL)          /*!< MOSTP (Bit 0)                                         */
+ #define R_SYSTEM_MOSCCR_MOSTP_Msk                 (0x1UL)        /*!< MOSTP (Bitfield-Mask: 0x01)                           */
+/* ========================================================  HOCOCR  ========================================================= */
+ #define R_SYSTEM_HOCOCR_HCSTP_Pos                 (0UL)          /*!< HCSTP (Bit 0)                                         */
+ #define R_SYSTEM_HOCOCR_HCSTP_Msk                 (0x1UL)        /*!< HCSTP (Bitfield-Mask: 0x01)                           */
+/* ========================================================  MOCOCR  ========================================================= */
+ #define R_SYSTEM_MOCOCR_MCSTP_Pos                 (0UL)          /*!< MCSTP (Bit 0)                                         */
+ #define R_SYSTEM_MOCOCR_MCSTP_Msk                 (0x1UL)        /*!< MCSTP (Bitfield-Mask: 0x01)                           */
+/* ========================================================  FLLCR1  ========================================================= */
+ #define R_SYSTEM_FLLCR1_FLLEN_Pos                 (0UL)          /*!< FLLEN (Bit 0)                                         */
+ #define R_SYSTEM_FLLCR1_FLLEN_Msk                 (0x1UL)        /*!< FLLEN (Bitfield-Mask: 0x01)                           */
+/* ========================================================  FLLCR2  ========================================================= */
+ #define R_SYSTEM_FLLCR2_FLLCNTL_Pos               (0UL)          /*!< FLLCNTL (Bit 0)                                       */
+ #define R_SYSTEM_FLLCR2_FLLCNTL_Msk               (0x7ffUL)      /*!< FLLCNTL (Bitfield-Mask: 0x7ff)                        */
+/* =========================================================  OSCSF  ========================================================= */
+ #define R_SYSTEM_OSCSF_PLLSF_Pos                  (5UL)          /*!< PLLSF (Bit 5)                                         */
+ #define R_SYSTEM_OSCSF_PLLSF_Msk                  (0x20UL)       /*!< PLLSF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_OSCSF_MOSCSF_Pos                 (3UL)          /*!< MOSCSF (Bit 3)                                        */
+ #define R_SYSTEM_OSCSF_MOSCSF_Msk                 (0x8UL)        /*!< MOSCSF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_OSCSF_HOCOSF_Pos                 (0UL)          /*!< HOCOSF (Bit 0)                                        */
+ #define R_SYSTEM_OSCSF_HOCOSF_Msk                 (0x1UL)        /*!< HOCOSF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_OSCSF_PLL2SF_Pos                 (6UL)          /*!< PLL2SF (Bit 6)                                        */
+ #define R_SYSTEM_OSCSF_PLL2SF_Msk                 (0x40UL)       /*!< PLL2SF (Bitfield-Mask: 0x01)                          */
+/* =========================================================  CKOCR  ========================================================= */
+ #define R_SYSTEM_CKOCR_CKOEN_Pos                  (7UL)          /*!< CKOEN (Bit 7)                                         */
+ #define R_SYSTEM_CKOCR_CKOEN_Msk                  (0x80UL)       /*!< CKOEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_CKOCR_CKODIV_Pos                 (4UL)          /*!< CKODIV (Bit 4)                                        */
+ #define R_SYSTEM_CKOCR_CKODIV_Msk                 (0x70UL)       /*!< CKODIV (Bitfield-Mask: 0x07)                          */
+ #define R_SYSTEM_CKOCR_CKOSEL_Pos                 (0UL)          /*!< CKOSEL (Bit 0)                                        */
+ #define R_SYSTEM_CKOCR_CKOSEL_Msk                 (0x7UL)        /*!< CKOSEL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  TRCKCR  ========================================================= */
+ #define R_SYSTEM_TRCKCR_TRCKEN_Pos                (7UL)          /*!< TRCKEN (Bit 7)                                        */
+ #define R_SYSTEM_TRCKCR_TRCKEN_Msk                (0x80UL)       /*!< TRCKEN (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_TRCKCR_TRCK_Pos                  (0UL)          /*!< TRCK (Bit 0)                                          */
+ #define R_SYSTEM_TRCKCR_TRCK_Msk                  (0xfUL)        /*!< TRCK (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  OSTDCR  ========================================================= */
+ #define R_SYSTEM_OSTDCR_OSTDE_Pos                 (7UL)          /*!< OSTDE (Bit 7)                                         */
+ #define R_SYSTEM_OSTDCR_OSTDE_Msk                 (0x80UL)       /*!< OSTDE (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_OSTDCR_OSTDIE_Pos                (0UL)          /*!< OSTDIE (Bit 0)                                        */
+ #define R_SYSTEM_OSTDCR_OSTDIE_Msk                (0x1UL)        /*!< OSTDIE (Bitfield-Mask: 0x01)                          */
+/* ========================================================  OSTDSR  ========================================================= */
+ #define R_SYSTEM_OSTDSR_OSTDF_Pos                 (0UL)          /*!< OSTDF (Bit 0)                                         */
+ #define R_SYSTEM_OSTDSR_OSTDF_Msk                 (0x1UL)        /*!< OSTDF (Bitfield-Mask: 0x01)                           */
+/* =========================================================  LPOPT  ========================================================= */
+ #define R_SYSTEM_LPOPT_LPOPTEN_Pos                (7UL)          /*!< LPOPTEN (Bit 7)                                       */
+ #define R_SYSTEM_LPOPT_LPOPTEN_Msk                (0x80UL)       /*!< LPOPTEN (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos              (3UL)          /*!< BPFCLKDIS (Bit 3)                                     */
+ #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk              (0x8UL)        /*!< BPFCLKDIS (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_LPOPT_DCLKDIS_Pos                (1UL)          /*!< DCLKDIS (Bit 1)                                       */
+ #define R_SYSTEM_LPOPT_DCLKDIS_Msk                (0x6UL)        /*!< DCLKDIS (Bitfield-Mask: 0x03)                         */
+ #define R_SYSTEM_LPOPT_MPUDIS_Pos                 (0UL)          /*!< MPUDIS (Bit 0)                                        */
+ #define R_SYSTEM_LPOPT_MPUDIS_Msk                 (0x1UL)        /*!< MPUDIS (Bitfield-Mask: 0x01)                          */
+/* =======================================================  SLCDSCKCR  ======================================================= */
+ #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos           (7UL)          /*!< LCDSCKEN (Bit 7)                                      */
+ #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk           (0x80UL)       /*!< LCDSCKEN (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos          (0UL)          /*!< LCDSCKSEL (Bit 0)                                     */
+ #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk          (0x7UL)        /*!< LCDSCKSEL (Bitfield-Mask: 0x07)                       */
+/* ========================================================  EBCKOCR  ======================================================== */
+ #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos              (0UL)          /*!< EBCKOEN (Bit 0)                                       */
+ #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk              (0x1UL)        /*!< EBCKOEN (Bitfield-Mask: 0x01)                         */
+/* ========================================================  SDCKOCR  ======================================================== */
+ #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos              (0UL)          /*!< SDCKOEN (Bit 0)                                       */
+ #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk              (0x1UL)        /*!< SDCKOEN (Bitfield-Mask: 0x01)                         */
+/* =======================================================  MOCOUTCR  ======================================================== */
+ #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos            (0UL)          /*!< MOCOUTRM (Bit 0)                                      */
+ #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk            (0xffUL)       /*!< MOCOUTRM (Bitfield-Mask: 0xff)                        */
+/* =======================================================  HOCOUTCR  ======================================================== */
+ #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos            (0UL)          /*!< HOCOUTRM (Bit 0)                                      */
+ #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk            (0xffUL)       /*!< HOCOUTRM (Bitfield-Mask: 0xff)                        */
+/* =========================================================  SNZCR  ========================================================= */
+ #define R_SYSTEM_SNZCR_SNZE_Pos                   (7UL)          /*!< SNZE (Bit 7)                                          */
+ #define R_SYSTEM_SNZCR_SNZE_Msk                   (0x80UL)       /*!< SNZE (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_SNZCR_SNZDTCEN_Pos               (1UL)          /*!< SNZDTCEN (Bit 1)                                      */
+ #define R_SYSTEM_SNZCR_SNZDTCEN_Msk               (0x2UL)        /*!< SNZDTCEN (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SNZCR_RXDREQEN_Pos               (0UL)          /*!< RXDREQEN (Bit 0)                                      */
+ #define R_SYSTEM_SNZCR_RXDREQEN_Msk               (0x1UL)        /*!< RXDREQEN (Bitfield-Mask: 0x01)                        */
+/* ========================================================  SNZEDCR  ======================================================== */
+ #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos            (7UL)          /*!< SCI0UMTED (Bit 7)                                     */
+ #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk            (0x80UL)       /*!< SCI0UMTED (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos             (6UL)          /*!< AD1UMTED (Bit 6)                                      */
+ #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk             (0x40UL)       /*!< AD1UMTED (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SNZEDCR_AD1MATED_Pos             (5UL)          /*!< AD1MATED (Bit 5)                                      */
+ #define R_SYSTEM_SNZEDCR_AD1MATED_Msk             (0x20UL)       /*!< AD1MATED (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos             (4UL)          /*!< AD0UMTED (Bit 4)                                      */
+ #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk             (0x10UL)       /*!< AD0UMTED (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SNZEDCR_AD0MATED_Pos             (3UL)          /*!< AD0MATED (Bit 3)                                      */
+ #define R_SYSTEM_SNZEDCR_AD0MATED_Msk             (0x8UL)        /*!< AD0MATED (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos             (2UL)          /*!< DTCNZRED (Bit 2)                                      */
+ #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk             (0x4UL)        /*!< DTCNZRED (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SNZEDCR_DTCZRED_Pos              (1UL)          /*!< DTCZRED (Bit 1)                                       */
+ #define R_SYSTEM_SNZEDCR_DTCZRED_Msk              (0x2UL)        /*!< DTCZRED (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos            (0UL)          /*!< AGT1UNFED (Bit 0)                                     */
+ #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk            (0x1UL)        /*!< AGT1UNFED (Bitfield-Mask: 0x01)                       */
+/* =======================================================  SNZREQCR  ======================================================== */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos          (30UL)         /*!< SNZREQEN30 (Bit 30)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk          (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos          (29UL)         /*!< SNZREQEN29 (Bit 29)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk          (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos          (28UL)         /*!< SNZREQEN28 (Bit 28)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk          (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos          (25UL)         /*!< SNZREQEN25 (Bit 25)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk          (0x2000000UL)  /*!< SNZREQEN25 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos          (24UL)         /*!< SNZREQEN24 (Bit 24)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk          (0x1000000UL)  /*!< SNZREQEN24 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos          (23UL)         /*!< SNZREQEN23 (Bit 23)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk          (0x800000UL)   /*!< SNZREQEN23 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos          (22UL)         /*!< SNZREQEN22 (Bit 22)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk          (0x400000UL)   /*!< SNZREQEN22 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos          (17UL)         /*!< SNZREQEN17 (Bit 17)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk          (0x20000UL)    /*!< SNZREQEN17 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos            (0UL)          /*!< SNZREQEN (Bit 0)                                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk            (0x1UL)        /*!< SNZREQEN (Bitfield-Mask: 0x01)                        */
+/* ========================================================  FLSTOP  ========================================================= */
+ #define R_SYSTEM_FLSTOP_FLSTPF_Pos                (4UL)          /*!< FLSTPF (Bit 4)                                        */
+ #define R_SYSTEM_FLSTOP_FLSTPF_Msk                (0x10UL)       /*!< FLSTPF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_FLSTOP_FLSTOP_Pos                (0UL)          /*!< FLSTOP (Bit 0)                                        */
+ #define R_SYSTEM_FLSTOP_FLSTOP_Msk                (0x1UL)        /*!< FLSTOP (Bitfield-Mask: 0x01)                          */
+/* =========================================================  PSMCR  ========================================================= */
+ #define R_SYSTEM_PSMCR_PSMC_Pos                   (0UL)          /*!< PSMC (Bit 0)                                          */
+ #define R_SYSTEM_PSMCR_PSMC_Msk                   (0x3UL)        /*!< PSMC (Bitfield-Mask: 0x03)                            */
+/* =========================================================  OPCCR  ========================================================= */
+ #define R_SYSTEM_OPCCR_OPCMTSF_Pos                (4UL)          /*!< OPCMTSF (Bit 4)                                       */
+ #define R_SYSTEM_OPCCR_OPCMTSF_Msk                (0x10UL)       /*!< OPCMTSF (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_OPCCR_OPCM_Pos                   (0UL)          /*!< OPCM (Bit 0)                                          */
+ #define R_SYSTEM_OPCCR_OPCM_Msk                   (0x3UL)        /*!< OPCM (Bitfield-Mask: 0x03)                            */
+/* ========================================================  SOPCCR  ========================================================= */
+ #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos              (4UL)          /*!< SOPCMTSF (Bit 4)                                      */
+ #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk              (0x10UL)       /*!< SOPCMTSF (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SOPCCR_SOPCM_Pos                 (0UL)          /*!< SOPCM (Bit 0)                                         */
+ #define R_SYSTEM_SOPCCR_SOPCM_Msk                 (0x1UL)        /*!< SOPCM (Bitfield-Mask: 0x01)                           */
+/* =======================================================  MOSCWTCR  ======================================================== */
+ #define R_SYSTEM_MOSCWTCR_MSTS_Pos                (0UL)          /*!< MSTS (Bit 0)                                          */
+ #define R_SYSTEM_MOSCWTCR_MSTS_Msk                (0xfUL)        /*!< MSTS (Bitfield-Mask: 0x0f)                            */
+/* =======================================================  HOCOWTCR  ======================================================== */
+ #define R_SYSTEM_HOCOWTCR_HSTS_Pos                (0UL)          /*!< HSTS (Bit 0)                                          */
+ #define R_SYSTEM_HOCOWTCR_HSTS_Msk                (0x7UL)        /*!< HSTS (Bitfield-Mask: 0x07)                            */
+/* ========================================================  RSTSR1  ========================================================= */
+ #define R_SYSTEM_RSTSR1_SPERF_Pos                 (12UL)         /*!< SPERF (Bit 12)                                        */
+ #define R_SYSTEM_RSTSR1_SPERF_Msk                 (0x1000UL)     /*!< SPERF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_RSTSR1_BUSMRF_Pos                (11UL)         /*!< BUSMRF (Bit 11)                                       */
+ #define R_SYSTEM_RSTSR1_BUSMRF_Msk                (0x800UL)      /*!< BUSMRF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_RSTSR1_BUSSRF_Pos                (10UL)         /*!< BUSSRF (Bit 10)                                       */
+ #define R_SYSTEM_RSTSR1_BUSSRF_Msk                (0x400UL)      /*!< BUSSRF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_RSTSR1_REERF_Pos                 (9UL)          /*!< REERF (Bit 9)                                         */
+ #define R_SYSTEM_RSTSR1_REERF_Msk                 (0x200UL)      /*!< REERF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_RSTSR1_RPERF_Pos                 (8UL)          /*!< RPERF (Bit 8)                                         */
+ #define R_SYSTEM_RSTSR1_RPERF_Msk                 (0x100UL)      /*!< RPERF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_RSTSR1_SWRF_Pos                  (2UL)          /*!< SWRF (Bit 2)                                          */
+ #define R_SYSTEM_RSTSR1_SWRF_Msk                  (0x4UL)        /*!< SWRF (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_RSTSR1_WDTRF_Pos                 (1UL)          /*!< WDTRF (Bit 1)                                         */
+ #define R_SYSTEM_RSTSR1_WDTRF_Msk                 (0x2UL)        /*!< WDTRF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_RSTSR1_IWDTRF_Pos                (0UL)          /*!< IWDTRF (Bit 0)                                        */
+ #define R_SYSTEM_RSTSR1_IWDTRF_Msk                (0x1UL)        /*!< IWDTRF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_RSTSR1_TZERF_Pos                 (13UL)         /*!< TZERF (Bit 13)                                        */
+ #define R_SYSTEM_RSTSR1_TZERF_Msk                 (0x2000UL)     /*!< TZERF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_RSTSR1_CPERF_Pos                 (15UL)         /*!< CPERF (Bit 15)                                        */
+ #define R_SYSTEM_RSTSR1_CPERF_Msk                 (0x8000UL)     /*!< CPERF (Bitfield-Mask: 0x01)                           */
+/* ========================================================  STCONR  ========================================================= */
+ #define R_SYSTEM_STCONR_STCON_Pos                 (0UL)          /*!< STCON (Bit 0)                                         */
+ #define R_SYSTEM_STCONR_STCON_Msk                 (0x3UL)        /*!< STCON (Bitfield-Mask: 0x03)                           */
+/* ========================================================  LVD1CR1  ======================================================== */
+ #define R_SYSTEM_LVD1CR1_IRQSEL_Pos               (2UL)          /*!< IRQSEL (Bit 2)                                        */
+ #define R_SYSTEM_LVD1CR1_IRQSEL_Msk               (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_LVD1CR1_IDTSEL_Pos               (0UL)          /*!< IDTSEL (Bit 0)                                        */
+ #define R_SYSTEM_LVD1CR1_IDTSEL_Msk               (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
+/* ========================================================  LVD2CR1  ======================================================== */
+ #define R_SYSTEM_LVD2CR1_IRQSEL_Pos               (2UL)          /*!< IRQSEL (Bit 2)                                        */
+ #define R_SYSTEM_LVD2CR1_IRQSEL_Msk               (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_LVD2CR1_IDTSEL_Pos               (0UL)          /*!< IDTSEL (Bit 0)                                        */
+ #define R_SYSTEM_LVD2CR1_IDTSEL_Msk               (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
+/* ======================================================  USBCKCR_ALT  ====================================================== */
+ #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos        (0UL)          /*!< USBCLKSEL (Bit 0)                                     */
+ #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk        (0x1UL)        /*!< USBCLKSEL (Bitfield-Mask: 0x01)                       */
+/* =======================================================  SDADCCKCR  ======================================================= */
+ #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos         (0UL)          /*!< SDADCCKSEL (Bit 0)                                    */
+ #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk         (0x1UL)        /*!< SDADCCKSEL (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos          (7UL)          /*!< SDADCCKEN (Bit 7)                                     */
+ #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk          (0x80UL)       /*!< SDADCCKEN (Bitfield-Mask: 0x01)                       */
+/* ========================================================  LVD1SR  ========================================================= */
+ #define R_SYSTEM_LVD1SR_MON_Pos                   (1UL)          /*!< MON (Bit 1)                                           */
+ #define R_SYSTEM_LVD1SR_MON_Msk                   (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
+ #define R_SYSTEM_LVD1SR_DET_Pos                   (0UL)          /*!< DET (Bit 0)                                           */
+ #define R_SYSTEM_LVD1SR_DET_Msk                   (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
+/* ========================================================  LVD2SR  ========================================================= */
+ #define R_SYSTEM_LVD2SR_MON_Pos                   (1UL)          /*!< MON (Bit 1)                                           */
+ #define R_SYSTEM_LVD2SR_MON_Msk                   (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
+ #define R_SYSTEM_LVD2SR_DET_Pos                   (0UL)          /*!< DET (Bit 0)                                           */
+ #define R_SYSTEM_LVD2SR_DET_Msk                   (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
+/* =========================================================  PRCR  ========================================================== */
+ #define R_SYSTEM_PRCR_PRKEY_Pos                   (8UL)          /*!< PRKEY (Bit 8)                                         */
+ #define R_SYSTEM_PRCR_PRKEY_Msk                   (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
+ #define R_SYSTEM_PRCR_PRC3_Pos                    (3UL)          /*!< PRC3 (Bit 3)                                          */
+ #define R_SYSTEM_PRCR_PRC3_Msk                    (0x8UL)        /*!< PRC3 (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_PRCR_PRC1_Pos                    (1UL)          /*!< PRC1 (Bit 1)                                          */
+ #define R_SYSTEM_PRCR_PRC1_Msk                    (0x2UL)        /*!< PRC1 (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_PRCR_PRC0_Pos                    (0UL)          /*!< PRC0 (Bit 0)                                          */
+ #define R_SYSTEM_PRCR_PRC0_Msk                    (0x1UL)        /*!< PRC0 (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_PRCR_PRC4_Pos                    (4UL)          /*!< PRC4 (Bit 4)                                          */
+ #define R_SYSTEM_PRCR_PRC4_Msk                    (0x10UL)       /*!< PRC4 (Bitfield-Mask: 0x01)                            */
+/* ========================================================  DPSIER0  ======================================================== */
+ #define R_SYSTEM_DPSIER0_DIRQE_Pos                (0UL)          /*!< DIRQE (Bit 0)                                         */
+ #define R_SYSTEM_DPSIER0_DIRQE_Msk                (0x1UL)        /*!< DIRQE (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DPSIER1  ======================================================== */
+ #define R_SYSTEM_DPSIER1_DIRQE_Pos                (0UL)          /*!< DIRQE (Bit 0)                                         */
+ #define R_SYSTEM_DPSIER1_DIRQE_Msk                (0x1UL)        /*!< DIRQE (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DPSIER2  ======================================================== */
+ #define R_SYSTEM_DPSIER2_DNMIE_Pos                (4UL)          /*!< DNMIE (Bit 4)                                         */
+ #define R_SYSTEM_DPSIER2_DNMIE_Msk                (0x10UL)       /*!< DNMIE (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_DPSIER2_DRTCAIE_Pos              (3UL)          /*!< DRTCAIE (Bit 3)                                       */
+ #define R_SYSTEM_DPSIER2_DRTCAIE_Msk              (0x8UL)        /*!< DRTCAIE (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos             (2UL)          /*!< DTRTCIIE (Bit 2)                                      */
+ #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk             (0x4UL)        /*!< DTRTCIIE (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_DPSIER2_DLVD2IE_Pos              (1UL)          /*!< DLVD2IE (Bit 1)                                       */
+ #define R_SYSTEM_DPSIER2_DLVD2IE_Msk              (0x2UL)        /*!< DLVD2IE (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPSIER2_DLVD1IE_Pos              (0UL)          /*!< DLVD1IE (Bit 0)                                       */
+ #define R_SYSTEM_DPSIER2_DLVD1IE_Msk              (0x1UL)        /*!< DLVD1IE (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DPSIER3  ======================================================== */
+ #define R_SYSTEM_DPSIER3_DAGT1IE_Pos              (2UL)          /*!< DAGT1IE (Bit 2)                                       */
+ #define R_SYSTEM_DPSIER3_DAGT1IE_Msk              (0x4UL)        /*!< DAGT1IE (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos             (1UL)          /*!< DUSBHSIE (Bit 1)                                      */
+ #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk             (0x2UL)        /*!< DUSBHSIE (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos             (0UL)          /*!< DUSBFSIE (Bit 0)                                      */
+ #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk             (0x1UL)        /*!< DUSBFSIE (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_DPSIER3_DAGT3IE_Pos              (3UL)          /*!< DAGT3IE (Bit 3)                                       */
+ #define R_SYSTEM_DPSIER3_DAGT3IE_Msk              (0x8UL)        /*!< DAGT3IE (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DPSIFR0  ======================================================== */
+ #define R_SYSTEM_DPSIFR0_DIRQF_Pos                (0UL)          /*!< DIRQF (Bit 0)                                         */
+ #define R_SYSTEM_DPSIFR0_DIRQF_Msk                (0x1UL)        /*!< DIRQF (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DPSIFR1  ======================================================== */
+ #define R_SYSTEM_DPSIFR1_DIRQF_Pos                (0UL)          /*!< DIRQF (Bit 0)                                         */
+ #define R_SYSTEM_DPSIFR1_DIRQF_Msk                (0x1UL)        /*!< DIRQF (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DPSIFR2  ======================================================== */
+ #define R_SYSTEM_DPSIFR2_DNMIF_Pos                (4UL)          /*!< DNMIF (Bit 4)                                         */
+ #define R_SYSTEM_DPSIFR2_DNMIF_Msk                (0x10UL)       /*!< DNMIF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos              (3UL)          /*!< DRTCAIF (Bit 3)                                       */
+ #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk              (0x8UL)        /*!< DRTCAIF (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos             (2UL)          /*!< DTRTCIIF (Bit 2)                                      */
+ #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk             (0x4UL)        /*!< DTRTCIIF (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos              (1UL)          /*!< DLVD2IF (Bit 1)                                       */
+ #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk              (0x2UL)        /*!< DLVD2IF (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos              (0UL)          /*!< DLVD1IF (Bit 0)                                       */
+ #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk              (0x1UL)        /*!< DLVD1IF (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DPSIFR3  ======================================================== */
+ #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos              (2UL)          /*!< DAGT1IF (Bit 2)                                       */
+ #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk              (0x4UL)        /*!< DAGT1IF (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos             (1UL)          /*!< DUSBHSIF (Bit 1)                                      */
+ #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk             (0x2UL)        /*!< DUSBHSIF (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos             (0UL)          /*!< DUSBFSIF (Bit 0)                                      */
+ #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk             (0x1UL)        /*!< DUSBFSIF (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos              (3UL)          /*!< DAGT3IF (Bit 3)                                       */
+ #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk              (0x8UL)        /*!< DAGT3IF (Bitfield-Mask: 0x01)                         */
+/* =======================================================  DPSIEGR0  ======================================================== */
+ #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos              (0UL)          /*!< DIRQEG (Bit 0)                                        */
+ #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk              (0x1UL)        /*!< DIRQEG (Bitfield-Mask: 0x01)                          */
+/* =======================================================  DPSIEGR1  ======================================================== */
+ #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos              (0UL)          /*!< DIRQEG (Bit 0)                                        */
+ #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk              (0x1UL)        /*!< DIRQEG (Bitfield-Mask: 0x01)                          */
+/* =======================================================  DPSIEGR2  ======================================================== */
+ #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos              (4UL)          /*!< DNMIEG (Bit 4)                                        */
+ #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk              (0x10UL)       /*!< DNMIEG (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos            (1UL)          /*!< DLVD2IEG (Bit 1)                                      */
+ #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk            (0x2UL)        /*!< DLVD2IEG (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos            (0UL)          /*!< DLVD1IEG (Bit 0)                                      */
+ #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk            (0x1UL)        /*!< DLVD1IEG (Bitfield-Mask: 0x01)                        */
+/* ========================================================  DPSBYCR  ======================================================== */
+ #define R_SYSTEM_DPSBYCR_DPSBY_Pos                (7UL)          /*!< DPSBY (Bit 7)                                         */
+ #define R_SYSTEM_DPSBYCR_DPSBY_Msk                (0x80UL)       /*!< DPSBY (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_DPSBYCR_IOKEEP_Pos               (6UL)          /*!< IOKEEP (Bit 6)                                        */
+ #define R_SYSTEM_DPSBYCR_IOKEEP_Msk               (0x40UL)       /*!< IOKEEP (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos              (0UL)          /*!< DEEPCUT (Bit 0)                                       */
+ #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk              (0x3UL)        /*!< DEEPCUT (Bitfield-Mask: 0x03)                         */
+/* ========================================================  SYOCDCR  ======================================================== */
+ #define R_SYSTEM_SYOCDCR_DBGEN_Pos                (7UL)          /*!< DBGEN (Bit 7)                                         */
+ #define R_SYSTEM_SYOCDCR_DBGEN_Msk                (0x80UL)       /*!< DBGEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_SYOCDCR_DOCDF_Pos                (0UL)          /*!< DOCDF (Bit 0)                                         */
+ #define R_SYSTEM_SYOCDCR_DOCDF_Msk                (0x1UL)        /*!< DOCDF (Bitfield-Mask: 0x01)                           */
+/* =========================================================  MOMCR  ========================================================= */
+ #define R_SYSTEM_MOMCR_AUTODRVEN_Pos              (7UL)          /*!< AUTODRVEN (Bit 7)                                     */
+ #define R_SYSTEM_MOMCR_AUTODRVEN_Msk              (0x80UL)       /*!< AUTODRVEN (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_MOMCR_MOSEL_Pos                  (6UL)          /*!< MOSEL (Bit 6)                                         */
+ #define R_SYSTEM_MOMCR_MOSEL_Msk                  (0x40UL)       /*!< MOSEL (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_MOMCR_MODRV0_Pos                 (4UL)          /*!< MODRV0 (Bit 4)                                        */
+ #define R_SYSTEM_MOMCR_MODRV0_Msk                 (0x30UL)       /*!< MODRV0 (Bitfield-Mask: 0x03)                          */
+ #define R_SYSTEM_MOMCR_MODRV1_Pos                 (3UL)          /*!< MODRV1 (Bit 3)                                        */
+ #define R_SYSTEM_MOMCR_MODRV1_Msk                 (0x8UL)        /*!< MODRV1 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  RSTSR0  ========================================================= */
+ #define R_SYSTEM_RSTSR0_DPSRSTF_Pos               (7UL)          /*!< DPSRSTF (Bit 7)                                       */
+ #define R_SYSTEM_RSTSR0_DPSRSTF_Msk               (0x80UL)       /*!< DPSRSTF (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_RSTSR0_LVD2RF_Pos                (3UL)          /*!< LVD2RF (Bit 3)                                        */
+ #define R_SYSTEM_RSTSR0_LVD2RF_Msk                (0x8UL)        /*!< LVD2RF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_RSTSR0_LVD1RF_Pos                (2UL)          /*!< LVD1RF (Bit 2)                                        */
+ #define R_SYSTEM_RSTSR0_LVD1RF_Msk                (0x4UL)        /*!< LVD1RF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_RSTSR0_LVD0RF_Pos                (1UL)          /*!< LVD0RF (Bit 1)                                        */
+ #define R_SYSTEM_RSTSR0_LVD0RF_Msk                (0x2UL)        /*!< LVD0RF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_RSTSR0_PORF_Pos                  (0UL)          /*!< PORF (Bit 0)                                          */
+ #define R_SYSTEM_RSTSR0_PORF_Msk                  (0x1UL)        /*!< PORF (Bitfield-Mask: 0x01)                            */
+/* ========================================================  RSTSR2  ========================================================= */
+ #define R_SYSTEM_RSTSR2_CWSF_Pos                  (0UL)          /*!< CWSF (Bit 0)                                          */
+ #define R_SYSTEM_RSTSR2_CWSF_Msk                  (0x1UL)        /*!< CWSF (Bitfield-Mask: 0x01)                            */
+/* ========================================================  LVCMPCR  ======================================================== */
+ #define R_SYSTEM_LVCMPCR_LVD2E_Pos                (6UL)          /*!< LVD2E (Bit 6)                                         */
+ #define R_SYSTEM_LVCMPCR_LVD2E_Msk                (0x40UL)       /*!< LVD2E (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_LVCMPCR_LVD1E_Pos                (5UL)          /*!< LVD1E (Bit 5)                                         */
+ #define R_SYSTEM_LVCMPCR_LVD1E_Msk                (0x20UL)       /*!< LVD1E (Bitfield-Mask: 0x01)                           */
+/* =======================================================  LVD1CMPCR  ======================================================= */
+ #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos            (0UL)          /*!< LVD1LVL (Bit 0)                                       */
+ #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk            (0x1fUL)       /*!< LVD1LVL (Bitfield-Mask: 0x1f)                         */
+ #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos              (7UL)          /*!< LVD1E (Bit 7)                                         */
+ #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk              (0x80UL)       /*!< LVD1E (Bitfield-Mask: 0x01)                           */
+/* ========================================================  LVDLVLR  ======================================================== */
+ #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos              (5UL)          /*!< LVD2LVL (Bit 5)                                       */
+ #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk              (0xe0UL)       /*!< LVD2LVL (Bitfield-Mask: 0x07)                         */
+ #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos              (0UL)          /*!< LVD1LVL (Bit 0)                                       */
+ #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk              (0x1fUL)       /*!< LVD1LVL (Bitfield-Mask: 0x1f)                         */
+/* =======================================================  LVD2CMPCR  ======================================================= */
+ #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos            (0UL)          /*!< LVD2LVL (Bit 0)                                       */
+ #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk            (0x7UL)        /*!< LVD2LVL (Bitfield-Mask: 0x07)                         */
+ #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos              (7UL)          /*!< LVD2E (Bit 7)                                         */
+ #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk              (0x80UL)       /*!< LVD2E (Bitfield-Mask: 0x01)                           */
+/* ========================================================  LVD1CR0  ======================================================== */
+ #define R_SYSTEM_LVD1CR0_RN_Pos                   (7UL)          /*!< RN (Bit 7)                                            */
+ #define R_SYSTEM_LVD1CR0_RN_Msk                   (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
+ #define R_SYSTEM_LVD1CR0_RI_Pos                   (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_SYSTEM_LVD1CR0_RI_Msk                   (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_SYSTEM_LVD1CR0_FSAMP_Pos                (4UL)          /*!< FSAMP (Bit 4)                                         */
+ #define R_SYSTEM_LVD1CR0_FSAMP_Msk                (0x30UL)       /*!< FSAMP (Bitfield-Mask: 0x03)                           */
+ #define R_SYSTEM_LVD1CR0_CMPE_Pos                 (2UL)          /*!< CMPE (Bit 2)                                          */
+ #define R_SYSTEM_LVD1CR0_CMPE_Msk                 (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_LVD1CR0_DFDIS_Pos                (1UL)          /*!< DFDIS (Bit 1)                                         */
+ #define R_SYSTEM_LVD1CR0_DFDIS_Msk                (0x2UL)        /*!< DFDIS (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_LVD1CR0_RIE_Pos                  (0UL)          /*!< RIE (Bit 0)                                           */
+ #define R_SYSTEM_LVD1CR0_RIE_Msk                  (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
+/* ========================================================  LVD2CR0  ======================================================== */
+ #define R_SYSTEM_LVD2CR0_RN_Pos                   (7UL)          /*!< RN (Bit 7)                                            */
+ #define R_SYSTEM_LVD2CR0_RN_Msk                   (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
+ #define R_SYSTEM_LVD2CR0_RI_Pos                   (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_SYSTEM_LVD2CR0_RI_Msk                   (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_SYSTEM_LVD2CR0_FSAMP_Pos                (4UL)          /*!< FSAMP (Bit 4)                                         */
+ #define R_SYSTEM_LVD2CR0_FSAMP_Msk                (0x30UL)       /*!< FSAMP (Bitfield-Mask: 0x03)                           */
+ #define R_SYSTEM_LVD2CR0_CMPE_Pos                 (2UL)          /*!< CMPE (Bit 2)                                          */
+ #define R_SYSTEM_LVD2CR0_CMPE_Msk                 (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_LVD2CR0_DFDIS_Pos                (1UL)          /*!< DFDIS (Bit 1)                                         */
+ #define R_SYSTEM_LVD2CR0_DFDIS_Msk                (0x2UL)        /*!< DFDIS (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_LVD2CR0_RIE_Pos                  (0UL)          /*!< RIE (Bit 0)                                           */
+ #define R_SYSTEM_LVD2CR0_RIE_Msk                  (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
+/* ========================================================  VBTCR1  ========================================================= */
+ #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos              (0UL)          /*!< BPWSWSTP (Bit 0)                                      */
+ #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk              (0x1UL)        /*!< BPWSWSTP (Bitfield-Mask: 0x01)                        */
+/* ========================================================  DCDCCTL  ======================================================== */
+ #define R_SYSTEM_DCDCCTL_PD_Pos                   (7UL)          /*!< PD (Bit 7)                                            */
+ #define R_SYSTEM_DCDCCTL_PD_Msk                   (0x80UL)       /*!< PD (Bitfield-Mask: 0x01)                              */
+ #define R_SYSTEM_DCDCCTL_FST_Pos                  (6UL)          /*!< FST (Bit 6)                                           */
+ #define R_SYSTEM_DCDCCTL_FST_Msk                  (0x40UL)       /*!< FST (Bitfield-Mask: 0x01)                             */
+ #define R_SYSTEM_DCDCCTL_LCBOOST_Pos              (5UL)          /*!< LCBOOST (Bit 5)                                       */
+ #define R_SYSTEM_DCDCCTL_LCBOOST_Msk              (0x20UL)       /*!< LCBOOST (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DCDCCTL_STOPZA_Pos               (4UL)          /*!< STOPZA (Bit 4)                                        */
+ #define R_SYSTEM_DCDCCTL_STOPZA_Msk               (0x10UL)       /*!< STOPZA (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DCDCCTL_OCPEN_Pos                (1UL)          /*!< OCPEN (Bit 1)                                         */
+ #define R_SYSTEM_DCDCCTL_OCPEN_Msk                (0x2UL)        /*!< OCPEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_DCDCCTL_DCDCON_Pos               (0UL)          /*!< DCDCON (Bit 0)                                        */
+ #define R_SYSTEM_DCDCCTL_DCDCON_Msk               (0x1UL)        /*!< DCDCON (Bitfield-Mask: 0x01)                          */
+/* ========================================================  VCCSEL  ========================================================= */
+ #define R_SYSTEM_VCCSEL_VCCSEL_Pos                (0UL)          /*!< VCCSEL (Bit 0)                                        */
+ #define R_SYSTEM_VCCSEL_VCCSEL_Msk                (0x3UL)        /*!< VCCSEL (Bitfield-Mask: 0x03)                          */
+/* ========================================================  LDOSCR  ========================================================= */
+ #define R_SYSTEM_LDOSCR_LDOSTP0_Pos               (0UL)          /*!< LDOSTP0 (Bit 0)                                       */
+ #define R_SYSTEM_LDOSCR_LDOSTP0_Msk               (0x1UL)        /*!< LDOSTP0 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_LDOSCR_LDOSTP1_Pos               (1UL)          /*!< LDOSTP1 (Bit 1)                                       */
+ #define R_SYSTEM_LDOSCR_LDOSTP1_Msk               (0x2UL)        /*!< LDOSTP1 (Bitfield-Mask: 0x01)                         */
+/* =======================================================  PL2LDOSCR  ======================================================= */
+ #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos          (0UL)          /*!< PL2LDOSTP (Bit 0)                                     */
+ #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk          (0x1UL)        /*!< PL2LDOSTP (Bitfield-Mask: 0x01)                       */
+/* ========================================================  SOSCCR  ========================================================= */
+ #define R_SYSTEM_SOSCCR_SOSTP_Pos                 (0UL)          /*!< SOSTP (Bit 0)                                         */
+ #define R_SYSTEM_SOSCCR_SOSTP_Msk                 (0x1UL)        /*!< SOSTP (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SOMCR  ========================================================= */
+ #define R_SYSTEM_SOMCR_SODRV_Pos                  (0UL)          /*!< SODRV (Bit 0)                                         */
+ #define R_SYSTEM_SOMCR_SODRV_Msk                  (0x3UL)        /*!< SODRV (Bitfield-Mask: 0x03)                           */
+/* ========================================================  LOCOCR  ========================================================= */
+ #define R_SYSTEM_LOCOCR_LCSTP_Pos                 (0UL)          /*!< LCSTP (Bit 0)                                         */
+ #define R_SYSTEM_LOCOCR_LCSTP_Msk                 (0x1UL)        /*!< LCSTP (Bitfield-Mask: 0x01)                           */
+/* =======================================================  LOCOUTCR  ======================================================== */
+ #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos            (0UL)          /*!< LOCOUTRM (Bit 0)                                      */
+ #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk            (0xffUL)       /*!< LOCOUTRM (Bitfield-Mask: 0xff)                        */
+/* ========================================================  VBTCR2  ========================================================= */
+ #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos             (6UL)          /*!< VBTLVDLVL (Bit 6)                                     */
+ #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk             (0xc0UL)       /*!< VBTLVDLVL (Bitfield-Mask: 0x03)                       */
+ #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos              (4UL)          /*!< VBTLVDEN (Bit 4)                                      */
+ #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk              (0x10UL)       /*!< VBTLVDEN (Bitfield-Mask: 0x01)                        */
+/* =========================================================  VBTSR  ========================================================= */
+ #define R_SYSTEM_VBTSR_VBTRVLD_Pos                (4UL)          /*!< VBTRVLD (Bit 4)                                       */
+ #define R_SYSTEM_VBTSR_VBTRVLD_Msk                (0x10UL)       /*!< VBTRVLD (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_VBTSR_VBTBLDF_Pos                (1UL)          /*!< VBTBLDF (Bit 1)                                       */
+ #define R_SYSTEM_VBTSR_VBTBLDF_Msk                (0x2UL)        /*!< VBTBLDF (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_VBTSR_VBTRDF_Pos                 (0UL)          /*!< VBTRDF (Bit 0)                                        */
+ #define R_SYSTEM_VBTSR_VBTRDF_Msk                 (0x1UL)        /*!< VBTRDF (Bitfield-Mask: 0x01)                          */
+/* =======================================================  VBTCMPCR  ======================================================== */
+ #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos             (0UL)          /*!< VBTCMPE (Bit 0)                                       */
+ #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk             (0x1UL)        /*!< VBTCMPE (Bitfield-Mask: 0x01)                         */
+/* =======================================================  VBTLVDICR  ======================================================= */
+ #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos         (1UL)          /*!< VBTLVDISEL (Bit 1)                                    */
+ #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk         (0x2UL)        /*!< VBTLVDISEL (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos           (0UL)          /*!< VBTLVDIE (Bit 0)                                      */
+ #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk           (0x1UL)        /*!< VBTLVDIE (Bitfield-Mask: 0x01)                        */
+/* =======================================================  VBTWCTLR  ======================================================== */
+ #define R_SYSTEM_VBTWCTLR_VWEN_Pos                (0UL)          /*!< VWEN (Bit 0)                                          */
+ #define R_SYSTEM_VBTWCTLR_VWEN_Msk                (0x1UL)        /*!< VWEN (Bitfield-Mask: 0x01)                            */
+/* ======================================================  VBTWCH0OTSR  ====================================================== */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos       (5UL)          /*!< CH0VAGTUTE (Bit 5)                                    */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk       (0x20UL)       /*!< CH0VAGTUTE (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos       (4UL)          /*!< CH0VRTCATE (Bit 4)                                    */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk       (0x10UL)       /*!< CH0VRTCATE (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos        (3UL)          /*!< CH0VRTCTE (Bit 3)                                     */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk        (0x8UL)        /*!< CH0VRTCTE (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos        (2UL)          /*!< CH0VCH2TE (Bit 2)                                     */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk        (0x4UL)        /*!< CH0VCH2TE (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos        (1UL)          /*!< CH0VCH1TE (Bit 1)                                     */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk        (0x2UL)        /*!< CH0VCH1TE (Bitfield-Mask: 0x01)                       */
+/* ======================================================  VBTWCH1OTSR  ====================================================== */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos       (5UL)          /*!< CH1VAGTUTE (Bit 5)                                    */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk       (0x20UL)       /*!< CH1VAGTUTE (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos       (4UL)          /*!< CH1VRTCATE (Bit 4)                                    */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk       (0x10UL)       /*!< CH1VRTCATE (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos        (3UL)          /*!< CH1VRTCTE (Bit 3)                                     */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk        (0x8UL)        /*!< CH1VRTCTE (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos        (2UL)          /*!< CH1VCH2TE (Bit 2)                                     */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk        (0x4UL)        /*!< CH1VCH2TE (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos        (0UL)          /*!< CH1VCH0TE (Bit 0)                                     */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk        (0x1UL)        /*!< CH1VCH0TE (Bitfield-Mask: 0x01)                       */
+/* ======================================================  VBTWCH2OTSR  ====================================================== */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos       (5UL)          /*!< CH2VAGTUTE (Bit 5)                                    */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk       (0x20UL)       /*!< CH2VAGTUTE (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos       (4UL)          /*!< CH2VRTCATE (Bit 4)                                    */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk       (0x10UL)       /*!< CH2VRTCATE (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos        (3UL)          /*!< CH2VRTCTE (Bit 3)                                     */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk        (0x8UL)        /*!< CH2VRTCTE (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos        (1UL)          /*!< CH2VCH1TE (Bit 1)                                     */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk        (0x2UL)        /*!< CH2VCH1TE (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos        (0UL)          /*!< CH2VCH0TE (Bit 0)                                     */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk        (0x1UL)        /*!< CH2VCH0TE (Bitfield-Mask: 0x01)                       */
+/* =======================================================  VBTICTLR  ======================================================== */
+ #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos            (2UL)          /*!< VCH2INEN (Bit 2)                                      */
+ #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk            (0x4UL)        /*!< VCH2INEN (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos            (1UL)          /*!< VCH1INEN (Bit 1)                                      */
+ #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk            (0x2UL)        /*!< VCH1INEN (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos            (0UL)          /*!< VCH0INEN (Bit 0)                                      */
+ #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk            (0x1UL)        /*!< VCH0INEN (Bitfield-Mask: 0x01)                        */
+/* =======================================================  VBTOCTLR  ======================================================== */
+ #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos           (5UL)          /*!< VOUT2LSEL (Bit 5)                                     */
+ #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk           (0x20UL)       /*!< VOUT2LSEL (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos           (4UL)          /*!< VCOU1LSEL (Bit 4)                                     */
+ #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk           (0x10UL)       /*!< VCOU1LSEL (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos           (3UL)          /*!< VOUT0LSEL (Bit 3)                                     */
+ #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk           (0x8UL)        /*!< VOUT0LSEL (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos             (2UL)          /*!< VCH2OEN (Bit 2)                                       */
+ #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk             (0x4UL)        /*!< VCH2OEN (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos             (1UL)          /*!< VCH1OEN (Bit 1)                                       */
+ #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk             (0x2UL)        /*!< VCH1OEN (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos             (0UL)          /*!< VCH0OEN (Bit 0)                                       */
+ #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk             (0x1UL)        /*!< VCH0OEN (Bitfield-Mask: 0x01)                         */
+/* ========================================================  VBTWTER  ======================================================== */
+ #define R_SYSTEM_VBTWTER_VAGTUE_Pos               (5UL)          /*!< VAGTUE (Bit 5)                                        */
+ #define R_SYSTEM_VBTWTER_VAGTUE_Msk               (0x20UL)       /*!< VAGTUE (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWTER_VRTCAE_Pos               (4UL)          /*!< VRTCAE (Bit 4)                                        */
+ #define R_SYSTEM_VBTWTER_VRTCAE_Msk               (0x10UL)       /*!< VRTCAE (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWTER_VRTCIE_Pos               (3UL)          /*!< VRTCIE (Bit 3)                                        */
+ #define R_SYSTEM_VBTWTER_VRTCIE_Msk               (0x8UL)        /*!< VRTCIE (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWTER_VCH2E_Pos                (2UL)          /*!< VCH2E (Bit 2)                                         */
+ #define R_SYSTEM_VBTWTER_VCH2E_Msk                (0x4UL)        /*!< VCH2E (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_VBTWTER_VCH1E_Pos                (1UL)          /*!< VCH1E (Bit 1)                                         */
+ #define R_SYSTEM_VBTWTER_VCH1E_Msk                (0x2UL)        /*!< VCH1E (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_VBTWTER_VCH0E_Pos                (0UL)          /*!< VCH0E (Bit 0)                                         */
+ #define R_SYSTEM_VBTWTER_VCH0E_Msk                (0x1UL)        /*!< VCH0E (Bitfield-Mask: 0x01)                           */
+/* ========================================================  VBTWEGR  ======================================================== */
+ #define R_SYSTEM_VBTWEGR_VCH2EG_Pos               (2UL)          /*!< VCH2EG (Bit 2)                                        */
+ #define R_SYSTEM_VBTWEGR_VCH2EG_Msk               (0x4UL)        /*!< VCH2EG (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWEGR_VCH1EG_Pos               (1UL)          /*!< VCH1EG (Bit 1)                                        */
+ #define R_SYSTEM_VBTWEGR_VCH1EG_Msk               (0x2UL)        /*!< VCH1EG (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWEGR_VCH0EG_Pos               (0UL)          /*!< VCH0EG (Bit 0)                                        */
+ #define R_SYSTEM_VBTWEGR_VCH0EG_Msk               (0x1UL)        /*!< VCH0EG (Bitfield-Mask: 0x01)                          */
+/* ========================================================  VBTWFR  ========================================================= */
+ #define R_SYSTEM_VBTWFR_VAGTUF_Pos                (5UL)          /*!< VAGTUF (Bit 5)                                        */
+ #define R_SYSTEM_VBTWFR_VAGTUF_Msk                (0x20UL)       /*!< VAGTUF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWFR_VRTCAF_Pos                (4UL)          /*!< VRTCAF (Bit 4)                                        */
+ #define R_SYSTEM_VBTWFR_VRTCAF_Msk                (0x10UL)       /*!< VRTCAF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWFR_VRTCIF_Pos                (3UL)          /*!< VRTCIF (Bit 3)                                        */
+ #define R_SYSTEM_VBTWFR_VRTCIF_Msk                (0x8UL)        /*!< VRTCIF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWFR_VCH2F_Pos                 (2UL)          /*!< VCH2F (Bit 2)                                         */
+ #define R_SYSTEM_VBTWFR_VCH2F_Msk                 (0x4UL)        /*!< VCH2F (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_VBTWFR_VCH1F_Pos                 (1UL)          /*!< VCH1F (Bit 1)                                         */
+ #define R_SYSTEM_VBTWFR_VCH1F_Msk                 (0x2UL)        /*!< VCH1F (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_VBTWFR_VCH0F_Pos                 (0UL)          /*!< VCH0F (Bit 0)                                         */
+ #define R_SYSTEM_VBTWFR_VCH0F_Msk                 (0x1UL)        /*!< VCH0F (Bitfield-Mask: 0x01)                           */
+/* ========================================================  VBTBKR  ========================================================= */
+ #define R_SYSTEM_VBTBKR_VBTBKR_Pos                (0UL)          /*!< VBTBKR (Bit 0)                                        */
+ #define R_SYSTEM_VBTBKR_VBTBKR_Msk                (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
+/* ========================================================  FWEPROR  ======================================================== */
+ #define R_SYSTEM_FWEPROR_FLWE_Pos                 (0UL)          /*!< FLWE (Bit 0)                                          */
+ #define R_SYSTEM_FWEPROR_FLWE_Msk                 (0x3UL)        /*!< FLWE (Bitfield-Mask: 0x03)                            */
+/* ========================================================  PLL2CCR  ======================================================== */
+ #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos              (0UL)          /*!< PL2IDIV (Bit 0)                                       */
+ #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk              (0x3UL)        /*!< PL2IDIV (Bitfield-Mask: 0x03)                         */
+ #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos            (4UL)          /*!< PL2SRCSEL (Bit 4)                                     */
+ #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk            (0x10UL)       /*!< PL2SRCSEL (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos              (8UL)          /*!< PLL2MUL (Bit 8)                                       */
+ #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk              (0x3f00UL)     /*!< PLL2MUL (Bitfield-Mask: 0x3f)                         */
+/* ========================================================  PLL2CR  ========================================================= */
+ #define R_SYSTEM_PLL2CR_PLL2STP_Pos               (0UL)          /*!< PLL2STP (Bit 0)                                       */
+ #define R_SYSTEM_PLL2CR_PLL2STP_Msk               (0x1UL)        /*!< PLL2STP (Bitfield-Mask: 0x01)                         */
+/* ======================================================  USBCKDIVCR  ======================================================= */
+ #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos          (0UL)          /*!< USBCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk          (0x7UL)        /*!< USBCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  OCTACKDIVCR  ====================================================== */
+ #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos        (0UL)          /*!< OCTACKDIV (Bit 0)                                     */
+ #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk        (0x7UL)        /*!< OCTACKDIV (Bitfield-Mask: 0x07)                       */
+/* =====================================================  SCISPICKDIVCR  ===================================================== */
+ #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos    (0UL)          /*!< SCISPICKDIV (Bit 0)                                   */
+ #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk    (0x7UL)        /*!< SCISPICKDIV (Bitfield-Mask: 0x07)                     */
+/* =====================================================  CANFDCKDIVCR  ====================================================== */
+ #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos      (0UL)          /*!< CANFDCKDIV (Bit 0)                                    */
+ #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk      (0x7UL)        /*!< CANFDCKDIV (Bitfield-Mask: 0x07)                      */
+/* ======================================================  GPTCKDIVCR  ======================================================= */
+ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos          (0UL)          /*!< GPTCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk          (0x7UL)        /*!< GPTCKDIV (Bitfield-Mask: 0x07)                        */
+/* =====================================================  USB60CKDIVCR  ====================================================== */
+ #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos      (0UL)          /*!< USB60CKDIV (Bit 0)                                    */
+ #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk      (0x7UL)        /*!< USB60CKDIV (Bitfield-Mask: 0x07)                      */
+/* ======================================================  CECCKDIVCR  ======================================================= */
+ #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  I3CCKDIVCR  ======================================================= */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  IICCKDIVCR  ======================================================= */
+ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
+/* ========================================================  USBCKCR  ======================================================== */
+ #define R_SYSTEM_USBCKCR_USBCKSEL_Pos             (0UL)          /*!< USBCKSEL (Bit 0)                                      */
+ #define R_SYSTEM_USBCKCR_USBCKSEL_Msk             (0x7UL)        /*!< USBCKSEL (Bitfield-Mask: 0x07)                        */
+ #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos            (6UL)          /*!< USBCKSREQ (Bit 6)                                     */
+ #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk            (0x40UL)       /*!< USBCKSREQ (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos            (7UL)          /*!< USBCKSRDY (Bit 7)                                     */
+ #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk            (0x80UL)       /*!< USBCKSRDY (Bitfield-Mask: 0x01)                       */
+/* =======================================================  OCTACKCR  ======================================================== */
+ #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos           (0UL)          /*!< OCTACKSEL (Bit 0)                                     */
+ #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk           (0x7UL)        /*!< OCTACKSEL (Bitfield-Mask: 0x07)                       */
+ #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos          (6UL)          /*!< OCTACKSREQ (Bit 6)                                    */
+ #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk          (0x40UL)       /*!< OCTACKSREQ (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos          (7UL)          /*!< OCTACKSRDY (Bit 7)                                    */
+ #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk          (0x80UL)       /*!< OCTACKSRDY (Bitfield-Mask: 0x01)                      */
+/* ======================================================  SCISPICKCR  ======================================================= */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos       (0UL)          /*!< SCISPICKSEL (Bit 0)                                   */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk       (0x7UL)        /*!< SCISPICKSEL (Bitfield-Mask: 0x07)                     */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos      (6UL)          /*!< SCISPICKSREQ (Bit 6)                                  */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk      (0x40UL)       /*!< SCISPICKSREQ (Bitfield-Mask: 0x01)                    */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos      (7UL)          /*!< SCISPICKSRDY (Bit 7)                                  */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk      (0x80UL)       /*!< SCISPICKSRDY (Bitfield-Mask: 0x01)                    */
+/* =======================================================  CANFDCKCR  ======================================================= */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos         (0UL)          /*!< CANFDCKSEL (Bit 0)                                    */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk         (0x7UL)        /*!< CANFDCKSEL (Bitfield-Mask: 0x07)                      */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos        (6UL)          /*!< CANFDCKSREQ (Bit 6)                                   */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk        (0x40UL)       /*!< CANFDCKSREQ (Bitfield-Mask: 0x01)                     */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos        (7UL)          /*!< CANFDCKSRDY (Bit 7)                                   */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk        (0x80UL)       /*!< CANFDCKSRDY (Bitfield-Mask: 0x01)                     */
+/* ========================================================  GPTCKCR  ======================================================== */
+ #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos             (0UL)          /*!< GPTCKSEL (Bit 0)                                      */
+ #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk             (0x7UL)        /*!< GPTCKSEL (Bitfield-Mask: 0x07)                        */
+ #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos            (6UL)          /*!< GPTCKSREQ (Bit 6)                                     */
+ #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk            (0x40UL)       /*!< GPTCKSREQ (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos            (7UL)          /*!< GPTCKSRDY (Bit 7)                                     */
+ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk            (0x80UL)       /*!< GPTCKSRDY (Bitfield-Mask: 0x01)                       */
+/* =======================================================  USB60CKCR  ======================================================= */
+ #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos         (0UL)          /*!< USB60CKSEL (Bit 0)                                    */
+ #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk         (0xfUL)        /*!< USB60CKSEL (Bitfield-Mask: 0x0f)                      */
+ #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos        (6UL)          /*!< USB60CKSREQ (Bit 6)                                   */
+ #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk        (0x40UL)       /*!< USB60CKSREQ (Bitfield-Mask: 0x01)                     */
+ #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos        (7UL)          /*!< USB60CKSRDY (Bit 7)                                   */
+ #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk        (0x80UL)       /*!< USB60CKSRDY (Bitfield-Mask: 0x01)                     */
+/* ========================================================  CECCKCR  ======================================================== */
+ #define R_SYSTEM_CECCKCR_CECCKSEL_Pos             (0UL)          /*!< CECCKSEL (Bit 0)                                      */
+ #define R_SYSTEM_CECCKCR_CECCKSEL_Msk             (0x7UL)        /*!< CECCKSEL (Bitfield-Mask: 0x07)                        */
+ #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos            (6UL)          /*!< CECCKSREQ (Bit 6)                                     */
+ #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk            (0x40UL)       /*!< CECCKSREQ (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos            (7UL)          /*!< CECCKSRDY (Bit 7)                                     */
+ #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk            (0x80UL)       /*!< CECCKSRDY (Bitfield-Mask: 0x01)                       */
+/* ========================================================  IICCKCR  ======================================================== */
+ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos             (0UL)          /*!< IICCKSEL (Bit 0)                                      */
+ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk             (0x7UL)        /*!< IICCKSEL (Bitfield-Mask: 0x07)                        */
+ #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos            (6UL)          /*!< IICCKSREQ (Bit 6)                                     */
+ #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk            (0x40UL)       /*!< IICCKSREQ (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos            (7UL)          /*!< IICCKSRDY (Bit 7)                                     */
+ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk            (0x80UL)       /*!< IICCKSRDY (Bitfield-Mask: 0x01)                       */
+/* ========================================================  I3CCKCR  ======================================================== */
+ #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos             (0UL)          /*!< I3CCKSEL (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk             (0x7UL)        /*!< I3CCKSEL (Bitfield-Mask: 0x07)                        */
+ #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos            (6UL)          /*!< I3CCKSREQ (Bit 6)                                     */
+ #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk            (0x40UL)       /*!< I3CCKSREQ (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos            (7UL)          /*!< I3CCKSRDY (Bit 7)                                     */
+ #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk            (0x80UL)       /*!< I3CCKSRDY (Bitfield-Mask: 0x01)                       */
+/* =======================================================  SNZREQCR1  ======================================================= */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos          (0UL)          /*!< SNZREQEN0 (Bit 0)                                     */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk          (0x1UL)        /*!< SNZREQEN0 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos          (1UL)          /*!< SNZREQEN1 (Bit 1)                                     */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk          (0x2UL)        /*!< SNZREQEN1 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos          (2UL)          /*!< SNZREQEN2 (Bit 2)                                     */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk          (0x4UL)        /*!< SNZREQEN2 (Bitfield-Mask: 0x01)                       */
+/* =======================================================  SNZEDCR1  ======================================================== */
+ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos           (0UL)          /*!< AGT3UNFED (Bit 0)                                     */
+ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk           (0x1UL)        /*!< AGT3UNFED (Bitfield-Mask: 0x01)                       */
+/* ========================================================  CGFSAR  ========================================================= */
+ #define R_SYSTEM_CGFSAR_NONSEC00_Pos              (0UL)          /*!< NONSEC00 (Bit 0)                                      */
+ #define R_SYSTEM_CGFSAR_NONSEC00_Msk              (0x1UL)        /*!< NONSEC00 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC02_Pos              (2UL)          /*!< NONSEC02 (Bit 2)                                      */
+ #define R_SYSTEM_CGFSAR_NONSEC02_Msk              (0x4UL)        /*!< NONSEC02 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC03_Pos              (3UL)          /*!< NONSEC03 (Bit 3)                                      */
+ #define R_SYSTEM_CGFSAR_NONSEC03_Msk              (0x8UL)        /*!< NONSEC03 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC04_Pos              (4UL)          /*!< NONSEC04 (Bit 4)                                      */
+ #define R_SYSTEM_CGFSAR_NONSEC04_Msk              (0x10UL)       /*!< NONSEC04 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC05_Pos              (5UL)          /*!< NONSEC05 (Bit 5)                                      */
+ #define R_SYSTEM_CGFSAR_NONSEC05_Msk              (0x20UL)       /*!< NONSEC05 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC06_Pos              (6UL)          /*!< NONSEC06 (Bit 6)                                      */
+ #define R_SYSTEM_CGFSAR_NONSEC06_Msk              (0x40UL)       /*!< NONSEC06 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC07_Pos              (7UL)          /*!< NONSEC07 (Bit 7)                                      */
+ #define R_SYSTEM_CGFSAR_NONSEC07_Msk              (0x80UL)       /*!< NONSEC07 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC08_Pos              (8UL)          /*!< NONSEC08 (Bit 8)                                      */
+ #define R_SYSTEM_CGFSAR_NONSEC08_Msk              (0x100UL)      /*!< NONSEC08 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC09_Pos              (9UL)          /*!< NONSEC09 (Bit 9)                                      */
+ #define R_SYSTEM_CGFSAR_NONSEC09_Msk              (0x200UL)      /*!< NONSEC09 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC11_Pos              (11UL)         /*!< NONSEC11 (Bit 11)                                     */
+ #define R_SYSTEM_CGFSAR_NONSEC11_Msk              (0x800UL)      /*!< NONSEC11 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC12_Pos              (12UL)         /*!< NONSEC12 (Bit 12)                                     */
+ #define R_SYSTEM_CGFSAR_NONSEC12_Msk              (0x1000UL)     /*!< NONSEC12 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC16_Pos              (16UL)         /*!< NONSEC16 (Bit 16)                                     */
+ #define R_SYSTEM_CGFSAR_NONSEC16_Msk              (0x10000UL)    /*!< NONSEC16 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC17_Pos              (17UL)         /*!< NONSEC17 (Bit 17)                                     */
+ #define R_SYSTEM_CGFSAR_NONSEC17_Msk              (0x20000UL)    /*!< NONSEC17 (Bitfield-Mask: 0x01)                        */
+/* ========================================================  LPMSAR  ========================================================= */
+ #define R_SYSTEM_LPMSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
+ #define R_SYSTEM_LPMSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_LPMSAR_NONSEC2_Pos               (2UL)          /*!< NONSEC2 (Bit 2)                                       */
+ #define R_SYSTEM_LPMSAR_NONSEC2_Msk               (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_LPMSAR_NONSEC4_Pos               (4UL)          /*!< NONSEC4 (Bit 4)                                       */
+ #define R_SYSTEM_LPMSAR_NONSEC4_Msk               (0x10UL)       /*!< NONSEC4 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_LPMSAR_NONSEC8_Pos               (8UL)          /*!< NONSEC8 (Bit 8)                                       */
+ #define R_SYSTEM_LPMSAR_NONSEC8_Msk               (0x100UL)      /*!< NONSEC8 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_LPMSAR_NONSEC9_Pos               (9UL)          /*!< NONSEC9 (Bit 9)                                       */
+ #define R_SYSTEM_LPMSAR_NONSEC9_Msk               (0x200UL)      /*!< NONSEC9 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  LVDSAR  ========================================================= */
+ #define R_SYSTEM_LVDSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
+ #define R_SYSTEM_LVDSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_LVDSAR_NONSEC1_Pos               (1UL)          /*!< NONSEC1 (Bit 1)                                       */
+ #define R_SYSTEM_LVDSAR_NONSEC1_Msk               (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  RSTSAR  ========================================================= */
+ #define R_SYSTEM_RSTSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
+ #define R_SYSTEM_RSTSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_RSTSAR_NONSEC1_Pos               (1UL)          /*!< NONSEC1 (Bit 1)                                       */
+ #define R_SYSTEM_RSTSAR_NONSEC1_Msk               (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_RSTSAR_NONSEC2_Pos               (2UL)          /*!< NONSEC2 (Bit 2)                                       */
+ #define R_SYSTEM_RSTSAR_NONSEC2_Msk               (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  BBFSAR  ========================================================= */
+ #define R_SYSTEM_BBFSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
+ #define R_SYSTEM_BBFSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_BBFSAR_NONSEC1_Pos               (1UL)          /*!< NONSEC1 (Bit 1)                                       */
+ #define R_SYSTEM_BBFSAR_NONSEC1_Msk               (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_BBFSAR_NONSEC2_Pos               (2UL)          /*!< NONSEC2 (Bit 2)                                       */
+ #define R_SYSTEM_BBFSAR_NONSEC2_Msk               (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_BBFSAR_NONSEC16_Pos              (16UL)         /*!< NONSEC16 (Bit 16)                                     */
+ #define R_SYSTEM_BBFSAR_NONSEC16_Msk              (0x10000UL)    /*!< NONSEC16 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_BBFSAR_NONSEC17_Pos              (17UL)         /*!< NONSEC17 (Bit 17)                                     */
+ #define R_SYSTEM_BBFSAR_NONSEC17_Msk              (0x20000UL)    /*!< NONSEC17 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_BBFSAR_NONSEC18_Pos              (18UL)         /*!< NONSEC18 (Bit 18)                                     */
+ #define R_SYSTEM_BBFSAR_NONSEC18_Msk              (0x40000UL)    /*!< NONSEC18 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_BBFSAR_NONSEC19_Pos              (19UL)         /*!< NONSEC19 (Bit 19)                                     */
+ #define R_SYSTEM_BBFSAR_NONSEC19_Msk              (0x80000UL)    /*!< NONSEC19 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_BBFSAR_NONSEC20_Pos              (20UL)         /*!< NONSEC20 (Bit 20)                                     */
+ #define R_SYSTEM_BBFSAR_NONSEC20_Msk              (0x100000UL)   /*!< NONSEC20 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_BBFSAR_NONSEC21_Pos              (21UL)         /*!< NONSEC21 (Bit 21)                                     */
+ #define R_SYSTEM_BBFSAR_NONSEC21_Msk              (0x200000UL)   /*!< NONSEC21 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_BBFSAR_NONSEC22_Pos              (22UL)         /*!< NONSEC22 (Bit 22)                                     */
+ #define R_SYSTEM_BBFSAR_NONSEC22_Msk              (0x400000UL)   /*!< NONSEC22 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_BBFSAR_NONSEC23_Pos              (23UL)         /*!< NONSEC23 (Bit 23)                                     */
+ #define R_SYSTEM_BBFSAR_NONSEC23_Msk              (0x800000UL)   /*!< NONSEC23 (Bitfield-Mask: 0x01)                        */
+/* ========================================================  DPFSAR  ========================================================= */
+ #define R_SYSTEM_DPFSAR_DPFSA0_Pos                (0UL)          /*!< DPFSA0 (Bit 0)                                        */
+ #define R_SYSTEM_DPFSAR_DPFSA0_Msk                (0x1UL)        /*!< DPFSA0 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPFSAR_DPFSA1_Pos                (1UL)          /*!< DPFSA1 (Bit 1)                                        */
+ #define R_SYSTEM_DPFSAR_DPFSA1_Msk                (0x2UL)        /*!< DPFSA1 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPFSAR_DPFSA2_Pos                (2UL)          /*!< DPFSA2 (Bit 2)                                        */
+ #define R_SYSTEM_DPFSAR_DPFSA2_Msk                (0x4UL)        /*!< DPFSA2 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPFSAR_DPFSA3_Pos                (3UL)          /*!< DPFSA3 (Bit 3)                                        */
+ #define R_SYSTEM_DPFSAR_DPFSA3_Msk                (0x8UL)        /*!< DPFSA3 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPFSAR_DPFSA4_Pos                (4UL)          /*!< DPFSA4 (Bit 4)                                        */
+ #define R_SYSTEM_DPFSAR_DPFSA4_Msk                (0x10UL)       /*!< DPFSA4 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPFSAR_DPFSA5_Pos                (5UL)          /*!< DPFSA5 (Bit 5)                                        */
+ #define R_SYSTEM_DPFSAR_DPFSA5_Msk                (0x20UL)       /*!< DPFSA5 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPFSAR_DPFSA6_Pos                (6UL)          /*!< DPFSA6 (Bit 6)                                        */
+ #define R_SYSTEM_DPFSAR_DPFSA6_Msk                (0x40UL)       /*!< DPFSA6 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPFSAR_DPFSA7_Pos                (7UL)          /*!< DPFSA7 (Bit 7)                                        */
+ #define R_SYSTEM_DPFSAR_DPFSA7_Msk                (0x80UL)       /*!< DPFSA7 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPFSAR_DPFSA8_Pos                (8UL)          /*!< DPFSA8 (Bit 8)                                        */
+ #define R_SYSTEM_DPFSAR_DPFSA8_Msk                (0x100UL)      /*!< DPFSA8 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPFSAR_DPFSA9_Pos                (9UL)          /*!< DPFSA9 (Bit 9)                                        */
+ #define R_SYSTEM_DPFSAR_DPFSA9_Msk                (0x200UL)      /*!< DPFSA9 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPFSAR_DPFSA10_Pos               (10UL)         /*!< DPFSA10 (Bit 10)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA10_Msk               (0x400UL)      /*!< DPFSA10 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA11_Pos               (11UL)         /*!< DPFSA11 (Bit 11)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA11_Msk               (0x800UL)      /*!< DPFSA11 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA12_Pos               (12UL)         /*!< DPFSA12 (Bit 12)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA12_Msk               (0x1000UL)     /*!< DPFSA12 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA13_Pos               (13UL)         /*!< DPFSA13 (Bit 13)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA13_Msk               (0x2000UL)     /*!< DPFSA13 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA14_Pos               (14UL)         /*!< DPFSA14 (Bit 14)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA14_Msk               (0x4000UL)     /*!< DPFSA14 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA15_Pos               (15UL)         /*!< DPFSA15 (Bit 15)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA15_Msk               (0x8000UL)     /*!< DPFSA15 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA16_Pos               (16UL)         /*!< DPFSA16 (Bit 16)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA16_Msk               (0x10000UL)    /*!< DPFSA16 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA17_Pos               (17UL)         /*!< DPFSA17 (Bit 17)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA17_Msk               (0x20000UL)    /*!< DPFSA17 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA18_Pos               (18UL)         /*!< DPFSA18 (Bit 18)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA18_Msk               (0x40000UL)    /*!< DPFSA18 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA19_Pos               (19UL)         /*!< DPFSA19 (Bit 19)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA19_Msk               (0x80000UL)    /*!< DPFSA19 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA20_Pos               (20UL)         /*!< DPFSA20 (Bit 20)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA20_Msk               (0x100000UL)   /*!< DPFSA20 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA24_Pos               (24UL)         /*!< DPFSA24 (Bit 24)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA24_Msk               (0x1000000UL)  /*!< DPFSA24 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA26_Pos               (26UL)         /*!< DPFSA26 (Bit 26)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA26_Msk               (0x4000000UL)  /*!< DPFSA26 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA27_Pos               (27UL)         /*!< DPFSA27 (Bit 27)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA27_Msk               (0x8000000UL)  /*!< DPFSA27 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DPSWCR  ========================================================= */
+ #define R_SYSTEM_DPSWCR_WTSTS_Pos                 (0UL)          /*!< WTSTS (Bit 0)                                         */
+ #define R_SYSTEM_DPSWCR_WTSTS_Msk                 (0x3fUL)       /*!< WTSTS (Bitfield-Mask: 0x3f)                           */
+/* ======================================================  VBATTMNSELR  ====================================================== */
+ #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos       (0UL)          /*!< VBATTMNSEL (Bit 0)                                    */
+ #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk       (0x1UL)        /*!< VBATTMNSEL (Bitfield-Mask: 0x01)                      */
+/* =======================================================  VBATTMONR  ======================================================= */
+ #define R_SYSTEM_VBATTMONR_VBATTMON_Pos           (0UL)          /*!< VBATTMON (Bit 0)                                      */
+ #define R_SYSTEM_VBATTMONR_VBATTMON_Msk           (0x1UL)        /*!< VBATTMON (Bitfield-Mask: 0x01)                        */
+/* ========================================================  VBTBER  ========================================================= */
+ #define R_SYSTEM_VBTBER_VBAE_Pos                  (3UL)          /*!< VBAE (Bit 3)                                          */
+ #define R_SYSTEM_VBTBER_VBAE_Msk                  (0x8UL)        /*!< VBAE (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_TSN_CAL                                         ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  TSCDR  ========================================================= */
+ #define R_TSN_CAL_TSCDR_TSCDR_Pos    (0UL)          /*!< TSCDR (Bit 0)                                         */
+ #define R_TSN_CAL_TSCDR_TSCDR_Msk    (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff)                     */
+
+/* =========================================================================================================================== */
+/* ================                                        R_TSN_CTRL                                         ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  TSCR  ========================================================== */
+ #define R_TSN_CTRL_TSCR_TSEN_Pos    (7UL)    /*!< TSEN (Bit 7)                                          */
+ #define R_TSN_CTRL_TSCR_TSEN_Msk    (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01)                            */
+ #define R_TSN_CTRL_TSCR_TSOE_Pos    (4UL)    /*!< TSOE (Bit 4)                                          */
+ #define R_TSN_CTRL_TSCR_TSOE_Msk    (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_USB_FS0                                         ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  SYSCFG  ========================================================= */
+ #define R_USB_FS0_SYSCFG_SCKE_Pos         (10UL)     /*!< SCKE (Bit 10)                                         */
+ #define R_USB_FS0_SYSCFG_SCKE_Msk         (0x400UL)  /*!< SCKE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_SYSCFG_CNEN_Pos         (8UL)      /*!< CNEN (Bit 8)                                          */
+ #define R_USB_FS0_SYSCFG_CNEN_Msk         (0x100UL)  /*!< CNEN (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_SYSCFG_DCFM_Pos         (6UL)      /*!< DCFM (Bit 6)                                          */
+ #define R_USB_FS0_SYSCFG_DCFM_Msk         (0x40UL)   /*!< DCFM (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_SYSCFG_DRPD_Pos         (5UL)      /*!< DRPD (Bit 5)                                          */
+ #define R_USB_FS0_SYSCFG_DRPD_Msk         (0x20UL)   /*!< DRPD (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_SYSCFG_DPRPU_Pos        (4UL)      /*!< DPRPU (Bit 4)                                         */
+ #define R_USB_FS0_SYSCFG_DPRPU_Msk        (0x10UL)   /*!< DPRPU (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_SYSCFG_DMRPU_Pos        (3UL)      /*!< DMRPU (Bit 3)                                         */
+ #define R_USB_FS0_SYSCFG_DMRPU_Msk        (0x8UL)    /*!< DMRPU (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_SYSCFG_USBE_Pos         (0UL)      /*!< USBE (Bit 0)                                          */
+ #define R_USB_FS0_SYSCFG_USBE_Msk         (0x1UL)    /*!< USBE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  BUSWAIT  ======================================================== */
+ #define R_USB_FS0_BUSWAIT_BWAIT_Pos       (0UL)      /*!< BWAIT (Bit 0)                                         */
+ #define R_USB_FS0_BUSWAIT_BWAIT_Msk       (0xfUL)    /*!< BWAIT (Bitfield-Mask: 0x0f)                           */
+/* ========================================================  SYSSTS0  ======================================================== */
+ #define R_USB_FS0_SYSSTS0_OVCMON_Pos      (14UL)     /*!< OVCMON (Bit 14)                                       */
+ #define R_USB_FS0_SYSSTS0_OVCMON_Msk      (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03)                          */
+ #define R_USB_FS0_SYSSTS0_HTACT_Pos       (6UL)      /*!< HTACT (Bit 6)                                         */
+ #define R_USB_FS0_SYSSTS0_HTACT_Msk       (0x40UL)   /*!< HTACT (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_SYSSTS0_SOFEA_Pos       (5UL)      /*!< SOFEA (Bit 5)                                         */
+ #define R_USB_FS0_SYSSTS0_SOFEA_Msk       (0x20UL)   /*!< SOFEA (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_SYSSTS0_IDMON_Pos       (2UL)      /*!< IDMON (Bit 2)                                         */
+ #define R_USB_FS0_SYSSTS0_IDMON_Msk       (0x4UL)    /*!< IDMON (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_SYSSTS0_LNST_Pos        (0UL)      /*!< LNST (Bit 0)                                          */
+ #define R_USB_FS0_SYSSTS0_LNST_Msk        (0x3UL)    /*!< LNST (Bitfield-Mask: 0x03)                            */
+/* ========================================================  PLLSTA  ========================================================= */
+ #define R_USB_FS0_PLLSTA_PLLLOCK_Pos      (0UL)      /*!< PLLLOCK (Bit 0)                                       */
+ #define R_USB_FS0_PLLSTA_PLLLOCK_Msk      (0x1UL)    /*!< PLLLOCK (Bitfield-Mask: 0x01)                         */
+/* =======================================================  DVSTCTR0  ======================================================== */
+ #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos    (11UL)     /*!< HNPBTOA (Bit 11)                                      */
+ #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk    (0x800UL)  /*!< HNPBTOA (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DVSTCTR0_EXICEN_Pos     (10UL)     /*!< EXICEN (Bit 10)                                       */
+ #define R_USB_FS0_DVSTCTR0_EXICEN_Msk     (0x400UL)  /*!< EXICEN (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos     (9UL)      /*!< VBUSEN (Bit 9)                                        */
+ #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk     (0x200UL)  /*!< VBUSEN (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DVSTCTR0_WKUP_Pos       (8UL)      /*!< WKUP (Bit 8)                                          */
+ #define R_USB_FS0_DVSTCTR0_WKUP_Msk       (0x100UL)  /*!< WKUP (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_DVSTCTR0_RWUPE_Pos      (7UL)      /*!< RWUPE (Bit 7)                                         */
+ #define R_USB_FS0_DVSTCTR0_RWUPE_Msk      (0x80UL)   /*!< RWUPE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DVSTCTR0_USBRST_Pos     (6UL)      /*!< USBRST (Bit 6)                                        */
+ #define R_USB_FS0_DVSTCTR0_USBRST_Msk     (0x40UL)   /*!< USBRST (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DVSTCTR0_RESUME_Pos     (5UL)      /*!< RESUME (Bit 5)                                        */
+ #define R_USB_FS0_DVSTCTR0_RESUME_Msk     (0x20UL)   /*!< RESUME (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DVSTCTR0_UACT_Pos       (4UL)      /*!< UACT (Bit 4)                                          */
+ #define R_USB_FS0_DVSTCTR0_UACT_Msk       (0x10UL)   /*!< UACT (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_DVSTCTR0_RHST_Pos       (0UL)      /*!< RHST (Bit 0)                                          */
+ #define R_USB_FS0_DVSTCTR0_RHST_Msk       (0x7UL)    /*!< RHST (Bitfield-Mask: 0x07)                            */
+/* =======================================================  TESTMODE  ======================================================== */
+ #define R_USB_FS0_TESTMODE_UTST_Pos       (0UL)      /*!< UTST (Bit 0)                                          */
+ #define R_USB_FS0_TESTMODE_UTST_Msk       (0xfUL)    /*!< UTST (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  CFIFOL  ========================================================= */
+/* ========================================================  CFIFOLL  ======================================================== */
+/* =========================================================  CFIFO  ========================================================= */
+/* ========================================================  CFIFOH  ========================================================= */
+/* ========================================================  CFIFOHH  ======================================================== */
+/* ========================================================  D0FIFOL  ======================================================== */
+/* =======================================================  D0FIFOLL  ======================================================== */
+/* ========================================================  D0FIFO  ========================================================= */
+/* ========================================================  D0FIFOH  ======================================================== */
+/* =======================================================  D0FIFOHH  ======================================================== */
+/* ========================================================  D1FIFOL  ======================================================== */
+/* =======================================================  D1FIFOLL  ======================================================== */
+/* ========================================================  D1FIFO  ========================================================= */
+/* ========================================================  D1FIFOH  ======================================================== */
+/* =======================================================  D1FIFOHH  ======================================================== */
+/* =======================================================  CFIFOSEL  ======================================================== */
+ #define R_USB_FS0_CFIFOSEL_RCNT_Pos            (15UL)       /*!< RCNT (Bit 15)                                         */
+ #define R_USB_FS0_CFIFOSEL_RCNT_Msk            (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_CFIFOSEL_REW_Pos             (14UL)       /*!< REW (Bit 14)                                          */
+ #define R_USB_FS0_CFIFOSEL_REW_Msk             (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
+ #define R_USB_FS0_CFIFOSEL_MBW_Pos             (10UL)       /*!< MBW (Bit 10)                                          */
+ #define R_USB_FS0_CFIFOSEL_MBW_Msk             (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
+ #define R_USB_FS0_CFIFOSEL_BIGEND_Pos          (8UL)        /*!< BIGEND (Bit 8)                                        */
+ #define R_USB_FS0_CFIFOSEL_BIGEND_Msk          (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_CFIFOSEL_ISEL_Pos            (5UL)        /*!< ISEL (Bit 5)                                          */
+ #define R_USB_FS0_CFIFOSEL_ISEL_Msk            (0x20UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos         (0UL)        /*!< CURPIPE (Bit 0)                                       */
+ #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk         (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  CFIFOCTR  ======================================================== */
+ #define R_USB_FS0_CFIFOCTR_BVAL_Pos            (15UL)       /*!< BVAL (Bit 15)                                         */
+ #define R_USB_FS0_CFIFOCTR_BVAL_Msk            (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_CFIFOCTR_BCLR_Pos            (14UL)       /*!< BCLR (Bit 14)                                         */
+ #define R_USB_FS0_CFIFOCTR_BCLR_Msk            (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_CFIFOCTR_FRDY_Pos            (13UL)       /*!< FRDY (Bit 13)                                         */
+ #define R_USB_FS0_CFIFOCTR_FRDY_Msk            (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_CFIFOCTR_DTLN_Pos            (0UL)        /*!< DTLN (Bit 0)                                          */
+ #define R_USB_FS0_CFIFOCTR_DTLN_Msk            (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
+/* =======================================================  D0FIFOSEL  ======================================================= */
+ #define R_USB_FS0_D0FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
+ #define R_USB_FS0_D0FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D0FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
+ #define R_USB_FS0_D0FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
+ #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
+ #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_D0FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
+ #define R_USB_FS0_D0FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_D0FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
+ #define R_USB_FS0_D0FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
+ #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
+ #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
+ #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  D0FIFOCTR  ======================================================= */
+ #define R_USB_FS0_D0FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
+ #define R_USB_FS0_D0FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D0FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
+ #define R_USB_FS0_D0FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D0FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
+ #define R_USB_FS0_D0FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D0FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
+ #define R_USB_FS0_D0FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
+/* =======================================================  D1FIFOSEL  ======================================================= */
+ #define R_USB_FS0_D1FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
+ #define R_USB_FS0_D1FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D1FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
+ #define R_USB_FS0_D1FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
+ #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
+ #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_D1FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
+ #define R_USB_FS0_D1FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_D1FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
+ #define R_USB_FS0_D1FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
+ #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
+ #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
+ #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  D1FIFOCTR  ======================================================= */
+ #define R_USB_FS0_D1FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
+ #define R_USB_FS0_D1FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D1FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
+ #define R_USB_FS0_D1FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D1FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
+ #define R_USB_FS0_D1FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D1FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
+ #define R_USB_FS0_D1FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
+/* ========================================================  INTENB0  ======================================================== */
+ #define R_USB_FS0_INTENB0_VBSE_Pos             (15UL)       /*!< VBSE (Bit 15)                                         */
+ #define R_USB_FS0_INTENB0_VBSE_Msk             (0x8000UL)   /*!< VBSE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTENB0_RSME_Pos             (14UL)       /*!< RSME (Bit 14)                                         */
+ #define R_USB_FS0_INTENB0_RSME_Msk             (0x4000UL)   /*!< RSME (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTENB0_SOFE_Pos             (13UL)       /*!< SOFE (Bit 13)                                         */
+ #define R_USB_FS0_INTENB0_SOFE_Msk             (0x2000UL)   /*!< SOFE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTENB0_DVSE_Pos             (12UL)       /*!< DVSE (Bit 12)                                         */
+ #define R_USB_FS0_INTENB0_DVSE_Msk             (0x1000UL)   /*!< DVSE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTENB0_CTRE_Pos             (11UL)       /*!< CTRE (Bit 11)                                         */
+ #define R_USB_FS0_INTENB0_CTRE_Msk             (0x800UL)    /*!< CTRE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTENB0_BEMPE_Pos            (10UL)       /*!< BEMPE (Bit 10)                                        */
+ #define R_USB_FS0_INTENB0_BEMPE_Msk            (0x400UL)    /*!< BEMPE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTENB0_NRDYE_Pos            (9UL)        /*!< NRDYE (Bit 9)                                         */
+ #define R_USB_FS0_INTENB0_NRDYE_Msk            (0x200UL)    /*!< NRDYE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTENB0_BRDYE_Pos            (8UL)        /*!< BRDYE (Bit 8)                                         */
+ #define R_USB_FS0_INTENB0_BRDYE_Msk            (0x100UL)    /*!< BRDYE (Bitfield-Mask: 0x01)                           */
+/* ========================================================  INTENB1  ======================================================== */
+ #define R_USB_FS0_INTENB1_OVRCRE_Pos           (15UL)       /*!< OVRCRE (Bit 15)                                       */
+ #define R_USB_FS0_INTENB1_OVRCRE_Msk           (0x8000UL)   /*!< OVRCRE (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_INTENB1_BCHGE_Pos            (14UL)       /*!< BCHGE (Bit 14)                                        */
+ #define R_USB_FS0_INTENB1_BCHGE_Msk            (0x4000UL)   /*!< BCHGE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTENB1_DTCHE_Pos            (12UL)       /*!< DTCHE (Bit 12)                                        */
+ #define R_USB_FS0_INTENB1_DTCHE_Msk            (0x1000UL)   /*!< DTCHE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTENB1_ATTCHE_Pos           (11UL)       /*!< ATTCHE (Bit 11)                                       */
+ #define R_USB_FS0_INTENB1_ATTCHE_Msk           (0x800UL)    /*!< ATTCHE (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_INTENB1_EOFERRE_Pos          (6UL)        /*!< EOFERRE (Bit 6)                                       */
+ #define R_USB_FS0_INTENB1_EOFERRE_Msk          (0x40UL)     /*!< EOFERRE (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_INTENB1_SIGNE_Pos            (5UL)        /*!< SIGNE (Bit 5)                                         */
+ #define R_USB_FS0_INTENB1_SIGNE_Msk            (0x20UL)     /*!< SIGNE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTENB1_SACKE_Pos            (4UL)        /*!< SACKE (Bit 4)                                         */
+ #define R_USB_FS0_INTENB1_SACKE_Msk            (0x10UL)     /*!< SACKE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTENB1_PDDETINTE0_Pos       (0UL)        /*!< PDDETINTE0 (Bit 0)                                    */
+ #define R_USB_FS0_INTENB1_PDDETINTE0_Msk       (0x1UL)      /*!< PDDETINTE0 (Bitfield-Mask: 0x01)                      */
+/* ========================================================  BRDYENB  ======================================================== */
+ #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos        (0UL)        /*!< PIPEBRDYE (Bit 0)                                     */
+ #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk        (0x1UL)      /*!< PIPEBRDYE (Bitfield-Mask: 0x01)                       */
+/* ========================================================  NRDYENB  ======================================================== */
+ #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos        (0UL)        /*!< PIPENRDYE (Bit 0)                                     */
+ #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk        (0x1UL)      /*!< PIPENRDYE (Bitfield-Mask: 0x01)                       */
+/* ========================================================  BEMPENB  ======================================================== */
+ #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos        (0UL)        /*!< PIPEBEMPE (Bit 0)                                     */
+ #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk        (0x1UL)      /*!< PIPEBEMPE (Bitfield-Mask: 0x01)                       */
+/* ========================================================  SOFCFG  ========================================================= */
+ #define R_USB_FS0_SOFCFG_TRNENSEL_Pos          (8UL)        /*!< TRNENSEL (Bit 8)                                      */
+ #define R_USB_FS0_SOFCFG_TRNENSEL_Msk          (0x100UL)    /*!< TRNENSEL (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_SOFCFG_BRDYM_Pos             (6UL)        /*!< BRDYM (Bit 6)                                         */
+ #define R_USB_FS0_SOFCFG_BRDYM_Msk             (0x40UL)     /*!< BRDYM (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_SOFCFG_INTL_Pos              (5UL)        /*!< INTL (Bit 5)                                          */
+ #define R_USB_FS0_SOFCFG_INTL_Msk              (0x20UL)     /*!< INTL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_SOFCFG_EDGESTS_Pos           (4UL)        /*!< EDGESTS (Bit 4)                                       */
+ #define R_USB_FS0_SOFCFG_EDGESTS_Msk           (0x10UL)     /*!< EDGESTS (Bitfield-Mask: 0x01)                         */
+/* ========================================================  PHYSET  ========================================================= */
+ #define R_USB_FS0_PHYSET_HSEB_Pos              (15UL)       /*!< HSEB (Bit 15)                                         */
+ #define R_USB_FS0_PHYSET_HSEB_Msk              (0x8000UL)   /*!< HSEB (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_PHYSET_REPSTART_Pos          (11UL)       /*!< REPSTART (Bit 11)                                     */
+ #define R_USB_FS0_PHYSET_REPSTART_Msk          (0x800UL)    /*!< REPSTART (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_PHYSET_REPSEL_Pos            (8UL)        /*!< REPSEL (Bit 8)                                        */
+ #define R_USB_FS0_PHYSET_REPSEL_Msk            (0x300UL)    /*!< REPSEL (Bitfield-Mask: 0x03)                          */
+ #define R_USB_FS0_PHYSET_CLKSEL_Pos            (4UL)        /*!< CLKSEL (Bit 4)                                        */
+ #define R_USB_FS0_PHYSET_CLKSEL_Msk            (0x30UL)     /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
+ #define R_USB_FS0_PHYSET_CDPEN_Pos             (3UL)        /*!< CDPEN (Bit 3)                                         */
+ #define R_USB_FS0_PHYSET_CDPEN_Msk             (0x8UL)      /*!< CDPEN (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PHYSET_PLLRESET_Pos          (1UL)        /*!< PLLRESET (Bit 1)                                      */
+ #define R_USB_FS0_PHYSET_PLLRESET_Msk          (0x2UL)      /*!< PLLRESET (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_PHYSET_DIRPD_Pos             (0UL)        /*!< DIRPD (Bit 0)                                         */
+ #define R_USB_FS0_PHYSET_DIRPD_Msk             (0x1UL)      /*!< DIRPD (Bitfield-Mask: 0x01)                           */
+/* ========================================================  INTSTS0  ======================================================== */
+ #define R_USB_FS0_INTSTS0_VBINT_Pos            (15UL)       /*!< VBINT (Bit 15)                                        */
+ #define R_USB_FS0_INTSTS0_VBINT_Msk            (0x8000UL)   /*!< VBINT (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTSTS0_RESM_Pos             (14UL)       /*!< RESM (Bit 14)                                         */
+ #define R_USB_FS0_INTSTS0_RESM_Msk             (0x4000UL)   /*!< RESM (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_SOFR_Pos             (13UL)       /*!< SOFR (Bit 13)                                         */
+ #define R_USB_FS0_INTSTS0_SOFR_Msk             (0x2000UL)   /*!< SOFR (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_DVST_Pos             (12UL)       /*!< DVST (Bit 12)                                         */
+ #define R_USB_FS0_INTSTS0_DVST_Msk             (0x1000UL)   /*!< DVST (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_CTRT_Pos             (11UL)       /*!< CTRT (Bit 11)                                         */
+ #define R_USB_FS0_INTSTS0_CTRT_Msk             (0x800UL)    /*!< CTRT (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_BEMP_Pos             (10UL)       /*!< BEMP (Bit 10)                                         */
+ #define R_USB_FS0_INTSTS0_BEMP_Msk             (0x400UL)    /*!< BEMP (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_NRDY_Pos             (9UL)        /*!< NRDY (Bit 9)                                          */
+ #define R_USB_FS0_INTSTS0_NRDY_Msk             (0x200UL)    /*!< NRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_BRDY_Pos             (8UL)        /*!< BRDY (Bit 8)                                          */
+ #define R_USB_FS0_INTSTS0_BRDY_Msk             (0x100UL)    /*!< BRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_VBSTS_Pos            (7UL)        /*!< VBSTS (Bit 7)                                         */
+ #define R_USB_FS0_INTSTS0_VBSTS_Msk            (0x80UL)     /*!< VBSTS (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTSTS0_DVSQ_Pos             (4UL)        /*!< DVSQ (Bit 4)                                          */
+ #define R_USB_FS0_INTSTS0_DVSQ_Msk             (0x70UL)     /*!< DVSQ (Bitfield-Mask: 0x07)                            */
+ #define R_USB_FS0_INTSTS0_VALID_Pos            (3UL)        /*!< VALID (Bit 3)                                         */
+ #define R_USB_FS0_INTSTS0_VALID_Msk            (0x8UL)      /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTSTS0_CTSQ_Pos             (0UL)        /*!< CTSQ (Bit 0)                                          */
+ #define R_USB_FS0_INTSTS0_CTSQ_Msk             (0x7UL)      /*!< CTSQ (Bitfield-Mask: 0x07)                            */
+/* ========================================================  INTSTS1  ======================================================== */
+ #define R_USB_FS0_INTSTS1_OVRCR_Pos            (15UL)       /*!< OVRCR (Bit 15)                                        */
+ #define R_USB_FS0_INTSTS1_OVRCR_Msk            (0x8000UL)   /*!< OVRCR (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTSTS1_BCHG_Pos             (14UL)       /*!< BCHG (Bit 14)                                         */
+ #define R_USB_FS0_INTSTS1_BCHG_Msk             (0x4000UL)   /*!< BCHG (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS1_DTCH_Pos             (12UL)       /*!< DTCH (Bit 12)                                         */
+ #define R_USB_FS0_INTSTS1_DTCH_Msk             (0x1000UL)   /*!< DTCH (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS1_ATTCH_Pos            (11UL)       /*!< ATTCH (Bit 11)                                        */
+ #define R_USB_FS0_INTSTS1_ATTCH_Msk            (0x800UL)    /*!< ATTCH (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTSTS1_L1RSMEND_Pos         (9UL)        /*!< L1RSMEND (Bit 9)                                      */
+ #define R_USB_FS0_INTSTS1_L1RSMEND_Msk         (0x200UL)    /*!< L1RSMEND (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_INTSTS1_LPMEND_Pos           (8UL)        /*!< LPMEND (Bit 8)                                        */
+ #define R_USB_FS0_INTSTS1_LPMEND_Msk           (0x100UL)    /*!< LPMEND (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_INTSTS1_EOFERR_Pos           (6UL)        /*!< EOFERR (Bit 6)                                        */
+ #define R_USB_FS0_INTSTS1_EOFERR_Msk           (0x40UL)     /*!< EOFERR (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_INTSTS1_SIGN_Pos             (5UL)        /*!< SIGN (Bit 5)                                          */
+ #define R_USB_FS0_INTSTS1_SIGN_Msk             (0x20UL)     /*!< SIGN (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS1_SACK_Pos             (4UL)        /*!< SACK (Bit 4)                                          */
+ #define R_USB_FS0_INTSTS1_SACK_Msk             (0x10UL)     /*!< SACK (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS1_PDDETINT0_Pos        (0UL)        /*!< PDDETINT0 (Bit 0)                                     */
+ #define R_USB_FS0_INTSTS1_PDDETINT0_Msk        (0x1UL)      /*!< PDDETINT0 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  BRDYSTS  ======================================================== */
+ #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos         (0UL)        /*!< PIPEBRDY (Bit 0)                                      */
+ #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk         (0x1UL)      /*!< PIPEBRDY (Bitfield-Mask: 0x01)                        */
+/* ========================================================  NRDYSTS  ======================================================== */
+ #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos         (0UL)        /*!< PIPENRDY (Bit 0)                                      */
+ #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk         (0x1UL)      /*!< PIPENRDY (Bitfield-Mask: 0x01)                        */
+/* ========================================================  BEMPSTS  ======================================================== */
+ #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos         (0UL)        /*!< PIPEBEMP (Bit 0)                                      */
+ #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk         (0x1UL)      /*!< PIPEBEMP (Bitfield-Mask: 0x01)                        */
+/* ========================================================  FRMNUM  ========================================================= */
+ #define R_USB_FS0_FRMNUM_OVRN_Pos              (15UL)       /*!< OVRN (Bit 15)                                         */
+ #define R_USB_FS0_FRMNUM_OVRN_Msk              (0x8000UL)   /*!< OVRN (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_FRMNUM_CRCE_Pos              (14UL)       /*!< CRCE (Bit 14)                                         */
+ #define R_USB_FS0_FRMNUM_CRCE_Msk              (0x4000UL)   /*!< CRCE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_FRMNUM_FRNM_Pos              (0UL)        /*!< FRNM (Bit 0)                                          */
+ #define R_USB_FS0_FRMNUM_FRNM_Msk              (0x7ffUL)    /*!< FRNM (Bitfield-Mask: 0x7ff)                           */
+/* ========================================================  UFRMNUM  ======================================================== */
+ #define R_USB_FS0_UFRMNUM_DVCHG_Pos            (15UL)       /*!< DVCHG (Bit 15)                                        */
+ #define R_USB_FS0_UFRMNUM_DVCHG_Msk            (0x8000UL)   /*!< DVCHG (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_UFRMNUM_UFRNM_Pos            (0UL)        /*!< UFRNM (Bit 0)                                         */
+ #define R_USB_FS0_UFRMNUM_UFRNM_Msk            (0x7UL)      /*!< UFRNM (Bitfield-Mask: 0x07)                           */
+/* ========================================================  USBADDR  ======================================================== */
+ #define R_USB_FS0_USBADDR_STSRECOV0_Pos        (8UL)        /*!< STSRECOV0 (Bit 8)                                     */
+ #define R_USB_FS0_USBADDR_STSRECOV0_Msk        (0x700UL)    /*!< STSRECOV0 (Bitfield-Mask: 0x07)                       */
+ #define R_USB_FS0_USBADDR_USBADDR_Pos          (0UL)        /*!< USBADDR (Bit 0)                                       */
+ #define R_USB_FS0_USBADDR_USBADDR_Msk          (0x7fUL)     /*!< USBADDR (Bitfield-Mask: 0x7f)                         */
+/* ========================================================  USBREQ  ========================================================= */
+ #define R_USB_FS0_USBREQ_BREQUEST_Pos          (8UL)        /*!< BREQUEST (Bit 8)                                      */
+ #define R_USB_FS0_USBREQ_BREQUEST_Msk          (0xff00UL)   /*!< BREQUEST (Bitfield-Mask: 0xff)                        */
+ #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos     (0UL)        /*!< BMREQUESTTYPE (Bit 0)                                 */
+ #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk     (0xffUL)     /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff)                   */
+/* ========================================================  USBVAL  ========================================================= */
+ #define R_USB_FS0_USBVAL_WVALUE_Pos            (0UL)        /*!< WVALUE (Bit 0)                                        */
+ #define R_USB_FS0_USBVAL_WVALUE_Msk            (0xffffUL)   /*!< WVALUE (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  USBINDX  ======================================================== */
+ #define R_USB_FS0_USBINDX_WINDEX_Pos           (0UL)        /*!< WINDEX (Bit 0)                                        */
+ #define R_USB_FS0_USBINDX_WINDEX_Msk           (0xffffUL)   /*!< WINDEX (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  USBLENG  ======================================================== */
+ #define R_USB_FS0_USBLENG_WLENGTH_Pos          (0UL)        /*!< WLENGTH (Bit 0)                                       */
+ #define R_USB_FS0_USBLENG_WLENGTH_Msk          (0xffffUL)   /*!< WLENGTH (Bitfield-Mask: 0xffff)                       */
+/* ========================================================  DCPCFG  ========================================================= */
+ #define R_USB_FS0_DCPCFG_CNTMD_Pos             (8UL)        /*!< CNTMD (Bit 8)                                         */
+ #define R_USB_FS0_DCPCFG_CNTMD_Msk             (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DCPCFG_SHTNAK_Pos            (7UL)        /*!< SHTNAK (Bit 7)                                        */
+ #define R_USB_FS0_DCPCFG_SHTNAK_Msk            (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DCPCFG_DIR_Pos               (4UL)        /*!< DIR (Bit 4)                                           */
+ #define R_USB_FS0_DCPCFG_DIR_Msk               (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
+/* ========================================================  DCPMAXP  ======================================================== */
+ #define R_USB_FS0_DCPMAXP_DEVSEL_Pos           (12UL)       /*!< DEVSEL (Bit 12)                                       */
+ #define R_USB_FS0_DCPMAXP_DEVSEL_Msk           (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
+ #define R_USB_FS0_DCPMAXP_MXPS_Pos             (0UL)        /*!< MXPS (Bit 0)                                          */
+ #define R_USB_FS0_DCPMAXP_MXPS_Msk             (0x7fUL)     /*!< MXPS (Bitfield-Mask: 0x7f)                            */
+/* ========================================================  DCPCTR  ========================================================= */
+ #define R_USB_FS0_DCPCTR_BSTS_Pos              (15UL)       /*!< BSTS (Bit 15)                                         */
+ #define R_USB_FS0_DCPCTR_BSTS_Msk              (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_DCPCTR_SUREQ_Pos             (14UL)       /*!< SUREQ (Bit 14)                                        */
+ #define R_USB_FS0_DCPCTR_SUREQ_Msk             (0x4000UL)   /*!< SUREQ (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DCPCTR_SUREQCLR_Pos          (11UL)       /*!< SUREQCLR (Bit 11)                                     */
+ #define R_USB_FS0_DCPCTR_SUREQCLR_Msk          (0x800UL)    /*!< SUREQCLR (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_DCPCTR_SQCLR_Pos             (8UL)        /*!< SQCLR (Bit 8)                                         */
+ #define R_USB_FS0_DCPCTR_SQCLR_Msk             (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DCPCTR_SQSET_Pos             (7UL)        /*!< SQSET (Bit 7)                                         */
+ #define R_USB_FS0_DCPCTR_SQSET_Msk             (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DCPCTR_SQMON_Pos             (6UL)        /*!< SQMON (Bit 6)                                         */
+ #define R_USB_FS0_DCPCTR_SQMON_Msk             (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DCPCTR_PBUSY_Pos             (5UL)        /*!< PBUSY (Bit 5)                                         */
+ #define R_USB_FS0_DCPCTR_PBUSY_Msk             (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DCPCTR_CCPL_Pos              (2UL)        /*!< CCPL (Bit 2)                                          */
+ #define R_USB_FS0_DCPCTR_CCPL_Msk              (0x4UL)      /*!< CCPL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_DCPCTR_PID_Pos               (0UL)        /*!< PID (Bit 0)                                           */
+ #define R_USB_FS0_DCPCTR_PID_Msk               (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
+/* ========================================================  PIPESEL  ======================================================== */
+ #define R_USB_FS0_PIPESEL_PIPESEL_Pos          (0UL)        /*!< PIPESEL (Bit 0)                                       */
+ #define R_USB_FS0_PIPESEL_PIPESEL_Msk          (0xfUL)      /*!< PIPESEL (Bitfield-Mask: 0x0f)                         */
+/* ========================================================  PIPECFG  ======================================================== */
+ #define R_USB_FS0_PIPECFG_TYPE_Pos             (14UL)       /*!< TYPE (Bit 14)                                         */
+ #define R_USB_FS0_PIPECFG_TYPE_Msk             (0xc000UL)   /*!< TYPE (Bitfield-Mask: 0x03)                            */
+ #define R_USB_FS0_PIPECFG_BFRE_Pos             (10UL)       /*!< BFRE (Bit 10)                                         */
+ #define R_USB_FS0_PIPECFG_BFRE_Msk             (0x400UL)    /*!< BFRE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_PIPECFG_DBLB_Pos             (9UL)        /*!< DBLB (Bit 9)                                          */
+ #define R_USB_FS0_PIPECFG_DBLB_Msk             (0x200UL)    /*!< DBLB (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_PIPECFG_SHTNAK_Pos           (7UL)        /*!< SHTNAK (Bit 7)                                        */
+ #define R_USB_FS0_PIPECFG_SHTNAK_Msk           (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_PIPECFG_DIR_Pos              (4UL)        /*!< DIR (Bit 4)                                           */
+ #define R_USB_FS0_PIPECFG_DIR_Msk              (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
+ #define R_USB_FS0_PIPECFG_EPNUM_Pos            (0UL)        /*!< EPNUM (Bit 0)                                         */
+ #define R_USB_FS0_PIPECFG_EPNUM_Msk            (0xfUL)      /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
+/* =======================================================  PIPEMAXP  ======================================================== */
+ #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos          (12UL)       /*!< DEVSEL (Bit 12)                                       */
+ #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk          (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
+ #define R_USB_FS0_PIPEMAXP_MXPS_Pos            (0UL)        /*!< MXPS (Bit 0)                                          */
+ #define R_USB_FS0_PIPEMAXP_MXPS_Msk            (0x1ffUL)    /*!< MXPS (Bitfield-Mask: 0x1ff)                           */
+/* =======================================================  PIPEPERI  ======================================================== */
+ #define R_USB_FS0_PIPEPERI_IFIS_Pos            (12UL)       /*!< IFIS (Bit 12)                                         */
+ #define R_USB_FS0_PIPEPERI_IFIS_Msk            (0x1000UL)   /*!< IFIS (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_PIPEPERI_IITV_Pos            (0UL)        /*!< IITV (Bit 0)                                          */
+ #define R_USB_FS0_PIPEPERI_IITV_Msk            (0x7UL)      /*!< IITV (Bitfield-Mask: 0x07)                            */
+/* =======================================================  PIPE_CTR  ======================================================== */
+ #define R_USB_FS0_PIPE_CTR_BSTS_Pos            (15UL)       /*!< BSTS (Bit 15)                                         */
+ #define R_USB_FS0_PIPE_CTR_BSTS_Msk            (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_PIPE_CTR_INBUFM_Pos          (14UL)       /*!< INBUFM (Bit 14)                                       */
+ #define R_USB_FS0_PIPE_CTR_INBUFM_Msk          (0x4000UL)   /*!< INBUFM (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_PIPE_CTR_CSCLR_Pos           (13UL)       /*!< CSCLR (Bit 13)                                        */
+ #define R_USB_FS0_PIPE_CTR_CSCLR_Msk           (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_CSSTS_Pos           (12UL)       /*!< CSSTS (Bit 12)                                        */
+ #define R_USB_FS0_PIPE_CTR_CSSTS_Msk           (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_ATREPM_Pos          (10UL)       /*!< ATREPM (Bit 10)                                       */
+ #define R_USB_FS0_PIPE_CTR_ATREPM_Msk          (0x400UL)    /*!< ATREPM (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_PIPE_CTR_ACLRM_Pos           (9UL)        /*!< ACLRM (Bit 9)                                         */
+ #define R_USB_FS0_PIPE_CTR_ACLRM_Msk           (0x200UL)    /*!< ACLRM (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_SQCLR_Pos           (8UL)        /*!< SQCLR (Bit 8)                                         */
+ #define R_USB_FS0_PIPE_CTR_SQCLR_Msk           (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_SQSET_Pos           (7UL)        /*!< SQSET (Bit 7)                                         */
+ #define R_USB_FS0_PIPE_CTR_SQSET_Msk           (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_SQMON_Pos           (6UL)        /*!< SQMON (Bit 6)                                         */
+ #define R_USB_FS0_PIPE_CTR_SQMON_Msk           (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_PBUSY_Pos           (5UL)        /*!< PBUSY (Bit 5)                                         */
+ #define R_USB_FS0_PIPE_CTR_PBUSY_Msk           (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_PID_Pos             (0UL)        /*!< PID (Bit 0)                                           */
+ #define R_USB_FS0_PIPE_CTR_PID_Msk             (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
+/* ========================================================  DEVADD  ========================================================= */
+ #define R_USB_FS0_DEVADD_UPPHUB_Pos            (11UL)       /*!< UPPHUB (Bit 11)                                       */
+ #define R_USB_FS0_DEVADD_UPPHUB_Msk            (0x7800UL)   /*!< UPPHUB (Bitfield-Mask: 0x0f)                          */
+ #define R_USB_FS0_DEVADD_HUBPORT_Pos           (8UL)        /*!< HUBPORT (Bit 8)                                       */
+ #define R_USB_FS0_DEVADD_HUBPORT_Msk           (0x700UL)    /*!< HUBPORT (Bitfield-Mask: 0x07)                         */
+ #define R_USB_FS0_DEVADD_USBSPD_Pos            (6UL)        /*!< USBSPD (Bit 6)                                        */
+ #define R_USB_FS0_DEVADD_USBSPD_Msk            (0xc0UL)     /*!< USBSPD (Bitfield-Mask: 0x03)                          */
+/* ======================================================  USBBCCTRL0  ======================================================= */
+ #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos     (9UL)        /*!< PDDETSTS0 (Bit 9)                                     */
+ #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk     (0x200UL)    /*!< PDDETSTS0 (Bitfield-Mask: 0x01)                       */
+ #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos    (8UL)        /*!< CHGDETSTS0 (Bit 8)                                    */
+ #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk    (0x100UL)    /*!< CHGDETSTS0 (Bitfield-Mask: 0x01)                      */
+ #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos      (7UL)        /*!< BATCHGE0 (Bit 7)                                      */
+ #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk      (0x80UL)     /*!< BATCHGE0 (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos      (5UL)        /*!< VDMSRCE0 (Bit 5)                                      */
+ #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk      (0x20UL)     /*!< VDMSRCE0 (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos     (4UL)        /*!< IDPSINKE0 (Bit 4)                                     */
+ #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk     (0x10UL)     /*!< IDPSINKE0 (Bitfield-Mask: 0x01)                       */
+ #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos      (3UL)        /*!< VDPSRCE0 (Bit 3)                                      */
+ #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk      (0x8UL)      /*!< VDPSRCE0 (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos     (2UL)        /*!< IDMSINKE0 (Bit 2)                                     */
+ #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk     (0x4UL)      /*!< IDMSINKE0 (Bitfield-Mask: 0x01)                       */
+ #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos      (1UL)        /*!< IDPSRCE0 (Bit 1)                                      */
+ #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk      (0x2UL)      /*!< IDPSRCE0 (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos        (0UL)        /*!< RPDME0 (Bit 0)                                        */
+ #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk        (0x1UL)      /*!< RPDME0 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  UCKSEL  ========================================================= */
+ #define R_USB_FS0_UCKSEL_UCKSELC_Pos           (0UL)        /*!< UCKSELC (Bit 0)                                       */
+ #define R_USB_FS0_UCKSEL_UCKSELC_Msk           (0x1UL)      /*!< UCKSELC (Bitfield-Mask: 0x01)                         */
+/* =========================================================  USBMC  ========================================================= */
+ #define R_USB_FS0_USBMC_VDCEN_Pos              (7UL)        /*!< VDCEN (Bit 7)                                         */
+ #define R_USB_FS0_USBMC_VDCEN_Msk              (0x80UL)     /*!< VDCEN (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_USBMC_VDDUSBE_Pos            (0UL)        /*!< VDDUSBE (Bit 0)                                       */
+ #define R_USB_FS0_USBMC_VDDUSBE_Msk            (0x1UL)      /*!< VDDUSBE (Bitfield-Mask: 0x01)                         */
+/* ========================================================  PHYSLEW  ======================================================== */
+ #define R_USB_FS0_PHYSLEW_SLEWF01_Pos          (3UL)        /*!< SLEWF01 (Bit 3)                                       */
+ #define R_USB_FS0_PHYSLEW_SLEWF01_Msk          (0x8UL)      /*!< SLEWF01 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_PHYSLEW_SLEWF00_Pos          (2UL)        /*!< SLEWF00 (Bit 2)                                       */
+ #define R_USB_FS0_PHYSLEW_SLEWF00_Msk          (0x4UL)      /*!< SLEWF00 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_PHYSLEW_SLEWR01_Pos          (1UL)        /*!< SLEWR01 (Bit 1)                                       */
+ #define R_USB_FS0_PHYSLEW_SLEWR01_Msk          (0x2UL)      /*!< SLEWR01 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_PHYSLEW_SLEWR00_Pos          (0UL)        /*!< SLEWR00 (Bit 0)                                       */
+ #define R_USB_FS0_PHYSLEW_SLEWR00_Msk          (0x1UL)      /*!< SLEWR00 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  LPCTRL  ========================================================= */
+ #define R_USB_FS0_LPCTRL_HWUPM_Pos             (7UL)        /*!< HWUPM (Bit 7)                                         */
+ #define R_USB_FS0_LPCTRL_HWUPM_Msk             (0x80UL)     /*!< HWUPM (Bitfield-Mask: 0x01)                           */
+/* =========================================================  LPSTS  ========================================================= */
+ #define R_USB_FS0_LPSTS_SUSPENDM_Pos           (14UL)       /*!< SUSPENDM (Bit 14)                                     */
+ #define R_USB_FS0_LPSTS_SUSPENDM_Msk           (0x4000UL)   /*!< SUSPENDM (Bitfield-Mask: 0x01)                        */
+/* ========================================================  BCCTRL  ========================================================= */
+ #define R_USB_FS0_BCCTRL_PDDETSTS_Pos          (9UL)        /*!< PDDETSTS (Bit 9)                                      */
+ #define R_USB_FS0_BCCTRL_PDDETSTS_Msk          (0x200UL)    /*!< PDDETSTS (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos         (8UL)        /*!< CHGDETSTS (Bit 8)                                     */
+ #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk         (0x100UL)    /*!< CHGDETSTS (Bitfield-Mask: 0x01)                       */
+ #define R_USB_FS0_BCCTRL_DCPMODE_Pos           (5UL)        /*!< DCPMODE (Bit 5)                                       */
+ #define R_USB_FS0_BCCTRL_DCPMODE_Msk           (0x20UL)     /*!< DCPMODE (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_BCCTRL_VDMSRCE_Pos           (4UL)        /*!< VDMSRCE (Bit 4)                                       */
+ #define R_USB_FS0_BCCTRL_VDMSRCE_Msk           (0x10UL)     /*!< VDMSRCE (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_BCCTRL_IDPSINKE_Pos          (3UL)        /*!< IDPSINKE (Bit 3)                                      */
+ #define R_USB_FS0_BCCTRL_IDPSINKE_Msk          (0x8UL)      /*!< IDPSINKE (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_BCCTRL_VDPSRCE_Pos           (2UL)        /*!< VDPSRCE (Bit 2)                                       */
+ #define R_USB_FS0_BCCTRL_VDPSRCE_Msk           (0x4UL)      /*!< VDPSRCE (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_BCCTRL_IDMSINKE_Pos          (1UL)        /*!< IDMSINKE (Bit 1)                                      */
+ #define R_USB_FS0_BCCTRL_IDMSINKE_Msk          (0x2UL)      /*!< IDMSINKE (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_BCCTRL_IDPSRCE_Pos           (0UL)        /*!< IDPSRCE (Bit 0)                                       */
+ #define R_USB_FS0_BCCTRL_IDPSRCE_Msk           (0x1UL)      /*!< IDPSRCE (Bitfield-Mask: 0x01)                         */
+/* =======================================================  PL1CTRL1  ======================================================== */
+ #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos         (14UL)       /*!< L1EXTMD (Bit 14)                                      */
+ #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk         (0x4000UL)   /*!< L1EXTMD (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos         (8UL)        /*!< HIRDTHR (Bit 8)                                       */
+ #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk         (0xf00UL)    /*!< HIRDTHR (Bitfield-Mask: 0x0f)                         */
+ #define R_USB_FS0_PL1CTRL1_DVSQ_Pos            (4UL)        /*!< DVSQ (Bit 4)                                          */
+ #define R_USB_FS0_PL1CTRL1_DVSQ_Msk            (0xf0UL)     /*!< DVSQ (Bitfield-Mask: 0x0f)                            */
+ #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos        (3UL)        /*!< L1NEGOMD (Bit 3)                                      */
+ #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk        (0x8UL)      /*!< L1NEGOMD (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos        (1UL)        /*!< L1RESPMD (Bit 1)                                      */
+ #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk        (0x6UL)      /*!< L1RESPMD (Bitfield-Mask: 0x03)                        */
+ #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos        (0UL)        /*!< L1RESPEN (Bit 0)                                      */
+ #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk        (0x1UL)      /*!< L1RESPEN (Bitfield-Mask: 0x01)                        */
+/* =======================================================  PL1CTRL2  ======================================================== */
+ #define R_USB_FS0_PL1CTRL2_RWEMON_Pos          (12UL)       /*!< RWEMON (Bit 12)                                       */
+ #define R_USB_FS0_PL1CTRL2_RWEMON_Msk          (0x1000UL)   /*!< RWEMON (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos         (8UL)        /*!< HIRDMON (Bit 8)                                       */
+ #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk         (0xf00UL)    /*!< HIRDMON (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  HL1CTRL1  ======================================================== */
+ #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos        (1UL)        /*!< L1STATUS (Bit 1)                                      */
+ #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk        (0x6UL)      /*!< L1STATUS (Bitfield-Mask: 0x03)                        */
+ #define R_USB_FS0_HL1CTRL1_L1REQ_Pos           (0UL)        /*!< L1REQ (Bit 0)                                         */
+ #define R_USB_FS0_HL1CTRL1_L1REQ_Msk           (0x1UL)      /*!< L1REQ (Bitfield-Mask: 0x01)                           */
+/* =======================================================  HL1CTRL2  ======================================================== */
+ #define R_USB_FS0_HL1CTRL2_BESL_Pos            (15UL)       /*!< BESL (Bit 15)                                         */
+ #define R_USB_FS0_HL1CTRL2_BESL_Msk            (0x8000UL)   /*!< BESL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_HL1CTRL2_L1RWE_Pos           (12UL)       /*!< L1RWE (Bit 12)                                        */
+ #define R_USB_FS0_HL1CTRL2_L1RWE_Msk           (0x1000UL)   /*!< L1RWE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_HL1CTRL2_HIRD_Pos            (8UL)        /*!< HIRD (Bit 8)                                          */
+ #define R_USB_FS0_HL1CTRL2_HIRD_Msk            (0xf00UL)    /*!< HIRD (Bitfield-Mask: 0x0f)                            */
+ #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos          (0UL)        /*!< L1ADDR (Bit 0)                                        */
+ #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk          (0xfUL)      /*!< L1ADDR (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  DPUSR0R  ======================================================== */
+ #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos         (23UL)       /*!< DVBSTSHM (Bit 23)                                     */
+ #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk         (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos          (21UL)       /*!< DOVCBHM (Bit 21)                                      */
+ #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk          (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos          (20UL)       /*!< DOVCAHM (Bit 20)                                      */
+ #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk          (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DPUSR1R  ======================================================== */
+ #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos          (23UL)       /*!< DVBSTSH (Bit 23)                                      */
+ #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk          (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR1R_DOVCBH_Pos           (21UL)       /*!< DOVCBH (Bit 21)                                       */
+ #define R_USB_FS0_DPUSR1R_DOVCBH_Msk           (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR1R_DOVCAH_Pos           (20UL)       /*!< DOVCAH (Bit 20)                                       */
+ #define R_USB_FS0_DPUSR1R_DOVCAH_Msk           (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos         (7UL)        /*!< DVBSTSHE (Bit 7)                                      */
+ #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk         (0x80UL)     /*!< DVBSTSHE (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos          (5UL)        /*!< DOVCBHE (Bit 5)                                       */
+ #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk          (0x20UL)     /*!< DOVCBHE (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos          (4UL)        /*!< DOVCAHE (Bit 4)                                       */
+ #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk          (0x10UL)     /*!< DOVCAHE (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DPUSR2R  ======================================================== */
+ #define R_USB_FS0_DPUSR2R_DMINTE_Pos           (9UL)        /*!< DMINTE (Bit 9)                                        */
+ #define R_USB_FS0_DPUSR2R_DMINTE_Msk           (0x200UL)    /*!< DMINTE (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR2R_DPINTE_Pos           (8UL)        /*!< DPINTE (Bit 8)                                        */
+ #define R_USB_FS0_DPUSR2R_DPINTE_Msk           (0x100UL)    /*!< DPINTE (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR2R_DMVAL_Pos            (5UL)        /*!< DMVAL (Bit 5)                                         */
+ #define R_USB_FS0_DPUSR2R_DMVAL_Msk            (0x20UL)     /*!< DMVAL (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DPUSR2R_DPVAL_Pos            (4UL)        /*!< DPVAL (Bit 4)                                         */
+ #define R_USB_FS0_DPUSR2R_DPVAL_Msk            (0x10UL)     /*!< DPVAL (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DPUSR2R_DMINT_Pos            (1UL)        /*!< DMINT (Bit 1)                                         */
+ #define R_USB_FS0_DPUSR2R_DMINT_Msk            (0x2UL)      /*!< DMINT (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DPUSR2R_DPINT_Pos            (0UL)        /*!< DPINT (Bit 0)                                         */
+ #define R_USB_FS0_DPUSR2R_DPINT_Msk            (0x1UL)      /*!< DPINT (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DPUSRCR  ======================================================== */
+ #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos         (1UL)        /*!< FIXPHYPD (Bit 1)                                      */
+ #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk         (0x2UL)      /*!< FIXPHYPD (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_DPUSRCR_FIXPHY_Pos           (0UL)        /*!< FIXPHY (Bit 0)                                        */
+ #define R_USB_FS0_DPUSRCR_FIXPHY_Msk           (0x1UL)      /*!< FIXPHY (Bitfield-Mask: 0x01)                          */
+/* ======================================================  DPUSR0R_FS  ======================================================= */
+ #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos       (23UL)       /*!< DVBSTS0 (Bit 23)                                      */
+ #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk       (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos        (21UL)       /*!< DOVCB0 (Bit 21)                                       */
+ #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk        (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos        (20UL)       /*!< DOVCA0 (Bit 20)                                       */
+ #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk        (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR0R_FS_DM0_Pos           (17UL)       /*!< DM0 (Bit 17)                                          */
+ #define R_USB_FS0_DPUSR0R_FS_DM0_Msk           (0x20000UL)  /*!< DM0 (Bitfield-Mask: 0x01)                             */
+ #define R_USB_FS0_DPUSR0R_FS_DP0_Pos           (16UL)       /*!< DP0 (Bit 16)                                          */
+ #define R_USB_FS0_DPUSR0R_FS_DP0_Msk           (0x10000UL)  /*!< DP0 (Bitfield-Mask: 0x01)                             */
+ #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos       (4UL)        /*!< FIXPHY0 (Bit 4)                                       */
+ #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk       (0x10UL)     /*!< FIXPHY0 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos         (3UL)        /*!< DRPD0 (Bit 3)                                         */
+ #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk         (0x8UL)      /*!< DRPD0 (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos         (1UL)        /*!< RPUE0 (Bit 1)                                         */
+ #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk         (0x2UL)      /*!< RPUE0 (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos         (0UL)        /*!< SRPC0 (Bit 0)                                         */
+ #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk         (0x1UL)      /*!< SRPC0 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  DPUSR1R_FS  ======================================================= */
+ #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos       (23UL)       /*!< DVBINT0 (Bit 23)                                      */
+ #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk       (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos      (21UL)       /*!< DOVRCRB0 (Bit 21)                                     */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk      (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos      (20UL)       /*!< DOVRCRA0 (Bit 20)                                     */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk      (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos        (17UL)       /*!< DMINT0 (Bit 17)                                       */
+ #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk        (0x20000UL)  /*!< DMINT0 (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos        (16UL)       /*!< DPINT0 (Bit 16)                                       */
+ #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk        (0x10000UL)  /*!< DPINT0 (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos        (7UL)        /*!< DVBSE0 (Bit 7)                                        */
+ #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk        (0x80UL)     /*!< DVBSE0 (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos     (5UL)        /*!< DOVRCRBE0 (Bit 5)                                     */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk     (0x20UL)     /*!< DOVRCRBE0 (Bitfield-Mask: 0x01)                       */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos     (4UL)        /*!< DOVRCRAE0 (Bit 4)                                     */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk     (0x10UL)     /*!< DOVRCRAE0 (Bitfield-Mask: 0x01)                       */
+ #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos       (1UL)        /*!< DMINTE0 (Bit 1)                                       */
+ #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk       (0x2UL)      /*!< DMINTE0 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos       (0UL)        /*!< DPINTE0 (Bit 0)                                       */
+ #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk       (0x1UL)      /*!< DPINTE0 (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                           R_WDT                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  WDTRR  ========================================================= */
+ #define R_WDT_WDTRR_WDTRR_Pos        (0UL)      /*!< WDTRR (Bit 0)                                         */
+ #define R_WDT_WDTRR_WDTRR_Msk        (0xffUL)   /*!< WDTRR (Bitfield-Mask: 0xff)                           */
+/* =========================================================  WDTCR  ========================================================= */
+ #define R_WDT_WDTCR_RPSS_Pos         (12UL)     /*!< RPSS (Bit 12)                                         */
+ #define R_WDT_WDTCR_RPSS_Msk         (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
+ #define R_WDT_WDTCR_RPES_Pos         (8UL)      /*!< RPES (Bit 8)                                          */
+ #define R_WDT_WDTCR_RPES_Msk         (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
+ #define R_WDT_WDTCR_CKS_Pos          (4UL)      /*!< CKS (Bit 4)                                           */
+ #define R_WDT_WDTCR_CKS_Msk          (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
+ #define R_WDT_WDTCR_TOPS_Pos         (0UL)      /*!< TOPS (Bit 0)                                          */
+ #define R_WDT_WDTCR_TOPS_Msk         (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  WDTSR  ========================================================= */
+ #define R_WDT_WDTSR_REFEF_Pos        (15UL)     /*!< REFEF (Bit 15)                                        */
+ #define R_WDT_WDTSR_REFEF_Msk        (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
+ #define R_WDT_WDTSR_UNDFF_Pos        (14UL)     /*!< UNDFF (Bit 14)                                        */
+ #define R_WDT_WDTSR_UNDFF_Msk        (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
+ #define R_WDT_WDTSR_CNTVAL_Pos       (0UL)      /*!< CNTVAL (Bit 0)                                        */
+ #define R_WDT_WDTSR_CNTVAL_Msk       (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
+/* ========================================================  WDTRCR  ========================================================= */
+ #define R_WDT_WDTRCR_RSTIRQS_Pos     (7UL)      /*!< RSTIRQS (Bit 7)                                       */
+ #define R_WDT_WDTRCR_RSTIRQS_Msk     (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
+/* =======================================================  WDTCSTPR  ======================================================== */
+ #define R_WDT_WDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
+ #define R_WDT_WDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_TZF                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  TZFOAD  ========================================================= */
+ #define R_TZF_TZFOAD_OAD_Pos       (0UL)      /*!< OAD (Bit 0)                                           */
+ #define R_TZF_TZFOAD_OAD_Msk       (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
+ #define R_TZF_TZFOAD_KEY_Pos       (8UL)      /*!< KEY (Bit 8)                                           */
+ #define R_TZF_TZFOAD_KEY_Msk       (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
+/* =========================================================  TZFPT  ========================================================= */
+ #define R_TZF_TZFPT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
+ #define R_TZF_TZFPT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
+ #define R_TZF_TZFPT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
+ #define R_TZF_TZFPT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
+/* ========================================================  TZFSAR  ========================================================= */
+ #define R_TZF_TZFSAR_TZFSA0_Pos    (0UL)      /*!< TZFSA0 (Bit 0)                                        */
+ #define R_TZF_TZFSAR_TZFSA0_Msk    (0x1UL)    /*!< TZFSA0 (Bitfield-Mask: 0x01)                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CACHE                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CCACTL  ========================================================= */
+ #define R_CACHE_CCACTL_ENC_Pos     (0UL)    /*!< ENC (Bit 0)                                           */
+ #define R_CACHE_CCACTL_ENC_Msk     (0x1UL)  /*!< ENC (Bitfield-Mask: 0x01)                             */
+/* ========================================================  CCAFCT  ========================================================= */
+ #define R_CACHE_CCAFCT_FC_Pos      (0UL)    /*!< FC (Bit 0)                                            */
+ #define R_CACHE_CCAFCT_FC_Msk      (0x1UL)  /*!< FC (Bitfield-Mask: 0x01)                              */
+/* ========================================================  CCALCF  ========================================================= */
+ #define R_CACHE_CCALCF_CC_Pos      (0UL)    /*!< CC (Bit 0)                                            */
+ #define R_CACHE_CCALCF_CC_Msk      (0x3UL)  /*!< CC (Bitfield-Mask: 0x03)                              */
+/* ========================================================  SCACTL  ========================================================= */
+ #define R_CACHE_SCACTL_ENS_Pos     (0UL)    /*!< ENS (Bit 0)                                           */
+ #define R_CACHE_SCACTL_ENS_Msk     (0x1UL)  /*!< ENS (Bitfield-Mask: 0x01)                             */
+/* ========================================================  SCAFCT  ========================================================= */
+ #define R_CACHE_SCAFCT_FS_Pos      (0UL)    /*!< FS (Bit 0)                                            */
+ #define R_CACHE_SCAFCT_FS_Msk      (0x1UL)  /*!< FS (Bitfield-Mask: 0x01)                              */
+/* ========================================================  SCALCF  ========================================================= */
+ #define R_CACHE_SCALCF_CS_Pos      (0UL)    /*!< CS (Bit 0)                                            */
+ #define R_CACHE_SCALCF_CS_Msk      (0x3UL)  /*!< CS (Bitfield-Mask: 0x03)                              */
+/* ========================================================  CAPOAD  ========================================================= */
+ #define R_CACHE_CAPOAD_OAD_Pos     (0UL)    /*!< OAD (Bit 0)                                           */
+ #define R_CACHE_CAPOAD_OAD_Msk     (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
+/* ========================================================  CAPRCR  ========================================================= */
+ #define R_CACHE_CAPRCR_PRCR_Pos    (0UL)    /*!< PRCR (Bit 0)                                          */
+ #define R_CACHE_CAPRCR_PRCR_Msk    (0x1UL)  /*!< PRCR (Bitfield-Mask: 0x01)                            */
+ #define R_CACHE_CAPRCR_KW_Pos      (1UL)    /*!< KW (Bit 1)                                            */
+ #define R_CACHE_CAPRCR_KW_Msk      (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CPSCU                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  CSAR  ========================================================== */
+ #define R_CPSCU_CSAR_CACHESA_Pos            (0UL)          /*!< CACHESA (Bit 0)                                       */
+ #define R_CPSCU_CSAR_CACHESA_Msk            (0x1UL)        /*!< CACHESA (Bitfield-Mask: 0x01)                         */
+ #define R_CPSCU_CSAR_CACHELSA_Pos           (1UL)          /*!< CACHELSA (Bit 1)                                      */
+ #define R_CPSCU_CSAR_CACHELSA_Msk           (0x2UL)        /*!< CACHELSA (Bitfield-Mask: 0x01)                        */
+ #define R_CPSCU_CSAR_CACHEESA_Pos           (2UL)          /*!< CACHEESA (Bit 2)                                      */
+ #define R_CPSCU_CSAR_CACHEESA_Msk           (0x4UL)        /*!< CACHEESA (Bitfield-Mask: 0x01)                        */
+/* ========================================================  SRAMSAR  ======================================================== */
+ #define R_CPSCU_SRAMSAR_SRAMSA0_Pos         (0UL)          /*!< SRAMSA0 (Bit 0)                                       */
+ #define R_CPSCU_SRAMSAR_SRAMSA0_Msk         (0x1UL)        /*!< SRAMSA0 (Bitfield-Mask: 0x01)                         */
+ #define R_CPSCU_SRAMSAR_SRAMSA1_Pos         (1UL)          /*!< SRAMSA1 (Bit 1)                                       */
+ #define R_CPSCU_SRAMSAR_SRAMSA1_Msk         (0x2UL)        /*!< SRAMSA1 (Bitfield-Mask: 0x01)                         */
+ #define R_CPSCU_SRAMSAR_SRAMSA2_Pos         (2UL)          /*!< SRAMSA2 (Bit 2)                                       */
+ #define R_CPSCU_SRAMSAR_SRAMSA2_Msk         (0x4UL)        /*!< SRAMSA2 (Bitfield-Mask: 0x01)                         */
+/* =======================================================  STBRAMSAR  ======================================================= */
+ #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos       (0UL)          /*!< NSBSTBR (Bit 0)                                       */
+ #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk       (0xfUL)        /*!< NSBSTBR (Bitfield-Mask: 0x0f)                         */
+/* ========================================================  DTCSAR  ========================================================= */
+ #define R_CPSCU_DTCSAR_DTCSTSA_Pos          (0UL)          /*!< DTCSTSA (Bit 0)                                       */
+ #define R_CPSCU_DTCSAR_DTCSTSA_Msk          (0x1UL)        /*!< DTCSTSA (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DMACSAR  ======================================================== */
+ #define R_CPSCU_DMACSAR_DMASTSA_Pos         (0UL)          /*!< DMASTSA (Bit 0)                                       */
+ #define R_CPSCU_DMACSAR_DMASTSA_Msk         (0x1UL)        /*!< DMASTSA (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ICUSARA  ======================================================== */
+ #define R_CPSCU_ICUSARA_SAIRQCRn_Pos        (0UL)          /*!< SAIRQCRn (Bit 0)                                      */
+ #define R_CPSCU_ICUSARA_SAIRQCRn_Msk        (0xffffUL)     /*!< SAIRQCRn (Bitfield-Mask: 0xffff)                      */
+/* ========================================================  ICUSARB  ======================================================== */
+ #define R_CPSCU_ICUSARB_SANMI_Pos           (0UL)          /*!< SANMI (Bit 0)                                         */
+ #define R_CPSCU_ICUSARB_SANMI_Msk           (0x1UL)        /*!< SANMI (Bitfield-Mask: 0x01)                           */
+/* ========================================================  ICUSARC  ======================================================== */
+ #define R_CPSCU_ICUSARC_SADMACn_Pos         (0UL)          /*!< SADMACn (Bit 0)                                       */
+ #define R_CPSCU_ICUSARC_SADMACn_Msk         (0xffUL)       /*!< SADMACn (Bitfield-Mask: 0xff)                         */
+/* ========================================================  ICUSARD  ======================================================== */
+ #define R_CPSCU_ICUSARD_SASELSR0_Pos        (0UL)          /*!< SASELSR0 (Bit 0)                                      */
+ #define R_CPSCU_ICUSARD_SASELSR0_Msk        (0x1UL)        /*!< SASELSR0 (Bitfield-Mask: 0x01)                        */
+/* ========================================================  ICUSARE  ======================================================== */
+ #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos       (16UL)         /*!< SAIWDTWUP (Bit 16)                                    */
+ #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk       (0x10000UL)    /*!< SAIWDTWUP (Bitfield-Mask: 0x01)                       */
+ #define R_CPSCU_ICUSARE_SALVD1WUP_Pos       (18UL)         /*!< SALVD1WUP (Bit 18)                                    */
+ #define R_CPSCU_ICUSARE_SALVD1WUP_Msk       (0x40000UL)    /*!< SALVD1WUP (Bitfield-Mask: 0x01)                       */
+ #define R_CPSCU_ICUSARE_SALVD2WUP_Pos       (19UL)         /*!< SALVD2WUP (Bit 19)                                    */
+ #define R_CPSCU_ICUSARE_SALVD2WUP_Msk       (0x80000UL)    /*!< SALVD2WUP (Bitfield-Mask: 0x01)                       */
+ #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos      (20UL)         /*!< SAVBATTWUP (Bit 20)                                   */
+ #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk      (0x100000UL)   /*!< SAVBATTWUP (Bitfield-Mask: 0x01)                      */
+ #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos     (24UL)         /*!< SARTCALMWUP (Bit 24)                                  */
+ #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk     (0x1000000UL)  /*!< SARTCALMWUP (Bitfield-Mask: 0x01)                     */
+ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos     (25UL)         /*!< SARTCPRDWUP (Bit 25)                                  */
+ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk     (0x2000000UL)  /*!< SARTCPRDWUP (Bitfield-Mask: 0x01)                     */
+ #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos     (27UL)         /*!< SAUSBFS0WUP (Bit 27)                                  */
+ #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk     (0x8000000UL)  /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01)                     */
+ #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos     (28UL)         /*!< SAAGT1UDWUP (Bit 28)                                  */
+ #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk     (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01)                     */
+ #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos     (29UL)         /*!< SAAGT1CAWUP (Bit 29)                                  */
+ #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk     (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01)                     */
+ #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos     (30UL)         /*!< SAAGT1CBWUP (Bit 30)                                  */
+ #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk     (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01)                     */
+ #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos       (31UL)         /*!< SAIIC0WUP (Bit 31)                                    */
+ #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk       (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01)                       */
+/* ========================================================  ICUSARF  ======================================================== */
+ #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos     (0UL)          /*!< SAAGT3UDWUP (Bit 0)                                   */
+ #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk     (0x1UL)        /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01)                     */
+ #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos     (1UL)          /*!< SAAGT3CAWUP (Bit 1)                                   */
+ #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk     (0x2UL)        /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01)                     */
+ #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos     (2UL)          /*!< SAAGT3CBWUP (Bit 2)                                   */
+ #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk     (0x4UL)        /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01)                     */
+ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos    (3UL)          /*!< SACOMPHS0WUP (Bit 3)                                  */
+ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk    (0x8UL)        /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01)                    */
+ #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos      (8UL)          /*!< SAULP0UWUP (Bit 8)                                    */
+ #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk      (0x100UL)      /*!< SAULP0UWUP (Bitfield-Mask: 0x01)                      */
+ #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos      (9UL)          /*!< SAULP0AWUP (Bit 9)                                    */
+ #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk      (0x200UL)      /*!< SAULP0AWUP (Bitfield-Mask: 0x01)                      */
+ #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos      (10UL)         /*!< SAULP0BWUP (Bit 10)                                   */
+ #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk      (0x400UL)      /*!< SAULP0BWUP (Bitfield-Mask: 0x01)                      */
+ #define R_CPSCU_ICUSARF_SAI3CWUP_Pos        (11UL)         /*!< SAI3CWUP (Bit 11)                                     */
+ #define R_CPSCU_ICUSARF_SAI3CWUP_Msk        (0x800UL)      /*!< SAI3CWUP (Bitfield-Mask: 0x01)                        */
+ #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos      (12UL)         /*!< SAULP1UWUP (Bit 12)                                   */
+ #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk      (0x1000UL)     /*!< SAULP1UWUP (Bitfield-Mask: 0x01)                      */
+ #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos      (13UL)         /*!< SAULP1AWUP (Bit 13)                                   */
+ #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk      (0x2000UL)     /*!< SAULP1AWUP (Bitfield-Mask: 0x01)                      */
+ #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos      (14UL)         /*!< SAULP1BWUP (Bit 14)                                   */
+ #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk      (0x4000UL)     /*!< SAULP1BWUP (Bitfield-Mask: 0x01)                      */
+/* ========================================================  ICUSARG  ======================================================== */
+ #define R_CPSCU_ICUSARG_SAIELSRn_Pos        (0UL)          /*!< SAIELSRn (Bit 0)                                      */
+ #define R_CPSCU_ICUSARG_SAIELSRn_Msk        (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
+/* ========================================================  ICUSARH  ======================================================== */
+ #define R_CPSCU_ICUSARH_SAIELSRn_Pos        (0UL)          /*!< SAIELSRn (Bit 0)                                      */
+ #define R_CPSCU_ICUSARH_SAIELSRn_Msk        (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
+/* ========================================================  ICUSARI  ======================================================== */
+ #define R_CPSCU_ICUSARI_SAIELSRn_Pos        (0UL)          /*!< SAIELSRn (Bit 0)                                      */
+ #define R_CPSCU_ICUSARI_SAIELSRn_Msk        (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
+/* ========================================================  BUSSARA  ======================================================== */
+ #define R_CPSCU_BUSSARA_BUSSA0_Pos          (0UL)          /*!< BUSSA0 (Bit 0)                                        */
+ #define R_CPSCU_BUSSARA_BUSSA0_Msk          (0x1UL)        /*!< BUSSA0 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  BUSSARB  ======================================================== */
+ #define R_CPSCU_BUSSARB_BUSSB0_Pos          (0UL)          /*!< BUSSB0 (Bit 0)                                        */
+ #define R_CPSCU_BUSSARB_BUSSB0_Msk          (0x1UL)        /*!< BUSSB0 (Bitfield-Mask: 0x01)                          */
+/* =======================================================  MMPUSARA  ======================================================== */
+ #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos       (0UL)          /*!< MMPUAnSA (Bit 0)                                      */
+ #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk       (0xffUL)       /*!< MMPUAnSA (Bitfield-Mask: 0xff)                        */
+/* =======================================================  MMPUSARB  ======================================================== */
+ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos       (0UL)          /*!< MMPUB0SA (Bit 0)                                      */
+ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk       (0x1UL)        /*!< MMPUB0SA (Bitfield-Mask: 0x01)                        */
+/* ========================================================  DMASARA  ======================================================== */
+ #define R_CPSCU_DMASARA_DMASARAn_Pos        (0UL)          /*!< DMASARAn (Bit 0)                                      */
+ #define R_CPSCU_DMASARA_DMASARAn_Msk        (0xffUL)       /*!< DMASARAn (Bitfield-Mask: 0xff)                        */
+/* ========================================================  CPUDSAR  ======================================================== */
+ #define R_CPSCU_CPUDSAR_CPUDSA0_Pos         (0UL)          /*!< CPUDSA0 (Bit 0)                                       */
+ #define R_CPSCU_CPUDSAR_CPUDSA0_Msk         (0x1UL)        /*!< CPUDSA0 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  TEVTRCR  ======================================================== */
+ #define R_CPSCU_TEVTRCR_TEVTE_Pos           (0UL)          /*!< TEVTE (Bit 0)                                         */
+ #define R_CPSCU_TEVTRCR_TEVTE_Msk           (0x1UL)        /*!< TEVTE (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                           R_CEC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  CADR  ========================================================== */
+ #define R_CEC_CADR_ADR00_Pos            (0UL)      /*!< ADR00 (Bit 0)                                         */
+ #define R_CEC_CADR_ADR00_Msk            (0x1UL)    /*!< ADR00 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR01_Pos            (1UL)      /*!< ADR01 (Bit 1)                                         */
+ #define R_CEC_CADR_ADR01_Msk            (0x2UL)    /*!< ADR01 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR02_Pos            (2UL)      /*!< ADR02 (Bit 2)                                         */
+ #define R_CEC_CADR_ADR02_Msk            (0x4UL)    /*!< ADR02 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR03_Pos            (3UL)      /*!< ADR03 (Bit 3)                                         */
+ #define R_CEC_CADR_ADR03_Msk            (0x8UL)    /*!< ADR03 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR04_Pos            (4UL)      /*!< ADR04 (Bit 4)                                         */
+ #define R_CEC_CADR_ADR04_Msk            (0x10UL)   /*!< ADR04 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR05_Pos            (5UL)      /*!< ADR05 (Bit 5)                                         */
+ #define R_CEC_CADR_ADR05_Msk            (0x20UL)   /*!< ADR05 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR06_Pos            (6UL)      /*!< ADR06 (Bit 6)                                         */
+ #define R_CEC_CADR_ADR06_Msk            (0x40UL)   /*!< ADR06 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR07_Pos            (7UL)      /*!< ADR07 (Bit 7)                                         */
+ #define R_CEC_CADR_ADR07_Msk            (0x80UL)   /*!< ADR07 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR08_Pos            (8UL)      /*!< ADR08 (Bit 8)                                         */
+ #define R_CEC_CADR_ADR08_Msk            (0x100UL)  /*!< ADR08 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR09_Pos            (9UL)      /*!< ADR09 (Bit 9)                                         */
+ #define R_CEC_CADR_ADR09_Msk            (0x200UL)  /*!< ADR09 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR10_Pos            (10UL)     /*!< ADR10 (Bit 10)                                        */
+ #define R_CEC_CADR_ADR10_Msk            (0x400UL)  /*!< ADR10 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR11_Pos            (11UL)     /*!< ADR11 (Bit 11)                                        */
+ #define R_CEC_CADR_ADR11_Msk            (0x800UL)  /*!< ADR11 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR12_Pos            (12UL)     /*!< ADR12 (Bit 12)                                        */
+ #define R_CEC_CADR_ADR12_Msk            (0x1000UL) /*!< ADR12 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR13_Pos            (13UL)     /*!< ADR13 (Bit 13)                                        */
+ #define R_CEC_CADR_ADR13_Msk            (0x2000UL) /*!< ADR13 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR14_Pos            (14UL)     /*!< ADR14 (Bit 14)                                        */
+ #define R_CEC_CADR_ADR14_Msk            (0x4000UL) /*!< ADR14 (Bitfield-Mask: 0x01)                           */
+/* ========================================================  CECCTL1  ======================================================== */
+ #define R_CEC_CECCTL1_SFT_Pos           (0UL)      /*!< SFT (Bit 0)                                           */
+ #define R_CEC_CECCTL1_SFT_Msk           (0x3UL)    /*!< SFT (Bitfield-Mask: 0x03)                             */
+ #define R_CEC_CECCTL1_CESEL_Pos         (2UL)      /*!< CESEL (Bit 2)                                         */
+ #define R_CEC_CECCTL1_CESEL_Msk         (0xcUL)    /*!< CESEL (Bitfield-Mask: 0x03)                           */
+ #define R_CEC_CECCTL1_STERRD_Pos        (4UL)      /*!< STERRD (Bit 4)                                        */
+ #define R_CEC_CECCTL1_STERRD_Msk        (0x10UL)   /*!< STERRD (Bitfield-Mask: 0x01)                          */
+ #define R_CEC_CECCTL1_BLERRD_Pos        (5UL)      /*!< BLERRD (Bit 5)                                        */
+ #define R_CEC_CECCTL1_BLERRD_Msk        (0x20UL)   /*!< BLERRD (Bitfield-Mask: 0x01)                          */
+ #define R_CEC_CECCTL1_CINTMK_Pos        (6UL)      /*!< CINTMK (Bit 6)                                        */
+ #define R_CEC_CECCTL1_CINTMK_Msk        (0x40UL)   /*!< CINTMK (Bitfield-Mask: 0x01)                          */
+ #define R_CEC_CECCTL1_CDFC_Pos          (7UL)      /*!< CDFC (Bit 7)                                          */
+ #define R_CEC_CECCTL1_CDFC_Msk          (0x80UL)   /*!< CDFC (Bitfield-Mask: 0x01)                            */
+/* =========================================================  STATB  ========================================================= */
+ #define R_CEC_STATB_STATB_Pos           (0UL)      /*!< STATB (Bit 0)                                         */
+ #define R_CEC_STATB_STATB_Msk           (0x1ffUL)  /*!< STATB (Bitfield-Mask: 0x1ff)                          */
+/* =========================================================  STATL  ========================================================= */
+ #define R_CEC_STATL_STATL_Pos           (0UL)      /*!< STATL (Bit 0)                                         */
+ #define R_CEC_STATL_STATL_Msk           (0x1ffUL)  /*!< STATL (Bitfield-Mask: 0x1ff)                          */
+/* =========================================================  LGC0L  ========================================================= */
+ #define R_CEC_LGC0L_LGC0L_Pos           (0UL)      /*!< LGC0L (Bit 0)                                         */
+ #define R_CEC_LGC0L_LGC0L_Msk           (0x1ffUL)  /*!< LGC0L (Bitfield-Mask: 0x1ff)                          */
+/* =========================================================  LGC1L  ========================================================= */
+ #define R_CEC_LGC1L_LGC1L_Pos           (0UL)      /*!< LGC1L (Bit 0)                                         */
+ #define R_CEC_LGC1L_LGC1L_Msk           (0x1ffUL)  /*!< LGC1L (Bitfield-Mask: 0x1ff)                          */
+/* =========================================================  DATB  ========================================================== */
+ #define R_CEC_DATB_DATB_Pos             (0UL)      /*!< DATB (Bit 0)                                          */
+ #define R_CEC_DATB_DATB_Msk             (0x1ffUL)  /*!< DATB (Bitfield-Mask: 0x1ff)                           */
+/* =========================================================  NOMT  ========================================================== */
+ #define R_CEC_NOMT_NOMT_Pos             (0UL)      /*!< NOMT (Bit 0)                                          */
+ #define R_CEC_NOMT_NOMT_Msk             (0x1ffUL)  /*!< NOMT (Bitfield-Mask: 0x1ff)                           */
+/* ========================================================  STATLL  ========================================================= */
+ #define R_CEC_STATLL_STATLL_Pos         (0UL)      /*!< STATLL (Bit 0)                                        */
+ #define R_CEC_STATLL_STATLL_Msk         (0x1ffUL)  /*!< STATLL (Bitfield-Mask: 0x1ff)                         */
+/* ========================================================  STATLH  ========================================================= */
+ #define R_CEC_STATLH_STATLH_Pos         (0UL)      /*!< STATLH (Bit 0)                                        */
+ #define R_CEC_STATLH_STATLH_Msk         (0x1ffUL)  /*!< STATLH (Bitfield-Mask: 0x1ff)                         */
+/* ========================================================  STATBL  ========================================================= */
+ #define R_CEC_STATBL_STATBL_Pos         (0UL)      /*!< STATBL (Bit 0)                                        */
+ #define R_CEC_STATBL_STATBL_Msk         (0x1ffUL)  /*!< STATBL (Bitfield-Mask: 0x1ff)                         */
+/* ========================================================  STATBH  ========================================================= */
+ #define R_CEC_STATBH_STATBH_Pos         (0UL)      /*!< STATBH (Bit 0)                                        */
+ #define R_CEC_STATBH_STATBH_Msk         (0x1ffUL)  /*!< STATBH (Bitfield-Mask: 0x1ff)                         */
+/* ========================================================  LGC0LL  ========================================================= */
+ #define R_CEC_LGC0LL_LGC0LL_Pos         (0UL)      /*!< LGC0LL (Bit 0)                                        */
+ #define R_CEC_LGC0LL_LGC0LL_Msk         (0x1ffUL)  /*!< LGC0LL (Bitfield-Mask: 0x1ff)                         */
+/* ========================================================  LGC0LH  ========================================================= */
+ #define R_CEC_LGC0LH_LGC0LH_Pos         (0UL)      /*!< LGC0LH (Bit 0)                                        */
+ #define R_CEC_LGC0LH_LGC0LH_Msk         (0x1ffUL)  /*!< LGC0LH (Bitfield-Mask: 0x1ff)                         */
+/* ========================================================  LGC1LL  ========================================================= */
+ #define R_CEC_LGC1LL_LGC1LL_Pos         (0UL)      /*!< LGC1LL (Bit 0)                                        */
+ #define R_CEC_LGC1LL_LGC1LL_Msk         (0x1ffUL)  /*!< LGC1LL (Bitfield-Mask: 0x1ff)                         */
+/* ========================================================  LGC1LH  ========================================================= */
+ #define R_CEC_LGC1LH_LGC1LH_Pos         (0UL)      /*!< LGC1LH (Bit 0)                                        */
+ #define R_CEC_LGC1LH_LGC1LH_Msk         (0x1ffUL)  /*!< LGC1LH (Bitfield-Mask: 0x1ff)                         */
+/* =========================================================  DATBL  ========================================================= */
+ #define R_CEC_DATBL_DATBL_Pos           (0UL)      /*!< DATBL (Bit 0)                                         */
+ #define R_CEC_DATBL_DATBL_Msk           (0x1ffUL)  /*!< DATBL (Bitfield-Mask: 0x1ff)                          */
+/* =========================================================  DATBH  ========================================================= */
+ #define R_CEC_DATBH_DATBH_Pos           (0UL)      /*!< DATBH (Bit 0)                                         */
+ #define R_CEC_DATBH_DATBH_Msk           (0x1ffUL)  /*!< DATBH (Bitfield-Mask: 0x1ff)                          */
+/* =========================================================  NOMP  ========================================================== */
+ #define R_CEC_NOMP_NOMP_Pos             (0UL)      /*!< NOMP (Bit 0)                                          */
+ #define R_CEC_NOMP_NOMP_Msk             (0x1ffUL)  /*!< NOMP (Bitfield-Mask: 0x1ff)                           */
+/* ========================================================  CECEXMD  ======================================================== */
+ #define R_CEC_CECEXMD_LERPLEN_Pos       (4UL)      /*!< LERPLEN (Bit 4)                                       */
+ #define R_CEC_CECEXMD_LERPLEN_Msk       (0x10UL)   /*!< LERPLEN (Bitfield-Mask: 0x01)                         */
+ #define R_CEC_CECEXMD_RERCVEN_Pos       (5UL)      /*!< RERCVEN (Bit 5)                                       */
+ #define R_CEC_CECEXMD_RERCVEN_Msk       (0x20UL)   /*!< RERCVEN (Bitfield-Mask: 0x01)                         */
+ #define R_CEC_CECEXMD_RCVINTDSEL_Pos    (7UL)      /*!< RCVINTDSEL (Bit 7)                                    */
+ #define R_CEC_CECEXMD_RCVINTDSEL_Msk    (0x80UL)   /*!< RCVINTDSEL (Bitfield-Mask: 0x01)                      */
+/* =======================================================  CECEXMON  ======================================================== */
+ #define R_CEC_CECEXMON_CECLNMON_Pos     (0UL)      /*!< CECLNMON (Bit 0)                                      */
+ #define R_CEC_CECEXMON_CECLNMON_Msk     (0x1UL)    /*!< CECLNMON (Bitfield-Mask: 0x01)                        */
+ #define R_CEC_CECEXMON_ACKF_Pos         (1UL)      /*!< ACKF (Bit 1)                                          */
+ #define R_CEC_CECEXMON_ACKF_Msk         (0x2UL)    /*!< ACKF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  CTXD  ========================================================== */
+/* =========================================================  CRXD  ========================================================== */
+/* =========================================================  CECES  ========================================================= */
+ #define R_CEC_CECES_OERR_Pos            (0UL)      /*!< OERR (Bit 0)                                          */
+ #define R_CEC_CECES_OERR_Msk            (0x1UL)    /*!< OERR (Bitfield-Mask: 0x01)                            */
+ #define R_CEC_CECES_UERR_Pos            (1UL)      /*!< UERR (Bit 1)                                          */
+ #define R_CEC_CECES_UERR_Msk            (0x2UL)    /*!< UERR (Bitfield-Mask: 0x01)                            */
+ #define R_CEC_CECES_ACKERR_Pos          (2UL)      /*!< ACKERR (Bit 2)                                        */
+ #define R_CEC_CECES_ACKERR_Msk          (0x4UL)    /*!< ACKERR (Bitfield-Mask: 0x01)                          */
+ #define R_CEC_CECES_TERR_Pos            (3UL)      /*!< TERR (Bit 3)                                          */
+ #define R_CEC_CECES_TERR_Msk            (0x8UL)    /*!< TERR (Bitfield-Mask: 0x01)                            */
+ #define R_CEC_CECES_TXERR_Pos           (4UL)      /*!< TXERR (Bit 4)                                         */
+ #define R_CEC_CECES_TXERR_Msk           (0x10UL)   /*!< TXERR (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CECES_AERR_Pos            (5UL)      /*!< AERR (Bit 5)                                          */
+ #define R_CEC_CECES_AERR_Msk            (0x20UL)   /*!< AERR (Bitfield-Mask: 0x01)                            */
+ #define R_CEC_CECES_BLERR_Pos           (6UL)      /*!< BLERR (Bit 6)                                         */
+ #define R_CEC_CECES_BLERR_Msk           (0x40UL)   /*!< BLERR (Bitfield-Mask: 0x01)                           */
+/* =========================================================  CECS  ========================================================== */
+ #define R_CEC_CECS_ADRF_Pos             (0UL)      /*!< ADRF (Bit 0)                                          */
+ #define R_CEC_CECS_ADRF_Msk             (0x1UL)    /*!< ADRF (Bitfield-Mask: 0x01)                            */
+ #define R_CEC_CECS_BUSST_Pos            (1UL)      /*!< BUSST (Bit 1)                                         */
+ #define R_CEC_CECS_BUSST_Msk            (0x2UL)    /*!< BUSST (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CECS_TXST_Pos             (2UL)      /*!< TXST (Bit 2)                                          */
+ #define R_CEC_CECS_TXST_Msk             (0x4UL)    /*!< TXST (Bitfield-Mask: 0x01)                            */
+ #define R_CEC_CECS_EOMF_Pos             (3UL)      /*!< EOMF (Bit 3)                                          */
+ #define R_CEC_CECS_EOMF_Msk             (0x8UL)    /*!< EOMF (Bitfield-Mask: 0x01)                            */
+ #define R_CEC_CECS_ITCEF_Pos            (4UL)      /*!< ITCEF (Bit 4)                                         */
+ #define R_CEC_CECS_ITCEF_Msk            (0x10UL)   /*!< ITCEF (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CECS_SFTST_Pos            (7UL)      /*!< SFTST (Bit 7)                                         */
+ #define R_CEC_CECS_SFTST_Msk            (0x80UL)   /*!< SFTST (Bitfield-Mask: 0x01)                           */
+/* =========================================================  CECFC  ========================================================= */
+ #define R_CEC_CECFC_OCTRG_Pos           (0UL)      /*!< OCTRG (Bit 0)                                         */
+ #define R_CEC_CECFC_OCTRG_Msk           (0x1UL)    /*!< OCTRG (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CECFC_UCTRG_Pos           (1UL)      /*!< UCTRG (Bit 1)                                         */
+ #define R_CEC_CECFC_UCTRG_Msk           (0x2UL)    /*!< UCTRG (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CECFC_ACKCTRG_Pos         (2UL)      /*!< ACKCTRG (Bit 2)                                       */
+ #define R_CEC_CECFC_ACKCTRG_Msk         (0x4UL)    /*!< ACKCTRG (Bitfield-Mask: 0x01)                         */
+ #define R_CEC_CECFC_TCTRG_Pos           (3UL)      /*!< TCTRG (Bit 3)                                         */
+ #define R_CEC_CECFC_TCTRG_Msk           (0x8UL)    /*!< TCTRG (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CECFC_TXCTRG_Pos          (4UL)      /*!< TXCTRG (Bit 4)                                        */
+ #define R_CEC_CECFC_TXCTRG_Msk          (0x10UL)   /*!< TXCTRG (Bitfield-Mask: 0x01)                          */
+ #define R_CEC_CECFC_ACTRG_Pos           (5UL)      /*!< ACTRG (Bit 5)                                         */
+ #define R_CEC_CECFC_ACTRG_Msk           (0x20UL)   /*!< ACTRG (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CECFC_BLCTRG_Pos          (6UL)      /*!< BLCTRG (Bit 6)                                        */
+ #define R_CEC_CECFC_BLCTRG_Msk          (0x40UL)   /*!< BLCTRG (Bitfield-Mask: 0x01)                          */
+/* ========================================================  CECCTL0  ======================================================== */
+ #define R_CEC_CECCTL0_EOM_Pos           (0UL)      /*!< EOM (Bit 0)                                           */
+ #define R_CEC_CECCTL0_EOM_Msk           (0x1UL)    /*!< EOM (Bitfield-Mask: 0x01)                             */
+ #define R_CEC_CECCTL0_CECRXEN_Pos       (1UL)      /*!< CECRXEN (Bit 1)                                       */
+ #define R_CEC_CECCTL0_CECRXEN_Msk       (0x2UL)    /*!< CECRXEN (Bitfield-Mask: 0x01)                         */
+ #define R_CEC_CECCTL0_TXTRG_Pos         (2UL)      /*!< TXTRG (Bit 2)                                         */
+ #define R_CEC_CECCTL0_TXTRG_Msk         (0x4UL)    /*!< TXTRG (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CECCTL0_CCL_Pos           (3UL)      /*!< CCL (Bit 3)                                           */
+ #define R_CEC_CECCTL0_CCL_Msk           (0x38UL)   /*!< CCL (Bitfield-Mask: 0x07)                             */
+ #define R_CEC_CECCTL0_ACKTEN_Pos        (6UL)      /*!< ACKTEN (Bit 6)                                        */
+ #define R_CEC_CECCTL0_ACKTEN_Msk        (0x40UL)   /*!< ACKTEN (Bitfield-Mask: 0x01)                          */
+ #define R_CEC_CECCTL0_CECE_Pos          (7UL)      /*!< CECE (Bit 7)                                          */
+ #define R_CEC_CECCTL0_CECE_Msk          (0x80UL)   /*!< CECE (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_FLAD                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  FCKMHZ  ========================================================= */
+ #define R_FLAD_FCKMHZ_FCKMHZ_Pos    (0UL)    /*!< FCKMHZ (Bit 0)                                        */
+ #define R_FLAD_FCKMHZ_FCKMHZ_Msk    (0xffUL) /*!< FCKMHZ (Bitfield-Mask: 0xff)                          */
+
+/** @} */ /* End of group PosMask_peripherals */
+
+ #ifdef __cplusplus
+}
+ #endif
+
+#endif                                 /* R7FA4E2B9_H */
+
+/** @} */ /* End of group R7FA4E2B9 */
+
+/** @} */ /* End of group Renesas Electronics Corporation */
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h
index d824c35c4..154393c95 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h
@@ -830,7 +830,8 @@ typedef struct
             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
             uint8_t            : 1;
             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
-            uint8_t            : 2;
+            uint8_t            : 1;
+            __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
         } RTCCR_b;
     };
     __IM uint8_t RESERVED;
@@ -1002,6 +1003,213 @@ typedef struct
     };
 } R_USB_FS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
 
+/**
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
+            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
+            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
+            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
+            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
+            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
+        } AGTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
+            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
+            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
+            uint8_t              : 1;
+        } AGTMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+                                        *   ratio                                                                     */
+            uint8_t           : 4;
+            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
+        } AGTMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+                                        *   mode.                                                                     */
+            uint8_t             : 1;
+            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
+            uint8_t             : 1;
+            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
+            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
+        } AGTIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
+            uint8_t            : 5;
+        } AGTISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
+
+        struct
+        {
+            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
+            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
+            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
+            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
+            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
+            uint8_t              : 1;
+        } AGTCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_b;
+    };
+} R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
+
+        struct
+        {
+            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IM uint16_t                 RESERVED;
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
+} R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
+
+        struct
+        {
+            __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
+} R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_clusters */
 
 /* =========================================================================================================================== */
@@ -1380,16 +1588,17 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
 
     union
     {
-        __IM uint16_t ADDR[28];        /*!< (@ 0x00000020) A/D Data Register                                          */
+        __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
 
         struct
         {
             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
                                         *   storing the result of A/D conversion.                                     */
-        } ADDR_b[28];
+        } ADDR_b[29];
     };
-    __IM uint32_t RESERVED1[2];
-    __IM uint16_t RESERVED2;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+    __IM uint16_t RESERVED3;
 
     union
     {
@@ -1582,7 +1791,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint16_t                : 3;
         } ADSWTSTR2_b;
     };
-    __IM uint16_t RESERVED3;
+    __IM uint16_t RESERVED4;
 
     union
     {
@@ -1644,7 +1853,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 6;
         } ADACSR_b;
     };
-    __IM uint8_t RESERVED4;
+    __IM uint8_t RESERVED5;
 
     union
     {
@@ -1714,7 +1923,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
         } ADSER_b;
     };
-    __IM uint8_t RESERVED5;
+    __IM uint8_t RESERVED6;
 
     union
     {
@@ -1730,7 +1939,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
         } ADHVREFCNT_b;
     };
-    __IM uint8_t RESERVED6;
+    __IM uint8_t RESERVED7;
 
     union
     {
@@ -1748,8 +1957,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t              : 2;
         } ADWINMON_b;
     };
-    __IM uint8_t  RESERVED7;
-    __IM uint16_t RESERVED8;
+    __IM uint8_t  RESERVED8;
+    __IM uint16_t RESERVED9;
 
     union
     {
@@ -1925,7 +2134,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 6;
         } ADCMPSER_b;
     };
-    __IM uint8_t RESERVED9;
+    __IM uint8_t RESERVED10;
 
     union
     {
@@ -1940,7 +2149,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
         } ADCMPBNSR_b;
     };
-    __IM uint8_t RESERVED10;
+    __IM uint8_t RESERVED11;
 
     union
     {
@@ -1979,8 +2188,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 7;
         } ADCMPBSR_b;
     };
-    __IM uint8_t  RESERVED11;
-    __IM uint16_t RESERVED12;
+    __IM uint8_t  RESERVED12;
+    __IM uint16_t RESERVED13;
 
     union
     {
@@ -2184,7 +2393,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 7;
         } ADBUFEN_b;
     };
-    __IM uint8_t RESERVED13;
+    __IM uint8_t RESERVED14;
 
     union
     {
@@ -2198,9 +2407,9 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 3;
         } ADBUFPTR_b;
     };
-    __IM uint8_t  RESERVED14;
-    __IM uint32_t RESERVED15[2];
-    __IM uint8_t  RESERVED16;
+    __IM uint8_t  RESERVED15;
+    __IM uint32_t RESERVED16[2];
+    __IM uint8_t  RESERVED17;
 
     union
     {
@@ -2267,7 +2476,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
         } ADCALEXE_b;
     };
-    __IM uint8_t RESERVED17;
+    __IM uint8_t RESERVED18;
 
     union
     {
@@ -2284,8 +2493,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
         } VREFAMPCNT_b;
     };
-    __IM uint8_t  RESERVED18;
-    __IM uint16_t RESERVED19;
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -2307,8 +2516,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 6;
         } ADRST_b;
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint32_t RESERVED21[41];
+    __IM uint8_t  RESERVED21;
+    __IM uint32_t RESERVED22[41];
 
     union
     {
@@ -2366,7 +2575,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
         } ADPGAGS0_b;
     };
-    __IM uint32_t RESERVED22[3];
+    __IM uint32_t RESERVED23[3];
 
     union
     {
@@ -2393,7 +2602,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
         } ADPGADCR0_b;
     };
-    __IM uint16_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -2422,8 +2631,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 7;
         } ADPGADBS1_b;
     };
-    __IM uint16_t RESERVED24;
-    __IM uint32_t RESERVED25[10];
+    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED26[10];
 
     union
     {
@@ -2439,156 +2648,6 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
     };
 } R_ADC0_Type;                         /*!< Size = 484 (0x1e4)                                                        */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Asynchronous General Purpose Timer (R_AGT0)
- */
-
-typedef struct                         /*!< (@ 0x40084000) R_AGT0 Structure                                           */
-{
-    union
-    {
-        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
-
-        struct
-        {
-            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written
-                                        *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
-                                        *   is forcibly stopped and set to FFFFH.                                     */
-        } AGT_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCRn register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMA_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCR register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMB_b;
-    };
-    __IM uint16_t RESERVED;
-
-    union
-    {
-        __IOM uint8_t AGTCR;           /*!< (@ 0x00000008) AGT Control Register                                       */
-
-        struct
-        {
-            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
-            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
-            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
-            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
-            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
-            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
-        } AGTCR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000009) AGT Mode Register 1                                        */
-
-        struct
-        {
-            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
-            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
-            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
-            uint8_t              : 1;
-        } AGTMR1_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000A) AGT Mode Register 2                                        */
-
-        struct
-        {
-            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
-                                        *   ratio                                                                     */
-            uint8_t           : 4;
-            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
-        } AGTMR2_b;
-    };
-    __IM uint8_t RESERVED1;
-
-    union
-    {
-        __IOM uint8_t AGTIOC;          /*!< (@ 0x0000000C) AGT I/O Control Register                                   */
-
-        struct
-        {
-            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
-                                        *   mode.                                                                     */
-            uint8_t             : 1;
-            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
-            uint8_t             : 1;
-            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
-            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
-        } AGTIOC_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTISR;          /*!< (@ 0x0000000D) AGT Event Pin Select Register                              */
-
-        struct
-        {
-            uint8_t            : 2;
-            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
-            uint8_t            : 5;
-        } AGTISR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTCMSR;         /*!< (@ 0x0000000E) AGT Compare Match Function Select Register                 */
-
-        struct
-        {
-            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
-            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
-            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
-            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
-            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
-            uint8_t              : 1;
-        } AGTCMSR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x0000000F) AGT Pin Select Register                                    */
-
-        struct
-        {
-            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
-            uint8_t            : 2;
-            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
-            uint8_t            : 3;
-        } AGTIOSEL_b;
-    };
-} R_AGT0_Type;                         /*!< Size = 16 (0x10)                                                          */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -4861,46 +4920,99 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            uint32_t : 18;
         } GTSTR_b;
     };
 
@@ -4952,7 +5064,60 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
                                          *   1 means counter stop.                                                     */
-            uint32_t : 18;
+            __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
         } GTSTP_b;
     };
 
@@ -4976,7 +5141,24 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
-            uint32_t             : 18;
+            __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
         } GTCLR_b;
     };
 
@@ -5297,16 +5479,23 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+        __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
 
         struct
         {
-            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
-            uint32_t            : 15;
-            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
-            uint32_t            : 5;
-            __IOM uint32_t TPCS : 3;   /*!< [26..24] Timer Prescaler Select                                           */
-            uint32_t            : 5;
+            __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
+            uint32_t               : 7;
+            __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
+            __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
+            __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
+            __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
+            uint32_t               : 2;
+            __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
+            __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
+            uint32_t               : 4;
+            __IOM uint32_t TPCS    : 3; /*!< [26..24] Timer Prescaler Select                                           */
+            __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
+            uint32_t               : 3;
         } GTCR_b;
     };
 
@@ -5377,13 +5566,36 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
         struct
         {
-            uint32_t               : 24;
-            __IOM uint32_t GRP     : 2; /*!< [25..24] Output Disable Source Select                                     */
+            uint32_t            : 8;
+            __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
+            __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            uint32_t               : 4;
+            __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
             uint32_t               : 2;
-            __IOM uint32_t GRPDTE  : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
-            __IOM uint32_t GRPABH  : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable               */
-            __IOM uint32_t GRPABL  : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
-            __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
+            __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
+            __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
         } GTINTAD_b;
     };
 
@@ -5426,32 +5638,36 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTBER;          /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
 
         struct
         {
-            __IOM uint32_t BD0    : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
-            __IOM uint32_t BD1    : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
-            __IOM uint32_t BD2    : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
-            __IOM uint32_t BD3    : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
-            uint32_t              : 12;
-            __IOM uint32_t CCRA   : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
-            __IOM uint32_t CCRB   : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
-            __IOM uint32_t PR     : 2; /*!< [21..20] GTPR Buffer Operation                                            */
-            __OM uint32_t  CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
-                                        *   is read as 0.                                                             */
+            __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
+            __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+                                         *   is read as 0.                                                             */
             uint32_t             : 1;
-            __IOM uint32_t ADTTA : 2;  /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDA : 1;  /*!< [26..26] GTADTRA Double Buffer Operation                                  */
+            __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
             uint32_t             : 1;
-            __IOM uint32_t ADTTB : 2;  /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDB : 1;  /*!< [30..30] GTADTRB Double Buffer Operation                                  */
+            __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
             uint32_t             : 1;
         } GTBER_b;
     };
@@ -5675,7 +5891,126 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             uint32_t            : 31;
         } GTSOTR_b;
     };
-    __IM uint32_t RESERVED[5];
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
 
     union
     {
@@ -5709,7 +6044,7 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             uint32_t            : 4;
         } GTPC_b;
     };
-    __IM uint32_t RESERVED1[4];
+    __IM uint32_t RESERVED[4];
 
     union
     {
@@ -5751,17 +6086,137 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
         {
             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 4;
             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
-            uint32_t             : 7;
+            __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
+            uint32_t             : 6;
             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
-            uint32_t             : 7;
+            __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
+            uint32_t             : 6;
         } GTSECR_b;
     };
-} R_GPT0_Type;                         /*!< Size = 216 (0xd8)                                                         */
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
+            __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
+                                        *   Disable                                                                   */
+            uint32_t             : 2;
+            __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t             : 1;
+            __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
+                                        *   Transfer Disable                                                          */
+            uint32_t             : 2;
+            __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
+            __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
+            __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
+            __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
+            uint32_t             : 2;
+        } GTBER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
+
+        struct
+        {
+            __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
+            uint32_t              : 11;
+            __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
+            uint32_t              : 11;
+        } GTOLBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
+                                        *                  Capture Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
+            __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
+                                        *   Other Channel GTCCRb Input Capture Source Enable                          */
+            __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
+        } GTICCR_b;
+    };
+} R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_OPS                                         ================ */
@@ -9583,8 +10038,18 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } IICCKDIVCR_b;
         };
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint16_t RESERVED21;
+
+    union
+    {
+        __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
+
+        struct
+        {
+            __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
+            uint8_t                : 5;
+        } I3CCKDIVCR_b;
+    };
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -9711,8 +10176,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
         } I3CCKCR_b;
     };
-    __IM uint16_t RESERVED22;
-    __IM uint32_t RESERVED23[3];
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
 
     union
     {
@@ -9726,8 +10191,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                 : 29;
         } SNZREQCR1_b;
     };
-    __IM uint32_t RESERVED24;
-    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -9742,7 +10207,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
         } SNZCR_b;
     };
-    __IM uint8_t RESERVED26;
+    __IM uint8_t RESERVED25;
 
     union
     {
@@ -9772,7 +10237,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } SNZEDCR1_b;
     };
-    __IM uint16_t RESERVED27;
+    __IM uint16_t RESERVED26;
 
     union
     {
@@ -9815,7 +10280,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 1;
         } SNZREQCR_b;
     };
-    __IM uint16_t RESERVED28;
+    __IM uint16_t RESERVED27;
 
     union
     {
@@ -9853,7 +10318,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 3;
         } OPCCR_b;
     };
-    __IM uint8_t RESERVED29;
+    __IM uint8_t RESERVED28;
 
     union
     {
@@ -9865,7 +10330,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } MOSCWTCR_b;
     };
-    __IM uint8_t RESERVED30[2];
+    __IM uint8_t RESERVED29[2];
 
     union
     {
@@ -9878,7 +10343,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t : 5;
         } HOCOWTCR_b;
     };
-    __IM uint16_t RESERVED31[2];
+    __IM uint16_t RESERVED30[2];
 
     union
     {
@@ -9892,8 +10357,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 3;
         } SOPCCR_b;
     };
-    __IM uint8_t  RESERVED32;
-    __IM uint32_t RESERVED33[5];
+    __IM uint8_t  RESERVED31;
+    __IM uint32_t RESERVED32[5];
 
     union
     {
@@ -9927,8 +10392,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
         } RSTSR1_b;
     };
-    __IM uint16_t RESERVED34;
-    __IM uint32_t RESERVED35[3];
+    __IM uint16_t RESERVED33;
+    __IM uint32_t RESERVED34[3];
 
     union
     {
@@ -9954,8 +10419,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
         } SDADCCKCR_b;
     };
-    __IM uint16_t RESERVED36;
-    __IM uint32_t RESERVED37[3];
+    __IM uint16_t RESERVED35;
+    __IM uint32_t RESERVED36[3];
 
     union
     {
@@ -10010,7 +10475,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t          : 6;
         } LVD2SR_b;
     };
-    __IM uint32_t RESERVED38[183];
+    __IM uint32_t RESERVED37[183];
 
     union
     {
@@ -10038,7 +10503,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 14;
         } CGFSAR_b;
     };
-    __IM uint32_t RESERVED39;
+    __IM uint32_t RESERVED38;
 
     union
     {
@@ -10107,7 +10572,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 8;
         } BBFSAR_b;
     };
-    __IM uint32_t RESERVED40[3];
+    __IM uint32_t RESERVED39[3];
 
     union
     {
@@ -10169,8 +10634,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 4;
         } DPFSAR_b;
     };
-    __IM uint32_t RESERVED41[6];
-    __IM uint16_t RESERVED42;
+    __IM uint32_t RESERVED40[6];
+    __IM uint16_t RESERVED41;
 
     union
     {
@@ -10388,7 +10853,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 3;
         } DPSIEGR2_b;
     };
-    __IM uint8_t RESERVED43;
+    __IM uint8_t RESERVED42;
 
     union
     {
@@ -10446,7 +10911,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } RSTSR2_b;
     };
-    __IM uint8_t RESERVED44;
+    __IM uint8_t RESERVED43;
 
     union
     {
@@ -10463,7 +10928,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                           *   Enable                                                                    */
         } MOMCR_b;
     };
-    __IM uint16_t RESERVED45;
+    __IM uint16_t RESERVED44;
 
     union
     {
@@ -10533,7 +10998,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } LVD2CMPCR_b;
         };
     };
-    __IM uint8_t RESERVED46;
+    __IM uint8_t RESERVED45;
 
     union
     {
@@ -10566,7 +11031,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
         } LVD2CR0_b;
     };
-    __IM uint8_t RESERVED47;
+    __IM uint8_t RESERVED46;
 
     union
     {
@@ -10601,7 +11066,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 7;
         } VBTCR1_b;
     };
-    __IM uint32_t RESERVED48[8];
+    __IM uint32_t RESERVED47[8];
 
     union
     {
@@ -10644,7 +11109,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 6;
         } VCCSEL_b;
     };
-    __IM uint16_t RESERVED49;
+    __IM uint16_t RESERVED48;
 
     union
     {
@@ -10656,9 +11121,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } PL2LDOSCR_b;
     };
-    __IM uint8_t  RESERVED50;
-    __IM uint16_t RESERVED51;
-    __IM uint32_t RESERVED52[14];
+    __IM uint8_t  RESERVED49;
+    __IM uint16_t RESERVED50;
+    __IM uint32_t RESERVED51[14];
 
     union
     {
@@ -10681,8 +11146,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 6;
         } SOMCR_b;
     };
-    __IM uint16_t RESERVED53;
-    __IM uint32_t RESERVED54[3];
+    __IM uint16_t RESERVED52;
+    __IM uint32_t RESERVED53[3];
 
     union
     {
@@ -10694,7 +11159,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 7;
         } LOCOCR_b;
     };
-    __IM uint8_t RESERVED55;
+    __IM uint8_t RESERVED54;
 
     union
     {
@@ -10709,8 +11174,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                          *   trimming bits                                                             */
         } LOCOUTCR_b;
     };
-    __IM uint8_t  RESERVED56;
-    __IM uint32_t RESERVED57[7];
+    __IM uint8_t  RESERVED55;
+    __IM uint32_t RESERVED56[7];
 
     union
     {
@@ -10749,7 +11214,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 7;
         } VBTCMPCR_b;
     };
-    __IM uint8_t RESERVED58;
+    __IM uint8_t RESERVED57;
 
     union
     {
@@ -10763,7 +11228,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                  : 6;
         } VBTLVDICR_b;
     };
-    __IM uint8_t RESERVED59;
+    __IM uint8_t RESERVED58;
 
     union
     {
@@ -10775,7 +11240,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } VBTWCTLR_b;
     };
-    __IM uint8_t RESERVED60;
+    __IM uint8_t RESERVED59;
 
     union
     {
@@ -10910,9 +11375,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } VBTBER_b;
     };
-    __IM uint8_t  RESERVED61;
-    __IM uint16_t RESERVED62;
-    __IM uint32_t RESERVED63[15];
+    __IM uint8_t  RESERVED60;
+    __IM uint16_t RESERVED61;
+    __IM uint32_t RESERVED62[15];
 
     union
     {
@@ -12109,6 +12574,23 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
     __IM uint16_t RESERVED3;
 } R_WDT_Type;                          /*!< Size = 12 (0xc)                                                           */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
+ */
+
+typedef struct                          /*!< (@ 0x40084000) R_AGTX0 Structure                                          */
+{
+    union
+    {
+        __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
+        __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
+    };
+} R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_peripherals */
 
 /* =========================================================================================================================== */
@@ -12122,12 +12604,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_ACMPLP_BASE       0x40085E00UL
  #define R_ADC0_BASE         0x4005C000UL
  #define R_ADC1_BASE         0x4005C200UL
- #define R_AGT0_BASE         0x40084000UL
- #define R_AGT1_BASE         0x40084100UL
- #define R_AGT2_BASE         0x40084200UL
- #define R_AGT3_BASE         0x40084300UL
- #define R_AGT4_BASE         0x40084400UL
- #define R_AGT5_BASE         0x40084500UL
  #define R_BUS_BASE          0x40003000UL
  #define R_CAC_BASE          0x40044600UL
  #define R_CAN0_BASE         0x40050000UL
@@ -12217,6 +12693,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_TSN_BASE          0x407EC000UL
  #define R_USB_FS0_BASE      0x40090000UL
  #define R_WDT_BASE          0x40044200UL
+ #define R_AGTX0_BASE        0x40084000UL
+ #define R_AGTX1_BASE        0x40084100UL
+ #define R_AGTX2_BASE        0x40084200UL
+ #define R_AGTX3_BASE        0x40084300UL
+ #define R_AGTX4_BASE        0x40084400UL
+ #define R_AGTX5_BASE        0x40084500UL
+ #define R_AGTX6_BASE        0x40084600UL
+ #define R_AGTX7_BASE        0x40084700UL
+ #define R_AGTX8_BASE        0x40084800UL
+ #define R_AGTX9_BASE        0x40084900UL
 
 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
 
@@ -12231,12 +12717,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_ACMPLP       ((R_ACMPLP_Type *) R_ACMPLP_BASE)
  #define R_ADC0         ((R_ADC0_Type *) R_ADC0_BASE)
  #define R_ADC1         ((R_ADC0_Type *) R_ADC1_BASE)
- #define R_AGT0         ((R_AGT0_Type *) R_AGT0_BASE)
- #define R_AGT1         ((R_AGT0_Type *) R_AGT1_BASE)
- #define R_AGT2         ((R_AGT0_Type *) R_AGT2_BASE)
- #define R_AGT3         ((R_AGT0_Type *) R_AGT3_BASE)
- #define R_AGT4         ((R_AGT0_Type *) R_AGT4_BASE)
- #define R_AGT5         ((R_AGT0_Type *) R_AGT5_BASE)
  #define R_BUS          ((R_BUS_Type *) R_BUS_BASE)
  #define R_CAC          ((R_CAC_Type *) R_CAC_BASE)
  #define R_CAN0         ((R_CAN0_Type *) R_CAN0_BASE)
@@ -12326,6 +12806,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_TSN          ((R_TSN_Type *) R_TSN_BASE)
  #define R_USB_FS0      ((R_USB_FS0_Type *) R_USB_FS0_BASE)
  #define R_WDT          ((R_WDT_Type *) R_WDT_BASE)
+ #define R_AGTX0        ((R_AGTX0_Type *) R_AGTX0_BASE)
+ #define R_AGTX1        ((R_AGTX0_Type *) R_AGTX1_BASE)
+ #define R_AGTX2        ((R_AGTX0_Type *) R_AGTX2_BASE)
+ #define R_AGTX3        ((R_AGTX0_Type *) R_AGTX3_BASE)
+ #define R_AGTX4        ((R_AGTX0_Type *) R_AGTX4_BASE)
+ #define R_AGTX5        ((R_AGTX0_Type *) R_AGTX5_BASE)
+ #define R_AGTX6        ((R_AGTX0_Type *) R_AGTX6_BASE)
+ #define R_AGTX7        ((R_AGTX0_Type *) R_AGTX7_BASE)
+ #define R_AGTX8        ((R_AGTX0_Type *) R_AGTX8_BASE)
+ #define R_AGTX9        ((R_AGTX0_Type *) R_AGTX9_BASE)
 
 /** @} */ /* End of group Device_Peripheral_declaration */
 
@@ -12701,6 +13191,8 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 /* =========================================================================================================================== */
 
 /* =========================================================  RTCCR  ========================================================= */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
@@ -12765,6 +13257,101 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
 
+/* =========================================================================================================================== */
+/* ================                                           CTRL                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  AGTCR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AGTMR1  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
+/* ========================================================  AGTMR2  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
+/* =====================================================  AGTIOSEL_ALT  ====================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+/* ========================================================  AGTIOC  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AGTISR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AGTCMSR  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
+/* =======================================================  AGTIOSEL  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT16                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT32                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
+
 /** @} */ /* End of group PosMask_clusters */
 
 /* =========================================================================================================================== */
@@ -13324,77 +13911,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_ADC0_ADREFMON_MONSEL_Pos         (16UL)      /*!< MONSEL (Bit 16)                                       */
  #define R_ADC0_ADREFMON_MONSEL_Msk         (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f)                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/* ==========================================================  AGT  ========================================================== */
- #define R_AGT0_AGT_AGT_Pos           (0UL)      /*!< AGT (Bit 0)                                           */
- #define R_AGT0_AGT_AGT_Msk           (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
-/* ========================================================  AGTCMA  ========================================================= */
- #define R_AGT0_AGTCMA_AGTCMA_Pos     (0UL)      /*!< AGTCMA (Bit 0)                                        */
- #define R_AGT0_AGTCMA_AGTCMA_Msk     (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
-/* ========================================================  AGTCMB  ========================================================= */
- #define R_AGT0_AGTCMB_AGTCMB_Pos     (0UL)      /*!< AGTCMB (Bit 0)                                        */
- #define R_AGT0_AGTCMB_AGTCMB_Msk     (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
-/* =========================================================  AGTCR  ========================================================= */
- #define R_AGT0_AGTCR_TCMBF_Pos       (7UL)      /*!< TCMBF (Bit 7)                                         */
- #define R_AGT0_AGTCR_TCMBF_Msk       (0x80UL)   /*!< TCMBF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCMAF_Pos       (6UL)      /*!< TCMAF (Bit 6)                                         */
- #define R_AGT0_AGTCR_TCMAF_Msk       (0x40UL)   /*!< TCMAF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TUNDF_Pos       (5UL)      /*!< TUNDF (Bit 5)                                         */
- #define R_AGT0_AGTCR_TUNDF_Msk       (0x20UL)   /*!< TUNDF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TEDGF_Pos       (4UL)      /*!< TEDGF (Bit 4)                                         */
- #define R_AGT0_AGTCR_TEDGF_Msk       (0x10UL)   /*!< TEDGF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTOP_Pos       (2UL)      /*!< TSTOP (Bit 2)                                         */
- #define R_AGT0_AGTCR_TSTOP_Msk       (0x4UL)    /*!< TSTOP (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCSTF_Pos       (1UL)      /*!< TCSTF (Bit 1)                                         */
- #define R_AGT0_AGTCR_TCSTF_Msk       (0x2UL)    /*!< TCSTF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTART_Pos      (0UL)      /*!< TSTART (Bit 0)                                        */
- #define R_AGT0_AGTCR_TSTART_Msk      (0x1UL)    /*!< TSTART (Bitfield-Mask: 0x01)                          */
-/* ========================================================  AGTMR1  ========================================================= */
- #define R_AGT0_AGTMR1_TCK_Pos        (4UL)      /*!< TCK (Bit 4)                                           */
- #define R_AGT0_AGTMR1_TCK_Msk        (0x70UL)   /*!< TCK (Bitfield-Mask: 0x07)                             */
- #define R_AGT0_AGTMR1_TEDGPL_Pos     (3UL)      /*!< TEDGPL (Bit 3)                                        */
- #define R_AGT0_AGTMR1_TEDGPL_Msk     (0x8UL)    /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTMR1_TMOD_Pos       (0UL)      /*!< TMOD (Bit 0)                                          */
- #define R_AGT0_AGTMR1_TMOD_Msk       (0x7UL)    /*!< TMOD (Bitfield-Mask: 0x07)                            */
-/* ========================================================  AGTMR2  ========================================================= */
- #define R_AGT0_AGTMR2_LPM_Pos        (7UL)      /*!< LPM (Bit 7)                                           */
- #define R_AGT0_AGTMR2_LPM_Msk        (0x80UL)   /*!< LPM (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTMR2_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
- #define R_AGT0_AGTMR2_CKS_Msk        (0x7UL)    /*!< CKS (Bitfield-Mask: 0x07)                             */
-/* ========================================================  AGTIOC  ========================================================= */
- #define R_AGT0_AGTIOC_TIOGT_Pos      (6UL)      /*!< TIOGT (Bit 6)                                         */
- #define R_AGT0_AGTIOC_TIOGT_Msk      (0xc0UL)   /*!< TIOGT (Bitfield-Mask: 0x03)                           */
- #define R_AGT0_AGTIOC_TIPF_Pos       (4UL)      /*!< TIPF (Bit 4)                                          */
- #define R_AGT0_AGTIOC_TIPF_Msk       (0x30UL)   /*!< TIPF (Bitfield-Mask: 0x03)                            */
- #define R_AGT0_AGTIOC_TOE_Pos        (2UL)      /*!< TOE (Bit 2)                                           */
- #define R_AGT0_AGTIOC_TOE_Msk        (0x4UL)    /*!< TOE (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTIOC_TEDGSEL_Pos    (0UL)      /*!< TEDGSEL (Bit 0)                                       */
- #define R_AGT0_AGTIOC_TEDGSEL_Msk    (0x1UL)    /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
-/* ========================================================  AGTISR  ========================================================= */
- #define R_AGT0_AGTISR_EEPS_Pos       (2UL)      /*!< EEPS (Bit 2)                                          */
- #define R_AGT0_AGTISR_EEPS_Msk       (0x4UL)    /*!< EEPS (Bitfield-Mask: 0x01)                            */
-/* ========================================================  AGTCMSR  ======================================================== */
- #define R_AGT0_AGTCMSR_TOPOLB_Pos    (6UL)      /*!< TOPOLB (Bit 6)                                        */
- #define R_AGT0_AGTCMSR_TOPOLB_Msk    (0x40UL)   /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEB_Pos      (5UL)      /*!< TOEB (Bit 5)                                          */
- #define R_AGT0_AGTCMSR_TOEB_Msk      (0x20UL)   /*!< TOEB (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEB_Pos     (4UL)      /*!< TCMEB (Bit 4)                                         */
- #define R_AGT0_AGTCMSR_TCMEB_Msk     (0x10UL)   /*!< TCMEB (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCMSR_TOPOLA_Pos    (2UL)      /*!< TOPOLA (Bit 2)                                        */
- #define R_AGT0_AGTCMSR_TOPOLA_Msk    (0x4UL)    /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEA_Pos      (1UL)      /*!< TOEA (Bit 1)                                          */
- #define R_AGT0_AGTCMSR_TOEA_Msk      (0x2UL)    /*!< TOEA (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEA_Pos     (0UL)      /*!< TCMEA (Bit 0)                                         */
- #define R_AGT0_AGTCMSR_TCMEA_Msk     (0x1UL)    /*!< TCMEA (Bitfield-Mask: 0x01)                           */
-/* =======================================================  AGTIOSEL  ======================================================== */
- #define R_AGT0_AGTIOSEL_TIES_Pos     (4UL)      /*!< TIES (Bit 4)                                          */
- #define R_AGT0_AGTIOSEL_TIES_Msk     (0x10UL)   /*!< TIES (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTIOSEL_SEL_Pos      (0UL)      /*!< SEL (Bit 0)                                           */
- #define R_AGT0_AGTIOSEL_SEL_Msk      (0x3UL)    /*!< SEL (Bitfield-Mask: 0x03)                             */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -14685,10 +15201,22 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
 /* =========================================================  GTCR  ========================================================== */
+ #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
+ #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTCR_TPCS_Pos              (24UL)         /*!< TPCS (Bit 24)                                         */
  #define R_GPT0_GTCR_TPCS_Msk              (0x7000000UL)  /*!< TPCS (Bitfield-Mask: 0x07)                            */
  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
- #define R_GPT0_GTCR_MD_Msk                (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
+ #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
+ #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
+ #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
+ #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
 /* =======================================================  GTUDDTYC  ======================================================== */
@@ -14746,6 +15274,8 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
 /* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
+ #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
@@ -14754,8 +15284,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
- #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
- #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
+ #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
+ #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
+ #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
 /* =========================================================  GTST  ========================================================== */
  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
@@ -14812,6 +15350,8 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
+ #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
@@ -14901,6 +15441,67 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 /* ========================================================  GTSOTR  ========================================================= */
  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
 /* ========================================================  GTICLF  ========================================================= */
  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
@@ -14943,14 +15544,113 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
+ #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
+ #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTBER2  ========================================================= */
+ #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
+ #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
+ #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
+ #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
+ #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
+ #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
+ #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
+ #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
+ #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
+ #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
+ #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
+ #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
+ #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
+ #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
+ #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
+ #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
+ #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
+ #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
+ #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
+ #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTOLBR  ========================================================= */
+ #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
+ #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
+ #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
+ #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  GTICCR  ========================================================= */
+ #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
+ #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
+ #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
+ #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
+ #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
+ #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
+ #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
+ #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
+ #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
+ #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
+ #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
+ #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
+ #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
+ #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
+ #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
+ #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
+ #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
+ #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
+ #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
+ #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
+ #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_OPS                                         ================ */
@@ -17317,6 +18017,9 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 /* ======================================================  CECCKDIVCR  ======================================================= */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  I3CCKDIVCR  ======================================================= */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
 /* ======================================================  IICCKDIVCR  ======================================================= */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
@@ -18122,6 +18825,10 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_WDT_WDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
  #define R_WDT_WDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
 /** @} */ /* End of group PosMask_peripherals */
 
  #ifdef __cplusplus
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h
index a738099d4..2078b7bdb 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h
@@ -799,7 +799,8 @@ typedef struct
             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
             uint8_t            : 1;
             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
-            uint8_t            : 2;
+            uint8_t            : 1;
+            __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
         } RTCCR_b;
     };
     __IM uint8_t RESERVED;
@@ -1144,6 +1145,213 @@ typedef struct
     };
 } R_USB_FS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
 
+/**
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
+            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
+            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
+            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
+            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
+            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
+        } AGTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
+            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
+            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
+            uint8_t              : 1;
+        } AGTMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+                                        *   ratio                                                                     */
+            uint8_t           : 4;
+            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
+        } AGTMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+                                        *   mode.                                                                     */
+            uint8_t             : 1;
+            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
+            uint8_t             : 1;
+            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
+            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
+        } AGTIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
+            uint8_t            : 5;
+        } AGTISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
+
+        struct
+        {
+            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
+            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
+            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
+            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
+            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
+            uint8_t              : 1;
+        } AGTCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_b;
+    };
+} R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
+
+        struct
+        {
+            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IM uint16_t                 RESERVED;
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
+} R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
+
+        struct
+        {
+            __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
+} R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_clusters */
 
 /* =========================================================================================================================== */
@@ -1436,16 +1644,17 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
 
     union
     {
-        __IM uint16_t ADDR[28];        /*!< (@ 0x00000020) A/D Data Register                                          */
+        __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
 
         struct
         {
             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
                                         *   storing the result of A/D conversion.                                     */
-        } ADDR_b[28];
+        } ADDR_b[29];
     };
-    __IM uint32_t RESERVED1[2];
-    __IM uint16_t RESERVED2;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+    __IM uint16_t RESERVED3;
 
     union
     {
@@ -1638,7 +1847,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint16_t                : 3;
         } ADSWTSTR2_b;
     };
-    __IM uint16_t RESERVED3;
+    __IM uint16_t RESERVED4;
 
     union
     {
@@ -1700,7 +1909,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 6;
         } ADACSR_b;
     };
-    __IM uint8_t RESERVED4;
+    __IM uint8_t RESERVED5;
 
     union
     {
@@ -1770,7 +1979,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
         } ADSER_b;
     };
-    __IM uint8_t RESERVED5;
+    __IM uint8_t RESERVED6;
 
     union
     {
@@ -1786,7 +1995,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
         } ADHVREFCNT_b;
     };
-    __IM uint8_t RESERVED6;
+    __IM uint8_t RESERVED7;
 
     union
     {
@@ -1804,8 +2013,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t              : 2;
         } ADWINMON_b;
     };
-    __IM uint8_t  RESERVED7;
-    __IM uint16_t RESERVED8;
+    __IM uint8_t  RESERVED8;
+    __IM uint16_t RESERVED9;
 
     union
     {
@@ -1981,7 +2190,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 6;
         } ADCMPSER_b;
     };
-    __IM uint8_t RESERVED9;
+    __IM uint8_t RESERVED10;
 
     union
     {
@@ -1996,7 +2205,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
         } ADCMPBNSR_b;
     };
-    __IM uint8_t RESERVED10;
+    __IM uint8_t RESERVED11;
 
     union
     {
@@ -2035,8 +2244,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 7;
         } ADCMPBSR_b;
     };
-    __IM uint8_t  RESERVED11;
-    __IM uint16_t RESERVED12;
+    __IM uint8_t  RESERVED12;
+    __IM uint16_t RESERVED13;
 
     union
     {
@@ -2240,7 +2449,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 7;
         } ADBUFEN_b;
     };
-    __IM uint8_t RESERVED13;
+    __IM uint8_t RESERVED14;
 
     union
     {
@@ -2254,9 +2463,9 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 3;
         } ADBUFPTR_b;
     };
-    __IM uint8_t  RESERVED14;
-    __IM uint32_t RESERVED15[2];
-    __IM uint8_t  RESERVED16;
+    __IM uint8_t  RESERVED15;
+    __IM uint32_t RESERVED16[2];
+    __IM uint8_t  RESERVED17;
 
     union
     {
@@ -2323,7 +2532,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
         } ADCALEXE_b;
     };
-    __IM uint8_t RESERVED17;
+    __IM uint8_t RESERVED18;
 
     union
     {
@@ -2340,8 +2549,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
         } VREFAMPCNT_b;
     };
-    __IM uint8_t  RESERVED18;
-    __IM uint16_t RESERVED19;
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -2363,8 +2572,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 6;
         } ADRST_b;
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint32_t RESERVED21[41];
+    __IM uint8_t  RESERVED21;
+    __IM uint32_t RESERVED22[41];
 
     union
     {
@@ -2422,7 +2631,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
         } ADPGAGS0_b;
     };
-    __IM uint32_t RESERVED22[3];
+    __IM uint32_t RESERVED23[3];
 
     union
     {
@@ -2449,7 +2658,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
         } ADPGADCR0_b;
     };
-    __IM uint16_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -2478,8 +2687,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 7;
         } ADPGADBS1_b;
     };
-    __IM uint16_t RESERVED24;
-    __IM uint32_t RESERVED25[10];
+    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED26[10];
 
     union
     {
@@ -2643,63 +2852,63 @@ typedef struct                         /*!< (@ 0x400E0000) R_PSCU Structure
 
     union
     {
-        __IM uint32_t CFSAMONA;        /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
+        __IOM uint32_t CFSAMONA;       /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
                                         *                  A                                                          */
 
         struct
         {
-            uint32_t           : 15;
-            __IM uint32_t CFS2 : 9;    /*!< [23..15] Code Flash Secure area 2                                         */
-            uint32_t           : 8;
+            uint32_t            : 15;
+            __IOM uint32_t CFS2 : 9;   /*!< [23..15] Code Flash Secure area 2                                         */
+            uint32_t            : 8;
         } CFSAMONA_b;
     };
 
     union
     {
-        __IM uint32_t CFSAMONB;        /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
+        __IOM uint32_t CFSAMONB;       /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
                                         *                  B                                                          */
 
         struct
         {
-            uint32_t           : 10;
-            __IM uint32_t CFS1 : 14;   /*!< [23..10] Code Flash Secure area 1                                         */
-            uint32_t           : 8;
+            uint32_t            : 10;
+            __IOM uint32_t CFS1 : 14;  /*!< [23..10] Code Flash Secure area 1                                         */
+            uint32_t            : 8;
         } CFSAMONB_b;
     };
 
     union
     {
-        __IM uint32_t DFSAMON;         /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register           */
+        __IOM uint32_t DFSAMON;        /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register           */
 
         struct
         {
-            uint32_t          : 10;
-            __IM uint32_t DFS : 6;     /*!< [15..10] Data flash Secure area                                           */
-            uint32_t          : 16;
+            uint32_t           : 10;
+            __IOM uint32_t DFS : 6;    /*!< [15..10] Data flash Secure area                                           */
+            uint32_t           : 16;
         } DFSAMON_b;
     };
 
     union
     {
-        __IM uint32_t SSAMONA;         /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A               */
+        __IOM uint32_t SSAMONA;        /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A               */
 
         struct
         {
-            uint32_t          : 13;
-            __IM uint32_t SS2 : 8;     /*!< [20..13] SRAM Secure area 2                                               */
-            uint32_t          : 11;
+            uint32_t           : 13;
+            __IOM uint32_t SS2 : 8;    /*!< [20..13] SRAM Secure area 2                                               */
+            uint32_t           : 11;
         } SSAMONA_b;
     };
 
     union
     {
-        __IM uint32_t SSAMONB;         /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B               */
+        __IOM uint32_t SSAMONB;        /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B               */
 
         struct
         {
-            uint32_t          : 10;
-            __IM uint32_t SS1 : 11;    /*!< [20..10] SRAM secure area 1                                               */
-            uint32_t          : 11;
+            uint32_t           : 10;
+            __IOM uint32_t SS1 : 11;   /*!< [20..10] SRAM secure area 1                                               */
+            uint32_t           : 11;
         } SSAMONB_b;
     };
 
@@ -2715,156 +2924,6 @@ typedef struct                         /*!< (@ 0x400E0000) R_PSCU Structure
     };
 } R_PSCU_Type;                         /*!< Size = 48 (0x30)                                                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Asynchronous General Purpose Timer (R_AGT0)
- */
-
-typedef struct                         /*!< (@ 0x400E8000) R_AGT0 Structure                                           */
-{
-    union
-    {
-        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
-
-        struct
-        {
-            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written
-                                        *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
-                                        *   is forcibly stopped and set to FFFFH.                                     */
-        } AGT_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCRn register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMA_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCR register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMB_b;
-    };
-    __IM uint16_t RESERVED;
-
-    union
-    {
-        __IOM uint8_t AGTCR;           /*!< (@ 0x00000008) AGT Control Register                                       */
-
-        struct
-        {
-            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
-            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
-            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
-            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
-            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
-            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
-        } AGTCR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000009) AGT Mode Register 1                                        */
-
-        struct
-        {
-            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
-            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
-            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
-            uint8_t              : 1;
-        } AGTMR1_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000A) AGT Mode Register 2                                        */
-
-        struct
-        {
-            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
-                                        *   ratio                                                                     */
-            uint8_t           : 4;
-            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
-        } AGTMR2_b;
-    };
-    __IM uint8_t RESERVED1;
-
-    union
-    {
-        __IOM uint8_t AGTIOC;          /*!< (@ 0x0000000C) AGT I/O Control Register                                   */
-
-        struct
-        {
-            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
-                                        *   mode.                                                                     */
-            uint8_t             : 1;
-            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
-            uint8_t             : 1;
-            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
-            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
-        } AGTIOC_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTISR;          /*!< (@ 0x0000000D) AGT Event Pin Select Register                              */
-
-        struct
-        {
-            uint8_t            : 2;
-            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
-            uint8_t            : 5;
-        } AGTISR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTCMSR;         /*!< (@ 0x0000000E) AGT Compare Match Function Select Register                 */
-
-        struct
-        {
-            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
-            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
-            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
-            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
-            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
-            uint8_t              : 1;
-        } AGTCMSR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x0000000F) AGT Pin Select Register                                    */
-
-        struct
-        {
-            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
-            uint8_t            : 2;
-            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
-            uint8_t            : 3;
-        } AGTIOSEL_b;
-    };
-} R_AGT0_Type;                         /*!< Size = 16 (0x10)                                                          */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -4967,46 +5026,99 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            uint32_t : 18;
         } GTSTR_b;
     };
 
@@ -5058,7 +5170,60 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
                                          *   1 means counter stop.                                                     */
-            uint32_t : 18;
+            __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
         } GTSTP_b;
     };
 
@@ -5082,7 +5247,24 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
-            uint32_t             : 18;
+            __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
         } GTCLR_b;
     };
 
@@ -5403,16 +5585,23 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+        __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
 
         struct
         {
-            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
-            uint32_t            : 15;
-            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
-            uint32_t            : 4;
-            __IOM uint32_t TPCS : 4;   /*!< [26..23] Timer Prescaler Select                                           */
-            uint32_t            : 5;
+            __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
+            uint32_t               : 7;
+            __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
+            __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
+            __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
+            __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
+            uint32_t               : 2;
+            __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
+            __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
+            uint32_t               : 3;
+            __IOM uint32_t TPCS    : 4; /*!< [26..23] Timer Prescaler Select                                           */
+            __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
+            uint32_t               : 3;
         } GTCR_b;
     };
 
@@ -5483,13 +5672,36 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
         struct
         {
-            uint32_t               : 24;
-            __IOM uint32_t GRP     : 2; /*!< [25..24] Output Disable Source Select                                     */
+            uint32_t            : 8;
+            __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
+            __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            uint32_t               : 4;
+            __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
             uint32_t               : 2;
-            __IOM uint32_t GRPDTE  : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
-            __IOM uint32_t GRPABH  : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable               */
-            __IOM uint32_t GRPABL  : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
-            __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
+            __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
+            __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
         } GTINTAD_b;
     };
 
@@ -5532,32 +5744,36 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTBER;          /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
 
         struct
         {
-            __IOM uint32_t BD0    : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
-            __IOM uint32_t BD1    : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
-            __IOM uint32_t BD2    : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
-            __IOM uint32_t BD3    : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
-            uint32_t              : 12;
-            __IOM uint32_t CCRA   : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
-            __IOM uint32_t CCRB   : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
-            __IOM uint32_t PR     : 2; /*!< [21..20] GTPR Buffer Operation                                            */
-            __OM uint32_t  CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
-                                        *   is read as 0.                                                             */
+            __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
+            __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+                                         *   is read as 0.                                                             */
             uint32_t             : 1;
-            __IOM uint32_t ADTTA : 2;  /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDA : 1;  /*!< [26..26] GTADTRA Double Buffer Operation                                  */
+            __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
             uint32_t             : 1;
-            __IOM uint32_t ADTTB : 2;  /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDB : 1;  /*!< [30..30] GTADTRB Double Buffer Operation                                  */
+            __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
             uint32_t             : 1;
         } GTBER_b;
     };
@@ -5781,7 +5997,126 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             uint32_t            : 31;
         } GTSOTR_b;
     };
-    __IM uint32_t RESERVED[5];
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
 
     union
     {
@@ -5815,7 +6150,7 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             uint32_t            : 4;
         } GTPC_b;
     };
-    __IM uint32_t RESERVED1[4];
+    __IM uint32_t RESERVED[4];
 
     union
     {
@@ -5857,17 +6192,137 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
         {
             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 4;
             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
-            uint32_t             : 7;
+            __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
+            uint32_t             : 6;
             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
-            uint32_t             : 7;
+            __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
+            uint32_t             : 6;
         } GTSECR_b;
     };
-} R_GPT0_Type;                         /*!< Size = 216 (0xd8)                                                         */
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
+            __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
+                                        *   Disable                                                                   */
+            uint32_t             : 2;
+            __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t             : 1;
+            __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
+                                        *   Transfer Disable                                                          */
+            uint32_t             : 2;
+            __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
+            __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
+            __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
+            __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
+            uint32_t             : 2;
+        } GTBER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
+
+        struct
+        {
+            __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
+            uint32_t              : 11;
+            __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
+            uint32_t              : 11;
+        } GTOLBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
+                                        *                  Capture Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
+            __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
+                                        *   Other Channel GTCCRb Input Capture Source Enable                          */
+            __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
+        } GTICCR_b;
+    };
+} R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_OPS                                         ================ */
@@ -10452,8 +10907,18 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } IICCKDIVCR_b;
         };
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint16_t RESERVED21;
+
+    union
+    {
+        __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
+
+        struct
+        {
+            __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
+            uint8_t                : 5;
+        } I3CCKDIVCR_b;
+    };
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -10580,8 +11045,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
         } I3CCKCR_b;
     };
-    __IM uint16_t RESERVED22;
-    __IM uint32_t RESERVED23[3];
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
 
     union
     {
@@ -10595,8 +11060,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                 : 29;
         } SNZREQCR1_b;
     };
-    __IM uint32_t RESERVED24;
-    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -10611,7 +11076,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
         } SNZCR_b;
     };
-    __IM uint8_t RESERVED26;
+    __IM uint8_t RESERVED25;
 
     union
     {
@@ -10641,7 +11106,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } SNZEDCR1_b;
     };
-    __IM uint16_t RESERVED27;
+    __IM uint16_t RESERVED26;
 
     union
     {
@@ -10684,7 +11149,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 1;
         } SNZREQCR_b;
     };
-    __IM uint16_t RESERVED28;
+    __IM uint16_t RESERVED27;
 
     union
     {
@@ -10722,7 +11187,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 3;
         } OPCCR_b;
     };
-    __IM uint8_t RESERVED29;
+    __IM uint8_t RESERVED28;
 
     union
     {
@@ -10734,7 +11199,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } MOSCWTCR_b;
     };
-    __IM uint8_t RESERVED30[2];
+    __IM uint8_t RESERVED29[2];
 
     union
     {
@@ -10747,7 +11212,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t : 5;
         } HOCOWTCR_b;
     };
-    __IM uint16_t RESERVED31[2];
+    __IM uint16_t RESERVED30[2];
 
     union
     {
@@ -10761,8 +11226,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 3;
         } SOPCCR_b;
     };
-    __IM uint8_t  RESERVED32;
-    __IM uint32_t RESERVED33[5];
+    __IM uint8_t  RESERVED31;
+    __IM uint32_t RESERVED32[5];
 
     union
     {
@@ -10796,8 +11261,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
         } RSTSR1_b;
     };
-    __IM uint16_t RESERVED34;
-    __IM uint32_t RESERVED35[3];
+    __IM uint16_t RESERVED33;
+    __IM uint32_t RESERVED34[3];
 
     union
     {
@@ -10823,8 +11288,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
         } SDADCCKCR_b;
     };
-    __IM uint16_t RESERVED36;
-    __IM uint32_t RESERVED37[3];
+    __IM uint16_t RESERVED35;
+    __IM uint32_t RESERVED36[3];
 
     union
     {
@@ -10879,7 +11344,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t          : 6;
         } LVD2SR_b;
     };
-    __IM uint32_t RESERVED38[183];
+    __IM uint32_t RESERVED37[183];
 
     union
     {
@@ -10907,7 +11372,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 14;
         } CGFSAR_b;
     };
-    __IM uint32_t RESERVED39;
+    __IM uint32_t RESERVED38;
 
     union
     {
@@ -10976,7 +11441,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 8;
         } BBFSAR_b;
     };
-    __IM uint32_t RESERVED40[3];
+    __IM uint32_t RESERVED39[3];
 
     union
     {
@@ -11038,8 +11503,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 4;
         } DPFSAR_b;
     };
-    __IM uint32_t RESERVED41[6];
-    __IM uint16_t RESERVED42;
+    __IM uint32_t RESERVED40[6];
+    __IM uint16_t RESERVED41;
 
     union
     {
@@ -11257,7 +11722,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 3;
         } DPSIEGR2_b;
     };
-    __IM uint8_t RESERVED43;
+    __IM uint8_t RESERVED42;
 
     union
     {
@@ -11315,7 +11780,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } RSTSR2_b;
     };
-    __IM uint8_t RESERVED44;
+    __IM uint8_t RESERVED43;
 
     union
     {
@@ -11332,7 +11797,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                           *   Enable                                                                    */
         } MOMCR_b;
     };
-    __IM uint16_t RESERVED45;
+    __IM uint16_t RESERVED44;
 
     union
     {
@@ -11402,7 +11867,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } LVD2CMPCR_b;
         };
     };
-    __IM uint8_t RESERVED46;
+    __IM uint8_t RESERVED45;
 
     union
     {
@@ -11435,7 +11900,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
         } LVD2CR0_b;
     };
-    __IM uint8_t RESERVED47;
+    __IM uint8_t RESERVED46;
 
     union
     {
@@ -11470,7 +11935,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 7;
         } VBTCR1_b;
     };
-    __IM uint32_t RESERVED48[8];
+    __IM uint32_t RESERVED47[8];
 
     union
     {
@@ -11513,7 +11978,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 6;
         } VCCSEL_b;
     };
-    __IM uint16_t RESERVED49;
+    __IM uint16_t RESERVED48;
 
     union
     {
@@ -11525,9 +11990,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } PL2LDOSCR_b;
     };
-    __IM uint8_t  RESERVED50;
-    __IM uint16_t RESERVED51;
-    __IM uint32_t RESERVED52[14];
+    __IM uint8_t  RESERVED49;
+    __IM uint16_t RESERVED50;
+    __IM uint32_t RESERVED51[14];
 
     union
     {
@@ -11550,8 +12015,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 6;
         } SOMCR_b;
     };
-    __IM uint16_t RESERVED53;
-    __IM uint32_t RESERVED54[3];
+    __IM uint16_t RESERVED52;
+    __IM uint32_t RESERVED53[3];
 
     union
     {
@@ -11563,7 +12028,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 7;
         } LOCOCR_b;
     };
-    __IM uint8_t RESERVED55;
+    __IM uint8_t RESERVED54;
 
     union
     {
@@ -11578,8 +12043,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                          *   trimming bits                                                             */
         } LOCOUTCR_b;
     };
-    __IM uint8_t  RESERVED56;
-    __IM uint32_t RESERVED57[7];
+    __IM uint8_t  RESERVED55;
+    __IM uint32_t RESERVED56[7];
 
     union
     {
@@ -11618,7 +12083,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 7;
         } VBTCMPCR_b;
     };
-    __IM uint8_t RESERVED58;
+    __IM uint8_t RESERVED57;
 
     union
     {
@@ -11632,7 +12097,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                  : 6;
         } VBTLVDICR_b;
     };
-    __IM uint8_t RESERVED59;
+    __IM uint8_t RESERVED58;
 
     union
     {
@@ -11644,7 +12109,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } VBTWCTLR_b;
     };
-    __IM uint8_t RESERVED60;
+    __IM uint8_t RESERVED59;
 
     union
     {
@@ -11779,9 +12244,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } VBTBER_b;
     };
-    __IM uint8_t  RESERVED61;
-    __IM uint16_t RESERVED62;
-    __IM uint32_t RESERVED63[15];
+    __IM uint8_t  RESERVED60;
+    __IM uint16_t RESERVED61;
+    __IM uint32_t RESERVED62[15];
 
     union
     {
@@ -13318,6 +13783,23 @@ typedef struct                           /*!< (@ 0x40008000) R_CPSCU Structure
     };
 } R_CPSCU_Type;                        /*!< Size = 1540 (0x604)                                                       */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
+ */
+
+typedef struct                          /*!< (@ 0x400E8000) R_AGTX0 Structure                                          */
+{
+    union
+    {
+        __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
+        __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
+    };
+} R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
 /* =========================================================================================================================== */
 /* ================                                          R_FLAD                                           ================ */
 /* =========================================================================================================================== */
@@ -13354,12 +13836,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_ADC0_BASE           0x40170000UL
  #define R_ADC1_BASE           0x40170200UL
  #define R_PSCU_BASE           0x400E0000UL
- #define R_AGT0_BASE           0x400E8000UL
- #define R_AGT1_BASE           0x400E8100UL
- #define R_AGT2_BASE           0x400E8200UL
- #define R_AGT3_BASE           0x400E8300UL
- #define R_AGT4_BASE           0x400E8400UL
- #define R_AGT5_BASE           0x400E8500UL
  #define R_BUS_BASE            0x40003000UL
  #define R_CAC_BASE            0x40083600UL
  #define R_CAN0_BASE           0x400A8000UL
@@ -13453,6 +13929,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_WDT_BASE            0x40083400UL
  #define R_TZF_BASE            0x40000E00UL
  #define R_CPSCU_BASE          0x40008000UL
+ #define R_AGTX0_BASE          0x400E8000UL
+ #define R_AGTX1_BASE          0x400E8100UL
+ #define R_AGTX2_BASE          0x400E8200UL
+ #define R_AGTX3_BASE          0x400E8300UL
+ #define R_AGTX4_BASE          0x400E8400UL
+ #define R_AGTX5_BASE          0x400E8500UL
+ #define R_AGTX6_BASE          0x400E8600UL
+ #define R_AGTX7_BASE          0x400E8700UL
+ #define R_AGTX8_BASE          0x400E8800UL
+ #define R_AGTX9_BASE          0x400E8900UL
  #define R_FLAD_BASE           0x407FC000UL
 
 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
@@ -13468,12 +13954,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_ADC0           ((R_ADC0_Type *) R_ADC0_BASE)
  #define R_ADC1           ((R_ADC0_Type *) R_ADC1_BASE)
  #define R_PSCU           ((R_PSCU_Type *) R_PSCU_BASE)
- #define R_AGT0           ((R_AGT0_Type *) R_AGT0_BASE)
- #define R_AGT1           ((R_AGT0_Type *) R_AGT1_BASE)
- #define R_AGT2           ((R_AGT0_Type *) R_AGT2_BASE)
- #define R_AGT3           ((R_AGT0_Type *) R_AGT3_BASE)
- #define R_AGT4           ((R_AGT0_Type *) R_AGT4_BASE)
- #define R_AGT5           ((R_AGT0_Type *) R_AGT5_BASE)
 
 /* #define R_BUS                       ((R_BUS_Type*)             R_BUS_BASE) */
  #define R_CAC            ((R_CAC_Type *) R_CAC_BASE)
@@ -13568,6 +14048,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_WDT            ((R_WDT_Type *) R_WDT_BASE)
  #define R_TZF            ((R_TZF_Type *) R_TZF_BASE)
  #define R_CPSCU          ((R_CPSCU_Type *) R_CPSCU_BASE)
+ #define R_AGTX0          ((R_AGTX0_Type *) R_AGTX0_BASE)
+ #define R_AGTX1          ((R_AGTX0_Type *) R_AGTX1_BASE)
+ #define R_AGTX2          ((R_AGTX0_Type *) R_AGTX2_BASE)
+ #define R_AGTX3          ((R_AGTX0_Type *) R_AGTX3_BASE)
+ #define R_AGTX4          ((R_AGTX0_Type *) R_AGTX4_BASE)
+ #define R_AGTX5          ((R_AGTX0_Type *) R_AGTX5_BASE)
+ #define R_AGTX6          ((R_AGTX0_Type *) R_AGTX6_BASE)
+ #define R_AGTX7          ((R_AGTX0_Type *) R_AGTX7_BASE)
+ #define R_AGTX8          ((R_AGTX0_Type *) R_AGTX8_BASE)
+ #define R_AGTX9          ((R_AGTX0_Type *) R_AGTX9_BASE)
  #define R_FLAD           ((R_FLAD_Type *) R_FLAD_BASE)
 
 /** @} */ /* End of group Device_Peripheral_declaration */
@@ -13925,6 +14415,8 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* =========================================================================================================================== */
 
 /* =========================================================  RTCCR  ========================================================= */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
@@ -14072,6 +14564,101 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
 
+/* =========================================================================================================================== */
+/* ================                                           CTRL                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  AGTCR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AGTMR1  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
+/* ========================================================  AGTMR2  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
+/* =====================================================  AGTIOSEL_ALT  ====================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+/* ========================================================  AGTIOC  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AGTISR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AGTCMSR  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
+/* =======================================================  AGTIOSEL  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT16                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT32                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
+
 /** @} */ /* End of group PosMask_clusters */
 
 /* =========================================================================================================================== */
@@ -14737,77 +15324,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_PSCU_DLMMON_DLMMON_Pos    (0UL)          /*!< DLMMON (Bit 0)                                        */
  #define R_PSCU_DLMMON_DLMMON_Msk    (0xfUL)        /*!< DLMMON (Bitfield-Mask: 0x0f)                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/* ==========================================================  AGT  ========================================================== */
- #define R_AGT0_AGT_AGT_Pos           (0UL)      /*!< AGT (Bit 0)                                           */
- #define R_AGT0_AGT_AGT_Msk           (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
-/* ========================================================  AGTCMA  ========================================================= */
- #define R_AGT0_AGTCMA_AGTCMA_Pos     (0UL)      /*!< AGTCMA (Bit 0)                                        */
- #define R_AGT0_AGTCMA_AGTCMA_Msk     (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
-/* ========================================================  AGTCMB  ========================================================= */
- #define R_AGT0_AGTCMB_AGTCMB_Pos     (0UL)      /*!< AGTCMB (Bit 0)                                        */
- #define R_AGT0_AGTCMB_AGTCMB_Msk     (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
-/* =========================================================  AGTCR  ========================================================= */
- #define R_AGT0_AGTCR_TCMBF_Pos       (7UL)      /*!< TCMBF (Bit 7)                                         */
- #define R_AGT0_AGTCR_TCMBF_Msk       (0x80UL)   /*!< TCMBF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCMAF_Pos       (6UL)      /*!< TCMAF (Bit 6)                                         */
- #define R_AGT0_AGTCR_TCMAF_Msk       (0x40UL)   /*!< TCMAF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TUNDF_Pos       (5UL)      /*!< TUNDF (Bit 5)                                         */
- #define R_AGT0_AGTCR_TUNDF_Msk       (0x20UL)   /*!< TUNDF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TEDGF_Pos       (4UL)      /*!< TEDGF (Bit 4)                                         */
- #define R_AGT0_AGTCR_TEDGF_Msk       (0x10UL)   /*!< TEDGF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTOP_Pos       (2UL)      /*!< TSTOP (Bit 2)                                         */
- #define R_AGT0_AGTCR_TSTOP_Msk       (0x4UL)    /*!< TSTOP (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCSTF_Pos       (1UL)      /*!< TCSTF (Bit 1)                                         */
- #define R_AGT0_AGTCR_TCSTF_Msk       (0x2UL)    /*!< TCSTF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTART_Pos      (0UL)      /*!< TSTART (Bit 0)                                        */
- #define R_AGT0_AGTCR_TSTART_Msk      (0x1UL)    /*!< TSTART (Bitfield-Mask: 0x01)                          */
-/* ========================================================  AGTMR1  ========================================================= */
- #define R_AGT0_AGTMR1_TCK_Pos        (4UL)      /*!< TCK (Bit 4)                                           */
- #define R_AGT0_AGTMR1_TCK_Msk        (0x70UL)   /*!< TCK (Bitfield-Mask: 0x07)                             */
- #define R_AGT0_AGTMR1_TEDGPL_Pos     (3UL)      /*!< TEDGPL (Bit 3)                                        */
- #define R_AGT0_AGTMR1_TEDGPL_Msk     (0x8UL)    /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTMR1_TMOD_Pos       (0UL)      /*!< TMOD (Bit 0)                                          */
- #define R_AGT0_AGTMR1_TMOD_Msk       (0x7UL)    /*!< TMOD (Bitfield-Mask: 0x07)                            */
-/* ========================================================  AGTMR2  ========================================================= */
- #define R_AGT0_AGTMR2_LPM_Pos        (7UL)      /*!< LPM (Bit 7)                                           */
- #define R_AGT0_AGTMR2_LPM_Msk        (0x80UL)   /*!< LPM (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTMR2_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
- #define R_AGT0_AGTMR2_CKS_Msk        (0x7UL)    /*!< CKS (Bitfield-Mask: 0x07)                             */
-/* ========================================================  AGTIOC  ========================================================= */
- #define R_AGT0_AGTIOC_TIOGT_Pos      (6UL)      /*!< TIOGT (Bit 6)                                         */
- #define R_AGT0_AGTIOC_TIOGT_Msk      (0xc0UL)   /*!< TIOGT (Bitfield-Mask: 0x03)                           */
- #define R_AGT0_AGTIOC_TIPF_Pos       (4UL)      /*!< TIPF (Bit 4)                                          */
- #define R_AGT0_AGTIOC_TIPF_Msk       (0x30UL)   /*!< TIPF (Bitfield-Mask: 0x03)                            */
- #define R_AGT0_AGTIOC_TOE_Pos        (2UL)      /*!< TOE (Bit 2)                                           */
- #define R_AGT0_AGTIOC_TOE_Msk        (0x4UL)    /*!< TOE (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTIOC_TEDGSEL_Pos    (0UL)      /*!< TEDGSEL (Bit 0)                                       */
- #define R_AGT0_AGTIOC_TEDGSEL_Msk    (0x1UL)    /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
-/* ========================================================  AGTISR  ========================================================= */
- #define R_AGT0_AGTISR_EEPS_Pos       (2UL)      /*!< EEPS (Bit 2)                                          */
- #define R_AGT0_AGTISR_EEPS_Msk       (0x4UL)    /*!< EEPS (Bitfield-Mask: 0x01)                            */
-/* ========================================================  AGTCMSR  ======================================================== */
- #define R_AGT0_AGTCMSR_TOPOLB_Pos    (6UL)      /*!< TOPOLB (Bit 6)                                        */
- #define R_AGT0_AGTCMSR_TOPOLB_Msk    (0x40UL)   /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEB_Pos      (5UL)      /*!< TOEB (Bit 5)                                          */
- #define R_AGT0_AGTCMSR_TOEB_Msk      (0x20UL)   /*!< TOEB (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEB_Pos     (4UL)      /*!< TCMEB (Bit 4)                                         */
- #define R_AGT0_AGTCMSR_TCMEB_Msk     (0x10UL)   /*!< TCMEB (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCMSR_TOPOLA_Pos    (2UL)      /*!< TOPOLA (Bit 2)                                        */
- #define R_AGT0_AGTCMSR_TOPOLA_Msk    (0x4UL)    /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEA_Pos      (1UL)      /*!< TOEA (Bit 1)                                          */
- #define R_AGT0_AGTCMSR_TOEA_Msk      (0x2UL)    /*!< TOEA (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEA_Pos     (0UL)      /*!< TCMEA (Bit 0)                                         */
- #define R_AGT0_AGTCMSR_TCMEA_Msk     (0x1UL)    /*!< TCMEA (Bitfield-Mask: 0x01)                           */
-/* =======================================================  AGTIOSEL  ======================================================== */
- #define R_AGT0_AGTIOSEL_TIES_Pos     (4UL)      /*!< TIES (Bit 4)                                          */
- #define R_AGT0_AGTIOSEL_TIES_Msk     (0x10UL)   /*!< TIES (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTIOSEL_SEL_Pos      (0UL)      /*!< SEL (Bit 0)                                           */
- #define R_AGT0_AGTIOSEL_SEL_Msk      (0x3UL)    /*!< SEL (Bitfield-Mask: 0x03)                             */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -16035,10 +16551,22 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
 /* =========================================================  GTCR  ========================================================== */
+ #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
+ #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTCR_TPCS_Pos              (23UL)         /*!< TPCS (Bit 23)                                         */
  #define R_GPT0_GTCR_TPCS_Msk              (0x7800000UL)  /*!< TPCS (Bitfield-Mask: 0x0f)                            */
  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
- #define R_GPT0_GTCR_MD_Msk                (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
+ #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
+ #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
+ #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
+ #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
 /* =======================================================  GTUDDTYC  ======================================================== */
@@ -16096,6 +16624,8 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
 /* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
+ #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
@@ -16104,8 +16634,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
- #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
- #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
+ #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
+ #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
+ #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
 /* =========================================================  GTST  ========================================================== */
  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
@@ -16162,6 +16700,8 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
+ #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
@@ -16251,6 +16791,67 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* ========================================================  GTSOTR  ========================================================= */
  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
 /* ========================================================  GTICLF  ========================================================= */
  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
@@ -16293,14 +16894,113 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
+ #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
+ #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTBER2  ========================================================= */
+ #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
+ #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
+ #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
+ #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
+ #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
+ #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
+ #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
+ #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
+ #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
+ #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
+ #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
+ #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
+ #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
+ #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
+ #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
+ #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
+ #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
+ #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
+ #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
+ #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTOLBR  ========================================================= */
+ #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
+ #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
+ #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
+ #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  GTICCR  ========================================================= */
+ #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
+ #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
+ #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
+ #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
+ #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
+ #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
+ #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
+ #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
+ #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
+ #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
+ #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
+ #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
+ #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
+ #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
+ #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
+ #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
+ #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
+ #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
+ #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
+ #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
+ #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_OPS                                         ================ */
@@ -18987,6 +19687,9 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* ======================================================  CECCKDIVCR  ======================================================= */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  I3CCKDIVCR  ======================================================= */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
 /* ======================================================  IICCKDIVCR  ======================================================= */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
@@ -19933,6 +20636,10 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_CPSCU_TEVTRCR_TEVTE_Pos           (0UL)          /*!< TEVTE (Bit 0)                                         */
  #define R_CPSCU_TEVTRCR_TEVTE_Msk           (0x1UL)        /*!< TEVTE (Bitfield-Mask: 0x01)                           */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
 /* =========================================================================================================================== */
 /* ================                                          R_FLAD                                           ================ */
 /* =========================================================================================================================== */
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h
index b269b2075..c4d2a9367 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h
@@ -799,7 +799,8 @@ typedef struct
             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
             uint8_t            : 1;
             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
-            uint8_t            : 2;
+            uint8_t            : 1;
+            __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
         } RTCCR_b;
     };
     __IM uint8_t RESERVED;
@@ -1144,6 +1145,213 @@ typedef struct
     };
 } R_USB_FS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
 
+/**
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
+            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
+            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
+            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
+            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
+            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
+        } AGTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
+            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
+            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
+            uint8_t              : 1;
+        } AGTMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+                                        *   ratio                                                                     */
+            uint8_t           : 4;
+            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
+        } AGTMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+                                        *   mode.                                                                     */
+            uint8_t             : 1;
+            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
+            uint8_t             : 1;
+            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
+            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
+        } AGTIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
+            uint8_t            : 5;
+        } AGTISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
+
+        struct
+        {
+            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
+            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
+            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
+            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
+            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
+            uint8_t              : 1;
+        } AGTCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_b;
+    };
+} R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
+
+        struct
+        {
+            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IM uint16_t                 RESERVED;
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
+} R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
+
+        struct
+        {
+            __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
+} R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_clusters */
 
 /* =========================================================================================================================== */
@@ -1436,16 +1644,17 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
 
     union
     {
-        __IM uint16_t ADDR[28];        /*!< (@ 0x00000020) A/D Data Register                                          */
+        __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
 
         struct
         {
             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
                                         *   storing the result of A/D conversion.                                     */
-        } ADDR_b[28];
+        } ADDR_b[29];
     };
-    __IM uint32_t RESERVED1[2];
-    __IM uint16_t RESERVED2;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+    __IM uint16_t RESERVED3;
 
     union
     {
@@ -1638,7 +1847,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint16_t                : 3;
         } ADSWTSTR2_b;
     };
-    __IM uint16_t RESERVED3;
+    __IM uint16_t RESERVED4;
 
     union
     {
@@ -1700,7 +1909,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 6;
         } ADACSR_b;
     };
-    __IM uint8_t RESERVED4;
+    __IM uint8_t RESERVED5;
 
     union
     {
@@ -1770,7 +1979,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
         } ADSER_b;
     };
-    __IM uint8_t RESERVED5;
+    __IM uint8_t RESERVED6;
 
     union
     {
@@ -1786,7 +1995,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
         } ADHVREFCNT_b;
     };
-    __IM uint8_t RESERVED6;
+    __IM uint8_t RESERVED7;
 
     union
     {
@@ -1804,8 +2013,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t              : 2;
         } ADWINMON_b;
     };
-    __IM uint8_t  RESERVED7;
-    __IM uint16_t RESERVED8;
+    __IM uint8_t  RESERVED8;
+    __IM uint16_t RESERVED9;
 
     union
     {
@@ -1981,7 +2190,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 6;
         } ADCMPSER_b;
     };
-    __IM uint8_t RESERVED9;
+    __IM uint8_t RESERVED10;
 
     union
     {
@@ -1996,7 +2205,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
         } ADCMPBNSR_b;
     };
-    __IM uint8_t RESERVED10;
+    __IM uint8_t RESERVED11;
 
     union
     {
@@ -2035,8 +2244,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 7;
         } ADCMPBSR_b;
     };
-    __IM uint8_t  RESERVED11;
-    __IM uint16_t RESERVED12;
+    __IM uint8_t  RESERVED12;
+    __IM uint16_t RESERVED13;
 
     union
     {
@@ -2240,7 +2449,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 7;
         } ADBUFEN_b;
     };
-    __IM uint8_t RESERVED13;
+    __IM uint8_t RESERVED14;
 
     union
     {
@@ -2254,9 +2463,9 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 3;
         } ADBUFPTR_b;
     };
-    __IM uint8_t  RESERVED14;
-    __IM uint32_t RESERVED15[2];
-    __IM uint8_t  RESERVED16;
+    __IM uint8_t  RESERVED15;
+    __IM uint32_t RESERVED16[2];
+    __IM uint8_t  RESERVED17;
 
     union
     {
@@ -2323,7 +2532,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
         } ADCALEXE_b;
     };
-    __IM uint8_t RESERVED17;
+    __IM uint8_t RESERVED18;
 
     union
     {
@@ -2340,8 +2549,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
         } VREFAMPCNT_b;
     };
-    __IM uint8_t  RESERVED18;
-    __IM uint16_t RESERVED19;
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -2363,8 +2572,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 6;
         } ADRST_b;
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint32_t RESERVED21[41];
+    __IM uint8_t  RESERVED21;
+    __IM uint32_t RESERVED22[41];
 
     union
     {
@@ -2422,7 +2631,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
         } ADPGAGS0_b;
     };
-    __IM uint32_t RESERVED22[3];
+    __IM uint32_t RESERVED23[3];
 
     union
     {
@@ -2449,7 +2658,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
         } ADPGADCR0_b;
     };
-    __IM uint16_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -2478,8 +2687,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 7;
         } ADPGADBS1_b;
     };
-    __IM uint16_t RESERVED24;
-    __IM uint32_t RESERVED25[10];
+    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED26[10];
 
     union
     {
@@ -2643,63 +2852,63 @@ typedef struct                         /*!< (@ 0x400E0000) R_PSCU Structure
 
     union
     {
-        __IM uint32_t CFSAMONA;        /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
+        __IOM uint32_t CFSAMONA;       /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
                                         *                  A                                                          */
 
         struct
         {
-            uint32_t           : 15;
-            __IM uint32_t CFS2 : 9;    /*!< [23..15] Code Flash Secure area 2                                         */
-            uint32_t           : 8;
+            uint32_t            : 15;
+            __IOM uint32_t CFS2 : 9;   /*!< [23..15] Code Flash Secure area 2                                         */
+            uint32_t            : 8;
         } CFSAMONA_b;
     };
 
     union
     {
-        __IM uint32_t CFSAMONB;        /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
+        __IOM uint32_t CFSAMONB;       /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
                                         *                  B                                                          */
 
         struct
         {
-            uint32_t           : 10;
-            __IM uint32_t CFS1 : 14;   /*!< [23..10] Code Flash Secure area 1                                         */
-            uint32_t           : 8;
+            uint32_t            : 10;
+            __IOM uint32_t CFS1 : 14;  /*!< [23..10] Code Flash Secure area 1                                         */
+            uint32_t            : 8;
         } CFSAMONB_b;
     };
 
     union
     {
-        __IM uint32_t DFSAMON;         /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register           */
+        __IOM uint32_t DFSAMON;        /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register           */
 
         struct
         {
-            uint32_t          : 10;
-            __IM uint32_t DFS : 6;     /*!< [15..10] Data flash Secure area                                           */
-            uint32_t          : 16;
+            uint32_t           : 10;
+            __IOM uint32_t DFS : 6;    /*!< [15..10] Data flash Secure area                                           */
+            uint32_t           : 16;
         } DFSAMON_b;
     };
 
     union
     {
-        __IM uint32_t SSAMONA;         /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A               */
+        __IOM uint32_t SSAMONA;        /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A               */
 
         struct
         {
-            uint32_t          : 13;
-            __IM uint32_t SS2 : 8;     /*!< [20..13] SRAM Secure area 2                                               */
-            uint32_t          : 11;
+            uint32_t           : 13;
+            __IOM uint32_t SS2 : 8;    /*!< [20..13] SRAM Secure area 2                                               */
+            uint32_t           : 11;
         } SSAMONA_b;
     };
 
     union
     {
-        __IM uint32_t SSAMONB;         /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B               */
+        __IOM uint32_t SSAMONB;        /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B               */
 
         struct
         {
-            uint32_t          : 10;
-            __IM uint32_t SS1 : 11;    /*!< [20..10] SRAM secure area 1                                               */
-            uint32_t          : 11;
+            uint32_t           : 10;
+            __IOM uint32_t SS1 : 11;   /*!< [20..10] SRAM secure area 1                                               */
+            uint32_t           : 11;
         } SSAMONB_b;
     };
 
@@ -2715,156 +2924,6 @@ typedef struct                         /*!< (@ 0x400E0000) R_PSCU Structure
     };
 } R_PSCU_Type;                         /*!< Size = 48 (0x30)                                                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Asynchronous General Purpose Timer (R_AGT0)
- */
-
-typedef struct                         /*!< (@ 0x400E8000) R_AGT0 Structure                                           */
-{
-    union
-    {
-        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
-
-        struct
-        {
-            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written
-                                        *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
-                                        *   is forcibly stopped and set to FFFFH.                                     */
-        } AGT_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCRn register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMA_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCR register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMB_b;
-    };
-    __IM uint16_t RESERVED;
-
-    union
-    {
-        __IOM uint8_t AGTCR;           /*!< (@ 0x00000008) AGT Control Register                                       */
-
-        struct
-        {
-            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
-            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
-            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
-            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
-            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
-            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
-        } AGTCR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000009) AGT Mode Register 1                                        */
-
-        struct
-        {
-            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
-            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
-            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
-            uint8_t              : 1;
-        } AGTMR1_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000A) AGT Mode Register 2                                        */
-
-        struct
-        {
-            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
-                                        *   ratio                                                                     */
-            uint8_t           : 4;
-            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
-        } AGTMR2_b;
-    };
-    __IM uint8_t RESERVED1;
-
-    union
-    {
-        __IOM uint8_t AGTIOC;          /*!< (@ 0x0000000C) AGT I/O Control Register                                   */
-
-        struct
-        {
-            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
-                                        *   mode.                                                                     */
-            uint8_t             : 1;
-            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
-            uint8_t             : 1;
-            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
-            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
-        } AGTIOC_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTISR;          /*!< (@ 0x0000000D) AGT Event Pin Select Register                              */
-
-        struct
-        {
-            uint8_t            : 2;
-            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
-            uint8_t            : 5;
-        } AGTISR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTCMSR;         /*!< (@ 0x0000000E) AGT Compare Match Function Select Register                 */
-
-        struct
-        {
-            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
-            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
-            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
-            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
-            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
-            uint8_t              : 1;
-        } AGTCMSR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x0000000F) AGT Pin Select Register                                    */
-
-        struct
-        {
-            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
-            uint8_t            : 2;
-            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
-            uint8_t            : 3;
-        } AGTIOSEL_b;
-    };
-} R_AGT0_Type;                         /*!< Size = 16 (0x10)                                                          */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -4967,46 +5026,99 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            uint32_t : 18;
         } GTSTR_b;
     };
 
@@ -5058,7 +5170,60 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
                                          *   1 means counter stop.                                                     */
-            uint32_t : 18;
+            __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
         } GTSTP_b;
     };
 
@@ -5082,7 +5247,24 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
-            uint32_t             : 18;
+            __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
         } GTCLR_b;
     };
 
@@ -5403,16 +5585,23 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+        __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
 
         struct
         {
-            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
-            uint32_t            : 15;
-            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
-            uint32_t            : 4;
-            __IOM uint32_t TPCS : 4;   /*!< [26..23] Timer Prescaler Select                                           */
-            uint32_t            : 5;
+            __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
+            uint32_t               : 7;
+            __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
+            __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
+            __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
+            __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
+            uint32_t               : 2;
+            __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
+            __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
+            uint32_t               : 3;
+            __IOM uint32_t TPCS    : 4; /*!< [26..23] Timer Prescaler Select                                           */
+            __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
+            uint32_t               : 3;
         } GTCR_b;
     };
 
@@ -5483,13 +5672,36 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
         struct
         {
-            uint32_t               : 24;
-            __IOM uint32_t GRP     : 2; /*!< [25..24] Output Disable Source Select                                     */
+            uint32_t            : 8;
+            __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
+            __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            uint32_t               : 4;
+            __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
             uint32_t               : 2;
-            __IOM uint32_t GRPDTE  : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
-            __IOM uint32_t GRPABH  : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable               */
-            __IOM uint32_t GRPABL  : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
-            __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
+            __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
+            __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
         } GTINTAD_b;
     };
 
@@ -5532,32 +5744,36 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTBER;          /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
 
         struct
         {
-            __IOM uint32_t BD0    : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
-            __IOM uint32_t BD1    : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
-            __IOM uint32_t BD2    : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
-            __IOM uint32_t BD3    : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
-            uint32_t              : 12;
-            __IOM uint32_t CCRA   : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
-            __IOM uint32_t CCRB   : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
-            __IOM uint32_t PR     : 2; /*!< [21..20] GTPR Buffer Operation                                            */
-            __OM uint32_t  CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
-                                        *   is read as 0.                                                             */
+            __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
+            __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+                                         *   is read as 0.                                                             */
             uint32_t             : 1;
-            __IOM uint32_t ADTTA : 2;  /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDA : 1;  /*!< [26..26] GTADTRA Double Buffer Operation                                  */
+            __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
             uint32_t             : 1;
-            __IOM uint32_t ADTTB : 2;  /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDB : 1;  /*!< [30..30] GTADTRB Double Buffer Operation                                  */
+            __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
             uint32_t             : 1;
         } GTBER_b;
     };
@@ -5781,7 +5997,126 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             uint32_t            : 31;
         } GTSOTR_b;
     };
-    __IM uint32_t RESERVED[5];
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
 
     union
     {
@@ -5815,7 +6150,7 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             uint32_t            : 4;
         } GTPC_b;
     };
-    __IM uint32_t RESERVED1[4];
+    __IM uint32_t RESERVED[4];
 
     union
     {
@@ -5857,17 +6192,137 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
         {
             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 4;
             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
-            uint32_t             : 7;
+            __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
+            uint32_t             : 6;
             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
-            uint32_t             : 7;
+            __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
+            uint32_t             : 6;
         } GTSECR_b;
     };
-} R_GPT0_Type;                         /*!< Size = 216 (0xd8)                                                         */
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
+            __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
+                                        *   Disable                                                                   */
+            uint32_t             : 2;
+            __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t             : 1;
+            __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
+                                        *   Transfer Disable                                                          */
+            uint32_t             : 2;
+            __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
+            __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
+            __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
+            __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
+            uint32_t             : 2;
+        } GTBER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
+
+        struct
+        {
+            __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
+            uint32_t              : 11;
+            __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
+            uint32_t              : 11;
+        } GTOLBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
+                                        *                  Capture Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
+            __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
+                                        *   Other Channel GTCCRb Input Capture Source Enable                          */
+            __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
+        } GTICCR_b;
+    };
+} R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_OPS                                         ================ */
@@ -10452,8 +10907,18 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } IICCKDIVCR_b;
         };
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint16_t RESERVED21;
+
+    union
+    {
+        __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
+
+        struct
+        {
+            __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
+            uint8_t                : 5;
+        } I3CCKDIVCR_b;
+    };
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -10580,8 +11045,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
         } I3CCKCR_b;
     };
-    __IM uint16_t RESERVED22;
-    __IM uint32_t RESERVED23[3];
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
 
     union
     {
@@ -10595,8 +11060,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                 : 29;
         } SNZREQCR1_b;
     };
-    __IM uint32_t RESERVED24;
-    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -10611,7 +11076,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
         } SNZCR_b;
     };
-    __IM uint8_t RESERVED26;
+    __IM uint8_t RESERVED25;
 
     union
     {
@@ -10641,7 +11106,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } SNZEDCR1_b;
     };
-    __IM uint16_t RESERVED27;
+    __IM uint16_t RESERVED26;
 
     union
     {
@@ -10684,7 +11149,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 1;
         } SNZREQCR_b;
     };
-    __IM uint16_t RESERVED28;
+    __IM uint16_t RESERVED27;
 
     union
     {
@@ -10722,7 +11187,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 3;
         } OPCCR_b;
     };
-    __IM uint8_t RESERVED29;
+    __IM uint8_t RESERVED28;
 
     union
     {
@@ -10734,7 +11199,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } MOSCWTCR_b;
     };
-    __IM uint8_t RESERVED30[2];
+    __IM uint8_t RESERVED29[2];
 
     union
     {
@@ -10747,7 +11212,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t : 5;
         } HOCOWTCR_b;
     };
-    __IM uint16_t RESERVED31[2];
+    __IM uint16_t RESERVED30[2];
 
     union
     {
@@ -10761,8 +11226,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 3;
         } SOPCCR_b;
     };
-    __IM uint8_t  RESERVED32;
-    __IM uint32_t RESERVED33[5];
+    __IM uint8_t  RESERVED31;
+    __IM uint32_t RESERVED32[5];
 
     union
     {
@@ -10796,8 +11261,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
         } RSTSR1_b;
     };
-    __IM uint16_t RESERVED34;
-    __IM uint32_t RESERVED35[3];
+    __IM uint16_t RESERVED33;
+    __IM uint32_t RESERVED34[3];
 
     union
     {
@@ -10823,8 +11288,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
         } SDADCCKCR_b;
     };
-    __IM uint16_t RESERVED36;
-    __IM uint32_t RESERVED37[3];
+    __IM uint16_t RESERVED35;
+    __IM uint32_t RESERVED36[3];
 
     union
     {
@@ -10879,7 +11344,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t          : 6;
         } LVD2SR_b;
     };
-    __IM uint32_t RESERVED38[183];
+    __IM uint32_t RESERVED37[183];
 
     union
     {
@@ -10907,7 +11372,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 14;
         } CGFSAR_b;
     };
-    __IM uint32_t RESERVED39;
+    __IM uint32_t RESERVED38;
 
     union
     {
@@ -10976,7 +11441,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 8;
         } BBFSAR_b;
     };
-    __IM uint32_t RESERVED40[3];
+    __IM uint32_t RESERVED39[3];
 
     union
     {
@@ -11038,8 +11503,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 4;
         } DPFSAR_b;
     };
-    __IM uint32_t RESERVED41[6];
-    __IM uint16_t RESERVED42;
+    __IM uint32_t RESERVED40[6];
+    __IM uint16_t RESERVED41;
 
     union
     {
@@ -11257,7 +11722,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 3;
         } DPSIEGR2_b;
     };
-    __IM uint8_t RESERVED43;
+    __IM uint8_t RESERVED42;
 
     union
     {
@@ -11315,7 +11780,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } RSTSR2_b;
     };
-    __IM uint8_t RESERVED44;
+    __IM uint8_t RESERVED43;
 
     union
     {
@@ -11332,7 +11797,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                           *   Enable                                                                    */
         } MOMCR_b;
     };
-    __IM uint16_t RESERVED45;
+    __IM uint16_t RESERVED44;
 
     union
     {
@@ -11402,7 +11867,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } LVD2CMPCR_b;
         };
     };
-    __IM uint8_t RESERVED46;
+    __IM uint8_t RESERVED45;
 
     union
     {
@@ -11435,7 +11900,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
         } LVD2CR0_b;
     };
-    __IM uint8_t RESERVED47;
+    __IM uint8_t RESERVED46;
 
     union
     {
@@ -11470,7 +11935,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 7;
         } VBTCR1_b;
     };
-    __IM uint32_t RESERVED48[8];
+    __IM uint32_t RESERVED47[8];
 
     union
     {
@@ -11513,7 +11978,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 6;
         } VCCSEL_b;
     };
-    __IM uint16_t RESERVED49;
+    __IM uint16_t RESERVED48;
 
     union
     {
@@ -11525,9 +11990,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } PL2LDOSCR_b;
     };
-    __IM uint8_t  RESERVED50;
-    __IM uint16_t RESERVED51;
-    __IM uint32_t RESERVED52[14];
+    __IM uint8_t  RESERVED49;
+    __IM uint16_t RESERVED50;
+    __IM uint32_t RESERVED51[14];
 
     union
     {
@@ -11550,8 +12015,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 6;
         } SOMCR_b;
     };
-    __IM uint16_t RESERVED53;
-    __IM uint32_t RESERVED54[3];
+    __IM uint16_t RESERVED52;
+    __IM uint32_t RESERVED53[3];
 
     union
     {
@@ -11563,7 +12028,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 7;
         } LOCOCR_b;
     };
-    __IM uint8_t RESERVED55;
+    __IM uint8_t RESERVED54;
 
     union
     {
@@ -11578,8 +12043,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                          *   trimming bits                                                             */
         } LOCOUTCR_b;
     };
-    __IM uint8_t  RESERVED56;
-    __IM uint32_t RESERVED57[7];
+    __IM uint8_t  RESERVED55;
+    __IM uint32_t RESERVED56[7];
 
     union
     {
@@ -11618,7 +12083,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 7;
         } VBTCMPCR_b;
     };
-    __IM uint8_t RESERVED58;
+    __IM uint8_t RESERVED57;
 
     union
     {
@@ -11632,7 +12097,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                  : 6;
         } VBTLVDICR_b;
     };
-    __IM uint8_t RESERVED59;
+    __IM uint8_t RESERVED58;
 
     union
     {
@@ -11644,7 +12109,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } VBTWCTLR_b;
     };
-    __IM uint8_t RESERVED60;
+    __IM uint8_t RESERVED59;
 
     union
     {
@@ -11779,9 +12244,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } VBTBER_b;
     };
-    __IM uint8_t  RESERVED61;
-    __IM uint16_t RESERVED62;
-    __IM uint32_t RESERVED63[15];
+    __IM uint8_t  RESERVED60;
+    __IM uint16_t RESERVED61;
+    __IM uint32_t RESERVED62[15];
 
     union
     {
@@ -13421,6 +13886,23 @@ typedef struct                           /*!< (@ 0x40008000) R_CPSCU Structure
     };
 } R_CPSCU_Type;                        /*!< Size = 1540 (0x604)                                                       */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
+ */
+
+typedef struct                          /*!< (@ 0x400E8000) R_AGTX0 Structure                                          */
+{
+    union
+    {
+        __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
+        __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
+    };
+} R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
 /* =========================================================================================================================== */
 /* ================                                          R_FLAD                                           ================ */
 /* =========================================================================================================================== */
@@ -13457,12 +13939,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_ADC0_BASE           0x40170000UL
  #define R_ADC1_BASE           0x40170200UL
  #define R_PSCU_BASE           0x400E0000UL
- #define R_AGT0_BASE           0x400E8000UL
- #define R_AGT1_BASE           0x400E8100UL
- #define R_AGT2_BASE           0x400E8200UL
- #define R_AGT3_BASE           0x400E8300UL
- #define R_AGT4_BASE           0x400E8400UL
- #define R_AGT5_BASE           0x400E8500UL
  #define R_BUS_BASE            0x40003000UL
  #define R_CAC_BASE            0x40083600UL
  #define R_CAN0_BASE           0x400A8000UL
@@ -13557,6 +14033,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_TZF_BASE            0x40000E00UL
  #define R_CACHE_BASE          0x40007000UL
  #define R_CPSCU_BASE          0x40008000UL
+ #define R_AGTX0_BASE          0x400E8000UL
+ #define R_AGTX1_BASE          0x400E8100UL
+ #define R_AGTX2_BASE          0x400E8200UL
+ #define R_AGTX3_BASE          0x400E8300UL
+ #define R_AGTX4_BASE          0x400E8400UL
+ #define R_AGTX5_BASE          0x400E8500UL
+ #define R_AGTX6_BASE          0x400E8600UL
+ #define R_AGTX7_BASE          0x400E8700UL
+ #define R_AGTX8_BASE          0x400E8800UL
+ #define R_AGTX9_BASE          0x400E8900UL
  #define R_FLAD_BASE           0x407FC000UL
 
 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
@@ -13572,12 +14058,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_ADC0           ((R_ADC0_Type *) R_ADC0_BASE)
  #define R_ADC1           ((R_ADC0_Type *) R_ADC1_BASE)
  #define R_PSCU           ((R_PSCU_Type *) R_PSCU_BASE)
- #define R_AGT0           ((R_AGT0_Type *) R_AGT0_BASE)
- #define R_AGT1           ((R_AGT0_Type *) R_AGT1_BASE)
- #define R_AGT2           ((R_AGT0_Type *) R_AGT2_BASE)
- #define R_AGT3           ((R_AGT0_Type *) R_AGT3_BASE)
- #define R_AGT4           ((R_AGT0_Type *) R_AGT4_BASE)
- #define R_AGT5           ((R_AGT0_Type *) R_AGT5_BASE)
 
 /* #define R_BUS                       ((R_BUS_Type*)             R_BUS_BASE) */
  #define R_CAC            ((R_CAC_Type *) R_CAC_BASE)
@@ -13673,6 +14153,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_TZF            ((R_TZF_Type *) R_TZF_BASE)
  #define R_CACHE          ((R_CACHE_Type *) R_CACHE_BASE)
  #define R_CPSCU          ((R_CPSCU_Type *) R_CPSCU_BASE)
+ #define R_AGTX0          ((R_AGTX0_Type *) R_AGTX0_BASE)
+ #define R_AGTX1          ((R_AGTX0_Type *) R_AGTX1_BASE)
+ #define R_AGTX2          ((R_AGTX0_Type *) R_AGTX2_BASE)
+ #define R_AGTX3          ((R_AGTX0_Type *) R_AGTX3_BASE)
+ #define R_AGTX4          ((R_AGTX0_Type *) R_AGTX4_BASE)
+ #define R_AGTX5          ((R_AGTX0_Type *) R_AGTX5_BASE)
+ #define R_AGTX6          ((R_AGTX0_Type *) R_AGTX6_BASE)
+ #define R_AGTX7          ((R_AGTX0_Type *) R_AGTX7_BASE)
+ #define R_AGTX8          ((R_AGTX0_Type *) R_AGTX8_BASE)
+ #define R_AGTX9          ((R_AGTX0_Type *) R_AGTX9_BASE)
  #define R_FLAD           ((R_FLAD_Type *) R_FLAD_BASE)
 
 /** @} */ /* End of group Device_Peripheral_declaration */
@@ -14030,6 +14520,8 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* =========================================================================================================================== */
 
 /* =========================================================  RTCCR  ========================================================= */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
@@ -14177,6 +14669,101 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
 
+/* =========================================================================================================================== */
+/* ================                                           CTRL                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  AGTCR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AGTMR1  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
+/* ========================================================  AGTMR2  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
+/* =====================================================  AGTIOSEL_ALT  ====================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+/* ========================================================  AGTIOC  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AGTISR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AGTCMSR  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
+/* =======================================================  AGTIOSEL  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT16                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT32                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
+
 /** @} */ /* End of group PosMask_clusters */
 
 /* =========================================================================================================================== */
@@ -14842,77 +15429,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_PSCU_DLMMON_DLMMON_Pos    (0UL)          /*!< DLMMON (Bit 0)                                        */
  #define R_PSCU_DLMMON_DLMMON_Msk    (0xfUL)        /*!< DLMMON (Bitfield-Mask: 0x0f)                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/* ==========================================================  AGT  ========================================================== */
- #define R_AGT0_AGT_AGT_Pos           (0UL)      /*!< AGT (Bit 0)                                           */
- #define R_AGT0_AGT_AGT_Msk           (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
-/* ========================================================  AGTCMA  ========================================================= */
- #define R_AGT0_AGTCMA_AGTCMA_Pos     (0UL)      /*!< AGTCMA (Bit 0)                                        */
- #define R_AGT0_AGTCMA_AGTCMA_Msk     (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
-/* ========================================================  AGTCMB  ========================================================= */
- #define R_AGT0_AGTCMB_AGTCMB_Pos     (0UL)      /*!< AGTCMB (Bit 0)                                        */
- #define R_AGT0_AGTCMB_AGTCMB_Msk     (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
-/* =========================================================  AGTCR  ========================================================= */
- #define R_AGT0_AGTCR_TCMBF_Pos       (7UL)      /*!< TCMBF (Bit 7)                                         */
- #define R_AGT0_AGTCR_TCMBF_Msk       (0x80UL)   /*!< TCMBF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCMAF_Pos       (6UL)      /*!< TCMAF (Bit 6)                                         */
- #define R_AGT0_AGTCR_TCMAF_Msk       (0x40UL)   /*!< TCMAF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TUNDF_Pos       (5UL)      /*!< TUNDF (Bit 5)                                         */
- #define R_AGT0_AGTCR_TUNDF_Msk       (0x20UL)   /*!< TUNDF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TEDGF_Pos       (4UL)      /*!< TEDGF (Bit 4)                                         */
- #define R_AGT0_AGTCR_TEDGF_Msk       (0x10UL)   /*!< TEDGF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTOP_Pos       (2UL)      /*!< TSTOP (Bit 2)                                         */
- #define R_AGT0_AGTCR_TSTOP_Msk       (0x4UL)    /*!< TSTOP (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCSTF_Pos       (1UL)      /*!< TCSTF (Bit 1)                                         */
- #define R_AGT0_AGTCR_TCSTF_Msk       (0x2UL)    /*!< TCSTF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTART_Pos      (0UL)      /*!< TSTART (Bit 0)                                        */
- #define R_AGT0_AGTCR_TSTART_Msk      (0x1UL)    /*!< TSTART (Bitfield-Mask: 0x01)                          */
-/* ========================================================  AGTMR1  ========================================================= */
- #define R_AGT0_AGTMR1_TCK_Pos        (4UL)      /*!< TCK (Bit 4)                                           */
- #define R_AGT0_AGTMR1_TCK_Msk        (0x70UL)   /*!< TCK (Bitfield-Mask: 0x07)                             */
- #define R_AGT0_AGTMR1_TEDGPL_Pos     (3UL)      /*!< TEDGPL (Bit 3)                                        */
- #define R_AGT0_AGTMR1_TEDGPL_Msk     (0x8UL)    /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTMR1_TMOD_Pos       (0UL)      /*!< TMOD (Bit 0)                                          */
- #define R_AGT0_AGTMR1_TMOD_Msk       (0x7UL)    /*!< TMOD (Bitfield-Mask: 0x07)                            */
-/* ========================================================  AGTMR2  ========================================================= */
- #define R_AGT0_AGTMR2_LPM_Pos        (7UL)      /*!< LPM (Bit 7)                                           */
- #define R_AGT0_AGTMR2_LPM_Msk        (0x80UL)   /*!< LPM (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTMR2_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
- #define R_AGT0_AGTMR2_CKS_Msk        (0x7UL)    /*!< CKS (Bitfield-Mask: 0x07)                             */
-/* ========================================================  AGTIOC  ========================================================= */
- #define R_AGT0_AGTIOC_TIOGT_Pos      (6UL)      /*!< TIOGT (Bit 6)                                         */
- #define R_AGT0_AGTIOC_TIOGT_Msk      (0xc0UL)   /*!< TIOGT (Bitfield-Mask: 0x03)                           */
- #define R_AGT0_AGTIOC_TIPF_Pos       (4UL)      /*!< TIPF (Bit 4)                                          */
- #define R_AGT0_AGTIOC_TIPF_Msk       (0x30UL)   /*!< TIPF (Bitfield-Mask: 0x03)                            */
- #define R_AGT0_AGTIOC_TOE_Pos        (2UL)      /*!< TOE (Bit 2)                                           */
- #define R_AGT0_AGTIOC_TOE_Msk        (0x4UL)    /*!< TOE (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTIOC_TEDGSEL_Pos    (0UL)      /*!< TEDGSEL (Bit 0)                                       */
- #define R_AGT0_AGTIOC_TEDGSEL_Msk    (0x1UL)    /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
-/* ========================================================  AGTISR  ========================================================= */
- #define R_AGT0_AGTISR_EEPS_Pos       (2UL)      /*!< EEPS (Bit 2)                                          */
- #define R_AGT0_AGTISR_EEPS_Msk       (0x4UL)    /*!< EEPS (Bitfield-Mask: 0x01)                            */
-/* ========================================================  AGTCMSR  ======================================================== */
- #define R_AGT0_AGTCMSR_TOPOLB_Pos    (6UL)      /*!< TOPOLB (Bit 6)                                        */
- #define R_AGT0_AGTCMSR_TOPOLB_Msk    (0x40UL)   /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEB_Pos      (5UL)      /*!< TOEB (Bit 5)                                          */
- #define R_AGT0_AGTCMSR_TOEB_Msk      (0x20UL)   /*!< TOEB (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEB_Pos     (4UL)      /*!< TCMEB (Bit 4)                                         */
- #define R_AGT0_AGTCMSR_TCMEB_Msk     (0x10UL)   /*!< TCMEB (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCMSR_TOPOLA_Pos    (2UL)      /*!< TOPOLA (Bit 2)                                        */
- #define R_AGT0_AGTCMSR_TOPOLA_Msk    (0x4UL)    /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEA_Pos      (1UL)      /*!< TOEA (Bit 1)                                          */
- #define R_AGT0_AGTCMSR_TOEA_Msk      (0x2UL)    /*!< TOEA (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEA_Pos     (0UL)      /*!< TCMEA (Bit 0)                                         */
- #define R_AGT0_AGTCMSR_TCMEA_Msk     (0x1UL)    /*!< TCMEA (Bitfield-Mask: 0x01)                           */
-/* =======================================================  AGTIOSEL  ======================================================== */
- #define R_AGT0_AGTIOSEL_TIES_Pos     (4UL)      /*!< TIES (Bit 4)                                          */
- #define R_AGT0_AGTIOSEL_TIES_Msk     (0x10UL)   /*!< TIES (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTIOSEL_SEL_Pos      (0UL)      /*!< SEL (Bit 0)                                           */
- #define R_AGT0_AGTIOSEL_SEL_Msk      (0x3UL)    /*!< SEL (Bitfield-Mask: 0x03)                             */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -16140,10 +16656,22 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
 /* =========================================================  GTCR  ========================================================== */
+ #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
+ #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTCR_TPCS_Pos              (23UL)         /*!< TPCS (Bit 23)                                         */
  #define R_GPT0_GTCR_TPCS_Msk              (0x7800000UL)  /*!< TPCS (Bitfield-Mask: 0x0f)                            */
  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
- #define R_GPT0_GTCR_MD_Msk                (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
+ #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
+ #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
+ #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
+ #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
 /* =======================================================  GTUDDTYC  ======================================================== */
@@ -16201,6 +16729,8 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
 /* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
+ #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
@@ -16209,8 +16739,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
- #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
- #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
+ #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
+ #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
+ #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
 /* =========================================================  GTST  ========================================================== */
  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
@@ -16267,6 +16805,8 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
+ #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
@@ -16356,6 +16896,67 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* ========================================================  GTSOTR  ========================================================= */
  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
 /* ========================================================  GTICLF  ========================================================= */
  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
@@ -16398,14 +16999,113 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
+ #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
+ #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTBER2  ========================================================= */
+ #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
+ #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
+ #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
+ #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
+ #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
+ #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
+ #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
+ #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
+ #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
+ #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
+ #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
+ #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
+ #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
+ #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
+ #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
+ #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
+ #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
+ #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
+ #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
+ #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTOLBR  ========================================================= */
+ #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
+ #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
+ #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
+ #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  GTICCR  ========================================================= */
+ #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
+ #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
+ #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
+ #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
+ #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
+ #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
+ #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
+ #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
+ #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
+ #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
+ #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
+ #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
+ #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
+ #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
+ #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
+ #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
+ #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
+ #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
+ #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
+ #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
+ #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_OPS                                         ================ */
@@ -19092,6 +19792,9 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* ======================================================  CECCKDIVCR  ======================================================= */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  I3CCKDIVCR  ======================================================= */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
 /* ======================================================  IICCKDIVCR  ======================================================= */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
@@ -20069,6 +20772,10 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_CPSCU_TEVTRCR_TEVTE_Pos           (0UL)          /*!< TEVTE (Bit 0)                                         */
  #define R_CPSCU_TEVTRCR_TEVTE_Msk           (0x1UL)        /*!< TEVTE (Bitfield-Mask: 0x01)                           */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
 /* =========================================================================================================================== */
 /* ================                                          R_FLAD                                           ================ */
 /* =========================================================================================================================== */
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h
index 25d88e96a..e1337eacb 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h
@@ -830,7 +830,8 @@ typedef struct
             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
             uint8_t            : 1;
             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
-            uint8_t            : 2;
+            uint8_t            : 1;
+            __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
         } RTCCR_b;
     };
     __IM uint8_t RESERVED;
@@ -1002,6 +1003,213 @@ typedef struct
     };
 } R_USB_FS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
 
+/**
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
+            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
+            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
+            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
+            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
+            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
+        } AGTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
+            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
+            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
+            uint8_t              : 1;
+        } AGTMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+                                        *   ratio                                                                     */
+            uint8_t           : 4;
+            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
+        } AGTMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+                                        *   mode.                                                                     */
+            uint8_t             : 1;
+            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
+            uint8_t             : 1;
+            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
+            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
+        } AGTIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
+            uint8_t            : 5;
+        } AGTISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
+
+        struct
+        {
+            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
+            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
+            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
+            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
+            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
+            uint8_t              : 1;
+        } AGTCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_b;
+    };
+} R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
+
+        struct
+        {
+            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IM uint16_t                 RESERVED;
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
+} R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
+
+        struct
+        {
+            __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
+} R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_clusters */
 
 /* =========================================================================================================================== */
@@ -1380,16 +1588,17 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
 
     union
     {
-        __IM uint16_t ADDR[28];        /*!< (@ 0x00000020) A/D Data Register                                          */
+        __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
 
         struct
         {
             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
                                         *   storing the result of A/D conversion.                                     */
-        } ADDR_b[28];
+        } ADDR_b[29];
     };
-    __IM uint32_t RESERVED1[2];
-    __IM uint16_t RESERVED2;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+    __IM uint16_t RESERVED3;
 
     union
     {
@@ -1582,7 +1791,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint16_t                : 3;
         } ADSWTSTR2_b;
     };
-    __IM uint16_t RESERVED3;
+    __IM uint16_t RESERVED4;
 
     union
     {
@@ -1644,7 +1853,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 6;
         } ADACSR_b;
     };
-    __IM uint8_t RESERVED4;
+    __IM uint8_t RESERVED5;
 
     union
     {
@@ -1714,7 +1923,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
         } ADSER_b;
     };
-    __IM uint8_t RESERVED5;
+    __IM uint8_t RESERVED6;
 
     union
     {
@@ -1730,7 +1939,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
         } ADHVREFCNT_b;
     };
-    __IM uint8_t RESERVED6;
+    __IM uint8_t RESERVED7;
 
     union
     {
@@ -1748,8 +1957,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t              : 2;
         } ADWINMON_b;
     };
-    __IM uint8_t  RESERVED7;
-    __IM uint16_t RESERVED8;
+    __IM uint8_t  RESERVED8;
+    __IM uint16_t RESERVED9;
 
     union
     {
@@ -1925,7 +2134,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 6;
         } ADCMPSER_b;
     };
-    __IM uint8_t RESERVED9;
+    __IM uint8_t RESERVED10;
 
     union
     {
@@ -1940,7 +2149,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
         } ADCMPBNSR_b;
     };
-    __IM uint8_t RESERVED10;
+    __IM uint8_t RESERVED11;
 
     union
     {
@@ -1979,8 +2188,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 7;
         } ADCMPBSR_b;
     };
-    __IM uint8_t  RESERVED11;
-    __IM uint16_t RESERVED12;
+    __IM uint8_t  RESERVED12;
+    __IM uint16_t RESERVED13;
 
     union
     {
@@ -2184,7 +2393,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 7;
         } ADBUFEN_b;
     };
-    __IM uint8_t RESERVED13;
+    __IM uint8_t RESERVED14;
 
     union
     {
@@ -2198,9 +2407,9 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 3;
         } ADBUFPTR_b;
     };
-    __IM uint8_t  RESERVED14;
-    __IM uint32_t RESERVED15[2];
-    __IM uint8_t  RESERVED16;
+    __IM uint8_t  RESERVED15;
+    __IM uint32_t RESERVED16[2];
+    __IM uint8_t  RESERVED17;
 
     union
     {
@@ -2267,7 +2476,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
         } ADCALEXE_b;
     };
-    __IM uint8_t RESERVED17;
+    __IM uint8_t RESERVED18;
 
     union
     {
@@ -2284,8 +2493,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
         } VREFAMPCNT_b;
     };
-    __IM uint8_t  RESERVED18;
-    __IM uint16_t RESERVED19;
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -2307,8 +2516,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 6;
         } ADRST_b;
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint32_t RESERVED21[41];
+    __IM uint8_t  RESERVED21;
+    __IM uint32_t RESERVED22[41];
 
     union
     {
@@ -2366,7 +2575,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
         } ADPGAGS0_b;
     };
-    __IM uint32_t RESERVED22[3];
+    __IM uint32_t RESERVED23[3];
 
     union
     {
@@ -2393,7 +2602,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
         } ADPGADCR0_b;
     };
-    __IM uint16_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -2422,8 +2631,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 7;
         } ADPGADBS1_b;
     };
-    __IM uint16_t RESERVED24;
-    __IM uint32_t RESERVED25[10];
+    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED26[10];
 
     union
     {
@@ -2439,156 +2648,6 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
     };
 } R_ADC0_Type;                         /*!< Size = 484 (0x1e4)                                                        */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Asynchronous General Purpose Timer (R_AGT0)
- */
-
-typedef struct                         /*!< (@ 0x40084000) R_AGT0 Structure                                           */
-{
-    union
-    {
-        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
-
-        struct
-        {
-            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written
-                                        *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
-                                        *   is forcibly stopped and set to FFFFH.                                     */
-        } AGT_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCRn register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMA_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCR register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMB_b;
-    };
-    __IM uint16_t RESERVED;
-
-    union
-    {
-        __IOM uint8_t AGTCR;           /*!< (@ 0x00000008) AGT Control Register                                       */
-
-        struct
-        {
-            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
-            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
-            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
-            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
-            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
-            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
-        } AGTCR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000009) AGT Mode Register 1                                        */
-
-        struct
-        {
-            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
-            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
-            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
-            uint8_t              : 1;
-        } AGTMR1_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000A) AGT Mode Register 2                                        */
-
-        struct
-        {
-            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
-                                        *   ratio                                                                     */
-            uint8_t           : 4;
-            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
-        } AGTMR2_b;
-    };
-    __IM uint8_t RESERVED1;
-
-    union
-    {
-        __IOM uint8_t AGTIOC;          /*!< (@ 0x0000000C) AGT I/O Control Register                                   */
-
-        struct
-        {
-            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
-                                        *   mode.                                                                     */
-            uint8_t             : 1;
-            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
-            uint8_t             : 1;
-            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
-            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
-        } AGTIOC_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTISR;          /*!< (@ 0x0000000D) AGT Event Pin Select Register                              */
-
-        struct
-        {
-            uint8_t            : 2;
-            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
-            uint8_t            : 5;
-        } AGTISR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTCMSR;         /*!< (@ 0x0000000E) AGT Compare Match Function Select Register                 */
-
-        struct
-        {
-            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
-            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
-            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
-            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
-            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
-            uint8_t              : 1;
-        } AGTCMSR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x0000000F) AGT Pin Select Register                                    */
-
-        struct
-        {
-            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
-            uint8_t            : 2;
-            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
-            uint8_t            : 3;
-        } AGTIOSEL_b;
-    };
-} R_AGT0_Type;                         /*!< Size = 16 (0x10)                                                          */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -4861,46 +4920,99 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            uint32_t : 18;
         } GTSTR_b;
     };
 
@@ -4952,7 +5064,60 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
                                          *   1 means counter stop.                                                     */
-            uint32_t : 18;
+            __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
         } GTSTP_b;
     };
 
@@ -4976,7 +5141,24 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
-            uint32_t             : 18;
+            __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
         } GTCLR_b;
     };
 
@@ -5297,16 +5479,23 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+        __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
 
         struct
         {
-            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
-            uint32_t            : 15;
-            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
-            uint32_t            : 5;
-            __IOM uint32_t TPCS : 3;   /*!< [26..24] Timer Prescaler Select                                           */
-            uint32_t            : 5;
+            __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
+            uint32_t               : 7;
+            __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
+            __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
+            __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
+            __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
+            uint32_t               : 2;
+            __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
+            __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
+            uint32_t               : 4;
+            __IOM uint32_t TPCS    : 3; /*!< [26..24] Timer Prescaler Select                                           */
+            __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
+            uint32_t               : 3;
         } GTCR_b;
     };
 
@@ -5377,13 +5566,36 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
         struct
         {
-            uint32_t               : 24;
-            __IOM uint32_t GRP     : 2; /*!< [25..24] Output Disable Source Select                                     */
+            uint32_t            : 8;
+            __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
+            __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            uint32_t               : 4;
+            __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
             uint32_t               : 2;
-            __IOM uint32_t GRPDTE  : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
-            __IOM uint32_t GRPABH  : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable               */
-            __IOM uint32_t GRPABL  : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
-            __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
+            __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
+            __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
         } GTINTAD_b;
     };
 
@@ -5426,32 +5638,36 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTBER;          /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
 
         struct
         {
-            __IOM uint32_t BD0    : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
-            __IOM uint32_t BD1    : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
-            __IOM uint32_t BD2    : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
-            __IOM uint32_t BD3    : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
-            uint32_t              : 12;
-            __IOM uint32_t CCRA   : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
-            __IOM uint32_t CCRB   : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
-            __IOM uint32_t PR     : 2; /*!< [21..20] GTPR Buffer Operation                                            */
-            __OM uint32_t  CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
-                                        *   is read as 0.                                                             */
+            __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
+            __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+                                         *   is read as 0.                                                             */
             uint32_t             : 1;
-            __IOM uint32_t ADTTA : 2;  /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDA : 1;  /*!< [26..26] GTADTRA Double Buffer Operation                                  */
+            __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
             uint32_t             : 1;
-            __IOM uint32_t ADTTB : 2;  /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDB : 1;  /*!< [30..30] GTADTRB Double Buffer Operation                                  */
+            __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
             uint32_t             : 1;
         } GTBER_b;
     };
@@ -5675,7 +5891,126 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             uint32_t            : 31;
         } GTSOTR_b;
     };
-    __IM uint32_t RESERVED[5];
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
 
     union
     {
@@ -5709,7 +6044,7 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             uint32_t            : 4;
         } GTPC_b;
     };
-    __IM uint32_t RESERVED1[4];
+    __IM uint32_t RESERVED[4];
 
     union
     {
@@ -5751,17 +6086,137 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
         {
             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 4;
             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
-            uint32_t             : 7;
+            __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
+            uint32_t             : 6;
             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
-            uint32_t             : 7;
+            __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
+            uint32_t             : 6;
         } GTSECR_b;
     };
-} R_GPT0_Type;                         /*!< Size = 216 (0xd8)                                                         */
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
+            __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
+                                        *   Disable                                                                   */
+            uint32_t             : 2;
+            __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t             : 1;
+            __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
+                                        *   Transfer Disable                                                          */
+            uint32_t             : 2;
+            __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
+            __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
+            __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
+            __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
+            uint32_t             : 2;
+        } GTBER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
+
+        struct
+        {
+            __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
+            uint32_t              : 11;
+            __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
+            uint32_t              : 11;
+        } GTOLBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
+                                        *                  Capture Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
+            __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
+                                        *   Other Channel GTCCRb Input Capture Source Enable                          */
+            __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
+        } GTICCR_b;
+    };
+} R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_OPS                                         ================ */
@@ -9419,8 +9874,18 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } IICCKDIVCR_b;
         };
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint16_t RESERVED21;
+
+    union
+    {
+        __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
+
+        struct
+        {
+            __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
+            uint8_t                : 5;
+        } I3CCKDIVCR_b;
+    };
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -9547,8 +10012,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
         } I3CCKCR_b;
     };
-    __IM uint16_t RESERVED22;
-    __IM uint32_t RESERVED23[3];
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
 
     union
     {
@@ -9562,8 +10027,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                 : 29;
         } SNZREQCR1_b;
     };
-    __IM uint32_t RESERVED24;
-    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -9578,7 +10043,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
         } SNZCR_b;
     };
-    __IM uint8_t RESERVED26;
+    __IM uint8_t RESERVED25;
 
     union
     {
@@ -9608,7 +10073,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } SNZEDCR1_b;
     };
-    __IM uint16_t RESERVED27;
+    __IM uint16_t RESERVED26;
 
     union
     {
@@ -9651,7 +10116,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 1;
         } SNZREQCR_b;
     };
-    __IM uint16_t RESERVED28;
+    __IM uint16_t RESERVED27;
 
     union
     {
@@ -9689,7 +10154,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 3;
         } OPCCR_b;
     };
-    __IM uint8_t RESERVED29;
+    __IM uint8_t RESERVED28;
 
     union
     {
@@ -9701,7 +10166,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } MOSCWTCR_b;
     };
-    __IM uint8_t RESERVED30[2];
+    __IM uint8_t RESERVED29[2];
 
     union
     {
@@ -9714,7 +10179,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t : 5;
         } HOCOWTCR_b;
     };
-    __IM uint16_t RESERVED31[2];
+    __IM uint16_t RESERVED30[2];
 
     union
     {
@@ -9728,8 +10193,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 3;
         } SOPCCR_b;
     };
-    __IM uint8_t  RESERVED32;
-    __IM uint32_t RESERVED33[5];
+    __IM uint8_t  RESERVED31;
+    __IM uint32_t RESERVED32[5];
 
     union
     {
@@ -9763,8 +10228,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
         } RSTSR1_b;
     };
-    __IM uint16_t RESERVED34;
-    __IM uint32_t RESERVED35[3];
+    __IM uint16_t RESERVED33;
+    __IM uint32_t RESERVED34[3];
 
     union
     {
@@ -9790,8 +10255,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
         } SDADCCKCR_b;
     };
-    __IM uint16_t RESERVED36;
-    __IM uint32_t RESERVED37[3];
+    __IM uint16_t RESERVED35;
+    __IM uint32_t RESERVED36[3];
 
     union
     {
@@ -9846,7 +10311,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t          : 6;
         } LVD2SR_b;
     };
-    __IM uint32_t RESERVED38[183];
+    __IM uint32_t RESERVED37[183];
 
     union
     {
@@ -9874,7 +10339,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 14;
         } CGFSAR_b;
     };
-    __IM uint32_t RESERVED39;
+    __IM uint32_t RESERVED38;
 
     union
     {
@@ -9943,7 +10408,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 8;
         } BBFSAR_b;
     };
-    __IM uint32_t RESERVED40[3];
+    __IM uint32_t RESERVED39[3];
 
     union
     {
@@ -10005,8 +10470,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 4;
         } DPFSAR_b;
     };
-    __IM uint32_t RESERVED41[6];
-    __IM uint16_t RESERVED42;
+    __IM uint32_t RESERVED40[6];
+    __IM uint16_t RESERVED41;
 
     union
     {
@@ -10224,7 +10689,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 3;
         } DPSIEGR2_b;
     };
-    __IM uint8_t RESERVED43;
+    __IM uint8_t RESERVED42;
 
     union
     {
@@ -10282,7 +10747,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } RSTSR2_b;
     };
-    __IM uint8_t RESERVED44;
+    __IM uint8_t RESERVED43;
 
     union
     {
@@ -10299,7 +10764,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                           *   Enable                                                                    */
         } MOMCR_b;
     };
-    __IM uint16_t RESERVED45;
+    __IM uint16_t RESERVED44;
 
     union
     {
@@ -10369,7 +10834,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } LVD2CMPCR_b;
         };
     };
-    __IM uint8_t RESERVED46;
+    __IM uint8_t RESERVED45;
 
     union
     {
@@ -10402,7 +10867,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
         } LVD2CR0_b;
     };
-    __IM uint8_t RESERVED47;
+    __IM uint8_t RESERVED46;
 
     union
     {
@@ -10437,7 +10902,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 7;
         } VBTCR1_b;
     };
-    __IM uint32_t RESERVED48[8];
+    __IM uint32_t RESERVED47[8];
 
     union
     {
@@ -10480,7 +10945,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 6;
         } VCCSEL_b;
     };
-    __IM uint16_t RESERVED49;
+    __IM uint16_t RESERVED48;
 
     union
     {
@@ -10492,9 +10957,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } PL2LDOSCR_b;
     };
-    __IM uint8_t  RESERVED50;
-    __IM uint16_t RESERVED51;
-    __IM uint32_t RESERVED52[14];
+    __IM uint8_t  RESERVED49;
+    __IM uint16_t RESERVED50;
+    __IM uint32_t RESERVED51[14];
 
     union
     {
@@ -10517,8 +10982,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 6;
         } SOMCR_b;
     };
-    __IM uint16_t RESERVED53;
-    __IM uint32_t RESERVED54[3];
+    __IM uint16_t RESERVED52;
+    __IM uint32_t RESERVED53[3];
 
     union
     {
@@ -10530,7 +10995,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 7;
         } LOCOCR_b;
     };
-    __IM uint8_t RESERVED55;
+    __IM uint8_t RESERVED54;
 
     union
     {
@@ -10545,8 +11010,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                          *   trimming bits                                                             */
         } LOCOUTCR_b;
     };
-    __IM uint8_t  RESERVED56;
-    __IM uint32_t RESERVED57[7];
+    __IM uint8_t  RESERVED55;
+    __IM uint32_t RESERVED56[7];
 
     union
     {
@@ -10585,7 +11050,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 7;
         } VBTCMPCR_b;
     };
-    __IM uint8_t RESERVED58;
+    __IM uint8_t RESERVED57;
 
     union
     {
@@ -10599,7 +11064,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                  : 6;
         } VBTLVDICR_b;
     };
-    __IM uint8_t RESERVED59;
+    __IM uint8_t RESERVED58;
 
     union
     {
@@ -10611,7 +11076,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } VBTWCTLR_b;
     };
-    __IM uint8_t RESERVED60;
+    __IM uint8_t RESERVED59;
 
     union
     {
@@ -10746,9 +11211,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } VBTBER_b;
     };
-    __IM uint8_t  RESERVED61;
-    __IM uint16_t RESERVED62;
-    __IM uint32_t RESERVED63[15];
+    __IM uint8_t  RESERVED60;
+    __IM uint16_t RESERVED61;
+    __IM uint32_t RESERVED62[15];
 
     union
     {
@@ -11945,6 +12410,23 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
     __IM uint16_t RESERVED3;
 } R_WDT_Type;                          /*!< Size = 12 (0xc)                                                           */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
+ */
+
+typedef struct                          /*!< (@ 0x40084000) R_AGTX0 Structure                                          */
+{
+    union
+    {
+        __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
+        __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
+    };
+} R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_peripherals */
 
 /* =========================================================================================================================== */
@@ -11958,12 +12440,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_ACMPLP_BASE       0x40085E00UL
  #define R_ADC0_BASE         0x4005C000UL
  #define R_ADC1_BASE         0x4005C200UL
- #define R_AGT0_BASE         0x40084000UL
- #define R_AGT1_BASE         0x40084100UL
- #define R_AGT2_BASE         0x40084200UL
- #define R_AGT3_BASE         0x40084300UL
- #define R_AGT4_BASE         0x40084400UL
- #define R_AGT5_BASE         0x40084500UL
  #define R_BUS_BASE          0x40003000UL
  #define R_CAC_BASE          0x40044600UL
  #define R_CAN0_BASE         0x40050000UL
@@ -12052,6 +12528,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_TSN_BASE          0x407EC000UL
  #define R_USB_FS0_BASE      0x40090000UL
  #define R_WDT_BASE          0x40044200UL
+ #define R_AGTX0_BASE        0x40084000UL
+ #define R_AGTX1_BASE        0x40084100UL
+ #define R_AGTX2_BASE        0x40084200UL
+ #define R_AGTX3_BASE        0x40084300UL
+ #define R_AGTX4_BASE        0x40084400UL
+ #define R_AGTX5_BASE        0x40084500UL
+ #define R_AGTX6_BASE        0x40084600UL
+ #define R_AGTX7_BASE        0x40084700UL
+ #define R_AGTX8_BASE        0x40084800UL
+ #define R_AGTX9_BASE        0x40084900UL
 
 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
 
@@ -12066,12 +12552,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_ACMPLP       ((R_ACMPLP_Type *) R_ACMPLP_BASE)
  #define R_ADC0         ((R_ADC0_Type *) R_ADC0_BASE)
  #define R_ADC1         ((R_ADC0_Type *) R_ADC1_BASE)
- #define R_AGT0         ((R_AGT0_Type *) R_AGT0_BASE)
- #define R_AGT1         ((R_AGT0_Type *) R_AGT1_BASE)
- #define R_AGT2         ((R_AGT0_Type *) R_AGT2_BASE)
- #define R_AGT3         ((R_AGT0_Type *) R_AGT3_BASE)
- #define R_AGT4         ((R_AGT0_Type *) R_AGT4_BASE)
- #define R_AGT5         ((R_AGT0_Type *) R_AGT5_BASE)
  #define R_BUS          ((R_BUS_Type *) R_BUS_BASE)
  #define R_CAC          ((R_CAC_Type *) R_CAC_BASE)
  #define R_CAN0         ((R_CAN0_Type *) R_CAN0_BASE)
@@ -12160,6 +12640,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_TSN          ((R_TSN_Type *) R_TSN_BASE)
  #define R_USB_FS0      ((R_USB_FS0_Type *) R_USB_FS0_BASE)
  #define R_WDT          ((R_WDT_Type *) R_WDT_BASE)
+ #define R_AGTX0        ((R_AGTX0_Type *) R_AGTX0_BASE)
+ #define R_AGTX1        ((R_AGTX0_Type *) R_AGTX1_BASE)
+ #define R_AGTX2        ((R_AGTX0_Type *) R_AGTX2_BASE)
+ #define R_AGTX3        ((R_AGTX0_Type *) R_AGTX3_BASE)
+ #define R_AGTX4        ((R_AGTX0_Type *) R_AGTX4_BASE)
+ #define R_AGTX5        ((R_AGTX0_Type *) R_AGTX5_BASE)
+ #define R_AGTX6        ((R_AGTX0_Type *) R_AGTX6_BASE)
+ #define R_AGTX7        ((R_AGTX0_Type *) R_AGTX7_BASE)
+ #define R_AGTX8        ((R_AGTX0_Type *) R_AGTX8_BASE)
+ #define R_AGTX9        ((R_AGTX0_Type *) R_AGTX9_BASE)
 
 /** @} */ /* End of group Device_Peripheral_declaration */
 
@@ -12535,6 +13025,8 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 /* =========================================================================================================================== */
 
 /* =========================================================  RTCCR  ========================================================= */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
@@ -12599,6 +13091,101 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
 
+/* =========================================================================================================================== */
+/* ================                                           CTRL                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  AGTCR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AGTMR1  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
+/* ========================================================  AGTMR2  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
+/* =====================================================  AGTIOSEL_ALT  ====================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+/* ========================================================  AGTIOC  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AGTISR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AGTCMSR  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
+/* =======================================================  AGTIOSEL  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT16                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT32                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
+
 /** @} */ /* End of group PosMask_clusters */
 
 /* =========================================================================================================================== */
@@ -13158,77 +13745,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_ADC0_ADREFMON_MONSEL_Pos         (16UL)      /*!< MONSEL (Bit 16)                                       */
  #define R_ADC0_ADREFMON_MONSEL_Msk         (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f)                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/* ==========================================================  AGT  ========================================================== */
- #define R_AGT0_AGT_AGT_Pos           (0UL)      /*!< AGT (Bit 0)                                           */
- #define R_AGT0_AGT_AGT_Msk           (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
-/* ========================================================  AGTCMA  ========================================================= */
- #define R_AGT0_AGTCMA_AGTCMA_Pos     (0UL)      /*!< AGTCMA (Bit 0)                                        */
- #define R_AGT0_AGTCMA_AGTCMA_Msk     (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
-/* ========================================================  AGTCMB  ========================================================= */
- #define R_AGT0_AGTCMB_AGTCMB_Pos     (0UL)      /*!< AGTCMB (Bit 0)                                        */
- #define R_AGT0_AGTCMB_AGTCMB_Msk     (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
-/* =========================================================  AGTCR  ========================================================= */
- #define R_AGT0_AGTCR_TCMBF_Pos       (7UL)      /*!< TCMBF (Bit 7)                                         */
- #define R_AGT0_AGTCR_TCMBF_Msk       (0x80UL)   /*!< TCMBF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCMAF_Pos       (6UL)      /*!< TCMAF (Bit 6)                                         */
- #define R_AGT0_AGTCR_TCMAF_Msk       (0x40UL)   /*!< TCMAF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TUNDF_Pos       (5UL)      /*!< TUNDF (Bit 5)                                         */
- #define R_AGT0_AGTCR_TUNDF_Msk       (0x20UL)   /*!< TUNDF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TEDGF_Pos       (4UL)      /*!< TEDGF (Bit 4)                                         */
- #define R_AGT0_AGTCR_TEDGF_Msk       (0x10UL)   /*!< TEDGF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTOP_Pos       (2UL)      /*!< TSTOP (Bit 2)                                         */
- #define R_AGT0_AGTCR_TSTOP_Msk       (0x4UL)    /*!< TSTOP (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCSTF_Pos       (1UL)      /*!< TCSTF (Bit 1)                                         */
- #define R_AGT0_AGTCR_TCSTF_Msk       (0x2UL)    /*!< TCSTF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTART_Pos      (0UL)      /*!< TSTART (Bit 0)                                        */
- #define R_AGT0_AGTCR_TSTART_Msk      (0x1UL)    /*!< TSTART (Bitfield-Mask: 0x01)                          */
-/* ========================================================  AGTMR1  ========================================================= */
- #define R_AGT0_AGTMR1_TCK_Pos        (4UL)      /*!< TCK (Bit 4)                                           */
- #define R_AGT0_AGTMR1_TCK_Msk        (0x70UL)   /*!< TCK (Bitfield-Mask: 0x07)                             */
- #define R_AGT0_AGTMR1_TEDGPL_Pos     (3UL)      /*!< TEDGPL (Bit 3)                                        */
- #define R_AGT0_AGTMR1_TEDGPL_Msk     (0x8UL)    /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTMR1_TMOD_Pos       (0UL)      /*!< TMOD (Bit 0)                                          */
- #define R_AGT0_AGTMR1_TMOD_Msk       (0x7UL)    /*!< TMOD (Bitfield-Mask: 0x07)                            */
-/* ========================================================  AGTMR2  ========================================================= */
- #define R_AGT0_AGTMR2_LPM_Pos        (7UL)      /*!< LPM (Bit 7)                                           */
- #define R_AGT0_AGTMR2_LPM_Msk        (0x80UL)   /*!< LPM (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTMR2_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
- #define R_AGT0_AGTMR2_CKS_Msk        (0x7UL)    /*!< CKS (Bitfield-Mask: 0x07)                             */
-/* ========================================================  AGTIOC  ========================================================= */
- #define R_AGT0_AGTIOC_TIOGT_Pos      (6UL)      /*!< TIOGT (Bit 6)                                         */
- #define R_AGT0_AGTIOC_TIOGT_Msk      (0xc0UL)   /*!< TIOGT (Bitfield-Mask: 0x03)                           */
- #define R_AGT0_AGTIOC_TIPF_Pos       (4UL)      /*!< TIPF (Bit 4)                                          */
- #define R_AGT0_AGTIOC_TIPF_Msk       (0x30UL)   /*!< TIPF (Bitfield-Mask: 0x03)                            */
- #define R_AGT0_AGTIOC_TOE_Pos        (2UL)      /*!< TOE (Bit 2)                                           */
- #define R_AGT0_AGTIOC_TOE_Msk        (0x4UL)    /*!< TOE (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTIOC_TEDGSEL_Pos    (0UL)      /*!< TEDGSEL (Bit 0)                                       */
- #define R_AGT0_AGTIOC_TEDGSEL_Msk    (0x1UL)    /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
-/* ========================================================  AGTISR  ========================================================= */
- #define R_AGT0_AGTISR_EEPS_Pos       (2UL)      /*!< EEPS (Bit 2)                                          */
- #define R_AGT0_AGTISR_EEPS_Msk       (0x4UL)    /*!< EEPS (Bitfield-Mask: 0x01)                            */
-/* ========================================================  AGTCMSR  ======================================================== */
- #define R_AGT0_AGTCMSR_TOPOLB_Pos    (6UL)      /*!< TOPOLB (Bit 6)                                        */
- #define R_AGT0_AGTCMSR_TOPOLB_Msk    (0x40UL)   /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEB_Pos      (5UL)      /*!< TOEB (Bit 5)                                          */
- #define R_AGT0_AGTCMSR_TOEB_Msk      (0x20UL)   /*!< TOEB (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEB_Pos     (4UL)      /*!< TCMEB (Bit 4)                                         */
- #define R_AGT0_AGTCMSR_TCMEB_Msk     (0x10UL)   /*!< TCMEB (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCMSR_TOPOLA_Pos    (2UL)      /*!< TOPOLA (Bit 2)                                        */
- #define R_AGT0_AGTCMSR_TOPOLA_Msk    (0x4UL)    /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEA_Pos      (1UL)      /*!< TOEA (Bit 1)                                          */
- #define R_AGT0_AGTCMSR_TOEA_Msk      (0x2UL)    /*!< TOEA (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEA_Pos     (0UL)      /*!< TCMEA (Bit 0)                                         */
- #define R_AGT0_AGTCMSR_TCMEA_Msk     (0x1UL)    /*!< TCMEA (Bitfield-Mask: 0x01)                           */
-/* =======================================================  AGTIOSEL  ======================================================== */
- #define R_AGT0_AGTIOSEL_TIES_Pos     (4UL)      /*!< TIES (Bit 4)                                          */
- #define R_AGT0_AGTIOSEL_TIES_Msk     (0x10UL)   /*!< TIES (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTIOSEL_SEL_Pos      (0UL)      /*!< SEL (Bit 0)                                           */
- #define R_AGT0_AGTIOSEL_SEL_Msk      (0x3UL)    /*!< SEL (Bitfield-Mask: 0x03)                             */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -14519,10 +15035,22 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
 /* =========================================================  GTCR  ========================================================== */
+ #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
+ #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTCR_TPCS_Pos              (24UL)         /*!< TPCS (Bit 24)                                         */
  #define R_GPT0_GTCR_TPCS_Msk              (0x7000000UL)  /*!< TPCS (Bitfield-Mask: 0x07)                            */
  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
- #define R_GPT0_GTCR_MD_Msk                (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
+ #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
+ #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
+ #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
+ #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
 /* =======================================================  GTUDDTYC  ======================================================== */
@@ -14580,6 +15108,8 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
 /* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
+ #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
@@ -14588,8 +15118,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
- #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
- #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
+ #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
+ #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
+ #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
 /* =========================================================  GTST  ========================================================== */
  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
@@ -14646,6 +15184,8 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
+ #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
@@ -14735,6 +15275,67 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 /* ========================================================  GTSOTR  ========================================================= */
  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
 /* ========================================================  GTICLF  ========================================================= */
  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
@@ -14777,14 +15378,113 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
+ #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
+ #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTBER2  ========================================================= */
+ #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
+ #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
+ #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
+ #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
+ #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
+ #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
+ #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
+ #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
+ #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
+ #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
+ #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
+ #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
+ #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
+ #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
+ #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
+ #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
+ #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
+ #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
+ #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
+ #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTOLBR  ========================================================= */
+ #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
+ #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
+ #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
+ #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  GTICCR  ========================================================= */
+ #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
+ #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
+ #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
+ #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
+ #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
+ #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
+ #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
+ #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
+ #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
+ #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
+ #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
+ #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
+ #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
+ #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
+ #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
+ #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
+ #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
+ #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
+ #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
+ #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
+ #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_OPS                                         ================ */
@@ -17049,6 +17749,9 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 /* ======================================================  CECCKDIVCR  ======================================================= */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  I3CCKDIVCR  ======================================================= */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
 /* ======================================================  IICCKDIVCR  ======================================================= */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
@@ -17854,6 +18557,10 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_WDT_WDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
  #define R_WDT_WDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
 /** @} */ /* End of group PosMask_peripherals */
 
  #ifdef __cplusplus
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h
index 3805b8135..dae037560 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h
@@ -799,7 +799,8 @@ typedef struct
             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
             uint8_t            : 1;
             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
-            uint8_t            : 2;
+            uint8_t            : 1;
+            __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
         } RTCCR_b;
     };
     __IM uint8_t RESERVED;
@@ -1144,6 +1145,213 @@ typedef struct
     };
 } R_USB_FS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
 
+/**
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
+            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
+            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
+            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
+            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
+            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
+        } AGTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
+            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
+            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
+            uint8_t              : 1;
+        } AGTMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+                                        *   ratio                                                                     */
+            uint8_t           : 4;
+            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
+        } AGTMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+                                        *   mode.                                                                     */
+            uint8_t             : 1;
+            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
+            uint8_t             : 1;
+            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
+            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
+        } AGTIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
+            uint8_t            : 5;
+        } AGTISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
+
+        struct
+        {
+            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
+            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
+            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
+            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
+            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
+            uint8_t              : 1;
+        } AGTCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_b;
+    };
+} R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
+
+        struct
+        {
+            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IM uint16_t                 RESERVED;
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
+} R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
+
+        struct
+        {
+            __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
+} R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_clusters */
 
 /* =========================================================================================================================== */
@@ -1436,16 +1644,17 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
 
     union
     {
-        __IM uint16_t ADDR[28];        /*!< (@ 0x00000020) A/D Data Register                                          */
+        __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
 
         struct
         {
             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
                                         *   storing the result of A/D conversion.                                     */
-        } ADDR_b[28];
+        } ADDR_b[29];
     };
-    __IM uint32_t RESERVED1[2];
-    __IM uint16_t RESERVED2;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+    __IM uint16_t RESERVED3;
 
     union
     {
@@ -1638,7 +1847,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint16_t                : 3;
         } ADSWTSTR2_b;
     };
-    __IM uint16_t RESERVED3;
+    __IM uint16_t RESERVED4;
 
     union
     {
@@ -1700,7 +1909,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 6;
         } ADACSR_b;
     };
-    __IM uint8_t RESERVED4;
+    __IM uint8_t RESERVED5;
 
     union
     {
@@ -1770,7 +1979,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
         } ADSER_b;
     };
-    __IM uint8_t RESERVED5;
+    __IM uint8_t RESERVED6;
 
     union
     {
@@ -1786,7 +1995,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
         } ADHVREFCNT_b;
     };
-    __IM uint8_t RESERVED6;
+    __IM uint8_t RESERVED7;
 
     union
     {
@@ -1804,8 +2013,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t              : 2;
         } ADWINMON_b;
     };
-    __IM uint8_t  RESERVED7;
-    __IM uint16_t RESERVED8;
+    __IM uint8_t  RESERVED8;
+    __IM uint16_t RESERVED9;
 
     union
     {
@@ -1981,7 +2190,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 6;
         } ADCMPSER_b;
     };
-    __IM uint8_t RESERVED9;
+    __IM uint8_t RESERVED10;
 
     union
     {
@@ -1996,7 +2205,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
         } ADCMPBNSR_b;
     };
-    __IM uint8_t RESERVED10;
+    __IM uint8_t RESERVED11;
 
     union
     {
@@ -2035,8 +2244,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 7;
         } ADCMPBSR_b;
     };
-    __IM uint8_t  RESERVED11;
-    __IM uint16_t RESERVED12;
+    __IM uint8_t  RESERVED12;
+    __IM uint16_t RESERVED13;
 
     union
     {
@@ -2240,7 +2449,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 7;
         } ADBUFEN_b;
     };
-    __IM uint8_t RESERVED13;
+    __IM uint8_t RESERVED14;
 
     union
     {
@@ -2254,9 +2463,9 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 3;
         } ADBUFPTR_b;
     };
-    __IM uint8_t  RESERVED14;
-    __IM uint32_t RESERVED15[2];
-    __IM uint8_t  RESERVED16;
+    __IM uint8_t  RESERVED15;
+    __IM uint32_t RESERVED16[2];
+    __IM uint8_t  RESERVED17;
 
     union
     {
@@ -2323,7 +2532,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
         } ADCALEXE_b;
     };
-    __IM uint8_t RESERVED17;
+    __IM uint8_t RESERVED18;
 
     union
     {
@@ -2340,8 +2549,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
         } VREFAMPCNT_b;
     };
-    __IM uint8_t  RESERVED18;
-    __IM uint16_t RESERVED19;
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -2363,8 +2572,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 6;
         } ADRST_b;
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint32_t RESERVED21[41];
+    __IM uint8_t  RESERVED21;
+    __IM uint32_t RESERVED22[41];
 
     union
     {
@@ -2422,7 +2631,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
         } ADPGAGS0_b;
     };
-    __IM uint32_t RESERVED22[3];
+    __IM uint32_t RESERVED23[3];
 
     union
     {
@@ -2449,7 +2658,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
         } ADPGADCR0_b;
     };
-    __IM uint16_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -2478,8 +2687,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 7;
         } ADPGADBS1_b;
     };
-    __IM uint16_t RESERVED24;
-    __IM uint32_t RESERVED25[10];
+    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED26[10];
 
     union
     {
@@ -2643,63 +2852,63 @@ typedef struct                         /*!< (@ 0x400E0000) R_PSCU Structure
 
     union
     {
-        __IM uint32_t CFSAMONA;        /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
+        __IOM uint32_t CFSAMONA;       /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
                                         *                  A                                                          */
 
         struct
         {
-            uint32_t           : 15;
-            __IM uint32_t CFS2 : 9;    /*!< [23..15] Code Flash Secure area 2                                         */
-            uint32_t           : 8;
+            uint32_t            : 15;
+            __IOM uint32_t CFS2 : 9;   /*!< [23..15] Code Flash Secure area 2                                         */
+            uint32_t            : 8;
         } CFSAMONA_b;
     };
 
     union
     {
-        __IM uint32_t CFSAMONB;        /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
+        __IOM uint32_t CFSAMONB;       /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
                                         *                  B                                                          */
 
         struct
         {
-            uint32_t           : 10;
-            __IM uint32_t CFS1 : 14;   /*!< [23..10] Code Flash Secure area 1                                         */
-            uint32_t           : 8;
+            uint32_t            : 10;
+            __IOM uint32_t CFS1 : 14;  /*!< [23..10] Code Flash Secure area 1                                         */
+            uint32_t            : 8;
         } CFSAMONB_b;
     };
 
     union
     {
-        __IM uint32_t DFSAMON;         /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register           */
+        __IOM uint32_t DFSAMON;        /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register           */
 
         struct
         {
-            uint32_t          : 10;
-            __IM uint32_t DFS : 6;     /*!< [15..10] Data flash Secure area                                           */
-            uint32_t          : 16;
+            uint32_t           : 10;
+            __IOM uint32_t DFS : 6;    /*!< [15..10] Data flash Secure area                                           */
+            uint32_t           : 16;
         } DFSAMON_b;
     };
 
     union
     {
-        __IM uint32_t SSAMONA;         /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A               */
+        __IOM uint32_t SSAMONA;        /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A               */
 
         struct
         {
-            uint32_t          : 13;
-            __IM uint32_t SS2 : 8;     /*!< [20..13] SRAM Secure area 2                                               */
-            uint32_t          : 11;
+            uint32_t           : 13;
+            __IOM uint32_t SS2 : 8;    /*!< [20..13] SRAM Secure area 2                                               */
+            uint32_t           : 11;
         } SSAMONA_b;
     };
 
     union
     {
-        __IM uint32_t SSAMONB;         /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B               */
+        __IOM uint32_t SSAMONB;        /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B               */
 
         struct
         {
-            uint32_t          : 10;
-            __IM uint32_t SS1 : 11;    /*!< [20..10] SRAM secure area 1                                               */
-            uint32_t          : 11;
+            uint32_t           : 10;
+            __IOM uint32_t SS1 : 11;   /*!< [20..10] SRAM secure area 1                                               */
+            uint32_t           : 11;
         } SSAMONB_b;
     };
 
@@ -2715,156 +2924,6 @@ typedef struct                         /*!< (@ 0x400E0000) R_PSCU Structure
     };
 } R_PSCU_Type;                         /*!< Size = 48 (0x30)                                                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Asynchronous General Purpose Timer (R_AGT0)
- */
-
-typedef struct                         /*!< (@ 0x400E8000) R_AGT0 Structure                                           */
-{
-    union
-    {
-        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
-
-        struct
-        {
-            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written
-                                        *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
-                                        *   is forcibly stopped and set to FFFFH.                                     */
-        } AGT_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCRn register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMA_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCR register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMB_b;
-    };
-    __IM uint16_t RESERVED;
-
-    union
-    {
-        __IOM uint8_t AGTCR;           /*!< (@ 0x00000008) AGT Control Register                                       */
-
-        struct
-        {
-            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
-            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
-            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
-            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
-            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
-            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
-        } AGTCR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000009) AGT Mode Register 1                                        */
-
-        struct
-        {
-            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
-            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
-            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
-            uint8_t              : 1;
-        } AGTMR1_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000A) AGT Mode Register 2                                        */
-
-        struct
-        {
-            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
-                                        *   ratio                                                                     */
-            uint8_t           : 4;
-            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
-        } AGTMR2_b;
-    };
-    __IM uint8_t RESERVED1;
-
-    union
-    {
-        __IOM uint8_t AGTIOC;          /*!< (@ 0x0000000C) AGT I/O Control Register                                   */
-
-        struct
-        {
-            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
-                                        *   mode.                                                                     */
-            uint8_t             : 1;
-            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
-            uint8_t             : 1;
-            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
-            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
-        } AGTIOC_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTISR;          /*!< (@ 0x0000000D) AGT Event Pin Select Register                              */
-
-        struct
-        {
-            uint8_t            : 2;
-            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
-            uint8_t            : 5;
-        } AGTISR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTCMSR;         /*!< (@ 0x0000000E) AGT Compare Match Function Select Register                 */
-
-        struct
-        {
-            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
-            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
-            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
-            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
-            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
-            uint8_t              : 1;
-        } AGTCMSR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x0000000F) AGT Pin Select Register                                    */
-
-        struct
-        {
-            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
-            uint8_t            : 2;
-            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
-            uint8_t            : 3;
-        } AGTIOSEL_b;
-    };
-} R_AGT0_Type;                         /*!< Size = 16 (0x10)                                                          */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -5455,43 +5514,96 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            uint32_t : 18;
         } GTSTR_b;
     };
 
@@ -5543,7 +5655,60 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
                                          *   1 means counter stop.                                                     */
-            uint32_t : 18;
+            __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
         } GTSTP_b;
     };
 
@@ -5567,7 +5732,24 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
-            uint32_t             : 18;
+            __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
         } GTCLR_b;
     };
 
@@ -5888,16 +6070,23 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+        __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
 
         struct
         {
-            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
-            uint32_t            : 15;
-            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
-            uint32_t            : 4;
-            __IOM uint32_t TPCS : 4;   /*!< [26..23] Timer Prescaler Select                                           */
-            uint32_t            : 5;
+            __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
+            uint32_t               : 7;
+            __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
+            __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
+            __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
+            __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
+            uint32_t               : 2;
+            __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
+            __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
+            uint32_t               : 3;
+            __IOM uint32_t TPCS    : 4; /*!< [26..23] Timer Prescaler Select                                           */
+            __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
+            uint32_t               : 3;
         } GTCR_b;
     };
 
@@ -5968,13 +6157,36 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
         struct
         {
-            uint32_t               : 24;
-            __IOM uint32_t GRP     : 2; /*!< [25..24] Output Disable Source Select                                     */
+            uint32_t            : 8;
+            __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
+            __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            uint32_t               : 4;
+            __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
             uint32_t               : 2;
-            __IOM uint32_t GRPDTE  : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
-            __IOM uint32_t GRPABH  : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable               */
-            __IOM uint32_t GRPABL  : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
-            __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
+            __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
+            __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
         } GTINTAD_b;
     };
 
@@ -6017,32 +6229,36 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTBER;          /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
 
         struct
         {
-            __IOM uint32_t BD0    : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
-            __IOM uint32_t BD1    : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
-            __IOM uint32_t BD2    : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
-            __IOM uint32_t BD3    : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
-            uint32_t              : 12;
-            __IOM uint32_t CCRA   : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
-            __IOM uint32_t CCRB   : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
-            __IOM uint32_t PR     : 2; /*!< [21..20] GTPR Buffer Operation                                            */
-            __OM uint32_t  CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
-                                        *   is read as 0.                                                             */
+            __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
+            __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+                                         *   is read as 0.                                                             */
             uint32_t             : 1;
-            __IOM uint32_t ADTTA : 2;  /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDA : 1;  /*!< [26..26] GTADTRA Double Buffer Operation                                  */
+            __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
             uint32_t             : 1;
-            __IOM uint32_t ADTTB : 2;  /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDB : 1;  /*!< [30..30] GTADTRB Double Buffer Operation                                  */
+            __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
             uint32_t             : 1;
         } GTBER_b;
     };
@@ -6266,7 +6482,126 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             uint32_t            : 31;
         } GTSOTR_b;
     };
-    __IM uint32_t RESERVED[5];
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
 
     union
     {
@@ -6300,7 +6635,7 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             uint32_t            : 4;
         } GTPC_b;
     };
-    __IM uint32_t RESERVED1[4];
+    __IM uint32_t RESERVED[4];
 
     union
     {
@@ -6342,17 +6677,137 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
         {
             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 4;
             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
-            uint32_t             : 7;
+            __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
+            uint32_t             : 6;
             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
-            uint32_t             : 7;
+            __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
+            uint32_t             : 6;
         } GTSECR_b;
     };
-} R_GPT0_Type;                         /*!< Size = 216 (0xd8)                                                         */
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
+            __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
+                                        *   Disable                                                                   */
+            uint32_t             : 2;
+            __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t             : 1;
+            __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
+                                        *   Transfer Disable                                                          */
+            uint32_t             : 2;
+            __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
+            __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
+            __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
+            __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
+            uint32_t             : 2;
+        } GTBER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
+
+        struct
+        {
+            __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
+            uint32_t              : 11;
+            __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
+            uint32_t              : 11;
+        } GTOLBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
+                                        *                  Capture Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
+            __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
+                                        *   Other Channel GTCCRb Input Capture Source Enable                          */
+            __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
+        } GTICCR_b;
+    };
+} R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
 
 /* =========================================================================================================================== */
 /* ================                                        R_GPT_POEG0                                        ================ */
@@ -10881,8 +11336,18 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } IICCKDIVCR_b;
         };
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint16_t RESERVED21;
+
+    union
+    {
+        __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
+
+        struct
+        {
+            __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
+            uint8_t                : 5;
+        } I3CCKDIVCR_b;
+    };
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -11009,8 +11474,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
         } I3CCKCR_b;
     };
-    __IM uint16_t RESERVED22;
-    __IM uint32_t RESERVED23[3];
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
 
     union
     {
@@ -11024,8 +11489,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                 : 29;
         } SNZREQCR1_b;
     };
-    __IM uint32_t RESERVED24;
-    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -11040,7 +11505,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
         } SNZCR_b;
     };
-    __IM uint8_t RESERVED26;
+    __IM uint8_t RESERVED25;
 
     union
     {
@@ -11070,7 +11535,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } SNZEDCR1_b;
     };
-    __IM uint16_t RESERVED27;
+    __IM uint16_t RESERVED26;
 
     union
     {
@@ -11113,7 +11578,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 1;
         } SNZREQCR_b;
     };
-    __IM uint16_t RESERVED28;
+    __IM uint16_t RESERVED27;
 
     union
     {
@@ -11151,7 +11616,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 3;
         } OPCCR_b;
     };
-    __IM uint8_t RESERVED29;
+    __IM uint8_t RESERVED28;
 
     union
     {
@@ -11163,7 +11628,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } MOSCWTCR_b;
     };
-    __IM uint8_t RESERVED30[2];
+    __IM uint8_t RESERVED29[2];
 
     union
     {
@@ -11176,7 +11641,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t : 5;
         } HOCOWTCR_b;
     };
-    __IM uint16_t RESERVED31[2];
+    __IM uint16_t RESERVED30[2];
 
     union
     {
@@ -11190,8 +11655,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 3;
         } SOPCCR_b;
     };
-    __IM uint8_t  RESERVED32;
-    __IM uint32_t RESERVED33[5];
+    __IM uint8_t  RESERVED31;
+    __IM uint32_t RESERVED32[5];
 
     union
     {
@@ -11225,8 +11690,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
         } RSTSR1_b;
     };
-    __IM uint16_t RESERVED34;
-    __IM uint32_t RESERVED35[3];
+    __IM uint16_t RESERVED33;
+    __IM uint32_t RESERVED34[3];
 
     union
     {
@@ -11252,8 +11717,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
         } SDADCCKCR_b;
     };
-    __IM uint16_t RESERVED36;
-    __IM uint32_t RESERVED37[3];
+    __IM uint16_t RESERVED35;
+    __IM uint32_t RESERVED36[3];
 
     union
     {
@@ -11308,7 +11773,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t          : 6;
         } LVD2SR_b;
     };
-    __IM uint32_t RESERVED38[183];
+    __IM uint32_t RESERVED37[183];
 
     union
     {
@@ -11336,7 +11801,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 14;
         } CGFSAR_b;
     };
-    __IM uint32_t RESERVED39;
+    __IM uint32_t RESERVED38;
 
     union
     {
@@ -11405,7 +11870,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 8;
         } BBFSAR_b;
     };
-    __IM uint32_t RESERVED40[3];
+    __IM uint32_t RESERVED39[3];
 
     union
     {
@@ -11467,8 +11932,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 4;
         } DPFSAR_b;
     };
-    __IM uint32_t RESERVED41[6];
-    __IM uint16_t RESERVED42;
+    __IM uint32_t RESERVED40[6];
+    __IM uint16_t RESERVED41;
 
     union
     {
@@ -11686,7 +12151,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 3;
         } DPSIEGR2_b;
     };
-    __IM uint8_t RESERVED43;
+    __IM uint8_t RESERVED42;
 
     union
     {
@@ -11744,7 +12209,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } RSTSR2_b;
     };
-    __IM uint8_t RESERVED44;
+    __IM uint8_t RESERVED43;
 
     union
     {
@@ -11761,7 +12226,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                           *   Enable                                                                    */
         } MOMCR_b;
     };
-    __IM uint16_t RESERVED45;
+    __IM uint16_t RESERVED44;
 
     union
     {
@@ -11831,7 +12296,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } LVD2CMPCR_b;
         };
     };
-    __IM uint8_t RESERVED46;
+    __IM uint8_t RESERVED45;
 
     union
     {
@@ -11864,7 +12329,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
         } LVD2CR0_b;
     };
-    __IM uint8_t RESERVED47;
+    __IM uint8_t RESERVED46;
 
     union
     {
@@ -11899,7 +12364,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 7;
         } VBTCR1_b;
     };
-    __IM uint32_t RESERVED48[8];
+    __IM uint32_t RESERVED47[8];
 
     union
     {
@@ -11942,7 +12407,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 6;
         } VCCSEL_b;
     };
-    __IM uint16_t RESERVED49;
+    __IM uint16_t RESERVED48;
 
     union
     {
@@ -11954,9 +12419,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } PL2LDOSCR_b;
     };
-    __IM uint8_t  RESERVED50;
-    __IM uint16_t RESERVED51;
-    __IM uint32_t RESERVED52[14];
+    __IM uint8_t  RESERVED49;
+    __IM uint16_t RESERVED50;
+    __IM uint32_t RESERVED51[14];
 
     union
     {
@@ -11979,8 +12444,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 6;
         } SOMCR_b;
     };
-    __IM uint16_t RESERVED53;
-    __IM uint32_t RESERVED54[3];
+    __IM uint16_t RESERVED52;
+    __IM uint32_t RESERVED53[3];
 
     union
     {
@@ -11992,7 +12457,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 7;
         } LOCOCR_b;
     };
-    __IM uint8_t RESERVED55;
+    __IM uint8_t RESERVED54;
 
     union
     {
@@ -12007,8 +12472,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                          *   trimming bits                                                             */
         } LOCOUTCR_b;
     };
-    __IM uint8_t  RESERVED56;
-    __IM uint32_t RESERVED57[7];
+    __IM uint8_t  RESERVED55;
+    __IM uint32_t RESERVED56[7];
 
     union
     {
@@ -12047,7 +12512,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 7;
         } VBTCMPCR_b;
     };
-    __IM uint8_t RESERVED58;
+    __IM uint8_t RESERVED57;
 
     union
     {
@@ -12061,7 +12526,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                  : 6;
         } VBTLVDICR_b;
     };
-    __IM uint8_t RESERVED59;
+    __IM uint8_t RESERVED58;
 
     union
     {
@@ -12073,7 +12538,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } VBTWCTLR_b;
     };
-    __IM uint8_t RESERVED60;
+    __IM uint8_t RESERVED59;
 
     union
     {
@@ -12208,9 +12673,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } VBTBER_b;
     };
-    __IM uint8_t  RESERVED61;
-    __IM uint16_t RESERVED62;
-    __IM uint32_t RESERVED63[15];
+    __IM uint8_t  RESERVED60;
+    __IM uint16_t RESERVED61;
+    __IM uint32_t RESERVED62[15];
 
     union
     {
@@ -13804,6 +14269,23 @@ typedef struct                           /*!< (@ 0x40008000) R_CPSCU Structure
     };
 } R_CPSCU_Type;                        /*!< Size = 1540 (0x604)                                                       */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
+ */
+
+typedef struct                          /*!< (@ 0x400E8000) R_AGTX0 Structure                                          */
+{
+    union
+    {
+        __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
+        __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
+    };
+} R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
 /* =========================================================================================================================== */
 /* ================                                          R_FLAD                                           ================ */
 /* =========================================================================================================================== */
@@ -13840,12 +14322,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_ADC0_BASE            0x40170000UL
  #define R_ADC1_BASE            0x40170200UL
  #define R_PSCU_BASE            0x400E0000UL
- #define R_AGT0_BASE            0x400E8000UL
- #define R_AGT1_BASE            0x400E8100UL
- #define R_AGT2_BASE            0x400E8200UL
- #define R_AGT3_BASE            0x400E8300UL
- #define R_AGT4_BASE            0x400E8400UL
- #define R_AGT5_BASE            0x400E8500UL
  #define R_BUS_BASE             0x40003000UL
  #define R_CAC_BASE             0x40083600UL
  #define R_CAN0_BASE            0x400A8000UL
@@ -13938,6 +14414,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_TZF_BASE             0x40000E00UL
  #define R_CACHE_BASE           0x40007000UL
  #define R_CPSCU_BASE           0x40008000UL
+ #define R_AGTX0_BASE           0x400E8000UL
+ #define R_AGTX1_BASE           0x400E8100UL
+ #define R_AGTX2_BASE           0x400E8200UL
+ #define R_AGTX3_BASE           0x400E8300UL
+ #define R_AGTX4_BASE           0x400E8400UL
+ #define R_AGTX5_BASE           0x400E8500UL
+ #define R_AGTX6_BASE           0x400E8600UL
+ #define R_AGTX7_BASE           0x400E8700UL
+ #define R_AGTX8_BASE           0x400E8800UL
+ #define R_AGTX9_BASE           0x400E8900UL
  #define R_FLAD_BASE            0x407FC000UL
 
 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
@@ -13953,12 +14439,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_ADC0            ((R_ADC0_Type *) R_ADC0_BASE)
  #define R_ADC1            ((R_ADC0_Type *) R_ADC1_BASE)
  #define R_PSCU            ((R_PSCU_Type *) R_PSCU_BASE)
- #define R_AGT0            ((R_AGT0_Type *) R_AGT0_BASE)
- #define R_AGT1            ((R_AGT0_Type *) R_AGT1_BASE)
- #define R_AGT2            ((R_AGT0_Type *) R_AGT2_BASE)
- #define R_AGT3            ((R_AGT0_Type *) R_AGT3_BASE)
- #define R_AGT4            ((R_AGT0_Type *) R_AGT4_BASE)
- #define R_AGT5            ((R_AGT0_Type *) R_AGT5_BASE)
 
 /* #define R_BUS                       ((R_BUS_Type*)             R_BUS_BASE) */
  #define R_CAC             ((R_CAC_Type *) R_CAC_BASE)
@@ -14052,6 +14532,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_TZF             ((R_TZF_Type *) R_TZF_BASE)
  #define R_CACHE           ((R_CACHE_Type *) R_CACHE_BASE)
  #define R_CPSCU           ((R_CPSCU_Type *) R_CPSCU_BASE)
+ #define R_AGTX0           ((R_AGTX0_Type *) R_AGTX0_BASE)
+ #define R_AGTX1           ((R_AGTX0_Type *) R_AGTX1_BASE)
+ #define R_AGTX2           ((R_AGTX0_Type *) R_AGTX2_BASE)
+ #define R_AGTX3           ((R_AGTX0_Type *) R_AGTX3_BASE)
+ #define R_AGTX4           ((R_AGTX0_Type *) R_AGTX4_BASE)
+ #define R_AGTX5           ((R_AGTX0_Type *) R_AGTX5_BASE)
+ #define R_AGTX6           ((R_AGTX0_Type *) R_AGTX6_BASE)
+ #define R_AGTX7           ((R_AGTX0_Type *) R_AGTX7_BASE)
+ #define R_AGTX8           ((R_AGTX0_Type *) R_AGTX8_BASE)
+ #define R_AGTX9           ((R_AGTX0_Type *) R_AGTX9_BASE)
  #define R_FLAD            ((R_FLAD_Type *) R_FLAD_BASE)
 
 /** @} */ /* End of group Device_Peripheral_declaration */
@@ -14409,6 +14899,8 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* =========================================================================================================================== */
 
 /* =========================================================  RTCCR  ========================================================= */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
@@ -14556,6 +15048,101 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
 
+/* =========================================================================================================================== */
+/* ================                                           CTRL                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  AGTCR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AGTMR1  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
+/* ========================================================  AGTMR2  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
+/* =====================================================  AGTIOSEL_ALT  ====================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+/* ========================================================  AGTIOC  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AGTISR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AGTCMSR  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
+/* =======================================================  AGTIOSEL  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT16                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT32                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
+
 /** @} */ /* End of group PosMask_clusters */
 
 /* =========================================================================================================================== */
@@ -15221,77 +15808,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_PSCU_DLMMON_DLMMON_Pos    (0UL)          /*!< DLMMON (Bit 0)                                        */
  #define R_PSCU_DLMMON_DLMMON_Msk    (0xfUL)        /*!< DLMMON (Bitfield-Mask: 0x0f)                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/* ==========================================================  AGT  ========================================================== */
- #define R_AGT0_AGT_AGT_Pos           (0UL)      /*!< AGT (Bit 0)                                           */
- #define R_AGT0_AGT_AGT_Msk           (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
-/* ========================================================  AGTCMA  ========================================================= */
- #define R_AGT0_AGTCMA_AGTCMA_Pos     (0UL)      /*!< AGTCMA (Bit 0)                                        */
- #define R_AGT0_AGTCMA_AGTCMA_Msk     (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
-/* ========================================================  AGTCMB  ========================================================= */
- #define R_AGT0_AGTCMB_AGTCMB_Pos     (0UL)      /*!< AGTCMB (Bit 0)                                        */
- #define R_AGT0_AGTCMB_AGTCMB_Msk     (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
-/* =========================================================  AGTCR  ========================================================= */
- #define R_AGT0_AGTCR_TCMBF_Pos       (7UL)      /*!< TCMBF (Bit 7)                                         */
- #define R_AGT0_AGTCR_TCMBF_Msk       (0x80UL)   /*!< TCMBF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCMAF_Pos       (6UL)      /*!< TCMAF (Bit 6)                                         */
- #define R_AGT0_AGTCR_TCMAF_Msk       (0x40UL)   /*!< TCMAF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TUNDF_Pos       (5UL)      /*!< TUNDF (Bit 5)                                         */
- #define R_AGT0_AGTCR_TUNDF_Msk       (0x20UL)   /*!< TUNDF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TEDGF_Pos       (4UL)      /*!< TEDGF (Bit 4)                                         */
- #define R_AGT0_AGTCR_TEDGF_Msk       (0x10UL)   /*!< TEDGF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTOP_Pos       (2UL)      /*!< TSTOP (Bit 2)                                         */
- #define R_AGT0_AGTCR_TSTOP_Msk       (0x4UL)    /*!< TSTOP (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCSTF_Pos       (1UL)      /*!< TCSTF (Bit 1)                                         */
- #define R_AGT0_AGTCR_TCSTF_Msk       (0x2UL)    /*!< TCSTF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTART_Pos      (0UL)      /*!< TSTART (Bit 0)                                        */
- #define R_AGT0_AGTCR_TSTART_Msk      (0x1UL)    /*!< TSTART (Bitfield-Mask: 0x01)                          */
-/* ========================================================  AGTMR1  ========================================================= */
- #define R_AGT0_AGTMR1_TCK_Pos        (4UL)      /*!< TCK (Bit 4)                                           */
- #define R_AGT0_AGTMR1_TCK_Msk        (0x70UL)   /*!< TCK (Bitfield-Mask: 0x07)                             */
- #define R_AGT0_AGTMR1_TEDGPL_Pos     (3UL)      /*!< TEDGPL (Bit 3)                                        */
- #define R_AGT0_AGTMR1_TEDGPL_Msk     (0x8UL)    /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTMR1_TMOD_Pos       (0UL)      /*!< TMOD (Bit 0)                                          */
- #define R_AGT0_AGTMR1_TMOD_Msk       (0x7UL)    /*!< TMOD (Bitfield-Mask: 0x07)                            */
-/* ========================================================  AGTMR2  ========================================================= */
- #define R_AGT0_AGTMR2_LPM_Pos        (7UL)      /*!< LPM (Bit 7)                                           */
- #define R_AGT0_AGTMR2_LPM_Msk        (0x80UL)   /*!< LPM (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTMR2_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
- #define R_AGT0_AGTMR2_CKS_Msk        (0x7UL)    /*!< CKS (Bitfield-Mask: 0x07)                             */
-/* ========================================================  AGTIOC  ========================================================= */
- #define R_AGT0_AGTIOC_TIOGT_Pos      (6UL)      /*!< TIOGT (Bit 6)                                         */
- #define R_AGT0_AGTIOC_TIOGT_Msk      (0xc0UL)   /*!< TIOGT (Bitfield-Mask: 0x03)                           */
- #define R_AGT0_AGTIOC_TIPF_Pos       (4UL)      /*!< TIPF (Bit 4)                                          */
- #define R_AGT0_AGTIOC_TIPF_Msk       (0x30UL)   /*!< TIPF (Bitfield-Mask: 0x03)                            */
- #define R_AGT0_AGTIOC_TOE_Pos        (2UL)      /*!< TOE (Bit 2)                                           */
- #define R_AGT0_AGTIOC_TOE_Msk        (0x4UL)    /*!< TOE (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTIOC_TEDGSEL_Pos    (0UL)      /*!< TEDGSEL (Bit 0)                                       */
- #define R_AGT0_AGTIOC_TEDGSEL_Msk    (0x1UL)    /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
-/* ========================================================  AGTISR  ========================================================= */
- #define R_AGT0_AGTISR_EEPS_Pos       (2UL)      /*!< EEPS (Bit 2)                                          */
- #define R_AGT0_AGTISR_EEPS_Msk       (0x4UL)    /*!< EEPS (Bitfield-Mask: 0x01)                            */
-/* ========================================================  AGTCMSR  ======================================================== */
- #define R_AGT0_AGTCMSR_TOPOLB_Pos    (6UL)      /*!< TOPOLB (Bit 6)                                        */
- #define R_AGT0_AGTCMSR_TOPOLB_Msk    (0x40UL)   /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEB_Pos      (5UL)      /*!< TOEB (Bit 5)                                          */
- #define R_AGT0_AGTCMSR_TOEB_Msk      (0x20UL)   /*!< TOEB (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEB_Pos     (4UL)      /*!< TCMEB (Bit 4)                                         */
- #define R_AGT0_AGTCMSR_TCMEB_Msk     (0x10UL)   /*!< TCMEB (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCMSR_TOPOLA_Pos    (2UL)      /*!< TOPOLA (Bit 2)                                        */
- #define R_AGT0_AGTCMSR_TOPOLA_Msk    (0x4UL)    /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEA_Pos      (1UL)      /*!< TOEA (Bit 1)                                          */
- #define R_AGT0_AGTCMSR_TOEA_Msk      (0x2UL)    /*!< TOEA (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEA_Pos     (0UL)      /*!< TCMEA (Bit 0)                                         */
- #define R_AGT0_AGTCMSR_TCMEA_Msk     (0x1UL)    /*!< TCMEA (Bitfield-Mask: 0x01)                           */
-/* =======================================================  AGTIOSEL  ======================================================== */
- #define R_AGT0_AGTIOSEL_TIES_Pos     (4UL)      /*!< TIES (Bit 4)                                          */
- #define R_AGT0_AGTIOSEL_TIES_Msk     (0x10UL)   /*!< TIES (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTIOSEL_SEL_Pos      (0UL)      /*!< SEL (Bit 0)                                           */
- #define R_AGT0_AGTIOSEL_SEL_Msk      (0x3UL)    /*!< SEL (Bitfield-Mask: 0x03)                             */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -16709,10 +17225,22 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
 /* =========================================================  GTCR  ========================================================== */
+ #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
+ #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTCR_TPCS_Pos              (23UL)         /*!< TPCS (Bit 23)                                         */
  #define R_GPT0_GTCR_TPCS_Msk              (0x7800000UL)  /*!< TPCS (Bitfield-Mask: 0x0f)                            */
  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
- #define R_GPT0_GTCR_MD_Msk                (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
+ #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
+ #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
+ #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
+ #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
 /* =======================================================  GTUDDTYC  ======================================================== */
@@ -16770,6 +17298,8 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
 /* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
+ #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
@@ -16778,8 +17308,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
- #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
- #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
+ #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
+ #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
+ #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
 /* =========================================================  GTST  ========================================================== */
  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
@@ -16836,6 +17374,8 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
+ #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
@@ -16925,6 +17465,67 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* ========================================================  GTSOTR  ========================================================= */
  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
 /* ========================================================  GTICLF  ========================================================= */
  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
@@ -16967,14 +17568,113 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
+ #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
+ #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTBER2  ========================================================= */
+ #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
+ #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
+ #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
+ #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
+ #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
+ #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
+ #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
+ #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
+ #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
+ #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
+ #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
+ #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
+ #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
+ #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
+ #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
+ #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
+ #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
+ #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
+ #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
+ #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTOLBR  ========================================================= */
+ #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
+ #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
+ #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
+ #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  GTICCR  ========================================================= */
+ #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
+ #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
+ #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
+ #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
+ #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
+ #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
+ #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
+ #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
+ #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
+ #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
+ #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
+ #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
+ #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
+ #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
+ #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
+ #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
+ #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
+ #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
+ #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
+ #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
+ #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
 
 /* =========================================================================================================================== */
 /* ================                                        R_GPT_POEG0                                        ================ */
@@ -19621,6 +20321,9 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* ======================================================  CECCKDIVCR  ======================================================= */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  I3CCKDIVCR  ======================================================= */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
 /* ======================================================  IICCKDIVCR  ======================================================= */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
@@ -20580,6 +21283,10 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_CPSCU_TEVTRCR_TEVTE_Pos           (0UL)          /*!< TEVTE (Bit 0)                                         */
  #define R_CPSCU_TEVTRCR_TEVTE_Msk           (0x1UL)        /*!< TEVTE (Bitfield-Mask: 0x01)                           */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
 /* =========================================================================================================================== */
 /* ================                                          R_FLAD                                           ================ */
 /* =========================================================================================================================== */
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E2BB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E2BB.h
new file mode 100644
index 000000000..4db4438b7
--- /dev/null
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E2BB.h
@@ -0,0 +1,22152 @@
+/*
+ * This software is supplied by Renesas Electronics Corporation and is only intended for
+ * use with Renesas products. No other uses are authorized. This software is owned by
+ * Renesas Electronics Corporation and is protected under all applicable laws, including
+ * copyright laws.
+ *
+ * THIS SOFTWARE IS PROVIDED 'AS IS' AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT
+ * PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED
+ * COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL
+ * DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ *
+ * Renesas reserves the right, without notice, to make changes to this software and to
+ * discontinue the availability of this software. By using this software, you agree to
+ * the additional terms and conditions found by accessing the following link:
+ * http://www.renesas.com/disclaimer
+ *
+ *
+ * @file     ./out/R7FA6E2BB.h
+ * @brief    CMSIS HeaderFile
+ * @version  1.00.00
+ */
+
+/** @addtogroup Renesas Electronics Corporation
+ * @{
+ */
+
+/** @addtogroup R7FA6E2BB
+ * @{
+ */
+
+#ifndef R7FA6E2BB_H
+ #define R7FA6E2BB_H
+
+ #ifdef __cplusplus
+extern "C" {
+ #endif
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                Interrupt Number Definition                                ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                           Processor and Core Peripheral Section                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================  Configuration of the ARM Cortex-M33 Processor and Core Peripherals  =========================== */
+ #define __CM33_REV                0x0004U /*!< CM33 Core Revision                                                        */
+ #define __NVIC_PRIO_BITS          4       /*!< Number of Bits used for Priority Levels                                   */
+ #define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used                              */
+ #define __VTOR_PRESENT            1       /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
+ #define __MPU_PRESENT             1       /*!< MPU present                                                               */
+ #define __FPU_PRESENT             1       /*!< FPU present                                                               */
+ #define __FPU_DP                  0       /*!< Double Precision FPU                                                      */
+ #define __DSP_PRESENT             1       /*!< DSP extension present                                                     */
+ #define __SAUREGION_PRESENT       0       /*!< SAU region present                                                        */
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+ #include "core_cm33.h"                    /*!< ARM Cortex-M33 processor and core peripherals                             */
+ #include "system.h"                       /*!< R7FA6E2BB System                                                          */
+
+ #ifndef __IM                              /*!< Fallback for older CMSIS versions                                         */
+  #define __IM     __I
+ #endif
+ #ifndef __OM                              /*!< Fallback for older CMSIS versions                                         */
+  #define __OM     __O
+ #endif
+ #ifndef __IOM                             /*!< Fallback for older CMSIS versions                                         */
+  #define __IOM    __IO
+ #endif
+
+/* ========================================  Start of section using anonymous unions  ======================================== */
+ #if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+ #elif defined(__ICCARM__)
+  #pragma language=extended
+ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wc11-extensions"
+  #pragma clang diagnostic ignored "-Wreserved-id-macro"
+  #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
+  #pragma clang diagnostic ignored "-Wnested-anon-types"
+ #elif defined(__GNUC__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TMS470__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TASKING__)
+  #pragma warning 586
+ #elif defined(__CSMC__)
+
+/* anonymous unions are enabled by default */
+ #else
+  #warning Not supported compiler type
+ #endif
+
+/* =========================================================================================================================== */
+/* ================                              Device Specific Cluster Section                              ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_clusters
+ * @{
+ */
+
+/**
+ * @brief R_BUS_CSa [CSa] (CS Registers)
+ */
+typedef struct
+{
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t MOD;            /*!< (@ 0x00000002) Mode Register                                              */
+
+        struct
+        {
+            __IOM uint16_t WRMOD : 1;  /*!< [0..0] Write Access Mode Select                                           */
+            uint16_t             : 2;
+            __IOM uint16_t EWENB : 1;  /*!< [3..3] External Wait Enable                                               */
+            uint16_t             : 4;
+            __IOM uint16_t PRENB : 1;  /*!< [8..8] Page Read Access Enable                                            */
+            __IOM uint16_t PWENB : 1;  /*!< [9..9] Page Write Access Enable                                           */
+            uint16_t             : 5;
+            __IOM uint16_t PRMOD : 1;  /*!< [15..15] Page Read Access Mode Select                                     */
+        } MOD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t WCR1;             /*!< (@ 0x00000004) Wait Control Register 1                                    */
+
+        struct
+        {
+            __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value
+                                          *   is valid only when the PWENB bit in CSnMOD is set to 1.                   */
+            uint32_t                : 5;
+            __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value
+                                          *   is valid only when the PRENB bit in CSnMOD is set to 1.                   */
+            uint32_t               : 5;
+            __IOM uint32_t CSWWAIT : 5;  /*!< [20..16] Normal Write Cycle Wait Select                                   */
+            uint32_t               : 3;
+            __IOM uint32_t CSRWAIT : 5;  /*!< [28..24] Normal Read Cycle Wait Select                                    */
+            uint32_t               : 3;
+        } WCR1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t WCR2;           /*!< (@ 0x00000008) Wait Control Register 2                                    */
+
+        struct
+        {
+            __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select                              */
+            uint32_t              : 1;
+            __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select                             */
+            uint32_t              : 1;
+            __IOM uint32_t WDOFF  : 3; /*!< [10..8] Write Data Output Extension Cycle Select                          */
+            uint32_t              : 1;
+            __IOM uint32_t AWAIT  : 2; /*!< [13..12] CS Assert Wait Select                                            */
+            uint32_t              : 2;
+            __IOM uint32_t RDON   : 3; /*!< [18..16] RD Assert Wait Select                                            */
+            uint32_t              : 1;
+            __IOM uint32_t WRON   : 3; /*!< [22..20] WR Assert Wait Select                                            */
+            uint32_t              : 1;
+            __IOM uint32_t WDON   : 3; /*!< [26..24] Write Data Output Wait Select                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CSON   : 3; /*!< [30..28] CS Assert Wait Select                                            */
+            uint32_t              : 1;
+        } WCR2_b;
+    };
+    __IM uint32_t RESERVED1;
+} R_BUS_CSa_Type;                      /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_BUS_CSb [CSb] (CS Registers)
+ */
+typedef struct
+{
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t CR;             /*!< (@ 0x00000002) Control Register                                           */
+
+        struct
+        {
+            __IOM uint16_t EXENB : 1;  /*!< [0..0] Operation Enable                                                   */
+            uint16_t             : 3;
+            __IOM uint16_t BSIZE : 2;  /*!< [5..4] External Bus Width Select                                          */
+            uint16_t             : 2;
+            __IOM uint16_t EMODE : 1;  /*!< [8..8] Endian Mode                                                        */
+            uint16_t             : 3;
+            __IOM uint16_t MPXEN : 1;  /*!< [12..12] Address/Data Multiplexed I/O Interface Select                    */
+            uint16_t             : 3;
+        } CR_b;
+    };
+    __IM uint16_t RESERVED1[3];
+
+    union
+    {
+        __IOM uint16_t REC;            /*!< (@ 0x0000000A) Recovery Cycle Register                                    */
+
+        struct
+        {
+            __IOM uint16_t RRCV : 4;   /*!< [3..0] Read Recovery                                                      */
+            uint16_t            : 4;
+            __IOM uint16_t WRCV : 4;   /*!< [11..8] Write Recovery                                                    */
+            uint16_t            : 4;
+        } REC_b;
+    };
+    __IM uint16_t RESERVED2[2];
+} R_BUS_CSb_Type;                      /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t SDCCR;           /*!< (@ 0x00000000) SDC Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t EXENB : 1;   /*!< [0..0] Operation Enable                                                   */
+            uint8_t             : 3;
+            __IOM uint8_t BSIZE : 2;   /*!< [5..4] SDRAM Bus Width Select                                             */
+            uint8_t             : 2;
+        } SDCCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SDCMOD;          /*!< (@ 0x00000001) SDC Mode Register                                          */
+
+        struct
+        {
+            __IOM uint8_t EMODE : 1;   /*!< [0..0] Endian Mode                                                        */
+            uint8_t             : 7;
+        } SDCMOD_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SDAMOD;          /*!< (@ 0x00000002) SDRAM Access Mode Register                                 */
+
+        struct
+        {
+            __IOM uint8_t BE : 1;      /*!< [0..0] Continuous Access Enable                                           */
+            uint8_t          : 7;
+        } SDAMOD_b;
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint32_t RESERVED1[3];
+
+    union
+    {
+        __IOM uint8_t SDSELF;          /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t SFEN : 1;    /*!< [0..0] SDRAM Self-Refresh Enable                                          */
+            uint8_t            : 7;
+        } SDSELF_b;
+    };
+    __IM uint8_t  RESERVED2;
+    __IM uint16_t RESERVED3;
+
+    union
+    {
+        __IOM uint16_t SDRFCR;         /*!< (@ 0x00000014) SDRAM Refresh Control Register                             */
+
+        struct
+        {
+            __IOM uint16_t RFC  : 12;  /*!< [11..0] Auto-Refresh Request Interval Setting                             */
+            __IOM uint16_t REFW : 4;   /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count
+                                        *   Setting. ( REFW+1 Cycles )                                                */
+        } SDRFCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SDRFEN;          /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t RFEN : 1;    /*!< [0..0] Auto-Refresh Operation Enable                                      */
+            uint8_t            : 7;
+        } SDRFEN_b;
+    };
+    __IM uint8_t  RESERVED4;
+    __IM uint32_t RESERVED5[2];
+
+    union
+    {
+        __IOM uint8_t SDICR;           /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register             */
+
+        struct
+        {
+            __IOM uint8_t INIRQ : 1;   /*!< [0..0] Initialization Sequence Start                                      */
+            uint8_t             : 7;
+        } SDICR_b;
+    };
+    __IM uint8_t  RESERVED6;
+    __IM uint16_t RESERVED7;
+
+    union
+    {
+        __IOM uint16_t SDIR;           /*!< (@ 0x00000024) SDRAM Initialization Register                              */
+
+        struct
+        {
+            __IOM uint16_t ARFI : 4;   /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles )              */
+            __IOM uint16_t ARFC : 4;   /*!< [7..4] Initialization Auto-Refresh Count                                  */
+            __IOM uint16_t PRC  : 3;   /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles
+                                        *   )                                                                         */
+            uint16_t : 5;
+        } SDIR_b;
+    };
+    __IM uint16_t RESERVED8;
+    __IM uint32_t RESERVED9[6];
+
+    union
+    {
+        __IOM uint8_t SDADR;           /*!< (@ 0x00000040) SDRAM Address Register                                     */
+
+        struct
+        {
+            __IOM uint8_t MXC : 2;     /*!< [1..0] Address Multiplex Select                                           */
+            uint8_t           : 6;
+        } SDADR_b;
+    };
+    __IM uint8_t  RESERVED10;
+    __IM uint16_t RESERVED11;
+
+    union
+    {
+        __IOM uint32_t SDTR;           /*!< (@ 0x00000044) SDRAM Timing Register                                      */
+
+        struct
+        {
+            __IOM uint32_t CL  : 3;    /*!< [2..0] SDRAMC Column Latency                                              */
+            uint32_t           : 5;
+            __IOM uint32_t WR  : 1;    /*!< [8..8] Write Recovery Interval                                            */
+            __IOM uint32_t RP  : 3;    /*!< [11..9] Row Precharge Interval ( RP+1 cycles )                            */
+            __IOM uint32_t RCD : 2;    /*!< [13..12] Row Column Latency ( RCD+1 cycles )                              */
+            uint32_t           : 2;
+            __IOM uint32_t RAS : 3;    /*!< [18..16] Row Active Interval                                              */
+            uint32_t           : 13;
+        } SDTR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t SDMOD;          /*!< (@ 0x00000048) SDRAM Mode Register                                        */
+
+        struct
+        {
+            __IOM uint16_t MR : 15;    /*!< [14..0] Mode Register SettingWriting to these bits: Mode register
+                                        *   set command is issued.                                                    */
+            uint16_t : 1;
+        } SDMOD_b;
+    };
+    __IM uint16_t RESERVED12;
+    __IM uint32_t RESERVED13;
+
+    union
+    {
+        __IM uint8_t SDSR;             /*!< (@ 0x00000050) SDRAM Status Register                                      */
+
+        struct
+        {
+            __IM uint8_t MRSST : 1;    /*!< [0..0] Mode Register Setting Status                                       */
+            uint8_t            : 2;
+            __IM uint8_t INIST : 1;    /*!< [3..3] Initialization Status                                              */
+            __IM uint8_t SRFST : 1;    /*!< [4..4] Self-Refresh Transition/Recovery Status                            */
+            uint8_t            : 3;
+        } SDSR_b;
+    };
+    __IM uint8_t  RESERVED14;
+    __IM uint16_t RESERVED15;
+} R_BUS_SDRAM_Type;                    /*!< Size = 84 (0x54)                                                          */
+
+/**
+ * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IM uint32_t ADD;             /*!< (@ 0x00000000) Bus Error Address Register                                 */
+
+        struct
+        {
+            __IM uint32_t BERAD : 32;  /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores
+                                        *   an error address.                                                         */
+        } ADD_b;
+    };
+
+    union
+    {
+        __IM uint8_t STAT;             /*!< (@ 0x00000004) Bus Error Status Register                                  */
+
+        struct
+        {
+            __IM uint8_t ACCSTAT : 1;  /*!< [0..0] Error access statusThe status at the time of the error             */
+            uint8_t              : 6;
+            __IM uint8_t ERRSTAT : 1;  /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs.          */
+        } STAT_b;
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2[2];
+} R_BUS_BUSERR_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t CNT;            /*!< (@ 0x00000000) Master Bus Control Register                                */
+
+        struct
+        {
+            uint16_t             : 15;
+            __IOM uint16_t IERES : 1;  /*!< [15..15] Ignore Error Responses                                           */
+        } CNT_b;
+    };
+    __IM uint16_t RESERVED;
+} R_BUS_BUSM_Type;                     /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t CNT;            /*!< (@ 0x00000000) Slave Bus Control Register                                 */
+
+        struct
+        {
+            uint16_t              : 4;
+            __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups              */
+            uint16_t              : 10;
+        } CNT_b;
+    };
+    __IM uint16_t RESERVED;
+} R_BUS_BUSS_Type;                     /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t NCFG;            /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register             */
+
+        struct
+        {
+            __IOM uint32_t NBRP   : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler                                */
+            __IOM uint32_t NSJW   : 7;  /*!< [16..10] Resynchronization Jump Width                                     */
+            __IOM uint32_t NTSEG1 : 8;  /*!< [24..17] Timing Segment 1                                                 */
+            __IOM uint32_t NTSEG2 : 7;  /*!< [31..25] Timing Segment 2                                                 */
+        } NCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CTR;             /*!< (@ 0x00000004) Channel Control Registers                                  */
+
+        struct
+        {
+            __IOM uint32_t CHMDC   : 2; /*!< [1..0] Channel Mode Control                                               */
+            __IOM uint32_t CSLPR   : 1; /*!< [2..2] Channel Sleep Request                                              */
+            __IOM uint32_t RTBO    : 1; /*!< [3..3] Return from Bus-Off                                                */
+            uint32_t               : 4;
+            __IOM uint32_t BEIE    : 1; /*!< [8..8] Bus Error Interrupt Enable                                         */
+            __IOM uint32_t EWIE    : 1; /*!< [9..9] Error Warning Interrupt Enable                                     */
+            __IOM uint32_t EPIE    : 1; /*!< [10..10] Error Passive Interrupt Enable                                   */
+            __IOM uint32_t BOEIE   : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable                                   */
+            __IOM uint32_t BORIE   : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable                                */
+            __IOM uint32_t OLIE    : 1; /*!< [13..13] Overload Interrupt Enable                                        */
+            __IOM uint32_t BLIE    : 1; /*!< [14..14] Bus Lock Interrupt Enable                                        */
+            __IOM uint32_t ALIE    : 1; /*!< [15..15] Arbitration Lost Interrupt Enable                                */
+            __IOM uint32_t TAIE    : 1; /*!< [16..16] Transmission abort Interrupt Enable                              */
+            __IOM uint32_t EOCOIE  : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable               */
+            __IOM uint32_t SOCOIE  : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable          */
+            __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt
+                                         *   enable                                                                    */
+            uint32_t            : 1;
+            __IOM uint32_t BOM  : 2;    /*!< [22..21] Channel Bus-Off Mode                                             */
+            __IOM uint32_t ERRD : 1;    /*!< [23..23] Channel Error Display                                            */
+            __IOM uint32_t CTME : 1;    /*!< [24..24] Channel Test Mode Enable                                         */
+            __IOM uint32_t CTMS : 2;    /*!< [26..25] Channel Test Mode Select                                         */
+            uint32_t            : 3;
+            __IOM uint32_t CRCT : 1;    /*!< [30..30] CRC Error Test                                                   */
+            __IOM uint32_t ROM  : 1;    /*!< [31..31] Restricted Operation Mode                                        */
+        } CTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STS;             /*!< (@ 0x00000008) Channel Status Registers                                   */
+
+        struct
+        {
+            __IM uint32_t  CRSTSTS : 1; /*!< [0..0] Channel RESET Status                                               */
+            __IM uint32_t  CHLTSTS : 1; /*!< [1..1] Channel HALT Status                                                */
+            __IM uint32_t  CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status                                               */
+            __IM uint32_t  EPSTS   : 1; /*!< [3..3] Channel Error Passive Status                                       */
+            __IM uint32_t  BOSTS   : 1; /*!< [4..4] Channel Bus-Off Status                                             */
+            __IM uint32_t  TRMSTS  : 1; /*!< [5..5] Channel Transmit Status                                            */
+            __IM uint32_t  RECSTS  : 1; /*!< [6..6] Channel Receive Status                                             */
+            __IM uint32_t  COMSTS  : 1; /*!< [7..7] Channel Communication Status                                       */
+            __IOM uint32_t ESIF    : 1; /*!< [8..8] Error State Indication Flag                                        */
+            uint32_t               : 7;
+            __IM uint32_t  REC     : 8; /*!< [23..16] Reception Error Count                                            */
+            __IOM uint32_t TEC     : 8; /*!< [31..24] Transmission Error Count                                         */
+        } STS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ERFL;           /*!< (@ 0x0000000C) Channel Error Flag Registers                               */
+
+        struct
+        {
+            __IOM uint32_t BEF   : 1;  /*!< [0..0] Bus Error Flag                                                     */
+            __IOM uint32_t EWF   : 1;  /*!< [1..1] Error Warning Flag                                                 */
+            __IOM uint32_t EPF   : 1;  /*!< [2..2] Error Passive Flag                                                 */
+            __IOM uint32_t BOEF  : 1;  /*!< [3..3] Bus-Off Entry Flag                                                 */
+            __IOM uint32_t BORF  : 1;  /*!< [4..4] Bus-Off Recovery Flag                                              */
+            __IOM uint32_t OVLF  : 1;  /*!< [5..5] Overload Flag                                                      */
+            __IOM uint32_t BLF   : 1;  /*!< [6..6] Bus Lock Flag                                                      */
+            __IOM uint32_t ALF   : 1;  /*!< [7..7] Arbitration Lost Flag                                              */
+            __IOM uint32_t SERR  : 1;  /*!< [8..8] Stuff Error                                                        */
+            __IOM uint32_t FERR  : 1;  /*!< [9..9] Form Error                                                         */
+            __IOM uint32_t AERR  : 1;  /*!< [10..10] Acknowledge Error                                                */
+            __IOM uint32_t CERR  : 1;  /*!< [11..11] CRC Error                                                        */
+            __IOM uint32_t B1ERR : 1;  /*!< [12..12] Bit 1 Error                                                      */
+            __IOM uint32_t B0ERR : 1;  /*!< [13..13] Bit 0 Error                                                      */
+            __IOM uint32_t ADERR : 1;  /*!< [14..14] Acknowledge Delimiter Error                                      */
+            uint32_t             : 1;
+            __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value                                               */
+            uint32_t             : 1;
+        } ERFL_b;
+    };
+} R_CANFD_CFDC_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t DCFG;           /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register                */
+
+        struct
+        {
+            __IOM uint32_t DBRP   : 8; /*!< [7..0] Channel Data Baud Rate Prescaler                                   */
+            __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1                                                  */
+            uint32_t              : 3;
+            __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2                                                 */
+            uint32_t              : 4;
+            __IOM uint32_t DSJW   : 4; /*!< [27..24] Resynchronization Jump Width                                     */
+            uint32_t              : 4;
+        } DCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDCFG;          /*!< (@ 0x00000004) Channel CAN-FD Configuration Register                      */
+
+        struct
+        {
+            __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration                             */
+            uint32_t              : 5;
+            __IOM uint32_t TDCOC  : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration                */
+            __IOM uint32_t TDCE   : 1; /*!< [9..9] Transceiver Delay Compensation Enable                              */
+            __IOM uint32_t ESIC   : 1; /*!< [10..10] Error State Indication Configuration                             */
+            uint32_t              : 5;
+            __IOM uint32_t TDCO   : 8; /*!< [23..16] Transceiver Delay Compensation Offset                            */
+            uint32_t              : 4;
+            __IOM uint32_t FDOE   : 1; /*!< [28..28] FD only enable                                                   */
+            __IOM uint32_t REFE   : 1; /*!< [29..29] RX edge filter enable                                            */
+            __IOM uint32_t CLOE   : 1; /*!< [30..30] Classical CAN only enable                                        */
+            uint32_t              : 1;
+        } FDCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) Channel CAN-FD Control Register                            */
+
+        struct
+        {
+            __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear                                     */
+            __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear                                */
+            uint32_t              : 30;
+        } FDCTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDSTS;          /*!< (@ 0x0000000C) Channel CAN-FD Status Register                             */
+
+        struct
+        {
+            __IM uint32_t  TDCR  : 8;  /*!< [7..0] Transceiver Delay Compensation Result                              */
+            __IOM uint32_t EOCO  : 1;  /*!< [8..8] Error occurrence counter overflow                                  */
+            __IOM uint32_t SOCO  : 1;  /*!< [9..9] Successful occurrence counter overflow                             */
+            uint32_t             : 5;
+            __IOM uint32_t TDCVF : 1;  /*!< [15..15] Transceiver Delay Compensation Violation Flag                    */
+            __IM uint32_t  EOC   : 8;  /*!< [23..16] Error occurrence counter register                                */
+            __IM uint32_t  SOC   : 8;  /*!< [31..24] Successful occurrence counter register                           */
+        } FDSTS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDCRC;          /*!< (@ 0x00000010) Channel CAN-FD CRC Register                                */
+
+        struct
+        {
+            __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value                                                */
+            uint32_t             : 3;
+            __IM uint32_t SCNT   : 4;  /*!< [27..24] Stuff bit count                                                  */
+            uint32_t             : 4;
+        } FDCRC_b;
+    };
+    __IM uint32_t RESERVED[3];
+} R_CANFD_CFDC2_Type;                  /*!< Size = 32 (0x20)                                                          */
+
+/**
+ * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t ID;               /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers                 */
+
+        struct
+        {
+            __IOM uint32_t GAFLID  : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field                      */
+            __IOM uint32_t GAFLLB  : 1;  /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration       */
+            __IOM uint32_t GAFLRTR : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Field                    */
+            __IOM uint32_t GAFLIDE : 1;  /*!< [31..31] Global Acceptance Filter List Entry IDE Field                    */
+        } ID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t M;                 /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers               */
+
+        struct
+        {
+            __IOM uint32_t GAFLIDM  : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field                       */
+            __IOM uint32_t GAFLIFL1 : 1;  /*!< [29..29] Global Acceptance Filter List Information Label 1                */
+            __IOM uint32_t GAFLRTRM : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Mask                     */
+            __IOM uint32_t GAFLIDEM : 1;  /*!< [31..31] Global Acceptance Filter List IDE Mask                           */
+        } M_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P0;               /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers          */
+
+        struct
+        {
+            __IOM uint32_t GAFLDLC  : 4; /*!< [3..0] Global Acceptance Filter List DLC Field                            */
+            uint32_t                : 3;
+            __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0                  */
+            __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction
+                                          *   Pointer                                                                   */
+            uint32_t               : 2;
+            __IOM uint32_t GAFLRMV : 1;  /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid            */
+            __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field                      */
+        } P0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t P1;              /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers          */
+
+        struct
+        {
+            __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer               */
+            uint32_t               : 23;
+        } P1_b;
+    };
+} R_CANFD_CFDGAFL_Type;                 /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List)
+ */
+typedef struct
+{
+    union
+    {
+        __IM uint32_t ACC0;            /*!< (@ 0x00000000) Channel TX History List Access Registers 0                 */
+
+        struct
+        {
+            __IM uint32_t BT   : 3;    /*!< [2..0] Buffer Type                                                        */
+            __IM uint32_t BN   : 7;    /*!< [9..3] Buffer No.                                                         */
+            uint32_t           : 6;
+            __IM uint32_t TMTS : 16;   /*!< [31..16] Transmit Timestamp                                               */
+        } ACC0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ACC1;           /*!< (@ 0x00000004) Channel TX History List Access Registers 1                 */
+
+        struct
+        {
+            __IM uint32_t TID  : 16;   /*!< [15..0] Transmit ID                                                       */
+            __IM uint32_t TIFL : 2;    /*!< [17..16] Transmit Information Label                                       */
+            uint32_t           : 14;
+        } ACC1_b;
+    };
+} R_CANFD_CFDTHL_Type;                 /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IM uint32_t ID;              /*!< (@ 0x00000000) RX FIFO Access ID Register                                 */
+
+        struct
+        {
+            __IM uint32_t RFID  : 29;  /*!< [28..0] RX FIFO Buffer ID Field                                           */
+            uint32_t            : 1;
+            __IM uint32_t RFRTR : 1;   /*!< [30..30] RX FIFO Buffer RTR Frame                                         */
+            __IM uint32_t RFIDE : 1;   /*!< [31..31] RX FIFO Buffer IDE Bit                                           */
+        } ID_b;
+    };
+
+    union
+    {
+        __IM uint32_t PTR;             /*!< (@ 0x00000004) RX FIFO Access Pointer Register                            */
+
+        struct
+        {
+            __IM uint32_t RFTS  : 16;  /*!< [15..0] RX FIFO Timestamp Field                                           */
+            uint32_t            : 12;
+            __IM uint32_t RFDLC : 4;   /*!< [31..28] RX FIFO Buffer DLC Field                                         */
+        } PTR_b;
+    };
+
+    union
+    {
+        __IM uint32_t FDSTS;           /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register                      */
+
+        struct
+        {
+            __IM uint32_t RFESI : 1;   /*!< [0..0] Error State Indicator bit                                          */
+            __IM uint32_t RFBRS : 1;   /*!< [1..1] Bit Rate Switch bit                                                */
+            __IM uint32_t RFFDF : 1;   /*!< [2..2] CAN FD Format bit                                                  */
+            uint32_t            : 5;
+            __IM uint32_t RFIFL : 2;   /*!< [9..8] RX FIFO Buffer Information Label Field                             */
+            uint32_t            : 6;
+            __IM uint32_t RFPTR : 16;  /*!< [31..16] RX FIFO Buffer Pointer Field                                     */
+        } FDSTS_b;
+    };
+
+    union
+    {
+        __IM uint8_t DF[64];           /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers                        */
+
+        struct
+        {
+            __IM uint8_t RFDB : 8;     /*!< [7..0] RX FIFO Buffer Data Byte                                           */
+        } DF_b[64];
+    };
+} R_CANFD_CFDRF_Type;                  /*!< Size = 76 (0x4c)                                                          */
+
+/**
+ * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t ID;             /*!< (@ 0x00000000) Common FIFO Access ID Register                             */
+
+        struct
+        {
+            __IOM uint32_t CFID  : 29; /*!< [28..0] Common FIFO Buffer ID Field                                       */
+            uint32_t             : 1;
+            __IOM uint32_t CFRTR : 1;  /*!< [30..30] Common FIFO Buffer RTR Frame                                     */
+            __IOM uint32_t CFIDE : 1;  /*!< [31..31] Common FIFO Buffer IDE Bit                                       */
+        } ID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTR;            /*!< (@ 0x00000004) Common FIFO Access Pointer Register                        */
+
+        struct
+        {
+            __IOM uint32_t CFTS  : 16; /*!< [15..0] Common FIFO Timestamp Field                                       */
+            uint32_t             : 12;
+            __IOM uint32_t CFDLC : 4;  /*!< [31..28] Common FIFO Buffer DLC Field                                     */
+        } PTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDSTS;          /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register                  */
+
+        struct
+        {
+            __IOM uint32_t CFESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
+            __IOM uint32_t CFBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
+            __IOM uint32_t CFFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
+            uint32_t             : 5;
+            __IOM uint32_t CFIFL : 2;  /*!< [9..8] Common FIFO Buffer Information Label Field                         */
+            uint32_t             : 6;
+            __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field                                 */
+        } FDSTS_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DF[64];          /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers                    */
+
+        struct
+        {
+            __IOM uint8_t CFDB : 8;    /*!< [7..0] Common FIFO Buffer Data Byte                                       */
+        } DF_b[64];
+    };
+} R_CANFD_CFDCF_Type;                  /*!< Size = 76 (0x4c)                                                          */
+
+/**
+ * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t ID;             /*!< (@ 0x00000000) TX Message Buffer ID Register                              */
+
+        struct
+        {
+            __IOM uint32_t TMID  : 29; /*!< [28..0] TX Message Buffer ID Field                                        */
+            uint32_t             : 1;
+            __IOM uint32_t TMRTR : 1;  /*!< [30..30] TX Message Buffer RTR Frame                                      */
+            __IOM uint32_t TMIDE : 1;  /*!< [31..31] TX Message Buffer IDE Bit                                        */
+        } ID_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PTR;            /*!< (@ 0x00000004) TX Message Buffer Pointer Register                         */
+
+        struct
+        {
+            __IOM uint32_t TMTS  : 16; /*!< [15..0] TX Message Buffer Timestamp Field                                 */
+            uint32_t             : 12;
+            __IOM uint32_t TMDLC : 4;  /*!< [31..28] TX Message Buffer DLC Field                                      */
+        } PTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register                  */
+
+        struct
+        {
+            __IOM uint32_t TMESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
+            __IOM uint32_t TMBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
+            __IOM uint32_t TMFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
+            uint32_t             : 5;
+            __IOM uint32_t TMIFL : 2;  /*!< [9..8] TX Message Buffer Information Label Field                          */
+            uint32_t             : 6;
+            __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field                                  */
+        } FDCTR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DF[64];          /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers                     */
+
+        struct
+        {
+            __IOM uint8_t TMDB : 8;    /*!< [7..0] TX Message Buffer Data Byte                                        */
+        } DF_b[64];
+    };
+} R_CANFD_CFDTM_Type;                  /*!< Size = 76 (0x4c)                                                          */
+
+/**
+ * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IM uint32_t ID;              /*!< (@ 0x00000000) RX Message Buffer ID Register                              */
+
+        struct
+        {
+            __IM uint32_t RMID  : 29;  /*!< [28..0] RX Message Buffer ID Field                                        */
+            uint32_t            : 1;
+            __IM uint32_t RMRTR : 1;   /*!< [30..30] RX Message Buffer RTR Frame                                      */
+            __IM uint32_t RMIDE : 1;   /*!< [31..31] RX Message Buffer IDE Bit                                        */
+        } ID_b;
+    };
+
+    union
+    {
+        __IM uint32_t PTR;             /*!< (@ 0x00000004) RX Message Buffer Pointer Register                         */
+
+        struct
+        {
+            __IM uint32_t RMTS  : 16;  /*!< [15..0] RX Message Buffer Timestamp Field                                 */
+            uint32_t            : 12;
+            __IM uint32_t RMDLC : 4;   /*!< [31..28] RX Message Buffer DLC Field                                      */
+        } PTR_b;
+    };
+
+    union
+    {
+        __IM uint32_t FDSTS;           /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register                   */
+
+        struct
+        {
+            __IM uint32_t RMESI : 1;   /*!< [0..0] Error State Indicator bit                                          */
+            __IM uint32_t RMBRS : 1;   /*!< [1..1] Bit Rate Switch bit                                                */
+            __IM uint32_t RMFDF : 1;   /*!< [2..2] CAN FD Format bit                                                  */
+            uint32_t            : 5;
+            __IM uint32_t RMIFL : 2;   /*!< [9..8] RX Message Buffer Information Label Field                          */
+            uint32_t            : 6;
+            __IM uint32_t RMPTR : 16;  /*!< [31..16] RX Message Buffer Pointer Field                                  */
+        } FDSTS_b;
+    };
+
+    union
+    {
+        __IM uint8_t DF[64];           /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers                     */
+
+        struct
+        {
+            __IM uint8_t RMDB : 8;     /*!< [7..0] RX Message Buffer Data Byte                                        */
+        } DF_b[64];
+    };
+} R_CANFD_CFDRM_RM_Type;               /*!< Size = 76 (0x4c)                                                          */
+
+/**
+ * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters)
+ */
+typedef struct
+{
+    __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers                         */
+    __IM uint32_t               RESERVED[104];
+} R_CANFD_CFDRM_Type;                  /*!< Size = 1024 (0x400)                                                       */
+
+/**
+ * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t BY;              /*!< (@ 0x00000000) Event Link Software Event Generation Register              */
+
+        struct
+        {
+            __OM uint8_t SEG : 1;      /*!< [0..0] Software Event Generation                                          */
+            uint8_t          : 5;
+            __IOM uint8_t WE : 1;      /*!< [6..6] SEG Bit Write Enable                                               */
+            __OM uint8_t  WI : 1;      /*!< [7..7] ELSEGR Register Write Disable                                      */
+        } BY_b;
+    };
+    __IM uint8_t RESERVED;
+} R_ELC_ELSEGR_Type;                   /*!< Size = 2 (0x2)                                                            */
+
+/**
+ * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22])
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t HA;             /*!< (@ 0x00000000) Event Link Setting Register                                */
+
+        struct
+        {
+            __IOM uint16_t ELS : 9;    /*!< [8..0] Event Link Select                                                  */
+            uint16_t           : 7;
+        } HA_b;
+    };
+    __IM uint16_t RESERVED;
+} R_ELC_ELSR_Type;                     /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_IIC0_SAR [SAR] (Slave Address Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t L;               /*!< (@ 0x00000000) Slave Address Register L                                   */
+
+        struct
+        {
+            __IOM uint8_t SVA : 8;     /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit
+                                        *   Address = { SVA9,SVA8,SVA[7:0] }                                          */
+        } L_b;
+    };
+
+    union
+    {
+        __IOM uint8_t U;               /*!< (@ 0x00000001) Slave Address Register U                                   */
+
+        struct
+        {
+            __IOM uint8_t FS   : 1;    /*!< [0..0] 7-Bit/10-Bit Address Format Selection                              */
+            __IOM uint8_t SVA8 : 1;    /*!< [1..1] 10-Bit Address(bit8)                                               */
+            __IOM uint8_t SVA9 : 1;    /*!< [2..2] 10-Bit Address(bit9)                                               */
+            uint8_t            : 5;
+        } U_b;
+    };
+} R_IIC0_SAR_Type;                     /*!< Size = 2 (0x2)                                                            */
+
+/**
+ * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t OAD;            /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
+            uint16_t           : 7;
+            __OM uint16_t KEY  : 8;    /*!< [15..8] Write Keyword The data written to these bits are not
+                                        *   stored.                                                                   */
+        } OAD_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t CTL;            /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register              */
+
+        struct
+        {
+            __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable                                       */
+            uint16_t              : 7;
+            __IOM uint16_t ERROR  : 1; /*!< [8..8] Stack Pointer Monitor Error Flag                                   */
+            uint16_t              : 7;
+        } CTL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PT;              /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register                  */
+
+        struct
+        {
+            __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE)           */
+            uint16_t               : 7;
+            __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
+                                         *   stored.                                                                   */
+        } PT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SA;                /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register               */
+
+        struct
+        {
+            __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region
+                                           *   starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF
+                                           *   The low-order 2 bits are fixed to 0.                                      */
+        } SA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EA;                /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register                 */
+
+        struct
+        {
+            __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region
+                                           *   starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF
+                                           *   The low-order 2 bits are fixed to 1.                                      */
+        } EA_b;
+    };
+} R_MPU_SPMON_SP_Type;                    /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects)
+ */
+typedef struct
+{
+    union
+    {
+        union
+        {
+            __IOM uint32_t PmnPFS;        /*!< (@ 0x00000000) Pin Function Control Register                              */
+
+            struct
+            {
+                __IOM uint32_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
+                __IM uint32_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
+                __IOM uint32_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
+                uint32_t             : 1;
+                __IOM uint32_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
+                __IOM uint32_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
+                __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
+                uint32_t             : 3;
+                __IOM uint32_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
+                __IOM uint32_t EOFR  : 2; /*!< [13..12] Event on Falling/Rising                                          */
+                __IOM uint32_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
+                __IOM uint32_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
+                __IOM uint32_t PMR   : 1; /*!< [16..16] Port Mode Control                                                */
+                uint32_t             : 7;
+                __IOM uint32_t PSEL  : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral
+                                           *   function. For individual pin functions, see the MPC table                 */
+                uint32_t : 3;
+            } PmnPFS_b;
+        };
+
+        struct
+        {
+            union
+            {
+                struct
+                {
+                    __IM uint16_t RESERVED;
+
+                    union
+                    {
+                        __IOM uint16_t PmnPFS_HA;     /*!< (@ 0x00000002) Pin Function Control Register                              */
+
+                        struct
+                        {
+                            __IOM uint16_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
+                            __IM uint16_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
+                            __IOM uint16_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
+                            uint16_t             : 1;
+                            __IOM uint16_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
+                            __IOM uint16_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
+                            __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
+                            uint16_t             : 3;
+                            __IOM uint16_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
+                            __IOM uint16_t EOFR  : 2; /*!< [13..12] Event on Falling/Rising                                          */
+                            __IOM uint16_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
+                            __IOM uint16_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
+                        } PmnPFS_HA_b;
+                    };
+                };
+
+                struct
+                {
+                    __IM uint16_t RESERVED1;
+                    __IM uint8_t  RESERVED2;
+
+                    union
+                    {
+                        __IOM uint8_t PmnPFS_BY;     /*!< (@ 0x00000003) Pin Function Control Register                              */
+
+                        struct
+                        {
+                            __IOM uint8_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
+                            __IM uint8_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
+                            __IOM uint8_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
+                            uint8_t             : 1;
+                            __IOM uint8_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
+                            __IOM uint8_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
+                            __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
+                            uint8_t             : 1;
+                        } PmnPFS_BY_b;
+                    };
+                };
+            };
+        };
+    };
+} R_PFS_PORT_PIN_Type;                 /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_PFS_PORT [PORT] (Port [0..14])
+ */
+typedef struct
+{
+    __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects                                       */
+} R_PFS_PORT_Type;                     /*!< Size = 64 (0x40)                                                          */
+
+/**
+ * @brief R_PFS_VLSEL [VLSEL] (VLSEL)
+ */
+typedef struct
+{
+    __IM uint8_t RESERVED[389];
+
+    union
+    {
+        __IOM uint8_t VL1SEL;          /*!< (@ 0x00000185) VL1 Select Control Register                                */
+
+        struct
+        {
+            __IOM uint8_t SELVL : 1;   /*!< [0..0] VL1 Voltage Connection Switching Control                           */
+            uint8_t             : 7;
+        } VL1SEL_b;
+    };
+} R_PFS_VLSEL_Type;                    /*!< Size = 390 (0x186)                                                        */
+
+/**
+ * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register)
+ */
+typedef struct
+{
+    __IOM uint16_t PMSAR;              /*!< (@ 0x00000000) Port Security Attribution Register                         */
+} R_PMISC_PMSAR_Type;                  /*!< Size = 2 (0x2)                                                            */
+
+/**
+ * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t RTCCR;           /*!< (@ 0x00000000) Time Capture Control Register                              */
+
+        struct
+        {
+            __IOM uint8_t TCCT : 2;    /*!< [1..0] Time Capture Control                                               */
+            __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
+            uint8_t            : 1;
+            __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
+            uint8_t            : 1;
+            __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
+        } RTCCR_b;
+    };
+    __IM uint8_t RESERVED;
+} R_RTC_RTCCR_Type;                    /*!< Size = 2 (0x2)                                                            */
+
+/**
+ * @brief R_RTC_CP [CP] (Capture registers)
+ */
+typedef struct
+{
+    __IM uint8_t RESERVED[2];
+
+    union
+    {
+        union
+        {
+            __IM uint8_t RSEC;          /*!< (@ 0x00000002) Second Capture Register                                    */
+
+            struct
+            {
+                __IM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Capture Capture value for the ones place of
+                                         *   seconds                                                                   */
+                __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of
+                                         *   seconds                                                                   */
+                uint8_t : 1;
+            } RSEC_b;
+        };
+
+        union
+        {
+            __IM uint8_t BCNT0;           /*!< (@ 0x00000002) BCNT0 Capture Register                                     */
+
+            struct
+            {
+                __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0
+                                           *   value when a time capture event is detected.                              */
+            } BCNT0_b;
+        };
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        union
+        {
+            __IM uint8_t RMIN;          /*!< (@ 0x00000004) Minute Capture Register                                    */
+
+            struct
+            {
+                __IM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
+                                         *   minutes                                                                   */
+                __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of
+                                         *   minutes                                                                   */
+                uint8_t : 1;
+            } RMIN_b;
+        };
+
+        union
+        {
+            __IM uint8_t BCNT1;           /*!< (@ 0x00000004) BCNT1 Capture Register                                     */
+
+            struct
+            {
+                __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1
+                                           *   value when a time capture event is detected.                              */
+            } BCNT1_b;
+        };
+    };
+    __IM uint8_t RESERVED2;
+
+    union
+    {
+        union
+        {
+            __IM uint8_t RHR;          /*!< (@ 0x00000006) Hour Capture Register                                      */
+
+            struct
+            {
+                __IM uint8_t HR1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
+                                        *   minutes                                                                   */
+                __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of
+                                        *   minutes                                                                   */
+                __IM uint8_t PM : 1;   /*!< [6..6] A.m./p.m. select for time counter setting.                         */
+                uint8_t         : 1;
+            } RHR_b;
+        };
+
+        union
+        {
+            __IM uint8_t BCNT2;           /*!< (@ 0x00000006) BCNT2 Capture Register                                     */
+
+            struct
+            {
+                __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2
+                                           *   value when a time capture event is detected.                              */
+            } BCNT2_b;
+        };
+    };
+    __IM uint8_t RESERVED3[3];
+
+    union
+    {
+        union
+        {
+            __IM uint8_t RDAY;           /*!< (@ 0x0000000A) Date Capture Register                                      */
+
+            struct
+            {
+                __IM uint8_t DATE1  : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes          */
+                __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes         */
+                uint8_t             : 2;
+            } RDAY_b;
+        };
+
+        union
+        {
+            __IM uint8_t BCNT3;           /*!< (@ 0x0000000A) BCNT3 Capture Register                                     */
+
+            struct
+            {
+                __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3
+                                           *   value when a time capture event is detected.                              */
+            } BCNT3_b;
+        };
+    };
+    __IM uint8_t RESERVED4;
+
+    union
+    {
+        __IM uint8_t RMON;             /*!< (@ 0x0000000C) Month Capture Register                                     */
+
+        struct
+        {
+            __IM uint8_t MON1  : 4;    /*!< [3..0] 1-Month Capture Capture value for the ones place of months         */
+            __IM uint8_t MON10 : 1;    /*!< [4..4] 10-Month Capture Capture value for the tens place of
+                                        *   months                                                                    */
+            uint8_t : 3;
+        } RMON_b;
+    };
+    __IM uint8_t RESERVED5[3];
+} R_RTC_CP_Type;                       /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t E;              /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register                   */
+
+        struct
+        {
+            uint16_t             : 8;
+            __IOM uint16_t TRCLR : 1;  /*!< [8..8] Transaction Counter Clear                                          */
+            __IOM uint16_t TRENB : 1;  /*!< [9..9] Transaction Counter Enable                                         */
+            uint16_t             : 6;
+        } E_b;
+    };
+
+    union
+    {
+        __IOM uint16_t N;               /*!< (@ 0x00000002) Pipe Transaction Counter Register                          */
+
+        struct
+        {
+            __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter                                               */
+        } N_b;
+    };
+} R_USB_FS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
+            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
+            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
+            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
+            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
+            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
+        } AGTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
+            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
+            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
+            uint8_t              : 1;
+        } AGTMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+                                        *   ratio                                                                     */
+            uint8_t           : 4;
+            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
+        } AGTMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+                                        *   mode.                                                                     */
+            uint8_t             : 1;
+            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
+            uint8_t             : 1;
+            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
+            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
+        } AGTIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
+            uint8_t            : 5;
+        } AGTISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
+
+        struct
+        {
+            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
+            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
+            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
+            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
+            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
+            uint8_t              : 1;
+        } AGTCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_b;
+    };
+} R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
+
+        struct
+        {
+            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IM uint16_t                 RESERVED;
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
+} R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
+
+        struct
+        {
+            __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
+} R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
+
+/** @} */ /* End of group Device_Peripheral_clusters */
+
+/* =========================================================================================================================== */
+/* ================                            Device Specific Peripheral Section                             ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_peripherals
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ADC0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief A/D Converter (R_ADC0)
+ */
+
+typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure                                           */
+{
+    union
+    {
+        __IOM uint16_t ADCSR;          /*!< (@ 0x00000000) A/D Control Register                                       */
+
+        struct
+        {
+            __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog
+                                        *   input channel for double triggered operation. The setting
+                                        *   is only effective while double trigger mode is selected.                  */
+            uint16_t              : 1;
+            __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable                                  */
+            __IOM uint16_t DBLE   : 1; /*!< [7..7] Double Trigger Mode Select                                         */
+            __IOM uint16_t EXTRG  : 1; /*!< [8..8] Trigger Select                                                     */
+            __IOM uint16_t TRGE   : 1; /*!< [9..9] Trigger Start Enable                                               */
+            __IOM uint16_t ADHSC  : 1; /*!< [10..10] A/D Conversion Operation Mode Select                             */
+            uint16_t              : 1;
+            __IOM uint16_t ADIE   : 1; /*!< [12..12] Scan End Interrupt Enable                                        */
+            __IOM uint16_t ADCS   : 2; /*!< [14..13] Scan Mode Select                                                 */
+            __IOM uint16_t ADST   : 1; /*!< [15..15] A/D Conversion Start                                             */
+        } ADCSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADREF;           /*!< (@ 0x00000002) A/D status register                                        */
+
+        struct
+        {
+            __IOM uint8_t ADF : 1;     /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes
+                                        *   '1' while scanning.                                                       */
+            uint8_t              : 6;
+            __IM uint8_t ADSCACT : 1;  /*!< [7..7] Scanning status bit                                                */
+        } ADREF_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADEXREF;         /*!< (@ 0x00000003) A/D enhancing status register                              */
+
+        struct
+        {
+            __IOM uint8_t GBADF : 1;   /*!< [0..0] Group B scanning end flag bit.                                     */
+            uint8_t             : 7;
+        } ADEXREF_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADANSA[2];      /*!< (@ 0x00000004) A/D Channel Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t ANSA0  : 1; /*!< [0..0] AN Input Select                                                    */
+            __IOM uint16_t ANSA1  : 1; /*!< [1..1] AN Input Select                                                    */
+            __IOM uint16_t ANSA2  : 1; /*!< [2..2] AN Input Select                                                    */
+            __IOM uint16_t ANSA3  : 1; /*!< [3..3] AN Input Select                                                    */
+            __IOM uint16_t ANSA4  : 1; /*!< [4..4] AN Input Select                                                    */
+            __IOM uint16_t ANSA5  : 1; /*!< [5..5] AN Input Select                                                    */
+            __IOM uint16_t ANSA6  : 1; /*!< [6..6] AN Input Select                                                    */
+            __IOM uint16_t ANSA7  : 1; /*!< [7..7] AN Input Select                                                    */
+            __IOM uint16_t ANSA8  : 1; /*!< [8..8] AN Input Select                                                    */
+            __IOM uint16_t ANSA9  : 1; /*!< [9..9] AN Input Select                                                    */
+            __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select                                                  */
+            __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select                                                  */
+            __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select                                                  */
+            __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select                                                  */
+            __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select                                                  */
+            __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select                                                  */
+        } ADANSA_b[2];
+    };
+
+    union
+    {
+        __IOM uint16_t ADADS[2];       /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel
+                                        *                  Select Register                                            */
+
+        struct
+        {
+            __IOM uint16_t ADS0  : 1;  /*!< [0..0] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS1  : 1;  /*!< [1..1] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS2  : 1;  /*!< [2..2] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS3  : 1;  /*!< [3..3] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS4  : 1;  /*!< [4..4] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS5  : 1;  /*!< [5..5] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS6  : 1;  /*!< [6..6] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS7  : 1;  /*!< [7..7] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS8  : 1;  /*!< [8..8] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS9  : 1;  /*!< [9..9] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS10 : 1;  /*!< [10..10] A/D-Converted Value Addition/Average Channel Select              */
+            __IOM uint16_t ADS11 : 1;  /*!< [11..11] A/D-Converted Value Addition/Average Channel Select              */
+            __IOM uint16_t ADS12 : 1;  /*!< [12..12] A/D-Converted Value Addition/Average Channel Select              */
+            __IOM uint16_t ADS13 : 1;  /*!< [13..13] A/D-Converted Value Addition/Average Channel Select              */
+            __IOM uint16_t ADS14 : 1;  /*!< [14..14] A/D-Converted Value Addition/Average Channel Select              */
+            __IOM uint16_t ADS15 : 1;  /*!< [15..15] A/D-Converted Value Addition/Average Channel Select              */
+        } ADADS_b[2];
+    };
+
+    union
+    {
+        __IOM uint8_t ADADC;           /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t ADC : 3;     /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid
+                                        *   at the only setting of ADC[2:0] bits = 001b or 011b. When
+                                        *   average mode is selected by setting the ADADC.AVEE bit
+                                        *   to 1, do not set the addition count to three times (ADADC.ADC[2:0]
+                                        *   = 010b)                                                                   */
+            uint8_t            : 4;
+            __IOM uint8_t AVEE : 1;    /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected
+                                        *   by setting the ADADC.AVEE bit to 0, set the addition count
+                                        *   to 1, 2, 3, 4 or 16-time conversion. 16-time conversion
+                                        *   can only be used with 12-bit accuracy selected. NOTE: AVEE
+                                        *   bit is valid at the only setting of ADC[2:0] bits = 001b
+                                        *   or 011b. When average mode is selected by setting the ADADC.AVEE
+                                        *   bit to 1, do not set the addition count to three times
+                                        *   (ADADC.ADC[2:0] = 010b)                                                   */
+        } ADADC_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t ADCER;          /*!< (@ 0x0000000E) A/D Control Extended Register                              */
+
+        struct
+        {
+            uint16_t               : 1;
+            __IOM uint16_t ADPRC   : 2; /*!< [2..1] A/D Conversion Accuracy Specify                                    */
+            uint16_t               : 1;
+            __IOM uint16_t DCE     : 1; /*!< [4..4] Discharge Enable                                                   */
+            __IOM uint16_t ACE     : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable                        */
+            uint16_t               : 2;
+            __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select                           */
+            __IOM uint16_t DIAGLD  : 1; /*!< [10..10] Self-Diagnosis Mode Select                                       */
+            __IOM uint16_t DIAGM   : 1; /*!< [11..11] Self-Diagnosis Enable                                            */
+            uint16_t               : 2;
+            __IOM uint16_t ADINV   : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select           */
+            __IOM uint16_t ADRFMT  : 1; /*!< [15..15] A/D Data Register Format Select                                  */
+        } ADCER_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADSTRGR;        /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register               */
+
+        struct
+        {
+            __IOM uint16_t TRSB : 6;   /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect
+                                        *   the A/D conversion start trigger for group B in group scan
+                                        *   mode.                                                                     */
+            uint16_t            : 2;
+            __IOM uint16_t TRSA : 6;   /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion
+                                        *   start trigger in single scan mode and continuous mode.
+                                        *   In group scan mode, the A/D conversion start trigger for
+                                        *   group A is selected.                                                      */
+            uint16_t : 2;
+        } ADSTRGR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADEXICR;        /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register             */
+
+        struct
+        {
+            __IOM uint16_t TSSAD : 1;  /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average
+                                        *   Mode Select                                                               */
+            __IOM uint16_t OCSAD : 1;  /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average
+                                        *   Mode Select                                                               */
+            uint16_t            : 6;
+            __IOM uint16_t TSSA : 1;   /*!< [8..8] Temperature Sensor Output A/D Conversion Select                    */
+            __IOM uint16_t OCSA : 1;   /*!< [9..9] Internal Reference Voltage A/D Conversion Select                   */
+            __IOM uint16_t TSSB : 1;   /*!< [10..10] Temperature Sensor Output A/D Conversion Select for
+                                        *   Group B in group scan mode.                                               */
+            __IOM uint16_t OCSB : 1;   /*!< [11..11] Internal Reference Voltage A/D Conversion Select for
+                                        *   Group B in group scan mode.                                               */
+            uint16_t             : 2;
+            __IOM uint16_t EXSEL : 1;  /*!< [14..14] Extended Analog Input Select                                     */
+            __IOM uint16_t EXOEN : 1;  /*!< [15..15] Extended Analog Output Control                                   */
+        } ADEXICR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADANSB[2];      /*!< (@ 0x00000014) A/D Channel Select Register B                              */
+
+        struct
+        {
+            __IOM uint16_t ANSB0  : 1; /*!< [0..0] AN Input Select                                                    */
+            __IOM uint16_t ANSB1  : 1; /*!< [1..1] AN Input Select                                                    */
+            __IOM uint16_t ANSB2  : 1; /*!< [2..2] AN Input Select                                                    */
+            __IOM uint16_t ANSB3  : 1; /*!< [3..3] AN Input Select                                                    */
+            __IOM uint16_t ANSB4  : 1; /*!< [4..4] AN Input Select                                                    */
+            __IOM uint16_t ANSB5  : 1; /*!< [5..5] AN Input Select                                                    */
+            __IOM uint16_t ANSB6  : 1; /*!< [6..6] AN Input Select                                                    */
+            __IOM uint16_t ANSB7  : 1; /*!< [7..7] AN Input Select                                                    */
+            __IOM uint16_t ANSB8  : 1; /*!< [8..8] AN Input Select                                                    */
+            __IOM uint16_t ANSB9  : 1; /*!< [9..9] AN Input Select                                                    */
+            __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select                                                  */
+            __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select                                                  */
+            __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select                                                  */
+            __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select                                                  */
+            __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select                                                  */
+            __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select                                                  */
+        } ADANSB_b[2];
+    };
+
+    union
+    {
+        __IM uint16_t ADDBLDR;          /*!< (@ 0x00000018) A/D Data Duplication Register                              */
+
+        struct
+        {
+            __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
+                                         *   result of A/D conversion in response to the second trigger
+                                         *   in double trigger mode.                                                   */
+        } ADDBLDR_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADTSDR;          /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register                       */
+
+        struct
+        {
+            __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
+                                        *   A/D conversion result of temperature sensor output.                       */
+        } ADTSDR_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADOCDR;          /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register               */
+
+        struct
+        {
+            __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
+                                        *   A/D result of internal reference voltage.                                 */
+        } ADOCDR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint16_t ADRD_RIGHT;     /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified           */
+
+            struct
+            {
+                __IM uint16_t AD : 14;    /*!< [13..0] A/D-converted value (right-justified)The format for
+                                           *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
+                __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status                                            */
+            } ADRD_RIGHT_b;
+        };
+
+        union
+        {
+            __IM uint16_t ADRD_LEFT;       /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified            */
+
+            struct
+            {
+                __IM uint16_t DIAGST : 2;  /*!< [1..0] Self-Diagnosis Status                                              */
+                __IM uint16_t AD     : 14; /*!< [15..2] A/D-converted value (right-justified)The format for
+                                            *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
+            } ADRD_LEFT_b;
+        };
+    };
+
+    union
+    {
+        __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
+
+        struct
+        {
+            __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
+                                        *   storing the result of A/D conversion.                                     */
+        } ADDR_b[29];
+    };
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+    __IM uint16_t RESERVED3;
+
+    union
+    {
+        __IOM uint8_t ADAMPOFF;        /*!< (@ 0x00000062) A/D RRAMP off state register                               */
+
+        struct
+        {
+            __IOM uint8_t OPOFF : 8;   /*!< [7..0] OPOFF                                                              */
+        } ADAMPOFF_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADTSTPR;         /*!< (@ 0x00000063) A/D Test Protecting Release Register                       */
+
+        struct
+        {
+            __IOM uint8_t PRO  : 1;    /*!< [0..0] Test register protecting bit.                                      */
+            __IOM uint8_t B0WI : 1;    /*!< [1..1] Bit 0 writing permission bit.                                      */
+            uint8_t            : 6;
+        } ADTSTPR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADDDACER;       /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register                        */
+
+        struct
+        {
+            __IOM uint16_t WRION  : 5; /*!< [4..0] WRION                                                              */
+            uint16_t              : 3;
+            __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF                                                            */
+            uint16_t              : 2;
+            __IOM uint16_t ADHS   : 1; /*!< [15..15] ADHS                                                             */
+        } ADDDACER_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADSHCR;         /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register               */
+
+        struct
+        {
+            __IOM uint16_t SSTSH : 8;  /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time
+                                        *   Setting Set the sampling time (4 to 255 states)                           */
+            __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select                               */
+            __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select                               */
+            __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select                             */
+            uint16_t              : 5;
+        } ADSHCR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADEXTSTR;       /*!< (@ 0x00000068) A/D Enhancing Test Register                                */
+
+        struct
+        {
+            __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit
+                                        *   only for channel.                                                         */
+            uint16_t             : 1;
+            __IOM uint16_t SWTST : 2;  /*!< [5..4] Test selection bit for pressure switch.                            */
+            uint16_t             : 2;
+            __IOM uint16_t SHTRM : 2;  /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit
+                                        *   for adjustment to hardening of process.                                   */
+            uint16_t              : 1;
+            __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator
+                                        *   power save bit for A/D hard macro to hardening of process.                */
+            __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim
+                                        *   bit for A/D hard macro to hardening of process.                           */
+            __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim
+                                        *   bit for A/D hard macro to hardening of process.                           */
+        } ADEXTSTR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADTSTRA;           /*!< (@ 0x0000006A) A/D Test Register A                                        */
+
+        struct
+        {
+            __IOM uint16_t ATBUSSEL : 1;  /*!< [0..0] Analog test bus selection bit.                                     */
+            __IOM uint16_t TSTSWREF : 3;  /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit
+                                           *   amplifier test.Refreshing the pressure switch that opens
+                                           *   for the DAC output voltage charge period when the amplifier
+                                           *   of the S&H circuit is tested only for the channel is set.                 */
+            uint16_t            : 1;
+            __IOM uint16_t OCSW : 1;      /*!< [5..5] Internal reference voltage analog switch test control
+                                           *   bit.                                                                      */
+            __IOM uint16_t TSSW : 1;      /*!< [6..6] Temperature sensor output analogue switch test control
+                                           *   bit                                                                       */
+            uint16_t                 : 1;
+            __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog
+                                           *   module Details are described to the bit explanation.                      */
+            __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the
+                                           *   bit explanation.                                                          */
+        } ADTSTRA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADTSTRB;        /*!< (@ 0x0000006C) A/D Test Register B                                        */
+
+        struct
+        {
+            __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It
+                                        *   corresponds to ADVAL 14:0 input of A/D analog module.                     */
+            uint16_t : 1;
+        } ADTSTRB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADTSTRC;         /*!< (@ 0x0000006E) A/D Test Register C                                        */
+
+        struct
+        {
+            __IOM uint16_t ADMD : 8;    /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D
+                                         *   analog module.                                                            */
+            uint16_t               : 4;
+            __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit.              */
+            uint16_t               : 3;
+        } ADTSTRC_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADTSTRD;         /*!< (@ 0x00000070) A/D Test Register D                                        */
+
+        struct
+        {
+            __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It
+                                         *   corresponds to ADVAL 16 input of A/D analog module.                       */
+            uint16_t : 15;
+        } ADTSTRD_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADSWTSTR0;      /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0                 */
+
+        struct
+        {
+            __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit.                                   */
+            __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit.                                   */
+            __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit.                                   */
+            __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit.                                   */
+            __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit.                                   */
+            __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit.                                   */
+            uint16_t              : 10;
+        } ADSWTSTR0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADSWTSTR1;      /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1                 */
+
+        struct
+        {
+            __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit.                                   */
+            __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit.                                   */
+            __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit.                                   */
+            __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit.                                   */
+            __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit.                                   */
+            __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit.                                   */
+            uint16_t              : 10;
+        } ADSWTSTR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADSWTSTR2;        /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2                 */
+
+        struct
+        {
+            __IOM uint16_t EX0SW : 1;    /*!< [0..0] Test control of 0 enhancing input channel switches bit
+                                          *   (ANEX0 switch)                                                            */
+            __IOM uint16_t EX1SW : 1;    /*!< [1..1] Test control of one enhancing input channel switch bit
+                                          *   (ANEX1 switch).                                                           */
+            uint16_t                : 2;
+            __IOM uint16_t SHBYPS0  : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0.                          */
+            __IOM uint16_t SHBYPS1  : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1.                          */
+            __IOM uint16_t SHBYPS2  : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2.                          */
+            uint16_t                : 1;
+            __IOM uint16_t GRP0SW   : 1; /*!< [8..8] Test control of 0 group switches bit.                              */
+            __IOM uint16_t GRP1SW   : 1; /*!< [9..9] Test control of one group switch bit.                              */
+            __IOM uint16_t GRP2SW   : 1; /*!< [10..10] Test control of two group switches bit                           */
+            __IOM uint16_t GRP3SW   : 1; /*!< [11..11] Test control of two group switches bit                           */
+            __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1                */
+            uint16_t                : 3;
+        } ADSWTSTR2_b;
+    };
+    __IM uint16_t RESERVED4;
+
+    union
+    {
+        __IOM uint8_t ADDISCR;         /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register               */
+
+        struct
+        {
+            __IOM uint8_t ADNDIS : 4;  /*!< [3..0] The charging time                                                  */
+            __IOM uint8_t CHARGE : 1;  /*!< [4..4] Selection of Precharge or Discharge                                */
+            uint8_t              : 3;
+        } ADDISCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADSWCR;          /*!< (@ 0x0000007B) A/D Pressure Switch Control Register                       */
+
+        struct
+        {
+            __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing
+                                        *   the pressure switch in A/D analog module is set.                          */
+            uint8_t               : 1;
+            __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting                          */
+            uint8_t               : 1;
+        } ADSWCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADSHMSR;         /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register         */
+
+        struct
+        {
+            __IOM uint8_t SHMD : 1;    /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode
+                                        *   Select                                                                    */
+            uint8_t : 7;
+        } ADSHMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADICR;           /*!< (@ 0x0000007D) A/D Interrupt Control Register                             */
+
+        struct
+        {
+            __IOM uint8_t ADIC : 2;    /*!< [1..0] A/D Interrupt Control                                              */
+            uint8_t            : 6;
+        } ADICR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADACSR;          /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register              */
+
+        struct
+        {
+            uint8_t             : 1;
+            __IOM uint8_t ADSAC : 1;   /*!< [1..1] Successive Approximation Control Setting                           */
+            uint8_t             : 6;
+        } ADACSR_b;
+    };
+    __IM uint8_t RESERVED5;
+
+    union
+    {
+        __IOM uint16_t ADGSPCR;         /*!< (@ 0x00000080) A/D Group Scan Priority Control Register                   */
+
+        struct
+        {
+            __IOM uint16_t PGS : 1;     /*!< [0..0] Group A priority control setting bit.Note: When the PGS
+                                         *   bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be
+                                         *   set to 01b (group scan mode). If the bits are set to any
+                                         *   other values, proper operation is not guaranteed.                         */
+            __IOM uint16_t GBRSCN : 1;  /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved
+                                         *   when PGS = 0.)                                                            */
+            uint16_t               : 6;
+            __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B.                        */
+            uint16_t               : 6;
+            __IOM uint16_t GBRP    : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when
+                                         *   PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit
+                                         *   has been set to 1, single scan is performed continuously
+                                         *   for group B regardless of the setting of the GBRSCN bit.                  */
+        } ADGSPCR_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADGSCS;          /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group
+                                        *                  Scan)                                                      */
+
+        struct
+        {
+            __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan                                     */
+            __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan                                    */
+        } ADGSCS_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADDBLDRA;          /*!< (@ 0x00000084) A/D Data Duplexing Register A                              */
+
+        struct
+        {
+            __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
+                                          *   the result of A/D conversion in response to the respective
+                                          *   triggers during extended operation in double trigger mode.                */
+        } ADDBLDRA_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADDBLDRB;          /*!< (@ 0x00000086) A/D Data Duplexing Register B                              */
+
+        struct
+        {
+            __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
+                                          *   the result of A/D conversion in response to the respective
+                                          *   triggers during extended operation in double trigger mode.                */
+        } ADDBLDRB_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADSER;           /*!< (@ 0x00000088) A/D Sampling Extension Register                            */
+
+        struct
+        {
+            uint8_t             : 7;
+            __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
+        } ADSER_b;
+    };
+    __IM uint8_t RESERVED6;
+
+    union
+    {
+        __IOM uint8_t ADHVREFCNT;      /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage
+                                        *                  Control Register                                           */
+
+        struct
+        {
+            __IOM uint8_t HVSEL : 2;   /*!< [1..0] High-Potential Reference Voltage Select                            */
+            uint8_t             : 2;
+            __IOM uint8_t LVSEL : 1;   /*!< [4..4] Low-Potential Reference Voltage Select                             */
+            uint8_t             : 2;
+            __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
+        } ADHVREFCNT_b;
+    };
+    __IM uint8_t RESERVED7;
+
+    union
+    {
+        __IM uint8_t ADWINMON;         /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IM uint8_t MONCOMB : 1;  /*!< [0..0] Combination result monitorThis bit indicates the combination
+                                        *   result.This bit is valid when both window A operation and
+                                        *   window B operation are enabled.                                           */
+            uint8_t              : 3;
+            __IM uint8_t MONCMPA : 1;  /*!< [4..4] Comparison Result Monitor A                                        */
+            __IM uint8_t MONCMPB : 1;  /*!< [5..5] Comparison Result Monitor B                                        */
+            uint8_t              : 2;
+        } ADWINMON_b;
+    };
+    __IM uint8_t  RESERVED8;
+    __IM uint16_t RESERVED9;
+
+    union
+    {
+        __IOM uint16_t ADCMPCR;        /*!< (@ 0x00000090) A/D Compare Function Control Register                      */
+
+        struct
+        {
+            __IOM uint16_t CMPAB : 2;  /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits
+                                        *   are valid when both window A and window B are enabled (CMPAE
+                                        *   = 1 and CMPBE = 1).                                                       */
+            uint16_t              : 7;
+            __IOM uint16_t CMPBE  : 1; /*!< [9..9] Compare Window B Operation Enable                                  */
+            uint16_t              : 1;
+            __IOM uint16_t CMPAE  : 1; /*!< [11..11] Compare Window A Operation Enable                                */
+            uint16_t              : 1;
+            __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable                                       */
+            __IOM uint16_t WCMPE  : 1; /*!< [14..14] Window Function Setting                                          */
+            __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable                                       */
+        } ADCMPCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADCMPANSER;      /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input
+                                        *                  Select Register                                            */
+
+        struct
+        {
+            __IOM uint8_t CMPTSA : 1;  /*!< [0..0] Temperature sensor output Compare selection bit.                   */
+            __IOM uint8_t CMPOCA : 1;  /*!< [1..1] Internal reference voltage Compare selection bit.                  */
+            uint8_t              : 6;
+        } ADCMPANSER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADCMPLER;        /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input
+                                        *                  Comparison Condition Setting Register                      */
+
+        struct
+        {
+            __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison
+                                        *   Condition Select                                                          */
+            __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition
+                                        *   Select                                                                    */
+            uint8_t : 6;
+        } ADCMPLER_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPANSR[2];     /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select
+                                          *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t CMPCHA0  : 1; /*!< [0..0] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA1  : 1; /*!< [1..1] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA2  : 1; /*!< [2..2] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA3  : 1; /*!< [3..3] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA4  : 1; /*!< [4..4] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA5  : 1; /*!< [5..5] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA6  : 1; /*!< [6..6] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA7  : 1; /*!< [7..7] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA8  : 1; /*!< [8..8] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA9  : 1; /*!< [9..9] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select                                                  */
+            __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select                                                  */
+            __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select                                                  */
+            __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select                                                  */
+            __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select                                                  */
+            __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select                                                  */
+        } ADCMPANSR_b[2];
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPLR[2];        /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition
+                                           *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t CMPLCHA0  : 1; /*!< [0..0] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA1  : 1; /*!< [1..1] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA2  : 1; /*!< [2..2] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA3  : 1; /*!< [3..3] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA4  : 1; /*!< [4..4] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA5  : 1; /*!< [5..5] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA6  : 1; /*!< [6..6] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA7  : 1; /*!< [7..7] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA8  : 1; /*!< [8..8] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA9  : 1; /*!< [9..9] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input                                    */
+            __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input                                    */
+            __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input                                    */
+            __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input                                    */
+            __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input                                    */
+            __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input                                    */
+        } ADCMPLR_b[2];
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPDR0;          /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level
+                                           *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the
+                                           *   compare window A function is used. ADCMPDR0 sets the lower-side
+                                           *   level of window A.                                                        */
+        } ADCMPDR0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPDR1;          /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level
+                                           *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the
+                                           *   compare window A function is used. ADCMPDR1 sets the upper-side
+                                           *   level of window A..                                                       */
+        } ADCMPDR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPSR[2];         /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status
+                                            *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t CMPSTCHA0  : 1; /*!< [0..0] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA1  : 1; /*!< [1..1] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA2  : 1; /*!< [2..2] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA3  : 1; /*!< [3..3] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA4  : 1; /*!< [4..4] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA5  : 1; /*!< [5..5] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA6  : 1; /*!< [6..6] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA7  : 1; /*!< [7..7] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA8  : 1; /*!< [8..8] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA9  : 1; /*!< [9..9] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input                                   */
+            __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input                                   */
+            __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input                                   */
+            __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input                                   */
+            __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input                                   */
+            __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input                                   */
+        } ADCMPSR_b[2];
+    };
+
+    union
+    {
+        __IOM uint8_t ADCMPSER;         /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input
+                                         *                  Channel Status Register                                    */
+
+        struct
+        {
+            __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag
+                                         *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
+                                         *   this bit indicates the temperature sensor output comparison
+                                         *   result. When window A operation is disabled (ADCMPCR.CMPAE
+                                         *   = 0b), comparison conditions for CMPSTTSA are not met any
+                                         *   time.                                                                     */
+            __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag
+                                         *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
+                                         *   this bit indicates the temperature sensor output comparison
+                                         *   result. When window A operation is disabled (ADCMPCR.CMPAE
+                                         *   = 0b), comparison conditions for CMPSTTSA are not met any
+                                         *   time.                                                                     */
+            uint8_t : 6;
+        } ADCMPSER_b;
+    };
+    __IM uint8_t RESERVED10;
+
+    union
+    {
+        __IOM uint8_t ADCMPBNSR;       /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t CMPCHB : 6;  /*!< [5..0] Compare window B channel selection bit.The channel that
+                                        *   compares it on the condition of compare window B is selected.             */
+            uint8_t             : 1;
+            __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
+        } ADCMPBNSR_b;
+    };
+    __IM uint8_t RESERVED11;
+
+    union
+    {
+        __IOM uint16_t ADWINLLB;          /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level
+                                           *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is
+                                           *   used to set the lower level of the window B.                              */
+        } ADWINLLB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADWINULB;          /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level
+                                           *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is
+                                           *   used to set the higher level of the window B.                             */
+        } ADWINULB_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADCMPBSR;        /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register              */
+
+        struct
+        {
+            __IOM uint8_t CMPSTB : 1;  /*!< [0..0] Compare window B flag.It is a status flag that shows
+                                        *   the comparative result of CH (AN000-AN027, temperature
+                                        *   sensor, and internal reference voltage) made the object
+                                        *   of window B relation condition.                                           */
+            uint8_t : 7;
+        } ADCMPBSR_b;
+    };
+    __IM uint8_t  RESERVED12;
+    __IM uint16_t RESERVED13;
+
+    union
+    {
+        __IM uint16_t ADBUF0;          /*!< (@ 0x000000B0) A/D Data Buffer Register 0                                 */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF0_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF1;          /*!< (@ 0x000000B2) A/D Data Buffer Register 1                                 */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF1_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF2;          /*!< (@ 0x000000B4) A/D Data Buffer Register 2                                 */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF2_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF3;          /*!< (@ 0x000000B6) A/D Data Buffer Register 3                                 */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF3_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF4;          /*!< (@ 0x000000B8) A/D Data Buffer Register 4                                 */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF4_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF5;          /*!< (@ 0x000000BA) A/D Data Buffer Register 5                                 */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF5_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF6;          /*!< (@ 0x000000BC) A/D Data Buffer Register 6                                 */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF6_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF7;          /*!< (@ 0x000000BE) A/D Data Buffer Register 7                                 */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF7_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF8;          /*!< (@ 0x000000C0) A/D Data Buffer Register 8                                 */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF8_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF9;          /*!< (@ 0x000000C2) A/D Data Buffer Register 9                                 */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF9_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF10;         /*!< (@ 0x000000C4) A/D Data Buffer Register 10                                */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF10_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF11;         /*!< (@ 0x000000C6) A/D Data Buffer Register 11                                */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF11_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF12;         /*!< (@ 0x000000C8) A/D Data Buffer Register 12                                */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF12_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF13;         /*!< (@ 0x000000CA) A/D Data Buffer Register 13                                */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF13_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF14;         /*!< (@ 0x000000CC) A/D Data Buffer Register 14                                */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF14_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADBUF15;         /*!< (@ 0x000000CE) A/D Data Buffer Register 15                                */
+
+        struct
+        {
+            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
+                                        *   registers that sequentially store all A/D converted values.
+                                        *   The automatic clear function is not applied to these registers.           */
+        } ADBUF15_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADBUFEN;         /*!< (@ 0x000000D0) A/D Data Buffer Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t BUFEN : 1;   /*!< [0..0] Data Buffer Enable                                                 */
+            uint8_t             : 7;
+        } ADBUFEN_b;
+    };
+    __IM uint8_t RESERVED14;
+
+    union
+    {
+        __IOM uint8_t ADBUFPTR;        /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register                           */
+
+        struct
+        {
+            __IM uint8_t BUFPTR : 4;   /*!< [3..0] Data Buffer PointerThese bits indicate the number of
+                                        *   data buffer to which the next A/D converted data is transferred.          */
+            __IM uint8_t PTROVF : 1;   /*!< [4..4] Pointer Overflow Flag                                              */
+            uint8_t             : 3;
+        } ADBUFPTR_b;
+    };
+    __IM uint8_t  RESERVED15;
+    __IM uint32_t RESERVED16[2];
+    __IM uint8_t  RESERVED17;
+
+    union
+    {
+        __IOM uint8_t ADSSTRL;         /*!< (@ 0x000000DD) A/D Sampling State Register L                              */
+
+        struct
+        {
+            __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (AN016-AN027)                                */
+        } ADSSTRL_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADSSTRT;         /*!< (@ 0x000000DE) A/D Sampling State Register T                              */
+
+        struct
+        {
+            __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (temperature sensor output)                  */
+        } ADSSTRT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADSSTRO;         /*!< (@ 0x000000DF) A/D Sampling State Register O                              */
+
+        struct
+        {
+            __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (Internal reference voltage)                 */
+        } ADSSTRO_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADSSTR[16];      /*!< (@ 0x000000E0) A/D Sampling State Registers                               */
+
+        struct
+        {
+            __IOM uint8_t SST : 8;     /*!< [7..0] Sampling time setting                                              */
+        } ADSSTR_b[16];
+    };
+
+    union
+    {
+        __IOM uint16_t ADANIM;         /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register                     */
+
+        struct
+        {
+            __IOM uint16_t ANIM0 : 1;  /*!< [0..0] Analog Channel Input Mode Select                                   */
+            __IOM uint16_t ANIM1 : 1;  /*!< [1..1] Analog Channel Input Mode Select                                   */
+            __IOM uint16_t ANIM2 : 1;  /*!< [2..2] Analog Channel Input Mode Select                                   */
+            __IOM uint16_t ANIM3 : 1;  /*!< [3..3] Analog Channel Input Mode Select                                   */
+            uint16_t             : 12;
+        } ADANIM_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADCALEXE;        /*!< (@ 0x000000F2) A/D Calibration Execution Register                         */
+
+        struct
+        {
+            uint8_t              : 6;
+            __IM uint8_t  CALMON : 1;  /*!< [6..6] Calibration Status Flag                                            */
+            __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
+        } ADCALEXE_b;
+    };
+    __IM uint8_t RESERVED18;
+
+    union
+    {
+        __IOM uint8_t VREFAMPCNT;        /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control
+                                          *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t OLDETEN   : 1; /*!< [0..0] OLDET Enable                                                       */
+            __IOM uint8_t VREFADCG  : 2; /*!< [2..1] VREFADC Output Voltage Control                                     */
+            __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable                                                    */
+            __IOM uint8_t BGREN     : 1; /*!< [4..4] BGR Enable                                                         */
+            uint8_t                 : 2;
+            __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
+        } VREFAMPCNT_b;
+    };
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
+
+    union
+    {
+        __IOM uint16_t ADRD;           /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register                           */
+
+        struct
+        {
+            __IM uint16_t AD : 16;     /*!< [15..0] Converted Value 15 to 0                                           */
+        } ADRD_b;
+    };
+
+    union
+    {
+        __IM uint8_t ADRST;            /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register                        */
+
+        struct
+        {
+            __IM uint8_t DIAGST : 2;   /*!< [1..0] Self-Diagnosis Status                                              */
+            uint8_t             : 6;
+        } ADRST_b;
+    };
+    __IM uint8_t  RESERVED21;
+    __IM uint32_t RESERVED22[41];
+
+    union
+    {
+        __IOM uint16_t ADPGACR;           /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register           */
+
+        struct
+        {
+            __IOM uint16_t P000SEL0  : 1; /*!< [0..0] A through amplifier is enable for PGA P000                         */
+            __IOM uint16_t P000SEL1  : 1; /*!< [1..1] The amplifier passing is enable for PGA P000                       */
+            __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000                                  */
+            __IOM uint16_t P000GEN   : 1; /*!< [3..3] PGA P000 gain setting and enable bit                               */
+            __IOM uint16_t P001SEL0  : 1; /*!< [4..4] A through amplifier is enable for PGA P001                         */
+            __IOM uint16_t P001SEL1  : 1; /*!< [5..5] The amplifier passing is enable for PGA P001                       */
+            __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001                                  */
+            __IOM uint16_t P001GEN   : 1; /*!< [7..7] PGA P001 gain setting and enable bit                               */
+            __IOM uint16_t P002SEL0  : 1; /*!< [8..8] A through amplifier is enable for PGA P002                         */
+            __IOM uint16_t P002SEL1  : 1; /*!< [9..9] The amplifier passing is enable for PGA P002                       */
+            __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002                                */
+            __IOM uint16_t P002GEN   : 1; /*!< [11..11] PGA P002 gain setting and enable bit                             */
+            __IOM uint16_t P003SEL0  : 1; /*!< [12..12] A through amplifier is enable for PGA P003                       */
+            __IOM uint16_t P003SEL1  : 1; /*!< [13..13] The amplifier passing is enable for PGA P003                     */
+            __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003                                */
+            __IOM uint16_t P003GEN   : 1; /*!< [15..15] PGA P003 gain setting and enable bit                             */
+        } ADPGACR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADPGAGS0;         /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting
+                                          *                  Register 0                                                 */
+
+        struct
+        {
+            __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=
+                                          *   b) when the shingle end is input and each PGA P000 is set.
+                                          *   When the differential motion is input, (ADPGSDCR0.P000GEN=1b)
+                                          *   sets the gain magnification when the differential motion
+                                          *   is input by the combination with ADPGSDCR0.P000DG 1:0.                    */
+            __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=
+                                          *   b) when the shingle end is input and each PGA P001 is set.
+                                          *   When the differential motion is input, (ADPGSDCR0.P001GEN=1b)
+                                          *   sets the gain magnification when the differential motion
+                                          *   is input by the combination with ADPGSDCR0.P001DG 1:0.                    */
+            __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of
+                                          *   (ADPGSDCR0.P002GEN=0b) when the shingle end is input and
+                                          *   each PGA P002 is set. When the differential motion is input,
+                                          *   (ADPGSDCR0.P002GEN=1b) sets the gain magnification when
+                                          *   the differential motion is input by the combination with
+                                          *   ADPGSDCR0.P002DG 1:0.                                                     */
+            __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of
+                                          *   (ADPGSDCR0.P003GEN=0b) when the shingle end is input and
+                                          *   each PGA P003 is set. When the differential motion is input,
+                                          *   (ADPGSDCR0.P003GEN=1b) sets the gain magnification when
+                                          *   the differential motion is input by the combination with
+                                          *   ADPGSDCR0.P003DG 1:0.                                                     */
+        } ADPGAGS0_b;
+    };
+    __IM uint32_t RESERVED23[3];
+
+    union
+    {
+        __IOM uint16_t ADPGADCR0;       /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential
+                                         *                  Input Control Register                                     */
+
+        struct
+        {
+            __IOM uint16_t P000DG : 2;  /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these
+                                         *   bits are used, set {P000DEN, P000GEN} to 11b.                             */
+            uint16_t               : 1;
+            __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable                                     */
+            __IOM uint16_t P001DG  : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these
+                                         *   bits are used, set {P001DEN, P001GEN} to 11b.                             */
+            uint16_t               : 1;
+            __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable                                     */
+            __IOM uint16_t P002DG  : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these
+                                         *   bits are used, set {P002DEN, P002GEN} to 11b.                             */
+            uint16_t               : 1;
+            __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable                                   */
+            __IOM uint16_t P003DG  : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these
+                                         *   bits are used, set {P003DEN, P003GEN} to 11b.                             */
+            uint16_t               : 1;
+            __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
+        } ADPGADCR0_b;
+    };
+    __IM uint16_t RESERVED24;
+
+    union
+    {
+        __IOM uint8_t ADPGADBS0;       /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential
+                                        *                  Input Bias Select Register 0                               */
+
+        struct
+        {
+            __IOM uint8_t P0BIAS : 1;  /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage
+                                        *   SelectNOTE: This bit selects the input bias voltage value
+                                        *   when differential inputs are used.                                        */
+            uint8_t : 7;
+        } ADPGADBS0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADPGADBS1;       /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential
+                                        *                  Input Bias Select Register 1                               */
+
+        struct
+        {
+            __IOM uint8_t P3BIAS : 1;  /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE:
+                                        *   This bit selects the input bias voltage value when differential
+                                        *   inputs are used.                                                          */
+            uint8_t : 7;
+        } ADPGADBS1_b;
+    };
+    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED26[10];
+
+    union
+    {
+        __IOM uint32_t ADREFMON;       /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register            */
+
+        struct
+        {
+            __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable                                          */
+            uint32_t              : 13;
+            __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit.                                    */
+            uint32_t              : 12;
+        } ADREFMON_b;
+    };
+} R_ADC0_Type;                         /*!< Size = 484 (0x1e4)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_PSCU                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Peripheral Security Control Unit (R_PSCU)
+ */
+
+typedef struct                         /*!< (@ 0x400E0000) R_PSCU Structure                                           */
+{
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t PSARB;          /*!< (@ 0x00000004) Peripheral Security Attribution Register B                 */
+
+        struct
+        {
+            uint32_t               : 1;
+            __IOM uint32_t PSARB1  : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution               */
+            __IOM uint32_t PSARB2  : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution               */
+            __IOM uint32_t PSARB3  : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution                */
+            uint32_t               : 2;
+            __IM uint32_t  PSARB6  : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution               */
+            __IOM uint32_t PSARB7  : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution               */
+            __IOM uint32_t PSARB8  : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution               */
+            __IOM uint32_t PSARB9  : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution               */
+            uint32_t               : 1;
+            __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution           */
+            __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution           */
+            uint32_t               : 2;
+            __IM uint32_t PSARB15  : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0
+                                         *   bit security attribution                                                  */
+            __IM uint32_t PSARB16  : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution            */
+            uint32_t               : 1;
+            __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution           */
+            __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution           */
+            uint32_t               : 2;
+            __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution            */
+            __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution            */
+            __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution            */
+            __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution            */
+            __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution            */
+            __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution            */
+            __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution            */
+            __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution            */
+            __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution            */
+            __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution            */
+        } PSARB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PSARC;           /*!< (@ 0x00000008) Peripheral Security Attribution Register C                 */
+
+        struct
+        {
+            __IOM uint32_t PSARC0  : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution                */
+            __IOM uint32_t PSARC1  : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution                */
+            uint32_t               : 1;
+            __IOM uint32_t PSARC3  : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution               */
+            uint32_t               : 4;
+            __IOM uint32_t PSARC8  : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution              */
+            uint32_t               : 3;
+            __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution           */
+            __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution             */
+            uint32_t               : 6;
+            __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution             */
+            uint32_t               : 6;
+            __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution          */
+            uint32_t               : 3;
+            __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution            */
+        } PSARC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PSARD;           /*!< (@ 0x0000000C) Peripheral Security Attribution Register D                 */
+
+        struct
+        {
+            __IOM uint32_t PSARD0  : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution               */
+            __IOM uint32_t PSARD1  : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution               */
+            __IOM uint32_t PSARD2  : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution               */
+            __IOM uint32_t PSARD3  : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution               */
+            uint32_t               : 7;
+            __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution            */
+            __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution            */
+            __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution            */
+            __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution            */
+            __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution            */
+            __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution            */
+            uint32_t               : 2;
+            __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution          */
+            __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution          */
+            uint32_t               : 1;
+            __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution             */
+            uint32_t               : 2;
+            __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution         */
+            __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution         */
+            __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution         */
+            __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution         */
+            uint32_t               : 3;
+        } PSARD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PSARE;           /*!< (@ 0x00000010) Peripheral Security Attribution Register E                 */
+
+        struct
+        {
+            __IOM uint32_t PSARE0  : 1; /*!< [0..0] WDT security attribution                                           */
+            __IOM uint32_t PSARE1  : 1; /*!< [1..1] IWDT security attribution                                          */
+            __IOM uint32_t PSARE2  : 1; /*!< [2..2] RTC security attribution                                           */
+            uint32_t               : 11;
+            __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution            */
+            __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution            */
+            uint32_t               : 6;
+            __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution            */
+            __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution            */
+            __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution            */
+            __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution            */
+            __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution            */
+            __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution            */
+            __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution            */
+            __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution            */
+            __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution            */
+            __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution            */
+        } PSARE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSSAR;          /*!< (@ 0x00000014) Module Stop Security Attribution Register                  */
+
+        struct
+        {
+            __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution                       */
+            __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution                       */
+            __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution                        */
+            __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution                        */
+            uint32_t              : 28;
+        } MSSAR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFSAMONA;       /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
+                                        *                  A                                                          */
+
+        struct
+        {
+            uint32_t            : 15;
+            __IOM uint32_t CFS2 : 9;   /*!< [23..15] Code Flash Secure area 2                                         */
+            uint32_t            : 8;
+        } CFSAMONA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFSAMONB;       /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
+                                        *                  B                                                          */
+
+        struct
+        {
+            uint32_t            : 10;
+            __IOM uint32_t CFS1 : 14;  /*!< [23..10] Code Flash Secure area 1                                         */
+            uint32_t            : 8;
+        } CFSAMONB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DFSAMON;        /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register           */
+
+        struct
+        {
+            uint32_t           : 10;
+            __IOM uint32_t DFS : 6;    /*!< [15..10] Data flash Secure area                                           */
+            uint32_t           : 16;
+        } DFSAMON_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SSAMONA;        /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A               */
+
+        struct
+        {
+            uint32_t           : 13;
+            __IOM uint32_t SS2 : 8;    /*!< [20..13] SRAM Secure area 2                                               */
+            uint32_t           : 11;
+        } SSAMONA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SSAMONB;        /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B               */
+
+        struct
+        {
+            uint32_t           : 10;
+            __IOM uint32_t SS1 : 11;   /*!< [20..10] SRAM secure area 1                                               */
+            uint32_t           : 11;
+        } SSAMONB_b;
+    };
+
+    union
+    {
+        __IM uint32_t DLMMON;          /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register         */
+
+        struct
+        {
+            __IM uint32_t DLMMON : 4;  /*!< [3..0] Device Lifecycle Management State Monitor                          */
+            uint32_t             : 28;
+        } DLMMON_b;
+    };
+} R_PSCU_Type;                         /*!< Size = 48 (0x30)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_BUS                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Bus Interface (R_BUS)
+ */
+
+typedef struct                          /*!< (@ 0x40003000) R_BUS Structure                                            */
+{
+    __IOM R_BUS_CSa_Type CSa[8];        /*!< (@ 0x00000000) CS Registers                                               */
+    __IM uint32_t        RESERVED[480];
+    __IOM R_BUS_CSb_Type CSb[8];        /*!< (@ 0x00000800) CS Registers                                               */
+
+    union
+    {
+        __IOM uint16_t CSRECEN;         /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register                */
+
+        struct
+        {
+            __IOM uint16_t RCVEN0  : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN1  : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN2  : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN3  : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN4  : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN5  : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN6  : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN7  : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable                    */
+            __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable                    */
+            __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable                  */
+            __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable                  */
+            __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable                  */
+            __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable                  */
+            __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable                  */
+            __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable                  */
+        } CSRECEN_b;
+    };
+    __IM uint16_t           RESERVED1;
+    __IM uint32_t           RESERVED2[223];
+    __IOM R_BUS_SDRAM_Type  SDRAM;      /*!< (@ 0x00000C00) SDRAM Registers                                            */
+    __IM uint32_t           RESERVED3[235];
+    __IOM R_BUS_BUSM_Type   BUSM[6];    /*!< (@ 0x00001000) Master Bus Control Register Array                          */
+    __IM uint32_t           RESERVED4[58];
+    __IOM R_BUS_BUSS_Type   BUSS[16];   /*!< (@ 0x00001100) Slave Bus Control Register Array                           */
+    __IM uint32_t           RESERVED5[432];
+    __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers                                        */
+} R_BUS_Type;                           /*!< Size = 6320 (0x18b0)                                                      */
+
+/* =========================================================================================================================== */
+/* ================                                           R_CAC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC)
+ */
+
+typedef struct                         /*!< (@ 0x40083600) R_CAC Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t CACR0;           /*!< (@ 0x00000000) CAC Control Register 0                                     */
+
+        struct
+        {
+            __IOM uint8_t CFME : 1;    /*!< [0..0] Clock Frequency Measurement Enable.                                */
+            uint8_t            : 7;
+        } CACR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CACR1;           /*!< (@ 0x00000001) CAC Control Register 1                                     */
+
+        struct
+        {
+            __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable                                            */
+            __IOM uint8_t FMCS    : 3; /*!< [3..1] Measurement Target Clock Select                                    */
+            __IOM uint8_t TCSS    : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select           */
+            __IOM uint8_t EDGES   : 2; /*!< [7..6] Valid Edge Select                                                  */
+        } CACR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CACR2;           /*!< (@ 0x00000002) CAC Control Register 2                                     */
+
+        struct
+        {
+            __IOM uint8_t RPS  : 1;    /*!< [0..0] Reference Signal Select                                            */
+            __IOM uint8_t RSCS : 3;    /*!< [3..1] Measurement Reference Clock Select                                 */
+            __IOM uint8_t RCDS : 2;    /*!< [5..4] Measurement Reference Clock Frequency Division Ratio
+                                        *   Select                                                                    */
+            __IOM uint8_t DFS : 2;     /*!< [7..6] Digital Filter Selection                                           */
+        } CACR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CAICR;           /*!< (@ 0x00000003) CAC Interrupt Control Register                             */
+
+        struct
+        {
+            __IOM uint8_t FERRIE : 1;  /*!< [0..0] Frequency Error Interrupt Request Enable                           */
+            __IOM uint8_t MENDIE : 1;  /*!< [1..1] Measurement End Interrupt Request Enable                           */
+            __IOM uint8_t OVFIE  : 1;  /*!< [2..2] Overflow Interrupt Request Enable                                  */
+            uint8_t              : 1;
+            __OM uint8_t FERRFCL : 1;  /*!< [4..4] FERRF Clear                                                        */
+            __OM uint8_t MENDFCL : 1;  /*!< [5..5] MENDF Clear                                                        */
+            __OM uint8_t OVFFCL  : 1;  /*!< [6..6] OVFF Clear                                                         */
+            uint8_t              : 1;
+        } CAICR_b;
+    };
+
+    union
+    {
+        __IM uint8_t CASTR;            /*!< (@ 0x00000004) CAC Status Register                                        */
+
+        struct
+        {
+            __IM uint8_t FERRF : 1;    /*!< [0..0] Frequency Error Flag                                               */
+            __IM uint8_t MENDF : 1;    /*!< [1..1] Measurement End Flag                                               */
+            __IM uint8_t OVFF  : 1;    /*!< [2..2] Counter Overflow Flag                                              */
+            uint8_t            : 5;
+        } CASTR_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t CAULVR;          /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register                     */
+
+        struct
+        {
+            __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores
+                                         *   the upper-limit value of the frequency.                                   */
+        } CAULVR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t CALLVR;          /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register                     */
+
+        struct
+        {
+            __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores
+                                         *   the lower-limit value of the frequency.                                   */
+        } CALLVR_b;
+    };
+
+    union
+    {
+        __IM uint16_t CACNTBR;          /*!< (@ 0x0000000A) CAC Counter Buffer Register                                */
+
+        struct
+        {
+            __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains
+                                         *   the counter value at the time a valid reference signal
+                                         *   edge is input                                                             */
+        } CACNTBR_b;
+    };
+} R_CAC_Type;                           /*!< Size = 12 (0xc)                                                           */
+
+/* =========================================================================================================================== */
+/* ================                                         R_CANFD0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD0)
+ */
+
+typedef struct                         /*!< (@ 0x400B0000) R_CANFD0 Structure                                         */
+{
+    __IOM R_CANFD_CFDC_Type CFDC[1];   /*!< (@ 0x00000000) Channel Control/Status                                     */
+    __IM uint32_t           RESERVED;
+
+    union
+    {
+        __IOM uint32_t CFDGCFG;        /*!< (@ 0x00000014) Global Configuration Register                              */
+
+        struct
+        {
+            __IOM uint32_t TPRI  : 1;  /*!< [0..0] Transmission Priority                                              */
+            __IOM uint32_t DCE   : 1;  /*!< [1..1] DLC Check Enable                                                   */
+            __IOM uint32_t DRE   : 1;  /*!< [2..2] DLC Replacement Enable                                             */
+            __IOM uint32_t MME   : 1;  /*!< [3..3] Mirror Mode Enable                                                 */
+            __IOM uint32_t DCS   : 1;  /*!< [4..4] Data Link Controller Clock Select                                  */
+            __IOM uint32_t CMPOC : 1;  /*!< [5..5] CAN-FD message Payload overflow configuration                      */
+            uint32_t             : 2;
+            __IOM uint32_t TSP   : 4;  /*!< [11..8] Timestamp Prescaler                                               */
+            __IOM uint32_t TSSS  : 1;  /*!< [12..12] Timestamp Source Select                                          */
+            uint32_t             : 3;
+            __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler                         */
+        } CFDGCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGCTR;         /*!< (@ 0x00000018) Global Control Register                                    */
+
+        struct
+        {
+            __IOM uint32_t GMDC    : 2; /*!< [1..0] Global Mode Control                                                */
+            __IOM uint32_t GSLPR   : 1; /*!< [2..2] Global Sleep Request                                               */
+            uint32_t               : 5;
+            __IOM uint32_t DEIE    : 1; /*!< [8..8] DLC check Interrupt Enable                                         */
+            __IOM uint32_t MEIE    : 1; /*!< [9..9] Message lost Error Interrupt Enable                                */
+            __IOM uint32_t THLEIE  : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable                      */
+            __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable            */
+            uint32_t               : 4;
+            __IOM uint32_t TSRST   : 1; /*!< [16..16] Timestamp Reset                                                  */
+            uint32_t               : 15;
+        } CFDGCTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGSTS;         /*!< (@ 0x0000001C) Global Status Register                                     */
+
+        struct
+        {
+            __IM uint32_t GRSTSTS  : 1; /*!< [0..0] Global Reset Status                                                */
+            __IM uint32_t GHLTSTS  : 1; /*!< [1..1] Global Halt Status                                                 */
+            __IM uint32_t GSLPSTS  : 1; /*!< [2..2] Global Sleep Status                                                */
+            __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation                                          */
+            uint32_t               : 28;
+        } CFDGSTS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGERFL;       /*!< (@ 0x00000020) Global Error Flag Register                                 */
+
+        struct
+        {
+            __IOM uint32_t DEF   : 1;  /*!< [0..0] DLC Error Flag                                                     */
+            __IM uint32_t  MES   : 1;  /*!< [1..1] Message Lost Error Status                                          */
+            __IM uint32_t  THLES : 1;  /*!< [2..2] TX History List Entry Lost Error Status                            */
+            __IOM uint32_t CMPOF : 1;  /*!< [3..3] CAN-FD message payload overflow Flag                               */
+            uint32_t             : 12;
+            __IOM uint32_t EEF0  : 1;  /*!< [16..16] ECC Error Flag for Channel 0                                     */
+            uint32_t             : 15;
+        } CFDGERFL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGTSC;        /*!< (@ 0x00000024) Global Timestamp Counter Register                          */
+
+        struct
+        {
+            __IM uint32_t TS : 16;     /*!< [15..0] Timestamp Value                                                   */
+            uint32_t         : 16;
+        } CFDGTSC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGAFLECTR;    /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register       */
+
+        struct
+        {
+            __IOM uint32_t AFLPN  : 4; /*!< [3..0] Acceptance Filter List Page Number                                 */
+            uint32_t              : 4;
+            __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable                          */
+            uint32_t              : 23;
+        } CFDGAFLECTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGAFLCFG0;    /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register
+                                        *                  0                                                          */
+
+        struct
+        {
+            __IOM uint32_t RNC1 : 9;   /*!< [8..0] Rule Number for Channel 1                                          */
+            uint32_t            : 7;
+            __IOM uint32_t RNC0 : 9;   /*!< [24..16] Rule Number for Channel 0                                        */
+            uint32_t            : 7;
+        } CFDGAFLCFG0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDRMNB;        /*!< (@ 0x00000030) RX Message Buffer Number Register                          */
+
+        struct
+        {
+            __IOM uint32_t NRXMB : 8;  /*!< [7..0] Number of RX Message Buffers                                       */
+            __IOM uint32_t RMPLS : 3;  /*!< [10..8] Reception Message Buffer Payload Data Size                        */
+            uint32_t             : 21;
+        } CFDRMNB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDRMND0;       /*!< (@ 0x00000034) RX Message Buffer New Data Register 0                      */
+
+        struct
+        {
+            __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status                                 */
+        } CFDRMND0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDRMIEC;       /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t RMIE : 32;  /*!< [31..0] RX Message Buffer Interrupt Enable                                */
+        } CFDRMIEC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDRFCC[2];     /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers                  */
+
+        struct
+        {
+            __IOM uint32_t RFE    : 1; /*!< [0..0] RX FIFO Enable                                                     */
+            __IOM uint32_t RFIE   : 1; /*!< [1..1] RX FIFO Interrupt Enable                                           */
+            uint32_t              : 2;
+            __IOM uint32_t RFPLS  : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration                            */
+            uint32_t              : 1;
+            __IOM uint32_t RFDC   : 3; /*!< [10..8] RX FIFO Depth Configuration                                       */
+            uint32_t              : 1;
+            __IOM uint32_t RFIM   : 1; /*!< [12..12] RX FIFO Interrupt Mode                                           */
+            __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value                       */
+            uint32_t              : 16;
+        } CFDRFCC_b[2];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDRFSTS[2];    /*!< (@ 0x00000044) RX FIFO Status Registers                                   */
+
+        struct
+        {
+            __IM uint32_t  RFEMP : 1;  /*!< [0..0] RX FIFO Empty                                                      */
+            __IM uint32_t  RFFLL : 1;  /*!< [1..1] RX FIFO Full                                                       */
+            __IOM uint32_t RFMLT : 1;  /*!< [2..2] RX FIFO Message Lost                                               */
+            __IOM uint32_t RFIF  : 1;  /*!< [3..3] RX FIFO Interrupt Flag                                             */
+            uint32_t             : 4;
+            __IM uint32_t RFMC   : 8;  /*!< [15..8] RX FIFO Message Count                                             */
+            uint32_t             : 16;
+        } CFDRFSTS_b[2];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDRFPCTR[2];   /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers                          */
+
+        struct
+        {
+            __OM uint32_t RFPC : 8;    /*!< [7..0] RX FIFO Pointer Control                                            */
+            uint32_t           : 24;
+        } CFDRFPCTR_b[2];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDCFCC[1];     /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers              */
+
+        struct
+        {
+            __IOM uint32_t CFE    : 1; /*!< [0..0] Common FIFO Enable                                                 */
+            __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable                                    */
+            __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CFPLS  : 3; /*!< [6..4] Common FIFO Payload Data size configuration                        */
+            uint32_t              : 1;
+            __IOM uint32_t CFM    : 2; /*!< [9..8] Common FIFO Mode                                                   */
+            __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select                         */
+            __IOM uint32_t CFITR  : 1; /*!< [11..11] Common FIFO Interval Timer Resolution                            */
+            __IOM uint32_t CFIM   : 1; /*!< [12..12] Common FIFO Interrupt Mode                                       */
+            __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value                   */
+            __IOM uint32_t CFTML  : 5; /*!< [20..16] Common FIFO TX Message Buffer Link                               */
+            __IOM uint32_t CFDC   : 3; /*!< [23..21] Common FIFO Depth Configuration                                  */
+            __IOM uint32_t CFITT  : 8; /*!< [31..24] Common FIFO Interval Transmission Time                           */
+        } CFDCFCC_b[1];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDCFSTS[1];    /*!< (@ 0x00000058) Common FIFO Status Registers                               */
+
+        struct
+        {
+            __IM uint32_t  CFEMP  : 1; /*!< [0..0] Common FIFO Empty                                                  */
+            __IM uint32_t  CFFLL  : 1; /*!< [1..1] Common FIFO Full                                                   */
+            __IOM uint32_t CFMLT  : 1; /*!< [2..2] Common FIFO Message Lost                                           */
+            __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag                                      */
+            __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag                                      */
+            uint32_t              : 3;
+            __IM uint32_t CFMC    : 8; /*!< [15..8] Common FIFO Message Count                                         */
+            uint32_t              : 16;
+        } CFDCFSTS_b[1];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDCFPCTR[1];   /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers                      */
+
+        struct
+        {
+            __OM uint32_t CFPC : 8;    /*!< [7..0] Common FIFO Pointer Control                                        */
+            uint32_t           : 24;
+        } CFDCFPCTR_b[1];
+    };
+
+    union
+    {
+        __IM uint32_t CFDFESTS;        /*!< (@ 0x00000060) FIFO Empty Status Register                                 */
+
+        struct
+        {
+            __IM uint32_t RFXEMP : 2;  /*!< [1..0] RX FIF0 Empty Status                                               */
+            uint32_t             : 6;
+            __IM uint32_t CFXEMP : 1;  /*!< [8..8] Common FIF0 Empty Status                                           */
+            uint32_t             : 23;
+        } CFDFESTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDFFSTS;        /*!< (@ 0x00000064) FIFO Full Status Register                                  */
+
+        struct
+        {
+            __IM uint32_t RFXFLL : 2;  /*!< [1..0] RX FIF0 Full Status                                                */
+            uint32_t             : 6;
+            __IM uint32_t CFXFLL : 1;  /*!< [8..8] Common FIF0 Full Status                                            */
+            uint32_t             : 23;
+        } CFDFFSTS_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDFMSTS;        /*!< (@ 0x00000068) FIFO Message Lost Status Register                          */
+
+        struct
+        {
+            __IM uint32_t RFXMLT : 2;  /*!< [1..0] RX FIFO Msg Lost Status                                            */
+            uint32_t             : 6;
+            __IM uint32_t CFXMLT : 1;  /*!< [8..8] Common FIFO Msg Lost Status                                        */
+            uint32_t             : 23;
+        } CFDFMSTS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDRFISTS;      /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register                     */
+
+        struct
+        {
+            __IM uint32_t RFXIF : 1;   /*!< [0..0] RX FIFO[x] Interrupt Flag Status                                   */
+            uint32_t            : 31;
+        } CFDRFISTS_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CFDTMC[4];       /*!< (@ 0x00000070) TX Message Buffer Control Registers                        */
+
+        struct
+        {
+            __IOM uint8_t TMTR  : 1;   /*!< [0..0] TX Message Buffer Transmission Request                             */
+            __IOM uint8_t TMTAR : 1;   /*!< [1..1] TX Message Buffer Transmission abort Request                       */
+            __IOM uint8_t TMOM  : 1;   /*!< [2..2] TX Message Buffer One-shot Mode                                    */
+            uint8_t             : 5;
+        } CFDTMC_b[4];
+    };
+
+    union
+    {
+        __IOM uint8_t CFDTMSTS[4];     /*!< (@ 0x00000074) TX Message Buffer Status Registers                         */
+
+        struct
+        {
+            __IM uint8_t  TMTSTS : 1;  /*!< [0..0] TX Message Buffer Transmission Status                              */
+            __IOM uint8_t TMTRF  : 2;  /*!< [2..1] TX Message Buffer Transmission Result Flag                         */
+            __IM uint8_t  TMTRM  : 1;  /*!< [3..3] TX Message Buffer Transmission Request Mirrored                    */
+            __IM uint8_t  TMTARM : 1;  /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored              */
+            uint8_t              : 3;
+        } CFDTMSTS_b[4];
+    };
+
+    union
+    {
+        __IM uint32_t CFDTMTRSTS[1];       /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status
+                                            *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status                      */
+            uint32_t                  : 28;
+        } CFDTMTRSTS_b[1];
+    };
+
+    union
+    {
+        __IM uint32_t CFDTMTARSTS[1];       /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request
+                                             *                  Status Register                                            */
+
+        struct
+        {
+            __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status                */
+            uint32_t                   : 28;
+        } CFDTMTARSTS_b[1];
+    };
+
+    union
+    {
+        __IM uint32_t CFDTMTCSTS[1];       /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status
+                                            *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status                   */
+            uint32_t                  : 28;
+        } CFDTMTCSTS_b[1];
+    };
+
+    union
+    {
+        __IM uint32_t CFDTMTASTS[1];       /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register       */
+
+        struct
+        {
+            __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status                        */
+            uint32_t                  : 28;
+        } CFDTMTASTS_b[1];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDTMIEC[1];    /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t TMIEg : 4;  /*!< [3..0] TX Message Buffer Interrupt Enable                                 */
+            uint32_t             : 28;
+        } CFDTMIEC_b[1];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDTXQCC0[1];    /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0               */
+
+        struct
+        {
+            __IOM uint32_t TXQE    : 1; /*!< [0..0] TX Queue Enable                                                    */
+            uint32_t               : 4;
+            __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
+            uint32_t               : 1;
+            __IOM uint32_t TXQIM   : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
+            __IOM uint32_t TXQDC   : 2; /*!< [9..8] TX Queue Depth Configuration                                       */
+            uint32_t               : 22;
+        } CFDTXQCC0_b[1];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDTXQSTS0[1];   /*!< (@ 0x00000090) TX Queue Status Registers 0                                */
+
+        struct
+        {
+            __IM uint32_t  TXQEMP  : 1; /*!< [0..0] TX Queue Empty                                                     */
+            __IM uint32_t  TXQFLL  : 1; /*!< [1..1] TX Queue Full                                                      */
+            __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
+            uint32_t               : 5;
+            __IM uint32_t TXQMC    : 6; /*!< [13..8] TX Queue Message Count                                            */
+            uint32_t               : 18;
+        } CFDTXQSTS0_b[1];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0                       */
+
+        struct
+        {
+            __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
+            uint32_t            : 24;
+        } CFDTXQPCTR0_b[1];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDTHLCC[1];    /*!< (@ 0x00000098) TX History List Configuration / Control Register           */
+
+        struct
+        {
+            __IOM uint32_t THLE   : 1; /*!< [0..0] TX History List Enable                                             */
+            uint32_t              : 7;
+            __IOM uint32_t THLIE  : 1; /*!< [8..8] TX History List Interrupt Enable                                   */
+            __IOM uint32_t THLIM  : 1; /*!< [9..9] TX History List Interrupt Mode                                     */
+            __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable                              */
+            uint32_t              : 21;
+        } CFDTHLCC_b[1];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDTHLSTS[1];   /*!< (@ 0x0000009C) TX History List Status Register                            */
+
+        struct
+        {
+            __IM uint32_t  THLEMP : 1; /*!< [0..0] TX History List Empty                                              */
+            __IM uint32_t  THLFLL : 1; /*!< [1..1] TX History List Full                                               */
+            __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost                                         */
+            __IOM uint32_t THLIF  : 1; /*!< [3..3] TX History List Interrupt Flag                                     */
+            uint32_t              : 4;
+            __IM uint32_t THLMC   : 6; /*!< [13..8] TX History List Message Count                                     */
+            uint32_t              : 18;
+        } CFDTHLSTS_b[1];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDTHLPCTR[1];  /*!< (@ 0x000000A0) TX History List Pointer Control Registers                  */
+
+        struct
+        {
+            __OM uint32_t THLPC : 8;   /*!< [7..0] TX History List Pointer Control                                    */
+            uint32_t            : 24;
+        } CFDTHLPCTR_b[1];
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGTINTSTS0;   /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0                      */
+
+        struct
+        {
+            __IM uint32_t TSIF0  : 1;  /*!< [0..0] TX Successful Interrupt Flag Channel 0                             */
+            __IM uint32_t TAIF0  : 1;  /*!< [1..1] TX Abort Interrupt Flag Channel 0                                  */
+            __IM uint32_t TQIF0  : 1;  /*!< [2..2] TX Queue Interrupt Flag Channel 0                                  */
+            __IM uint32_t CFTIF0 : 1;  /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0                       */
+            __IM uint32_t THIF0  : 1;  /*!< [4..4] TX History List Interrupt Channel 0                                */
+            uint32_t             : 27;
+        } CFDGTINTSTS0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGTSTCFG;     /*!< (@ 0x000000A8) Global Test Configuration Register                         */
+
+        struct
+        {
+            uint32_t             : 16;
+            __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select                                        */
+            uint32_t             : 6;
+        } CFDGTSTCFG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGTSTCTR;     /*!< (@ 0x000000AC) Global Test Control Register                               */
+
+        struct
+        {
+            uint32_t            : 2;
+            __IOM uint32_t RTME : 1;   /*!< [2..2] RAM Test Mode Enable                                               */
+            uint32_t            : 29;
+        } CFDGTSTCTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGFDCFG;      /*!< (@ 0x000000B0) Global FD Configuration register                           */
+
+        struct
+        {
+            __IOM uint32_t RPED   : 1; /*!< [0..0] RES bit Protocol exception disable                                 */
+            uint32_t              : 7;
+            __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration                                    */
+            uint32_t              : 22;
+        } CFDGFDCFG_b;
+    };
+    __IM uint32_t RESERVED1;
+
+    union
+    {
+        __IOM uint32_t CFDGLOCKK;      /*!< (@ 0x000000B8) Global Lock Key Register                                   */
+
+        struct
+        {
+            __OM uint32_t LOCK : 16;   /*!< [15..0] Lock Key                                                          */
+            uint32_t           : 16;
+        } CFDGLOCKK_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t CFDGAFLIGNENT;  /*!< (@ 0x000000C0) Global AFL Ignore Entry Register                           */
+
+        struct
+        {
+            __IOM uint32_t IRN : 5;    /*!< [4..0] Ignore Rule Number                                                 */
+            uint32_t           : 27;
+        } CFDGAFLIGNENT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDGAFLIGNCTR;  /*!< (@ 0x000000C4) Global AFL Ignore Control Register                         */
+
+        struct
+        {
+            __IOM uint32_t IREN : 1;   /*!< [0..0] Ignore Rule Enable                                                 */
+            uint32_t            : 7;
+            __OM uint32_t KEY   : 8;   /*!< [15..8] Key code                                                          */
+            uint32_t            : 16;
+        } CFDGAFLIGNCTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CFDCDTCT;        /*!< (@ 0x000000C8) DMA Transfer Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0                                   */
+            __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1                                   */
+            uint32_t               : 6;
+            __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0                 */
+            uint32_t               : 23;
+        } CFDCDTCT_b;
+    };
+
+    union
+    {
+        __IM uint32_t CFDCDTSTS;         /*!< (@ 0x000000CC) DMA Transfer Status Register                               */
+
+        struct
+        {
+            __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0                                  */
+            __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1                                  */
+            uint32_t                : 6;
+            __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel
+                                          *   0                                                                         */
+            uint32_t : 23;
+        } CFDCDTSTS_b;
+    };
+    __IM uint32_t RESERVED3[2];
+
+    union
+    {
+        __IOM uint32_t CFDGRSTC;       /*!< (@ 0x000000D8) Global SW reset Register                                   */
+
+        struct
+        {
+            __IOM uint32_t SRST : 1;   /*!< [0..0] SW reset                                                           */
+            uint32_t            : 7;
+            __OM uint32_t KEY   : 8;   /*!< [15..8] Key code                                                          */
+            uint32_t            : 16;
+        } CFDGRSTC_b;
+    };
+    __IM uint32_t              RESERVED4[9];
+    __IOM R_CANFD_CFDC2_Type   CFDC2[1];    /*!< (@ 0x00000100) Channel Configuration Registers                            */
+    __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers                    */
+    __IM uint32_t              RESERVED5[24];
+
+    union
+    {
+        __IOM uint32_t CFDRPGACC[64];    /*!< (@ 0x00000280) RAM Test Page Access Registers                             */
+
+        struct
+        {
+            __IOM uint32_t RDTA : 32;    /*!< [31..0] RAM Data Test Access                                              */
+        } CFDRPGACC_b[64];
+    };
+    __IM uint32_t             RESERVED6[104];
+    __IOM R_CANFD_CFDRF_Type  CFDRF[2];  /*!< (@ 0x00000520) RX FIFO Access Registers                                   */
+    __IOM R_CANFD_CFDCF_Type  CFDCF[1];  /*!< (@ 0x000005B8) Common FIFO Access Registers                               */
+    __IOM R_CANFD_CFDTM_Type  CFDTM[4];  /*!< (@ 0x00000604) TX Message Buffer Access Registers                         */
+    __IM uint32_t             RESERVED7[3];
+    __IOM R_CANFD_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List                                    */
+    __IM uint32_t             RESERVED8[118];
+    __IOM R_CANFD_CFDRM_Type  CFDRM[4];  /*!< (@ 0x00000920) RX Message Buffer Access Clusters                          */
+} R_CANFD_Type;                          /*!< Size = 6432 (0x1920)                                                      */
+
+/* =========================================================================================================================== */
+/* ================                                           R_CRC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC)
+ */
+
+typedef struct                         /*!< (@ 0x40108000) R_CRC Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t CRCCR0;          /*!< (@ 0x00000000) CRC Control Register0                                      */
+
+        struct
+        {
+            __IOM uint8_t GPS    : 3;  /*!< [2..0] CRC Generating Polynomial Switching                                */
+            uint8_t              : 3;
+            __IOM uint8_t LMS    : 1;  /*!< [6..6] CRC Calculation Switching                                          */
+            __OM uint8_t  DORCLR : 1;  /*!< [7..7] CRCDOR Register Clear                                              */
+        } CRCCR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CRCCR1;          /*!< (@ 0x00000001) CRC Control Register1                                      */
+
+        struct
+        {
+            uint8_t              : 6;
+            __IOM uint8_t CRCSWR : 1;  /*!< [6..6] Snoop-on-write/read switch bit                                     */
+            __IOM uint8_t CRCSEN : 1;  /*!< [7..7] Snoop enable bit                                                   */
+        } CRCCR1_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CRCDIR;          /*!< (@ 0x00000004) CRC Data Input Register                                    */
+
+            struct
+            {
+                __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C )                 */
+            } CRCDIR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t CRCDIR_BY;         /*!< (@ 0x00000004) CRC Data Input Register (byte access)                      */
+
+            struct
+            {
+                __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT
+                                              *   )                                                                         */
+            } CRCDIR_BY_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CRCDOR;          /*!< (@ 0x00000008) CRC Data Output Register                                   */
+
+            struct
+            {
+                __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C )                */
+            } CRCDOR_b;
+        };
+
+        union
+        {
+            __IOM uint16_t CRCDOR_HA;          /*!< (@ 0x00000008) CRC Data Output Register (halfword access)                 */
+
+            struct
+            {
+                __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT
+                                                *   )                                                                         */
+            } CRCDOR_HA_b;
+        };
+
+        union
+        {
+            __IOM uint8_t CRCDOR_BY;         /*!< (@ 0x00000008) CRC Data Output Register(byte access)                      */
+
+            struct
+            {
+                __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 )                           */
+            } CRCDOR_BY_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint16_t CRCSAR;         /*!< (@ 0x0000000C) Snoop Address Register                                     */
+
+        struct
+        {
+            __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop            */
+            uint16_t             : 2;
+        } CRCSAR_b;
+    };
+    __IM uint16_t RESERVED1;
+} R_CRC_Type;                          /*!< Size = 16 (0x10)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DAC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief D/A Converter (R_DAC)
+ */
+
+typedef struct                         /*!< (@ 0x40171000) R_DAC Structure                                            */
+{
+    union
+    {
+        __IOM uint16_t DADR[2];        /*!< (@ 0x00000000) D/A Data Register                                          */
+
+        struct
+        {
+            __IOM uint16_t DADR : 16;  /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order
+                                        *   4 bits are fixed to 0: right justified format. When DADPR.DPSEL
+                                        *   = 1, the low-order 4 bits are fixed to 0: left justified
+                                        *   format.                                                                   */
+        } DADR_b[2];
+    };
+
+    union
+    {
+        __IOM uint8_t DACR;            /*!< (@ 0x00000004) D/A Control Register                                       */
+
+        struct
+        {
+            uint8_t             : 5;
+            __IOM uint8_t DAE   : 1;   /*!< [5..5] D/A Enable                                                         */
+            __IOM uint8_t DAOE0 : 1;   /*!< [6..6] D/A Output Enable 0                                                */
+            __IOM uint8_t DAOE1 : 1;   /*!< [7..7] D/A Output Enable 0                                                */
+        } DACR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DADPR;           /*!< (@ 0x00000005) DADR0 Format Select Register                               */
+
+        struct
+        {
+            uint8_t             : 7;
+            __IOM uint8_t DPSEL : 1;   /*!< [7..7] DADRm Format Select                                                */
+        } DADPR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DAADSCR;         /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register                 */
+
+        struct
+        {
+            uint8_t              : 7;
+            __IOM uint8_t DAADST : 1;  /*!< [7..7] D/A-A/D Synchronous Conversion                                     */
+        } DAADSCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DAVREFCR;        /*!< (@ 0x00000007) D/A VREF Control Register                                  */
+
+        struct
+        {
+            __IOM uint8_t REF : 3;     /*!< [2..0] D/A Reference Voltage Select                                       */
+            uint8_t           : 5;
+        } DAVREFCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DAAMPCR;         /*!< (@ 0x00000008) D/A Output Amplifier Control Register                      */
+
+        struct
+        {
+            uint8_t              : 6;
+            __IOM uint8_t DAAMP0 : 1;  /*!< [6..6] Amplifier Control                                                  */
+            __IOM uint8_t DAAMP1 : 1;  /*!< [7..7] Amplifier Control                                                  */
+        } DAAMPCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DAPC;            /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register                    */
+
+        struct
+        {
+            __IOM uint8_t PUMPEN : 1;  /*!< [0..0] Charge Pump Enable                                                 */
+            uint8_t              : 7;
+        } DAPC_b;
+    };
+    __IM uint16_t RESERVED[9];
+
+    union
+    {
+        __IOM uint8_t DAASWCR;         /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register          */
+
+        struct
+        {
+            uint8_t              : 6;
+            __IOM uint8_t DAASW0 : 1;  /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure
+                                        *   to wait for stabilization of the output amplifier of D/A
+                                        *   channel 0. When DAASW0 is set to 1, D/A conversion operates,
+                                        *   but the conversion result D/A is not output from channel
+                                        *   0. When the DAASW0 bit is 0, the stabilization wait time
+                                        *   stops, and the D/A conversion result of channel 0 is output
+                                        *   through the output amplifier.                                             */
+            __IOM uint8_t DAASW1 : 1;  /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure
+                                        *   to wait for stabilization of the output amplifier of D/A
+                                        *   channel 1. When DAASW1 is set to 1, D/A conversion operates,
+                                        *   but the conversion result D/A is not output from channel
+                                        *   1. When the DAASW1 bit is 0, the stabilization wait time
+                                        *   stops, and the D/A conversion result of channel 1 is output
+                                        *   through the output amplifier.                                             */
+        } DAASWCR_b;
+    };
+    __IM uint8_t  RESERVED1;
+    __IM uint16_t RESERVED2[2129];
+
+    union
+    {
+        __IOM uint8_t DAADUSR;          /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register                   */
+
+        struct
+        {
+            __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for
+                                         *   D/A and A/D synchronous conversions. Set bit [0] to 1 to
+                                         *   select unit 0 as the target synchronous unit for the MCU.
+                                         *   When setting the DAADSCR.DAADST bit to 1 for synchronous
+                                         *   conversions, select the target unit in this register in
+                                         *   advance. Only set the DAADUSR register while the ADCSR.ADST
+                                         *   bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
+                                         *   is set to 0.                                                              */
+            __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for
+                                         *   D/A and A/D synchronous conversions. Set bit [1] to 1 to
+                                         *   select unit 1 as the target synchronous unit for the MCU.
+                                         *   When setting the DAADSCR.DAADST bit to 1 for synchronous
+                                         *   conversions, select the target unit in this register in
+                                         *   advance. Only set the DAADUSR register while the ADCSR.ADST
+                                         *   bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
+                                         *   is set to 0.                                                              */
+            uint8_t : 6;
+        } DAADUSR_b;
+    };
+    __IM uint8_t  RESERVED3;
+    __IM uint16_t RESERVED4;
+} R_DAC_Type;                          /*!< Size = 4292 (0x10c4)                                                      */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DEBUG                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Debug Function (R_DEBUG)
+ */
+
+typedef struct                         /*!< (@ 0x4001B000) R_DEBUG Structure                                          */
+{
+    union
+    {
+        __IM uint32_t DBGSTR;          /*!< (@ 0x00000000) Debug Status Register                                      */
+
+        struct
+        {
+            uint32_t                   : 28;
+            __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request                                           */
+            __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge                                       */
+            uint32_t                   : 2;
+        } DBGSTR_b;
+    };
+    __IM uint32_t RESERVED[3];
+
+    union
+    {
+        __IOM uint32_t DBGSTOPCR;             /*!< (@ 0x00000010) Debug Stop Control Register                                */
+
+        struct
+        {
+            __IOM uint32_t DBGSTOP_IWDT  : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt                                  */
+            __IOM uint32_t DBGSTOP_WDT   : 1; /*!< [1..1] Mask bit for WDT reset/interrupt                                   */
+            uint32_t                     : 14;
+            __IOM uint32_t DBGSTOP_LVD0  : 1; /*!< [16..16] Mask bit for LVD reset/interupt                                  */
+            __IOM uint32_t DBGSTOP_LVD1  : 1; /*!< [17..17] Mask bit for LVD reset/interupt                                  */
+            __IOM uint32_t DBGSTOP_LVD2  : 1; /*!< [18..18] Mask bit for LVD reset/interupt                                  */
+            uint32_t                     : 5;
+            __IOM uint32_t DBGSTOP_RPER  : 1; /*!< [24..24] Mask bit for SRAM parity error                                   */
+            __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error                                      */
+            uint32_t                     : 5;
+            __IOM uint32_t DBGSTOP_CPER  : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt             */
+        } DBGSTOPCR_b;
+    };
+} R_DEBUG_Type;                               /*!< Size = 20 (0x14)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DMA                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief DMA Controller Common (R_DMA)
+ */
+
+typedef struct                         /*!< (@ 0x40005200) R_DMA Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t DMAST;           /*!< (@ 0x00000000) DMAC Module Activation Register                            */
+
+        struct
+        {
+            __IOM uint8_t DMST : 1;    /*!< [0..0] DMAC Operation Enable                                              */
+            uint8_t            : 7;
+        } DMAST_b;
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2[15];
+
+    union
+    {
+        __IOM uint32_t DMECHR;          /*!< (@ 0x00000040) DMAC Error Channel Register                                */
+
+        struct
+        {
+            __IM uint32_t DMECH    : 3; /*!< [2..0] DMAC Error channel                                                 */
+            uint32_t               : 5;
+            __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor                    */
+            uint32_t               : 7;
+            __IOM uint32_t DMESTA  : 1; /*!< [16..16] DMAC Error Status                                                */
+            uint32_t               : 15;
+        } DMECHR_b;
+    };
+    __IM uint32_t RESERVED3[15];
+
+    union
+    {
+        __IOM uint32_t DELSR[8];       /*!< (@ 0x00000080) DMAC Event Link Setting Register                           */
+
+        struct
+        {
+            __IOM uint32_t DELS : 9;   /*!< [8..0] DMAC Event Link Select                                             */
+            uint32_t            : 7;
+            __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
+                                        *   IR flag is prohibited.                                                    */
+            uint32_t : 15;
+        } DELSR_b[8];
+    };
+} R_DMA_Type;                          /*!< Size = 160 (0xa0)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DMAC0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief DMA Controller (R_DMAC0)
+ */
+
+typedef struct                         /*!< (@ 0x40005000) R_DMAC0 Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t DMSAR;          /*!< (@ 0x00000000) DMA Source Address Register                                */
+
+        struct
+        {
+            __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address.                      */
+        } DMSAR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DMDAR;          /*!< (@ 0x00000004) DMA Destination Address Register                           */
+
+        struct
+        {
+            __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address.                 */
+        } DMDAR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DMCRA;           /*!< (@ 0x00000008) DMA Transfer Count Register                                */
+
+        struct
+        {
+            __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count                                      */
+            __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count                                     */
+            uint32_t              : 6;
+        } DMCRA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DMCRB;           /*!< (@ 0x0000000C) DMA Block Transfer Count Register                          */
+
+        struct
+        {
+            __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block
+                                         *   transfer counter.                                                         */
+            __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or
+                                         *   repeat transfer operations.                                               */
+        } DMCRB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DMTMD;          /*!< (@ 0x00000010) DMA Transfer Mode Register                                 */
+
+        struct
+        {
+            __IOM uint16_t DCTG : 2;   /*!< [1..0] Transfer Request Source Select                                     */
+            uint16_t            : 6;
+            __IOM uint16_t SZ   : 2;   /*!< [9..8] Transfer Data Size Select                                          */
+            __IOM uint16_t TKP  : 1;   /*!< [10..10] Transfer Keeping                                                 */
+            uint16_t            : 1;
+            __IOM uint16_t DTS  : 2;   /*!< [13..12] Repeat Area Select                                               */
+            __IOM uint16_t MD   : 2;   /*!< [15..14] Transfer Mode Select                                             */
+        } DMTMD_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t DMINT;           /*!< (@ 0x00000013) DMA Interrupt Setting Register                             */
+
+        struct
+        {
+            __IOM uint8_t DARIE : 1;   /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt
+                                        *   Enable                                                                    */
+            __IOM uint8_t SARIE : 1;   /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt
+                                        *   Enable                                                                    */
+            __IOM uint8_t RPTIE : 1;   /*!< [2..2] Repeat Size End Interrupt Enable                                   */
+            __IOM uint8_t ESIE  : 1;   /*!< [3..3] Transfer Escape End Interrupt Enable                               */
+            __IOM uint8_t DTIE  : 1;   /*!< [4..4] Transfer End Interrupt Enable                                      */
+            uint8_t             : 3;
+        } DMINT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DMAMD;          /*!< (@ 0x00000014) DMA Address Mode Register                                  */
+
+        struct
+        {
+            __IOM uint16_t DARA : 5;   /*!< [4..0] Destination Address Extended Repeat Area Specifies the
+                                        *   extended repeat area on the destination address. For details
+                                        *   on the settings.                                                          */
+            __IOM uint16_t DADR : 1;   /*!< [5..5] Destination Address Update Select After Reload                     */
+            __IOM uint16_t DM   : 2;   /*!< [7..6] Destination Address Update Mode                                    */
+            __IOM uint16_t SARA : 5;   /*!< [12..8] Source Address Extended Repeat Area Specifies the extended
+                                        *   repeat area on the source address. For details on the settings.           */
+            __IOM uint16_t SADR : 1;   /*!< [13..13] Source Address Update Select After Reload                        */
+            __IOM uint16_t SM   : 2;   /*!< [15..14] Source Address Update Mode                                       */
+        } DMAMD_b;
+    };
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint32_t DMOFR;          /*!< (@ 0x00000018) DMA Offset Register                                        */
+
+        struct
+        {
+            __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected
+                                        *   as the address update mode for transfer source or destination.            */
+        } DMOFR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DMCNT;           /*!< (@ 0x0000001C) DMA Transfer Enable Register                               */
+
+        struct
+        {
+            __IOM uint8_t DTE : 1;     /*!< [0..0] DMA Transfer Enable                                                */
+            uint8_t           : 7;
+        } DMCNT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DMREQ;           /*!< (@ 0x0000001D) DMA Software Start Register                                */
+
+        struct
+        {
+            __IOM uint8_t SWREQ : 1;   /*!< [0..0] DMA Software Start                                                 */
+            uint8_t             : 3;
+            __IOM uint8_t CLRS  : 1;   /*!< [4..4] DMA Software Start Bit Auto Clear Select                           */
+            uint8_t             : 3;
+        } DMREQ_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DMSTS;            /*!< (@ 0x0000001E) DMA Status Register                                        */
+
+        struct
+        {
+            __IOM uint8_t ESIF : 1;     /*!< [0..0] Transfer Escape End Interrupt Flag                                 */
+            uint8_t            : 3;
+            __IOM uint8_t DTIF : 1;     /*!< [4..4] Transfer End Interrupt Flag                                        */
+            uint8_t            : 2;
+            __IM uint8_t ACT   : 1;     /*!< [7..7] DMA Active Flag                                                    */
+        } DMSTS_b;
+    };
+    __IM uint8_t   RESERVED2;
+    __IOM uint32_t DMSRR;               /*!< (@ 0x00000020) DMA Source Reload Address Register                         */
+    __IOM uint32_t DMDRR;               /*!< (@ 0x00000024) DMA Destination Reload Address Register                    */
+
+    union
+    {
+        __IOM uint32_t DMSBS;           /*!< (@ 0x00000028) DMA Source Buffer Size Register                            */
+
+        struct
+        {
+            __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
+                                         *   mode                                                                      */
+            __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
+                                         *   mode                                                                      */
+        } DMSBS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DMDBS;           /*!< (@ 0x0000002C) DMA Destination Buffer Size Register                       */
+
+        struct
+        {
+            __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
+                                         *   mode                                                                      */
+            __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
+                                         *   mode                                                                      */
+        } DMDBS_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DMBWR;           /*!< (@ 0x00000030) DMA Bufferable Write Enable Register                       */
+
+        struct
+        {
+            __IOM uint8_t BWE : 1;     /*!< [0..0] Bufferable Write Enable                                            */
+            uint8_t           : 7;
+        } DMBWR_b;
+    };
+    __IM uint8_t  RESERVED3;
+    __IM uint16_t RESERVED4;
+} R_DMAC0_Type;                        /*!< Size = 52 (0x34)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DOC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Data Operation Circuit (R_DOC)
+ */
+
+typedef struct                         /*!< (@ 0x40109000) R_DOC Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t DOCR;            /*!< (@ 0x00000000) DOC Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t OMS     : 2; /*!< [1..0] Operating Mode Select                                              */
+            __IOM uint8_t DCSEL   : 1; /*!< [2..2] Detection Condition Select                                         */
+            uint8_t               : 2;
+            __IM uint8_t  DOPCF   : 1; /*!< [5..5] Data Operation Circuit Flag                                        */
+            __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear                                                        */
+            uint8_t               : 1;
+        } DOCR_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t DODIR;          /*!< (@ 0x00000002) DOC Data Input Register                                    */
+
+        struct
+        {
+            __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for
+                                        *   use in the operations are stored.                                         */
+        } DODIR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DODSR;          /*!< (@ 0x00000004) DOC Data Setting Register                                  */
+
+        struct
+        {
+            __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference
+                                        *   in data comparison mode. This register also stores the
+                                        *   results of operations in data addition and data subtraction
+                                        *   modes.                                                                    */
+        } DODSR_b;
+    };
+} R_DOC_Type;                          /*!< Size = 6 (0x6)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DTC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Data Transfer Controller (R_DTC)
+ */
+
+typedef struct                         /*!< (@ 0x40005400) R_DTC Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t DTCCR;           /*!< (@ 0x00000000) DTC Control Register                                       */
+
+        struct
+        {
+            uint8_t           : 4;
+            __IOM uint8_t RRS : 1;     /*!< [4..4] DTC Transfer Information Read Skip Enable.                         */
+            uint8_t           : 3;
+        } DTCCR_b;
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint32_t DTCVBR;          /*!< (@ 0x00000004) DTC Vector Base Register                                   */
+
+        struct
+        {
+            __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set
+                                         *   in the lower-order 10 bits. These bits are fixed to 0.                    */
+        } DTCVBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t DTCST;           /*!< (@ 0x0000000C) DTC Module Start Register                                  */
+
+        struct
+        {
+            __IOM uint8_t DTCST : 1;   /*!< [0..0] DTC Module Start                                                   */
+            uint8_t             : 7;
+        } DTCST_b;
+    };
+    __IM uint8_t RESERVED3;
+
+    union
+    {
+        __IM uint16_t DTCSTS;          /*!< (@ 0x0000000E) DTC Status Register                                        */
+
+        struct
+        {
+            __IM uint16_t VECN : 8;    /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate
+                                        *   the vector number for the activating source when DTC transfer
+                                        *   is in progress.The value is only valid if DTC transfer
+                                        *   is in progress (the value of the ACT flag is 1)                           */
+            uint16_t          : 7;
+            __IM uint16_t ACT : 1;     /*!< [15..15] DTC Active Flag                                                  */
+        } DTCSTS_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DTCCR_SEC;       /*!< (@ 0x00000010) DTC Control Register for secure Region                     */
+
+        struct
+        {
+            uint8_t            : 4;
+            __IOM uint8_t RRSS : 1;    /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure               */
+            uint8_t            : 3;
+        } DTCCR_SEC_b;
+    };
+    __IM uint8_t   RESERVED4;
+    __IM uint16_t  RESERVED5;
+    __IOM uint32_t DTCVBR_SEC;         /*!< (@ 0x00000014) DTC Vector Base Register for secure Region                 */
+    __IM uint32_t  RESERVED6[2];
+
+    union
+    {
+        __IOM uint32_t DTEVR;          /*!< (@ 0x00000020) DTC Error Vector Register                                  */
+
+        struct
+        {
+            __IM uint32_t DTEV    : 8; /*!< [7..0] DTC Error Vector Number                                            */
+            __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor                                 */
+            uint32_t              : 7;
+            __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag                                            */
+            uint32_t              : 15;
+        } DTEVR_b;
+    };
+} R_DTC_Type;                          /*!< Size = 36 (0x24)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ELC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Event Link Controller (R_ELC)
+ */
+
+typedef struct                         /*!< (@ 0x40082000) R_ELC Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t ELCR;            /*!< (@ 0x00000000) Event Link Controller Register                             */
+
+        struct
+        {
+            uint8_t             : 7;
+            __IOM uint8_t ELCON : 1;   /*!< [7..7] All Event Link Enable                                              */
+        } ELCR_b;
+    };
+    __IM uint8_t            RESERVED;
+    __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register              */
+    __IM uint16_t           RESERVED1[5];
+    __IOM R_ELC_ELSR_Type   ELSR[23];  /*!< (@ 0x00000010) Event Link Setting Register [0..22]                        */
+    __IM uint16_t           RESERVED2[4];
+
+    union
+    {
+        __IOM uint16_t ELCSARA;         /*!< (@ 0x00000074) Event Link Controller Security Attribution Register
+                                         *                  A                                                          */
+
+        struct
+        {
+            __IOM uint16_t ELCR    : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution                 */
+            __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security
+                                         *   Attribution                                                               */
+            __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security
+                                         *   Attribution                                                               */
+            uint16_t : 13;
+        } ELCSARA_b;
+    };
+    __IM uint16_t RESERVED3;
+
+    union
+    {
+        __IOM uint16_t ELCSARB;        /*!< (@ 0x00000078) Event Link Controller Security Attribution Register
+                                        *                  B                                                          */
+
+        struct
+        {
+            __IOM uint16_t ELSR0  : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution                  */
+            __IOM uint16_t ELSR1  : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution                  */
+            __IOM uint16_t ELSR2  : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution                  */
+            __IOM uint16_t ELSR3  : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution                  */
+            __IOM uint16_t ELSR4  : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution                  */
+            __IOM uint16_t ELSR5  : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution                  */
+            __IOM uint16_t ELSR6  : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution                  */
+            __IOM uint16_t ELSR7  : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution                  */
+            __IOM uint16_t ELSR8  : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution                  */
+            __IOM uint16_t ELSR9  : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution                  */
+            __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution               */
+            __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution               */
+            __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution               */
+            __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution               */
+            __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution               */
+            __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution               */
+        } ELCSARB_b;
+    };
+    __IM uint16_t RESERVED4;
+
+    union
+    {
+        __IOM uint16_t ELCSARC;        /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register
+                                        *                  C                                                          */
+
+        struct
+        {
+            __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution                 */
+            __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution                 */
+            __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution                 */
+            uint16_t              : 13;
+        } ELCSARC_b;
+    };
+} R_ELC_Type;                          /*!< Size = 126 (0x7e)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                       R_FACI_HP_CMD                                       ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD)
+ */
+
+typedef struct                         /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure                                    */
+{
+    union
+    {
+        __IOM uint16_t FACI_CMD16;     /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access)                */
+        __IOM uint8_t  FACI_CMD8;      /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access)                */
+    };
+} R_FACI_HP_CMD_Type;                  /*!< Size = 2 (0x2)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_FACI_HP                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Flash Application Command Interface (R_FACI_HP)
+ */
+
+typedef struct                         /*!< (@ 0x407FE000) R_FACI_HP Structure                                        */
+{
+    __IM uint32_t RESERVED[4];
+
+    union
+    {
+        __IOM uint8_t FASTAT;          /*!< (@ 0x00000010) Flash Access Status                                        */
+
+        struct
+        {
+            uint8_t             : 3;
+            __IOM uint8_t DFAE  : 1;   /*!< [3..3] Data Flash Access Error                                            */
+            __IM uint8_t  CMDLK : 1;   /*!< [4..4] Command Lock                                                       */
+            uint8_t             : 2;
+            __IOM uint8_t CFAE  : 1;   /*!< [7..7] Code Flash Access Error                                            */
+        } FASTAT_b;
+    };
+    __IM uint8_t  RESERVED1;
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t FAEINT;          /*!< (@ 0x00000014) Flash Access Error Interrupt Enable                        */
+
+        struct
+        {
+            uint8_t               : 3;
+            __IOM uint8_t DFAEIE  : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable                           */
+            __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable                                      */
+            uint8_t               : 2;
+            __IOM uint8_t CFAEIE  : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable                           */
+        } FAEINT_b;
+    };
+    __IM uint8_t  RESERVED3;
+    __IM uint16_t RESERVED4;
+
+    union
+    {
+        __IOM uint8_t FRDYIE;          /*!< (@ 0x00000018) Flash Ready Interrupt Enable                               */
+
+        struct
+        {
+            __IOM uint8_t FRDYIE : 1;  /*!< [0..0] FRDY Interrupt Enable                                              */
+            uint8_t              : 7;
+        } FRDYIE_b;
+    };
+    __IM uint8_t  RESERVED5;
+    __IM uint16_t RESERVED6;
+    __IM uint32_t RESERVED7[5];
+
+    union
+    {
+        __IOM uint32_t FSADDR;         /*!< (@ 0x00000030) Flash Start Address                                        */
+
+        struct
+        {
+            __IOM uint32_t FSA : 32;   /*!< [31..0] Start Address of Flash Sequencer Command Target Area
+                                        *   These bits can be written when FRDY bit of FSTATR register
+                                        *   is '1'. Writing to these bits in FRDY = '0' is ignored.                   */
+        } FSADDR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FEADDR;         /*!< (@ 0x00000034) Flash End Address                                          */
+
+        struct
+        {
+            __IOM uint32_t FEA : 32;   /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies
+                                        *   end address of target area in 'Blank Check' command. These
+                                        *   bits can be written when FRDY bit of FSTATR register is
+                                        *   '1'. Writing to these bits in FRDY = '0' is ignored.                      */
+        } FEADDR_b;
+    };
+    __IM uint32_t RESERVED8[3];
+
+    union
+    {
+        __IOM uint16_t FMEPROT;        /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register                   */
+
+        struct
+        {
+            __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit
+                                        *   is only possible when the FRDY bit in the FSTATR register
+                                        *   is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing
+                                        *   to this bit is only possible when 16 bits are written and
+                                        *   the value written to the KEY bits is D9h.Written values
+                                        *   are not retained by these bits (always read as 0x00).Only
+                                        *   secure access can write to this register. Both secure access
+                                        *   and non-secure read access are allowed. Non-secure writeaccess
+                                        *   is denied, but TrustZo                                                    */
+            uint16_t          : 7;
+            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
+        } FMEPROT_b;
+    };
+    __IM uint16_t RESERVED9;
+    __IM uint32_t RESERVED10[12];
+
+    union
+    {
+        __IOM uint16_t FBPROT0;        /*!< (@ 0x00000078) Flash Block Protection Register                            */
+
+        struct
+        {
+            __IOM uint16_t BPCN0 : 1;  /*!< [0..0] Block Protection for Non-secure CancelThis bit can be
+                                        *   written when the FRDY bit in the FSTATR register is 1.
+                                        *   Writing to this bit is ignored when the FRDY bit is 0.Writing
+                                        *   to this bit is only possible when 16 bits are written and
+                                        *   the value written to the KEY[7:0] bits is 0x78.Written
+                                        *   values are not retained by these bits (always read as 0x00).              */
+            uint16_t          : 7;
+            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
+        } FBPROT0_b;
+    };
+    __IM uint16_t RESERVED11;
+
+    union
+    {
+        __IOM uint16_t FBPROT1;        /*!< (@ 0x0000007C) Flash Block Protection for Secure Register                 */
+
+        struct
+        {
+            __IOM uint16_t BPCN1 : 1;  /*!< [0..0] Block Protection for Secure CancelWriting to this bit
+                                        *   is only possible when the FRDY bit in the FSTATR register
+                                        *   is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing
+                                        *   to this bit is only possible when 16 bits are written and
+                                        *   the value written to the KEY[7:0] bits is 0xB1.Written
+                                        *   values are not retained by these bits (always read as 0x00).              */
+            uint16_t          : 7;
+            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
+        } FBPROT1_b;
+    };
+    __IM uint16_t RESERVED12;
+
+    union
+    {
+        __IM uint32_t FSTATR;          /*!< (@ 0x00000080) Flash Status                                               */
+
+        struct
+        {
+            uint32_t                 : 6;
+            __IM uint32_t FLWEERR    : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag                               */
+            uint32_t                 : 1;
+            __IM uint32_t PRGSPD     : 1; /*!< [8..8] Programming-Suspended Status                                       */
+            __IM uint32_t ERSSPD     : 1; /*!< [9..9] Erasure-Suspended Status                                           */
+            __IM uint32_t DBFULL     : 1; /*!< [10..10] Data Buffer Full                                                 */
+            __IM uint32_t SUSRDY     : 1; /*!< [11..11] Suspend Ready                                                    */
+            __IM uint32_t PRGERR     : 1; /*!< [12..12] Programming Error                                                */
+            __IM uint32_t ERSERR     : 1; /*!< [13..13] Erasure Error                                                    */
+            __IM uint32_t ILGLERR    : 1; /*!< [14..14] Illegal Command Error                                            */
+            __IM uint32_t FRDY       : 1; /*!< [15..15] Flash Ready                                                      */
+            uint32_t                 : 4;
+            __IM uint32_t  OTERR     : 1; /*!< [20..20] Other Error                                                      */
+            __IOM uint32_t SECERR    : 1; /*!< [21..21] Security Error                                                   */
+            __IM uint32_t  FESETERR  : 1; /*!< [22..22] FENTRY Setting Error                                             */
+            __IM uint32_t  ILGCOMERR : 1; /*!< [23..23] Illegal Command Error                                            */
+            uint32_t                 : 8;
+        } FSTATR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t FENTRYR;         /*!< (@ 0x00000084) Program/Erase Mode Entry                                   */
+
+        struct
+        {
+            __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when
+                                         *   FRDY bit in FSTATR register is '1'. Writing to this bit
+                                         *   in FRDY = '0' is ignored. Writing to these bits is enabled
+                                         *   only when this register is accessed in 16-bit size and
+                                         *   H'AA is written to KEY bits                                               */
+            uint16_t               : 6;
+            __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when
+                                         *   FRDY bit in FSTATR register is '1'. Writing to this bit
+                                         *   in FRDY = '0' is ignored. Writing to these bits is enabled
+                                         *   only when this register is accessed in 16-bit size and
+                                         *   H'AA is written to KEY bits.                                              */
+            __OM uint16_t KEY : 8;      /*!< [15..8] KEY Code                                                          */
+        } FENTRYR_b;
+    };
+    __IM uint16_t RESERVED13;
+    __IM uint32_t RESERVED14;
+
+    union
+    {
+        __IOM uint16_t FSUINITR;       /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize                          */
+
+        struct
+        {
+            __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY
+                                        *   bit of FSTATR register is '1'. Writing to this bit in FRDY
+                                        *   = '0' is ignored. Writing to these bits is enabled only
+                                        *   when this register is accessed in 16-bit size and H'2D
+                                        *   is written to KEY bits.                                                   */
+            uint16_t          : 7;
+            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
+        } FSUINITR_b;
+    };
+    __IM uint16_t RESERVED15;
+    __IM uint32_t RESERVED16[4];
+
+    union
+    {
+        __IM uint16_t FCMDR;           /*!< (@ 0x000000A0) Flash Sequencer Command                                    */
+
+        struct
+        {
+            __IM uint16_t PCMDR : 8;   /*!< [7..0] Previous Command Register                                          */
+            __IM uint16_t CMDR  : 8;   /*!< [15..8] Command Register                                                  */
+        } FCMDR_b;
+    };
+    __IM uint16_t RESERVED17;
+    __IM uint32_t RESERVED18[11];
+
+    union
+    {
+        __IOM uint8_t FBCCNT;          /*!< (@ 0x000000D0) Blank Check Control                                        */
+
+        struct
+        {
+            __IOM uint8_t BCDIR : 1;   /*!< [0..0] Blank Check Direction                                              */
+            uint8_t             : 7;
+        } FBCCNT_b;
+    };
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
+
+    union
+    {
+        __IM uint8_t FBCSTAT;          /*!< (@ 0x000000D4) Blank Check Status                                         */
+
+        struct
+        {
+            __IM uint8_t BCST : 1;     /*!< [0..0] Blank Check Status Bit                                             */
+            uint8_t           : 7;
+        } FBCSTAT_b;
+    };
+    __IM uint8_t  RESERVED21;
+    __IM uint16_t RESERVED22;
+
+    union
+    {
+        __IM uint32_t FPSADDR;         /*!< (@ 0x000000D8) Programmed Area Start Address                              */
+
+        struct
+        {
+            __IM uint32_t PSADR : 19;  /*!< [18..0] Programmed Area Start Address NOTE: Indicates address
+                                        *   of the first programmed data which is found in 'Blank Check'
+                                        *   command execution.                                                        */
+            uint32_t : 13;
+        } FPSADDR_b;
+    };
+
+    union
+    {
+        __IM uint32_t FAWMON;          /*!< (@ 0x000000DC) Flash Access Window Monitor                                */
+
+        struct
+        {
+            __IM uint32_t FAWS : 11;   /*!< [10..0] Start Sector Address for Access Window NOTE: These bits
+                                        *   indicate the start sector address for setting the access
+                                        *   window that is located in the configuration area.                         */
+            uint32_t           : 4;
+            __IM uint32_t FSPR : 1;    /*!< [15..15] Protection Flag of programming the Access Window, Boot
+                                        *   Flag and Temporary Boot Swap Control and 'Config Clear'
+                                        *   command execution                                                         */
+            __IM uint32_t FAWE : 11;   /*!< [26..16] End Sector Address for Access Window NOTE: These bits
+                                        *   indicate the end sector address for setting the access
+                                        *   window that is located in the configuration area.                         */
+            uint32_t            : 4;
+            __IM uint32_t BTFLG : 1;   /*!< [31..31] Flag of Start-Up area select for Boot Swap                       */
+        } FAWMON_b;
+    };
+
+    union
+    {
+        __IOM uint16_t FCPSR;           /*!< (@ 0x000000E0) FCU Process Switch                                         */
+
+        struct
+        {
+            __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode                                             */
+            uint16_t               : 15;
+        } FCPSR_b;
+    };
+    __IM uint16_t RESERVED23;
+
+    union
+    {
+        __IOM uint16_t FPCKAR;         /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification    */
+
+        struct
+        {
+            __IOM uint16_t PCKA : 8;   /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits
+                                        *   can be written when FRDY bit in FSTATR register is '1'.
+                                        *   Writing to this bit in FRDY = '0' is ignored. Writing to
+                                        *   these bits is enabled only when this register is accessed
+                                        *   in 16-bit size and H'1E is written to KEY bits.                           */
+            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
+        } FPCKAR_b;
+    };
+    __IM uint16_t RESERVED24;
+
+    union
+    {
+        __IOM uint16_t FSUACR;         /*!< (@ 0x000000E8) Flash Start-Up Area Control Register                       */
+
+        struct
+        {
+            __IOM uint16_t SAS : 2;    /*!< [1..0] Start Up Area Select These bits can be written when FRDY
+                                        *   bit in FSTATR register is '1'. Writing to this bit in FRDY
+                                        *   = '0' is ignored. Writing to these bits is enabled only
+                                        *   when this register is accessed in 16-bit size and H'66
+                                        *   is written to KEY bits.                                                   */
+            uint16_t          : 6;
+            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
+        } FSUACR_b;
+    };
+    __IM uint16_t RESERVED25;
+} R_FACI_HP_Type;                      /*!< Size = 236 (0xec)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                         R_FCACHE                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Flash Memory Cache (R_FCACHE)
+ */
+
+typedef struct                         /*!< (@ 0x4001C000) R_FCACHE Structure                                         */
+{
+    __IM uint16_t RESERVED[128];
+
+    union
+    {
+        __IOM uint16_t FCACHEE;          /*!< (@ 0x00000100) Flash Cache Enable Register                                */
+
+        struct
+        {
+            __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable                                                      */
+            uint16_t                : 15;
+        } FCACHEE_b;
+    };
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint16_t FCACHEIV;         /*!< (@ 0x00000104) Flash Cache Invalidate Register                            */
+
+        struct
+        {
+            __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register                                    */
+            uint16_t                : 15;
+        } FCACHEIV_b;
+    };
+    __IM uint16_t RESERVED2[11];
+
+    union
+    {
+        __IOM uint8_t FLWT;            /*!< (@ 0x0000011C) Flash Wait Cycle Register                                  */
+
+        struct
+        {
+            __IOM uint8_t FLWT : 3;    /*!< [2..0] Flash Wait Cycle                                                   */
+            uint8_t            : 5;
+        } FLWT_b;
+    };
+    __IM uint8_t  RESERVED3;
+    __IM uint16_t RESERVED4[17];
+
+    union
+    {
+        __IOM uint16_t FSAR;             /*!< (@ 0x00000140) Flash Security Attribution Register                        */
+
+        struct
+        {
+            __IOM uint16_t FLWTSA   : 1; /*!< [0..0] FLWT Security Attribution                                          */
+            uint16_t                : 7;
+            __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution                                        */
+            uint16_t                : 7;
+        } FSAR_b;
+    };
+} R_FCACHE_Type;                         /*!< Size = 322 (0x142)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_GPT0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief General PWM Timer (R_GPT0)
+ */
+
+typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure                                           */
+{
+    union
+    {
+        __IOM uint32_t GTWP;           /*!< (@ 0x00000000) General PWM Timer Write-Protection Register                */
+
+        struct
+        {
+            __IOM uint32_t WP    : 1;  /*!< [0..0] Register Write Disable                                             */
+            __IOM uint32_t STRWP : 1;  /*!< [1..1] GTSTR.CSTRT Bit Write Disable                                      */
+            __IOM uint32_t STPWP : 1;  /*!< [2..2] GTSTP.CSTOP Bit Write Disable                                      */
+            __IOM uint32_t CLRWP : 1;  /*!< [3..3] GTCLR.CCLR Bit Write Disable                                       */
+            __IOM uint32_t CMNWP : 1;  /*!< [4..4] Common Register Write Disabled                                     */
+            uint32_t             : 3;
+            __OM uint32_t PRKEY  : 8;  /*!< [15..8] GTWP Key Code                                                     */
+            uint32_t             : 16;
+        } GTWP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSTR;           /*!< (@ 0x00000004) General PWM Timer Software Start Register                  */
+
+        struct
+        {
+            __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+        } GTSTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSTP;           /*!< (@ 0x00000008) General PWM Timer Software Stop Register                   */
+
+        struct
+        {
+            __IOM uint32_t CSTOP0 : 1;  /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP1 : 1;  /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP2 : 1;  /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP3 : 1;  /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP4 : 1;  /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP5 : 1;  /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP6 : 1;  /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP7 : 1;  /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP8 : 1;  /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP9 : 1;  /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+        } GTSTP_b;
+    };
+
+    union
+    {
+        __OM uint32_t GTCLR;           /*!< (@ 0x0000000C) General PWM Timer Software Clear Register                  */
+
+        struct
+        {
+            __OM uint32_t CCLR0  : 1;  /*!< [0..0] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR1  : 1;  /*!< [1..1] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR2  : 1;  /*!< [2..2] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR3  : 1;  /*!< [3..3] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR4  : 1;  /*!< [4..4] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR5  : 1;  /*!< [5..5] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR6  : 1;  /*!< [6..6] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR7  : 1;  /*!< [7..7] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR8  : 1;  /*!< [8..8] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR9  : 1;  /*!< [9..9] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR10 : 1;  /*!< [10..10] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
+        } GTCLR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSSR;            /*!< (@ 0x00000010) General PWM Timer Start Source Select Register             */
+
+        struct
+        {
+            __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable                */
+            __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable               */
+            __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable                */
+            __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable               */
+            __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable                */
+            __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable               */
+            __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable                */
+            __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable               */
+            __IOM uint32_t SSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Start Enable                        */
+            uint32_t              : 7;
+            __IOM uint32_t CSTRT  : 1;   /*!< [31..31] Software Source Counter Start Enable                             */
+        } GTSSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTPSR;            /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register              */
+
+        struct
+        {
+            __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable                 */
+            __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable                */
+            __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable                 */
+            __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable                */
+            __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable                 */
+            __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable                */
+            __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable                 */
+            __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable                */
+            __IOM uint32_t PSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable                        */
+            uint32_t              : 7;
+            __IOM uint32_t CSTOP  : 1;   /*!< [31..31] Software Source Counter Stop Enable                              */
+        } GTPSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTCSR;            /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register             */
+
+        struct
+        {
+            __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable                */
+            __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable               */
+            __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable                */
+            __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable               */
+            __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable                */
+            __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable               */
+            __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable                */
+            __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable               */
+            __IOM uint32_t CSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSCMSC : 3;   /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing
+                                          *   Source Counter Clear Enable.                                              */
+            __IOM uint32_t CP1CCE : 1;   /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear
+                                          *   Enable (This bit is only available in GPT324 to GPT329.
+                                          *   In GPT320 to GPT323, this bit is read as 0. The write value
+                                          *   should be 0.)                                                             */
+            uint32_t            : 3;
+            __IOM uint32_t CCLR : 1;     /*!< [31..31] Software Source Counter Clear Enable                             */
+        } GTCSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTUPSR;           /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register          */
+
+        struct
+        {
+            __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable             */
+            __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable            */
+            __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable             */
+            __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable            */
+            __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable             */
+            __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable            */
+            __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable             */
+            __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable            */
+            __IOM uint32_t USCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USILVL : 4;   /*!< [27..24] External Input Level Source Count-Up Enable                      */
+            uint32_t              : 4;
+        } GTUPSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDNSR;           /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register        */
+
+        struct
+        {
+            __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable           */
+            __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable          */
+            __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable           */
+            __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable          */
+            __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable           */
+            __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable          */
+            __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable           */
+            __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable          */
+            __IOM uint32_t DSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSILVL : 4;   /*!< [27..24] External Input Level Source Count-Down Enable                    */
+            uint32_t              : 4;
+        } GTDNSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTICASR;          /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select
+                                          *                  Register A                                                 */
+
+        struct
+        {
+            __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
+            __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
+            __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
+            __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
+            __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t ASCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            uint32_t              : 8;
+        } GTICASR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTICBSR;          /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select
+                                          *                  Register B                                                 */
+
+        struct
+        {
+            __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
+            __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
+            __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
+            __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
+            __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t BSCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            uint32_t              : 8;
+        } GTICBSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+
+        struct
+        {
+            __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
+            uint32_t               : 7;
+            __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
+            __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
+            __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
+            __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
+            uint32_t               : 2;
+            __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
+            __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
+            uint32_t               : 3;
+            __IOM uint32_t TPCS    : 4; /*!< [26..23] Timer Prescaler Select                                           */
+            __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
+            uint32_t               : 3;
+        } GTCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTUDDTYC;       /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t UD     : 1; /*!< [0..0] Count Direction Setting                                            */
+            __IOM uint32_t UDF    : 1; /*!< [1..1] Forcible Count Direction Setting                                   */
+            uint32_t              : 14;
+            __IOM uint32_t OADTY  : 2; /*!< [17..16] GTIOCA Output Duty Setting                                       */
+            __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting                              */
+            __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100
+                                        *   percent Duty Setting                                                      */
+            uint32_t              : 4;
+            __IOM uint32_t OBDTY  : 2; /*!< [25..24] GTIOCB Output Duty Setting                                       */
+            __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting                              */
+            __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100
+                                        *   percent Duty Setting                                                      */
+            uint32_t : 4;
+        } GTUDDTYC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTIOR;          /*!< (@ 0x00000034) General PWM Timer I/O Control Register                     */
+
+        struct
+        {
+            __IOM uint32_t GTIOA  : 5; /*!< [4..0] GTIOCA Pin Function Select                                         */
+            __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous
+                                        *   Clear Disable.(This bit is only available in GPT324 to
+                                        *   GPT329. In GPT320 to GPT323, this bit is read as 0. The
+                                        *   write value should be 0.)                                                 */
+            __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop                  */
+            __IOM uint32_t OAHLD  : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count                  */
+            __IOM uint32_t OAE    : 1; /*!< [8..8] GTIOCA Pin Output Enable                                           */
+            __IOM uint32_t OADF   : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting                                  */
+            __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This
+                                        *   bit is only available in GPT324 to GPT329. In GPT320 to
+                                        *   GPT323, this bit is read as 0. The write value should be
+                                        *   0.)                                                                       */
+            __IOM uint32_t PSYE   : 1; /*!< [12..12] PWM Synchronous output Enable                                    */
+            __IOM uint32_t NFAEN  : 1; /*!< [13..13] Noise Filter A Enable                                            */
+            __IOM uint32_t NFCSA  : 2; /*!< [15..14] Noise Filter A Sampling Clock Select                             */
+            __IOM uint32_t GTIOB  : 5; /*!< [20..16] GTIOCB Pin Function Select                                       */
+            uint32_t              : 1;
+            __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop                */
+            __IOM uint32_t OBHLD  : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count                */
+            __IOM uint32_t OBE    : 1; /*!< [24..24] GTIOCB Pin Output Enable                                         */
+            __IOM uint32_t OBDF   : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting                                 */
+            __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This
+                                        *   bit is only available in GPT324 to GPT329. In GPT320 to
+                                        *   GPT323, this bit is read as 0. The write value should be
+                                        *   0.)                                                                       */
+            uint32_t             : 1;
+            __IOM uint32_t NFBEN : 1;  /*!< [29..29] Noise Filter B Enable                                            */
+            __IOM uint32_t NFCSB : 2;  /*!< [31..30] Noise Filter B Sampling Clock Select                             */
+        } GTIOR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTINTAD;        /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register        */
+
+        struct
+        {
+            uint32_t            : 8;
+            __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
+            __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            uint32_t               : 4;
+            __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
+            uint32_t               : 2;
+            __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
+            __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
+        } GTINTAD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTST;            /*!< (@ 0x0000003C) General PWM Timer Status Register                          */
+
+        struct
+        {
+            __IOM uint32_t TCFA  : 1;   /*!< [0..0] Input Capture/Compare Match Flag A                                 */
+            __IOM uint32_t TCFB  : 1;   /*!< [1..1] Input Capture/Compare Match Flag B                                 */
+            __IOM uint32_t TCFC  : 1;   /*!< [2..2] Input Compare Match Flag C                                         */
+            __IOM uint32_t TCFD  : 1;   /*!< [3..3] Input Compare Match Flag D                                         */
+            __IOM uint32_t TCFE  : 1;   /*!< [4..4] Input Compare Match Flag E                                         */
+            __IOM uint32_t TCFF  : 1;   /*!< [5..5] Input Compare Match Flag F                                         */
+            __IOM uint32_t TCFPO : 1;   /*!< [6..6] Overflow Flag                                                      */
+            __IOM uint32_t TCFPU : 1;   /*!< [7..7] Underflow Flag                                                     */
+            __IM uint32_t  ITCNT : 3;   /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter
+                                         *   for counting the number of times a timer interrupt has
+                                         *   been skipped.)                                                            */
+            uint32_t               : 4;
+            __IM uint32_t  TUCF    : 1; /*!< [15..15] Count Direction Flag                                             */
+            __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start
+                                         *   Request Interrupt Enable                                                  */
+            __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor
+                                         *   Start Request Flag                                                        */
+            __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start
+                                         *   Request Flag                                                              */
+            __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor
+                                         *   Start Request Flag                                                        */
+            uint32_t             : 4;
+            __IM uint32_t ODF    : 1;   /*!< [24..24] Output Disable Flag                                              */
+            uint32_t             : 3;
+            __IM uint32_t  DTEF  : 1;   /*!< [28..28] Dead Time Error Flag                                             */
+            __IM uint32_t  OABHF : 1;   /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IM uint32_t  OABLF : 1;   /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t PCF   : 1;   /*!< [31..31] Period Count Function Finish Flag                                */
+        } GTST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+
+        struct
+        {
+            __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
+            __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+                                         *   is read as 0.                                                             */
+            uint32_t             : 1;
+            __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
+            uint32_t             : 1;
+            __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
+            uint32_t             : 1;
+        } GTBER_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTITC;          /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter
+                                        *                  Start Request Skipping Setting Register                    */
+
+        struct
+        {
+            __IOM uint32_t ITLA  : 1;  /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link                  */
+            __IOM uint32_t ITLB  : 1;  /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link                  */
+            __IOM uint32_t ITLC  : 1;  /*!< [2..2] GTCCRC Compare Match Interrupt Link                                */
+            __IOM uint32_t ITLD  : 1;  /*!< [3..3] GTCCRD Compare Match Interrupt Link                                */
+            __IOM uint32_t ITLE  : 1;  /*!< [4..4] GTCCRE Compare Match Interrupt Link                                */
+            __IOM uint32_t ITLF  : 1;  /*!< [5..5] GTCCRF Compare Match Interrupt Link                                */
+            __IOM uint32_t IVTC  : 2;  /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select                 */
+            __IOM uint32_t IVTT  : 3;  /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select                   */
+            uint32_t             : 1;
+            __IOM uint32_t ADTAL : 1;  /*!< [12..12] GTADTRA A/D Converter Start Request Link                         */
+            uint32_t             : 1;
+            __IOM uint32_t ADTBL : 1;  /*!< [14..14] GTADTRB A/D Converter Start Request Link                         */
+            uint32_t             : 17;
+        } GTITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTCNT;          /*!< (@ 0x00000048) General PWM Timer Counter                                  */
+
+        struct
+        {
+            __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter                                                           */
+        } GTCNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTCCR[6];       /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register                 */
+
+        struct
+        {
+            __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A                                        */
+        } GTCCR_b[6];
+    };
+
+    union
+    {
+        __IOM uint32_t GTPR;           /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register                   */
+
+        struct
+        {
+            __IOM uint32_t GTPR : 32;  /*!< [31..0] Cycle Setting Register                                            */
+        } GTPR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTPBR;          /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register            */
+
+        struct
+        {
+            __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register                                     */
+        } GTPBR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTPDBR;          /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer
+                                         *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register                              */
+        } GTPDBR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADTRA;          /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A              */
+
+        struct
+        {
+            __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A                     */
+        } GTADTRA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADTBRA;          /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register
+                                           *                  A                                                          */
+
+        struct
+        {
+            __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A              */
+        } GTADTBRA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADTDBRA;          /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer
+                                            *                  Register A                                                 */
+
+        struct
+        {
+            __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
+                                            *   A                                                                         */
+        } GTADTDBRA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADTRB;          /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B              */
+
+        struct
+        {
+            __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B                     */
+        } GTADTRB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADTBRB;          /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register
+                                           *                  B                                                          */
+
+        struct
+        {
+            __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B              */
+        } GTADTBRB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADTDBRB;          /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer
+                                            *                  Register B                                                 */
+
+        struct
+        {
+            __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
+                                            *   B                                                                         */
+        } GTADTDBRB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDTCR;         /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register               */
+
+        struct
+        {
+            __IOM uint32_t TDE   : 1;  /*!< [0..0] Negative-Phase Waveform Setting                                    */
+            uint32_t             : 3;
+            __IOM uint32_t TDBUE : 1;  /*!< [4..4] GTDVU Buffer Operation Enable                                      */
+            __IOM uint32_t TDBDE : 1;  /*!< [5..5] GTDVD Buffer Operation Enable                                      */
+            uint32_t             : 2;
+            __IOM uint32_t TDFER : 1;  /*!< [8..8] GTDVD Setting                                                      */
+            uint32_t             : 23;
+        } GTDTCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDVU;          /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U               */
+
+        struct
+        {
+            __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U                                        */
+        } GTDVU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDVD;          /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D               */
+
+        struct
+        {
+            __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D                                        */
+        } GTDVD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDBU;          /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U              */
+
+        struct
+        {
+            __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U                                       */
+        } GTDBU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDBD;          /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D              */
+
+        struct
+        {
+            __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D                                       */
+        } GTDBD_b;
+    };
+
+    union
+    {
+        __IM uint32_t GTSOS;           /*!< (@ 0x0000009C) General PWM Timer Output Protection Function
+                                        *                  Status Register                                            */
+
+        struct
+        {
+            __IM uint32_t SOS : 2;     /*!< [1..0] Output Protection Function Status                                  */
+            uint32_t          : 30;
+        } GTSOS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSOTR;         /*!< (@ 0x000000A0) General PWM Timer Output Protection Function
+                                        *                  Temporary Release Register                                 */
+
+        struct
+        {
+            __IOM uint32_t SOTR : 1;   /*!< [0..0] Output Protection Function Temporary Release                       */
+            uint32_t            : 31;
+        } GTSOTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTICLF;           /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation
+                                          *                  Function Setting Register                                  */
+
+        struct
+        {
+            __IOM uint32_t ICLFA    : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select                   */
+            uint32_t                : 1;
+            __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select                                      */
+            uint32_t                : 6;
+            __IOM uint32_t ICLFB    : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select                 */
+            uint32_t                : 1;
+            __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select                                    */
+            uint32_t                : 6;
+        } GTICLF_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTPC;           /*!< (@ 0x000000BC) General PWM Timer Period Count Register                    */
+
+        struct
+        {
+            __IOM uint32_t PCEN : 1;   /*!< [0..0] Period Count Function Enable                                       */
+            uint32_t            : 7;
+            __IOM uint32_t ASTP : 1;   /*!< [8..8] Automatic Stop Function Enable                                     */
+            uint32_t            : 7;
+            __IOM uint32_t PCNT : 12;  /*!< [27..16] Period Counter                                                   */
+            uint32_t            : 4;
+        } GTPC_b;
+    };
+    __IM uint32_t RESERVED[4];
+
+    union
+    {
+        __IOM uint32_t GTSECSR;         /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous
+                                         *                  Control Channel Select Register                            */
+
+        struct
+        {
+            __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel
+                                         *   Select                                                                    */
+            uint32_t : 22;
+        } GTSECSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSECR;         /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous
+                                        *                  Control Register                                           */
+
+        struct
+        {
+            __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
+            __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
+            __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
+            __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 4;
+            __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
+            __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
+            uint32_t             : 6;
+            __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
+            __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
+            uint32_t             : 6;
+        } GTSECR_b;
+    };
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
+            __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
+                                        *   Disable                                                                   */
+            uint32_t             : 2;
+            __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t             : 1;
+            __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
+                                        *   Transfer Disable                                                          */
+            uint32_t             : 2;
+            __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
+            __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
+            __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
+            __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
+            uint32_t             : 2;
+        } GTBER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
+
+        struct
+        {
+            __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
+            uint32_t              : 11;
+            __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
+            uint32_t              : 11;
+        } GTOLBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
+                                        *                  Capture Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
+            __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
+                                        *   Other Channel GTCCRb Input Capture Source Enable                          */
+            __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
+        } GTICCR_b;
+    };
+} R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                         R_GPT_OPS                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Output Phase Switching for GPT (R_GPT_OPS)
+ */
+
+typedef struct                         /*!< (@ 0x40169A00) R_GPT_OPS Structure                                        */
+{
+    union
+    {
+        __IOM uint32_t OPSCR;          /*!< (@ 0x00000000) Output Phase Switching Control Register                    */
+
+        struct
+        {
+            __IOM uint32_t UF : 1;     /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase
+                                        *   by the software settings.This bit setting is valid when
+                                        *   the OPSCR.FB bit = 1.                                                     */
+            __IOM uint32_t VF : 1;     /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase
+                                        *   by the software settings.This bit setting is valid when
+                                        *   the OPSCR.FB bit = 1.                                                     */
+            __IOM uint32_t WF : 1;     /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase
+                                        *   by the software settings.This bit setting is valid when
+                                        *   the OPSCR.FB bit = 1.                                                     */
+            uint32_t        : 1;
+            __IM uint32_t U : 1;       /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the
+                                        *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
+                                        *   e settings (UF/VF/WF)                                                     */
+            __IM uint32_t V : 1;       /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the
+                                        *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
+                                        *   e settings (UF/VF/WF)                                                     */
+            __IM uint32_t W : 1;       /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the
+                                        *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
+                                        *   e settings (UF/VF/WF)                                                     */
+            uint32_t          : 1;
+            __IOM uint32_t EN : 1;     /*!< [8..8] Enable-Phase Output Control                                        */
+            uint32_t          : 7;
+            __IOM uint32_t FB : 1;     /*!< [16..16] External Feedback Signal EnableThis bit selects the
+                                        *   input phase from the software settings and external input.                */
+            __IOM uint32_t P     : 1;  /*!< [17..17] Positive-Phase Output (P) Control                                */
+            __IOM uint32_t N     : 1;  /*!< [18..18] Negative-Phase Output (N) Control                                */
+            __IOM uint32_t INV   : 1;  /*!< [19..19] Invert-Phase Output Control                                      */
+            __IOM uint32_t RV    : 1;  /*!< [20..20] Output phase rotation direction reversal                         */
+            __IOM uint32_t ALIGN : 1;  /*!< [21..21] Input phase alignment                                            */
+            uint32_t             : 2;
+            __IOM uint32_t GRP   : 2;  /*!< [25..24] Output disabled source selection                                 */
+            __IOM uint32_t GODF  : 1;  /*!< [26..26] Group output disable function                                    */
+            uint32_t             : 2;
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] External Input Noise Filter Enable                               */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] External Input Noise Filter Clock selectionNoise filter
+                                        *   sampling clock setting of the external input.                             */
+        } OPSCR_b;
+    };
+} R_GPT_OPS_Type;                      /*!< Size = 4 (0x4)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                        R_GPT_POEG0                                        ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Port Output Enable for GPT (R_GPT_POEG0)
+ */
+
+typedef struct                         /*!< (@ 0x4008A000) R_GPT_POEG0 Structure                                      */
+{
+    union
+    {
+        __IOM uint32_t POEGG;          /*!< (@ 0x00000000) POEG Group Setting Register                                */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] Real Time Overcurrent Detection Flag                               */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection EnableNote: Can be modified only
+                                        *   once after a reset.                                                       */
+            __IOM uint32_t IOCE : 1;   /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified
+                                        *   only once after a reset.                                                  */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified
+                                        *   only once after a reset.                                                  */
+            uint32_t             : 1;
+            __IOM uint32_t CDRE0 : 1;  /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified
+                                        *   only once after a reset.                                                  */
+            __IOM uint32_t CDRE1 : 1;  /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified
+                                        *   only once after a reset.                                                  */
+            __IOM uint32_t CDRE2 : 1;  /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified
+                                        *   only once after a reset.                                                  */
+            __IOM uint32_t CDRE3 : 1;  /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified
+                                        *   only once after a reset.                                                  */
+            __IOM uint32_t CDRE4 : 1;  /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified
+                                        *   only once after a reset.                                                  */
+            __IOM uint32_t CDRE5 : 1;  /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified
+                                        *   only once after a reset.                                                  */
+            uint32_t            : 2;
+            __IM uint32_t ST    : 1;   /*!< [16..16] GTETRG Input Status Flag                                         */
+            uint32_t            : 11;
+            __IOM uint32_t INV  : 1;   /*!< [28..28] GTETRG Input Reverse                                             */
+            __IOM uint32_t NFEN : 1;   /*!< [29..29] Noise Filter Enable                                              */
+            __IOM uint32_t NFCS : 2;   /*!< [31..30] Noise Filter Clock Select                                        */
+        } POEGG_b;
+    };
+} R_GPT_POEG0_Type;                    /*!< Size = 4 (0x4)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ICU                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Interrupt Controller Unit (R_ICU)
+ */
+
+typedef struct                         /*!< (@ 0x40006000) R_ICU Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t IRQCR[16];       /*!< (@ 0x00000000) IRQ Control Register [0..15]                               */
+
+        struct
+        {
+            __IOM uint8_t IRQMD   : 2; /*!< [1..0] IRQ Detection Sense Select                                         */
+            uint8_t               : 2;
+            __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select                           */
+            uint8_t               : 1;
+            __IOM uint8_t FLTEN   : 1; /*!< [7..7] IRQ Digital Filter Enable                                          */
+        } IRQCR_b[16];
+    };
+    __IM uint32_t RESERVED[60];
+
+    union
+    {
+        __IOM uint8_t NMICR;            /*!< (@ 0x00000100) NMI Pin Interrupt Control Register                         */
+
+        struct
+        {
+            __IOM uint8_t NMIMD    : 1; /*!< [0..0] NMI Detection Set                                                  */
+            uint8_t                : 3;
+            __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select                           */
+            uint8_t                : 1;
+            __IOM uint8_t NFLTEN   : 1; /*!< [7..7] NMI Digital Filter Enable                                          */
+        } NMICR_b;
+    };
+    __IM uint8_t  RESERVED1;
+    __IM uint16_t RESERVED2;
+    __IM uint32_t RESERVED3[7];
+
+    union
+    {
+        __IOM uint16_t NMIER;           /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register                     */
+
+        struct
+        {
+            __IOM uint16_t IWDTEN  : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable                      */
+            __IOM uint16_t WDTEN   : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable                       */
+            __IOM uint16_t LVD1EN  : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable                              */
+            __IOM uint16_t LVD2EN  : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable                              */
+            __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable                                     */
+            uint16_t               : 1;
+            __IOM uint16_t OSTEN   : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable                        */
+            __IOM uint16_t NMIEN   : 1; /*!< [7..7] NMI Pin Interrupt Enable                                           */
+            __IOM uint16_t RPEEN   : 1; /*!< [8..8] RAM Parity Error Interrupt Enable                                  */
+            __IOM uint16_t RECCEN  : 1; /*!< [9..9] RAM ECC Error Interrupt Enable                                     */
+            __IOM uint16_t BUSSEN  : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable                             */
+            __IOM uint16_t BUSMEN  : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable                            */
+            __IOM uint16_t SPEEN   : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable                       */
+            __IOM uint16_t TZFEN   : 1; /*!< [13..13] TZFEN                                                            */
+            uint16_t               : 1;
+            __IOM uint16_t CPEEN   : 1; /*!< [15..15] CPEEN                                                            */
+        } NMIER_b;
+    };
+    __IM uint16_t RESERVED4;
+    __IM uint32_t RESERVED5[3];
+
+    union
+    {
+        __IOM uint16_t NMICLR;          /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register               */
+
+        struct
+        {
+            __OM uint16_t IWDTCLR  : 1; /*!< [0..0] IWDT Clear                                                         */
+            __OM uint16_t WDTCLR   : 1; /*!< [1..1] WDT Clear                                                          */
+            __OM uint16_t LVD1CLR  : 1; /*!< [2..2] LVD1 Clear                                                         */
+            __OM uint16_t LVD2CLR  : 1; /*!< [3..3] LVD2 Clear                                                         */
+            __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear                                                        */
+            uint16_t               : 1;
+            __OM uint16_t  OSTCLR  : 1; /*!< [6..6] OST Clear                                                          */
+            __OM uint16_t  NMICLR  : 1; /*!< [7..7] NMI Clear                                                          */
+            __OM uint16_t  RPECLR  : 1; /*!< [8..8] SRAM Parity Error Clear                                            */
+            __OM uint16_t  RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear                                               */
+            __OM uint16_t  BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear                                            */
+            __OM uint16_t  BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear                                           */
+            __OM uint16_t  SPECLR  : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear                        */
+            __IOM uint16_t TZFCLR  : 1; /*!< [13..13] TZFCLR                                                           */
+            uint16_t               : 1;
+            __IOM uint16_t CPECLR  : 1; /*!< [15..15] CPECLR                                                           */
+        } NMICLR_b;
+    };
+    __IM uint16_t RESERVED6;
+    __IM uint32_t RESERVED7[3];
+
+    union
+    {
+        __IM uint16_t NMISR;           /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register                     */
+
+        struct
+        {
+            __IM uint16_t IWDTST  : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag                           */
+            __IM uint16_t WDTST   : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag                            */
+            __IM uint16_t LVD1ST  : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag                         */
+            __IM uint16_t LVD2ST  : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag                         */
+            __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag                                */
+            uint16_t              : 1;
+            __IM uint16_t OSTST   : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag                   */
+            __IM uint16_t NMIST   : 1; /*!< [7..7] NMI Status Flag                                                    */
+            __IM uint16_t RPEST   : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag                             */
+            __IM uint16_t RECCST  : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag                                */
+            __IM uint16_t BUSSST  : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag                        */
+            __IM uint16_t BUSMST  : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag                       */
+            __IM uint16_t SPEST   : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag                  */
+            __IM uint16_t TZFST   : 1; /*!< [13..13] TZFST                                                            */
+            uint16_t              : 1;
+            __IM uint16_t CPEST   : 1; /*!< [15..15] CPEST                                                            */
+        } NMISR_b;
+    };
+    __IM uint16_t RESERVED8;
+    __IM uint32_t RESERVED9[23];
+
+    union
+    {
+        __IOM uint32_t WUPEN;                /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register                          */
+
+        struct
+        {
+            __IOM uint32_t IRQWUPEN0    : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN1    : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN2    : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN3    : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN4    : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN5    : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN6    : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN7    : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN8    : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN9    : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN10   : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable                         */
+            __IOM uint32_t IRQWUPEN11   : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable                         */
+            __IOM uint32_t IRQWUPEN12   : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable                         */
+            __IOM uint32_t IRQWUPEN13   : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable                         */
+            __IOM uint32_t IRQWUPEN14   : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable                         */
+            __IOM uint32_t IRQWUPEN15   : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable                         */
+            __IOM uint32_t IWDTWUPEN    : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable                        */
+            __IOM uint32_t KEYWUPEN     : 1; /*!< [17..17] Key interrupt S/W standby returns enable                         */
+            __IOM uint32_t LVD1WUPEN    : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable                        */
+            __IOM uint32_t LVD2WUPEN    : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable                        */
+            __IOM uint32_t VBATTWUPEN   : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable               */
+            uint32_t                    : 1;
+            __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit                 */
+            __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable                     */
+            __IOM uint32_t RTCALMWUPEN  : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable                   */
+            __IOM uint32_t RTCPRDWUPEN  : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable                  */
+            __IOM uint32_t USBHSWUPEN   : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit                   */
+            __IOM uint32_t USBFSWUPEN   : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable                       */
+            __IOM uint32_t AGT1UDWUPEN  : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable              */
+            __IOM uint32_t AGT1CAWUPEN  : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns
+                                              *   enable                                                                    */
+            __IOM uint32_t AGT1CBWUPEN : 1;  /*!< [30..30] AGT1 compare match B interrupt S/W standby returns
+                                              *   enable                                                                    */
+            __IOM uint32_t IIC0WUPEN : 1;    /*!< [31..31] IIC0 address match interrupt S/W standby returns enable          */
+        } WUPEN_b;
+    };
+
+    union
+    {
+        __IOM uint32_t WUPEN1;              /*!< (@ 0x000001A4) Wake Up interrupt enable register 1                        */
+
+        struct
+        {
+            __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit            */
+            __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable
+                                             *   bit                                                                       */
+            __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable
+                                             *   bit                                                                       */
+            uint32_t : 29;
+        } WUPEN1_b;
+    };
+    __IM uint32_t RESERVED10[6];
+
+    union
+    {
+        __IOM uint8_t IELEN;            /*!< (@ 0x000001C0) ICU event Enable Register                                  */
+
+        struct
+        {
+            __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit
+                                         *   = 1)                                                                      */
+            __IOM uint8_t IELEN : 1;    /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when
+                                         *   LPOPTEN bit = 1)                                                          */
+            uint8_t : 6;
+        } IELEN_b;
+    };
+    __IM uint8_t  RESERVED11;
+    __IM uint16_t RESERVED12;
+    __IM uint32_t RESERVED13[15];
+
+    union
+    {
+        __IOM uint16_t SELSR0;         /*!< (@ 0x00000200) Snooze Event Link Setting Register                         */
+
+        struct
+        {
+            __IOM uint16_t SELS : 9;   /*!< [8..0] SYS Event Link Select                                              */
+            uint16_t            : 7;
+        } SELSR0_b;
+    };
+    __IM uint16_t RESERVED14;
+    __IM uint32_t RESERVED15[31];
+
+    union
+    {
+        __IOM uint32_t DELSR[8];       /*!< (@ 0x00000280) DMAC Event Link Setting Register                           */
+
+        struct
+        {
+            __IOM uint32_t DELS : 9;   /*!< [8..0] Event selection to DMAC Start request                              */
+            uint32_t            : 7;
+            __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
+                                        *   IR flag is prohibited.                                                    */
+            uint32_t : 15;
+        } DELSR_b[8];
+    };
+    __IM uint32_t RESERVED16[24];
+
+    union
+    {
+        __IOM uint32_t IELSR[96];      /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95]                    */
+
+        struct
+        {
+            __IOM uint32_t IELS : 9;   /*!< [8..0] ICU Event selection to NVICSet the number for the event
+                                        *   signal to be linked .                                                     */
+            uint32_t            : 7;
+            __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag                                            */
+            uint32_t            : 7;
+            __IOM uint32_t DTCE : 1;   /*!< [24..24] DTC Activation Enable                                            */
+            uint32_t            : 7;
+        } IELSR_b[96];
+    };
+} R_ICU_Type;                          /*!< Size = 1152 (0x480)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_IIC0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I2C Bus Interface (R_IIC0)
+ */
+
+typedef struct                         /*!< (@ 0x4009F000) R_IIC0 Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t ICCR1;           /*!< (@ 0x00000000) I2C Bus Control Register 1                                 */
+
+        struct
+        {
+            __IM uint8_t  SDAI   : 1;  /*!< [0..0] SDA Line Monitor                                                   */
+            __IM uint8_t  SCLI   : 1;  /*!< [1..1] SCL Line Monitor                                                   */
+            __IOM uint8_t SDAO   : 1;  /*!< [2..2] SDA Output Control/Monitor                                         */
+            __IOM uint8_t SCLO   : 1;  /*!< [3..3] SCL Output Control/Monitor                                         */
+            __IOM uint8_t SOWP   : 1;  /*!< [4..4] SCLO/SDAO Write Protect                                            */
+            __IOM uint8_t CLO    : 1;  /*!< [5..5] Extra SCL Clock Cycle Output                                       */
+            __IOM uint8_t IICRST : 1;  /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset
+                                        *   is initiated using the IICRST bit for a bus hang-up occurred
+                                        *   during communication with the master device in slave mode,
+                                        *   the states may become different between the slave device
+                                        *   and the master device (due to the difference in the bit
+                                        *   counter information).                                                     */
+            __IOM uint8_t ICE : 1;     /*!< [7..7] I2C Bus Interface Enable                                           */
+        } ICCR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICCR2;           /*!< (@ 0x00000001) I2C Bus Control Register 2                                 */
+
+        struct
+        {
+            uint8_t          : 1;
+            __IOM uint8_t ST : 1;      /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start
+                                        *   condition issuance request) when the BBSY flag is set to
+                                        *   0 (bus free state).                                                       */
+            __IOM uint8_t RS : 1;      /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the
+                                        *   RS bit to 1 while issuing a stop condition.                               */
+            __IOM uint8_t SP : 1;      /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP
+                                        *   bit is not possible while the setting of the BBSY flag
+                                        *   is 0 (bus free state).Note: Do not set the SP bit to 1
+                                        *   while a restart condition is being issued.                                */
+            uint8_t            : 1;
+            __IOM uint8_t TRS  : 1;    /*!< [5..5] Transmit/Receive Mode                                              */
+            __IOM uint8_t MST  : 1;    /*!< [6..6] Master/Slave Mode                                                  */
+            __IM uint8_t  BBSY : 1;    /*!< [7..7] Bus Busy Detection Flag                                            */
+        } ICCR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICMR1;           /*!< (@ 0x00000002) I2C Bus Mode Register 1                                    */
+
+        struct
+        {
+            __IOM uint8_t BC   : 3;    /*!< [2..0] Bit Counter                                                        */
+            __OM uint8_t  BCWP : 1;    /*!< [3..3] BC Write Protect(This bit is read as 1.)                           */
+            __IOM uint8_t CKS  : 3;    /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB
+                                        *   / 2^CKS )                                                                 */
+            __IOM uint8_t MTWP : 1;    /*!< [7..7] MST/TRS Write Protect                                              */
+        } ICMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICMR2;           /*!< (@ 0x00000003) I2C Bus Mode Register 2                                    */
+
+        struct
+        {
+            __IOM uint8_t TMOS : 1;    /*!< [0..0] Timeout Detection Time Select                                      */
+            __IOM uint8_t TMOL : 1;    /*!< [1..1] Timeout L Count Control                                            */
+            __IOM uint8_t TMOH : 1;    /*!< [2..2] Timeout H Count Control                                            */
+            uint8_t            : 1;
+            __IOM uint8_t SDDL : 3;    /*!< [6..4] SDA Output Delay Counter                                           */
+            __IOM uint8_t DLCS : 1;    /*!< [7..7] SDA Output Delay Clock Source Select                               */
+        } ICMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICMR3;           /*!< (@ 0x00000004) I2C Bus Mode Register 3                                    */
+
+        struct
+        {
+            __IOM uint8_t NF    : 2;   /*!< [1..0] Noise Filter Stage Selection                                       */
+            __IM uint8_t  ACKBR : 1;   /*!< [2..2] Receive Acknowledge                                                */
+            __IOM uint8_t ACKBT : 1;   /*!< [3..3] Transmit Acknowledge                                               */
+            __IOM uint8_t ACKWP : 1;   /*!< [4..4] ACKBT Write Protect                                                */
+            __IOM uint8_t RDRFS : 1;   /*!< [5..5] RDRF Flag Set Timing Selection                                     */
+            __IOM uint8_t WAIT  : 1;   /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read,
+                                        *   be sure to read the ICDRR beforehand.                                     */
+            __IOM uint8_t SMBS : 1;    /*!< [7..7] SMBus/I2C Bus Selection                                            */
+        } ICMR3_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICFER;           /*!< (@ 0x00000005) I2C Bus Function Enable Register                           */
+
+        struct
+        {
+            __IOM uint8_t TMOE  : 1;   /*!< [0..0] Timeout Function Enable                                            */
+            __IOM uint8_t MALE  : 1;   /*!< [1..1] Master Arbitration-Lost Detection Enable                           */
+            __IOM uint8_t NALE  : 1;   /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable                */
+            __IOM uint8_t SALE  : 1;   /*!< [3..3] Slave Arbitration-Lost Detection Enable                            */
+            __IOM uint8_t NACKE : 1;   /*!< [4..4] NACK Reception Transfer Suspension Enable                          */
+            __IOM uint8_t NFE   : 1;   /*!< [5..5] Digital Noise Filter Circuit Enable                                */
+            __IOM uint8_t SCLE  : 1;   /*!< [6..6] SCL Synchronous Circuit Enable                                     */
+            __IOM uint8_t FMPE  : 1;   /*!< [7..7] Fast-mode Plus Enable                                              */
+        } ICFER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICSER;           /*!< (@ 0x00000006) I2C Bus Status Enable Register                             */
+
+        struct
+        {
+            __IOM uint8_t SAR0E : 1;   /*!< [0..0] Slave Address Register 0 Enable                                    */
+            __IOM uint8_t SAR1E : 1;   /*!< [1..1] Slave Address Register 1 Enable                                    */
+            __IOM uint8_t SAR2E : 1;   /*!< [2..2] Slave Address Register 2 Enable                                    */
+            __IOM uint8_t GCAE  : 1;   /*!< [3..3] General Call Address Enable                                        */
+            uint8_t             : 1;
+            __IOM uint8_t DIDE  : 1;   /*!< [5..5] Device-ID Address Detection Enable                                 */
+            uint8_t             : 1;
+            __IOM uint8_t HOAE  : 1;   /*!< [7..7] Host Address Enable                                                */
+        } ICSER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICIER;           /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register                          */
+
+        struct
+        {
+            __IOM uint8_t TMOIE : 1;   /*!< [0..0] Timeout Interrupt Request Enable                                   */
+            __IOM uint8_t ALIE  : 1;   /*!< [1..1] Arbitration-Lost Interrupt Request Enable                          */
+            __IOM uint8_t STIE  : 1;   /*!< [2..2] Start Condition Detection Interrupt Request Enable                 */
+            __IOM uint8_t SPIE  : 1;   /*!< [3..3] Stop Condition Detection Interrupt Request Enable                  */
+            __IOM uint8_t NAKIE : 1;   /*!< [4..4] NACK Reception Interrupt Request Enable                            */
+            __IOM uint8_t RIE   : 1;   /*!< [5..5] Receive Data Full Interrupt Request Enable                         */
+            __IOM uint8_t TEIE  : 1;   /*!< [6..6] Transmit End Interrupt Request Enable                              */
+            __IOM uint8_t TIE   : 1;   /*!< [7..7] Transmit Data Empty Interrupt Request Enable                       */
+        } ICIER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICSR1;           /*!< (@ 0x00000008) I2C Bus Status Register 1                                  */
+
+        struct
+        {
+            __IOM uint8_t AAS0 : 1;    /*!< [0..0] Slave Address 0 Detection Flag                                     */
+            __IOM uint8_t AAS1 : 1;    /*!< [1..1] Slave Address 1 Detection Flag                                     */
+            __IOM uint8_t AAS2 : 1;    /*!< [2..2] Slave Address 2 Detection Flag                                     */
+            __IOM uint8_t GCA  : 1;    /*!< [3..3] General Call Address Detection Flag                                */
+            uint8_t            : 1;
+            __IOM uint8_t DID  : 1;    /*!< [5..5] Device-ID Address Detection Flag                                   */
+            uint8_t            : 1;
+            __IOM uint8_t HOA  : 1;    /*!< [7..7] Host Address Detection Flag                                        */
+        } ICSR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICSR2;           /*!< (@ 0x00000009) I2C Bus Status Register 2                                  */
+
+        struct
+        {
+            __IOM uint8_t TMOF  : 1;   /*!< [0..0] Timeout Detection Flag                                             */
+            __IOM uint8_t AL    : 1;   /*!< [1..1] Arbitration-Lost Flag                                              */
+            __IOM uint8_t START : 1;   /*!< [2..2] Start Condition Detection Flag                                     */
+            __IOM uint8_t STOP  : 1;   /*!< [3..3] Stop Condition Detection Flag                                      */
+            __IOM uint8_t NACKF : 1;   /*!< [4..4] NACK Detection Flag                                                */
+            __IOM uint8_t RDRF  : 1;   /*!< [5..5] Receive Data Full Flag                                             */
+            __IOM uint8_t TEND  : 1;   /*!< [6..6] Transmit End Flag                                                  */
+            __IM uint8_t  TDRE  : 1;   /*!< [7..7] Transmit Data Empty Flag                                           */
+        } ICSR2_b;
+    };
+    __IOM R_IIC0_SAR_Type SAR[3];      /*!< (@ 0x0000000A) Slave Address Registers                                    */
+
+    union
+    {
+        __IOM uint8_t ICBRL;           /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register                        */
+
+        struct
+        {
+            __IOM uint8_t BRL : 5;     /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock)           */
+            uint8_t           : 3;
+        } ICBRL_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICBRH;           /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register                       */
+
+        struct
+        {
+            __IOM uint8_t BRH : 5;     /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock)         */
+            uint8_t           : 3;
+        } ICBRH_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICDRT;           /*!< (@ 0x00000012) I2C Bus Transmit Data Register                             */
+
+        struct
+        {
+            __IOM uint8_t ICDRT : 8;   /*!< [7..0] 8-bit read-write register that stores transmit data.               */
+        } ICDRT_b;
+    };
+
+    union
+    {
+        __IM uint8_t ICDRR;            /*!< (@ 0x00000013) I2C Bus Receive Data Register                              */
+
+        struct
+        {
+            __IM uint8_t ICDRR : 8;    /*!< [7..0] 8-bit register that stores the received data                       */
+        } ICDRR_b;
+    };
+    __IM uint8_t RESERVED[2];
+
+    union
+    {
+        __IOM uint8_t ICWUR;           /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register                              */
+
+        struct
+        {
+            __IOM uint8_t WUAFA : 1;   /*!< [0..0] Wakeup Analog Filter Additional Selection                          */
+            uint8_t             : 3;
+            __IOM uint8_t WUACK : 1;   /*!< [4..4] ACK bit for Wakeup Mode                                            */
+            __IOM uint8_t WUF   : 1;   /*!< [5..5] Wakeup Event Occurrence Flag                                       */
+            __IOM uint8_t WUIE  : 1;   /*!< [6..6] Wakeup Interrupt Request Enable                                    */
+            __IOM uint8_t WUE   : 1;   /*!< [7..7] Wakeup Function Enable                                             */
+        } ICWUR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICWUR2;          /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2                            */
+
+        struct
+        {
+            __IM uint8_t WUSEN  : 1;   /*!< [0..0] Wake-up Function Synchronous Enable                                */
+            __IM uint8_t WUASYF : 1;   /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag                */
+            __IM uint8_t WUSYF  : 1;   /*!< [2..2] Wake-up Function Synchronous Operation Status Flag                 */
+            uint8_t             : 5;
+        } ICWUR2_b;
+    };
+} R_IIC0_Type;                         /*!< Size = 24 (0x18)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_IWDT                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Independent Watchdog Timer (R_IWDT)
+ */
+
+typedef struct                         /*!< (@ 0x40083200) R_IWDT Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t IWDTRR;          /*!< (@ 0x00000000) IWDT Refresh Register                                      */
+
+        struct
+        {
+            __IOM uint8_t IWDTRR : 8;  /*!< [7..0] The counter is refreshed by writing 0x00 and then writing
+                                        *   0xFF to this register.                                                    */
+        } IWDTRR_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t IWDTCR;         /*!< (@ 0x00000002) IWDT Control Register                                      */
+
+        struct
+        {
+            __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
+            uint16_t            : 2;
+            __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
+            __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
+            uint16_t            : 2;
+            __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
+            uint16_t            : 2;
+        } IWDTCR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t IWDTSR;          /*!< (@ 0x00000004) IWDT Status Register                                       */
+
+        struct
+        {
+            __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
+            __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
+            __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
+        } IWDTSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t IWDTRCR;         /*!< (@ 0x00000006) IWDT Reset Control Register                                */
+
+        struct
+        {
+            uint8_t               : 7;
+            __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
+        } IWDTRCR_b;
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        __IOM uint8_t IWDTCSTPR;       /*!< (@ 0x00000008) IWDT Count Stop Control Register                           */
+
+        struct
+        {
+            uint8_t              : 7;
+            __IOM uint8_t SLCSTP : 1;  /*!< [7..7] Sleep-Mode Count Stop Control                                      */
+        } IWDTCSTPR_b;
+    };
+    __IM uint8_t  RESERVED2;
+    __IM uint16_t RESERVED3;
+} R_IWDT_Type;                         /*!< Size = 12 (0xc)                                                           */
+
+/* =========================================================================================================================== */
+/* ================                                          R_I3C0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I3C Bus Interface (R_I3C0)
+ */
+
+typedef struct                         /*!< (@ 0x4011F000) R_I3C0 Structure                                           */
+{
+    union
+    {
+        __IOM uint32_t PRTS;           /*!< (@ 0x00000000) Protocol Selection Register                                */
+
+        struct
+        {
+            __IOM uint32_t PRTMD : 1;  /*!< [0..0] Protocol Mode                                                      */
+            uint32_t             : 31;
+        } PRTS_b;
+    };
+    __IM uint32_t RESERVED[3];
+
+    union
+    {
+        __IOM uint32_t CECTL;          /*!< (@ 0x00000010) Clock Enable Control Resisters                             */
+
+        struct
+        {
+            __IOM uint32_t CLKE : 1;   /*!< [0..0] Clock Enable                                                       */
+            uint32_t            : 31;
+        } CECTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BCTL;             /*!< (@ 0x00000014) Bus Control Register                                       */
+
+        struct
+        {
+            __IOM uint32_t INCBA    : 1; /*!< [0..0] Include I3C Broadcast Address                                      */
+            uint32_t                : 6;
+            __IOM uint32_t BMDS     : 1; /*!< [7..7] Bus Mode Selection                                                 */
+            __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control                                       */
+            uint32_t                : 20;
+            __IOM uint32_t ABT      : 1; /*!< [29..29] Abort                                                            */
+            __IOM uint32_t RSM      : 1; /*!< [30..30] Resume                                                           */
+            __IOM uint32_t BUSE     : 1; /*!< [31..31] Bus Enable                                                       */
+        } BCTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSDVAD;         /*!< (@ 0x00000018) Master Device Address Register                             */
+
+        struct
+        {
+            uint32_t              : 16;
+            __IOM uint32_t MDYAD  : 7; /*!< [22..16] Master Dynamic Address                                           */
+            uint32_t              : 8;
+            __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid                                     */
+        } MSDVAD_b;
+    };
+    __IM uint32_t RESERVED1;
+
+    union
+    {
+        __IOM uint32_t RSTCTL;          /*!< (@ 0x00000020) Reset Control Register                                     */
+
+        struct
+        {
+            __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset                                                 */
+            __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset                                       */
+            __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset                                      */
+            __IOM uint32_t TDBRST  : 1; /*!< [3..3] Transmit Data Buffer Software Reset                                */
+            __IOM uint32_t RDBRST  : 1; /*!< [4..4] Receive Data Buffer Software Reset                                 */
+            __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset                                           */
+            __IOM uint32_t RSQRST  : 1; /*!< [6..6] Receive Status Queue Software Reset                                */
+            uint32_t               : 9;
+            __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset                                          */
+            uint32_t               : 15;
+        } RSTCTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PRSST;          /*!< (@ 0x00000024) Present State Register                                     */
+
+        struct
+        {
+            uint32_t              : 2;
+            __IOM uint32_t CRMS   : 1; /*!< [2..2] Current Master                                                     */
+            uint32_t              : 1;
+            __IM uint32_t TRMD    : 1; /*!< [4..4] Transmit/Receive Mode                                              */
+            uint32_t              : 2;
+            __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect                                        */
+            uint32_t              : 24;
+        } PRSST_b;
+    };
+    __IM uint32_t RESERVED2[2];
+
+    union
+    {
+        __IOM uint32_t INST;           /*!< (@ 0x00000030) Internal Status Register                                   */
+
+        struct
+        {
+            uint32_t            : 10;
+            __IOM uint32_t INEF : 1;   /*!< [10..10] Internal Error Flag                                              */
+            uint32_t            : 21;
+        } INST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t INSTE;          /*!< (@ 0x00000034) Internal Status Enable Register                            */
+
+        struct
+        {
+            uint32_t            : 10;
+            __IOM uint32_t INEE : 1;   /*!< [10..10] Internal Error Enable                                            */
+            uint32_t            : 21;
+        } INSTE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t INIE;           /*!< (@ 0x00000038) Internal Interrupt Enable Register                         */
+
+        struct
+        {
+            uint32_t             : 10;
+            __IOM uint32_t INEIE : 1;  /*!< [10..10] Internal Error Interrupt Enable                                  */
+            uint32_t             : 21;
+        } INIE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t INSTFC;         /*!< (@ 0x0000003C) Internal Status Force Register                             */
+
+        struct
+        {
+            uint32_t            : 10;
+            __OM uint32_t INEFC : 1;   /*!< [10..10] Internal Error Force                                             */
+            uint32_t            : 21;
+        } INSTFC_b;
+    };
+    __IM uint32_t RESERVED3;
+
+    union
+    {
+        __IM uint32_t DVCT;            /*!< (@ 0x00000044) Device Characteristic Table Register                       */
+
+        struct
+        {
+            uint32_t          : 19;
+            __IM uint32_t IDX : 5;     /*!< [23..19] DCT Table Index                                                  */
+            uint32_t          : 8;
+        } DVCT_b;
+    };
+    __IM uint32_t RESERVED4[4];
+
+    union
+    {
+        __IOM uint32_t IBINCTL;          /*!< (@ 0x00000058) IBI Notify Control Register                                */
+
+        struct
+        {
+            __IOM uint32_t NRHJCTL  : 1; /*!< [0..0] Notify Rejected Hot-Join Control                                   */
+            __IOM uint32_t NRMRCTL  : 1; /*!< [1..1] Notify Rejected Master Request Control                             */
+            uint32_t                : 1;
+            __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control                    */
+            uint32_t                : 28;
+        } IBINCTL_b;
+    };
+    __IM uint32_t RESERVED5;
+
+    union
+    {
+        __IOM uint32_t BFCTL;          /*!< (@ 0x00000060) Bus Function Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t MALE   : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable                           */
+            __IOM uint32_t NALE   : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable                */
+            __IOM uint32_t SALE   : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable                            */
+            uint32_t              : 5;
+            __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable                                     */
+            uint32_t              : 3;
+            __IOM uint32_t SMBS   : 1; /*!< [12..12] SMBus/I2C Bus Selection                                          */
+            uint32_t              : 1;
+            __IOM uint32_t FMPE   : 1; /*!< [14..14] Fast-mode Plus Enable                                            */
+            __IOM uint32_t HSME   : 1; /*!< [15..15] High Speed Mode Enable                                           */
+            uint32_t              : 16;
+        } BFCTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SVCTL;          /*!< (@ 0x00000064) Slave Control Register                                     */
+
+        struct
+        {
+            __IOM uint32_t GCAE  : 1;  /*!< [0..0] General Call Address Enable                                        */
+            uint32_t             : 4;
+            __IOM uint32_t HSMCE : 1;  /*!< [5..5] Hs-mode Master Code Enable                                         */
+            __IOM uint32_t DVIDE : 1;  /*!< [6..6] Device-ID Address Enable                                           */
+            uint32_t             : 8;
+            __IOM uint32_t HOAE  : 1;  /*!< [15..15] Host Address Enable                                              */
+            __IOM uint32_t SVAEn : 1;  /*!< [16..16] Slave Address Enable n (n = 0)                                   */
+            uint32_t             : 15;
+        } SVCTL_b;
+    };
+    __IM uint32_t RESERVED6[2];
+
+    union
+    {
+        __IOM uint32_t REFCKCTL;        /*!< (@ 0x00000070) Reference Clock Control Register                           */
+
+        struct
+        {
+            __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection                                 */
+            uint32_t               : 29;
+        } REFCKCTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STDBR;          /*!< (@ 0x00000074) Standard Bit Rate Register                                 */
+
+        struct
+        {
+            __IOM uint32_t SBRLO  : 8; /*!< [7..0] Count value of the Low-level period of SCL clock                   */
+            __IOM uint32_t SBRHO  : 8; /*!< [15..8] Count value of the High-level period of SCL clock                 */
+            __IOM uint32_t SBRLP  : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull                     */
+            uint32_t              : 2;
+            __IOM uint32_t SBRHP  : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull                    */
+            uint32_t              : 1;
+            __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain               */
+        } STDBR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EXTBR;          /*!< (@ 0x00000078) Extended Bit Rate Register                                 */
+
+        struct
+        {
+            __IOM uint32_t EBRLO : 8;  /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain                      */
+            __IOM uint32_t EBRHO : 8;  /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain                    */
+            __IOM uint32_t EBRLP : 6;  /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull                     */
+            uint32_t             : 2;
+            __IOM uint32_t EBRHP : 6;  /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull                     */
+            uint32_t             : 2;
+        } EXTBR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BFRECDT;        /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register                 */
+
+        struct
+        {
+            __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle                                 */
+            uint32_t              : 23;
+        } BFRECDT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BAVLCDT;        /*!< (@ 0x00000080) Bus Available Condition Detection Time Register            */
+
+        struct
+        {
+            __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle                            */
+            uint32_t              : 23;
+        } BAVLCDT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BIDLCDT;         /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register                 */
+
+        struct
+        {
+            __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle                                */
+            uint32_t              : 14;
+        } BIDLCDT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t OUTCTL;         /*!< (@ 0x00000088) Output Control Register                                    */
+
+        struct
+        {
+            __IOM uint32_t SDOC   : 1; /*!< [0..0] SDA Output Control                                                 */
+            __IOM uint32_t SCOC   : 1; /*!< [1..1] SCL Output Control                                                 */
+            __OM uint32_t  SOCWP  : 1; /*!< [2..2] SCL/SDA Output Control Write Protect                               */
+            uint32_t              : 1;
+            __IOM uint32_t EXCYC  : 1; /*!< [4..4] Extra SCL Clock Cycle Output                                       */
+            uint32_t              : 3;
+            __IOM uint32_t SDOD   : 3; /*!< [10..8] SDA Output Delay                                                  */
+            uint32_t              : 4;
+            __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection                          */
+            uint32_t              : 16;
+        } OUTCTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t INCTL;          /*!< (@ 0x0000008C) Input Control Register                                     */
+
+        struct
+        {
+            __IOM uint32_t DNFS : 4;   /*!< [3..0] Digital Noise Filter Stage Selection                               */
+            __IOM uint32_t DNFE : 1;   /*!< [4..4] Digital Noise Filter Circuit Enable                                */
+            uint32_t            : 27;
+        } INCTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TMOCTL;         /*!< (@ 0x00000090) Timeout Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t TODTS  : 2; /*!< [1..0] Timeout Detection Time Selection                                   */
+            uint32_t              : 2;
+            __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control                                            */
+            __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control                                            */
+            __IOM uint32_t TOMDS  : 2; /*!< [7..6] Timeout Operation Mode Selection                                   */
+            uint32_t              : 24;
+        } TMOCTL_b;
+    };
+    __IM uint32_t RESERVED7;
+
+    union
+    {
+        __IOM uint32_t WUCTL;           /*!< (@ 0x00000098) Wake Up Unit Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t WUACKS  : 1; /*!< [0..0] Wake-Up Acknowledge Selection                                      */
+            uint32_t               : 3;
+            __IOM uint32_t WUANFS  : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection                              */
+            uint32_t               : 1;
+            __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable                          */
+            __IOM uint32_t WUFE    : 1; /*!< [7..7] Wake-Up function Enable.                                           */
+            uint32_t               : 24;
+        } WUCTL_b;
+    };
+    __IM uint32_t RESERVED8;
+
+    union
+    {
+        __IOM uint32_t ACKCTL;         /*!< (@ 0x000000A0) Acknowledge Control Register                               */
+
+        struct
+        {
+            __IM uint32_t  ACKR   : 1; /*!< [0..0] Acknowledge Reception                                              */
+            __IOM uint32_t ACKT   : 1; /*!< [1..1] Acknowledge Transmission                                           */
+            __OM uint32_t  ACKTWP : 1; /*!< [2..2] ACKT Write Protect                                                 */
+            uint32_t              : 29;
+        } ACKCTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SCSTRCTL;       /*!< (@ 0x000000A4) SCL Stretch Control Register                               */
+
+        struct
+        {
+            __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable                               */
+            __IOM uint32_t RWE    : 1; /*!< [1..1] Receive Wait Enable                                                */
+            uint32_t              : 30;
+        } SCSTRCTL_b;
+    };
+    __IM uint32_t RESERVED9[2];
+
+    union
+    {
+        __IOM uint32_t SCSTLCTL;        /*!< (@ 0x000000B0) SCL Stalling Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle                                                    */
+            uint32_t              : 12;
+            __IOM uint32_t AAPE   : 1;  /*!< [28..28] Assigend Address Phase Enable                                    */
+            __IOM uint32_t TRAPE  : 1;  /*!< [29..29] Transition Phase Enable                                          */
+            __IOM uint32_t PARPE  : 1;  /*!< [30..30] Parity Phase Enable                                              */
+            __IOM uint32_t ACKPE  : 1;  /*!< [31..31] ACK phase Enable                                                 */
+        } SCSTLCTL_b;
+    };
+    __IM uint32_t RESERVED10[3];
+
+    union
+    {
+        __IOM uint32_t SVTDLG0;        /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0                      */
+
+        struct
+        {
+            uint32_t             : 16;
+            __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length                                       */
+        } SVTDLG0_b;
+    };
+    __IM uint32_t RESERVED11[31];
+
+    union
+    {
+        __IOM uint32_t CNDCTL;         /*!< (@ 0x00000140) Condition Control Register                                 */
+
+        struct
+        {
+            __IOM uint32_t STCND : 1;  /*!< [0..0] START (S) Condition Issuance                                       */
+            __IOM uint32_t SRCND : 1;  /*!< [1..1] Repeated START (Sr) Condition Issuance                             */
+            __IOM uint32_t SPCND : 1;  /*!< [2..2] STOP (P) Condition Issuance                                        */
+            uint32_t             : 29;
+        } CNDCTL_b;
+    };
+    __IM uint32_t  RESERVED12[3];
+    __OM uint32_t  NCMDQP;             /*!< (@ 0x00000150) Normal Command Queue Port Register                         */
+    __IM uint32_t  NRSPQP;             /*!< (@ 0x00000154) Normal Response Queue Port Register                        */
+    __IOM uint32_t NTDTBP0;            /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0                */
+    __IM uint32_t  RESERVED13[8];
+    __IOM uint32_t NIBIQP;             /*!< (@ 0x0000017C) Normal IBI Queue Port Register                             */
+    __IM uint32_t  NRSQP;              /*!< (@ 0x00000180) Normal Receive Status Queue Port Register                  */
+    __IM uint32_t  RESERVED14[3];
+
+    union
+    {
+        __IOM uint32_t NQTHCTL;         /*!< (@ 0x00000190) Normal Queue Threshold Control Register                    */
+
+        struct
+        {
+            __IOM uint32_t CMDQTH  : 8; /*!< [7..0] Normal Command Ready Queue Threshold                               */
+            __IOM uint32_t RSPQTH  : 8; /*!< [15..8] Normal Response Queue Threshold                                   */
+            __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size                                     */
+            __IOM uint32_t IBIQTH  : 8; /*!< [31..24] Normal IBI Queue Threshold                                       */
+        } NQTHCTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t NTBTHCTL0;      /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control
+                                        *                  Register 0                                                 */
+
+        struct
+        {
+            __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold                              */
+            uint32_t              : 5;
+            __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold                              */
+            uint32_t              : 5;
+            __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold                                        */
+            uint32_t              : 5;
+            __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold                                        */
+            uint32_t              : 5;
+        } NTBTHCTL0_b;
+    };
+    __IM uint32_t RESERVED15[10];
+
+    union
+    {
+        __IOM uint32_t NRQTHCTL;       /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t RSQTH : 8;  /*!< [7..0] Normal Receive Status Queue Threshold                              */
+            uint32_t             : 24;
+        } NRQTHCTL_b;
+    };
+    __IM uint32_t RESERVED16[3];
+
+    union
+    {
+        __IOM uint32_t BST;             /*!< (@ 0x000001D0) Bus Status Register                                        */
+
+        struct
+        {
+            __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag                                     */
+            __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag                                      */
+            __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag                                    */
+            uint32_t               : 1;
+            __IOM uint32_t NACKDF  : 1; /*!< [4..4] NACK Detection Flag                                                */
+            uint32_t               : 3;
+            __IOM uint32_t TENDF   : 1; /*!< [8..8] Transmit End Flag                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ALF     : 1; /*!< [16..16] Arbitration Lost Flag                                            */
+            uint32_t               : 3;
+            __IOM uint32_t TODF    : 1; /*!< [20..20] Timeout Detection Flag                                           */
+            uint32_t               : 11;
+        } BST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BSTE;            /*!< (@ 0x000001D4) Bus Status Enable Register                                 */
+
+        struct
+        {
+            __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable                                   */
+            __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable                                    */
+            __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable                                  */
+            uint32_t               : 1;
+            __IOM uint32_t NACKDE  : 1; /*!< [4..4] NACK Detection Enable                                              */
+            uint32_t               : 3;
+            __IOM uint32_t TENDE   : 1; /*!< [8..8] Transmit End Enable                                                */
+            uint32_t               : 7;
+            __IOM uint32_t ALE     : 1; /*!< [16..16] Arbitration Lost Enable                                          */
+            uint32_t               : 3;
+            __IOM uint32_t TODE    : 1; /*!< [20..20] Timeout Detection Enable                                         */
+            uint32_t               : 11;
+        } BSTE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BIE;              /*!< (@ 0x000001D8) Bus Interrupt Enable Register                              */
+
+        struct
+        {
+            __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable                         */
+            __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable                          */
+            __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable                        */
+            uint32_t                : 1;
+            __IOM uint32_t NACKDIE  : 1; /*!< [4..4] NACK Detection Interrupt Enable                                    */
+            uint32_t                : 3;
+            __IOM uint32_t TENDIE   : 1; /*!< [8..8] Transmit End Interrupt Enable                                      */
+            uint32_t                : 7;
+            __IOM uint32_t ALIE     : 1; /*!< [16..16] Arbitration Lost Interrupt Enable                                */
+            uint32_t                : 3;
+            __IOM uint32_t TODIE    : 1; /*!< [20..20] Timeout Detection Interrupt Enable                               */
+            uint32_t                : 11;
+        } BIE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BSTFC;           /*!< (@ 0x000001DC) Bus Status Force Register                                  */
+
+        struct
+        {
+            __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force                                    */
+            __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force                                     */
+            __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force                                   */
+            uint32_t               : 1;
+            __OM uint32_t NACKDFC  : 1; /*!< [4..4] NACK Detection Force                                               */
+            uint32_t               : 3;
+            __OM uint32_t TENDFC   : 1; /*!< [8..8] Transmit End Force                                                 */
+            uint32_t               : 7;
+            __OM uint32_t ALFC     : 1; /*!< [16..16] Arbitration Lost Force                                           */
+            uint32_t               : 3;
+            __OM uint32_t TODFC    : 1; /*!< [20..20] Timeout Detection Force                                          */
+            uint32_t               : 11;
+        } BSTFC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t NTST;            /*!< (@ 0x000001E0) Normal Transfer Status Register                            */
+
+        struct
+        {
+            __IOM uint32_t TDBEF0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0                           */
+            __IOM uint32_t RDBFF0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0                             */
+            __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag                                   */
+            __IOM uint32_t CMDQEF  : 1; /*!< [3..3] Normal Command Queue Empty Flag                                    */
+            __IOM uint32_t RSPQFF  : 1; /*!< [4..4] Normal Response Queue Full Flag                                    */
+            __IOM uint32_t TABTF   : 1; /*!< [5..5] Normal Transfer Abort Flag                                         */
+            uint32_t               : 3;
+            __IOM uint32_t TEF     : 1; /*!< [9..9] Normal Transfer Error Flag                                         */
+            uint32_t               : 10;
+            __IOM uint32_t RSQFF   : 1; /*!< [20..20] Normal Receive Status Queue Full Flag                            */
+            uint32_t               : 11;
+        } NTST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t NTSTE;           /*!< (@ 0x000001E4) Normal Transfer Status Enable Register                     */
+
+        struct
+        {
+            __IOM uint32_t TDBEE0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0                         */
+            __IOM uint32_t RDBFE0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0                           */
+            __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable                                 */
+            __IOM uint32_t CMDQEE  : 1; /*!< [3..3] Normal Command Queue Empty Enable                                  */
+            __IOM uint32_t RSPQFE  : 1; /*!< [4..4] Normal Response Queue Full Enable                                  */
+            __IOM uint32_t TABTE   : 1; /*!< [5..5] Normal Transfer Abort Enable                                       */
+            uint32_t               : 3;
+            __IOM uint32_t TEE     : 1; /*!< [9..9] Normal Transfer Error Enable                                       */
+            uint32_t               : 10;
+            __IOM uint32_t RSQFE   : 1; /*!< [20..20] Normal Receive Status Queue Full Enable                          */
+            uint32_t               : 11;
+        } NTSTE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t NTIE;             /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register                  */
+
+        struct
+        {
+            __IOM uint32_t TDBEIE0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0               */
+            __IOM uint32_t RDBFIE0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0                 */
+            __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable                       */
+            __IOM uint32_t CMDQEIE  : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable                        */
+            __IOM uint32_t RSPQFIE  : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable                        */
+            __IOM uint32_t TABTIE   : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable                             */
+            uint32_t                : 3;
+            __IOM uint32_t TEIE     : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable                             */
+            uint32_t                : 10;
+            __IOM uint32_t RSQFIE   : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable                */
+            uint32_t                : 11;
+        } NTIE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t NTSTFC;          /*!< (@ 0x000001EC) Normal Transfer Status Force Register                      */
+
+        struct
+        {
+            __OM uint32_t TDBEFC0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0                          */
+            __OM uint32_t RDBFFC0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0                            */
+            __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force                                  */
+            __OM uint32_t CMDQEFC  : 1; /*!< [3..3] Normal Command Queue Empty Force                                   */
+            __OM uint32_t RSPQFFC  : 1; /*!< [4..4] Normal Response Queue Full Force                                   */
+            __OM uint32_t TABTFC   : 1; /*!< [5..5] Normal Transfer Abort Force                                        */
+            uint32_t               : 3;
+            __OM uint32_t TEFC     : 1; /*!< [9..9] Normal Transfer Error Force                                        */
+            uint32_t               : 10;
+            __OM uint32_t RSQFFC   : 1; /*!< [20..20] Normal Receive Status Queue Full Force                           */
+            uint32_t               : 11;
+        } NTSTFC_b;
+    };
+    __IM uint32_t RESERVED17[8];
+
+    union
+    {
+        __IM uint32_t BCST;            /*!< (@ 0x00000210) Bus Condition Status Register                              */
+
+        struct
+        {
+            __IM uint32_t BFREF : 1;   /*!< [0..0] Bus Free Detection Flag                                            */
+            __IM uint32_t BAVLF : 1;   /*!< [1..1] Bus Available Detection Flag                                       */
+            __IM uint32_t BIDLF : 1;   /*!< [2..2] Bus Idle Detection Flag                                            */
+            uint32_t            : 29;
+        } BCST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SVST;           /*!< (@ 0x00000214) Slave Status Register                                      */
+
+        struct
+        {
+            __IOM uint32_t GCAF  : 1;  /*!< [0..0] General Call Address Detection Flag                                */
+            uint32_t             : 4;
+            __IOM uint32_t HSMCF : 1;  /*!< [5..5] Hs-mode Master Code Detection Flag                                 */
+            __IOM uint32_t DVIDF : 1;  /*!< [6..6] Device-ID Address Detection Flag                                   */
+            uint32_t             : 8;
+            __IOM uint32_t HOAF  : 1;  /*!< [15..15] Host Address Detection Flag                                      */
+            __IOM uint32_t SVAFn : 1;  /*!< [16..16] Slave Address Detection Flag n (n = 0)                           */
+            uint32_t             : 15;
+        } SVST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t WUST;            /*!< (@ 0x00000218) Wake Up Unit Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag.               */
+            uint32_t               : 31;
+        } WUST_b;
+    };
+    __IM uint32_t RESERVED18[2];
+
+    union
+    {
+        __IOM uint32_t DATBAS0;         /*!< (@ 0x00000224) Device Address Table Basic Register 0                      */
+
+        struct
+        {
+            __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
+            uint32_t               : 5;
+            __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
+            __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
+            __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
+            __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
+            __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
+            uint32_t               : 5;
+            __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
+            __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
+        } DATBAS0_b;
+    };
+    __IM uint32_t RESERVED19;
+
+    union
+    {
+        __IOM uint32_t DATBAS1;         /*!< (@ 0x0000022C) Device Address Table Basic Register 1                      */
+
+        struct
+        {
+            __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
+            uint32_t               : 5;
+            __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
+            __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
+            __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
+            __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
+            __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
+            uint32_t               : 5;
+            __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
+            __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
+        } DATBAS1_b;
+    };
+    __IM uint32_t RESERVED20;
+
+    union
+    {
+        __IOM uint32_t DATBAS2;         /*!< (@ 0x00000234) Device Address Table Basic Register 2                      */
+
+        struct
+        {
+            __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
+            uint32_t               : 5;
+            __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
+            __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
+            __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
+            __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
+            __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
+            uint32_t               : 5;
+            __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
+            __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
+        } DATBAS2_b;
+    };
+    __IM uint32_t RESERVED21;
+
+    union
+    {
+        __IOM uint32_t DATBAS3;         /*!< (@ 0x0000023C) Device Address Table Basic Register 3                      */
+
+        struct
+        {
+            __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
+            uint32_t               : 5;
+            __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
+            __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
+            __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
+            __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
+            __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
+            uint32_t               : 5;
+            __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
+            __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
+        } DATBAS3_b;
+    };
+    __IM uint32_t RESERVED22[24];
+
+    union
+    {
+        __IOM uint32_t EXDATBAS;       /*!< (@ 0x000002A0) Extended Device Address Table Basic Register               */
+
+        struct
+        {
+            __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address                                     */
+            uint32_t              : 9;
+            __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address                              */
+            uint32_t              : 5;
+            __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count                                 */
+            __IOM uint32_t EDTYP  : 1; /*!< [31..31] Extended Device Type                                             */
+        } EXDATBAS_b;
+    };
+    __IM uint32_t RESERVED23[3];
+
+    union
+    {
+        __IOM uint32_t SDATBAS0;         /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0                */
+
+        struct
+        {
+            __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
+            __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
+            uint32_t               : 1;
+            __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
+            uint32_t               : 3;
+            __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
+            uint32_t               : 9;
+        } SDATBAS0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SDATBAS1;         /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1                */
+
+        struct
+        {
+            __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
+            __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
+            uint32_t               : 1;
+            __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
+            uint32_t               : 3;
+            __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
+            uint32_t               : 9;
+        } SDATBAS1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SDATBAS2;         /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2                */
+
+        struct
+        {
+            __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
+            __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
+            uint32_t               : 1;
+            __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
+            uint32_t               : 3;
+            __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
+            uint32_t               : 9;
+        } SDATBAS2_b;
+    };
+    __IM uint32_t RESERVED24[5];
+
+    union
+    {
+        __IOM uint32_t MSDCT0;         /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0              */
+
+        struct
+        {
+            uint32_t              : 8;
+            __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
+            __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
+            __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
+            __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
+            uint32_t              : 2;
+            __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
+            uint32_t              : 16;
+        } MSDCT0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSDCT1;         /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1              */
+
+        struct
+        {
+            uint32_t              : 8;
+            __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
+            __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
+            __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
+            __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
+            uint32_t              : 2;
+            __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
+            uint32_t              : 16;
+        } MSDCT1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSDCT2;         /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2              */
+
+        struct
+        {
+            uint32_t              : 8;
+            __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
+            __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
+            __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
+            __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
+            uint32_t              : 2;
+            __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
+            uint32_t              : 16;
+        } MSDCT2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSDCT3;         /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3              */
+
+        struct
+        {
+            uint32_t              : 8;
+            __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
+            __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
+            __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
+            __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
+            uint32_t              : 2;
+            __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
+            uint32_t              : 16;
+        } MSDCT3_b;
+    };
+    __IM uint32_t RESERVED25[16];
+
+    union
+    {
+        __IOM uint32_t SVDCT;          /*!< (@ 0x00000320) Slave Device Characteristic Table Register                 */
+
+        struct
+        {
+            __IOM uint32_t TDCR   : 8; /*!< [7..0] Transfar Device Characteristic Register                            */
+            __IOM uint32_t TBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
+            __IOM uint32_t TBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
+            __IOM uint32_t TBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
+            __IOM uint32_t TBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
+            uint32_t              : 2;
+            __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role                                                      */
+            uint32_t              : 16;
+        } SVDCT_b;
+    };
+    __IOM uint32_t SDCTPIDL;           /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional
+                                        *                  ID Low Register                                            */
+    __IOM uint32_t SDCTPIDH;           /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional
+                                        *                  ID High Register                                           */
+    __IM uint32_t RESERVED26;
+
+    union
+    {
+        __IM uint32_t SVDVAD0;         /*!< (@ 0x00000330) Slave Device Address Register 0                            */
+
+        struct
+        {
+            uint32_t             : 16;
+            __IM uint32_t SVAD   : 10; /*!< [25..16] Slave Address                                                    */
+            uint32_t             : 1;
+            __IM uint32_t SADLG  : 1;  /*!< [27..27] Slave Address Length                                             */
+            uint32_t             : 2;
+            __IM uint32_t SSTADV : 1;  /*!< [30..30] Slave Static Address Valid                                       */
+            __IM uint32_t SDYADV : 1;  /*!< [31..31] Slave Dynamic Address Valid                                      */
+        } SVDVAD0_b;
+    };
+    __IM uint32_t RESERVED27[7];
+
+    union
+    {
+        __IOM uint32_t CSECMD;         /*!< (@ 0x00000350) CCC Slave Events Command Register                          */
+
+        struct
+        {
+            __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable                                    */
+            __IOM uint32_t MSRQE  : 1; /*!< [1..1] Mastership Requests Enable                                         */
+            uint32_t              : 1;
+            __IOM uint32_t HJEVE  : 1; /*!< [3..3] Hot-Join Event Enable                                              */
+            uint32_t              : 28;
+        } CSECMD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CEACTST;        /*!< (@ 0x00000354) CCC Enter Activity State Register                          */
+
+        struct
+        {
+            __IOM uint32_t ACTST : 4;  /*!< [3..0] Activity State                                                     */
+            uint32_t             : 28;
+        } CEACTST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CMWLG;          /*!< (@ 0x00000358) CCC Max Write Length Register                              */
+
+        struct
+        {
+            __IOM uint32_t MWLG : 16;  /*!< [15..0] Max Write Length                                                  */
+            uint32_t            : 16;
+        } CMWLG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CMRLG;           /*!< (@ 0x0000035C) CCC Max Read Length Register                               */
+
+        struct
+        {
+            __IOM uint32_t MRLG   : 16; /*!< [15..0] Max Read Length                                                   */
+            __IOM uint32_t IBIPSZ : 8;  /*!< [23..16] IBI Payload Size                                                 */
+            uint32_t              : 8;
+        } CMRLG_b;
+    };
+
+    union
+    {
+        __IM uint32_t CETSTMD;         /*!< (@ 0x00000360) CCC Enter Test Mode Register                               */
+
+        struct
+        {
+            __IM uint32_t TSTMD : 8;   /*!< [7..0] Test Mode                                                          */
+            uint32_t            : 24;
+        } CETSTMD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CGDVST;         /*!< (@ 0x00000364) CCC Get Device Status Register                             */
+
+        struct
+        {
+            __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t PRTE   : 1; /*!< [5..5] Protocol Error                                                     */
+            __IOM uint32_t ACTMD  : 2; /*!< [7..6] Slave Device's current Activity Mode                               */
+            __IOM uint32_t VDRSV  : 8; /*!< [15..8] Vendor Reserved                                                   */
+            uint32_t              : 16;
+        } CGDVST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CMDSPW;         /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register                      */
+
+        struct
+        {
+            __IOM uint32_t MSWDR : 3;  /*!< [2..0] Maximum Sustained Write Data Rate                                  */
+            uint32_t             : 29;
+        } CMDSPW_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CMDSPR;         /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register                       */
+
+        struct
+        {
+            __IOM uint32_t MSRDR  : 3; /*!< [2..0] Maximum Sustained Read Data Rate                                   */
+            __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO)                               */
+            uint32_t              : 26;
+        } CMDSPR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CMDSPT;          /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register                 */
+
+        struct
+        {
+            __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time                                      */
+            uint32_t              : 7;
+            __IOM uint32_t MRTE   : 1;  /*!< [31..31] Maximum Read Turnaround Time Enable                              */
+        } CMDSPT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CETSM;          /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode)
+                                        *                  Register                                                   */
+
+        struct
+        {
+            uint32_t            : 8;
+            __IOM uint32_t FREQ : 8;   /*!< [15..8] Frequency Byte                                                    */
+            __IOM uint32_t INAC : 8;   /*!< [23..16] Inaccuracy Byte                                                  */
+            uint32_t            : 8;
+        } CETSM_b;
+    };
+    __IM uint32_t RESERVED28[2];
+
+    union
+    {
+        __IOM uint32_t BITCNT;         /*!< (@ 0x00000380) Bit Count Register                                         */
+
+        struct
+        {
+            __IOM uint32_t BCNT  : 5;  /*!< [4..0] Bit Counter                                                        */
+            uint32_t             : 2;
+            __OM uint32_t BCNTWP : 1;  /*!< [7..7] BCNT Write Protect                                                 */
+            uint32_t             : 24;
+        } BITCNT_b;
+    };
+    __IM uint32_t RESERVED29[4];
+
+    union
+    {
+        __IM uint32_t NQSTLV;          /*!< (@ 0x00000394) Normal Queue Status Level Register                         */
+
+        struct
+        {
+            __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level                                    */
+            __IM uint32_t RSPQLV  : 8; /*!< [15..8] Normal Response Queue Level                                       */
+            __IM uint32_t IBIQLV  : 8; /*!< [23..16] Normal IBI Queue Level                                           */
+            __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count                                          */
+            uint32_t              : 3;
+        } NQSTLV_b;
+    };
+
+    union
+    {
+        __IM uint32_t NDBSTLV0;        /*!< (@ 0x00000398) Normal Data Buffer Status Level Register                   */
+
+        struct
+        {
+            __IM uint32_t TDBFLV : 8;  /*!< [7..0] Normal Transmit Data Buffer Free Level                             */
+            __IM uint32_t RDBLV  : 8;  /*!< [15..8] Normal Receive Data Buffer Level                                  */
+            uint32_t             : 16;
+        } NDBSTLV0_b;
+    };
+    __IM uint32_t RESERVED30[9];
+
+    union
+    {
+        __IM uint32_t NRSQSTLV;        /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register          */
+
+        struct
+        {
+            __IM uint32_t RSQLV : 8;   /*!< [7..0] Normal Receive Status Queue Level                                  */
+            uint32_t            : 24;
+        } NRSQSTLV_b;
+    };
+    __IM uint32_t RESERVED31[2];
+
+    union
+    {
+        __IM uint32_t PRSTDBG;         /*!< (@ 0x000003CC) Present State Debug Register                               */
+
+        struct
+        {
+            __IM uint32_t SCILV : 1;   /*!< [0..0] SCL Line Signal Level                                              */
+            __IM uint32_t SDILV : 1;   /*!< [1..1] SDA Line Signal Level                                              */
+            __IM uint32_t SCOLV : 1;   /*!< [2..2] SCL Output Level                                                   */
+            __IM uint32_t SDOLV : 1;   /*!< [3..3] SDA Output Level                                                   */
+            uint32_t            : 28;
+        } PRSTDBG_b;
+    };
+
+    union
+    {
+        __IM uint32_t MSERRCNT;        /*!< (@ 0x000003D0) Master Error Counters Register                             */
+
+        struct
+        {
+            __IM uint32_t M2ECNT : 8;  /*!< [7..0] M2 Error Counter                                                   */
+            uint32_t             : 24;
+        } MSERRCNT_b;
+    };
+} R_I3C0_Type;                         /*!< Size = 980 (0x3d4)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                        R_MPU_SPMON                                        ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief CPU Stack Pointer Monitor (R_MPU_SPMON)
+ */
+
+typedef struct                         /*!< (@ 0x40000D00) R_MPU_SPMON Structure                                      */
+{
+    __IOM R_MPU_SPMON_SP_Type SP[2];   /*!< (@ 0x00000000) Stack Pointer Monitor                                      */
+} R_MPU_SPMON_Type;                    /*!< Size = 32 (0x20)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MSTP                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief System-Module Stop (R_MSTP)
+ */
+
+typedef struct                          /*!< (@ 0x40084000) R_MSTP Structure                                           */
+{
+    union
+    {
+        __IOM uint32_t MSTPCRA;         /*!< (@ 0x00000000) Module Stop Control Register A                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPA0  : 1; /*!< [0..0] RAM0 Module Stop                                                   */
+            uint32_t               : 6;
+            __IOM uint32_t MSTPA7  : 1; /*!< [7..7] Standby RAM Module Stop                                            */
+            uint32_t               : 14;
+            __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop              */
+            uint32_t               : 9;
+        } MSTPCRA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRB;        /*!< (@ 0x00000004) Module Stop Control Register B                             */
+
+        struct
+        {
+            uint32_t               : 1;
+            __IOM uint32_t MSTPB1  : 1; /*!< [1..1] RCAN1 Module Stop                                                  */
+            __IOM uint32_t MSTPB2  : 1; /*!< [2..2] RCAN0 Module Stop                                                  */
+            __IOM uint32_t MSTPB3  : 1; /*!< [3..3] RCEC Module Stop                                                   */
+            uint32_t               : 1;
+            __IOM uint32_t MSTPB5  : 1; /*!< [5..5] IrDA Module Stop                                                   */
+            __IOM uint32_t MSTPB6  : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop                     */
+            __IOM uint32_t MSTPB7  : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop                                    */
+            __IOM uint32_t MSTPB8  : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop                                    */
+            __IOM uint32_t MSTPB9  : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop                                */
+            uint32_t               : 1;
+            __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop                */
+            __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop                */
+            __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop                                   */
+            __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop                                   */
+            __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop                                   */
+            __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Octa Memory Controller Module Stop                               */
+            uint32_t               : 1;
+            __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop                          */
+            __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop                        */
+            uint32_t               : 2;
+            __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop                     */
+            __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop                     */
+            __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop                     */
+            __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop                     */
+            __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop                     */
+            __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop                     */
+            __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop                     */
+            __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop                     */
+            __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop                     */
+            __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop                     */
+        } MSTPCRB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRC;         /*!< (@ 0x00000008) Module Stop Control Register C                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPC0  : 1; /*!< [0..0] CAC Module Stop                                                    */
+            __IOM uint32_t MSTPC1  : 1; /*!< [1..1] CRC Calculator Module Stop                                         */
+            __IOM uint32_t MSTPC2  : 1; /*!< [2..2] Parallel Data Capture Module Stop                                  */
+            __IOM uint32_t MSTPC3  : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop                          */
+            __IOM uint32_t MSTPC4  : 1; /*!< [4..4] Segment LCD Controller Module Stop                                 */
+            __IOM uint32_t MSTPC5  : 1; /*!< [5..5] JPEG codec engine Module Stop                                      */
+            __IOM uint32_t MSTPC6  : 1; /*!< [6..6] 2DG engine Module Stop                                             */
+            __IOM uint32_t MSTPC7  : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop                         */
+            __IOM uint32_t MSTPC8  : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop                         */
+            __IOM uint32_t MSTPC9  : 1; /*!< [9..9] Sampling Rate Converter Module Stop                                */
+            uint32_t               : 1;
+            __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop           */
+            __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop           */
+            __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop                               */
+            __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop                                */
+            __IOM uint32_t MSTPC15 : 1; /*!< [15..15] 32-bit Multiply-Accumulator Module Stop                          */
+            uint32_t               : 4;
+            __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop                          */
+            __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop                               */
+            uint32_t               : 5;
+            __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop                                                */
+            __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop                              */
+            uint32_t               : 2;
+            __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop                                                  */
+        } MSTPCRC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRD;         /*!< (@ 0x0000000C) Module Stop Control Register D                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPD0 : 1;  /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module
+                                         *   Stop                                                                      */
+            __IOM uint32_t MSTPD1 : 1;  /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module
+                                         *   Stop                                                                      */
+            __IOM uint32_t MSTPD2 : 1;  /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state
+                                         *   when the count source is either of PCLKB, PCLKB/2 or PCLKB/8.
+                                         *   In case the count source is sub-clock or LOCO, this bit
+                                         *   should be set to 1 except when accessing the registers
+                                         *   of AGT1.                                                                  */
+            __IOM uint32_t MSTPD3 : 1;  /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state
+                                         *   when the count source is either of PCLKB, PCLKB/2 or PCLKB/8.
+                                         *   In case the count source is sub-clock or LOCO, this bit
+                                         *   should be set to 1 except when accessing the registers
+                                         *   of AGT0.                                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t MSTPD5 : 1;  /*!< [5..5] GPT Lower Module Stop                                              */
+            __IOM uint32_t MSTPD6 : 1;  /*!< [6..6] GPT Higher Module Stop                                             */
+            __IOM uint32_t MSTPD7 : 1;  /*!< [7..7] 16-bit Low Power Asynchronous General Purpose Timer 7
+                                         *   Module Stop                                                               */
+            __IOM uint32_t MSTPD8 : 1;  /*!< [8..8] 16-bit Low Power Asynchronous General Purpose Timer 6
+                                         *   Module Stop                                                               */
+            __IOM uint32_t MSTPD9 : 1;  /*!< [9..9] 16-bit Low Power Asynchronous General Purpose Timer 5
+                                         *   Module Stop                                                               */
+            __IOM uint32_t MSTPD10 : 1; /*!< [10..10] 16-bit Low Power Asynchronous General Purpose Timer
+                                         *   4 Module Stop                                                             */
+            __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop                         */
+            __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop                         */
+            __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop                         */
+            __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop                                                 */
+            __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop                               */
+            __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop                                 */
+            __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop                      */
+            __IOM uint32_t MSTPD18 : 1; /*!< [18..18] 16-bit Low Power Asynchronous General Purpose Timer
+                                         *   1 Module Stop                                                             */
+            __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop                                  */
+            __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop                                 */
+            uint32_t               : 1;
+            __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop                                   */
+            __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop                                              */
+            __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop                                              */
+            __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop                                              */
+            __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop                                              */
+            __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop                                              */
+            __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop                                              */
+            __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop                                        */
+            uint32_t               : 1;
+            __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop                                */
+        } MSTPCRD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRE;        /*!< (@ 0x00000010) Module Stop Control Register E                             */
+
+        struct
+        {
+            uint32_t               : 4;
+            __IOM uint32_t MSTPE4  : 1; /*!< [4..4] KINT Module Stop                                                   */
+            uint32_t               : 9;
+            __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module
+                                         *   Stop                                                                      */
+            __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module
+                                         *   Stop                                                                      */
+            uint32_t               : 6;
+            __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop                                                 */
+            __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop                                                 */
+            __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop                                                 */
+            __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop                                                 */
+            __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop                                                 */
+            __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop                                                 */
+            __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop                                                 */
+            __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop                                                 */
+            __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop                                                 */
+            __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop                                                 */
+        } MSTPCRE_b;
+    };
+} R_MSTP_Type;                          /*!< Size = 20 (0x14)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_PORT0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I/O Ports (R_PORT0)
+ */
+
+typedef struct                         /*!< (@ 0x40080000) R_PORT0 Structure                                          */
+{
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCNTR1;        /*!< (@ 0x00000000) Port Control Register 1                                    */
+
+            struct
+            {
+                __IOM uint32_t PDR  : 16; /*!< [15..0] Pmn Direction                                                     */
+                __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data                                                  */
+            } PCNTR1_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t PODR;           /*!< (@ 0x00000000) Output data register                                       */
+
+                struct
+                {
+                    __IOM uint16_t PODR0  : 1; /*!< [0..0] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR1  : 1; /*!< [1..1] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR2  : 1; /*!< [2..2] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR3  : 1; /*!< [3..3] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR4  : 1; /*!< [4..4] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR5  : 1; /*!< [5..5] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR6  : 1; /*!< [6..6] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR7  : 1; /*!< [7..7] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR8  : 1; /*!< [8..8] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR9  : 1; /*!< [9..9] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data                                                  */
+                    __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data                                                  */
+                    __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data                                                  */
+                    __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data                                                  */
+                    __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data                                                  */
+                    __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data                                                  */
+                } PODR_b;
+            };
+
+            union
+            {
+                __IOM uint16_t PDR;           /*!< (@ 0x00000002) Data direction register                                    */
+
+                struct
+                {
+                    __IOM uint16_t PDR0  : 1; /*!< [0..0] Pmn Direction                                                      */
+                    __IOM uint16_t PDR1  : 1; /*!< [1..1] Pmn Direction                                                      */
+                    __IOM uint16_t PDR2  : 1; /*!< [2..2] Pmn Direction                                                      */
+                    __IOM uint16_t PDR3  : 1; /*!< [3..3] Pmn Direction                                                      */
+                    __IOM uint16_t PDR4  : 1; /*!< [4..4] Pmn Direction                                                      */
+                    __IOM uint16_t PDR5  : 1; /*!< [5..5] Pmn Direction                                                      */
+                    __IOM uint16_t PDR6  : 1; /*!< [6..6] Pmn Direction                                                      */
+                    __IOM uint16_t PDR7  : 1; /*!< [7..7] Pmn Direction                                                      */
+                    __IOM uint16_t PDR8  : 1; /*!< [8..8] Pmn Direction                                                      */
+                    __IOM uint16_t PDR9  : 1; /*!< [9..9] Pmn Direction                                                      */
+                    __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction                                                    */
+                    __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction                                                    */
+                    __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction                                                    */
+                    __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction                                                    */
+                    __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction                                                    */
+                    __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction                                                    */
+                } PDR_b;
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCNTR2;        /*!< (@ 0x00000004) Port Control Register 2                                    */
+
+            struct
+            {
+                __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data                                                    */
+                __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data                                             */
+            } PCNTR2_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IM uint16_t EIDR;           /*!< (@ 0x00000004) Event input data register                                  */
+
+                struct
+                {
+                    __IM uint16_t EIDR0  : 1; /*!< [0..0] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR1  : 1; /*!< [1..1] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR2  : 1; /*!< [2..2] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR3  : 1; /*!< [3..3] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR4  : 1; /*!< [4..4] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR5  : 1; /*!< [5..5] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR6  : 1; /*!< [6..6] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR7  : 1; /*!< [7..7] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR8  : 1; /*!< [8..8] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR9  : 1; /*!< [9..9] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data                                             */
+                    __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data                                             */
+                    __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data                                             */
+                    __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data                                             */
+                    __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data                                             */
+                    __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data                                             */
+                } EIDR_b;
+            };
+
+            union
+            {
+                __IM uint16_t PIDR;           /*!< (@ 0x00000006) Input data register                                        */
+
+                struct
+                {
+                    __IM uint16_t PIDR0  : 1; /*!< [0..0] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR1  : 1; /*!< [1..1] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR2  : 1; /*!< [2..2] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR3  : 1; /*!< [3..3] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR4  : 1; /*!< [4..4] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR5  : 1; /*!< [5..5] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR6  : 1; /*!< [6..6] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR7  : 1; /*!< [7..7] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR8  : 1; /*!< [8..8] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR9  : 1; /*!< [9..9] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data                                                   */
+                    __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data                                                   */
+                    __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data                                                   */
+                    __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data                                                   */
+                    __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data                                                   */
+                    __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data                                                   */
+                } PIDR_b;
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __OM uint32_t PCNTR3;        /*!< (@ 0x00000008) Port Control Register 3                                    */
+
+            struct
+            {
+                __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set                                                    */
+                __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset                                                 */
+            } PCNTR3_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __OM uint16_t PORR;           /*!< (@ 0x00000008) Output set register                                        */
+
+                struct
+                {
+                    __OM uint16_t PORR0  : 1; /*!< [0..0] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR1  : 1; /*!< [1..1] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR2  : 1; /*!< [2..2] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR3  : 1; /*!< [3..3] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR4  : 1; /*!< [4..4] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR5  : 1; /*!< [5..5] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR6  : 1; /*!< [6..6] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR7  : 1; /*!< [7..7] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR8  : 1; /*!< [8..8] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR9  : 1; /*!< [9..9] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset                                                 */
+                    __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset                                                 */
+                    __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset                                                 */
+                    __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset                                                 */
+                    __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset                                                 */
+                    __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset                                                 */
+                } PORR_b;
+            };
+
+            union
+            {
+                __OM uint16_t POSR;           /*!< (@ 0x0000000A) Output reset register                                      */
+
+                struct
+                {
+                    __OM uint16_t POSR0  : 1; /*!< [0..0] Pmn Output Set                                                     */
+                    __OM uint16_t POSR1  : 1; /*!< [1..1] Pmn Output Set                                                     */
+                    __OM uint16_t POSR2  : 1; /*!< [2..2] Pmn Output Set                                                     */
+                    __OM uint16_t POSR3  : 1; /*!< [3..3] Pmn Output Set                                                     */
+                    __OM uint16_t POSR4  : 1; /*!< [4..4] Pmn Output Set                                                     */
+                    __OM uint16_t POSR5  : 1; /*!< [5..5] Pmn Output Set                                                     */
+                    __OM uint16_t POSR6  : 1; /*!< [6..6] Pmn Output Set                                                     */
+                    __OM uint16_t POSR7  : 1; /*!< [7..7] Pmn Output Set                                                     */
+                    __OM uint16_t POSR8  : 1; /*!< [8..8] Pmn Output Set                                                     */
+                    __OM uint16_t POSR9  : 1; /*!< [9..9] Pmn Output Set                                                     */
+                    __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set                                                   */
+                    __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set                                                   */
+                    __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set                                                   */
+                    __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set                                                   */
+                    __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set                                                   */
+                    __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set                                                   */
+                } POSR_b;
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCNTR4;        /*!< (@ 0x0000000C) Port Control Register 4                                    */
+
+            struct
+            {
+                __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set                                              */
+                __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset                                           */
+            } PCNTR4_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t EORR;           /*!< (@ 0x0000000C) Event output set register                                  */
+
+                struct
+                {
+                    __IOM uint16_t EORR0  : 1; /*!< [0..0] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR1  : 1; /*!< [1..1] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR2  : 1; /*!< [2..2] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR3  : 1; /*!< [3..3] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR4  : 1; /*!< [4..4] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR5  : 1; /*!< [5..5] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR6  : 1; /*!< [6..6] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR7  : 1; /*!< [7..7] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR8  : 1; /*!< [8..8] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR9  : 1; /*!< [9..9] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset                                           */
+                    __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset                                           */
+                    __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset                                           */
+                    __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset                                           */
+                    __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset                                           */
+                    __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset                                           */
+                } EORR_b;
+            };
+
+            union
+            {
+                __IOM uint16_t EOSR;           /*!< (@ 0x0000000E) Event output reset register                                */
+
+                struct
+                {
+                    __IOM uint16_t EOSR0  : 1; /*!< [0..0] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR1  : 1; /*!< [1..1] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR2  : 1; /*!< [2..2] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR3  : 1; /*!< [3..3] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR4  : 1; /*!< [4..4] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR5  : 1; /*!< [5..5] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR6  : 1; /*!< [6..6] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR7  : 1; /*!< [7..7] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR8  : 1; /*!< [8..8] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR9  : 1; /*!< [9..9] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set                                             */
+                    __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set                                             */
+                    __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set                                             */
+                    __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set                                             */
+                    __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set                                             */
+                    __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set                                             */
+                } EOSR_b;
+            };
+        };
+    };
+} R_PORT0_Type;                        /*!< Size = 16 (0x10)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_PFS                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I/O Ports-PFS (R_PFS)
+ */
+
+typedef struct                           /*!< (@ 0x40080800) R_PFS Structure                                            */
+{
+    union
+    {
+        __IOM R_PFS_PORT_Type  PORT[15]; /*!< (@ 0x00000000) Port [0..14]                                               */
+        __IOM R_PFS_VLSEL_Type VLSEL;    /*!< (@ 0x00000000) VLSEL                                                      */
+    };
+} R_PFS_Type;                            /*!< Size = 960 (0x3c0)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_PMISC                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I/O Ports-MISC (R_PMISC)
+ */
+
+typedef struct                         /*!< (@ 0x40080D00) R_PMISC Structure                                          */
+{
+    union
+    {
+        __IOM uint8_t PFENET;          /*!< (@ 0x00000000) Ethernet Control Register                                  */
+
+        struct
+        {
+            uint8_t                : 4;
+            __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0                                          */
+            __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1                                          */
+            uint8_t                : 2;
+        } PFENET_b;
+    };
+    __IM uint8_t RESERVED[2];
+
+    union
+    {
+        __IOM uint8_t PWPR;            /*!< (@ 0x00000003) Write-Protect Register                                     */
+
+        struct
+        {
+            uint8_t             : 6;
+            __IOM uint8_t PFSWE : 1;   /*!< [6..6] PmnPFS Register Write                                              */
+            __IOM uint8_t B0WI  : 1;   /*!< [7..7] PFSWE Bit Write Disable                                            */
+        } PWPR_b;
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        __IOM uint8_t PWPRS;           /*!< (@ 0x00000005) Write-Protect Register for Secure                          */
+
+        struct
+        {
+            uint8_t             : 6;
+            __IOM uint8_t PFSWE : 1;    /*!< [6..6] PmnPFS Register Write                                              */
+            __IOM uint8_t B0WI  : 1;    /*!< [7..7] PFSWE Bit Write Disable                                            */
+        } PWPRS_b;
+    };
+    __IM uint16_t            RESERVED2[5];
+    __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register                         */
+} R_PMISC_Type;                         /*!< Size = 40 (0x28)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_QSPI                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Quad Serial Peripheral Interface (R_QSPI)
+ */
+
+typedef struct                         /*!< (@ 0x64000000) R_QSPI Structure                                           */
+{
+    union
+    {
+        __IOM uint32_t SFMSMD;         /*!< (@ 0x00000000) Transfer Mode Control Register                             */
+
+        struct
+        {
+            __IOM uint32_t SFMRM  : 3; /*!< [2..0] Serial interface read mode selection                               */
+            uint32_t              : 1;
+            __IOM uint32_t SFMSE  : 2; /*!< [5..4] Selection of the prefetch function                                 */
+            __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function                                 */
+            __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations
+                                        *   other than on byte boundaries                                             */
+            __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by
+                                        *   input to CFGMD3.                                                          */
+            __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for
+                                        *   the serial interface                                                      */
+            __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission                     */
+            __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission                    */
+            uint32_t              : 3;
+            __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection.                                 */
+            uint32_t              : 16;
+        } SFMSMD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SFMSSC;         /*!< (@ 0x00000004) Chip Selection Control Register                            */
+
+        struct
+        {
+            __IOM uint32_t SFMSW  : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal         */
+            __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection                               */
+            __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection                                */
+            uint32_t              : 26;
+        } SFMSSC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SFMSKC;         /*!< (@ 0x00000008) Clock Control Register                                     */
+
+        struct
+        {
+            __IOM uint32_t SFMDV : 5;  /*!< [4..0] Serial interface reference cycle selection (* Pay attention
+                                        *   to the irregularity.)NOTE: When PCLKA multiplied by an
+                                        *   odd number is selected, the high-level width of the SCK
+                                        *   signal is longer than the low-level width by 1 x PCLKA
+                                        *   before duty ratio correction.                                             */
+            __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the
+                                        *   SCK signal                                                                */
+            uint32_t : 26;
+        } SFMSKC_b;
+    };
+
+    union
+    {
+        __IM uint32_t SFMSST;          /*!< (@ 0x0000000C) Status Register                                            */
+
+        struct
+        {
+            __IM uint32_t PFCNT : 5;   /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010
+                                        *   (No combination other than the above is available.)                       */
+            uint32_t            : 1;
+            __IM uint32_t PFFUL : 1;   /*!< [6..6] Prefetch buffer state                                              */
+            __IM uint32_t PFOFF : 1;   /*!< [7..7] Prefetch function operation state                                  */
+            uint32_t            : 24;
+        } SFMSST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SFMCOM;         /*!< (@ 0x00000010) Communication Port Register                                */
+
+        struct
+        {
+            __IOM uint32_t SFMD : 8;   /*!< [7..0] Port for direct communication with the SPI bus.Input/output
+                                        *   to and from this port is converted to a SPIbus cycle. This
+                                        *   port is accessible in the direct communication mode (DCOM=1)
+                                        *   only.Access to this port is ignored in the ROM access mode.               */
+            uint32_t : 24;
+        } SFMCOM_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SFMCMD;         /*!< (@ 0x00000014) Communication Mode Control Register                        */
+
+        struct
+        {
+            __IOM uint32_t DCOM : 1;   /*!< [0..0] Selection of a mode of communication with the SPI bus              */
+            uint32_t            : 31;
+        } SFMCMD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SFMCST;         /*!< (@ 0x00000018) Communication Status Register                              */
+
+        struct
+        {
+            __IM uint32_t COMBSY : 1;  /*!< [0..0] SPI bus cycle completion state in direct communication             */
+            uint32_t             : 6;
+            __IM uint32_t EROMR  : 1;  /*!< [7..7] Status of ROM access detection in the direct communication
+                                        *   modeNOTE: Writing of 0 only is possible. Writing of 1 is
+                                        *   ignored.                                                                  */
+            uint32_t : 24;
+        } SFMCST_b;
+    };
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t SFMSIC;         /*!< (@ 0x00000020) Instruction Code Register                                  */
+
+        struct
+        {
+            __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute                          */
+            uint32_t              : 24;
+        } SFMSIC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SFMSAC;         /*!< (@ 0x00000024) Address Mode Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t SFMAS  : 2; /*!< [1..0] Selection the number of address bits of the serial interface       */
+            uint32_t              : 2;
+            __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial
+                                        *   Interface address width is selected 4 bytes.                              */
+            uint32_t : 27;
+        } SFMSAC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SFMSDC;         /*!< (@ 0x00000028) Dummy Cycle Control Register                               */
+
+        struct
+        {
+            __IOM uint32_t SFMDN : 4;  /*!< [3..0] Selection of the number of dummy cycles of Fast Read
+                                        *   instructions                                                              */
+            uint32_t              : 2;
+            __IM uint32_t  SFMXST : 1; /*!< [6..6] XIP mode status                                                    */
+            __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission                                                */
+            __IOM uint32_t SFMXD  : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode)                      */
+            uint32_t              : 16;
+        } SFMSDC_b;
+    };
+    __IM uint32_t RESERVED1;
+
+    union
+    {
+        __IOM uint32_t SFMSPC;         /*!< (@ 0x00000030) SPI Protocol Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol
+                                        *   is required to be set by software separately.                             */
+            uint32_t              : 2;
+            __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch,
+                                        *   when Dual SPI protocol or Quad SPI protocol is selected.                  */
+            uint32_t : 27;
+        } SFMSPC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SFMPMD;         /*!< (@ 0x00000034) Port Control Register                                      */
+
+        struct
+        {
+            uint32_t              : 2;
+            __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin                                            */
+            uint32_t              : 29;
+        } SFMPMD_b;
+    };
+    __IM uint32_t RESERVED2[499];
+
+    union
+    {
+        __IOM uint32_t SFMCNT1;        /*!< (@ 0x00000804) External QSPI Address Register 1                           */
+
+        struct
+        {
+            uint32_t                : 26;
+            __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000
+                                          *   to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order
+                                          *   6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited.                   */
+        } SFMCNT1_b;
+    };
+} R_QSPI_Type;                           /*!< Size = 2056 (0x808)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                           R_RTC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Realtime Clock (R_RTC)
+ */
+
+typedef struct                         /*!< (@ 0x40083000) R_RTC Structure                                            */
+{
+    union
+    {
+        __IM uint8_t R64CNT;           /*!< (@ 0x00000000) 64-Hz Counter                                              */
+
+        struct
+        {
+            __IM uint8_t F64HZ : 1;    /*!< [0..0] 64Hz                                                               */
+            __IM uint8_t F32HZ : 1;    /*!< [1..1] 32Hz                                                               */
+            __IM uint8_t F16HZ : 1;    /*!< [2..2] 16Hz                                                               */
+            __IM uint8_t F8HZ  : 1;    /*!< [3..3] 8Hz                                                                */
+            __IM uint8_t F4HZ  : 1;    /*!< [4..4] 4Hz                                                                */
+            __IM uint8_t F2HZ  : 1;    /*!< [5..5] 2Hz                                                                */
+            __IM uint8_t F1HZ  : 1;    /*!< [6..6] 1Hz                                                                */
+            uint8_t            : 1;
+        } R64CNT_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RSECCNT;       /*!< (@ 0x00000002) Second Counter                                             */
+
+            struct
+            {
+                __IOM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When
+                                          *   a carry is generated, 1 is added to the tens place.                       */
+                __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting.         */
+                uint8_t             : 1;
+            } RSECCNT_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT0;         /*!< (@ 0x00000002) Binary Counter 0                                           */
+
+            struct
+            {
+                __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary
+                                          *   counter b7 to b0.                                                         */
+            } BCNT0_b;
+        };
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RMINCNT;       /*!< (@ 0x00000004) Minute Counter                                             */
+
+            struct
+            {
+                __IOM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When
+                                          *   a carry is generated, 1 is added to the tens place.                       */
+                __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting.         */
+                uint8_t             : 1;
+            } RMINCNT_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT1;         /*!< (@ 0x00000004) Binary Counter 1                                           */
+
+            struct
+            {
+                __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary
+                                          *   counter b15 to b8.                                                        */
+            } BCNT1_b;
+        };
+    };
+    __IM uint8_t RESERVED2;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RHRCNT;       /*!< (@ 0x00000006) Hour Counter                                               */
+
+            struct
+            {
+                __IOM uint8_t HR1 : 4;  /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a
+                                         *   carry is generated, 1 is added to the tens place.                         */
+                __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from
+                                         *   the ones place.                                                           */
+                __IOM uint8_t PM : 1;   /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
+                uint8_t          : 1;
+            } RHRCNT_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT2;         /*!< (@ 0x00000006) Binary Counter 2                                           */
+
+            struct
+            {
+                __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary
+                                          *   counter b23 to b16.                                                       */
+            } BCNT2_b;
+        };
+    };
+    __IM uint8_t RESERVED3;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RWKCNT;       /*!< (@ 0x00000008) Day-of-Week Counter                                        */
+
+            struct
+            {
+                __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
+                uint8_t            : 5;
+            } RWKCNT_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT3;         /*!< (@ 0x00000008) Binary Counter 3                                           */
+
+            struct
+            {
+                __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary
+                                          *   counter b31 to b24.                                                       */
+            } BCNT3_b;
+        };
+    };
+    __IM uint8_t RESERVED4;
+
+    union
+    {
+        __IOM uint8_t RDAYCNT;         /*!< (@ 0x0000000A) Day Counter                                                */
+
+        struct
+        {
+            __IOM uint8_t DATE1 : 4;   /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry
+                                        *   is generated, 1 is added to the tens place.                               */
+            __IOM uint8_t DATE10 : 2;  /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the
+                                        *   ones place.                                                               */
+            uint8_t : 2;
+        } RDAYCNT_b;
+    };
+    __IM uint8_t RESERVED5;
+
+    union
+    {
+        __IOM uint8_t RMONCNT;         /*!< (@ 0x0000000C) Month Counter                                              */
+
+        struct
+        {
+            __IOM uint8_t MON1 : 4;    /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When
+                                        *   a carry is generated, 1 is added to the tens place.                       */
+            __IOM uint8_t MON10 : 1;   /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from
+                                        *   the ones place.                                                           */
+            uint8_t : 3;
+        } RMONCNT_b;
+    };
+    __IM uint8_t RESERVED6;
+
+    union
+    {
+        __IOM uint16_t RYRCNT;         /*!< (@ 0x0000000E) Year Counter                                               */
+
+        struct
+        {
+            __IOM uint16_t YR1 : 4;    /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a
+                                        *   carry is generated, 1 is added to the tens place.                         */
+            __IOM uint16_t YR10 : 4;   /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from
+                                        *   ones place. When a carry is generated in the tens place,
+                                        *   1 is added to the hundreds place.                                         */
+            uint16_t : 8;
+        } RYRCNT_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RSECAR;        /*!< (@ 0x00000010) Second Alarm Register                                      */
+
+            struct
+            {
+                __OM uint8_t  SEC1  : 4; /*!< [3..0] 1-Second Value for the ones place of seconds                       */
+                __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds                     */
+                __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
+            } RSECAR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT0AR;         /*!< (@ 0x00000010) Binary Counter 0 Alarm Register                            */
+
+            struct
+            {
+                __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register
+                                            *   corresponding to 32-bit binary counter b7 to b0.                          */
+            } BCNT0AR_b;
+        };
+    };
+    __IM uint8_t RESERVED7;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RMINAR;        /*!< (@ 0x00000012) Minute Alarm Register                                      */
+
+            struct
+            {
+                __IOM uint8_t MIN1  : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes                 */
+                __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes                */
+                __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
+            } RMINAR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT1AR;         /*!< (@ 0x00000012) Binary Counter 1 Alarm Register                            */
+
+            struct
+            {
+                __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register
+                                            *   corresponding to 32-bit binary counter b15 to b8.                         */
+            } BCNT1AR_b;
+        };
+    };
+    __IM uint8_t RESERVED8;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RHRAR;        /*!< (@ 0x00000014) Hour Alarm Register                                        */
+
+            struct
+            {
+                __IOM uint8_t HR1  : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours                     */
+                __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours                    */
+                __IOM uint8_t PM   : 1; /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
+                __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
+            } RHRAR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT2AR;         /*!< (@ 0x00000014) Binary Counter 2 Alarm Register                            */
+
+            struct
+            {
+                __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary
+                                            *   counter b23 to b16.                                                       */
+            } BCNT2AR_b;
+        };
+    };
+    __IM uint8_t RESERVED9;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RWKAR;        /*!< (@ 0x00000016) Day-of-Week Alarm Register                                 */
+
+            struct
+            {
+                __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
+                uint8_t            : 4;
+                __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
+            } RWKAR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT3AR;         /*!< (@ 0x00000016) Binary Counter 3 Alarm Register                            */
+
+            struct
+            {
+                __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary
+                                            *   counter b31 to b24.                                                       */
+            } BCNT3AR_b;
+        };
+    };
+    __IM uint8_t RESERVED10;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RDAYAR;         /*!< (@ 0x00000018) Date Alarm Register                                        */
+
+            struct
+            {
+                __IOM uint8_t DATE1  : 4; /*!< [3..0] 1 Day Value for the ones place of days                             */
+                __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days                           */
+                uint8_t              : 1;
+                __IOM uint8_t ENB    : 1; /*!< [7..7] Compare enable                                                     */
+            } RDAYAR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT0AER;    /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register                     */
+
+            struct
+            {
+                __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register
+                                        *   for setting the alarm enable corresponding to 32-bit binary
+                                        *   counter b7 to b0.                                                         */
+            } BCNT0AER_b;
+        };
+    };
+    __IM uint8_t RESERVED11;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RMONAR;        /*!< (@ 0x0000001A) Month Alarm Register                                       */
+
+            struct
+            {
+                __IOM uint8_t MON1  : 4; /*!< [3..0] 1 Month Value for the ones place of months                         */
+                __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months                       */
+                uint8_t             : 2;
+                __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
+            } RMONAR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT1AER;    /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register                     */
+
+            struct
+            {
+                __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register
+                                        *   for setting the alarm enable corresponding to 32-bit binary
+                                        *   counter b15 to b8.                                                        */
+            } BCNT1AER_b;
+        };
+    };
+    __IM uint8_t RESERVED12;
+
+    union
+    {
+        union
+        {
+            __IOM uint16_t RYRAR;        /*!< (@ 0x0000001C) Year Alarm Register                                        */
+
+            struct
+            {
+                __IOM uint16_t YR1  : 4; /*!< [3..0] 1 Year Value for the ones place of years                           */
+                __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years                         */
+                uint16_t            : 8;
+            } RYRAR_b;
+        };
+
+        union
+        {
+            __IOM uint16_t BCNT2AER;    /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register                     */
+
+            struct
+            {
+                __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register
+                                         *   for setting the alarm enable corresponding to 32-bit binary
+                                         *   counter b23 to b16.                                                       */
+                uint16_t : 8;
+            } BCNT2AER_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RYRAREN;     /*!< (@ 0x0000001E) Year Alarm Enable Register                                 */
+
+            struct
+            {
+                uint8_t           : 7;
+                __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable                                                     */
+            } RYRAREN_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT3AER;    /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register                     */
+
+            struct
+            {
+                __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register
+                                        *   for setting the alarm enable corresponding to 32-bit binary
+                                        *   counter b31 to b24.                                                       */
+            } BCNT3AER_b;
+        };
+    };
+    __IM uint8_t  RESERVED13;
+    __IM uint16_t RESERVED14;
+
+    union
+    {
+        __IOM uint8_t RCR1;            /*!< (@ 0x00000022) RTC Control Register 1                                     */
+
+        struct
+        {
+            __IOM uint8_t AIE   : 1;   /*!< [0..0] Alarm Interrupt Enable                                             */
+            __IOM uint8_t CIE   : 1;   /*!< [1..1] Carry Interrupt Enable                                             */
+            __IOM uint8_t PIE   : 1;   /*!< [2..2] Periodic Interrupt Enable                                          */
+            __IOM uint8_t RTCOS : 1;   /*!< [3..3] RTCOUT Output Select                                               */
+            __IOM uint8_t PES   : 4;   /*!< [7..4] Periodic Interrupt Select                                          */
+        } RCR1_b;
+    };
+    __IM uint8_t RESERVED15;
+
+    union
+    {
+        __IOM uint8_t RCR2;            /*!< (@ 0x00000024) RTC Control Register 2                                     */
+
+        struct
+        {
+            __IOM uint8_t START : 1;   /*!< [0..0] Start                                                              */
+            __IOM uint8_t RESET : 1;   /*!< [1..1] RTC Software Reset                                                 */
+            __IOM uint8_t ADJ30 : 1;   /*!< [2..2] 30-Second Adjustment                                               */
+            __IOM uint8_t RTCOE : 1;   /*!< [3..3] RTCOUT Output Enable                                               */
+            __IOM uint8_t AADJE : 1;   /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected,
+                                        *   the setting of this bit is disabled.)                                     */
+            __IOM uint8_t AADJP : 1;   /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock
+                                        *   is selected, the setting of this bit is disabled.)                        */
+            __IOM uint8_t HR24  : 1;   /*!< [6..6] Hours Mode                                                         */
+            __IOM uint8_t CNTMD : 1;   /*!< [7..7] Count Mode Select                                                  */
+        } RCR2_b;
+    };
+    __IM uint8_t  RESERVED16;
+    __IM uint16_t RESERVED17;
+
+    union
+    {
+        __IOM uint8_t RCR4;            /*!< (@ 0x00000028) RTC Control Register 4                                     */
+
+        struct
+        {
+            __IOM uint8_t RCKSEL : 1;  /*!< [0..0] Count Source Select                                                */
+            uint8_t              : 6;
+            __IOM uint8_t ROPSEL : 1;  /*!< [7..7] RTC Operation Mode Select                                          */
+        } RCR4_b;
+    };
+    __IM uint8_t RESERVED18;
+
+    union
+    {
+        __IOM uint16_t RFRH;           /*!< (@ 0x0000002A) Frequency Register H                                       */
+
+        struct
+        {
+            __IOM uint16_t RFC16 : 1;  /*!< [0..0] Frequency Comparison Value (b16) To generate the operating
+                                        *   clock from the LOCOclock, this bit sets the comparison
+                                        *   value of the 128-Hz clock cycle.                                          */
+            uint16_t : 15;
+        } RFRH_b;
+    };
+
+    union
+    {
+        __IOM uint16_t RFRL;           /*!< (@ 0x0000002C) Frequency Register L                                       */
+
+        struct
+        {
+            __IOM uint16_t RFC : 16;   /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating
+                                        *   clock from the main clock, this bit sets the comparison
+                                        *   value of the 128-Hz clock cycle.                                          */
+        } RFRL_b;
+    };
+
+    union
+    {
+        __IOM uint8_t RADJ;            /*!< (@ 0x0000002E) Time Error Adjustment Register                             */
+
+        struct
+        {
+            __IOM uint8_t ADJ : 6;     /*!< [5..0] Adjustment Value These bits specify the adjustment value
+                                        *   from the prescaler.                                                       */
+            __IOM uint8_t PMADJ : 2;   /*!< [7..6] Plus-Minus                                                         */
+        } RADJ_b;
+    };
+    __IM uint8_t           RESERVED19;
+    __IM uint16_t          RESERVED20[8];
+    __IOM R_RTC_RTCCR_Type RTCCR[3];   /*!< (@ 0x00000040) Time Capture Control Register                              */
+    __IM uint16_t          RESERVED21[5];
+    __IOM R_RTC_CP_Type    CP[3];      /*!< (@ 0x00000050) Capture registers                                          */
+} R_RTC_Type;                          /*!< Size = 128 (0x80)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SCI0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Serial Communications Interface (R_SCI0)
+ */
+
+typedef struct                         /*!< (@ 0x40118000) R_SCI0 Structure                                           */
+{
+    union
+    {
+        union
+        {
+            __IOM uint8_t SMR;          /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0)                       */
+
+            struct
+            {
+                __IOM uint8_t CKS  : 2; /*!< [1..0] Clock Select                                                       */
+                __IOM uint8_t MP   : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode)              */
+                __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode)                   */
+                __IOM uint8_t PM   : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
+                __IOM uint8_t PE   : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
+                __IOM uint8_t CHR  : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode)                  */
+                __IOM uint8_t CM   : 1; /*!< [7..7] Communication Mode                                                 */
+            } SMR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t SMR_SMCI;    /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1)                       */
+
+            struct
+            {
+                __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select                                                       */
+                __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode)                  */
+                __IOM uint8_t PM  : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
+                __IOM uint8_t PE  : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
+                __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode                                                */
+                __IOM uint8_t GM  : 1; /*!< [7..7] GSM Mode                                                           */
+            } SMR_SMCI_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint8_t BRR;             /*!< (@ 0x00000001) Bit Rate Register                                          */
+
+        struct
+        {
+            __IOM uint8_t BRR : 8;     /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate.                */
+        } BRR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t SCR;          /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0)                    */
+
+            struct
+            {
+                __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
+                __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
+                __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous
+                                         *   mode when SMR.MP = 1)                                                     */
+                __IOM uint8_t RE  : 1;  /*!< [4..4] Receive Enable                                                     */
+                __IOM uint8_t TE  : 1;  /*!< [5..5] Transmit Enable                                                    */
+                __IOM uint8_t RIE : 1;  /*!< [6..6] Receive Interrupt Enable                                           */
+                __IOM uint8_t TIE : 1;  /*!< [7..7] Transmit Interrupt Enable                                          */
+            } SCR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t SCR_SMCI;     /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1)                     */
+
+            struct
+            {
+                __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
+                __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
+                __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable                                   */
+                __IOM uint8_t RE   : 1; /*!< [4..4] Receive Enable                                                     */
+                __IOM uint8_t TE   : 1; /*!< [5..5] Transmit Enable                                                    */
+                __IOM uint8_t RIE  : 1; /*!< [6..6] Receive Interrupt Enable                                           */
+                __IOM uint8_t TIE  : 1; /*!< [7..7] Transmit Interrupt Enable                                          */
+            } SCR_SMCI_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint8_t TDR;             /*!< (@ 0x00000003) Transmit Data Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TDR : 8;     /*!< [7..0] TDR is an 8-bit register that stores transmit data.                */
+        } TDR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t SSR;          /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)         */
+
+            struct
+            {
+                __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer                                       */
+                __IM uint8_t  MPB  : 1; /*!< [1..1] Multi-Processor                                                    */
+                __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
+                __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
+                __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
+                __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
+                __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
+                __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
+            } SSR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t SSR_FIFO;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1)         */
+
+            struct
+            {
+                __IOM uint8_t DR : 1;   /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including
+                                         *   multi-processor) and FIFO selected)                                       */
+                uint8_t            : 1;
+                __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
+                __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
+                __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
+                __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
+                __IOM uint8_t RDF  : 1; /*!< [6..6] Receive FIFO data full flag                                        */
+                __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag                                      */
+            } SSR_FIFO_b;
+        };
+
+        union
+        {
+            __IOM uint8_t SSR_SMCI;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1)                      */
+
+            struct
+            {
+                __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart
+                                         *   card interface mode.                                                      */
+                __IM uint8_t MPB : 1;   /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface
+                                         *   mode.                                                                     */
+                __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
+                __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
+                __IOM uint8_t ERS  : 1; /*!< [4..4] Error Signal Status Flag                                           */
+                __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
+                __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
+                __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
+            } SSR_SMCI_b;
+        };
+    };
+
+    union
+    {
+        __IM uint8_t RDR;              /*!< (@ 0x00000005) Receive Data Register                                      */
+
+        struct
+        {
+            __IM uint8_t RDR : 8;      /*!< [7..0] RDR is an 8-bit register that stores receive data.                 */
+        } RDR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SCMR;            /*!< (@ 0x00000006) Smart Card Mode Register                                   */
+
+        struct
+        {
+            __IOM uint8_t SMIF : 1;    /*!< [0..0] Smart Card Interface Mode Select                                   */
+            uint8_t            : 1;
+            __IOM uint8_t SINV : 1;    /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if
+                                        *   operation is to be in simple I2C mode.                                    */
+            __IOM uint8_t SDIR : 1;    /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The
+                                        *   setting is invalid and a fixed data length of 8 bits is
+                                        *   used in modes other than asynchronous mode.Set this bit
+                                        *   to 1 if operation is to be in simple I2C mode.                            */
+            __IOM uint8_t CHR1 : 1;    /*!< [4..4] Character Length 1(Only valid in asynchronous mode)                */
+            uint8_t            : 2;
+            __IOM uint8_t BCP2 : 1;    /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles
+                                        *   in combination with the SMR.BCP[1:0] bits                                 */
+        } SCMR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SEMR;            /*!< (@ 0x00000007) Serial Extended Mode Register                              */
+
+        struct
+        {
+            __IOM uint8_t ACS0 : 1;    /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in
+                                        *   asynchronous mode).                                                       */
+            __IOM uint8_t PADIS : 1;   /*!< [1..1] Preamble function Disable (Valid only in asynchronous
+                                        *   mode).                                                                    */
+            __IOM uint8_t BRME  : 1;   /*!< [2..2] Bit Rate Modulation Enable                                         */
+            __IOM uint8_t ABCSE : 1;   /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid
+                                        *   only in asynchronous mode and SCR.CKE[1]=0)                               */
+            __IOM uint8_t ABCS : 1;    /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous
+                                        *   mode)                                                                     */
+            __IOM uint8_t NFEN : 1;    /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should
+                                        *   be 0 without simple I2C mode and asynchronous mode.)In
+                                        *   asynchronous mode, for RXDn input only. In simple I2C mode,
+                                        *   for RXDn/TxDn input.                                                      */
+            __IOM uint8_t BGDM : 1;    /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid
+                                        *   the CKE[1] bit in SCR is 0 in asynchronous mode).                         */
+            __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only
+                                        *   in asynchronous mode)                                                     */
+        } SEMR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SNFR;            /*!< (@ 0x00000008) Noise Filter Setting Register                              */
+
+        struct
+        {
+            __IOM uint8_t NFCS : 3;    /*!< [2..0] Noise Filter Clock Select                                          */
+            uint8_t            : 5;
+        } SNFR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SIMR1;           /*!< (@ 0x00000009) I2C Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t IICM  : 1;   /*!< [0..0] Simple I2C Mode Select                                             */
+            uint8_t             : 2;
+            __IOM uint8_t IICDL : 5;   /*!< [7..3] SDA Delay Output SelectCycles below are of the clock
+                                        *   signal from the on-chip baud rate generator.                              */
+        } SIMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SIMR2;           /*!< (@ 0x0000000A) I2C Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select                                          */
+            __IOM uint8_t IICCSC  : 1; /*!< [1..1] Clock Synchronization                                              */
+            uint8_t               : 3;
+            __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data                                              */
+            uint8_t               : 2;
+        } SIMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SIMR3;              /*!< (@ 0x0000000B) I2C Mode Register 3                                        */
+
+        struct
+        {
+            __IOM uint8_t IICSTAREQ  : 1; /*!< [0..0] Start Condition Generation                                         */
+            __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation                                       */
+            __IOM uint8_t IICSTPREQ  : 1; /*!< [2..2] Stop Condition Generation                                          */
+            __IOM uint8_t IICSTIF    : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
+                                           *   Flag(When 0 is written to IICSTIF, it is cleared to 0.)                   */
+            __IOM uint8_t IICSDAS : 2;    /*!< [5..4] SDA Output Select                                                  */
+            __IOM uint8_t IICSCLS : 2;    /*!< [7..6] SCL Output Select                                                  */
+        } SIMR3_b;
+    };
+
+    union
+    {
+        __IM uint8_t SISR;             /*!< (@ 0x0000000C) I2C Status Register                                        */
+
+        struct
+        {
+            __IM uint8_t IICACKR : 1;  /*!< [0..0] ACK Reception Data Flag                                            */
+            uint8_t              : 7;
+        } SISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPMR;            /*!< (@ 0x0000000D) SPI Mode Register                                          */
+
+        struct
+        {
+            __IOM uint8_t SSE    : 1;  /*!< [0..0] SSn Pin Function Enable                                            */
+            __IOM uint8_t CTSE   : 1;  /*!< [1..1] CTS Enable                                                         */
+            __IOM uint8_t MSS    : 1;  /*!< [2..2] Master Slave Select                                                */
+            __IOM uint8_t CSTPEN : 1;  /*!< [3..3] CTS external pin Enable                                            */
+            __IOM uint8_t MFF    : 1;  /*!< [4..4] Mode Fault Flag                                                    */
+            uint8_t              : 1;
+            __IOM uint8_t CKPOL  : 1;  /*!< [6..6] Clock Polarity Select                                              */
+            __IOM uint8_t CKPH   : 1;  /*!< [7..7] Clock Phase Select                                                 */
+        } SPMR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint16_t TDRHL;         /*!< (@ 0x0000000E) Transmit 9-bit Data Register                               */
+
+            struct
+            {
+                __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data.             */
+            } TDRHL_b;
+        };
+
+        union
+        {
+            __OM uint16_t FTDRHL;       /*!< (@ 0x0000000E) Transmit FIFO Data Register HL                             */
+
+            struct
+            {
+                __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including
+                                         *   multi-processor) or clock synchronous mode, and FIFO selected)            */
+                __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous
+                                         *   mode and SMR.MP=1 and FIFO selected)                                      */
+                uint16_t : 6;
+            } FTDRHL_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __OM uint8_t FTDRH;         /*!< (@ 0x0000000E) Transmit FIFO Data Register H                              */
+
+                struct
+                {
+                    __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous
+                                             *   mode(including multi-processor) or clock synchronous mode,
+                                             *   and FIFO selected)                                                        */
+                    __OM uint8_t MPBT : 1;  /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous
+                                             *   mode and SMR.MP=1 and FIFO selected)                                      */
+                    uint8_t : 6;
+                } FTDRH_b;
+            };
+
+            union
+            {
+                __OM uint8_t FTDRL;         /*!< (@ 0x0000000F) Transmit FIFO Data Register L                              */
+
+                struct
+                {
+                    __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous
+                                             *   mode(including multi-processor) or clock synchronous mode,
+                                             *   and FIFO selected)                                                        */
+                } FTDRL_b;
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint16_t RDRHL;          /*!< (@ 0x00000010) Receive 9-bit Data Register                                */
+
+            struct
+            {
+                __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data.             */
+            } RDRHL_b;
+        };
+
+        union
+        {
+            __IM uint16_t FRDRHL;       /*!< (@ 0x00000010) Receive FIFO Data Register HL                              */
+
+            struct
+            {
+                __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including
+                                         *   multi-processor) or clock synchronous mode, and FIFO selected)            */
+                __IM uint16_t MPB : 1;  /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode
+                                         *   with SMR.MP=1 and FIFO selected) It can read multi-processor
+                                         *   bit corresponded to serial receive data(RDATA[8:0])                       */
+                __IM uint16_t DR   : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR)                    */
+                __IM uint16_t PER  : 1; /*!< [11..11] Parity error flag                                                */
+                __IM uint16_t FER  : 1; /*!< [12..12] Framing error flag                                               */
+                __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER)                       */
+                __IM uint16_t RDF  : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF)               */
+                uint16_t           : 1;
+            } FRDRHL_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IM uint8_t FRDRH;         /*!< (@ 0x00000010) Receive FIFO Data Register H                               */
+
+                struct
+                {
+                    __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including
+                                             *   multi-processor) or clock synchronous mode, and FIFO selected)            */
+                    __IM uint8_t MPB : 1;   /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode
+                                             *   with SMR.MP=1 and FIFO selected) It can read multi-processor
+                                             *   bit corresponded to serial receive data(RDATA[8:0])                       */
+                    __IM uint8_t DR   : 1;  /*!< [2..2] Receive data ready flag(It is same as SSR.DR)                      */
+                    __IM uint8_t PER  : 1;  /*!< [3..3] Parity error flag                                                  */
+                    __IM uint8_t FER  : 1;  /*!< [4..4] Framing error flag                                                 */
+                    __IM uint8_t ORER : 1;  /*!< [5..5] Overrun error flag(It is same as SSR.ORER)                         */
+                    __IM uint8_t RDF  : 1;  /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF)                 */
+                    uint8_t           : 1;
+                } FRDRH_b;
+            };
+
+            union
+            {
+                __IM uint8_t FRDRL;         /*!< (@ 0x00000011) Receive FIFO Data Register L                               */
+
+                struct
+                {
+                    __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including
+                                             *   multi-processor) or clock synchronous mode, and FIFO selected)NOTE:
+                                             *   When reading both of FRDRH register and FRDRL register,
+                                             *   please read by an order of the FRDRH register and the FRDRL
+                                             *   register.                                                                 */
+                } FRDRL_b;
+            };
+        };
+    };
+
+    union
+    {
+        __IOM uint8_t MDDR;            /*!< (@ 0x00000012) Modulation Duty Register                                   */
+
+        struct
+        {
+            __IOM uint8_t MDDR : 8;    /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register.           */
+        } MDDR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DCCR;            /*!< (@ 0x00000013) Data Compare Match Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t DCMF  : 1;   /*!< [0..0] Data Compare Match Flag                                            */
+            uint8_t             : 2;
+            __IOM uint8_t DPER  : 1;   /*!< [3..3] Data Compare Match Parity Error Flag                               */
+            __IOM uint8_t DFER  : 1;   /*!< [4..4] Data Compare Match Framing Error Flag                              */
+            uint8_t             : 1;
+            __IOM uint8_t IDSEL : 1;   /*!< [6..6] ID frame select(Valid only in asynchronous mode(including
+                                        *   multi-processor)                                                          */
+            __IOM uint8_t DCME : 1;    /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous
+                                        *   mode(including multi-processor)                                           */
+        } DCCR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t FCR;            /*!< (@ 0x00000014) FIFO Control Register                                      */
+
+        struct
+        {
+            __IOM uint16_t FM : 1;     /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including
+                                        *   multi-processor) or clock synchronous mode)                               */
+            __IOM uint16_t RFRST : 1;  /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1)           */
+            __IOM uint16_t TFRST : 1;  /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1)          */
+            __IOM uint16_t DRES  : 1;  /*!< [3..3] Receive data ready error select bit(When detecting a
+                                        *   reception data ready, the interrupt request is selected.)                 */
+            __IOM uint16_t TTRG : 4;   /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous
+                                        *   mode(including multi-processor) or clock synchronous mode)                */
+            __IOM uint16_t RTRG : 4;   /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous
+                                        *   mode(including multi-processor) or clock synchronous mode)                */
+            __IOM uint16_t RSTRG : 4;  /*!< [15..12] RTS Output Active Trigger Number Select(Valid only
+                                        *   in asynchronous mode(including multi-processor) or clock
+                                        *   synchronous mode)                                                         */
+        } FCR_b;
+    };
+
+    union
+    {
+        __IM uint16_t FDR;             /*!< (@ 0x00000016) FIFO Data Count Register                                   */
+
+        struct
+        {
+            __IM uint16_t R : 5;       /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive
+                                        *   data stored in FRDRH and FRDRL(Valid only in asynchronous
+                                        *   mode(including multi-processor) or clock synchronous mode,
+                                        *   while FCR.FM=1)                                                           */
+            uint16_t        : 3;
+            __IM uint16_t T : 5;       /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit
+                                        *   data stored in FTDRH and FTDRL(Valid only in asynchronous
+                                        *   mode(including multi-processor) or clock synchronous mode,
+                                        *   while FCR.FM=1)                                                           */
+            uint16_t : 3;
+        } FDR_b;
+    };
+
+    union
+    {
+        __IM uint16_t LSR;             /*!< (@ 0x00000018) Line Status Register                                       */
+
+        struct
+        {
+            __IM uint16_t ORER : 1;    /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including
+                                        *   multi-processor) or clock synchronous mode, and FIFO selected)            */
+            uint16_t           : 1;
+            __IM uint16_t FNUM : 5;    /*!< [6..2] Framing Error CountIndicates the quantity of data with
+                                        *   a framing error among the receive data stored in the receive
+                                        *   FIFO data register (FRDRH and FRDRL).                                     */
+            uint16_t           : 1;
+            __IM uint16_t PNUM : 5;    /*!< [12..8] Parity Error CountIndicates the quantity of data with
+                                        *   a parity error among the receive data stored in the receive
+                                        *   FIFO data register (FRDRH and FRDRL).                                     */
+            uint16_t : 3;
+        } LSR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t CDR;            /*!< (@ 0x0000001A) Compare Match Data Register                                */
+
+        struct
+        {
+            __IOM uint16_t CMPD : 9;   /*!< [8..0] Compare Match DataCompare data pattern for address match
+                                        *   wake-up function                                                          */
+            uint16_t : 7;
+        } CDR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPTR;            /*!< (@ 0x0000001C) Serial Port Register                                       */
+
+        struct
+        {
+            __IM uint8_t RXDMON : 1;   /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal
+                                        *   is shown.)                                                                */
+            __IOM uint8_t SPB2DT : 1;  /*!< [1..1] Serial port break data select bit(The output level of
+                                        *   TxD terminal is selected when SCR.TE = 0.)                                */
+            __IOM uint8_t SPB2IO : 1;  /*!< [2..2] Serial port break I/O bit(It's selected whether the value
+                                        *   of SPB2DT is output to TxD terminal.)                                     */
+            uint8_t            : 1;
+            __IOM uint8_t RINV : 1;    /*!< [4..4] RXD invert bit                                                     */
+            __IOM uint8_t TINV : 1;    /*!< [5..5] TXD invert bit                                                     */
+            __IOM uint8_t ASEN : 1;    /*!< [6..6] Adjust receive sampling timing enable                              */
+            __IOM uint8_t ATEN : 1;    /*!< [7..7] Adjust transmit timing enable                                      */
+        } SPTR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ACTR;            /*!< (@ 0x0000001D) Adjustment Communication Timing Register                   */
+
+        struct
+        {
+            __IOM uint8_t AST : 3;     /*!< [2..0] Adjustment value for receive Sampling Timing                       */
+            __IOM uint8_t AJD : 1;     /*!< [3..3] Adjustment Direction for receive sampling timing                   */
+            __IOM uint8_t ATT : 3;     /*!< [6..4] Adjustment value for Transmit timing                               */
+            __IOM uint8_t AET : 1;     /*!< [7..7] Adjustment edge for transmit timing                                */
+        } ACTR_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t ESMER;           /*!< (@ 0x00000020) Extended Serial Module Enable Register                     */
+
+        struct
+        {
+            __IOM uint8_t ESME : 1;    /*!< [0..0] Extended Serial Mode Enable                                        */
+            uint8_t            : 7;
+        } ESMER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CR0;             /*!< (@ 0x00000021) Control Register 0                                         */
+
+        struct
+        {
+            uint8_t             : 1;
+            __IM uint8_t  SFSF  : 1;   /*!< [1..1] Start Frame Status Flag                                            */
+            __IM uint8_t  RXDSF : 1;   /*!< [2..2] RXDXn Input Status Flag                                            */
+            __IOM uint8_t BRME  : 1;   /*!< [3..3] Bit Rate Measurement Enable                                        */
+            uint8_t             : 4;
+        } CR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CR1;             /*!< (@ 0x00000022) Control Register 1                                         */
+
+        struct
+        {
+            __IOM uint8_t BFE   : 1;   /*!< [0..0] Break Field Enable                                                 */
+            __IOM uint8_t CF0RE : 1;   /*!< [1..1] Control Field 0 Reception Enable                                   */
+            __IOM uint8_t CF1DS : 2;   /*!< [3..2] Control Field 1 Data Register Select                               */
+            __IOM uint8_t PIBE  : 1;   /*!< [4..4] Priority Interrupt Bit Enable                                      */
+            __IOM uint8_t PIBS  : 3;   /*!< [7..5] Priority Interrupt Bit Select                                      */
+        } CR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CR2;             /*!< (@ 0x00000023) Control Register 2                                         */
+
+        struct
+        {
+            __IOM uint8_t DFCS : 3;    /*!< [2..0] RXDXn Signal Digital Filter Clock Select                           */
+            uint8_t            : 1;
+            __IOM uint8_t BCCS : 2;    /*!< [5..4] Bus Collision Detection Clock Select                               */
+            __IOM uint8_t RTS  : 2;    /*!< [7..6] RXDXn Reception Sampling Timing Select                             */
+        } CR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CR3;             /*!< (@ 0x00000024) Control Register 3                                         */
+
+        struct
+        {
+            __IOM uint8_t SDST : 1;    /*!< [0..0] Start Frame Detection Start                                        */
+            uint8_t            : 7;
+        } CR3_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PCR;             /*!< (@ 0x00000025) Port Control Register                                      */
+
+        struct
+        {
+            __IOM uint8_t TXDXPS : 1;  /*!< [0..0] TXDXn Signal Polarity Select                                       */
+            __IOM uint8_t RXDXPS : 1;  /*!< [1..1] RXDXn Signal Polarity Select                                       */
+            uint8_t              : 2;
+            __IOM uint8_t SHARPS : 1;  /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select                                */
+            uint8_t              : 3;
+        } PCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICR;             /*!< (@ 0x00000026) Interrupt Control Register                                 */
+
+        struct
+        {
+            __IOM uint8_t BFDIE  : 1;  /*!< [0..0] Break Field Low Width Detected Interrupt Enable                    */
+            __IOM uint8_t CF0MIE : 1;  /*!< [1..1] Control Field 0 Match Detected Interrupt Enable                    */
+            __IOM uint8_t CF1MIE : 1;  /*!< [2..2] Control Field 1 Match Detected Interrupt Enable                    */
+            __IOM uint8_t PIBDIE : 1;  /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable                   */
+            __IOM uint8_t BCDIE  : 1;  /*!< [4..4] Bus Collision Detected Interrupt Enable                            */
+            __IOM uint8_t AEDIE  : 1;  /*!< [5..5] Valid Edge Detected Interrupt Enable                               */
+            uint8_t              : 2;
+        } ICR_b;
+    };
+
+    union
+    {
+        __IM uint8_t STR;              /*!< (@ 0x00000027) Status Register                                            */
+
+        struct
+        {
+            __IM uint8_t BFDF  : 1;    /*!< [0..0] Break Field Low Width Detection Flag                               */
+            __IM uint8_t CF0MF : 1;    /*!< [1..1] Control Field 0 Match Flag                                         */
+            __IM uint8_t CF1MF : 1;    /*!< [2..2] Control Field 1 Match Flag                                         */
+            __IM uint8_t PIBDF : 1;    /*!< [3..3] Priority Interrupt Bit Detection Flag                              */
+            __IM uint8_t BCDF  : 1;    /*!< [4..4] Bus Collision Detected Flag                                        */
+            __IM uint8_t AEDF  : 1;    /*!< [5..5] Valid Edge Detection Flag                                          */
+            uint8_t            : 2;
+        } STR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t STCR;            /*!< (@ 0x00000028) Status Clear Register                                      */
+
+        struct
+        {
+            __IOM uint8_t BFDCL  : 1;  /*!< [0..0] BFDF Clear                                                         */
+            __IOM uint8_t CF0MCL : 1;  /*!< [1..1] CF0MF Clear                                                        */
+            __IOM uint8_t CF1MCL : 1;  /*!< [2..2] CF1MF Clear                                                        */
+            __IOM uint8_t PIBDCL : 1;  /*!< [3..3] PIBDF Clear                                                        */
+            __IOM uint8_t BCDCL  : 1;  /*!< [4..4] BCDF Clear                                                         */
+            __IOM uint8_t AEDCL  : 1;  /*!< [5..5] AEDF Clear                                                         */
+            uint8_t              : 2;
+        } STCR_b;
+    };
+    __IOM uint8_t CF0DR;               /*!< (@ 0x00000029) Control Field 0 Data Register                              */
+
+    union
+    {
+        __IOM uint8_t CF0CR;           /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register                    */
+
+        struct
+        {
+            __IOM uint8_t CF0CE0 : 1;  /*!< [0..0] Control Field 0 Bit 0 Compare Enable                               */
+            __IOM uint8_t CF0CE1 : 1;  /*!< [1..1] Control Field 1 Bit 0 Compare Enable                               */
+            __IOM uint8_t CF0CE2 : 1;  /*!< [2..2] Control Field 2 Bit 0 Compare Enable                               */
+            __IOM uint8_t CF0CE3 : 1;  /*!< [3..3] Control Field 3 Bit 0 Compare Enable                               */
+            __IOM uint8_t CF0CE4 : 1;  /*!< [4..4] Control Field 4 Bit 0 Compare Enable                               */
+            __IOM uint8_t CF0CE5 : 1;  /*!< [5..5] Control Field 5 Bit 0 Compare Enable                               */
+            __IOM uint8_t CF0CE6 : 1;  /*!< [6..6] Control Field 6 Bit 0 Compare Enable                               */
+            __IOM uint8_t CF0CE7 : 1;  /*!< [7..7] Control Field 7 Bit 0 Compare Enable                               */
+        } CF0CR_b;
+    };
+    __IOM uint8_t CF0RR;               /*!< (@ 0x0000002B) Control Field 0 Receive Data Register                      */
+    __IOM uint8_t PCF1DR;              /*!< (@ 0x0000002C) Primary Control Field 1 Data Register                      */
+    __IOM uint8_t SCF1DR;              /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register                    */
+
+    union
+    {
+        __IOM uint8_t CF1CR;           /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register                    */
+
+        struct
+        {
+            __IOM uint8_t CF1CE0 : 1;  /*!< [0..0] Control Field 1 Bit 0 Compare Enable                               */
+            __IOM uint8_t CF1CE1 : 1;  /*!< [1..1] Control Field 1 Bit 1 Compare Enable                               */
+            __IOM uint8_t CF1CE2 : 1;  /*!< [2..2] Control Field 1 Bit 2 Compare Enable                               */
+            __IOM uint8_t CF1CE3 : 1;  /*!< [3..3] Control Field 1 Bit 3 Compare Enable                               */
+            __IOM uint8_t CF1CE4 : 1;  /*!< [4..4] Control Field 1 Bit 4 Compare Enable                               */
+            __IOM uint8_t CF1CE5 : 1;  /*!< [5..5] Control Field 1 Bit 5 Compare Enable                               */
+            __IOM uint8_t CF1CE6 : 1;  /*!< [6..6] Control Field 1 Bit 6 Compare Enable                               */
+            __IOM uint8_t CF1CE7 : 1;  /*!< [7..7] Control Field 1 Bit 7 Compare Enable                               */
+        } CF1CR_b;
+    };
+    __IOM uint8_t CF1RR;               /*!< (@ 0x0000002F) Control Field 1 Receive Data Register                      */
+
+    union
+    {
+        __IOM uint8_t TCR;             /*!< (@ 0x00000030) Timer Control Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TCST : 1;    /*!< [0..0] Timer Count Start                                                  */
+            uint8_t            : 7;
+        } TCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TMR;             /*!< (@ 0x00000031) Timer Mode Register                                        */
+
+        struct
+        {
+            __IOM uint8_t TOMS : 2;    /*!< [1..0] Timer Operating Mode Select                                        */
+            uint8_t            : 1;
+            __IOM uint8_t TWRC : 1;    /*!< [3..3] Counter Write Control                                              */
+            __IOM uint8_t TCSS : 3;    /*!< [6..4] Timer Count Clock Source Select                                    */
+            uint8_t            : 1;
+        } TMR_b;
+    };
+    __IOM uint8_t TPRE;                /*!< (@ 0x00000032) Timer Prescaler Register                                   */
+    __IOM uint8_t TCNT;                /*!< (@ 0x00000033) Timer Count Register                                       */
+} R_SCI0_Type;                         /*!< Size = 52 (0x34)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SPI0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Serial Peripheral Interface (R_SPI0)
+ */
+
+typedef struct                         /*!< (@ 0x4011A000) R_SPI0 Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t SPCR;            /*!< (@ 0x00000000) SPI Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t SPMS   : 1;  /*!< [0..0] SPI Mode Select                                                    */
+            __IOM uint8_t TXMD   : 1;  /*!< [1..1] Communications Operating Mode Select                               */
+            __IOM uint8_t MODFEN : 1;  /*!< [2..2] Mode Fault Error Detection Enable                                  */
+            __IOM uint8_t MSTR   : 1;  /*!< [3..3] SPI Master/Slave Mode Select                                       */
+            __IOM uint8_t SPEIE  : 1;  /*!< [4..4] SPI Error Interrupt Enable                                         */
+            __IOM uint8_t SPTIE  : 1;  /*!< [5..5] Transmit Buffer Empty Interrupt Enable                             */
+            __IOM uint8_t SPE    : 1;  /*!< [6..6] SPI Function Enable                                                */
+            __IOM uint8_t SPRIE  : 1;  /*!< [7..7] SPI Receive Buffer Full Interrupt Enable                           */
+        } SPCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SSLP;            /*!< (@ 0x00000001) SPI Slave Select Polarity Register                         */
+
+        struct
+        {
+            __IOM uint8_t SSL0P : 1;   /*!< [0..0] SSL0 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL1P : 1;   /*!< [1..1] SSL1 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL2P : 1;   /*!< [2..2] SSL2 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL3P : 1;   /*!< [3..3] SSL3 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL4P : 1;   /*!< [4..4] SSL4 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL5P : 1;   /*!< [5..5] SSL5 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL6P : 1;   /*!< [6..6] SSL6 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL7P : 1;   /*!< [7..7] SSL7 Signal Polarity Setting                                       */
+        } SSLP_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPPCR;           /*!< (@ 0x00000002) SPI Pin Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t SPLP  : 1;   /*!< [0..0] SPI Loopback                                                       */
+            __IOM uint8_t SPLP2 : 1;   /*!< [1..1] SPI Loopback 2                                                     */
+            uint8_t             : 2;
+            __IOM uint8_t MOIFV : 1;   /*!< [4..4] MOSI Idle Fixed Value                                              */
+            __IOM uint8_t MOIFE : 1;   /*!< [5..5] MOSI Idle Value Fixing Enable                                      */
+            uint8_t             : 2;
+        } SPPCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPSR;            /*!< (@ 0x00000003) SPI Status Register                                        */
+
+        struct
+        {
+            __IOM uint8_t OVRF  : 1;   /*!< [0..0] Overrun Error Flag                                                 */
+            __IM uint8_t  IDLNF : 1;   /*!< [1..1] SPI Idle Flag                                                      */
+            __IOM uint8_t MODF  : 1;   /*!< [2..2] Mode Fault Error Flag                                              */
+            __IOM uint8_t PERF  : 1;   /*!< [3..3] Parity Error Flag                                                  */
+            __IOM uint8_t UDRF  : 1;   /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.)          */
+            __IOM uint8_t SPTEF : 1;   /*!< [5..5] SPI Transmit Buffer Empty Flag                                     */
+            __IOM uint8_t CENDF : 1;   /*!< [6..6] Communication End Flag                                             */
+            __IOM uint8_t SPRF  : 1;   /*!< [7..7] SPI Receive Buffer Full Flag                                       */
+        } SPSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SPDR;           /*!< (@ 0x00000004) SPI Data Register                                          */
+        __IOM uint16_t SPDR_HA;        /*!< (@ 0x00000004) SPI Data Register ( halfword access )                      */
+        __IOM uint8_t  SPDR_BY;        /*!< (@ 0x00000004) SPI Data Register ( byte access )                          */
+    };
+
+    union
+    {
+        __IOM uint8_t SPSCR;           /*!< (@ 0x00000008) SPI Sequence Control Register                              */
+
+        struct
+        {
+            __IOM uint8_t SPSLN : 3;   /*!< [2..0] RSPI Sequence Length SpecificationThe order in which
+                                        *   the SPCMD0 to SPCMD07 registers are to be referenced is
+                                        *   changed in accordance with the sequence length that is
+                                        *   set in these bits. The relationship among the setting of
+                                        *   these bits, sequence length, and SPCMD0 to SPCMD7 registers
+                                        *   referenced by the RSPI is shown above. However, the RSPI
+                                        *   in slave mode always references SPCMD0.                                   */
+            uint8_t : 5;
+        } SPSCR_b;
+    };
+
+    union
+    {
+        __IM uint8_t SPSSR;            /*!< (@ 0x00000009) SPI Sequence Status Register                               */
+
+        struct
+        {
+            __IM uint8_t SPCP  : 3;    /*!< [2..0] RSPI Command Pointer                                               */
+            uint8_t            : 1;
+            __IM uint8_t SPECM : 3;    /*!< [6..4] RSPI Error Command                                                 */
+            uint8_t            : 1;
+        } SPSSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPBR;            /*!< (@ 0x0000000A) SPI Bit Rate Register                                      */
+
+        struct
+        {
+            __IOM uint8_t SPR : 8;     /*!< [7..0] SPBR sets the bit rate in master mode.                             */
+        } SPBR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPDCR;           /*!< (@ 0x0000000B) SPI Data Control Register                                  */
+
+        struct
+        {
+            __IOM uint8_t SPFC   : 2;  /*!< [1..0] Number of Frames Specification                                     */
+            __IOM uint8_t SLSEL  : 2;  /*!< [3..2] SSL Pin Output Select                                              */
+            __IOM uint8_t SPRDTD : 1;  /*!< [4..4] SPI Receive/Transmit Data Selection                                */
+            __IOM uint8_t SPLW   : 1;  /*!< [5..5] SPI Word Access/Halfword Access Specification                      */
+            __IOM uint8_t SPBYT  : 1;  /*!< [6..6] SPI Byte Access Specification                                      */
+            uint8_t              : 1;
+        } SPDCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPCKD;           /*!< (@ 0x0000000C) SPI Clock Delay Register                                   */
+
+        struct
+        {
+            __IOM uint8_t SCKDL : 3;   /*!< [2..0] RSPCK Delay Setting                                                */
+            uint8_t             : 5;
+        } SPCKD_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SSLND;           /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register                   */
+
+        struct
+        {
+            __IOM uint8_t SLNDL : 3;   /*!< [2..0] SSL Negation Delay Setting                                         */
+            uint8_t             : 5;
+        } SSLND_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPND;            /*!< (@ 0x0000000E) SPI Next-Access Delay Register                             */
+
+        struct
+        {
+            __IOM uint8_t SPNDL : 3;   /*!< [2..0] SPI Next-Access Delay Setting                                      */
+            uint8_t             : 5;
+        } SPND_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPCR2;           /*!< (@ 0x0000000F) SPI Control Register 2                                     */
+
+        struct
+        {
+            __IOM uint8_t SPPE   : 1;  /*!< [0..0] Parity Enable                                                      */
+            __IOM uint8_t SPOE   : 1;  /*!< [1..1] Parity Mode                                                        */
+            __IOM uint8_t SPIIE  : 1;  /*!< [2..2] SPI Idle Interrupt Enable                                          */
+            __IOM uint8_t PTE    : 1;  /*!< [3..3] Parity Self-Testing                                                */
+            __IOM uint8_t SCKASE : 1;  /*!< [4..4] RSPCK Auto-Stop Function Enable                                    */
+            __IOM uint8_t SPTDDL : 3;  /*!< [7..5] RSPI Transmit Data Delay                                           */
+        } SPCR2_b;
+    };
+
+    union
+    {
+        __IOM uint16_t SPCMD[8];       /*!< (@ 0x00000010) SPI Command Register [0..7]                                */
+
+        struct
+        {
+            __IOM uint16_t CPHA   : 1; /*!< [0..0] RSPCK Phase Setting                                                */
+            __IOM uint16_t CPOL   : 1; /*!< [1..1] RSPCK Polarity Setting                                             */
+            __IOM uint16_t BRDV   : 2; /*!< [3..2] Bit Rate Division Setting                                          */
+            __IOM uint16_t SSLA   : 3; /*!< [6..4] SSL Signal Assertion Setting                                       */
+            __IOM uint16_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Keeping                                           */
+            __IOM uint16_t SPB    : 4; /*!< [11..8] SPI Data Length Setting                                           */
+            __IOM uint16_t LSBF   : 1; /*!< [12..12] SPI LSB First                                                    */
+            __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable                                     */
+            __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
+            __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
+        } SPCMD_b[8];
+    };
+
+    union
+    {
+        __IOM uint8_t SPDCR2;          /*!< (@ 0x00000020) SPI Data Control Register 2                                */
+
+        struct
+        {
+            __IOM uint8_t BYSW : 1;    /*!< [0..0] Byte Swap Operating Mode Select                                    */
+            __IOM uint8_t SINV : 1;    /*!< [1..1] Serial data invert bit                                             */
+            uint8_t            : 6;
+        } SPDCR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPCR3;           /*!< (@ 0x00000021) RSPI Control Register 3                                    */
+
+        struct
+        {
+            __IOM uint8_t ETXMD  : 1;  /*!< [0..0] Extended Communication Mode Select                                 */
+            __IOM uint8_t BFDS   : 1;  /*!< [1..1] Between Burst Transfer Frames Delay Select                         */
+            uint8_t              : 2;
+            __IOM uint8_t CENDIE : 1;  /*!< [4..4] RSPI Communication End Interrupt Enable                            */
+            uint8_t              : 3;
+        } SPCR3_b;
+    };
+    __IM uint16_t RESERVED;
+    __IM uint32_t RESERVED1[6];
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint16_t SPPR;           /*!< (@ 0x0000003E) RSPI Parameter Read Register                               */
+
+        struct
+        {
+            uint16_t              : 4;
+            __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check                                                 */
+            uint16_t              : 3;
+            __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check                                               */
+            uint16_t              : 1;
+            __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check                                             */
+        } SPPR_b;
+    };
+} R_SPI0_Type;                         /*!< Size = 64 (0x40)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SRAM                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief SRAM (R_SRAM)
+ */
+
+typedef struct                         /*!< (@ 0x40002000) R_SRAM Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t PARIOAD;         /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register       */
+
+        struct
+        {
+            __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after Detection                                          */
+            uint8_t           : 7;
+        } PARIOAD_b;
+    };
+    __IM uint8_t RESERVED[3];
+
+    union
+    {
+        __IOM uint8_t SRAMPRCR;         /*!< (@ 0x00000004) SRAM Protection Register                                   */
+
+        struct
+        {
+            __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control                                             */
+            __OM uint8_t  KW       : 7; /*!< [7..1] Write Key Code                                                     */
+        } SRAMPRCR_b;
+    };
+    __IM uint8_t  RESERVED1[3];
+    __IOM uint8_t SRAMWTSC;             /*!< (@ 0x00000008) RAM Wait State Control Register                            */
+    __IM uint8_t  RESERVED2[3];
+
+    union
+    {
+        __IOM uint8_t SRAMPRCR2;         /*!< (@ 0x0000000C) SRAM Protection Register 2                                 */
+
+        struct
+        {
+            __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control                                             */
+            __OM uint8_t  KW        : 7; /*!< [7..1] Write Key Code                                                     */
+        } SRAMPRCR2_b;
+    };
+    __IM uint8_t RESERVED3[179];
+
+    union
+    {
+        __IOM uint8_t ECCMODE;         /*!< (@ 0x000000C0) ECC Operating Mode Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t ECCMOD : 2;  /*!< [1..0] ECC Operating Mode Select                                          */
+            uint8_t              : 6;
+        } ECCMODE_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ECC2STS;         /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register                            */
+
+        struct
+        {
+            __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status                                             */
+            uint8_t               : 7;
+        } ECC2STS_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ECC1STSEN;       /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register         */
+
+        struct
+        {
+            __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable                          */
+            uint8_t               : 7;
+        } ECC1STSEN_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ECC1STS;         /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register                            */
+
+        struct
+        {
+            __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status                                             */
+            uint8_t               : 7;
+        } ECC1STS_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ECCPRCR;         /*!< (@ 0x000000C4) ECC Protection Register                                    */
+
+        struct
+        {
+            __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control                                             */
+            __OM uint8_t  KW      : 7; /*!< [7..1] Write Key Code                                                     */
+        } ECCPRCR_b;
+    };
+    __IM uint8_t RESERVED4[11];
+
+    union
+    {
+        __IOM uint8_t ECCPRCR2;         /*!< (@ 0x000000D0) ECC Protection Register 2                                  */
+
+        struct
+        {
+            __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control                                             */
+            __OM uint8_t  KW2      : 7; /*!< [7..1] Write Key Code                                                     */
+        } ECCPRCR2_b;
+    };
+    __IM uint8_t RESERVED5[3];
+
+    union
+    {
+        __IOM uint8_t ECCETST;         /*!< (@ 0x000000D4) ECC Test Control Register                                  */
+
+        struct
+        {
+            __IOM uint8_t TSTBYP : 1;  /*!< [0..0] ECC Bypass Select                                                  */
+            uint8_t              : 7;
+        } ECCETST_b;
+    };
+    __IM uint8_t RESERVED6[3];
+
+    union
+    {
+        __IOM uint8_t ECCOAD;          /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register          */
+
+        struct
+        {
+            __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after Detection                                          */
+            uint8_t           : 7;
+        } ECCOAD_b;
+    };
+} R_SRAM_Type;                         /*!< Size = 217 (0xd9)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SSI0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0)
+ */
+
+typedef struct                         /*!< (@ 0x4009D000) R_SSI0 Structure                                           */
+{
+    union
+    {
+        __IOM uint32_t SSICR;          /*!< (@ 0x00000000) Control Register                                           */
+
+        struct
+        {
+            __IOM uint32_t REN  : 1;   /*!< [0..0] Receive Enable                                                     */
+            __IOM uint32_t TEN  : 1;   /*!< [1..1] Transmit Enable                                                    */
+            uint32_t            : 1;
+            __IOM uint32_t MUEN : 1;   /*!< [3..3] Mute EnableNOTE: When this module is muted, the value
+                                        *   of outputting serial data is rewritten to 0 but data transmission
+                                        *   is not stopped. Write dummy data to the SSIFTDR not to
+                                        *   generate a transmit underflow because the number of data
+                                        *   in the transmit FIFO is decreasing.                                       */
+            __IOM uint32_t CKDV  : 4;  /*!< [7..4] Serial Oversampling Clock Division Ratio                           */
+            __IOM uint32_t DEL   : 1;  /*!< [8..8] Serial Data Delay                                                  */
+            __IOM uint32_t PDTA  : 1;  /*!< [9..9] Parallel Data Alignment                                            */
+            __IOM uint32_t SDTA  : 1;  /*!< [10..10] Serial Data Alignment                                            */
+            __IOM uint32_t SPDP  : 1;  /*!< [11..11] Serial Padding Polarity                                          */
+            __IOM uint32_t LRCKP : 1;  /*!< [12..12] Serial WS Polarity                                               */
+            __IOM uint32_t BCKP  : 1;  /*!< [13..13] Serial Bit Clock Polarity                                        */
+            __IOM uint32_t MST   : 1;  /*!< [14..14] Serial WS Direction NOTE: Only the following settings
+                                        *   are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings
+                                        *   are prohibited.                                                           */
+            uint32_t           : 1;
+            __IOM uint32_t SWL : 3;    /*!< [18..16] System Word LengthSet the system word length to the
+                                        *   bit clock frequency/2 fs.                                                 */
+            __IOM uint32_t DWL   : 3;  /*!< [21..19] Data Word Length                                                 */
+            __IOM uint32_t FRM   : 2;  /*!< [23..22] Channels                                                         */
+            uint32_t             : 1;
+            __IOM uint32_t IIEN  : 1;  /*!< [25..25] Idle Mode Interrupt Enable                                       */
+            __IOM uint32_t ROIEN : 1;  /*!< [26..26] Receive Overflow Interrupt Enable                                */
+            __IOM uint32_t RUIEN : 1;  /*!< [27..27] Receive Underflow Interrupt Enable                               */
+            __IOM uint32_t TOIEN : 1;  /*!< [28..28] Transmit Overflow Interrupt Enable                               */
+            __IOM uint32_t TUIEN : 1;  /*!< [29..29] Transmit Underflow Interrupt Enable                              */
+            __IOM uint32_t CKS   : 1;  /*!< [30..30] Oversampling Clock Select                                        */
+            uint32_t             : 1;
+        } SSICR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SSISR;          /*!< (@ 0x00000004) Status Register                                            */
+
+        struct
+        {
+            __IM uint32_t IDST   : 1;  /*!< [0..0] Idle Mode Status Flag                                              */
+            __IM uint32_t RSWNO  : 1;  /*!< [1..1] Receive Serial Word Number                                         */
+            __IM uint32_t RCHNO  : 2;  /*!< [3..2] Receive Channel Number.These bits are read as 00b.                 */
+            __IM uint32_t TSWNO  : 1;  /*!< [4..4] Transmit Serial Word Number                                        */
+            __IM uint32_t TCHNO  : 2;  /*!< [6..5] Transmit Channel Number                                            */
+            uint32_t             : 18;
+            __IM uint32_t  IIRQ  : 1;  /*!< [25..25] Idle Mode Interrupt Status Flag                                  */
+            __IOM uint32_t ROIRQ : 1;  /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE:
+                                        *   Writable only to clear the flag. Confirm the value is 1
+                                        *   and then write 0.                                                         */
+            __IOM uint32_t RUIRQ : 1;  /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE:
+                                        *   Writable only to clear the flag. Confirm the value is 1
+                                        *   and then write 0.                                                         */
+            __IOM uint32_t TOIRQ : 1;  /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE:
+                                        *   Writable only to clear the flag. Confirm the value is 1
+                                        *   and then write 0.                                                         */
+            __IOM uint32_t TUIRQ : 1;  /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE:
+                                        *   Writable only to clear the flag. Confirm the value is 1
+                                        *   and then write 0.                                                         */
+            uint32_t : 2;
+        } SSISR_b;
+    };
+    __IM uint32_t RESERVED[2];
+
+    union
+    {
+        __IOM uint32_t SSIFCR;         /*!< (@ 0x00000010) FIFO Control Register                                      */
+
+        struct
+        {
+            __IOM uint32_t RFRST : 1;  /*!< [0..0] Receive FIFO Data Register Reset                                   */
+            __IOM uint32_t TFRST : 1;  /*!< [1..1] Transmit FIFO Data Register Reset                                  */
+            __IOM uint32_t RIE   : 1;  /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by
+                                        *   clearing either the RDF flag (see the description of the
+                                        *   RDF bit for details) or RIE bit.                                          */
+            __IOM uint32_t TIE : 1;    /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by
+                                        *   clearing either the TDE flag (see the description of the
+                                        *   TDE bit for details) or TIE bit.                                          */
+            __IOM uint32_t RTRG : 2;   /*!< [5..4] Receive Data Trigger Number                                        */
+            __IOM uint32_t TTRG : 2;   /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis
+                                        *   are the number of empty stages in SSIFTDR at which the
+                                        *   TDE flag is set.                                                          */
+            uint32_t              : 3;
+            __IOM uint32_t BSW    : 1; /*!< [11..11] Byte Swap Enable                                                 */
+            uint32_t              : 4;
+            __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset                                              */
+            uint32_t              : 14;
+            __IOM uint32_t AUCKE  : 1; /*!< [31..31] Oversampling Clock Enable                                        */
+        } SSIFCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SSIFSR;         /*!< (@ 0x00000014) FIFO Status Register                                       */
+
+        struct
+        {
+            __IOM uint32_t RDF : 1;    /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register
+                                        *   is a 32-byte FIFO register, the maximum number of data
+                                        *   bytes that can be read from it while the RDF flag is 1
+                                        *   is indicated in the RDC[3:0] flags. If reading data from
+                                        *   the SSIFRDR register is continued after all the data is
+                                        *   read, undefined values will be read.                                      */
+            uint32_t          : 7;
+            __IM uint32_t RDC : 6;     /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data
+                                        *   units stored in SSIFRDR)                                                  */
+            uint32_t           : 2;
+            __IOM uint32_t TDE : 1;    /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register
+                                        *   is a 32-byte FIFO register, the maximum number of bytes
+                                        *   that can be written to it while the TDE flag is 1 is 8
+                                        *   - TDC[3:0]. If writing data to the SSIFTDR register is
+                                        *   continued after all the data is written, writing will be
+                                        *   invalid and an overflow occurs.                                           */
+            uint32_t          : 7;
+            __IM uint32_t TDC : 6;     /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of
+                                        *   data units stored in SSIFTDR)                                             */
+            uint32_t : 2;
+        } SSIFSR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __OM uint32_t SSIFTDR;          /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
+
+            struct
+            {
+                __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of
+                                             *   eight stages of 32-bit registers for storing data to be
+                                             *   serially transmitted. NOTE: that when the SSIFTDR register
+                                             *   is full of data (32 bytes), the next data cannot be written
+                                             *   to it. If writing is attempted, it will be ignored and
+                                             *   an overflow occurs.                                                       */
+            } SSIFTDR_b;
+        };
+        __OM uint16_t SSIFTDR16;            /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
+        __OM uint8_t  SSIFTDR8;             /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t SSIFRDR;          /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
+
+            struct
+            {
+                __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight
+                                             *   stages of 32-bit registers for storing serially received
+                                             *   data.                                                                     */
+            } SSIFRDR_b;
+        };
+        __IM uint16_t SSIFRDR16;            /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
+        __IM uint8_t  SSIFRDR8;             /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
+    };
+
+    union
+    {
+        __IOM uint32_t SSIOFR;          /*!< (@ 0x00000020) Audio Format Register                                      */
+
+        struct
+        {
+            __IOM uint32_t OMOD    : 2; /*!< [1..0] Audio Format Select                                                */
+            uint32_t               : 6;
+            __IOM uint32_t LRCONT  : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation                             */
+            __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in
+                                         *   Idle Status                                                               */
+            uint32_t : 22;
+        } SSIOFR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SSISCR;         /*!< (@ 0x00000024) Status Control Register                                    */
+
+        struct
+        {
+            __IOM uint32_t RDFS : 5;   /*!< [4..0] RDF Setting Condition Select                                       */
+            uint32_t            : 3;
+            __IOM uint32_t TDES : 5;   /*!< [12..8] TDE Setting Condition Select                                      */
+            uint32_t            : 19;
+        } SSISCR_b;
+    };
+} R_SSI0_Type;                         /*!< Size = 40 (0x28)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SYSTEM                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief System Pins (R_SYSTEM)
+ */
+
+typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure                                         */
+{
+    __IM uint32_t RESERVED[3];
+
+    union
+    {
+        __IOM uint16_t SBYCR;          /*!< (@ 0x0000000C) Standby Control Register                                   */
+
+        struct
+        {
+            uint16_t            : 14;
+            __IOM uint16_t OPE  : 1;   /*!< [14..14] Output Port Enable                                               */
+            __IOM uint16_t SSBY : 1;   /*!< [15..15] Software Standby                                                 */
+        } SBYCR_b;
+    };
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2[3];
+
+    union
+    {
+        __IOM uint32_t MSTPCRA;         /*!< (@ 0x0000001C) Module Stop Control Register A                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPA0  : 1; /*!< [0..0] RAM0 Module Stop                                                   */
+            __IOM uint32_t MSTPA1  : 1; /*!< [1..1] RAM1 Module Stop                                                   */
+            uint32_t               : 3;
+            __IOM uint32_t MSTPA5  : 1; /*!< [5..5] High-Speed RAM Module Stop                                         */
+            __IOM uint32_t MSTPA6  : 1; /*!< [6..6] ECCRAM Module Stop                                                 */
+            __IOM uint32_t MSTPA7  : 1; /*!< [7..7] Standby RAM Module Stop                                            */
+            uint32_t               : 14;
+            __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop              */
+            uint32_t               : 9;
+        } MSTPCRA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SCKDIVCR;       /*!< (@ 0x00000020) System Clock Division Control Register                     */
+
+        struct
+        {
+            __IOM uint32_t PCKD : 3;   /*!< [2..0] Peripheral Module Clock D (PCLKD) Select                           */
+            uint32_t            : 1;
+            __IOM uint32_t PCKC : 3;   /*!< [6..4] Peripheral Module Clock C (PCLKC) Select                           */
+            uint32_t            : 1;
+            __IOM uint32_t PCKB : 3;   /*!< [10..8] Peripheral Module Clock B (PCLKB) Select                          */
+            uint32_t            : 1;
+            __IOM uint32_t PCKA : 3;   /*!< [14..12] Peripheral Module Clock A (PCLKA) Select                         */
+            uint32_t            : 1;
+            __IOM uint32_t BCK  : 3;   /*!< [18..16] External Bus Clock (BCLK) Select                                 */
+            uint32_t            : 5;
+            __IOM uint32_t ICK  : 3;   /*!< [26..24] System Clock (ICLK) Select                                       */
+            uint32_t            : 1;
+            __IOM uint32_t FCK  : 3;   /*!< [30..28] Flash IF Clock (FCLK) Select                                     */
+            uint32_t            : 1;
+        } SCKDIVCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SCKDIVCR2;       /*!< (@ 0x00000024) System Clock Division Control Register 2                   */
+
+        struct
+        {
+            uint8_t           : 4;
+            __IOM uint8_t UCK : 3;     /*!< [6..4] USB Clock (UCLK) Select                                            */
+            uint8_t           : 1;
+        } SCKDIVCR2_b;
+    };
+    __IM uint8_t RESERVED3;
+
+    union
+    {
+        __IOM uint8_t SCKSCR;          /*!< (@ 0x00000026) System Clock Source Control Register                       */
+
+        struct
+        {
+            __IOM uint8_t CKSEL : 3;   /*!< [2..0] Clock Source Select                                                */
+            uint8_t             : 5;
+        } SCKSCR_b;
+    };
+    __IM uint8_t RESERVED4;
+
+    union
+    {
+        __IOM uint16_t PLLCCR;           /*!< (@ 0x00000028) PLL Clock Control Register                                 */
+
+        struct
+        {
+            __IOM uint16_t PLIDIV   : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select                          */
+            uint16_t                : 2;
+            __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select                                            */
+            uint16_t                : 3;
+            __IOM uint16_t PLLMUL   : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency
+                                          *   Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 -
+                                          *   0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0
+                                          *   : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5
+                                          *   111011: x30.0                                                             */
+            uint16_t : 2;
+        } PLLCCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PLLCR;           /*!< (@ 0x0000002A) PLL Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t PLLSTP : 1;  /*!< [0..0] PLL Stop Control                                                   */
+            uint8_t              : 7;
+        } PLLCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PLLCCR2;         /*!< (@ 0x0000002B) PLL Clock Control Register2                                */
+
+        struct
+        {
+            __IOM uint8_t PLLMUL : 5;  /*!< [4..0] PLL Frequency Multiplication Factor Select                         */
+            uint8_t              : 1;
+            __IOM uint8_t PLODIV : 2;  /*!< [7..6] PLL Output Frequency Division Ratio Select                         */
+        } PLLCCR2_b;
+    };
+    __IM uint32_t RESERVED5;
+
+    union
+    {
+        __IOM uint8_t BCKCR;           /*!< (@ 0x00000030) External Bus Clock Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select                                             */
+            uint8_t               : 7;
+        } BCKCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t MEMWAIT;         /*!< (@ 0x00000031) Memory Wait Cycle Control Register                         */
+
+        struct
+        {
+            __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT
+                                        *   is prohibited when SCKDIVCR.ICK selects division by 1 and
+                                        *   SCKSCR.CKSEL[2:0] bits select thesystem clock source that
+                                        *   is faster than 32 MHz (ICLK > 32 MHz).                                    */
+            uint8_t : 7;
+        } MEMWAIT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t MOSCCR;          /*!< (@ 0x00000032) Main Clock Oscillator Control Register                     */
+
+        struct
+        {
+            __IOM uint8_t MOSTP : 1;   /*!< [0..0] Main Clock Oscillator Stop                                         */
+            uint8_t             : 7;
+        } MOSCCR_b;
+    };
+    __IM uint8_t  RESERVED6;
+    __IM uint16_t RESERVED7;
+
+    union
+    {
+        __IOM uint8_t HOCOCR;          /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register             */
+
+        struct
+        {
+            __IOM uint8_t HCSTP : 1;   /*!< [0..0] HOCO Stop                                                          */
+            uint8_t             : 7;
+        } HOCOCR_b;
+    };
+    __IM uint8_t RESERVED8;
+
+    union
+    {
+        __IOM uint8_t MOCOCR;          /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register           */
+
+        struct
+        {
+            __IOM uint8_t MCSTP : 1;   /*!< [0..0] MOCO Stop                                                          */
+            uint8_t             : 7;
+        } MOCOCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t FLLCR1;          /*!< (@ 0x00000039) FLL Control Register 1                                     */
+
+        struct
+        {
+            __IOM uint8_t FLLEN : 1;   /*!< [0..0] FLL Enable                                                         */
+            uint8_t             : 7;
+        } FLLCR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t FLLCR2;           /*!< (@ 0x0000003A) FLL Control Register 2                                     */
+
+        struct
+        {
+            __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the
+                                          *   FLL reference clock select                                                */
+            uint16_t : 5;
+        } FLLCR2_b;
+    };
+
+    union
+    {
+        __IM uint8_t OSCSF;            /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register                    */
+
+        struct
+        {
+            __IM uint8_t HOCOSF : 1;   /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF
+                                        *   bit value after a reset is 1 when the OFS1.HOCOEN bit is
+                                        *   0. It is 0 when the OFS1.HOCOEN bit is 1.                                 */
+            uint8_t             : 2;
+            __IM uint8_t MOSCSF : 1;   /*!< [3..3] Main Clock Oscillation Stabilization Flag                          */
+            uint8_t             : 1;
+            __IM uint8_t PLLSF  : 1;   /*!< [5..5] PLL Clock Oscillation Stabilization Flag                           */
+            __IM uint8_t PLL2SF : 1;   /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag                          */
+            uint8_t             : 1;
+        } OSCSF_b;
+    };
+    __IM uint8_t RESERVED9;
+
+    union
+    {
+        __IOM uint8_t CKOCR;           /*!< (@ 0x0000003E) Clock Out Control Register                                 */
+
+        struct
+        {
+            __IOM uint8_t CKOSEL : 3;  /*!< [2..0] Clock out source select                                            */
+            uint8_t              : 1;
+            __IOM uint8_t CKODIV : 3;  /*!< [6..4] Clock out input frequency Division Select                          */
+            __IOM uint8_t CKOEN  : 1;  /*!< [7..7] Clock out enable                                                   */
+        } CKOCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TRCKCR;          /*!< (@ 0x0000003F) Trace Clock Control Register                               */
+
+        struct
+        {
+            __IOM uint8_t TRCK   : 4;  /*!< [3..0] Trace Clock operating frequency select                             */
+            uint8_t              : 3;
+            __IOM uint8_t TRCKEN : 1;  /*!< [7..7] Trace Clock operating Enable                                       */
+        } TRCKCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t OSTDCR;          /*!< (@ 0x00000040) Oscillation Stop Detection Control Register                */
+
+        struct
+        {
+            __IOM uint8_t OSTDIE : 1;  /*!< [0..0] Oscillation Stop Detection Interrupt Enable                        */
+            uint8_t              : 6;
+            __IOM uint8_t OSTDE  : 1;  /*!< [7..7] Oscillation Stop Detection Function Enable                         */
+        } OSTDCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t OSTDSR;          /*!< (@ 0x00000041) Oscillation Stop Detection Status Register                 */
+
+        struct
+        {
+            __IOM uint8_t OSTDF : 1;   /*!< [0..0] Oscillation Stop Detection Flag                                    */
+            uint8_t             : 7;
+        } OSTDSR_b;
+    };
+    __IM uint16_t RESERVED10;
+    __IM uint32_t RESERVED11;
+
+    union
+    {
+        __IOM uint16_t PLL2CCR;           /*!< (@ 0x00000048) PLL2 Clock Control Register                                */
+
+        struct
+        {
+            __IOM uint16_t PL2IDIV   : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select                         */
+            uint16_t                 : 2;
+            __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select                                           */
+            uint16_t                 : 3;
+            __IOM uint16_t PLL2MUL   : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select                       */
+            uint16_t                 : 2;
+        } PLL2CCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PLL2CR;          /*!< (@ 0x0000004A) PLL2 Control Register                                      */
+
+        struct
+        {
+            __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control                                                  */
+            uint8_t               : 7;
+        } PLL2CR_b;
+    };
+    __IM uint8_t RESERVED12;
+
+    union
+    {
+        __IOM uint8_t LPOPT;             /*!< (@ 0x0000004C) Lower Power Operation Control Register                     */
+
+        struct
+        {
+            __IOM uint8_t MPUDIS : 1;    /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock
+                                          *   (valid only when LPOPTEN = 1)                                             */
+            __IOM uint8_t DCLKDIS   : 2; /*!< [2..1] Debug Clock Disable Control                                        */
+            __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W
+                                          *   clock (valid only when LPOPT.LPOPTEN = 1)                                 */
+            uint8_t               : 3;
+            __IOM uint8_t LPOPTEN : 1;   /*!< [7..7] Lower Power Operation Enable                                       */
+        } LPOPT_b;
+    };
+    __IM uint8_t  RESERVED13;
+    __IM uint16_t RESERVED14;
+
+    union
+    {
+        __IOM uint8_t SLCDSCKCR;         /*!< (@ 0x00000050) Segment LCD Source Clock Control Register                  */
+
+        struct
+        {
+            __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select                                */
+            uint8_t                 : 4;
+            __IOM uint8_t LCDSCKEN  : 1; /*!< [7..7] LCD Source Clock Out Enable                                        */
+        } SLCDSCKCR_b;
+    };
+    __IM uint8_t RESERVED15;
+
+    union
+    {
+        __IOM uint8_t EBCKOCR;         /*!< (@ 0x00000052) External Bus Clock Output Control Register                 */
+
+        struct
+        {
+            __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control                                            */
+            uint8_t               : 7;
+        } EBCKOCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SDCKOCR;         /*!< (@ 0x00000053) SDRAM Clock Output Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control                                           */
+            uint8_t               : 7;
+        } SDCKOCR_b;
+    };
+    __IM uint32_t RESERVED16[3];
+    __IM uint8_t  RESERVED17;
+
+    union
+    {
+        __IOM uint8_t MOCOUTCR;         /*!< (@ 0x00000061) MOCO User Trimming Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127
+                                         *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
+                                         *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
+                                         +126 0111_1111 : +127These bits are added to original MOCO
+                                         *   trimming bits                                                             */
+        } MOCOUTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t HOCOUTCR;         /*!< (@ 0x00000062) HOCO User Trimming Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127
+                                         *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
+                                         *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
+                                         +126 0111_1111 : +127These bits are added to original HOCO
+                                         *   trimming bits                                                             */
+        } HOCOUTCR_b;
+    };
+    __IM uint8_t  RESERVED18;
+    __IM uint32_t RESERVED19[2];
+
+    union
+    {
+        __IOM uint8_t USBCKDIVCR;       /*!< (@ 0x0000006C) USB Clock Division Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select                                 */
+            uint8_t                : 5;
+        } USBCKDIVCR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t OCTACKDIVCR;       /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register                  */
+
+            struct
+            {
+                __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select                          */
+                uint8_t                 : 5;
+            } OCTACKDIVCR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t SCISPICKDIVCR;       /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register                    */
+
+            struct
+            {
+                __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select                          */
+                uint8_t                   : 5;
+            } SCISPICKDIVCR_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint8_t CANFDCKDIVCR;       /*!< (@ 0x0000006E) CANFD Clock Division Control Register                      */
+
+        struct
+        {
+            __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select                             */
+            uint8_t                  : 5;
+        } CANFDCKDIVCR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t GPTCKDIVCR;       /*!< (@ 0x0000006F) GPT Clock Division Control Register                        */
+
+            struct
+            {
+                __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select                                 */
+                uint8_t                : 5;
+            } GPTCKDIVCR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t USB60CKDIVCR;       /*!< (@ 0x0000006F) USB60 Clock Division Control Register                      */
+
+            struct
+            {
+                __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select                               */
+                uint8_t                  : 5;
+            } USB60CKDIVCR_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t CECCKDIVCR;       /*!< (@ 0x00000070) CEC Clock Division Control Register                        */
+
+            struct
+            {
+                __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select                                 */
+                uint8_t                : 5;
+            } CECCKDIVCR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t IICCKDIVCR;       /*!< (@ 0x00000070) IIC Clock Division Control Register                        */
+
+            struct
+            {
+                __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select                                 */
+                uint8_t                : 5;
+            } IICCKDIVCR_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
+
+        struct
+        {
+            __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
+            uint8_t                : 5;
+        } I3CCKDIVCR_b;
+    };
+    __IM uint16_t RESERVED20;
+
+    union
+    {
+        __IOM uint8_t USBCKCR;           /*!< (@ 0x00000074) USB Clock Control Register                                 */
+
+        struct
+        {
+            __IOM uint8_t USBCKSEL  : 3; /*!< [2..0] USB Clock (USBCLK) Source Select                                   */
+            uint8_t                 : 3;
+            __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request                               */
+            __IM uint8_t  USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag                      */
+        } USBCKCR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t OCTACKCR;           /*!< (@ 0x00000075) Octal-SPI Clock Control Register                           */
+
+            struct
+            {
+                __IOM uint8_t OCTACKSEL  : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select                            */
+                uint8_t                  : 3;
+                __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request                        */
+                __IM uint8_t  OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag               */
+            } OCTACKCR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t SCISPICKCR;           /*!< (@ 0x00000075) SCI SPI Clock Control Register                             */
+
+            struct
+            {
+                __IOM uint8_t SCISPICKSEL  : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select                            */
+                uint8_t                    : 3;
+                __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request                        */
+                __IM uint8_t  SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag               */
+            } SCISPICKCR_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint8_t CANFDCKCR;           /*!< (@ 0x00000076) CANFD Clock Control Register                               */
+
+        struct
+        {
+            __IOM uint8_t CANFDCKSEL  : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select                               */
+            uint8_t                   : 3;
+            __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request                           */
+            __IM uint8_t  CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag                  */
+        } CANFDCKCR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t GPTCKCR;           /*!< (@ 0x00000077) GPT Clock Control Register                                 */
+
+            struct
+            {
+                __IOM uint8_t GPTCKSEL  : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select                                   */
+                uint8_t                 : 3;
+                __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request                               */
+                __IM uint8_t  GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag                      */
+            } GPTCKCR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t USB60CKCR;           /*!< (@ 0x00000077) USB60 clock control register                               */
+
+            struct
+            {
+                __IOM uint8_t USB60CKSEL  : 4; /*!< [3..0] USB clock (USB60CLK) Source Select                                 */
+                uint8_t                   : 2;
+                __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request                             */
+                __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag                    */
+            } USB60CKCR_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t CECCKCR;           /*!< (@ 0x00000078) CEC Clock Control Register                                 */
+
+            struct
+            {
+                __IOM uint8_t CECCKSEL  : 3; /*!< [2..0] CEC clock (CECCLK) Source Select                                   */
+                uint8_t                 : 3;
+                __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request                               */
+                __IM uint8_t  CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag                      */
+            } CECCKCR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t IICCKCR;           /*!< (@ 0x00000078) IIC Clock Control Register                                 */
+
+            struct
+            {
+                __IOM uint8_t IICCKSEL  : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select                                   */
+                uint8_t                 : 3;
+                __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request                               */
+                __IM uint8_t  IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag                      */
+            } IICCKCR_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint8_t I3CCKCR;           /*!< (@ 0x00000079) I3C Clock Control Register                                 */
+
+        struct
+        {
+            __IOM uint8_t I3CCKSEL  : 3; /*!< [2..0] I3C clock (I3CCLK) source select                                   */
+            uint8_t                 : 3;
+            __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request                               */
+            __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
+        } I3CCKCR_b;
+    };
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
+
+    union
+    {
+        __IOM uint32_t SNZREQCR1;         /*!< (@ 0x00000088) Snooze Request Control Register 1                          */
+
+        struct
+        {
+            __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request                               */
+            __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request                               */
+            __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request                               */
+            uint32_t                 : 29;
+        } SNZREQCR1_b;
+    };
+    __IM uint32_t RESERVED23;
+    __IM uint16_t RESERVED24;
+
+    union
+    {
+        __IOM uint8_t SNZCR;            /*!< (@ 0x00000092) Snooze Control Register                                    */
+
+        struct
+        {
+            __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other
+                                         *   than in asynchronous mode.                                                */
+            __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode                                          */
+            uint8_t                : 5;
+            __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
+        } SNZCR_b;
+    };
+    __IM uint8_t RESERVED25;
+
+    union
+    {
+        __IOM uint8_t SNZEDCR;           /*!< (@ 0x00000094) Snooze End Control Register                                */
+
+        struct
+        {
+            __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable                                   */
+            __IOM uint8_t DTCZRED   : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable                 */
+            __IOM uint8_t DTCNZRED  : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable             */
+            __IOM uint8_t AD0MATED  : 1; /*!< [3..3] AD compare match 0 Snooze End Enable                               */
+            __IOM uint8_t AD0UMTED  : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable                            */
+            __IOM uint8_t AD1MATED  : 1; /*!< [5..5] AD compare match 1 Snooze End Enable                               */
+            __IOM uint8_t AD1UMTED  : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable                            */
+            __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set
+                                          *   to 1 other than in asynchronous mode.                                     */
+        } SNZEDCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SNZEDCR1;          /*!< (@ 0x00000095) Snooze End Control Register 1                              */
+
+        struct
+        {
+            __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable                                   */
+            uint8_t                 : 7;
+        } SNZEDCR1_b;
+    };
+    __IM uint16_t RESERVED26;
+
+    union
+    {
+        __IOM uint32_t SNZREQCR;           /*!< (@ 0x00000098) Snooze Request Control Register                            */
+
+        struct
+        {
+            __IOM uint32_t SNZREQEN0  : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request             */
+            __IOM uint32_t SNZREQEN1  : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request             */
+            __IOM uint32_t SNZREQEN2  : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request             */
+            __IOM uint32_t SNZREQEN3  : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request             */
+            __IOM uint32_t SNZREQEN4  : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request             */
+            __IOM uint32_t SNZREQEN5  : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request             */
+            __IOM uint32_t SNZREQEN6  : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request             */
+            __IOM uint32_t SNZREQEN7  : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request             */
+            __IOM uint32_t SNZREQEN8  : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request             */
+            __IOM uint32_t SNZREQEN9  : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request             */
+            __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request          */
+            __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request          */
+            __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request          */
+            __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request          */
+            __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request          */
+            __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request          */
+            uint32_t                  : 1;
+            __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request                 */
+            uint32_t                  : 4;
+            __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze
+                                            *   request                                                                   */
+            __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze
+                                            *   request                                                                   */
+            __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request          */
+            __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request         */
+            uint32_t                  : 2;
+            __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze
+                                            *   request                                                                   */
+            __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A
+                                            *   snooze request                                                            */
+            __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B
+                                            *   snooze request                                                            */
+            uint32_t : 1;
+        } SNZREQCR_b;
+    };
+    __IM uint16_t RESERVED27;
+
+    union
+    {
+        __IOM uint8_t FLSTOP;          /*!< (@ 0x0000009E) Flash Operation Control Register                           */
+
+        struct
+        {
+            __IOM uint8_t FLSTOP : 1;  /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation                     */
+            uint8_t              : 3;
+            __IOM uint8_t FLSTPF : 1;  /*!< [4..4] Flash Memory Operation Status Flag                                 */
+            uint8_t              : 3;
+        } FLSTOP_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PSMCR;           /*!< (@ 0x0000009F) Power Save Memory Control Register                         */
+
+        struct
+        {
+            __IOM uint8_t PSMC : 2;    /*!< [1..0] Power save memory control.                                         */
+            uint8_t            : 6;
+        } PSMCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t OPCCR;           /*!< (@ 0x000000A0) Operating Power Control Register                           */
+
+        struct
+        {
+            __IOM uint8_t OPCM   : 2;  /*!< [1..0] Operating Power Control Mode Select                                */
+            uint8_t              : 2;
+            __IM uint8_t OPCMTSF : 1;  /*!< [4..4] Operating Power Control Mode Transition Status Flag                */
+            uint8_t              : 3;
+        } OPCCR_b;
+    };
+    __IM uint8_t RESERVED28;
+
+    union
+    {
+        __IOM uint8_t MOSCWTCR;        /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register                */
+
+        struct
+        {
+            __IOM uint8_t MSTS : 4;    /*!< [3..0] Main clock oscillator wait time setting                            */
+            uint8_t            : 4;
+        } MOSCWTCR_b;
+    };
+    __IM uint8_t RESERVED29[2];
+
+    union
+    {
+        __IOM uint8_t HOCOWTCR;        /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register        */
+
+        struct
+        {
+            __IOM uint8_t HSTS : 3;    /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of
+                                        *   the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed)                     */
+            uint8_t : 5;
+        } HOCOWTCR_b;
+    };
+    __IM uint16_t RESERVED30[2];
+
+    union
+    {
+        __IOM uint8_t SOPCCR;          /*!< (@ 0x000000AA) Sub Operating Power Control Register                       */
+
+        struct
+        {
+            __IOM uint8_t SOPCM   : 1; /*!< [0..0] Sub Operating Power Control Mode Select                            */
+            uint8_t               : 3;
+            __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag            */
+            uint8_t               : 3;
+        } SOPCCR_b;
+    };
+    __IM uint8_t  RESERVED31;
+    __IM uint32_t RESERVED32[5];
+
+    union
+    {
+        __IOM uint16_t RSTSR1;         /*!< (@ 0x000000C0) Reset Status Register 1                                    */
+
+        struct
+        {
+            __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable
+                                        *   only to clear the flag. Confirm the value is 1 and then
+                                        *   write 0.                                                                  */
+            __IOM uint16_t WDTRF : 1;  /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to
+                                        *   clear the flag. Confirm the value is 1 and then write 0.                  */
+            __IOM uint16_t SWRF : 1;   /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear
+                                        *   the flag. Confirm the value is 1 and then write 0.                        */
+            uint16_t             : 5;
+            __IOM uint16_t RPERF : 1;  /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only
+                                        *   to clear the flag. Confirm the value is 1 and then write
+                                        *   0.                                                                        */
+            __IOM uint16_t REERF : 1;  /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to
+                                        *   clear the flag. Confirm the value is 1 and then write 0.                  */
+            __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only
+                                        *   to clear the flag. Confirm the value is 1 and then write
+                                        *   0.                                                                        */
+            __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only
+                                        *   to clear the flag. Confirm the value is 1 and then write
+                                        *   0.                                                                        */
+            __IOM uint16_t SPERF : 1;  /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear
+                                        *   the flag. Confirm the value is 1 and then write 0.                        */
+            __IOM uint16_t TZERF : 1;  /*!< [13..13] Trust Zone Error Reset Detect Flag                               */
+            uint16_t             : 1;
+            __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
+        } RSTSR1_b;
+    };
+    __IM uint16_t RESERVED33;
+    __IM uint32_t RESERVED34[3];
+
+    union
+    {
+        __IOM uint8_t USBCKCR_ALT;       /*!< (@ 0x000000D0) USB Clock Control Register                                 */
+
+        struct
+        {
+            __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock
+                                          *   (UCLK).                                                                   */
+            uint8_t : 7;
+        } USBCKCR_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SDADCCKCR;          /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control
+                                           *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select                      */
+            uint8_t                  : 6;
+            __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
+        } SDADCCKCR_b;
+    };
+    __IM uint16_t RESERVED35;
+    __IM uint32_t RESERVED36[3];
+
+    union
+    {
+        __IOM uint8_t LVD1CR1;         /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1               */
+
+        struct
+        {
+            __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
+            __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
+            uint8_t              : 5;
+        } LVD1CR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t LVD1SR;          /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register                  */
+
+        struct
+        {
+            __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
+                                        *   0 can be written to this bit. After writing 0 to this bit,
+                                        *   it takes 2 system clock cycles for the bit to be read as
+                                        *   0.                                                                        */
+            __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag                              */
+            uint8_t          : 6;
+        } LVD1SR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t LVD2CR1;         /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1               */
+
+        struct
+        {
+            __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
+            __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
+            uint8_t              : 5;
+        } LVD2CR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t LVD2SR;          /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register                  */
+
+        struct
+        {
+            __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
+                                        *   0 can be written to this bit. After writing 0 to this bit,
+                                        *   it takes 2 system clock cycles for the bit to be read as
+                                        *   0.                                                                        */
+            __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag                              */
+            uint8_t          : 6;
+        } LVD2SR_b;
+    };
+    __IM uint32_t RESERVED37[183];
+
+    union
+    {
+        __IOM uint32_t CGFSAR;           /*!< (@ 0x000003C0) Clock Generation Function Security Attribute
+                                          *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00                                        */
+            uint32_t                : 1;
+            __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02                                        */
+            __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03                                        */
+            __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04                                        */
+            __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05                                        */
+            __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06                                        */
+            __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07                                        */
+            __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08                                        */
+            __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09                                        */
+            uint32_t                : 1;
+            __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11                                      */
+            __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12                                      */
+            uint32_t                : 3;
+            __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16                                      */
+            __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17                                      */
+            uint32_t                : 14;
+        } CGFSAR_b;
+    };
+    __IM uint32_t RESERVED38;
+
+    union
+    {
+        __IOM uint32_t LPMSAR;          /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register               */
+
+        struct
+        {
+            __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
+            uint32_t               : 1;
+            __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
+            uint32_t               : 1;
+            __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4                                         */
+            uint32_t               : 3;
+            __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8                                         */
+            __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9                                         */
+            uint32_t               : 22;
+        } LPMSAR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t LVDSAR;          /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register        */
+
+            struct
+            {
+                __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
+                __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
+                uint32_t               : 30;
+            } LVDSAR_b;
+        };
+
+        union
+        {
+            __IOM uint32_t RSTSAR;          /*!< (@ 0x000003CC) Reset Security Attribution Register                        */
+
+            struct
+            {
+                __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
+                __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
+                __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
+                uint32_t               : 29;
+            } RSTSAR_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint32_t BBFSAR;           /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register        */
+
+        struct
+        {
+            __IOM uint32_t NONSEC0  : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
+            __IOM uint32_t NONSEC1  : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
+            __IOM uint32_t NONSEC2  : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
+            uint32_t                : 13;
+            __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16                                      */
+            __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17                                      */
+            __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18                                      */
+            __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19                                      */
+            __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20                                      */
+            __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21                                      */
+            __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22                                      */
+            __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23                                      */
+            uint32_t                : 8;
+        } BBFSAR_b;
+    };
+    __IM uint32_t RESERVED39[3];
+
+    union
+    {
+        __IOM uint32_t DPFSAR;          /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution
+                                         *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t DPFSA0 : 1;  /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   0                                                                         */
+            __IOM uint32_t DPFSA1 : 1;  /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   1                                                                         */
+            __IOM uint32_t DPFSA2 : 1;  /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   2                                                                         */
+            __IOM uint32_t DPFSA3 : 1;  /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   3                                                                         */
+            __IOM uint32_t DPFSA4 : 1;  /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   4                                                                         */
+            __IOM uint32_t DPFSA5 : 1;  /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   5                                                                         */
+            __IOM uint32_t DPFSA6 : 1;  /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   6                                                                         */
+            __IOM uint32_t DPFSA7 : 1;  /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   7                                                                         */
+            __IOM uint32_t DPFSA8 : 1;  /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   8                                                                         */
+            __IOM uint32_t DPFSA9 : 1;  /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   9                                                                         */
+            __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   10                                                                        */
+            __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   11                                                                        */
+            __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   12                                                                        */
+            __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   13                                                                        */
+            __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   14                                                                        */
+            __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   15                                                                        */
+            __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   16                                                                        */
+            __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   17                                                                        */
+            __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   18                                                                        */
+            __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   19                                                                        */
+            __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   20                                                                        */
+            uint32_t               : 3;
+            __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   24                                                                        */
+            uint32_t               : 1;
+            __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   26                                                                        */
+            __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit
+                                         *   27                                                                        */
+            uint32_t : 4;
+        } DPFSAR_b;
+    };
+    __IM uint32_t RESERVED40[6];
+    __IM uint16_t RESERVED41;
+
+    union
+    {
+        __IOM uint16_t PRCR;           /*!< (@ 0x000003FE) Protect Register                                           */
+
+        struct
+        {
+            __IOM uint16_t PRC0 : 1;   /*!< [0..0] Enables writing to the registers related to the clock
+                                        *   generation circuit.                                                       */
+            __IOM uint16_t PRC1 : 1;   /*!< [1..1] Enables writing to the registers related to the operating
+                                        *   modes, the low power consumption modes and the battery
+                                        *   backup function.                                                          */
+            uint16_t            : 1;
+            __IOM uint16_t PRC3 : 1;   /*!< [3..3] Enables writing to the registers related to the LVD.               */
+            __IOM uint16_t PRC4 : 1;   /*!< [4..4] PRC4                                                               */
+            uint16_t            : 3;
+            __OM uint16_t PRKEY : 8;   /*!< [15..8] PRKEY Key Code                                                    */
+        } PRCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSBYCR;         /*!< (@ 0x00000400) Deep Standby Control Register                              */
+
+        struct
+        {
+            __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control                                               */
+            uint8_t               : 4;
+            __IOM uint8_t IOKEEP  : 1; /*!< [6..6] I/O Port Retention                                                 */
+            __IOM uint8_t DPSBY   : 1; /*!< [7..7] Deep Software Standby                                              */
+        } DPSBYCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSWCR;          /*!< (@ 0x00000401) Deep Standby Wait Control Register                         */
+
+        struct
+        {
+            __IOM uint8_t WTSTS : 6;   /*!< [5..0] Deep Software Wait Standby Time Setting Bit                        */
+            uint8_t             : 2;
+        } DPSWCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIER0;         /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0                   */
+
+        struct
+        {
+            __IOM uint8_t DIRQ0E : 1;  /*!< [0..0] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ1E : 1;  /*!< [1..1] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ2E : 1;  /*!< [2..2] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ3E : 1;  /*!< [3..3] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ4E : 1;  /*!< [4..4] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ5E : 1;  /*!< [5..5] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ6E : 1;  /*!< [6..6] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ7E : 1;  /*!< [7..7] IRQ-DS Pin Enable                                                  */
+        } DPSIER0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIER1;         /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1                   */
+
+        struct
+        {
+            __IOM uint8_t DIRQ8E  : 1; /*!< [0..0] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ9E  : 1; /*!< [1..1] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable                                                  */
+        } DPSIER1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIER2;          /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2                   */
+
+        struct
+        {
+            __IOM uint8_t DLVD1IE  : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable                             */
+            __IOM uint8_t DLVD2IE  : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable                             */
+            __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable           */
+            __IOM uint8_t DRTCAIE  : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable              */
+            __IOM uint8_t DNMIE    : 1; /*!< [4..4] NMI Pin Enable                                                     */
+            uint8_t                : 3;
+        } DPSIER2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIER3;          /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3                   */
+
+        struct
+        {
+            __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable             */
+            __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable             */
+            __IOM uint8_t DAGT1IE  : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable                   */
+            __IOM uint8_t DAGT3IE  : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable                   */
+            uint8_t                : 4;
+        } DPSIER3_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIFR0;         /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0                     */
+
+        struct
+        {
+            __IOM uint8_t DIRQ0F : 1;  /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ1F : 1;  /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ2F : 1;  /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ3F : 1;  /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ4F : 1;  /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ5F : 1;  /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ6F : 1;  /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ7F : 1;  /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag                                */
+        } DPSIFR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIFR1;         /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1                     */
+
+        struct
+        {
+            __IOM uint8_t DIRQ8F  : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ9F  : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag                                */
+        } DPSIFR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIFR2;          /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2                     */
+
+        struct
+        {
+            __IOM uint8_t DLVD1IF  : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag                                      */
+            __IOM uint8_t DLVD2IF  : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag                                      */
+            __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag                    */
+            __IOM uint8_t DRTCAIF  : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag                       */
+            __IOM uint8_t DNMIF    : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag                                   */
+            uint8_t                : 3;
+        } DPSIFR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIFR3;          /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3                     */
+
+        struct
+        {
+            __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag                      */
+            __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag                      */
+            __IOM uint8_t DAGT1IF  : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag                            */
+            __IOM uint8_t DAGT3IF  : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag                            */
+            uint8_t                : 4;
+        } DPSIFR3_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIEGR0;        /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0                     */
+
+        struct
+        {
+            __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select                                             */
+        } DPSIEGR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIEGR1;        /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1                     */
+
+        struct
+        {
+            __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select                                             */
+        } DPSIEGR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIEGR2;         /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2                     */
+
+        struct
+        {
+            __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select                                                   */
+            __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select                                                   */
+            uint8_t                : 2;
+            __IOM uint8_t DNMIEG   : 1; /*!< [4..4] NMI Pin Edge Select                                                */
+            uint8_t                : 3;
+        } DPSIEGR2_b;
+    };
+    __IM uint8_t RESERVED42;
+
+    union
+    {
+        __IOM uint8_t SYOCDCR;         /*!< (@ 0x0000040E) System Control OCD Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t DOCDF : 1;   /*!< [0..0] Deep Standby OCD flag                                              */
+            uint8_t             : 6;
+            __IOM uint8_t DBGEN : 1;   /*!< [7..7] Debugger Enable bit                                                */
+        } SYOCDCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t STCONR;          /*!< (@ 0x0000040F) Standby Condition Register                                 */
+
+        struct
+        {
+            __IOM uint8_t STCON : 2;   /*!< [1..0] SSTBY condition bit                                                */
+            uint8_t             : 6;
+        } STCONR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t RSTSR0;          /*!< (@ 0x00000410) Reset Status Register 0                                    */
+
+        struct
+        {
+            __IOM uint8_t PORF : 1;    /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear
+                                        *   the flag. Confirm the value is 1 and then write 0.                        */
+            __IOM uint8_t LVD0RF : 1;  /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only
+                                        *   to clear the flag. Confirm the value is 1 and then write
+                                        *   0.                                                                        */
+            __IOM uint8_t LVD1RF : 1;  /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only
+                                        *   to clear the flag. Confirm the value is 1 and then write
+                                        *   0.                                                                        */
+            __IOM uint8_t LVD2RF : 1;  /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only
+                                        *   to clear the flag. Confirm the value is 1 and then write
+                                        *   0.                                                                        */
+            uint8_t               : 3;
+            __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to
+                                        *   clear the flag. Confirm the value is 1 and then write 0.                  */
+        } RSTSR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t RSTSR2;          /*!< (@ 0x00000411) Reset Status Register 2                                    */
+
+        struct
+        {
+            __IOM uint8_t CWSF : 1;    /*!< [0..0] Cold/Warm Start Determination Flag                                 */
+            uint8_t            : 7;
+        } RSTSR2_b;
+    };
+    __IM uint8_t RESERVED43;
+
+    union
+    {
+        __IOM uint8_t MOMCR;           /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control
+                                        *                  Register                                                   */
+
+        struct
+        {
+            uint8_t                 : 3;
+            __IOM uint8_t MODRV1    : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching                 */
+            __IOM uint8_t MODRV0    : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching                 */
+            __IOM uint8_t MOSEL     : 1; /*!< [6..6] Main Clock Oscillator Switching                                    */
+            __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching
+                                          *   Enable                                                                    */
+        } MOMCR_b;
+    };
+    __IM uint16_t RESERVED44;
+
+    union
+    {
+        __IOM uint8_t FWEPROR;         /*!< (@ 0x00000416) Flash P/E Protect Register                                 */
+
+        struct
+        {
+            __IOM uint8_t FLWE : 2;    /*!< [1..0] Flash Programming and Erasure                                      */
+            uint8_t            : 6;
+        } FWEPROR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t LVCMPCR;     /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register                   */
+
+            struct
+            {
+                uint8_t             : 5;
+                __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable                                         */
+                __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable                                         */
+                uint8_t             : 1;
+            } LVCMPCR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t LVD1CMPCR;       /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register           */
+
+            struct
+            {
+                __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during
+                                            *   drop in voltage)                                                          */
+                uint8_t             : 2;
+                __IOM uint8_t LVD1E : 1;   /*!< [7..7] Voltage Detection 1 Enable                                         */
+            } LVD1CMPCR_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t LVDLVLR;         /*!< (@ 0x00000418) Voltage Detection Level Select Register                    */
+
+            struct
+            {
+                __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during
+                                            *   fall in voltage)                                                          */
+                __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during
+                                            *   fall in voltage)                                                          */
+            } LVDLVLR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t LVD2CMPCR;       /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register           */
+
+            struct
+            {
+                __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during
+                                            *   drop in voltage)                                                          */
+                uint8_t             : 4;
+                __IOM uint8_t LVD2E : 1;   /*!< [7..7] Voltage Detection 2 Enable                                         */
+            } LVD2CMPCR_b;
+        };
+    };
+    __IM uint8_t RESERVED45;
+
+    union
+    {
+        __IOM uint8_t LVD1CR0;         /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0               */
+
+        struct
+        {
+            __IOM uint8_t RIE   : 1;   /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
+            __IOM uint8_t DFDIS : 1;   /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select                 */
+            __IOM uint8_t CMPE  : 1;   /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
+            uint8_t             : 1;
+            __IOM uint8_t FSAMP : 2;   /*!< [5..4] Sampling Clock Select                                              */
+            __IOM uint8_t RI    : 1;   /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
+            __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
+        } LVD1CR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t LVD2CR0;         /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0               */
+
+        struct
+        {
+            __IOM uint8_t RIE   : 1;   /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
+            __IOM uint8_t DFDIS : 1;   /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select                 */
+            __IOM uint8_t CMPE  : 1;   /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
+            uint8_t             : 1;
+            __IOM uint8_t FSAMP : 2;   /*!< [5..4] Sampling Clock Select                                              */
+            __IOM uint8_t RI    : 1;   /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
+            __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
+        } LVD2CR0_b;
+    };
+    __IM uint8_t RESERVED46;
+
+    union
+    {
+        __IOM uint8_t VBATTMNSELR;        /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select
+                                           *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit                       */
+            uint8_t                  : 7;
+        } VBATTMNSELR_b;
+    };
+
+    union
+    {
+        __IM uint8_t VBATTMONR;        /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register                    */
+
+        struct
+        {
+            __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit                                          */
+            uint8_t               : 7;
+        } VBATTMONR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTCR1;           /*!< (@ 0x0000041F) VBATT Control Register1                                    */
+
+        struct
+        {
+            __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop                                   */
+            uint8_t                : 7;
+        } VBTCR1_b;
+    };
+    __IM uint32_t RESERVED47[8];
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t DCDCCTL;         /*!< (@ 0x00000440) DCDC/LDO Control Register                                  */
+
+            struct
+            {
+                __IOM uint8_t DCDCON  : 1; /*!< [0..0] LDO/DCDC on/off Control bit                                        */
+                __IOM uint8_t OCPEN   : 1; /*!< [1..1] DCDC OCP Function Enable bit                                       */
+                uint8_t               : 2;
+                __IOM uint8_t STOPZA  : 1; /*!< [4..4] DCDC IO Buffer Power Control bit                                   */
+                __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit                                       */
+                __IOM uint8_t FST     : 1; /*!< [6..6] DCDC Fast Startup                                                  */
+                __IOM uint8_t PD      : 1; /*!< [7..7] DCDC VREF Generate Disable bit                                     */
+            } DCDCCTL_b;
+        };
+
+        union
+        {
+            __IOM uint8_t LDOSCR;          /*!< (@ 0x00000440) LDO Stop Control Register                                  */
+
+            struct
+            {
+                __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop                                                          */
+                __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop                                                          */
+                uint8_t               : 6;
+            } LDOSCR_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint8_t VCCSEL;          /*!< (@ 0x00000441) Voltage Level Selection Control Register                   */
+
+        struct
+        {
+            __IOM uint8_t VCCSEL : 2;  /*!< [1..0] DCDC Working Voltage Level Selection                               */
+            uint8_t              : 6;
+        } VCCSEL_b;
+    };
+    __IM uint16_t RESERVED48;
+
+    union
+    {
+        __IOM uint8_t PL2LDOSCR;         /*!< (@ 0x00000444) PLL2-LDO Stop Control Register                             */
+
+        struct
+        {
+            __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop                                                          */
+            uint8_t                 : 7;
+        } PL2LDOSCR_b;
+    };
+    __IM uint8_t  RESERVED49;
+    __IM uint16_t RESERVED50;
+    __IM uint32_t RESERVED51[14];
+
+    union
+    {
+        __IOM uint8_t SOSCCR;          /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register                      */
+
+        struct
+        {
+            __IOM uint8_t SOSTP : 1;   /*!< [0..0] Sub-Clock Oscillator Stop                                          */
+            uint8_t             : 7;
+        } SOSCCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SOMCR;           /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register                 */
+
+        struct
+        {
+            __IOM uint8_t SODRV : 2;   /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching                    */
+            uint8_t             : 6;
+        } SOMCR_b;
+    };
+    __IM uint16_t RESERVED52;
+    __IM uint32_t RESERVED53[3];
+
+    union
+    {
+        __IOM uint8_t LOCOCR;          /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register              */
+
+        struct
+        {
+            __IOM uint8_t LCSTP : 1;   /*!< [0..0] LOCO Stop                                                          */
+            uint8_t             : 7;
+        } LOCOCR_b;
+    };
+    __IM uint8_t RESERVED54;
+
+    union
+    {
+        __IOM uint8_t LOCOUTCR;         /*!< (@ 0x00000492) LOCO User Trimming Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127
+                                         *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
+                                         *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
+                                         +126 0111_1111 : +127These bits are added to original LOCO
+                                         *   trimming bits                                                             */
+        } LOCOUTCR_b;
+    };
+    __IM uint8_t  RESERVED55;
+    __IM uint32_t RESERVED56[7];
+
+    union
+    {
+        __IOM uint8_t VBTCR2;          /*!< (@ 0x000004B0) VBATT Control Register2                                    */
+
+        struct
+        {
+            uint8_t                 : 4;
+            __IOM uint8_t VBTLVDEN  : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit                            */
+            uint8_t                 : 1;
+            __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit              */
+        } VBTCR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTSR;           /*!< (@ 0x000004B1) VBATT Status Register                                      */
+
+        struct
+        {
+            __IOM uint8_t VBTRDF  : 1; /*!< [0..0] VBAT_R Reset Detect Flag                                           */
+            __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag                              */
+            uint8_t               : 2;
+            __IM uint8_t VBTRVLD  : 1; /*!< [4..4] VBATT_R Valid                                                      */
+            uint8_t               : 3;
+        } VBTSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTCMPCR;        /*!< (@ 0x000004B2) VBATT Comparator Control Register                          */
+
+        struct
+        {
+            __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable                 */
+            uint8_t               : 7;
+        } VBTCMPCR_b;
+    };
+    __IM uint8_t RESERVED57;
+
+    union
+    {
+        __IOM uint8_t VBTLVDICR;          /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control
+                                           *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t VBTLVDIE   : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit                  */
+            __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit                        */
+            uint8_t                  : 6;
+        } VBTLVDICR_b;
+    };
+    __IM uint8_t RESERVED58;
+
+    union
+    {
+        __IOM uint8_t VBTWCTLR;        /*!< (@ 0x000004B6) VBATT Wakeup function Control Register                     */
+
+        struct
+        {
+            __IOM uint8_t VWEN : 1;    /*!< [0..0] VBATT wakeup enable                                                */
+            uint8_t            : 7;
+        } VBTWCTLR_b;
+    };
+    __IM uint8_t RESERVED59;
+
+    union
+    {
+        __IOM uint8_t VBTWCH0OTSR;     /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register          */
+
+        struct
+        {
+            uint8_t                  : 1;
+            __IOM uint8_t CH0VCH1TE  : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable                            */
+            __IOM uint8_t CH0VCH2TE  : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable                            */
+            __IOM uint8_t CH0VRTCTE  : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable                         */
+            __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable                            */
+            __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable                        */
+            uint8_t                  : 2;
+        } VBTWCH0OTSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTWCH1OTSR;        /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register          */
+
+        struct
+        {
+            __IOM uint8_t CH1VCH0TE  : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable                            */
+            uint8_t                  : 1;
+            __IOM uint8_t CH1VCH2TE  : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable                            */
+            __IOM uint8_t CH1VRTCTE  : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable                         */
+            __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable                            */
+            __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable                        */
+            uint8_t                  : 2;
+        } VBTWCH1OTSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTWCH2OTSR;        /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register          */
+
+        struct
+        {
+            __IOM uint8_t CH2VCH0TE  : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable                            */
+            __IOM uint8_t CH2VCH1TE  : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable                            */
+            uint8_t                  : 1;
+            __IOM uint8_t CH2VRTCTE  : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable                         */
+            __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable                            */
+            __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable                        */
+            uint8_t                  : 2;
+        } VBTWCH2OTSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTICTLR;         /*!< (@ 0x000004BB) VBATT Input Control Register                               */
+
+        struct
+        {
+            __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable                                                */
+            __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable                                                */
+            __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable                                                */
+            uint8_t                : 5;
+        } VBTICTLR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTOCTLR;          /*!< (@ 0x000004BC) VBATT Output Control Register                              */
+
+        struct
+        {
+            __IOM uint8_t VCH0OEN   : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable                                   */
+            __IOM uint8_t VCH1OEN   : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable                                   */
+            __IOM uint8_t VCH2OEN   : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable                                   */
+            __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection                          */
+            __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection                          */
+            __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection                          */
+            uint8_t                 : 2;
+        } VBTOCTLR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTWTER;         /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register                */
+
+        struct
+        {
+            __IOM uint8_t VCH0E  : 1;  /*!< [0..0] VBATWIO0 Pin Enable                                                */
+            __IOM uint8_t VCH1E  : 1;  /*!< [1..1] VBATWIO1 Pin Enable                                                */
+            __IOM uint8_t VCH2E  : 1;  /*!< [2..2] VBATWIO2 Pin Enable                                                */
+            __IOM uint8_t VRTCIE : 1;  /*!< [3..3] RTC Periodic Signal Enable                                         */
+            __IOM uint8_t VRTCAE : 1;  /*!< [4..4] RTC Alarm Signal Enable                                            */
+            __IOM uint8_t VAGTUE : 1;  /*!< [5..5] AGT(ch1) underflow Signal Enable                                   */
+            uint8_t              : 2;
+        } VBTWTER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTWEGR;         /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register                  */
+
+        struct
+        {
+            __IOM uint8_t VCH0EG : 1;  /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select                         */
+            __IOM uint8_t VCH1EG : 1;  /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select                         */
+            __IOM uint8_t VCH2EG : 1;  /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select                         */
+            uint8_t              : 5;
+        } VBTWEGR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTWFR;          /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register                  */
+
+        struct
+        {
+            __IOM uint8_t VCH0F  : 1;  /*!< [0..0] VBATWIO0 Wakeup Trigger Flag                                       */
+            __IOM uint8_t VCH1F  : 1;  /*!< [1..1] VBATWIO1 Wakeup Trigger Flag                                       */
+            __IOM uint8_t VCH2F  : 1;  /*!< [2..2] VBATWIO2 Wakeup Trigger Flag                                       */
+            __IOM uint8_t VRTCIF : 1;  /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag                             */
+            __IOM uint8_t VRTCAF : 1;  /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag                                */
+            __IOM uint8_t VAGTUF : 1;  /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag                       */
+            uint8_t              : 2;
+        } VBTWFR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTBER;          /*!< (@ 0x000004C0) VBATT Backup Enable Register                               */
+
+        struct
+        {
+            uint8_t            : 3;
+            __IOM uint8_t VBAE : 1;    /*!< [3..3] VBATT backup register access enable bit                            */
+            uint8_t            : 4;
+        } VBTBER_b;
+    };
+    __IM uint8_t  RESERVED60;
+    __IM uint16_t RESERVED61;
+    __IM uint32_t RESERVED62[15];
+
+    union
+    {
+        __IOM uint8_t VBTBKR[512];     /*!< (@ 0x00000500) VBATT Backup Register [0..511]                             */
+
+        struct
+        {
+            __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store
+                                        *   data powered by VBATT.The value of this register is retained
+                                        *   even when VCC is not powered but VBATT is powered.VBTBKR
+                                        *   is initialized by VBATT selected voltage power-on-reset.                  */
+        } VBTBKR_b[512];
+    };
+} R_SYSTEM_Type;                       /*!< Size = 1792 (0x700)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                         R_TSN_CAL                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Temperature Sensor (R_TSN_CAL)
+ */
+
+typedef struct                         /*!< (@ 0x407FB17C) R_TSN_CAL Structure                                        */
+{
+    union
+    {
+        __IM uint32_t TSCDR;           /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register        */
+
+        struct
+        {
+            __IM uint32_t TSCDR : 32;  /*!< [31..0] The 32 bit TSCDR register stores temperature sensor
+                                        *   calibration converted value.                                              */
+        } TSCDR_b;
+    };
+} R_TSN_CAL_Type;                      /*!< Size = 4 (0x4)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                        R_TSN_CTRL                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Temperature Sensor (R_TSN_CTRL)
+ */
+
+typedef struct                         /*!< (@ 0x400F3000) R_TSN_CTRL Structure                                       */
+{
+    union
+    {
+        __IOM uint8_t TSCR;            /*!< (@ 0x00000000) Temperature Sensor Control Register                        */
+
+        struct
+        {
+            uint8_t            : 4;
+            __IOM uint8_t TSOE : 1;    /*!< [4..4] Temperature Sensor Enable                                          */
+            uint8_t            : 2;
+            __IOM uint8_t TSEN : 1;    /*!< [7..7] Temperature Sensor Output Enable                                   */
+        } TSCR_b;
+    };
+} R_TSN_CTRL_Type;                     /*!< Size = 1 (0x1)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_USB_FS0                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief USB 2.0 Module (R_USB_FS0)
+ */
+
+typedef struct                         /*!< (@ 0x40090000) R_USB_FS0 Structure                                        */
+{
+    union
+    {
+        __IOM uint16_t SYSCFG;         /*!< (@ 0x00000000) System Configuration Control Register                      */
+
+        struct
+        {
+            __IOM uint16_t USBE  : 1;  /*!< [0..0] USB Operation Enable                                               */
+            uint16_t             : 2;
+            __IOM uint16_t DMRPU : 1;  /*!< [3..3] D- Line Resistor Control                                           */
+            __IOM uint16_t DPRPU : 1;  /*!< [4..4] D+ Line Resistor Control                                           */
+            __IOM uint16_t DRPD  : 1;  /*!< [5..5] D+/D- Line Resistor Control                                        */
+            __IOM uint16_t DCFM  : 1;  /*!< [6..6] Controller Function Select                                         */
+            uint16_t             : 1;
+            __IOM uint16_t CNEN  : 1;  /*!< [8..8] CNEN Single End Receiver Enable                                    */
+            uint16_t             : 1;
+            __IOM uint16_t SCKE  : 1;  /*!< [10..10] USB Clock Enable                                                 */
+            uint16_t             : 5;
+        } SYSCFG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t BUSWAIT;        /*!< (@ 0x00000002) CPU Bus Wait Register                                      */
+
+        struct
+        {
+            __IOM uint16_t BWAIT : 4;  /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
+                                        *   access cycles)                                                            */
+            uint16_t : 12;
+        } BUSWAIT_b;
+    };
+
+    union
+    {
+        __IM uint16_t SYSSTS0;         /*!< (@ 0x00000004) System Configuration Status Register 0                     */
+
+        struct
+        {
+            __IM uint16_t LNST  : 2;   /*!< [1..0] USB Data Line Status Monitor                                       */
+            __IM uint16_t IDMON : 1;   /*!< [2..2] External ID0 Input Pin Monitor                                     */
+            uint16_t            : 2;
+            __IM uint16_t SOFEA : 1;   /*!< [5..5] SOF Active Monitor While Host Controller Function is
+                                        *   Selected.                                                                 */
+            __IM uint16_t HTACT  : 1;  /*!< [6..6] USB Host Sequencer Status Monitor                                  */
+            uint16_t             : 7;
+            __IM uint16_t OVCMON : 2;  /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe
+                                        *   OCVMON[1] bit indicates the status of the USBHS_OVRCURA
+                                        *   pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
+                                        *   pin.                                                                      */
+        } SYSSTS0_b;
+    };
+
+    union
+    {
+        __IM uint16_t PLLSTA;          /*!< (@ 0x00000006) PLL Status Register                                        */
+
+        struct
+        {
+            __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag                                                      */
+            uint16_t              : 15;
+        } PLLSTA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DVSTCTR0;        /*!< (@ 0x00000008) Device State Control Register 0                            */
+
+        struct
+        {
+            __IM uint16_t RHST     : 3; /*!< [2..0] USB Bus Reset Status                                               */
+            uint16_t               : 1;
+            __IOM uint16_t UACT    : 1; /*!< [4..4] USB Bus Enable                                                     */
+            __IOM uint16_t RESUME  : 1; /*!< [5..5] Resume Output                                                      */
+            __IOM uint16_t USBRST  : 1; /*!< [6..6] USB Bus Reset Output                                               */
+            __IOM uint16_t RWUPE   : 1; /*!< [7..7] Wakeup Detection Enable                                            */
+            __IOM uint16_t WKUP    : 1; /*!< [8..8] Wakeup Output                                                      */
+            __IOM uint16_t VBUSEN  : 1; /*!< [9..9] USB_VBUSEN Output Pin Control                                      */
+            __IOM uint16_t EXICEN  : 1; /*!< [10..10] USB_EXICEN Output Pin Control                                    */
+            __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is
+                                         *   used when switching from device B to device A while in
+                                         *   OTG mode. If the HNPBTOA bit is 1, the internal function
+                                         *   control keeps the suspended state until the HNP processing
+                                         *   ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is
+                                         *   set.                                                                      */
+            uint16_t : 4;
+        } DVSTCTR0_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t TESTMODE;       /*!< (@ 0x0000000C) USB Test Mode Register                                     */
+
+        struct
+        {
+            __IOM uint16_t UTST : 4;   /*!< [3..0] Test Mode                                                          */
+            uint16_t            : 12;
+        } TESTMODE_b;
+    };
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t CFIFO;          /*!< (@ 0x00000014) CFIFO Port Register                                        */
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t CFIFOL;  /*!< (@ 0x00000014) CFIFO Port Register L                                      */
+                __IOM uint8_t  CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL                                     */
+            };
+
+            union
+            {
+                __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H                                      */
+
+                struct
+                {
+                    __IM uint8_t  RESERVED3;
+                    __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH                                     */
+                };
+            };
+        };
+    };
+
+    union
+    {
+        __IOM uint32_t D0FIFO;         /*!< (@ 0x00000018) D0FIFO Port Register                                       */
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t D0FIFOL;  /*!< (@ 0x00000018) D0FIFO Port Register L                                     */
+                __IOM uint8_t  D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL                                    */
+            };
+
+            union
+            {
+                __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H                                     */
+
+                struct
+                {
+                    __IM uint8_t  RESERVED4;
+                    __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH                                    */
+                };
+            };
+        };
+    };
+
+    union
+    {
+        __IOM uint32_t D1FIFO;         /*!< (@ 0x0000001C) D1FIFO Port Register                                       */
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t D1FIFOL;  /*!< (@ 0x0000001C) D1FIFO Port Register L                                     */
+                __IOM uint8_t  D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL                                    */
+            };
+
+            union
+            {
+                __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H                                     */
+
+                struct
+                {
+                    __IM uint8_t  RESERVED5;
+                    __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH                                    */
+                };
+            };
+        };
+    };
+
+    union
+    {
+        __IOM uint16_t CFIFOSEL;        /*!< (@ 0x00000020) CFIFO Port Select Register                                 */
+
+        struct
+        {
+            __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification                               */
+            uint16_t               : 1;
+            __IOM uint16_t ISEL    : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected                   */
+            uint16_t               : 2;
+            __IOM uint16_t BIGEND  : 1; /*!< [8..8] CFIFO Port Endian Control                                          */
+            uint16_t               : 1;
+            __IOM uint16_t MBW     : 2; /*!< [11..10] CFIFO Port Access Bit Width                                      */
+            uint16_t               : 2;
+            __IOM uint16_t REW     : 1; /*!< [14..14] Buffer Pointer Rewind                                            */
+            __IOM uint16_t RCNT    : 1; /*!< [15..15] Read Count Mode                                                  */
+        } CFIFOSEL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t CFIFOCTR;       /*!< (@ 0x00000022) CFIFO Port Control Register                                */
+
+        struct
+        {
+            __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
+                                        *   data.                                                                     */
+            uint16_t            : 1;
+            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
+            __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
+            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
+        } CFIFOCTR_b;
+    };
+    __IM uint32_t RESERVED6;
+
+    union
+    {
+        __IOM uint16_t D0FIFOSEL;       /*!< (@ 0x00000028) D0FIFO Port Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
+            uint16_t               : 4;
+            __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
+            uint16_t               : 1;
+            __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
+            __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
+            __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
+                                         *   Pipe Data is Read                                                         */
+            __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read.                   */
+            __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
+        } D0FIFOSEL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t D0FIFOCTR;      /*!< (@ 0x0000002A) D0FIFO Port Control Register                               */
+
+        struct
+        {
+            __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
+                                        *   data.                                                                     */
+            uint16_t            : 1;
+            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
+            __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
+            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
+        } D0FIFOCTR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t D1FIFOSEL;       /*!< (@ 0x0000002C) D1FIFO Port Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
+            uint16_t               : 4;
+            __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
+            uint16_t               : 1;
+            __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
+            __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
+            __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
+                                         *   Pipe Data is Read                                                         */
+            __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
+            __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
+        } D1FIFOSEL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t D1FIFOCTR;      /*!< (@ 0x0000002E) D1FIFO Port Control Register                               */
+
+        struct
+        {
+            __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
+                                        *   data.                                                                     */
+            uint16_t            : 1;
+            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
+            __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
+            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
+        } D1FIFOCTR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTENB0;        /*!< (@ 0x00000030) Interrupt Enable Register 0                                */
+
+        struct
+        {
+            uint16_t             : 8;
+            __IOM uint16_t BRDYE : 1;  /*!< [8..8] Buffer Ready Interrupt Enable                                      */
+            __IOM uint16_t NRDYE : 1;  /*!< [9..9] Buffer Not Ready Response Interrupt Enable                         */
+            __IOM uint16_t BEMPE : 1;  /*!< [10..10] Buffer Empty Interrupt Enable                                    */
+            __IOM uint16_t CTRE  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Enable               */
+            __IOM uint16_t DVSE  : 1;  /*!< [12..12] Device State Transition Interrupt Enable                         */
+            __IOM uint16_t SOFE  : 1;  /*!< [13..13] Frame Number Update Interrupt Enable                             */
+            __IOM uint16_t RSME  : 1;  /*!< [14..14] Resume Interrupt Enable                                          */
+            __IOM uint16_t VBSE  : 1;  /*!< [15..15] VBUS Interrupt Enable                                            */
+        } INTENB0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTENB1;            /*!< (@ 0x00000032) Interrupt Enable Register 1                                */
+
+        struct
+        {
+            __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable                               */
+            uint16_t                  : 3;
+            __IOM uint16_t SACKE      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable                 */
+            __IOM uint16_t SIGNE      : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable                           */
+            __IOM uint16_t EOFERRE    : 1; /*!< [6..6] EOF Error Detection Interrupt Enable                               */
+            uint16_t                  : 4;
+            __IOM uint16_t ATTCHE     : 1; /*!< [11..11] Connection Detection Interrupt Enable                            */
+            __IOM uint16_t DTCHE      : 1; /*!< [12..12] Disconnection Detection Interrupt Enable                         */
+            uint16_t                  : 1;
+            __IOM uint16_t BCHGE      : 1; /*!< [14..14] USB Bus Change Interrupt Enable                                  */
+            __IOM uint16_t OVRCRE     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable                        */
+        } INTENB1_b;
+    };
+    __IM uint16_t RESERVED7;
+
+    union
+    {
+        __IOM uint16_t BRDYENB;            /*!< (@ 0x00000036) BRDY Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE                                     */
+            uint16_t                  : 6;
+        } BRDYENB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t NRDYENB;            /*!< (@ 0x00000038) NRDY Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE                                     */
+            uint16_t                  : 6;
+        } NRDYENB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t BEMPENB;            /*!< (@ 0x0000003A) BEMP Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE                                     */
+            uint16_t                  : 6;
+        } BEMPENB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t SOFCFG;         /*!< (@ 0x0000003C) SOF Output Configuration Register                          */
+
+        struct
+        {
+            uint16_t                : 4;
+            __IM uint16_t  EDGESTS  : 1; /*!< [4..4] Edge Interrupt Output Status Monitor                               */
+            __IOM uint16_t INTL     : 1; /*!< [5..5] Interrupt Output Sense Select                                      */
+            __IOM uint16_t BRDYM    : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing                                 */
+            uint16_t                : 1;
+            __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select                                    */
+            uint16_t                : 7;
+        } SOFCFG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PHYSET;           /*!< (@ 0x0000003E) PHY Setting Register                                       */
+
+        struct
+        {
+            __IOM uint16_t DIRPD    : 1; /*!< [0..0] Power-Down Control                                                 */
+            __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control                                                  */
+            uint16_t                : 1;
+            __IOM uint16_t CDPEN    : 1; /*!< [3..3] Charging Downstream Port Enable                                    */
+            __IOM uint16_t CLKSEL   : 2; /*!< [5..4] Input System Clock Frequency                                       */
+            uint16_t                : 2;
+            __IOM uint16_t REPSEL   : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle                            */
+            uint16_t                : 1;
+            __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment                 */
+            uint16_t                : 3;
+            __IOM uint16_t HSEB     : 1; /*!< [15..15] CL-Only Mode                                                     */
+        } PHYSET_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTSTS0;        /*!< (@ 0x00000040) Interrupt Status Register 0                                */
+
+        struct
+        {
+            __IM uint16_t  CTSQ  : 3;  /*!< [2..0] Control Transfer Stage                                             */
+            __IOM uint16_t VALID : 1;  /*!< [3..3] USB Request Reception                                              */
+            __IM uint16_t  DVSQ  : 3;  /*!< [6..4] Device State                                                       */
+            __IM uint16_t  VBSTS : 1;  /*!< [7..7] VBUS Input Status                                                  */
+            __IM uint16_t  BRDY  : 1;  /*!< [8..8] Buffer Ready Interrupt Status                                      */
+            __IM uint16_t  NRDY  : 1;  /*!< [9..9] Buffer Not Ready Interrupt Status                                  */
+            __IM uint16_t  BEMP  : 1;  /*!< [10..10] Buffer Empty Interrupt Status                                    */
+            __IOM uint16_t CTRT  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Status               */
+            __IOM uint16_t DVST  : 1;  /*!< [12..12] Device State Transition Interrupt Status                         */
+            __IOM uint16_t SOFR  : 1;  /*!< [13..13] Frame Number Refresh Interrupt Status                            */
+            __IOM uint16_t RESM  : 1;  /*!< [14..14] Resume Interrupt Status                                          */
+            __IOM uint16_t VBINT : 1;  /*!< [15..15] VBUS Interrupt Status                                            */
+        } INTSTS0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTSTS1;           /*!< (@ 0x00000042) Interrupt Status Register 1                                */
+
+        struct
+        {
+            __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status                                  */
+            uint16_t                 : 3;
+            __IOM uint16_t SACK      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status                 */
+            __IOM uint16_t SIGN      : 1; /*!< [5..5] Setup Transaction Error Interrupt Status                           */
+            __IOM uint16_t EOFERR    : 1; /*!< [6..6] EOF Error Detection Interrupt Status                               */
+            uint16_t                 : 1;
+            __IOM uint16_t LPMEND    : 1; /*!< [8..8] LPM Transaction End Interrupt Status                               */
+            __IOM uint16_t L1RSMEND  : 1; /*!< [9..9] L1 Resume End Interrupt Status                                     */
+            uint16_t                 : 1;
+            __IOM uint16_t ATTCH     : 1; /*!< [11..11] ATTCH Interrupt Status                                           */
+            __IOM uint16_t DTCH      : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status                     */
+            uint16_t                 : 1;
+            __IOM uint16_t BCHG      : 1; /*!< [14..14] USB Bus Change Interrupt Status                                  */
+            __IOM uint16_t OVRCR     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status                        */
+        } INTSTS1_b;
+    };
+    __IM uint16_t RESERVED8;
+
+    union
+    {
+        __IOM uint16_t BRDYSTS;           /*!< (@ 0x00000046) BRDY Interrupt Status Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE                                     */
+            uint16_t                 : 6;
+        } BRDYSTS_b;
+    };
+
+    union
+    {
+        __IOM uint16_t NRDYSTS;           /*!< (@ 0x00000048) NRDY Interrupt Status Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE                                     */
+            uint16_t                 : 6;
+        } NRDYSTS_b;
+    };
+
+    union
+    {
+        __IOM uint16_t BEMPSTS;           /*!< (@ 0x0000004A) BEMP Interrupt Status Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE                                     */
+            uint16_t                 : 6;
+        } BEMPSTS_b;
+    };
+
+    union
+    {
+        __IOM uint16_t FRMNUM;         /*!< (@ 0x0000004C) Frame Number Register                                      */
+
+        struct
+        {
+            __IM uint16_t FRNM  : 11;  /*!< [10..0] Frame NumberLatest frame number                                   */
+            uint16_t            : 3;
+            __IOM uint16_t CRCE : 1;   /*!< [14..14] Receive Data Error                                               */
+            __IOM uint16_t OVRN : 1;   /*!< [15..15] Overrun/Underrun Detection Status                                */
+        } FRMNUM_b;
+    };
+
+    union
+    {
+        __IOM uint16_t UFRMNUM;        /*!< (@ 0x0000004E) uFrame Number Register                                     */
+
+        struct
+        {
+            __IM uint16_t UFRNM  : 3;  /*!< [2..0] MicroframeIndicate the microframe number.                          */
+            uint16_t             : 12;
+            __IOM uint16_t DVCHG : 1;  /*!< [15..15] Device State Change                                              */
+        } UFRMNUM_b;
+    };
+
+    union
+    {
+        __IOM uint16_t USBADDR;           /*!< (@ 0x00000050) USB Address Register                                       */
+
+        struct
+        {
+            __IM uint16_t USBADDR : 7;    /*!< [6..0] USB Address In device controller mode, these flags indicate
+                                           *   the USB address assigned by the host when the USBHS processed
+                                           *   the SET_ADDRESS request successfully.                                     */
+            uint16_t                 : 1;
+            __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery                                                   */
+            uint16_t                 : 5;
+        } USBADDR_b;
+    };
+    __IM uint16_t RESERVED9;
+
+    union
+    {
+        __IOM uint16_t USBREQ;                /*!< (@ 0x00000054) USB Request Type Register                                  */
+
+        struct
+        {
+            __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType
+                                               *   value.                                                                    */
+            __IOM uint16_t BREQUEST : 8;      /*!< [15..8] RequestThese bits store the USB request bRequest value.           */
+        } USBREQ_b;
+    };
+
+    union
+    {
+        __IOM uint16_t USBVAL;          /*!< (@ 0x00000056) USB Request Value Register                                 */
+
+        struct
+        {
+            __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value.                */
+        } USBVAL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t USBINDX;         /*!< (@ 0x00000058) USB Request Index Register                                 */
+
+        struct
+        {
+            __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value.               */
+        } USBINDX_b;
+    };
+
+    union
+    {
+        __IOM uint16_t USBLENG;          /*!< (@ 0x0000005A) USB Request Length Register                                */
+
+        struct
+        {
+            __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value.             */
+        } USBLENG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DCPCFG;         /*!< (@ 0x0000005C) DCP Configuration Register                                 */
+
+        struct
+        {
+            uint16_t              : 4;
+            __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
+            uint16_t              : 2;
+            __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
+            __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
+            uint16_t              : 7;
+        } DCPCFG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DCPMAXP;        /*!< (@ 0x0000005E) DCP Maximum Packet Size Register                           */
+
+        struct
+        {
+            __IOM uint16_t MXPS : 7;   /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount
+                                        *   of data (maximum packet size) in payloads for the DCP.                    */
+            uint16_t              : 5;
+            __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
+        } DCPMAXP_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DCPCTR;           /*!< (@ 0x00000060) DCP Control Register                                       */
+
+        struct
+        {
+            __IOM uint16_t PID      : 2; /*!< [1..0] Response PID                                                       */
+            __IOM uint16_t CCPL     : 1; /*!< [2..2] Control Transfer End Enable                                        */
+            uint16_t                : 2;
+            __IM uint16_t  PBUSY    : 1; /*!< [5..5] Pipe Busy                                                          */
+            __IM uint16_t  SQMON    : 1; /*!< [6..6] Sequence Toggle Bit Monitor                                        */
+            __IOM uint16_t SQSET    : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
+            __IOM uint16_t SQCLR    : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
+            uint16_t                : 2;
+            __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear                                                  */
+            uint16_t                : 2;
+            __IOM uint16_t SUREQ    : 1; /*!< [14..14] Setup Token Transmission                                         */
+            __IM uint16_t  BSTS     : 1; /*!< [15..15] Buffer Status                                                    */
+        } DCPCTR_b;
+    };
+    __IM uint16_t RESERVED10;
+
+    union
+    {
+        __IOM uint16_t PIPESEL;         /*!< (@ 0x00000064) Pipe Window Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select                                                 */
+            uint16_t               : 12;
+        } PIPESEL_b;
+    };
+    __IM uint16_t RESERVED11;
+
+    union
+    {
+        __IOM uint16_t PIPECFG;        /*!< (@ 0x00000068) Pipe Configuration Register                                */
+
+        struct
+        {
+            __IOM uint16_t EPNUM : 4;  /*!< [3..0] Endpoint NumberThese bits specify the endpoint number
+                                        *   for the selected pipe.Setting 0000b means unused pipe.                    */
+            __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
+            uint16_t              : 2;
+            __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
+            uint16_t              : 1;
+            __IOM uint16_t DBLB   : 1; /*!< [9..9] Double Buffer Mode                                                 */
+            __IOM uint16_t BFRE   : 1; /*!< [10..10] BRDY Interrupt Operation Specification                           */
+            uint16_t              : 3;
+            __IOM uint16_t TYPE   : 2; /*!< [15..14] Transfer Type                                                    */
+        } PIPECFG_b;
+    };
+    __IM uint16_t RESERVED12;
+
+    union
+    {
+        __IOM uint16_t PIPEMAXP;       /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register                          */
+
+        struct
+        {
+            __IOM uint16_t MXPS : 9;   /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to
+                                        *   256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes
+                                        *   (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and
+                                        *   [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to
+                                        *   64 bytes (040h) (Bits [8:7] are not provided.)                            */
+            uint16_t              : 3;
+            __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
+        } PIPEMAXP_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PIPEPERI;       /*!< (@ 0x0000006E) Pipe Cycle Control Register                                */
+
+        struct
+        {
+            __IOM uint16_t IITV : 3;   /*!< [2..0] Interval Error Detection IntervalSpecifies the interval
+                                        *   error detection timing for the selected pipe in terms of
+                                        *   frames, which is expressed as nth power of 2.                             */
+            uint16_t            : 9;
+            __IOM uint16_t IFIS : 1;   /*!< [12..12] Isochronous IN Buffer Flush                                      */
+            uint16_t            : 3;
+        } PIPEPERI_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PIPE_CTR[9];    /*!< (@ 0x00000070) Pipe [0..8] Control Register                               */
+
+        struct
+        {
+            __IOM uint16_t PID    : 2; /*!< [1..0] Response PID                                                       */
+            uint16_t              : 3;
+            __IM uint16_t  PBUSY  : 1; /*!< [5..5] Pipe Busy                                                          */
+            __IM uint16_t  SQMON  : 1; /*!< [6..6] Sequence Toggle Bit Confirmation                                   */
+            __IOM uint16_t SQSET  : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
+            __IOM uint16_t SQCLR  : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
+            __IOM uint16_t ACLRM  : 1; /*!< [9..9] Auto Buffer Clear Mode                                             */
+            __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode                                               */
+            uint16_t              : 1;
+            __IM uint16_t CSSTS   : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
+                                        *   Split Transaction of the relevant pipe                                    */
+            __IOM uint16_t CSCLR : 1;  /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
+                                        *   the CSSTS bit of the relevant pipe                                        */
+            __IM uint16_t INBUFM : 1;  /*!< [14..14] Transmit Buffer Monitor                                          */
+            __IM uint16_t BSTS   : 1;  /*!< [15..15] Buffer Status                                                    */
+        } PIPE_CTR_b[9];
+    };
+    __IM uint16_t                RESERVED13;
+    __IM uint32_t                RESERVED14[3];
+    __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers                         */
+    __IM uint32_t                RESERVED15[3];
+
+    union
+    {
+        __IOM uint16_t USBBCCTRL0;         /*!< (@ 0x000000B0) BC Control Register 0                                      */
+
+        struct
+        {
+            __IOM uint16_t RPDME0     : 1; /*!< [0..0] D- Pin Pull-Down Control                                           */
+            __IOM uint16_t IDPSRCE0   : 1; /*!< [1..1] D+ Pin IDPSRC Output Control                                       */
+            __IOM uint16_t IDMSINKE0  : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control         */
+            __IOM uint16_t VDPSRCE0   : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control                               */
+            __IOM uint16_t IDPSINKE0  : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control         */
+            __IOM uint16_t VDMSRCE0   : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control                               */
+            uint16_t                  : 1;
+            __IOM uint16_t BATCHGE0   : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control           */
+            __IM uint16_t  CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status                                */
+            __IM uint16_t  PDDETSTS0  : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status                                */
+            uint16_t                  : 6;
+        } USBBCCTRL0_b;
+    };
+    __IM uint16_t RESERVED16;
+    __IM uint32_t RESERVED17[4];
+
+    union
+    {
+        __IOM uint16_t UCKSEL;          /*!< (@ 0x000000C4) USB Clock Selection Register                               */
+
+        struct
+        {
+            __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection                                                */
+            uint16_t               : 15;
+        } UCKSEL_b;
+    };
+    __IM uint16_t RESERVED18;
+    __IM uint32_t RESERVED19;
+
+    union
+    {
+        __IOM uint16_t USBMC;           /*!< (@ 0x000000CC) USB Module Control Register                                */
+
+        struct
+        {
+            __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control                  */
+            uint16_t               : 6;
+            __IOM uint16_t VDCEN   : 1; /*!< [7..7] USB Regulator On/Off Control                                       */
+            uint16_t               : 8;
+        } USBMC_b;
+    };
+    __IM uint16_t RESERVED20;
+
+    union
+    {
+        __IOM uint16_t DEVADD[10];     /*!< (@ 0x000000D0) Device Address Configuration Register                      */
+
+        struct
+        {
+            uint16_t               : 6;
+            __IOM uint16_t USBSPD  : 2; /*!< [7..6] Transfer Speed of Communication Target Device                      */
+            __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port                          */
+            __IOM uint16_t UPPHUB  : 4; /*!< [14..11] Communication Target Connecting Hub Register                     */
+            uint16_t               : 1;
+        } DEVADD_b[10];
+    };
+    __IM uint32_t RESERVED21[3];
+
+    union
+    {
+        __IOM uint32_t PHYSLEW;         /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register                        */
+
+        struct
+        {
+            __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00                                 */
+            __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01                                 */
+            __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00                                 */
+            __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01                                 */
+            uint32_t               : 28;
+        } PHYSLEW_b;
+    };
+    __IM uint32_t RESERVED22[3];
+
+    union
+    {
+        __IOM uint16_t LPCTRL;         /*!< (@ 0x00000100) Low Power Control Register                                 */
+
+        struct
+        {
+            uint16_t             : 7;
+            __IOM uint16_t HWUPM : 1;  /*!< [7..7] Resume Return Mode Setting                                         */
+            uint16_t             : 8;
+        } LPCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t LPSTS;          /*!< (@ 0x00000102) Low Power Status Register                                  */
+
+        struct
+        {
+            uint16_t                : 14;
+            __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control                                            */
+            uint16_t                : 1;
+        } LPSTS_b;
+    };
+    __IM uint32_t RESERVED23[15];
+
+    union
+    {
+        __IOM uint16_t BCCTRL;           /*!< (@ 0x00000140) Battery Charging Control Register                          */
+
+        struct
+        {
+            __IOM uint16_t IDPSRCE  : 1; /*!< [0..0] IDPSRC Control                                                     */
+            __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control                                                    */
+            __IOM uint16_t VDPSRCE  : 1; /*!< [2..2] VDPSRC Control                                                     */
+            __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control                                                    */
+            __IOM uint16_t VDMSRCE  : 1; /*!< [4..4] VDMSRC Control                                                     */
+            __IOM uint16_t DCPMODE  : 1; /*!< [5..5] DCP Mode Control                                                   */
+            uint16_t                : 2;
+            __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status                                                      */
+            __IM uint16_t PDDETSTS  : 1; /*!< [9..9] PDDET Status                                                       */
+            uint16_t                : 6;
+        } BCCTRL_b;
+    };
+    __IM uint16_t RESERVED24;
+
+    union
+    {
+        __IOM uint16_t PL1CTRL1;         /*!< (@ 0x00000144) Function L1 Control Register 1                             */
+
+        struct
+        {
+            __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable                                                 */
+            __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode                                                   */
+            __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
+                                          *   only when the L1RESPMD[1:0] value is 2'b11.                               */
+            __IM uint16_t DVSQ : 4;      /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
+                                          *   the L1 state together with the device state bits DVSQ[2:0].               */
+            __IOM uint16_t HIRDTHR : 4;  /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
+                                          *   value used for L1NEGOMD.The format is the same as the HIRD
+                                          *   field in HL1CTRL.                                                         */
+            uint16_t               : 2;
+            __IOM uint16_t L1EXTMD : 1;  /*!< [14..14] PHY Control Mode at L1 Return                                    */
+            uint16_t               : 1;
+        } PL1CTRL1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PL1CTRL2;       /*!< (@ 0x00000146) Function L1 Control Register 2                             */
+
+        struct
+        {
+            uint16_t               : 8;
+            __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor                                                */
+            __IOM uint16_t RWEMON  : 1; /*!< [12..12] RWE Value Monitor                                                */
+            uint16_t               : 3;
+        } PL1CTRL2_b;
+    };
+
+    union
+    {
+        __IOM uint16_t HL1CTRL1;         /*!< (@ 0x00000148) Host L1 Control Register 1                                 */
+
+        struct
+        {
+            __IOM uint16_t L1REQ    : 1; /*!< [0..0] L1 Transition Request                                              */
+            __IM uint16_t  L1STATUS : 2; /*!< [2..1] L1 Request Completion Status                                       */
+            uint16_t                : 13;
+        } HL1CTRL1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t HL1CTRL2;       /*!< (@ 0x0000014A) Host L1 Control Register 2                                 */
+
+        struct
+        {
+            __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
+                                        *   be set in the ADDR field of LPM token.                                    */
+            uint16_t             : 4;
+            __IOM uint16_t HIRD  : 4;  /*!< [11..8] LPM Token HIRD                                                    */
+            __IOM uint16_t L1RWE : 1;  /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
+                                        *   value to be set in the RWE field of LPM token.                            */
+            uint16_t            : 2;
+            __IOM uint16_t BESL : 1;   /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
+                                        *   period at the time of L1 Resume.                                          */
+        } HL1CTRL2_b;
+    };
+    __IM uint32_t RESERVED25[5];
+
+    union
+    {
+        __IM uint32_t DPUSR0R;         /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
+                                        *                  Register                                                   */
+
+        struct
+        {
+            uint32_t              : 20;
+            __IM uint32_t DOVCAHM : 1;  /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
+                                         *   HS side of USB port.                                                      */
+            __IM uint32_t DOVCBHM : 1;  /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
+                                         *   HS side of USB port.                                                      */
+            uint32_t               : 1;
+            __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
+                                         *   of USB port.                                                              */
+            uint32_t : 8;
+        } DPUSR0R_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DPUSR1R;        /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register         */
+
+        struct
+        {
+            uint32_t                : 4;
+            __IOM uint32_t DOVCAHE  : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear                                     */
+            __IOM uint32_t DOVCBHE  : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear                                     */
+            uint32_t                : 1;
+            __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear                                        */
+            uint32_t                : 12;
+            __IM uint32_t DOVCAH    : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source               */
+            __IM uint32_t DOVCBH    : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source               */
+            uint32_t                : 1;
+            __IM uint32_t DVBSTSH   : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source                  */
+            uint32_t                : 8;
+        } DPUSR1R_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DPUSR2R;        /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register         */
+
+        struct
+        {
+            __IM uint16_t DPINT : 1;   /*!< [0..0] Indication of Return from DP Interrupt Source                      */
+            __IM uint16_t DMINT : 1;   /*!< [1..1] Indication of Return from DM Interrupt Source                      */
+            uint16_t            : 2;
+            __IM uint16_t DPVAL : 1;   /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
+                                        *   port.                                                                     */
+            __IM uint16_t DMVAL : 1;   /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
+                                        *   port.                                                                     */
+            uint16_t              : 2;
+            __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear                                          */
+            __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear                                          */
+            uint16_t              : 6;
+        } DPUSR2R_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DPUSRCR;          /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register           */
+
+        struct
+        {
+            __IOM uint16_t FIXPHY   : 1; /*!< [0..0] USB Transceiver Control Fix                                        */
+            __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL                                */
+            uint16_t                : 14;
+        } DPUSRCR_b;
+    };
+    __IM uint32_t RESERVED26[165];
+
+    union
+    {
+        __IOM uint32_t DPUSR0R_FS;      /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin
+                                         *                  Monitor Register                                           */
+
+        struct
+        {
+            __IOM uint32_t SRPC0   : 1; /*!< [0..0] USB Single End Receiver Control                                    */
+            __IOM uint32_t RPUE0   : 1; /*!< [1..1] DP Pull-Up Resistor Control                                        */
+            uint32_t               : 1;
+            __IOM uint32_t DRPD0   : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control                                   */
+            __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix                                         */
+            uint32_t               : 11;
+            __IM uint32_t DP0      : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB.           */
+            __IM uint32_t DM0      : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB.             */
+            uint32_t               : 2;
+            __IM uint32_t DOVCA0   : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal
+                                         *   of the USB.                                                               */
+            __IM uint32_t DOVCB0 : 1;   /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal
+                                         *   of the USB.                                                               */
+            uint32_t              : 1;
+            __IM uint32_t DVBSTS0 : 1;  /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the
+                                         *   USB.                                                                      */
+            uint32_t : 8;
+        } DPUSR0R_FS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DPUSR1R_FS;        /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt
+                                           *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t DPINTE0   : 1; /*!< [0..0] USB DP Interrupt Enable/Clear                                      */
+            __IOM uint32_t DMINTE0   : 1; /*!< [1..1] USB DM Interrupt Enable/Clear                                      */
+            uint32_t                 : 2;
+            __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear                                 */
+            __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear                                 */
+            uint32_t                 : 1;
+            __IOM uint32_t DVBSE0    : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear                                    */
+            uint32_t                 : 8;
+            __IM uint32_t DPINT0     : 1; /*!< [16..16] USB DP Interrupt Source Recovery                                 */
+            __IM uint32_t DMINT0     : 1; /*!< [17..17] USB DM Interrupt Source Recovery                                 */
+            uint32_t                 : 2;
+            __IM uint32_t DOVRCRA0   : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery                            */
+            __IM uint32_t DOVRCRB0   : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery                            */
+            uint32_t                 : 1;
+            __IM uint32_t DVBINT0    : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery                               */
+            uint32_t                 : 8;
+        } DPUSR1R_FS_b;
+    };
+} R_USB_FS0_Type;                         /*!< Size = 1032 (0x408)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                           R_WDT                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Watchdog Timer (R_WDT)
+ */
+
+typedef struct                         /*!< (@ 0x40083400) R_WDT Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t WDTRR;           /*!< (@ 0x00000000) WDT Refresh Register                                       */
+
+        struct
+        {
+            __IOM uint8_t WDTRR : 8;   /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter
+                                        *   of the WDT.                                                               */
+        } WDTRR_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t WDTCR;          /*!< (@ 0x00000002) WDT Control Register                                       */
+
+        struct
+        {
+            __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
+            uint16_t            : 2;
+            __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
+            __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
+            uint16_t            : 2;
+            __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
+            uint16_t            : 2;
+        } WDTCR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t WDTSR;           /*!< (@ 0x00000004) WDT Status Register                                        */
+
+        struct
+        {
+            __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
+            __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
+            __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
+        } WDTSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t WDTRCR;          /*!< (@ 0x00000006) WDT Reset Control Register                                 */
+
+        struct
+        {
+            uint8_t               : 7;
+            __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
+        } WDTRCR_b;
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        __IOM uint8_t WDTCSTPR;        /*!< (@ 0x00000008) WDT Count Stop Control Register                            */
+
+        struct
+        {
+            uint8_t              : 7;
+            __IOM uint8_t SLCSTP : 1;  /*!< [7..7] Sleep-Mode Count Stop Control                                      */
+        } WDTCSTPR_b;
+    };
+    __IM uint8_t  RESERVED2;
+    __IM uint16_t RESERVED3;
+} R_WDT_Type;                          /*!< Size = 12 (0xc)                                                           */
+
+/* =========================================================================================================================== */
+/* ================                                           R_TZF                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief TrustZone Filter (R_TZF)
+ */
+
+typedef struct                         /*!< (@ 0x40000E00) R_TZF Structure                                            */
+{
+    union
+    {
+        __IOM uint16_t TZFOAD;         /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register        */
+
+        struct
+        {
+            __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
+            uint16_t           : 7;
+            __OM uint16_t KEY  : 8;    /*!< [15..8] KeyCode                                                           */
+        } TZFOAD_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t TZFPT;           /*!< (@ 0x00000004) TrustZone Filter Protect Register                          */
+
+        struct
+        {
+            __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
+            uint16_t               : 7;
+            __OM uint16_t KEY      : 8; /*!< [15..8] KeyCode                                                           */
+        } TZFPT_b;
+    };
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2[94];
+
+    union
+    {
+        __IOM uint32_t TZFSAR;         /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register             */
+
+        struct
+        {
+            __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter              */
+            uint32_t              : 31;
+        } TZFSAR_b;
+    };
+} R_TZF_Type;                          /*!< Size = 388 (0x184)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CACHE                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief R_CACHE (R_CACHE)
+ */
+
+typedef struct                         /*!< (@ 0x40007000) R_CACHE Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t CCACTL;         /*!< (@ 0x00000000) C-Cache Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ENC : 1;    /*!< [0..0] C-Cache Enable                                                     */
+            uint32_t           : 31;
+        } CCACTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCAFCT;         /*!< (@ 0x00000004) C-Cache Flush Control Register                             */
+
+        struct
+        {
+            __IOM uint32_t FC : 1;     /*!< [0..0] C-Cache Flush                                                      */
+            uint32_t          : 31;
+        } CCAFCT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CCALCF;         /*!< (@ 0x00000008) C-Cache Line Configuration Register                        */
+
+        struct
+        {
+            __IOM uint32_t CC : 2;     /*!< [1..0] C-Cache Line Size                                                  */
+            uint32_t          : 30;
+        } CCALCF_b;
+    };
+    __IM uint32_t RESERVED[13];
+
+    union
+    {
+        __IOM uint32_t SCACTL;         /*!< (@ 0x00000040) S-Cache Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ENS : 1;    /*!< [0..0] S-Cache Enable                                                     */
+            uint32_t           : 31;
+        } SCACTL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SCAFCT;         /*!< (@ 0x00000044) S-Cache Flush Control Register                             */
+
+        struct
+        {
+            __IOM uint32_t FS : 1;     /*!< [0..0] S-Cache Flush                                                      */
+            uint32_t          : 31;
+        } SCAFCT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SCALCF;         /*!< (@ 0x00000048) S-Cache Line Configuration Register                        */
+
+        struct
+        {
+            __IOM uint32_t CS : 2;     /*!< [1..0] S-Cache Line Size                                                  */
+            uint32_t          : 30;
+        } SCALCF_b;
+    };
+    __IM uint32_t RESERVED1[109];
+
+    union
+    {
+        __IOM uint32_t CAPOAD;         /*!< (@ 0x00000200) Cache Parity Error Operation After Detection
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t OAD : 1;    /*!< [0..0] Operation after Detection                                          */
+            uint32_t           : 31;
+        } CAPOAD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CAPRCR;         /*!< (@ 0x00000204) Cache Protection Register                                  */
+
+        struct
+        {
+            __IOM uint32_t PRCR : 1;   /*!< [0..0] Register Write Control                                             */
+            __IOM uint32_t KW   : 7;   /*!< [7..1] Write key code                                                     */
+            uint32_t            : 24;
+        } CAPRCR_b;
+    };
+} R_CACHE_Type;                        /*!< Size = 520 (0x208)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CPSCU                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief CPU System Security Control Unit (R_CPSCU)
+ */
+
+typedef struct                           /*!< (@ 0x40008000) R_CPSCU Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t CSAR;             /*!< (@ 0x00000000) Cache Security Attribution Register                        */
+
+        struct
+        {
+            __IOM uint32_t CACHESA  : 1; /*!< [0..0] Security Attributes of Registers for Cache Control                 */
+            __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration      */
+            __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error                   */
+            uint32_t                : 29;
+        } CSAR_b;
+    };
+    __IM uint32_t RESERVED[3];
+
+    union
+    {
+        __IOM uint32_t SRAMSAR;         /*!< (@ 0x00000010) SRAM Security Attribution Register                         */
+
+        struct
+        {
+            __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection               */
+            __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection
+                                         *   2                                                                         */
+            __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation                  */
+            uint32_t               : 29;
+        } SRAMSAR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STBRAMSAR;       /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register           */
+
+        struct
+        {
+            __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM                 */
+            uint32_t               : 28;
+        } STBRAMSAR_b;
+    };
+    __IM uint32_t RESERVED1[6];
+
+    union
+    {
+        __IOM uint32_t DTCSAR;          /*!< (@ 0x00000030) DTC Controller Security Attribution Register               */
+
+        struct
+        {
+            __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution                                           */
+            uint32_t               : 31;
+        } DTCSAR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DMACSAR;         /*!< (@ 0x00000034) DMAC Controller Security Attribution Register              */
+
+        struct
+        {
+            __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution                                         */
+            uint32_t               : 31;
+        } DMACSAR_b;
+    };
+    __IM uint32_t RESERVED2[2];
+
+    union
+    {
+        __IOM uint32_t ICUSARA;           /*!< (@ 0x00000040) ICU Security Attribution Register A                        */
+
+        struct
+        {
+            __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers         */
+            uint32_t                : 16;
+        } ICUSARA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ICUSARB;        /*!< (@ 0x00000044) ICU Security Attribution Register B                        */
+
+        struct
+        {
+            __IOM uint32_t SANMI : 1;  /*!< [0..0] Security Attributes of nonmaskable interrupt                       */
+            uint32_t             : 31;
+        } ICUSARB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ICUSARC;         /*!< (@ 0x00000048) ICU Security Attribution Register C                        */
+
+        struct
+        {
+            __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel                  */
+            uint32_t               : 24;
+        } ICUSARC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ICUSARD;          /*!< (@ 0x0000004C) ICU Security Attribution Register D                        */
+
+        struct
+        {
+            __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0                        */
+            uint32_t                : 31;
+        } ICUSARD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ICUSARE;        /*!< (@ 0x00000050) ICU Security Attribution Register E                        */
+
+        struct
+        {
+            uint32_t                   : 16;
+            __IOM uint32_t SAIWDTWUP   : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16                 */
+            uint32_t                   : 1;
+            __IOM uint32_t SALVD1WUP   : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18                 */
+            __IOM uint32_t SALVD2WUP   : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19                 */
+            __IOM uint32_t SAVBATTWUP  : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20                 */
+            uint32_t                   : 3;
+            __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24                 */
+            __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25                 */
+            uint32_t                   : 1;
+            __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27                 */
+            __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28                 */
+            __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29                 */
+            __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30                 */
+            __IOM uint32_t SAIIC0WUP   : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31                 */
+        } ICUSARE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ICUSARF;              /*!< (@ 0x00000054) ICU Security Attribution Register F                        */
+
+        struct
+        {
+            __IOM uint32_t SAAGT3UDWUP  : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0                    */
+            __IOM uint32_t SAAGT3CAWUP  : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1                    */
+            __IOM uint32_t SAAGT3CBWUP  : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2                    */
+            __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3                    */
+            uint32_t                    : 4;
+            __IOM uint32_t SAULP0UWUP   : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8                    */
+            __IOM uint32_t SAULP0AWUP   : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9                    */
+            __IOM uint32_t SAULP0BWUP   : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10                 */
+            __IOM uint32_t SAI3CWUP     : 1; /*!< [11..11] Security Attributes of registers for WUPEN1.b 11                 */
+            __IOM uint32_t SAULP1UWUP   : 1; /*!< [12..12] Security Attributes of registers for WUPEN1.b 12                 */
+            __IOM uint32_t SAULP1AWUP   : 1; /*!< [13..13] Security Attributes of registers for WUPEN1.b 13                 */
+            __IOM uint32_t SAULP1BWUP   : 1; /*!< [14..14] Security Attributes of registers for WUPEN1.b 14                 */
+            uint32_t                    : 17;
+        } ICUSARF_b;
+    };
+    __IM uint32_t RESERVED3[6];
+
+    union
+    {
+        __IOM uint32_t ICUSARG;           /*!< (@ 0x00000070) ICU Security Attribution Register G                        */
+
+        struct
+        {
+            __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0            */
+        } ICUSARG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ICUSARH;           /*!< (@ 0x00000074) ICU Security Attribution Register H                        */
+
+        struct
+        {
+            __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32           */
+        } ICUSARH_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ICUSARI;           /*!< (@ 0x00000078) ICU Security Attribution Register I                        */
+
+        struct
+        {
+            __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64           */
+        } ICUSARI_b;
+    };
+    __IM uint32_t RESERVED4[33];
+
+    union
+    {
+        __IOM uint32_t BUSSARA;        /*!< (@ 0x00000100) Bus Security Attribution Register A                        */
+
+        struct
+        {
+            __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0                                        */
+            uint32_t              : 31;
+        } BUSSARA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BUSSARB;        /*!< (@ 0x00000104) Bus Security Attribution Register B                        */
+
+        struct
+        {
+            __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0                                        */
+            uint32_t              : 31;
+        } BUSSARB_b;
+    };
+    __IM uint32_t RESERVED5[10];
+
+    union
+    {
+        __IOM uint32_t MMPUSARA;         /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution
+                                          *                  Register A                                                 */
+
+        struct
+        {
+            __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7)                           */
+            uint32_t                : 24;
+        } MMPUSARA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMPUSARB;         /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution
+                                          *                  Register B                                                 */
+
+        struct
+        {
+            __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution                                        */
+            uint32_t                : 31;
+        } MMPUSARB_b;
+    };
+    __IM uint32_t RESERVED6[26];
+
+    union
+    {
+        __IOM uint32_t DMASARA;          /*!< (@ 0x000001A0) ICU Security Attribution Register C                        */
+
+        struct
+        {
+            __IOM uint32_t DMASARAn : 8; /*!< [7..0] Security attributes of output and registers for DMAC
+                                          *   channel                                                                   */
+            uint32_t : 24;
+        } DMASARA_b;
+    };
+    __IM uint32_t RESERVED7[3];
+
+    union
+    {
+        __IOM uint32_t CPUDSAR;         /*!< (@ 0x000001B0) CPU Debug Security Attribution Register                    */
+
+        struct
+        {
+            __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0                                   */
+            uint32_t               : 31;
+        } CPUDSAR_b;
+    };
+    __IM uint32_t RESERVED8[275];
+
+    union
+    {
+        __IOM uint32_t TEVTRCR;        /*!< (@ 0x00000600) Trusted Event Route Control Register                       */
+
+        struct
+        {
+            __IOM uint32_t TEVTE : 1;  /*!< [0..0] Trusted Event Route Control Register for IELSRn, DELSRn
+                                        *   and ELCSRn                                                                */
+            uint32_t : 31;
+        } TEVTRCR_b;
+    };
+} R_CPSCU_Type;                        /*!< Size = 1540 (0x604)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                           R_CEC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Consumer Electronics Control (R_CEC)
+ */
+
+typedef struct                         /*!< (@ 0x400AC000) R_CEC Structure                                            */
+{
+    union
+    {
+        __IOM uint16_t CADR;           /*!< (@ 0x00000000) CEC Local Address Setting Register                         */
+
+        struct
+        {
+            __IOM uint16_t ADR00 : 1;  /*!< [0..0] Local Address at Address 0 (TV)                                    */
+            __IOM uint16_t ADR01 : 1;  /*!< [1..1] Local Address Setting at Address 1 (recording device
+                                        *   1)                                                                        */
+            __IOM uint16_t ADR02 : 1;  /*!< [2..2] Local Address Setting at Address 2 (recording device
+                                        *   2)                                                                        */
+            __IOM uint16_t ADR03 : 1;  /*!< [3..3] Local Address Setting at Address 3 (tuner 1)                       */
+            __IOM uint16_t ADR04 : 1;  /*!< [4..4] Local Address Setting at Address 4 (playback device 1)             */
+            __IOM uint16_t ADR05 : 1;  /*!< [5..5] Local Address Setting at Address 5 (audio system)                  */
+            __IOM uint16_t ADR06 : 1;  /*!< [6..6] Local Address Setting at Address 6 (tuner 2)                       */
+            __IOM uint16_t ADR07 : 1;  /*!< [7..7] Local Address Setting at Address 7 (tuner 3)                       */
+            __IOM uint16_t ADR08 : 1;  /*!< [8..8] Local Address Setting at Address 8 (playback device 2)             */
+            __IOM uint16_t ADR09 : 1;  /*!< [9..9] Local Address Setting at Address 9 (recording device
+                                        *   3)                                                                        */
+            __IOM uint16_t ADR10 : 1;  /*!< [10..10] Local Address Setting at Address 10 (tuner 4)                    */
+            __IOM uint16_t ADR11 : 1;  /*!< [11..11] Local Address Setting at Address 11 (playback device
+                                        *   3)                                                                        */
+            __IOM uint16_t ADR12 : 1;  /*!< [12..12] Local Address Setting at Address 12 (reserved)                   */
+            __IOM uint16_t ADR13 : 1;  /*!< [13..13] Local Address Setting at Address 13 (reserved)                   */
+            __IOM uint16_t ADR14 : 1;  /*!< [14..14] Local Address Setting at Address 14 (specific use)               */
+            uint16_t             : 1;
+        } CADR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CECCTL1;         /*!< (@ 0x00000002) CEC Control Register 1                                     */
+
+        struct
+        {
+            __IOM uint8_t SFT   : 2;   /*!< [1..0] Signal-Free Time Data Bit Width Select                             */
+            __IOM uint8_t CESEL : 2;   /*!< [3..2] Communication Complete Interrupt (INTCE) Generation Timing
+                                        *   Select                                                                    */
+            __IOM uint8_t STERRD : 1;  /*!< [4..4] Start Bit Error Detection Select                                   */
+            __IOM uint8_t BLERRD : 1;  /*!< [5..5] Bus Lock Detection Select                                          */
+            __IOM uint8_t CINTMK : 1;  /*!< [6..6] CEC Data Interrupt (INTDA) Generation Select                       */
+            __IOM uint8_t CDFC   : 1;  /*!< [7..7] Digital Filter Select                                              */
+        } CECCTL1_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t STATB;          /*!< (@ 0x00000004) CEC Transmission Start Bit Width Setting Register          */
+
+        struct
+        {
+            __IOM uint16_t STATB : 9;  /*!< [8..0] CEC Transmission Start Bit Width Setting                           */
+            uint16_t             : 7;
+        } STATB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t STATL;          /*!< (@ 0x00000006) CEC Transmission Start Bit Low Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t STATL : 9;  /*!< [8..0] CEC Transmission Start Bit Low Width Setting                       */
+            uint16_t             : 7;
+        } STATL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t LGC0L;          /*!< (@ 0x00000008) CEC Transmission Logical 0 Low Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t LGC0L : 9;  /*!< [8..0] CEC Transmission Logical 0 Low Width Setting                       */
+            uint16_t             : 7;
+        } LGC0L_b;
+    };
+
+    union
+    {
+        __IOM uint16_t LGC1L;          /*!< (@ 0x0000000A) CEC Transmission Logical 1 Low Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t LGC1L : 9;  /*!< [8..0] CEC Transmission Logical 1 Low Width Setting                       */
+            uint16_t             : 7;
+        } LGC1L_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DATB;           /*!< (@ 0x0000000C) CEC Transmission Data Bit Width Setting Register           */
+
+        struct
+        {
+            __IOM uint16_t DATB : 9;   /*!< [8..0] CEC Transmission Data Bit Width Setting                            */
+            uint16_t            : 7;
+        } DATB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t NOMT;           /*!< (@ 0x0000000E) CEC Reception Data Sampling Time Setting Register          */
+
+        struct
+        {
+            __IOM uint16_t NOMT : 9;   /*!< [8..0] CEC Reception Data Sampling Time Setting,                          */
+            uint16_t            : 7;
+        } NOMT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t STATLL;         /*!< (@ 0x00000010) CEC Reception Start Bit Minimum Low Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t STATLL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Low Width Setting                  */
+            uint16_t              : 7;
+        } STATLL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t STATLH;         /*!< (@ 0x00000012) CEC Reception Start Bit Maximum Low Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t STATLH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting                  */
+            uint16_t              : 7;
+        } STATLH_b;
+    };
+
+    union
+    {
+        __IOM uint16_t STATBL;         /*!< (@ 0x00000014) CEC Reception Start Bit Minimum Bit Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t STATBL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Bit Width Setting                  */
+            uint16_t              : 7;
+        } STATBL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t STATBH;         /*!< (@ 0x00000016) CEC Reception Start Bit Maximum Bit Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t STATBH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting                  */
+            uint16_t              : 7;
+        } STATBH_b;
+    };
+
+    union
+    {
+        __IOM uint16_t LGC0LL;         /*!< (@ 0x00000018) CEC Reception Logical 0 Minimum Low Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t LGC0LL : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting                  */
+            uint16_t              : 7;
+        } LGC0LL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t LGC0LH;         /*!< (@ 0x0000001A) CEC Reception Logical 0 Maximum Low Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t LGC0LH : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting                  */
+            uint16_t              : 7;
+        } LGC0LH_b;
+    };
+
+    union
+    {
+        __IOM uint16_t LGC1LL;         /*!< (@ 0x0000001C) CEC Reception Logical 1 Minimum Low Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t LGC1LL : 9; /*!< [8..0] CEC Reception Logical 1 Minimum Low Width Setting                  */
+            uint16_t              : 7;
+        } LGC1LL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t LGC1LH;         /*!< (@ 0x0000001E) CEC Reception Logical 1 Maximum Low Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t LGC1LH : 9; /*!< [8..0] CEC Reception Logical 1 Maximum Low Width Setting                  */
+            uint16_t              : 7;
+        } LGC1LH_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DATBL;          /*!< (@ 0x00000020) CEC Reception Data Bit Minimum Bit Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t DATBL : 9;  /*!< [8..0] CEC Reception Data Bit Minimum Bit Width Setting                   */
+            uint16_t             : 7;
+        } DATBL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DATBH;          /*!< (@ 0x00000022) CEC Reception Data Bit Maximum Bit Width Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t DATBH : 9;  /*!< [8..0] CEC Reception Data Bit Maximum Bit Width Setting                   */
+            uint16_t             : 7;
+        } DATBH_b;
+    };
+
+    union
+    {
+        __IOM uint16_t NOMP;           /*!< (@ 0x00000024) CEC Data Bit Reference Width Setting Register              */
+
+        struct
+        {
+            __IOM uint16_t NOMP : 9;   /*!< [8..0] CEC Data Bit Reference Width Setting                               */
+            uint16_t            : 7;
+        } NOMP_b;
+    };
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint8_t CECEXMD;         /*!< (@ 0x00000028) CEC Extension Mode Register                                */
+
+        struct
+        {
+            uint8_t                  : 4;
+            __IOM uint8_t LERPLEN    : 1; /*!< [4..4] Pulse Output Function Enable by Long Bit Width Error               */
+            __IOM uint8_t RERCVEN    : 1; /*!< [5..5] Start Detection Reception Restart Enable                           */
+            uint8_t                  : 1;
+            __IOM uint8_t RCVINTDSEL : 1; /*!< [7..7] INTDA Reception Interrupt Timing Change                            */
+        } CECEXMD_b;
+    };
+    __IM uint8_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t CECEXMON;        /*!< (@ 0x0000002A) CEC Extension Monitor Register                             */
+
+        struct
+        {
+            __IM uint8_t CECLNMON : 1; /*!< [0..0] CEC Line Monitor                                                   */
+            __IM uint8_t ACKF     : 1; /*!< [1..1] ACK Flag                                                           */
+            uint8_t               : 6;
+        } CECEXMON_b;
+    };
+    __IM uint8_t  RESERVED3;
+    __IM uint16_t RESERVED4[10];
+    __IOM uint8_t CTXD;                /*!< (@ 0x00000040) CEC Transmission Buffer Register                           */
+    __IOM uint8_t CRXD;                /*!< (@ 0x00000041) CEC Reception Buffer Register                              */
+
+    union
+    {
+        __IOM uint8_t CECES;           /*!< (@ 0x00000042) CEC Communication Error Status Register                    */
+
+        struct
+        {
+            __IM uint8_t OERR   : 1;   /*!< [0..0] Overrun Error Detection Flag                                       */
+            __IM uint8_t UERR   : 1;   /*!< [1..1] Underrun Error Detection Flag                                      */
+            __IM uint8_t ACKERR : 1;   /*!< [2..2] ACK Error Detection Flag                                           */
+            __IM uint8_t TERR   : 1;   /*!< [3..3] Timing Error Detection Flag                                        */
+            __IM uint8_t TXERR  : 1;   /*!< [4..4] Transmission Error Detection Flag                                  */
+            __IM uint8_t AERR   : 1;   /*!< [5..5] Arbitration Loss Detection Flag                                    */
+            __IM uint8_t BLERR  : 1;   /*!< [6..6] Bus Lock Error Detection Flag                                      */
+            uint8_t             : 1;
+        } CECES_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CECS;            /*!< (@ 0x00000043) CEC Communication Status Register                          */
+
+        struct
+        {
+            __IM uint8_t ADRF  : 1;    /*!< [0..0] Address Match Detection Flag                                       */
+            __IM uint8_t BUSST : 1;    /*!< [1..1] Bus Busy Detection Flag                                            */
+            __IM uint8_t TXST  : 1;    /*!< [2..2] Transmission Status Flag                                           */
+            __IM uint8_t EOMF  : 1;    /*!< [3..3] EOM Flag                                                           */
+            __IM uint8_t ITCEF : 1;    /*!< [4..4] INTCE Generation Source Flag                                       */
+            uint8_t            : 2;
+            __IM uint8_t SFTST : 1;    /*!< [7..7] Signal-Free Time Rewrite Disable Report Flag                       */
+        } CECS_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CECFC;           /*!< (@ 0x00000044) CEC Communication Error Flag Clear Trigger Register        */
+
+        struct
+        {
+            __OM uint8_t OCTRG   : 1;  /*!< [0..0] Overrun Error Detection Flag Clear Trigger                         */
+            __OM uint8_t UCTRG   : 1;  /*!< [1..1] Underrun Error Detection Flag Clear Trigger                        */
+            __OM uint8_t ACKCTRG : 1;  /*!< [2..2] ACK Error Detection Flag Clear Trigger                             */
+            __OM uint8_t TCTRG   : 1;  /*!< [3..3] Timing Error Detection Flag Clear Trigger                          */
+            __OM uint8_t TXCTRG  : 1;  /*!< [4..4] Transmission Error Detection Flag Clear Trigger                    */
+            __OM uint8_t ACTRG   : 1;  /*!< [5..5] Arbitration Loss Detection Flag Clear Trigger                      */
+            __OM uint8_t BLCTRG  : 1;  /*!< [6..6] Bus Lock Error Detection Flag Clear Trigger                        */
+            uint8_t              : 1;
+        } CECFC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CECCTL0;         /*!< (@ 0x00000045) CEC Control Register 0                                     */
+
+        struct
+        {
+            __IOM uint8_t EOM     : 1; /*!< [0..0] EOM Setting                                                        */
+            __IOM uint8_t CECRXEN : 1; /*!< [1..1] Reception Enable Control                                           */
+            __OM uint8_t  TXTRG   : 1; /*!< [2..2] Transmission Start Trigger                                         */
+            __IOM uint8_t CCL     : 3; /*!< [5..3] CEC Clock (CECCLK) Select                                          */
+            __IOM uint8_t ACKTEN  : 1; /*!< [6..6] ACK Bit Timing Error (Bit Width) Check Enable                      */
+            __IOM uint8_t CECE    : 1; /*!< [7..7] CEC Operation Enable Flag                                          */
+        } CECCTL0_b;
+    };
+} R_CEC_Type;                          /*!< Size = 70 (0x46)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
+ */
+
+typedef struct                          /*!< (@ 0x400E8000) R_AGTX0 Structure                                          */
+{
+    union
+    {
+        __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
+        __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
+    };
+} R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_FLAD                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Data Flash (R_FLAD)
+ */
+
+typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure                                           */
+{
+    __IM uint8_t RESERVED[64];
+
+    union
+    {
+        __IOM uint8_t FCKMHZ;          /*!< (@ 0x00000040) Data Flash Access Frequency Register                       */
+
+        struct
+        {
+            __IOM uint8_t FCKMHZ : 8;  /*!< [7..0] Data Flash Access Frequency Register                               */
+        } FCKMHZ_b;
+    };
+} R_FLAD_Type;                         /*!< Size = 65 (0x41)                                                          */
+
+/** @} */ /* End of group Device_Peripheral_peripherals */
+
+/* =========================================================================================================================== */
+/* ================                          Device Specific Peripheral Address Map                           ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_peripheralAddr
+ * @{
+ */
+
+ #define R_ADC0_BASE           0x40170000UL
+ #define R_ADC1_BASE           0x40170200UL
+ #define R_PSCU_BASE           0x400E0000UL
+ #define R_BUS_BASE            0x40003000UL
+ #define R_CAC_BASE            0x40083600UL
+ #define R_CANFD_BASE          0x400B0000UL
+ #define R_CANFD1_BASE         0x400B2000UL
+ #define R_CRC_BASE            0x40108000UL
+ #define R_DAC_BASE            0x40171000UL
+ #define R_DEBUG_BASE          0x4001B000UL
+ #define R_DMA_BASE            0x40005200UL
+ #define R_DMAC0_BASE          0x40005000UL
+ #define R_DMAC1_BASE          0x40005040UL
+ #define R_DMAC2_BASE          0x40005080UL
+ #define R_DMAC3_BASE          0x400050C0UL
+ #define R_DMAC4_BASE          0x40005100UL
+ #define R_DMAC5_BASE          0x40005140UL
+ #define R_DMAC6_BASE          0x40005180UL
+ #define R_DMAC7_BASE          0x400051C0UL
+ #define R_DOC_BASE            0x40109000UL
+ #define R_DTC_BASE            0x40005400UL
+ #define R_ELC_BASE            0x40082000UL
+ #define R_FACI_HP_CMD_BASE    0x407E0000UL
+ #define R_FACI_HP_BASE        0x407FE000UL
+ #define R_FCACHE_BASE         0x4001C000UL
+ #define R_GPT0_BASE           0x40169000UL
+ #define R_GPT1_BASE           0x40169100UL
+ #define R_GPT2_BASE           0x40169200UL
+ #define R_GPT3_BASE           0x40169300UL
+ #define R_GPT4_BASE           0x40169400UL
+ #define R_GPT5_BASE           0x40169500UL
+ #define R_GPT6_BASE           0x40169600UL
+ #define R_GPT7_BASE           0x40169700UL
+ #define R_GPT8_BASE           0x40169800UL
+ #define R_GPT9_BASE           0x40169900UL
+ #define R_GPT10_BASE          0x40169A00UL
+ #define R_GPT11_BASE          0x40169B00UL
+ #define R_GPT12_BASE          0x40169C00UL
+ #define R_GPT13_BASE          0x40169D00UL
+ #define R_GPT_OPS_BASE        0x40169A00UL
+ #define R_GPT_POEG0_BASE      0x4008A000UL
+ #define R_GPT_POEG1_BASE      0x4008A100UL
+ #define R_GPT_POEG2_BASE      0x4008A200UL
+ #define R_GPT_POEG3_BASE      0x4008A300UL
+ #define R_ICU_BASE            0x40006000UL
+ #define R_IIC0_BASE           0x4009F000UL
+ #define R_IIC1_BASE           0x4009F100UL
+ #define R_IIC2_BASE           0x4009F200UL
+ #define R_IWDT_BASE           0x40083200UL
+ #define R_I3C0_BASE           0x4011F000UL
+ #define R_I3C1_BASE           0x4011F400UL
+ #define R_MPU_SPMON_BASE      0x40000D00UL
+ #define R_MSTP_BASE           0x40084000UL
+ #define R_PORT0_BASE          0x40080000UL
+ #define R_PORT1_BASE          0x40080020UL
+ #define R_PORT2_BASE          0x40080040UL
+ #define R_PORT3_BASE          0x40080060UL
+ #define R_PORT4_BASE          0x40080080UL
+ #define R_PORT5_BASE          0x400800A0UL
+ #define R_PORT6_BASE          0x400800C0UL
+ #define R_PORT7_BASE          0x400800E0UL
+ #define R_PORT8_BASE          0x40080100UL
+ #define R_PORT9_BASE          0x40080120UL
+ #define R_PORT10_BASE         0x40080140UL
+ #define R_PORT11_BASE         0x40080160UL
+ #define R_PORT12_BASE         0x40080180UL
+ #define R_PORT13_BASE         0x400801A0UL
+ #define R_PORT14_BASE         0x400801C0UL
+ #define R_PFS_BASE            0x40080800UL
+ #define R_PMISC_BASE          0x40080D00UL
+ #define R_QSPI_BASE           0x64000000UL
+ #define R_RTC_BASE            0x40083000UL
+ #define R_SCI0_BASE           0x40118000UL
+ #define R_SCI1_BASE           0x40118100UL
+ #define R_SCI2_BASE           0x40118200UL
+ #define R_SCI3_BASE           0x40118300UL
+ #define R_SCI4_BASE           0x40118400UL
+ #define R_SCI5_BASE           0x40118500UL
+ #define R_SCI6_BASE           0x40118600UL
+ #define R_SCI7_BASE           0x40118700UL
+ #define R_SCI8_BASE           0x40118800UL
+ #define R_SCI9_BASE           0x40118900UL
+ #define R_SPI0_BASE           0x4011A000UL
+ #define R_SPI1_BASE           0x4011A100UL
+ #define R_SRAM_BASE           0x40002000UL
+ #define R_SSI0_BASE           0x4009D000UL
+ #define R_SSI1_BASE           0x4009D100UL
+ #define R_SYSTEM_BASE         0x4001E000UL
+ #define R_TSN_CAL_BASE        0x407FB17CUL
+ #define R_TSN_CTRL_BASE       0x400F3000UL
+ #define R_USB_FS0_BASE        0x40090000UL
+ #define R_WDT_BASE            0x40083400UL
+ #define R_TZF_BASE            0x40000E00UL
+ #define R_CACHE_BASE          0x40007000UL
+ #define R_CPSCU_BASE          0x40008000UL
+ #define R_CEC_BASE            0x400AC000UL
+ #define R_AGTX0_BASE          0x400E8000UL
+ #define R_AGTX1_BASE          0x400E8100UL
+ #define R_AGTX2_BASE          0x400E8200UL
+ #define R_AGTX3_BASE          0x400E8300UL
+ #define R_AGTX4_BASE          0x400E8400UL
+ #define R_AGTX5_BASE          0x400E8500UL
+ #define R_AGTX6_BASE          0x400E8600UL
+ #define R_AGTX7_BASE          0x400E8700UL
+ #define R_AGTX8_BASE          0x400E8800UL
+ #define R_AGTX9_BASE          0x400E8900UL
+ #define R_FLAD_BASE           0x407FC000UL
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+/* =========================================================================================================================== */
+/* ================                                  Peripheral declaration                                   ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_declaration
+ * @{
+ */
+
+ #define R_ADC0           ((R_ADC0_Type *) R_ADC0_BASE)
+ #define R_ADC1           ((R_ADC0_Type *) R_ADC1_BASE)
+ #define R_PSCU           ((R_PSCU_Type *) R_PSCU_BASE)
+ #define R_BUS            ((R_BUS_Type *) R_BUS_BASE)
+ #define R_CAC            ((R_CAC_Type *) R_CAC_BASE)
+ #define R_CANFD          ((R_CANFD_Type *) R_CANFD_BASE)
+ #define R_CANFD0         ((R_CANFD_Type *) R_CANFD_BASE)
+ #define R_CANFD1         ((R_CANFD_Type *) R_CANFD1_BASE)
+ #define R_CRC            ((R_CRC_Type *) R_CRC_BASE)
+ #define R_DAC            ((R_DAC_Type *) R_DAC_BASE)
+ #define R_DEBUG          ((R_DEBUG_Type *) R_DEBUG_BASE)
+ #define R_DMA            ((R_DMA_Type *) R_DMA_BASE)
+ #define R_DMAC0          ((R_DMAC0_Type *) R_DMAC0_BASE)
+ #define R_DMAC1          ((R_DMAC0_Type *) R_DMAC1_BASE)
+ #define R_DMAC2          ((R_DMAC0_Type *) R_DMAC2_BASE)
+ #define R_DMAC3          ((R_DMAC0_Type *) R_DMAC3_BASE)
+ #define R_DMAC4          ((R_DMAC0_Type *) R_DMAC4_BASE)
+ #define R_DMAC5          ((R_DMAC0_Type *) R_DMAC5_BASE)
+ #define R_DMAC6          ((R_DMAC0_Type *) R_DMAC6_BASE)
+ #define R_DMAC7          ((R_DMAC0_Type *) R_DMAC7_BASE)
+ #define R_DOC            ((R_DOC_Type *) R_DOC_BASE)
+ #define R_DTC            ((R_DTC_Type *) R_DTC_BASE)
+ #define R_ELC            ((R_ELC_Type *) R_ELC_BASE)
+ #define R_FACI_HP_CMD    ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
+ #define R_FACI_HP        ((R_FACI_HP_Type *) R_FACI_HP_BASE)
+ #define R_FCACHE         ((R_FCACHE_Type *) R_FCACHE_BASE)
+ #define R_GPT0           ((R_GPT0_Type *) R_GPT0_BASE)
+ #define R_GPT1           ((R_GPT0_Type *) R_GPT1_BASE)
+ #define R_GPT2           ((R_GPT0_Type *) R_GPT2_BASE)
+ #define R_GPT3           ((R_GPT0_Type *) R_GPT3_BASE)
+ #define R_GPT4           ((R_GPT0_Type *) R_GPT4_BASE)
+ #define R_GPT5           ((R_GPT0_Type *) R_GPT5_BASE)
+ #define R_GPT6           ((R_GPT0_Type *) R_GPT6_BASE)
+ #define R_GPT7           ((R_GPT0_Type *) R_GPT7_BASE)
+ #define R_GPT8           ((R_GPT0_Type *) R_GPT8_BASE)
+ #define R_GPT9           ((R_GPT0_Type *) R_GPT9_BASE)
+ #define R_GPT10          ((R_GPT0_Type *) R_GPT10_BASE)
+ #define R_GPT11          ((R_GPT0_Type *) R_GPT11_BASE)
+ #define R_GPT12          ((R_GPT0_Type *) R_GPT12_BASE)
+ #define R_GPT13          ((R_GPT0_Type *) R_GPT13_BASE)
+ #define R_GPT_OPS        ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
+ #define R_GPT_POEG0      ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
+ #define R_GPT_POEG1      ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
+ #define R_GPT_POEG2      ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
+ #define R_GPT_POEG3      ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
+ #define R_ICU            ((R_ICU_Type *) R_ICU_BASE)
+ #define R_IIC0           ((R_IIC0_Type *) R_IIC0_BASE)
+ #define R_IIC1           ((R_IIC0_Type *) R_IIC1_BASE)
+ #define R_IIC2           ((R_IIC0_Type *) R_IIC2_BASE)
+ #define R_IWDT           ((R_IWDT_Type *) R_IWDT_BASE)
+ #define R_I3C0           ((R_I3C0_Type *) R_I3C0_BASE)
+ #define R_I3C1           ((R_I3C0_Type *) R_I3C1_BASE)
+ #define R_MPU_SPMON      ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE)
+ #define R_MSTP           ((R_MSTP_Type *) R_MSTP_BASE)
+ #define R_PORT0          ((R_PORT0_Type *) R_PORT0_BASE)
+ #define R_PORT1          ((R_PORT0_Type *) R_PORT1_BASE)
+ #define R_PORT2          ((R_PORT0_Type *) R_PORT2_BASE)
+ #define R_PORT3          ((R_PORT0_Type *) R_PORT3_BASE)
+ #define R_PORT4          ((R_PORT0_Type *) R_PORT4_BASE)
+ #define R_PORT5          ((R_PORT0_Type *) R_PORT5_BASE)
+ #define R_PORT6          ((R_PORT0_Type *) R_PORT6_BASE)
+ #define R_PORT7          ((R_PORT0_Type *) R_PORT7_BASE)
+ #define R_PORT8          ((R_PORT0_Type *) R_PORT8_BASE)
+ #define R_PORT9          ((R_PORT0_Type *) R_PORT9_BASE)
+ #define R_PORT10         ((R_PORT0_Type *) R_PORT10_BASE)
+ #define R_PORT11         ((R_PORT0_Type *) R_PORT11_BASE)
+ #define R_PORT12         ((R_PORT0_Type *) R_PORT12_BASE)
+ #define R_PORT13         ((R_PORT0_Type *) R_PORT13_BASE)
+ #define R_PORT14         ((R_PORT0_Type *) R_PORT14_BASE)
+ #define R_PFS            ((R_PFS_Type *) R_PFS_BASE)
+ #define R_PMISC          ((R_PMISC_Type *) R_PMISC_BASE)
+ #define R_QSPI           ((R_QSPI_Type *) R_QSPI_BASE)
+ #define R_RTC            ((R_RTC_Type *) R_RTC_BASE)
+ #define R_SCI0           ((R_SCI0_Type *) R_SCI0_BASE)
+ #define R_SCI1           ((R_SCI0_Type *) R_SCI1_BASE)
+ #define R_SCI2           ((R_SCI0_Type *) R_SCI2_BASE)
+ #define R_SCI3           ((R_SCI0_Type *) R_SCI3_BASE)
+ #define R_SCI4           ((R_SCI0_Type *) R_SCI4_BASE)
+ #define R_SCI5           ((R_SCI0_Type *) R_SCI5_BASE)
+ #define R_SCI6           ((R_SCI0_Type *) R_SCI6_BASE)
+ #define R_SCI7           ((R_SCI0_Type *) R_SCI7_BASE)
+ #define R_SCI8           ((R_SCI0_Type *) R_SCI8_BASE)
+ #define R_SCI9           ((R_SCI0_Type *) R_SCI9_BASE)
+ #define R_SPI0           ((R_SPI0_Type *) R_SPI0_BASE)
+ #define R_SPI1           ((R_SPI0_Type *) R_SPI1_BASE)
+ #define R_SRAM           ((R_SRAM_Type *) R_SRAM_BASE)
+ #define R_SSI0           ((R_SSI0_Type *) R_SSI0_BASE)
+ #define R_SSI1           ((R_SSI0_Type *) R_SSI1_BASE)
+ #define R_SYSTEM         ((R_SYSTEM_Type *) R_SYSTEM_BASE)
+ #define R_TSN_CAL        ((R_TSN_CAL_Type *) R_TSN_CAL_BASE)
+ #define R_TSN_CTRL       ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
+ #define R_USB_FS0        ((R_USB_FS0_Type *) R_USB_FS0_BASE)
+ #define R_WDT            ((R_WDT_Type *) R_WDT_BASE)
+ #define R_TZF            ((R_TZF_Type *) R_TZF_BASE)
+ #define R_CACHE          ((R_CACHE_Type *) R_CACHE_BASE)
+ #define R_CPSCU          ((R_CPSCU_Type *) R_CPSCU_BASE)
+ #define R_CEC            ((R_CEC_Type *) R_CEC_BASE)
+ #define R_AGTX0          ((R_AGTX0_Type *) R_AGTX0_BASE)
+ #define R_AGTX1          ((R_AGTX0_Type *) R_AGTX1_BASE)
+ #define R_AGTX2          ((R_AGTX0_Type *) R_AGTX2_BASE)
+ #define R_AGTX3          ((R_AGTX0_Type *) R_AGTX3_BASE)
+ #define R_AGTX4          ((R_AGTX0_Type *) R_AGTX4_BASE)
+ #define R_AGTX5          ((R_AGTX0_Type *) R_AGTX5_BASE)
+ #define R_AGTX6          ((R_AGTX0_Type *) R_AGTX6_BASE)
+ #define R_AGTX7          ((R_AGTX0_Type *) R_AGTX7_BASE)
+ #define R_AGTX8          ((R_AGTX0_Type *) R_AGTX8_BASE)
+ #define R_AGTX9          ((R_AGTX0_Type *) R_AGTX9_BASE)
+ #define R_FLAD           ((R_FLAD_Type *) R_FLAD_BASE)
+
+/** @} */ /* End of group Device_Peripheral_declaration */
+
+/* =========================================  End of section using anonymous unions  ========================================= */
+ #if defined(__CC_ARM)
+  #pragma pop
+ #elif defined(__ICCARM__)
+
+/* leave anonymous unions enabled */
+ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic pop
+ #elif defined(__GNUC__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TMS470__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TASKING__)
+  #pragma warning restore
+ #elif defined(__CSMC__)
+
+/* anonymous unions are enabled by default */
+ #endif
+
+/* =========================================================================================================================== */
+/* ================                                 Pos/Mask Cluster Section                                  ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup PosMask_clusters
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                            CSa                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  MOD  ========================================================== */
+ #define R_BUS_CSa_MOD_PRMOD_Pos        (15UL)         /*!< PRMOD (Bit 15)                                        */
+ #define R_BUS_CSa_MOD_PRMOD_Msk        (0x8000UL)     /*!< PRMOD (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_CSa_MOD_PWENB_Pos        (9UL)          /*!< PWENB (Bit 9)                                         */
+ #define R_BUS_CSa_MOD_PWENB_Msk        (0x200UL)      /*!< PWENB (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_CSa_MOD_PRENB_Pos        (8UL)          /*!< PRENB (Bit 8)                                         */
+ #define R_BUS_CSa_MOD_PRENB_Msk        (0x100UL)      /*!< PRENB (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_CSa_MOD_EWENB_Pos        (3UL)          /*!< EWENB (Bit 3)                                         */
+ #define R_BUS_CSa_MOD_EWENB_Msk        (0x8UL)        /*!< EWENB (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_CSa_MOD_WRMOD_Pos        (0UL)          /*!< WRMOD (Bit 0)                                         */
+ #define R_BUS_CSa_MOD_WRMOD_Msk        (0x1UL)        /*!< WRMOD (Bitfield-Mask: 0x01)                           */
+/* =========================================================  WCR1  ========================================================== */
+ #define R_BUS_CSa_WCR1_CSRWAIT_Pos     (24UL)         /*!< CSRWAIT (Bit 24)                                      */
+ #define R_BUS_CSa_WCR1_CSRWAIT_Msk     (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f)                         */
+ #define R_BUS_CSa_WCR1_CSWWAIT_Pos     (16UL)         /*!< CSWWAIT (Bit 16)                                      */
+ #define R_BUS_CSa_WCR1_CSWWAIT_Msk     (0x1f0000UL)   /*!< CSWWAIT (Bitfield-Mask: 0x1f)                         */
+ #define R_BUS_CSa_WCR1_CSPRWAIT_Pos    (8UL)          /*!< CSPRWAIT (Bit 8)                                      */
+ #define R_BUS_CSa_WCR1_CSPRWAIT_Msk    (0x700UL)      /*!< CSPRWAIT (Bitfield-Mask: 0x07)                        */
+ #define R_BUS_CSa_WCR1_CSPWWAIT_Pos    (0UL)          /*!< CSPWWAIT (Bit 0)                                      */
+ #define R_BUS_CSa_WCR1_CSPWWAIT_Msk    (0x7UL)        /*!< CSPWWAIT (Bitfield-Mask: 0x07)                        */
+/* =========================================================  WCR2  ========================================================== */
+ #define R_BUS_CSa_WCR2_CSON_Pos        (28UL)         /*!< CSON (Bit 28)                                         */
+ #define R_BUS_CSa_WCR2_CSON_Msk        (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07)                            */
+ #define R_BUS_CSa_WCR2_WDON_Pos        (24UL)         /*!< WDON (Bit 24)                                         */
+ #define R_BUS_CSa_WCR2_WDON_Msk        (0x7000000UL)  /*!< WDON (Bitfield-Mask: 0x07)                            */
+ #define R_BUS_CSa_WCR2_WRON_Pos        (20UL)         /*!< WRON (Bit 20)                                         */
+ #define R_BUS_CSa_WCR2_WRON_Msk        (0x700000UL)   /*!< WRON (Bitfield-Mask: 0x07)                            */
+ #define R_BUS_CSa_WCR2_RDON_Pos        (16UL)         /*!< RDON (Bit 16)                                         */
+ #define R_BUS_CSa_WCR2_RDON_Msk        (0x70000UL)    /*!< RDON (Bitfield-Mask: 0x07)                            */
+ #define R_BUS_CSa_WCR2_AWAIT_Pos       (12UL)         /*!< AWAIT (Bit 12)                                        */
+ #define R_BUS_CSa_WCR2_AWAIT_Msk       (0x3000UL)     /*!< AWAIT (Bitfield-Mask: 0x03)                           */
+ #define R_BUS_CSa_WCR2_WDOFF_Pos       (8UL)          /*!< WDOFF (Bit 8)                                         */
+ #define R_BUS_CSa_WCR2_WDOFF_Msk       (0x700UL)      /*!< WDOFF (Bitfield-Mask: 0x07)                           */
+ #define R_BUS_CSa_WCR2_CSWOFF_Pos      (4UL)          /*!< CSWOFF (Bit 4)                                        */
+ #define R_BUS_CSa_WCR2_CSWOFF_Msk      (0x70UL)       /*!< CSWOFF (Bitfield-Mask: 0x07)                          */
+ #define R_BUS_CSa_WCR2_CSROFF_Pos      (0UL)          /*!< CSROFF (Bit 0)                                        */
+ #define R_BUS_CSa_WCR2_CSROFF_Msk      (0x7UL)        /*!< CSROFF (Bitfield-Mask: 0x07)                          */
+
+/* =========================================================================================================================== */
+/* ================                                            CSb                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+ #define R_BUS_CSb_CR_MPXEN_Pos    (12UL)     /*!< MPXEN (Bit 12)                                        */
+ #define R_BUS_CSb_CR_MPXEN_Msk    (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_CSb_CR_EMODE_Pos    (8UL)      /*!< EMODE (Bit 8)                                         */
+ #define R_BUS_CSb_CR_EMODE_Msk    (0x100UL)  /*!< EMODE (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_CSb_CR_BSIZE_Pos    (4UL)      /*!< BSIZE (Bit 4)                                         */
+ #define R_BUS_CSb_CR_BSIZE_Msk    (0x30UL)   /*!< BSIZE (Bitfield-Mask: 0x03)                           */
+ #define R_BUS_CSb_CR_EXENB_Pos    (0UL)      /*!< EXENB (Bit 0)                                         */
+ #define R_BUS_CSb_CR_EXENB_Msk    (0x1UL)    /*!< EXENB (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  REC  ========================================================== */
+ #define R_BUS_CSb_REC_WRCV_Pos    (8UL)      /*!< WRCV (Bit 8)                                          */
+ #define R_BUS_CSb_REC_WRCV_Msk    (0xf00UL)  /*!< WRCV (Bitfield-Mask: 0x0f)                            */
+ #define R_BUS_CSb_REC_RRCV_Pos    (0UL)      /*!< RRCV (Bit 0)                                          */
+ #define R_BUS_CSb_REC_RRCV_Msk    (0xfUL)    /*!< RRCV (Bitfield-Mask: 0x0f)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           SDRAM                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SDCCR  ========================================================= */
+ #define R_BUS_SDRAM_SDCCR_BSIZE_Pos     (4UL)       /*!< BSIZE (Bit 4)                                         */
+ #define R_BUS_SDRAM_SDCCR_BSIZE_Msk     (0x30UL)    /*!< BSIZE (Bitfield-Mask: 0x03)                           */
+ #define R_BUS_SDRAM_SDCCR_EXENB_Pos     (0UL)       /*!< EXENB (Bit 0)                                         */
+ #define R_BUS_SDRAM_SDCCR_EXENB_Msk     (0x1UL)     /*!< EXENB (Bitfield-Mask: 0x01)                           */
+/* ========================================================  SDCMOD  ========================================================= */
+ #define R_BUS_SDRAM_SDCMOD_EMODE_Pos    (0UL)       /*!< EMODE (Bit 0)                                         */
+ #define R_BUS_SDRAM_SDCMOD_EMODE_Msk    (0x1UL)     /*!< EMODE (Bitfield-Mask: 0x01)                           */
+/* ========================================================  SDAMOD  ========================================================= */
+ #define R_BUS_SDRAM_SDAMOD_BE_Pos       (0UL)       /*!< BE (Bit 0)                                            */
+ #define R_BUS_SDRAM_SDAMOD_BE_Msk       (0x1UL)     /*!< BE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  SDSELF  ========================================================= */
+ #define R_BUS_SDRAM_SDSELF_SFEN_Pos     (0UL)       /*!< SFEN (Bit 0)                                          */
+ #define R_BUS_SDRAM_SDSELF_SFEN_Msk     (0x1UL)     /*!< SFEN (Bitfield-Mask: 0x01)                            */
+/* ========================================================  SDRFCR  ========================================================= */
+ #define R_BUS_SDRAM_SDRFCR_REFW_Pos     (12UL)      /*!< REFW (Bit 12)                                         */
+ #define R_BUS_SDRAM_SDRFCR_REFW_Msk     (0xf000UL)  /*!< REFW (Bitfield-Mask: 0x0f)                            */
+ #define R_BUS_SDRAM_SDRFCR_RFC_Pos      (0UL)       /*!< RFC (Bit 0)                                           */
+ #define R_BUS_SDRAM_SDRFCR_RFC_Msk      (0xfffUL)   /*!< RFC (Bitfield-Mask: 0xfff)                            */
+/* ========================================================  SDRFEN  ========================================================= */
+ #define R_BUS_SDRAM_SDRFEN_RFEN_Pos     (0UL)       /*!< RFEN (Bit 0)                                          */
+ #define R_BUS_SDRAM_SDRFEN_RFEN_Msk     (0x1UL)     /*!< RFEN (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SDICR  ========================================================= */
+ #define R_BUS_SDRAM_SDICR_INIRQ_Pos     (0UL)       /*!< INIRQ (Bit 0)                                         */
+ #define R_BUS_SDRAM_SDICR_INIRQ_Msk     (0x1UL)     /*!< INIRQ (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SDIR  ========================================================== */
+ #define R_BUS_SDRAM_SDIR_PRC_Pos        (8UL)       /*!< PRC (Bit 8)                                           */
+ #define R_BUS_SDRAM_SDIR_PRC_Msk        (0x700UL)   /*!< PRC (Bitfield-Mask: 0x07)                             */
+ #define R_BUS_SDRAM_SDIR_ARFC_Pos       (4UL)       /*!< ARFC (Bit 4)                                          */
+ #define R_BUS_SDRAM_SDIR_ARFC_Msk       (0xf0UL)    /*!< ARFC (Bitfield-Mask: 0x0f)                            */
+ #define R_BUS_SDRAM_SDIR_ARFI_Pos       (0UL)       /*!< ARFI (Bit 0)                                          */
+ #define R_BUS_SDRAM_SDIR_ARFI_Msk       (0xfUL)     /*!< ARFI (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  SDADR  ========================================================= */
+ #define R_BUS_SDRAM_SDADR_MXC_Pos       (0UL)       /*!< MXC (Bit 0)                                           */
+ #define R_BUS_SDRAM_SDADR_MXC_Msk       (0x3UL)     /*!< MXC (Bitfield-Mask: 0x03)                             */
+/* =========================================================  SDTR  ========================================================== */
+ #define R_BUS_SDRAM_SDTR_RAS_Pos        (16UL)      /*!< RAS (Bit 16)                                          */
+ #define R_BUS_SDRAM_SDTR_RAS_Msk        (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07)                             */
+ #define R_BUS_SDRAM_SDTR_RCD_Pos        (12UL)      /*!< RCD (Bit 12)                                          */
+ #define R_BUS_SDRAM_SDTR_RCD_Msk        (0x3000UL)  /*!< RCD (Bitfield-Mask: 0x03)                             */
+ #define R_BUS_SDRAM_SDTR_RP_Pos         (9UL)       /*!< RP (Bit 9)                                            */
+ #define R_BUS_SDRAM_SDTR_RP_Msk         (0xe00UL)   /*!< RP (Bitfield-Mask: 0x07)                              */
+ #define R_BUS_SDRAM_SDTR_WR_Pos         (8UL)       /*!< WR (Bit 8)                                            */
+ #define R_BUS_SDRAM_SDTR_WR_Msk         (0x100UL)   /*!< WR (Bitfield-Mask: 0x01)                              */
+ #define R_BUS_SDRAM_SDTR_CL_Pos         (0UL)       /*!< CL (Bit 0)                                            */
+ #define R_BUS_SDRAM_SDTR_CL_Msk         (0x7UL)     /*!< CL (Bitfield-Mask: 0x07)                              */
+/* =========================================================  SDMOD  ========================================================= */
+ #define R_BUS_SDRAM_SDMOD_MR_Pos        (0UL)       /*!< MR (Bit 0)                                            */
+ #define R_BUS_SDRAM_SDMOD_MR_Msk        (0x7fffUL)  /*!< MR (Bitfield-Mask: 0x7fff)                            */
+/* =========================================================  SDSR  ========================================================== */
+ #define R_BUS_SDRAM_SDSR_SRFST_Pos      (4UL)       /*!< SRFST (Bit 4)                                         */
+ #define R_BUS_SDRAM_SDSR_SRFST_Msk      (0x10UL)    /*!< SRFST (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_SDRAM_SDSR_INIST_Pos      (3UL)       /*!< INIST (Bit 3)                                         */
+ #define R_BUS_SDRAM_SDSR_INIST_Msk      (0x8UL)     /*!< INIST (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_SDRAM_SDSR_MRSST_Pos      (0UL)       /*!< MRSST (Bit 0)                                         */
+ #define R_BUS_SDRAM_SDSR_MRSST_Msk      (0x1UL)     /*!< MRSST (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                          BUSERR                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ADD  ========================================================== */
+ #define R_BUS_BUSERR_ADD_BERAD_Pos       (0UL)          /*!< BERAD (Bit 0)                                         */
+ #define R_BUS_BUSERR_ADD_BERAD_Msk       (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  STAT  ========================================================== */
+ #define R_BUS_BUSERR_STAT_ERRSTAT_Pos    (7UL)          /*!< ERRSTAT (Bit 7)                                       */
+ #define R_BUS_BUSERR_STAT_ERRSTAT_Msk    (0x80UL)       /*!< ERRSTAT (Bitfield-Mask: 0x01)                         */
+ #define R_BUS_BUSERR_STAT_ACCSTAT_Pos    (0UL)          /*!< ACCSTAT (Bit 0)                                       */
+ #define R_BUS_BUSERR_STAT_ACCSTAT_Msk    (0x1UL)        /*!< ACCSTAT (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                           BUSM                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CNT  ========================================================== */
+ #define R_BUS_BUSM_CNT_IERES_Pos    (15UL)     /*!< IERES (Bit 15)                                        */
+ #define R_BUS_BUSM_CNT_IERES_Msk    (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                           BUSS                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CNT  ========================================================== */
+ #define R_BUS_BUSS_CNT_ARBMET_Pos    (4UL)    /*!< ARBMET (Bit 4)                                        */
+ #define R_BUS_BUSS_CNT_ARBMET_Msk    (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03)                          */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDC                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  NCFG  ========================================================== */
+ #define R_CANFD_CFDC_NCFG_NBRP_Pos      (0UL)          /*!< NBRP (Bit 0)                                          */
+ #define R_CANFD_CFDC_NCFG_NBRP_Msk      (0x3ffUL)      /*!< NBRP (Bitfield-Mask: 0x3ff)                           */
+ #define R_CANFD_CFDC_NCFG_NSJW_Pos      (10UL)         /*!< NSJW (Bit 10)                                         */
+ #define R_CANFD_CFDC_NCFG_NSJW_Msk      (0x1fc00UL)    /*!< NSJW (Bitfield-Mask: 0x7f)                            */
+ #define R_CANFD_CFDC_NCFG_NTSEG1_Pos    (17UL)         /*!< NTSEG1 (Bit 17)                                       */
+ #define R_CANFD_CFDC_NCFG_NTSEG1_Msk    (0x1fe0000UL)  /*!< NTSEG1 (Bitfield-Mask: 0xff)                          */
+ #define R_CANFD_CFDC_NCFG_NTSEG2_Pos    (25UL)         /*!< NTSEG2 (Bit 25)                                       */
+ #define R_CANFD_CFDC_NCFG_NTSEG2_Msk    (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f)                          */
+/* ==========================================================  CTR  ========================================================== */
+ #define R_CANFD_CFDC_CTR_CHMDC_Pos      (0UL)          /*!< CHMDC (Bit 0)                                         */
+ #define R_CANFD_CFDC_CTR_CHMDC_Msk      (0x3UL)        /*!< CHMDC (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDC_CTR_CSLPR_Pos      (2UL)          /*!< CSLPR (Bit 2)                                         */
+ #define R_CANFD_CFDC_CTR_CSLPR_Msk      (0x4UL)        /*!< CSLPR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_CTR_RTBO_Pos       (3UL)          /*!< RTBO (Bit 3)                                          */
+ #define R_CANFD_CFDC_CTR_RTBO_Msk       (0x8UL)        /*!< RTBO (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_BEIE_Pos       (8UL)          /*!< BEIE (Bit 8)                                          */
+ #define R_CANFD_CFDC_CTR_BEIE_Msk       (0x100UL)      /*!< BEIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_EWIE_Pos       (9UL)          /*!< EWIE (Bit 9)                                          */
+ #define R_CANFD_CFDC_CTR_EWIE_Msk       (0x200UL)      /*!< EWIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_EPIE_Pos       (10UL)         /*!< EPIE (Bit 10)                                         */
+ #define R_CANFD_CFDC_CTR_EPIE_Msk       (0x400UL)      /*!< EPIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_BOEIE_Pos      (11UL)         /*!< BOEIE (Bit 11)                                        */
+ #define R_CANFD_CFDC_CTR_BOEIE_Msk      (0x800UL)      /*!< BOEIE (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_CTR_BORIE_Pos      (12UL)         /*!< BORIE (Bit 12)                                        */
+ #define R_CANFD_CFDC_CTR_BORIE_Msk      (0x1000UL)     /*!< BORIE (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_CTR_OLIE_Pos       (13UL)         /*!< OLIE (Bit 13)                                         */
+ #define R_CANFD_CFDC_CTR_OLIE_Msk       (0x2000UL)     /*!< OLIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_BLIE_Pos       (14UL)         /*!< BLIE (Bit 14)                                         */
+ #define R_CANFD_CFDC_CTR_BLIE_Msk       (0x4000UL)     /*!< BLIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_ALIE_Pos       (15UL)         /*!< ALIE (Bit 15)                                         */
+ #define R_CANFD_CFDC_CTR_ALIE_Msk       (0x8000UL)     /*!< ALIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_TAIE_Pos       (16UL)         /*!< TAIE (Bit 16)                                         */
+ #define R_CANFD_CFDC_CTR_TAIE_Msk       (0x10000UL)    /*!< TAIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_EOCOIE_Pos     (17UL)         /*!< EOCOIE (Bit 17)                                       */
+ #define R_CANFD_CFDC_CTR_EOCOIE_Msk     (0x20000UL)    /*!< EOCOIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC_CTR_SOCOIE_Pos     (18UL)         /*!< SOCOIE (Bit 18)                                       */
+ #define R_CANFD_CFDC_CTR_SOCOIE_Msk     (0x40000UL)    /*!< SOCOIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC_CTR_TDCVFIE_Pos    (19UL)         /*!< TDCVFIE (Bit 19)                                      */
+ #define R_CANFD_CFDC_CTR_TDCVFIE_Msk    (0x80000UL)    /*!< TDCVFIE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDC_CTR_BOM_Pos        (21UL)         /*!< BOM (Bit 21)                                          */
+ #define R_CANFD_CFDC_CTR_BOM_Msk        (0x600000UL)   /*!< BOM (Bitfield-Mask: 0x03)                             */
+ #define R_CANFD_CFDC_CTR_ERRD_Pos       (23UL)         /*!< ERRD (Bit 23)                                         */
+ #define R_CANFD_CFDC_CTR_ERRD_Msk       (0x800000UL)   /*!< ERRD (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_CTME_Pos       (24UL)         /*!< CTME (Bit 24)                                         */
+ #define R_CANFD_CFDC_CTR_CTME_Msk       (0x1000000UL)  /*!< CTME (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_CTMS_Pos       (25UL)         /*!< CTMS (Bit 25)                                         */
+ #define R_CANFD_CFDC_CTR_CTMS_Msk       (0x6000000UL)  /*!< CTMS (Bitfield-Mask: 0x03)                            */
+ #define R_CANFD_CFDC_CTR_CRCT_Pos       (30UL)         /*!< CRCT (Bit 30)                                         */
+ #define R_CANFD_CFDC_CTR_CRCT_Msk       (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_CTR_ROM_Pos        (31UL)         /*!< ROM (Bit 31)                                          */
+ #define R_CANFD_CFDC_CTR_ROM_Msk        (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01)                             */
+/* ==========================================================  STS  ========================================================== */
+ #define R_CANFD_CFDC_STS_CRSTSTS_Pos    (0UL)          /*!< CRSTSTS (Bit 0)                                       */
+ #define R_CANFD_CFDC_STS_CRSTSTS_Msk    (0x1UL)        /*!< CRSTSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDC_STS_CHLTSTS_Pos    (1UL)          /*!< CHLTSTS (Bit 1)                                       */
+ #define R_CANFD_CFDC_STS_CHLTSTS_Msk    (0x2UL)        /*!< CHLTSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDC_STS_CSLPSTS_Pos    (2UL)          /*!< CSLPSTS (Bit 2)                                       */
+ #define R_CANFD_CFDC_STS_CSLPSTS_Msk    (0x4UL)        /*!< CSLPSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDC_STS_EPSTS_Pos      (3UL)          /*!< EPSTS (Bit 3)                                         */
+ #define R_CANFD_CFDC_STS_EPSTS_Msk      (0x8UL)        /*!< EPSTS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_STS_BOSTS_Pos      (4UL)          /*!< BOSTS (Bit 4)                                         */
+ #define R_CANFD_CFDC_STS_BOSTS_Msk      (0x10UL)       /*!< BOSTS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_STS_TRMSTS_Pos     (5UL)          /*!< TRMSTS (Bit 5)                                        */
+ #define R_CANFD_CFDC_STS_TRMSTS_Msk     (0x20UL)       /*!< TRMSTS (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC_STS_RECSTS_Pos     (6UL)          /*!< RECSTS (Bit 6)                                        */
+ #define R_CANFD_CFDC_STS_RECSTS_Msk     (0x40UL)       /*!< RECSTS (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC_STS_COMSTS_Pos     (7UL)          /*!< COMSTS (Bit 7)                                        */
+ #define R_CANFD_CFDC_STS_COMSTS_Msk     (0x80UL)       /*!< COMSTS (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC_STS_ESIF_Pos       (8UL)          /*!< ESIF (Bit 8)                                          */
+ #define R_CANFD_CFDC_STS_ESIF_Msk       (0x100UL)      /*!< ESIF (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_STS_REC_Pos        (16UL)         /*!< REC (Bit 16)                                          */
+ #define R_CANFD_CFDC_STS_REC_Msk        (0xff0000UL)   /*!< REC (Bitfield-Mask: 0xff)                             */
+ #define R_CANFD_CFDC_STS_TEC_Pos        (24UL)         /*!< TEC (Bit 24)                                          */
+ #define R_CANFD_CFDC_STS_TEC_Msk        (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff)                             */
+/* =========================================================  ERFL  ========================================================== */
+ #define R_CANFD_CFDC_ERFL_BEF_Pos       (0UL)          /*!< BEF (Bit 0)                                           */
+ #define R_CANFD_CFDC_ERFL_BEF_Msk       (0x1UL)        /*!< BEF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDC_ERFL_EWF_Pos       (1UL)          /*!< EWF (Bit 1)                                           */
+ #define R_CANFD_CFDC_ERFL_EWF_Msk       (0x2UL)        /*!< EWF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDC_ERFL_EPF_Pos       (2UL)          /*!< EPF (Bit 2)                                           */
+ #define R_CANFD_CFDC_ERFL_EPF_Msk       (0x4UL)        /*!< EPF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDC_ERFL_BOEF_Pos      (3UL)          /*!< BOEF (Bit 3)                                          */
+ #define R_CANFD_CFDC_ERFL_BOEF_Msk      (0x8UL)        /*!< BOEF (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_BORF_Pos      (4UL)          /*!< BORF (Bit 4)                                          */
+ #define R_CANFD_CFDC_ERFL_BORF_Msk      (0x10UL)       /*!< BORF (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_OVLF_Pos      (5UL)          /*!< OVLF (Bit 5)                                          */
+ #define R_CANFD_CFDC_ERFL_OVLF_Msk      (0x20UL)       /*!< OVLF (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_BLF_Pos       (6UL)          /*!< BLF (Bit 6)                                           */
+ #define R_CANFD_CFDC_ERFL_BLF_Msk       (0x40UL)       /*!< BLF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDC_ERFL_ALF_Pos       (7UL)          /*!< ALF (Bit 7)                                           */
+ #define R_CANFD_CFDC_ERFL_ALF_Msk       (0x80UL)       /*!< ALF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDC_ERFL_SERR_Pos      (8UL)          /*!< SERR (Bit 8)                                          */
+ #define R_CANFD_CFDC_ERFL_SERR_Msk      (0x100UL)      /*!< SERR (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_FERR_Pos      (9UL)          /*!< FERR (Bit 9)                                          */
+ #define R_CANFD_CFDC_ERFL_FERR_Msk      (0x200UL)      /*!< FERR (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_AERR_Pos      (10UL)         /*!< AERR (Bit 10)                                         */
+ #define R_CANFD_CFDC_ERFL_AERR_Msk      (0x400UL)      /*!< AERR (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_CERR_Pos      (11UL)         /*!< CERR (Bit 11)                                         */
+ #define R_CANFD_CFDC_ERFL_CERR_Msk      (0x800UL)      /*!< CERR (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC_ERFL_B1ERR_Pos     (12UL)         /*!< B1ERR (Bit 12)                                        */
+ #define R_CANFD_CFDC_ERFL_B1ERR_Msk     (0x1000UL)     /*!< B1ERR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_ERFL_B0ERR_Pos     (13UL)         /*!< B0ERR (Bit 13)                                        */
+ #define R_CANFD_CFDC_ERFL_B0ERR_Msk     (0x2000UL)     /*!< B0ERR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_ERFL_ADERR_Pos     (14UL)         /*!< ADERR (Bit 14)                                        */
+ #define R_CANFD_CFDC_ERFL_ADERR_Msk     (0x4000UL)     /*!< ADERR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC_ERFL_CRCREG_Pos    (16UL)         /*!< CRCREG (Bit 16)                                       */
+ #define R_CANFD_CFDC_ERFL_CRCREG_Msk    (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDC2                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DCFG  ========================================================== */
+ #define R_CANFD_CFDC2_DCFG_DBRP_Pos       (0UL)          /*!< DBRP (Bit 0)                                          */
+ #define R_CANFD_CFDC2_DCFG_DBRP_Msk       (0xffUL)       /*!< DBRP (Bitfield-Mask: 0xff)                            */
+ #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos     (8UL)          /*!< DTSEG1 (Bit 8)                                        */
+ #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk     (0x1f00UL)     /*!< DTSEG1 (Bitfield-Mask: 0x1f)                          */
+ #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos     (16UL)         /*!< DTSEG2 (Bit 16)                                       */
+ #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk     (0xf0000UL)    /*!< DTSEG2 (Bitfield-Mask: 0x0f)                          */
+ #define R_CANFD_CFDC2_DCFG_DSJW_Pos       (24UL)         /*!< DSJW (Bit 24)                                         */
+ #define R_CANFD_CFDC2_DCFG_DSJW_Msk       (0xf000000UL)  /*!< DSJW (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  FDCFG  ========================================================= */
+ #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos    (0UL)          /*!< EOCCFG (Bit 0)                                        */
+ #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk    (0x7UL)        /*!< EOCCFG (Bitfield-Mask: 0x07)                          */
+ #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos     (8UL)          /*!< TDCOC (Bit 8)                                         */
+ #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk     (0x100UL)      /*!< TDCOC (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC2_FDCFG_TDCE_Pos      (9UL)          /*!< TDCE (Bit 9)                                          */
+ #define R_CANFD_CFDC2_FDCFG_TDCE_Msk      (0x200UL)      /*!< TDCE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDCFG_ESIC_Pos      (10UL)         /*!< ESIC (Bit 10)                                         */
+ #define R_CANFD_CFDC2_FDCFG_ESIC_Msk      (0x400UL)      /*!< ESIC (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDCFG_TDCO_Pos      (16UL)         /*!< TDCO (Bit 16)                                         */
+ #define R_CANFD_CFDC2_FDCFG_TDCO_Msk      (0xff0000UL)   /*!< TDCO (Bitfield-Mask: 0xff)                            */
+ #define R_CANFD_CFDC2_FDCFG_FDOE_Pos      (28UL)         /*!< FDOE (Bit 28)                                         */
+ #define R_CANFD_CFDC2_FDCFG_FDOE_Msk      (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDCFG_REFE_Pos      (29UL)         /*!< REFE (Bit 29)                                         */
+ #define R_CANFD_CFDC2_FDCFG_REFE_Msk      (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDCFG_CLOE_Pos      (30UL)         /*!< CLOE (Bit 30)                                         */
+ #define R_CANFD_CFDC2_FDCFG_CLOE_Msk      (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  FDCTR  ========================================================= */
+ #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos    (0UL)          /*!< EOCCLR (Bit 0)                                        */
+ #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk    (0x1UL)        /*!< EOCCLR (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos    (1UL)          /*!< SOCCLR (Bit 1)                                        */
+ #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk    (0x2UL)        /*!< SOCCLR (Bitfield-Mask: 0x01)                          */
+/* =========================================================  FDSTS  ========================================================= */
+ #define R_CANFD_CFDC2_FDSTS_TDCR_Pos      (0UL)          /*!< TDCR (Bit 0)                                          */
+ #define R_CANFD_CFDC2_FDSTS_TDCR_Msk      (0xffUL)       /*!< TDCR (Bitfield-Mask: 0xff)                            */
+ #define R_CANFD_CFDC2_FDSTS_EOCO_Pos      (8UL)          /*!< EOCO (Bit 8)                                          */
+ #define R_CANFD_CFDC2_FDSTS_EOCO_Msk      (0x100UL)      /*!< EOCO (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDSTS_SOCO_Pos      (9UL)          /*!< SOCO (Bit 9)                                          */
+ #define R_CANFD_CFDC2_FDSTS_SOCO_Msk      (0x200UL)      /*!< SOCO (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos     (15UL)         /*!< TDCVF (Bit 15)                                        */
+ #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk     (0x8000UL)     /*!< TDCVF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDC2_FDSTS_EOC_Pos       (16UL)         /*!< EOC (Bit 16)                                          */
+ #define R_CANFD_CFDC2_FDSTS_EOC_Msk       (0xff0000UL)   /*!< EOC (Bitfield-Mask: 0xff)                             */
+ #define R_CANFD_CFDC2_FDSTS_SOC_Pos       (24UL)         /*!< SOC (Bit 24)                                          */
+ #define R_CANFD_CFDC2_FDSTS_SOC_Msk       (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff)                             */
+/* =========================================================  FDCRC  ========================================================= */
+ #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos    (0UL)          /*!< CRCREG (Bit 0)                                        */
+ #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk    (0x1fffffUL)   /*!< CRCREG (Bitfield-Mask: 0x1fffff)                      */
+ #define R_CANFD_CFDC2_FDCRC_SCNT_Pos      (24UL)         /*!< SCNT (Bit 24)                                         */
+ #define R_CANFD_CFDC2_FDCRC_SCNT_Msk      (0xf000000UL)  /*!< SCNT (Bitfield-Mask: 0x0f)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          CFDGAFL                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CANFD_CFDGAFL_ID_GAFLID_Pos      (0UL)          /*!< GAFLID (Bit 0)                                        */
+ #define R_CANFD_CFDGAFL_ID_GAFLID_Msk      (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff)                    */
+ #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos      (29UL)         /*!< GAFLLB (Bit 29)                                       */
+ #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk      (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos     (30UL)         /*!< GAFLRTR (Bit 30)                                      */
+ #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk     (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos     (31UL)         /*!< GAFLIDE (Bit 31)                                      */
+ #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk     (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01)                         */
+/* ===========================================================  M  =========================================================== */
+ #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos      (0UL)          /*!< GAFLIDM (Bit 0)                                       */
+ #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk      (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff)                   */
+ #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos     (29UL)         /*!< GAFLIFL1 (Bit 29)                                     */
+ #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk     (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos     (30UL)         /*!< GAFLRTRM (Bit 30)                                     */
+ #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk     (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos     (31UL)         /*!< GAFLIDEM (Bit 31)                                     */
+ #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk     (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01)                        */
+/* ==========================================================  P0  =========================================================== */
+ #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos     (0UL)          /*!< GAFLDLC (Bit 0)                                       */
+ #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk     (0xfUL)        /*!< GAFLDLC (Bitfield-Mask: 0x0f)                         */
+ #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos    (7UL)          /*!< GAFLIFL0 (Bit 7)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk    (0x80UL)       /*!< GAFLIFL0 (Bitfield-Mask: 0x01)                        */
+ #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos    (8UL)          /*!< GAFLRMDP (Bit 8)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk    (0x1f00UL)     /*!< GAFLRMDP (Bitfield-Mask: 0x1f)                        */
+ #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos     (15UL)         /*!< GAFLRMV (Bit 15)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk     (0x8000UL)     /*!< GAFLRMV (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos     (16UL)         /*!< GAFLPTR (Bit 16)                                      */
+ #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk     (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff)                       */
+/* ==========================================================  P1  =========================================================== */
+ #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos     (0UL)          /*!< GAFLFDP (Bit 0)                                       */
+ #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk     (0x1ffUL)      /*!< GAFLFDP (Bitfield-Mask: 0x1ff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                          CFDTHL                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ACC0  ========================================================== */
+ #define R_CANFD_CFDTHL_ACC0_BT_Pos      (0UL)          /*!< BT (Bit 0)                                            */
+ #define R_CANFD_CFDTHL_ACC0_BT_Msk      (0x7UL)        /*!< BT (Bitfield-Mask: 0x07)                              */
+ #define R_CANFD_CFDTHL_ACC0_BN_Pos      (3UL)          /*!< BN (Bit 3)                                            */
+ #define R_CANFD_CFDTHL_ACC0_BN_Msk      (0x3f8UL)      /*!< BN (Bitfield-Mask: 0x7f)                              */
+ #define R_CANFD_CFDTHL_ACC0_TMTS_Pos    (16UL)         /*!< TMTS (Bit 16)                                         */
+ #define R_CANFD_CFDTHL_ACC0_TMTS_Msk    (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  ACC1  ========================================================== */
+ #define R_CANFD_CFDTHL_ACC1_TID_Pos     (0UL)          /*!< TID (Bit 0)                                           */
+ #define R_CANFD_CFDTHL_ACC1_TID_Msk     (0xffffUL)     /*!< TID (Bitfield-Mask: 0xffff)                           */
+ #define R_CANFD_CFDTHL_ACC1_TIFL_Pos    (16UL)         /*!< TIFL (Bit 16)                                         */
+ #define R_CANFD_CFDTHL_ACC1_TIFL_Msk    (0x30000UL)    /*!< TIFL (Bitfield-Mask: 0x03)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDRF                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CANFD_CFDRF_ID_RFID_Pos        (0UL)          /*!< RFID (Bit 0)                                          */
+ #define R_CANFD_CFDRF_ID_RFID_Msk        (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff)                      */
+ #define R_CANFD_CFDRF_ID_RFRTR_Pos       (30UL)         /*!< RFRTR (Bit 30)                                        */
+ #define R_CANFD_CFDRF_ID_RFRTR_Msk       (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRF_ID_RFIDE_Pos       (31UL)         /*!< RFIDE (Bit 31)                                        */
+ #define R_CANFD_CFDRF_ID_RFIDE_Msk       (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  PTR  ========================================================== */
+ #define R_CANFD_CFDRF_PTR_RFTS_Pos       (0UL)          /*!< RFTS (Bit 0)                                          */
+ #define R_CANFD_CFDRF_PTR_RFTS_Msk       (0xffffUL)     /*!< RFTS (Bitfield-Mask: 0xffff)                          */
+ #define R_CANFD_CFDRF_PTR_RFDLC_Pos      (28UL)         /*!< RFDLC (Bit 28)                                        */
+ #define R_CANFD_CFDRF_PTR_RFDLC_Msk      (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f)                           */
+/* =========================================================  FDSTS  ========================================================= */
+ #define R_CANFD_CFDRF_FDSTS_RFESI_Pos    (0UL)          /*!< RFESI (Bit 0)                                         */
+ #define R_CANFD_CFDRF_FDSTS_RFESI_Msk    (0x1UL)        /*!< RFESI (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos    (1UL)          /*!< RFBRS (Bit 1)                                         */
+ #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk    (0x2UL)        /*!< RFBRS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos    (2UL)          /*!< RFFDF (Bit 2)                                         */
+ #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk    (0x4UL)        /*!< RFFDF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos    (8UL)          /*!< RFIFL (Bit 8)                                         */
+ #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk    (0x300UL)      /*!< RFIFL (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos    (16UL)         /*!< RFPTR (Bit 16)                                        */
+ #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk    (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff)                         */
+/* ==========================================================  DF  =========================================================== */
+ #define R_CANFD_CFDRF_DF_RFDB_Pos        (0UL)          /*!< RFDB (Bit 0)                                          */
+ #define R_CANFD_CFDRF_DF_RFDB_Msk        (0xffUL)       /*!< RFDB (Bitfield-Mask: 0xff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDCF                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CANFD_CFDCF_ID_CFID_Pos        (0UL)          /*!< CFID (Bit 0)                                          */
+ #define R_CANFD_CFDCF_ID_CFID_Msk        (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff)                      */
+ #define R_CANFD_CFDCF_ID_CFRTR_Pos       (30UL)         /*!< CFRTR (Bit 30)                                        */
+ #define R_CANFD_CFDCF_ID_CFRTR_Msk       (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCF_ID_CFIDE_Pos       (31UL)         /*!< CFIDE (Bit 31)                                        */
+ #define R_CANFD_CFDCF_ID_CFIDE_Msk       (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  PTR  ========================================================== */
+ #define R_CANFD_CFDCF_PTR_CFTS_Pos       (0UL)          /*!< CFTS (Bit 0)                                          */
+ #define R_CANFD_CFDCF_PTR_CFTS_Msk       (0xffffUL)     /*!< CFTS (Bitfield-Mask: 0xffff)                          */
+ #define R_CANFD_CFDCF_PTR_CFDLC_Pos      (28UL)         /*!< CFDLC (Bit 28)                                        */
+ #define R_CANFD_CFDCF_PTR_CFDLC_Msk      (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f)                           */
+/* =========================================================  FDSTS  ========================================================= */
+ #define R_CANFD_CFDCF_FDSTS_CFESI_Pos    (0UL)          /*!< CFESI (Bit 0)                                         */
+ #define R_CANFD_CFDCF_FDSTS_CFESI_Msk    (0x1UL)        /*!< CFESI (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos    (1UL)          /*!< CFBRS (Bit 1)                                         */
+ #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk    (0x2UL)        /*!< CFBRS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos    (2UL)          /*!< CFFDF (Bit 2)                                         */
+ #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk    (0x4UL)        /*!< CFFDF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos    (8UL)          /*!< CFIFL (Bit 8)                                         */
+ #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk    (0x300UL)      /*!< CFIFL (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos    (16UL)         /*!< CFPTR (Bit 16)                                        */
+ #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk    (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff)                         */
+/* ==========================================================  DF  =========================================================== */
+ #define R_CANFD_CFDCF_DF_CFDB_Pos        (0UL)          /*!< CFDB (Bit 0)                                          */
+ #define R_CANFD_CFDCF_DF_CFDB_Msk        (0xffUL)       /*!< CFDB (Bitfield-Mask: 0xff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDTM                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CANFD_CFDTM_ID_TMID_Pos        (0UL)          /*!< TMID (Bit 0)                                          */
+ #define R_CANFD_CFDTM_ID_TMID_Msk        (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff)                      */
+ #define R_CANFD_CFDTM_ID_TMRTR_Pos       (30UL)         /*!< TMRTR (Bit 30)                                        */
+ #define R_CANFD_CFDTM_ID_TMRTR_Msk       (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTM_ID_TMIDE_Pos       (31UL)         /*!< TMIDE (Bit 31)                                        */
+ #define R_CANFD_CFDTM_ID_TMIDE_Msk       (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  PTR  ========================================================== */
+ #define R_CANFD_CFDTM_PTR_TMTS_Pos       (0UL)          /*!< TMTS (Bit 0)                                          */
+ #define R_CANFD_CFDTM_PTR_TMTS_Msk       (0xffffUL)     /*!< TMTS (Bitfield-Mask: 0xffff)                          */
+ #define R_CANFD_CFDTM_PTR_TMDLC_Pos      (28UL)         /*!< TMDLC (Bit 28)                                        */
+ #define R_CANFD_CFDTM_PTR_TMDLC_Msk      (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f)                           */
+/* =========================================================  FDCTR  ========================================================= */
+ #define R_CANFD_CFDTM_FDCTR_TMESI_Pos    (0UL)          /*!< TMESI (Bit 0)                                         */
+ #define R_CANFD_CFDTM_FDCTR_TMESI_Msk    (0x1UL)        /*!< TMESI (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos    (1UL)          /*!< TMBRS (Bit 1)                                         */
+ #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk    (0x2UL)        /*!< TMBRS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos    (2UL)          /*!< TMFDF (Bit 2)                                         */
+ #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk    (0x4UL)        /*!< TMFDF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos    (8UL)          /*!< TMIFL (Bit 8)                                         */
+ #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk    (0x300UL)      /*!< TMIFL (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos    (16UL)         /*!< TMPTR (Bit 16)                                        */
+ #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk    (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff)                         */
+/* ==========================================================  DF  =========================================================== */
+ #define R_CANFD_CFDTM_DF_TMDB_Pos        (0UL)          /*!< TMDB (Bit 0)                                          */
+ #define R_CANFD_CFDTM_DF_TMDB_Msk        (0xffUL)       /*!< TMDB (Bitfield-Mask: 0xff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                            RM                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CANFD_CFDRM_RM_ID_RMID_Pos        (0UL)          /*!< RMID (Bit 0)                                          */
+ #define R_CANFD_CFDRM_RM_ID_RMID_Msk        (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff)                      */
+ #define R_CANFD_CFDRM_RM_ID_RMRTR_Pos       (30UL)         /*!< RMRTR (Bit 30)                                        */
+ #define R_CANFD_CFDRM_RM_ID_RMRTR_Msk       (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRM_RM_ID_RMIDE_Pos       (31UL)         /*!< RMIDE (Bit 31)                                        */
+ #define R_CANFD_CFDRM_RM_ID_RMIDE_Msk       (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  PTR  ========================================================== */
+ #define R_CANFD_CFDRM_RM_PTR_RMTS_Pos       (0UL)          /*!< RMTS (Bit 0)                                          */
+ #define R_CANFD_CFDRM_RM_PTR_RMTS_Msk       (0xffffUL)     /*!< RMTS (Bitfield-Mask: 0xffff)                          */
+ #define R_CANFD_CFDRM_RM_PTR_RMDLC_Pos      (28UL)         /*!< RMDLC (Bit 28)                                        */
+ #define R_CANFD_CFDRM_RM_PTR_RMDLC_Msk      (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f)                           */
+/* =========================================================  FDSTS  ========================================================= */
+ #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Pos    (0UL)          /*!< RMESI (Bit 0)                                         */
+ #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Msk    (0x1UL)        /*!< RMESI (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Pos    (1UL)          /*!< RMBRS (Bit 1)                                         */
+ #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Msk    (0x2UL)        /*!< RMBRS (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Pos    (2UL)          /*!< RMFDF (Bit 2)                                         */
+ #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Msk    (0x4UL)        /*!< RMFDF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Pos    (8UL)          /*!< RMIFL (Bit 8)                                         */
+ #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Msk    (0x300UL)      /*!< RMIFL (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Pos    (16UL)         /*!< RMPTR (Bit 16)                                        */
+ #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Msk    (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff)                         */
+/* ==========================================================  DF  =========================================================== */
+ #define R_CANFD_CFDRM_RM_DF_RMDB_Pos        (0UL)          /*!< RMDB (Bit 0)                                          */
+ #define R_CANFD_CFDRM_RM_DF_RMDB_Msk        (0xffUL)       /*!< RMDB (Bitfield-Mask: 0xff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           CFDRM                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          ELSEGR                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  BY  =========================================================== */
+ #define R_ELC_ELSEGR_BY_WI_Pos     (7UL)    /*!< WI (Bit 7)                                            */
+ #define R_ELC_ELSEGR_BY_WI_Msk     (0x80UL) /*!< WI (Bitfield-Mask: 0x01)                              */
+ #define R_ELC_ELSEGR_BY_WE_Pos     (6UL)    /*!< WE (Bit 6)                                            */
+ #define R_ELC_ELSEGR_BY_WE_Msk     (0x40UL) /*!< WE (Bitfield-Mask: 0x01)                              */
+ #define R_ELC_ELSEGR_BY_SEG_Pos    (0UL)    /*!< SEG (Bit 0)                                           */
+ #define R_ELC_ELSEGR_BY_SEG_Msk    (0x1UL)  /*!< SEG (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           ELSR                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  HA  =========================================================== */
+ #define R_ELC_ELSR_HA_ELS_Pos    (0UL)     /*!< ELS (Bit 0)                                           */
+ #define R_ELC_ELSR_HA_ELS_Msk    (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                            SAR                                            ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  L  =========================================================== */
+ #define R_IIC0_SAR_L_SVA_Pos     (0UL)    /*!< SVA (Bit 0)                                           */
+ #define R_IIC0_SAR_L_SVA_Msk     (0xffUL) /*!< SVA (Bitfield-Mask: 0xff)                             */
+/* ===========================================================  U  =========================================================== */
+ #define R_IIC0_SAR_U_SVA9_Pos    (2UL)    /*!< SVA9 (Bit 2)                                          */
+ #define R_IIC0_SAR_U_SVA9_Msk    (0x4UL)  /*!< SVA9 (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_SAR_U_SVA8_Pos    (1UL)    /*!< SVA8 (Bit 1)                                          */
+ #define R_IIC0_SAR_U_SVA8_Msk    (0x2UL)  /*!< SVA8 (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_SAR_U_FS_Pos      (0UL)    /*!< FS (Bit 0)                                            */
+ #define R_IIC0_SAR_U_FS_Msk      (0x1UL)  /*!< FS (Bitfield-Mask: 0x01)                              */
+
+/* =========================================================================================================================== */
+/* ================                                            SP                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  OAD  ========================================================== */
+ #define R_MPU_SPMON_SP_OAD_KEY_Pos        (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_MPU_SPMON_SP_OAD_KEY_Msk        (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_MPU_SPMON_SP_OAD_OAD_Pos        (0UL)          /*!< OAD (Bit 0)                                           */
+ #define R_MPU_SPMON_SP_OAD_OAD_Msk        (0x1UL)        /*!< OAD (Bitfield-Mask: 0x01)                             */
+/* ==========================================================  CTL  ========================================================== */
+ #define R_MPU_SPMON_SP_CTL_ERROR_Pos      (8UL)          /*!< ERROR (Bit 8)                                         */
+ #define R_MPU_SPMON_SP_CTL_ERROR_Msk      (0x100UL)      /*!< ERROR (Bitfield-Mask: 0x01)                           */
+ #define R_MPU_SPMON_SP_CTL_ENABLE_Pos     (0UL)          /*!< ENABLE (Bit 0)                                        */
+ #define R_MPU_SPMON_SP_CTL_ENABLE_Msk     (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+/* ==========================================================  PT  =========================================================== */
+ #define R_MPU_SPMON_SP_PT_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_MPU_SPMON_SP_PT_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_MPU_SPMON_SP_PT_PROTECT_Pos     (0UL)          /*!< PROTECT (Bit 0)                                       */
+ #define R_MPU_SPMON_SP_PT_PROTECT_Msk     (0x1UL)        /*!< PROTECT (Bitfield-Mask: 0x01)                         */
+/* ==========================================================  SA  =========================================================== */
+ #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos    (0UL)          /*!< MSPMPUSA (Bit 0)                                      */
+ #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk    (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff)                  */
+/* ==========================================================  EA  =========================================================== */
+ #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos    (0UL)          /*!< MSPMPUEA (Bit 0)                                      */
+ #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk    (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff)                  */
+
+/* =========================================================================================================================== */
+/* ================                                            PIN                                            ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  PmnPFS_BY  ======================================================= */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos      (5UL)          /*!< PIM (Bit 5)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk      (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
+/* =======================================================  PmnPFS_HA  ======================================================= */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos      (5UL)          /*!< PIM (Bit 5)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk      (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos     (15UL)         /*!< ASEL (Bit 15)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk     (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos     (14UL)         /*!< ISEL (Bit 14)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk     (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos     (12UL)         /*!< EOFR (Bit 12)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk     (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos     (10UL)         /*!< DSCR (Bit 10)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk     (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
+/* ========================================================  PmnPFS  ========================================================= */
+ #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos       (6UL)          /*!< NCODR (Bit 6)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk       (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
+ #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos         (5UL)          /*!< PIM (Bit 5)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk         (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos         (4UL)          /*!< PCR (Bit 4)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk         (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos         (2UL)          /*!< PDR (Bit 2)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk         (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos        (1UL)          /*!< PIDR (Bit 1)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk        (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos        (0UL)          /*!< PODR (Bit 0)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk        (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos        (15UL)         /*!< ASEL (Bit 15)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk        (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos        (14UL)         /*!< ISEL (Bit 14)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk        (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos        (12UL)         /*!< EOFR (Bit 12)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk        (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos        (10UL)         /*!< DSCR (Bit 10)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk        (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos        (24UL)         /*!< PSEL (Bit 24)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk        (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos         (16UL)         /*!< PMR (Bit 16)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk         (0x10000UL)    /*!< PMR (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           PORT                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                           VLSEL                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  VL1SEL  ========================================================= */
+ #define R_PFS_VLSEL_VL1SEL_SELVL_Pos    (0UL)   /*!< SELVL (Bit 0)                                         */
+ #define R_PFS_VLSEL_VL1SEL_SELVL_Msk    (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                           PMSAR                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  PMSAR  ========================================================= */
+
+/* =========================================================================================================================== */
+/* ================                                           RTCCR                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  RTCCR  ========================================================= */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
+ #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
+ #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCST_Msk    (0x4UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
+ #define R_RTC_RTCCR_RTCCR_TCCT_Pos    (0UL)    /*!< TCCT (Bit 0)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCCT_Msk    (0x3UL)  /*!< TCCT (Bitfield-Mask: 0x03)                            */
+
+/* =========================================================================================================================== */
+/* ================                                            CP                                             ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  RSEC  ========================================================== */
+ #define R_RTC_CP_RSEC_SEC10_Pos       (4UL)    /*!< SEC10 (Bit 4)                                         */
+ #define R_RTC_CP_RSEC_SEC10_Msk       (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07)                           */
+ #define R_RTC_CP_RSEC_SEC1_Pos        (0UL)    /*!< SEC1 (Bit 0)                                          */
+ #define R_RTC_CP_RSEC_SEC1_Msk        (0xfUL)  /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  BCNT0  ========================================================= */
+ #define R_RTC_CP_BCNT0_BCNT0CP_Pos    (0UL)    /*!< BCNT0CP (Bit 0)                                       */
+ #define R_RTC_CP_BCNT0_BCNT0CP_Msk    (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff)                         */
+/* =========================================================  RMIN  ========================================================== */
+ #define R_RTC_CP_RMIN_MIN10_Pos       (4UL)    /*!< MIN10 (Bit 4)                                         */
+ #define R_RTC_CP_RMIN_MIN10_Msk       (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07)                           */
+ #define R_RTC_CP_RMIN_MIN1_Pos        (0UL)    /*!< MIN1 (Bit 0)                                          */
+ #define R_RTC_CP_RMIN_MIN1_Msk        (0xfUL)  /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  BCNT1  ========================================================= */
+ #define R_RTC_CP_BCNT1_BCNT1CP_Pos    (0UL)    /*!< BCNT1CP (Bit 0)                                       */
+ #define R_RTC_CP_BCNT1_BCNT1CP_Msk    (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff)                         */
+/* ==========================================================  RHR  ========================================================== */
+ #define R_RTC_CP_RHR_PM_Pos           (6UL)    /*!< PM (Bit 6)                                            */
+ #define R_RTC_CP_RHR_PM_Msk           (0x40UL) /*!< PM (Bitfield-Mask: 0x01)                              */
+ #define R_RTC_CP_RHR_HR10_Pos         (4UL)    /*!< HR10 (Bit 4)                                          */
+ #define R_RTC_CP_RHR_HR10_Msk         (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03)                            */
+ #define R_RTC_CP_RHR_HR1_Pos          (0UL)    /*!< HR1 (Bit 0)                                           */
+ #define R_RTC_CP_RHR_HR1_Msk          (0xfUL)  /*!< HR1 (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  BCNT2  ========================================================= */
+ #define R_RTC_CP_BCNT2_BCNT2CP_Pos    (0UL)    /*!< BCNT2CP (Bit 0)                                       */
+ #define R_RTC_CP_BCNT2_BCNT2CP_Msk    (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff)                         */
+/* =========================================================  RDAY  ========================================================== */
+ #define R_RTC_CP_RDAY_DATE10_Pos      (4UL)    /*!< DATE10 (Bit 4)                                        */
+ #define R_RTC_CP_RDAY_DATE10_Msk      (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03)                          */
+ #define R_RTC_CP_RDAY_DATE1_Pos       (0UL)    /*!< DATE1 (Bit 0)                                         */
+ #define R_RTC_CP_RDAY_DATE1_Msk       (0xfUL)  /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
+/* =========================================================  BCNT3  ========================================================= */
+ #define R_RTC_CP_BCNT3_BCNT3CP_Pos    (0UL)    /*!< BCNT3CP (Bit 0)                                       */
+ #define R_RTC_CP_BCNT3_BCNT3CP_Msk    (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff)                         */
+/* =========================================================  RMON  ========================================================== */
+ #define R_RTC_CP_RMON_MON10_Pos       (4UL)    /*!< MON10 (Bit 4)                                         */
+ #define R_RTC_CP_RMON_MON10_Msk       (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_CP_RMON_MON1_Pos        (0UL)    /*!< MON1 (Bit 0)                                          */
+ #define R_RTC_CP_RMON_MON1_Msk        (0xfUL)  /*!< MON1 (Bitfield-Mask: 0x0f)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          PIPE_TR                                          ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  E  =========================================================== */
+ #define R_USB_FS0_PIPE_TR_E_TRENB_Pos     (9UL)      /*!< TRENB (Bit 9)                                         */
+ #define R_USB_FS0_PIPE_TR_E_TRENB_Msk     (0x200UL)  /*!< TRENB (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos     (8UL)      /*!< TRCLR (Bit 8)                                         */
+ #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk     (0x100UL)  /*!< TRCLR (Bitfield-Mask: 0x01)                           */
+/* ===========================================================  N  =========================================================== */
+ #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
+ #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           CTRL                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  AGTCR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AGTMR1  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
+/* ========================================================  AGTMR2  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
+/* =====================================================  AGTIOSEL_ALT  ====================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+/* ========================================================  AGTIOC  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AGTISR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AGTCMSR  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
+/* =======================================================  AGTIOSEL  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT16                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT32                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
+
+/** @} */ /* End of group PosMask_clusters */
+
+/* =========================================================================================================================== */
+/* ================                                Pos/Mask Peripheral Section                                ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup PosMask_peripherals
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ADC0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ADCSR  ========================================================= */
+ #define R_ADC0_ADCSR_ADST_Pos              (15UL)      /*!< ADST (Bit 15)                                         */
+ #define R_ADC0_ADCSR_ADST_Msk              (0x8000UL)  /*!< ADST (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADCSR_ADCS_Pos              (13UL)      /*!< ADCS (Bit 13)                                         */
+ #define R_ADC0_ADCSR_ADCS_Msk              (0x6000UL)  /*!< ADCS (Bitfield-Mask: 0x03)                            */
+ #define R_ADC0_ADCSR_ADHSC_Pos             (10UL)      /*!< ADHSC (Bit 10)                                        */
+ #define R_ADC0_ADCSR_ADHSC_Msk             (0x400UL)   /*!< ADHSC (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCSR_TRGE_Pos              (9UL)       /*!< TRGE (Bit 9)                                          */
+ #define R_ADC0_ADCSR_TRGE_Msk              (0x200UL)   /*!< TRGE (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADCSR_EXTRG_Pos             (8UL)       /*!< EXTRG (Bit 8)                                         */
+ #define R_ADC0_ADCSR_EXTRG_Msk             (0x100UL)   /*!< EXTRG (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCSR_DBLE_Pos              (7UL)       /*!< DBLE (Bit 7)                                          */
+ #define R_ADC0_ADCSR_DBLE_Msk              (0x80UL)    /*!< DBLE (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADCSR_GBADIE_Pos            (6UL)       /*!< GBADIE (Bit 6)                                        */
+ #define R_ADC0_ADCSR_GBADIE_Msk            (0x40UL)    /*!< GBADIE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCSR_DBLANS_Pos            (0UL)       /*!< DBLANS (Bit 0)                                        */
+ #define R_ADC0_ADCSR_DBLANS_Msk            (0x1fUL)    /*!< DBLANS (Bitfield-Mask: 0x1f)                          */
+ #define R_ADC0_ADCSR_ADIE_Pos              (12UL)      /*!< ADIE (Bit 12)                                         */
+ #define R_ADC0_ADCSR_ADIE_Msk              (0x1000UL)  /*!< ADIE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  ADANSA  ========================================================= */
+ #define R_ADC0_ADANSA_ANSA_Pos             (0UL)       /*!< ANSA (Bit 0)                                          */
+ #define R_ADC0_ADANSA_ANSA_Msk             (0x1UL)     /*!< ANSA (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ADADS  ========================================================= */
+ #define R_ADC0_ADADS_ADS_Pos               (0UL)       /*!< ADS (Bit 0)                                           */
+ #define R_ADC0_ADADS_ADS_Msk               (0x1UL)     /*!< ADS (Bitfield-Mask: 0x01)                             */
+/* =========================================================  ADADC  ========================================================= */
+ #define R_ADC0_ADADC_ADC_Pos               (0UL)       /*!< ADC (Bit 0)                                           */
+ #define R_ADC0_ADADC_ADC_Msk               (0x7UL)     /*!< ADC (Bitfield-Mask: 0x07)                             */
+ #define R_ADC0_ADADC_AVEE_Pos              (7UL)       /*!< AVEE (Bit 7)                                          */
+ #define R_ADC0_ADADC_AVEE_Msk              (0x80UL)    /*!< AVEE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ADCER  ========================================================= */
+ #define R_ADC0_ADCER_ADRFMT_Pos            (15UL)      /*!< ADRFMT (Bit 15)                                       */
+ #define R_ADC0_ADCER_ADRFMT_Msk            (0x8000UL)  /*!< ADRFMT (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCER_ADINV_Pos             (14UL)      /*!< ADINV (Bit 14)                                        */
+ #define R_ADC0_ADCER_ADINV_Msk             (0x4000UL)  /*!< ADINV (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCER_DIAGM_Pos             (11UL)      /*!< DIAGM (Bit 11)                                        */
+ #define R_ADC0_ADCER_DIAGM_Msk             (0x800UL)   /*!< DIAGM (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCER_DIAGLD_Pos            (10UL)      /*!< DIAGLD (Bit 10)                                       */
+ #define R_ADC0_ADCER_DIAGLD_Msk            (0x400UL)   /*!< DIAGLD (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCER_DIAGVAL_Pos           (8UL)       /*!< DIAGVAL (Bit 8)                                       */
+ #define R_ADC0_ADCER_DIAGVAL_Msk           (0x300UL)   /*!< DIAGVAL (Bitfield-Mask: 0x03)                         */
+ #define R_ADC0_ADCER_ACE_Pos               (5UL)       /*!< ACE (Bit 5)                                           */
+ #define R_ADC0_ADCER_ACE_Msk               (0x20UL)    /*!< ACE (Bitfield-Mask: 0x01)                             */
+ #define R_ADC0_ADCER_ADPRC_Pos             (1UL)       /*!< ADPRC (Bit 1)                                         */
+ #define R_ADC0_ADCER_ADPRC_Msk             (0x6UL)     /*!< ADPRC (Bitfield-Mask: 0x03)                           */
+ #define R_ADC0_ADCER_DCE_Pos               (4UL)       /*!< DCE (Bit 4)                                           */
+ #define R_ADC0_ADCER_DCE_Msk               (0x10UL)    /*!< DCE (Bitfield-Mask: 0x01)                             */
+/* ========================================================  ADSTRGR  ======================================================== */
+ #define R_ADC0_ADSTRGR_TRSA_Pos            (8UL)       /*!< TRSA (Bit 8)                                          */
+ #define R_ADC0_ADSTRGR_TRSA_Msk            (0x3f00UL)  /*!< TRSA (Bitfield-Mask: 0x3f)                            */
+ #define R_ADC0_ADSTRGR_TRSB_Pos            (0UL)       /*!< TRSB (Bit 0)                                          */
+ #define R_ADC0_ADSTRGR_TRSB_Msk            (0x3fUL)    /*!< TRSB (Bitfield-Mask: 0x3f)                            */
+/* ========================================================  ADEXICR  ======================================================== */
+ #define R_ADC0_ADEXICR_OCSB_Pos            (11UL)      /*!< OCSB (Bit 11)                                         */
+ #define R_ADC0_ADEXICR_OCSB_Msk            (0x800UL)   /*!< OCSB (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADEXICR_TSSB_Pos            (10UL)      /*!< TSSB (Bit 10)                                         */
+ #define R_ADC0_ADEXICR_TSSB_Msk            (0x400UL)   /*!< TSSB (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADEXICR_OCSA_Pos            (9UL)       /*!< OCSA (Bit 9)                                          */
+ #define R_ADC0_ADEXICR_OCSA_Msk            (0x200UL)   /*!< OCSA (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADEXICR_TSSA_Pos            (8UL)       /*!< TSSA (Bit 8)                                          */
+ #define R_ADC0_ADEXICR_TSSA_Msk            (0x100UL)   /*!< TSSA (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADEXICR_OCSAD_Pos           (1UL)       /*!< OCSAD (Bit 1)                                         */
+ #define R_ADC0_ADEXICR_OCSAD_Msk           (0x2UL)     /*!< OCSAD (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADEXICR_TSSAD_Pos           (0UL)       /*!< TSSAD (Bit 0)                                         */
+ #define R_ADC0_ADEXICR_TSSAD_Msk           (0x1UL)     /*!< TSSAD (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADEXICR_EXSEL_Pos           (14UL)      /*!< EXSEL (Bit 14)                                        */
+ #define R_ADC0_ADEXICR_EXSEL_Msk           (0x4000UL)  /*!< EXSEL (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADEXICR_EXOEN_Pos           (15UL)      /*!< EXOEN (Bit 15)                                        */
+ #define R_ADC0_ADEXICR_EXOEN_Msk           (0x8000UL)  /*!< EXOEN (Bitfield-Mask: 0x01)                           */
+/* ========================================================  ADANSB  ========================================================= */
+ #define R_ADC0_ADANSB_ANSB_Pos             (0UL)       /*!< ANSB (Bit 0)                                          */
+ #define R_ADC0_ADANSB_ANSB_Msk             (0x1UL)     /*!< ANSB (Bitfield-Mask: 0x01)                            */
+/* ========================================================  ADDBLDR  ======================================================== */
+ #define R_ADC0_ADDBLDR_ADDBLDR_Pos         (0UL)       /*!< ADDBLDR (Bit 0)                                       */
+ #define R_ADC0_ADDBLDR_ADDBLDR_Msk         (0xffffUL)  /*!< ADDBLDR (Bitfield-Mask: 0xffff)                       */
+/* ========================================================  ADTSDR  ========================================================= */
+ #define R_ADC0_ADTSDR_ADTSDR_Pos           (0UL)       /*!< ADTSDR (Bit 0)                                        */
+ #define R_ADC0_ADTSDR_ADTSDR_Msk           (0xffffUL)  /*!< ADTSDR (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  ADOCDR  ========================================================= */
+ #define R_ADC0_ADOCDR_ADOCDR_Pos           (0UL)       /*!< ADOCDR (Bit 0)                                        */
+ #define R_ADC0_ADOCDR_ADOCDR_Msk           (0xffffUL)  /*!< ADOCDR (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  ADRD_RIGHT  ======================================================= */
+ #define R_ADC0_ADRD_RIGHT_DIAGST_Pos       (14UL)      /*!< DIAGST (Bit 14)                                       */
+ #define R_ADC0_ADRD_RIGHT_DIAGST_Msk       (0xc000UL)  /*!< DIAGST (Bitfield-Mask: 0x03)                          */
+ #define R_ADC0_ADRD_RIGHT_AD_Pos           (0UL)       /*!< AD (Bit 0)                                            */
+ #define R_ADC0_ADRD_RIGHT_AD_Msk           (0x3fffUL)  /*!< AD (Bitfield-Mask: 0x3fff)                            */
+/* =======================================================  ADRD_LEFT  ======================================================= */
+ #define R_ADC0_ADRD_LEFT_AD_Pos            (2UL)       /*!< AD (Bit 2)                                            */
+ #define R_ADC0_ADRD_LEFT_AD_Msk            (0xfffcUL)  /*!< AD (Bitfield-Mask: 0x3fff)                            */
+ #define R_ADC0_ADRD_LEFT_DIAGST_Pos        (0UL)       /*!< DIAGST (Bit 0)                                        */
+ #define R_ADC0_ADRD_LEFT_DIAGST_Msk        (0x3UL)     /*!< DIAGST (Bitfield-Mask: 0x03)                          */
+/* =========================================================  ADDR  ========================================================== */
+ #define R_ADC0_ADDR_ADDR_Pos               (0UL)       /*!< ADDR (Bit 0)                                          */
+ #define R_ADC0_ADDR_ADDR_Msk               (0xffffUL)  /*!< ADDR (Bitfield-Mask: 0xffff)                          */
+/* ========================================================  ADSHCR  ========================================================= */
+ #define R_ADC0_ADSHCR_SHANS2_Pos           (10UL)      /*!< SHANS2 (Bit 10)                                       */
+ #define R_ADC0_ADSHCR_SHANS2_Msk           (0x400UL)   /*!< SHANS2 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSHCR_SHANS1_Pos           (9UL)       /*!< SHANS1 (Bit 9)                                        */
+ #define R_ADC0_ADSHCR_SHANS1_Msk           (0x200UL)   /*!< SHANS1 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSHCR_SHANS0_Pos           (8UL)       /*!< SHANS0 (Bit 8)                                        */
+ #define R_ADC0_ADSHCR_SHANS0_Msk           (0x100UL)   /*!< SHANS0 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSHCR_SSTSH_Pos            (0UL)       /*!< SSTSH (Bit 0)                                         */
+ #define R_ADC0_ADSHCR_SSTSH_Msk            (0xffUL)    /*!< SSTSH (Bitfield-Mask: 0xff)                           */
+/* ========================================================  ADDISCR  ======================================================== */
+ #define R_ADC0_ADDISCR_CHARGE_Pos          (4UL)       /*!< CHARGE (Bit 4)                                        */
+ #define R_ADC0_ADDISCR_CHARGE_Msk          (0x10UL)    /*!< CHARGE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADDISCR_ADNDIS_Pos          (0UL)       /*!< ADNDIS (Bit 0)                                        */
+ #define R_ADC0_ADDISCR_ADNDIS_Msk          (0xfUL)     /*!< ADNDIS (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  ADSHMSR  ======================================================== */
+ #define R_ADC0_ADSHMSR_SHMD_Pos            (0UL)       /*!< SHMD (Bit 0)                                          */
+ #define R_ADC0_ADSHMSR_SHMD_Msk            (0x1UL)     /*!< SHMD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  ADACSR  ========================================================= */
+ #define R_ADC0_ADACSR_ADSAC_Pos            (1UL)       /*!< ADSAC (Bit 1)                                         */
+ #define R_ADC0_ADACSR_ADSAC_Msk            (0x2UL)     /*!< ADSAC (Bitfield-Mask: 0x01)                           */
+/* ========================================================  ADGSPCR  ======================================================== */
+ #define R_ADC0_ADGSPCR_GBRP_Pos            (15UL)      /*!< GBRP (Bit 15)                                         */
+ #define R_ADC0_ADGSPCR_GBRP_Msk            (0x8000UL)  /*!< GBRP (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADGSPCR_GBRSCN_Pos          (1UL)       /*!< GBRSCN (Bit 1)                                        */
+ #define R_ADC0_ADGSPCR_GBRSCN_Msk          (0x2UL)     /*!< GBRSCN (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADGSPCR_PGS_Pos             (0UL)       /*!< PGS (Bit 0)                                           */
+ #define R_ADC0_ADGSPCR_PGS_Msk             (0x1UL)     /*!< PGS (Bitfield-Mask: 0x01)                             */
+ #define R_ADC0_ADGSPCR_GBEXTRG_Pos         (8UL)       /*!< GBEXTRG (Bit 8)                                       */
+ #define R_ADC0_ADGSPCR_GBEXTRG_Msk         (0x100UL)   /*!< GBEXTRG (Bitfield-Mask: 0x01)                         */
+/* =========================================================  ADICR  ========================================================= */
+ #define R_ADC0_ADICR_ADIC_Pos              (0UL)       /*!< ADIC (Bit 0)                                          */
+ #define R_ADC0_ADICR_ADIC_Msk              (0x3UL)     /*!< ADIC (Bitfield-Mask: 0x03)                            */
+/* =======================================================  ADDBLDRA  ======================================================== */
+ #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos       (0UL)       /*!< ADDBLDRA (Bit 0)                                      */
+ #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk       (0xffffUL)  /*!< ADDBLDRA (Bitfield-Mask: 0xffff)                      */
+/* =======================================================  ADDBLDRB  ======================================================== */
+ #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos       (0UL)       /*!< ADDBLDRB (Bit 0)                                      */
+ #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk       (0xffffUL)  /*!< ADDBLDRB (Bitfield-Mask: 0xffff)                      */
+/* ======================================================  ADHVREFCNT  ======================================================= */
+ #define R_ADC0_ADHVREFCNT_ADSLP_Pos        (7UL)       /*!< ADSLP (Bit 7)                                         */
+ #define R_ADC0_ADHVREFCNT_ADSLP_Msk        (0x80UL)    /*!< ADSLP (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADHVREFCNT_LVSEL_Pos        (4UL)       /*!< LVSEL (Bit 4)                                         */
+ #define R_ADC0_ADHVREFCNT_LVSEL_Msk        (0x10UL)    /*!< LVSEL (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADHVREFCNT_HVSEL_Pos        (0UL)       /*!< HVSEL (Bit 0)                                         */
+ #define R_ADC0_ADHVREFCNT_HVSEL_Msk        (0x3UL)     /*!< HVSEL (Bitfield-Mask: 0x03)                           */
+/* =======================================================  ADWINMON  ======================================================== */
+ #define R_ADC0_ADWINMON_MONCMPB_Pos        (5UL)       /*!< MONCMPB (Bit 5)                                       */
+ #define R_ADC0_ADWINMON_MONCMPB_Msk        (0x20UL)    /*!< MONCMPB (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADWINMON_MONCMPA_Pos        (4UL)       /*!< MONCMPA (Bit 4)                                       */
+ #define R_ADC0_ADWINMON_MONCMPA_Msk        (0x10UL)    /*!< MONCMPA (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADWINMON_MONCOMB_Pos        (0UL)       /*!< MONCOMB (Bit 0)                                       */
+ #define R_ADC0_ADWINMON_MONCOMB_Msk        (0x1UL)     /*!< MONCOMB (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ADCMPCR  ======================================================== */
+ #define R_ADC0_ADCMPCR_CMPAIE_Pos          (15UL)      /*!< CMPAIE (Bit 15)                                       */
+ #define R_ADC0_ADCMPCR_CMPAIE_Msk          (0x8000UL)  /*!< CMPAIE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCMPCR_WCMPE_Pos           (14UL)      /*!< WCMPE (Bit 14)                                        */
+ #define R_ADC0_ADCMPCR_WCMPE_Msk           (0x4000UL)  /*!< WCMPE (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCMPCR_CMPBIE_Pos          (13UL)      /*!< CMPBIE (Bit 13)                                       */
+ #define R_ADC0_ADCMPCR_CMPBIE_Msk          (0x2000UL)  /*!< CMPBIE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCMPCR_CMPAE_Pos           (11UL)      /*!< CMPAE (Bit 11)                                        */
+ #define R_ADC0_ADCMPCR_CMPAE_Msk           (0x800UL)   /*!< CMPAE (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCMPCR_CMPBE_Pos           (9UL)       /*!< CMPBE (Bit 9)                                         */
+ #define R_ADC0_ADCMPCR_CMPBE_Msk           (0x200UL)   /*!< CMPBE (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCMPCR_CMPAB_Pos           (0UL)       /*!< CMPAB (Bit 0)                                         */
+ #define R_ADC0_ADCMPCR_CMPAB_Msk           (0x3UL)     /*!< CMPAB (Bitfield-Mask: 0x03)                           */
+/* ======================================================  ADCMPANSER  ======================================================= */
+ #define R_ADC0_ADCMPANSER_CMPOCA_Pos       (1UL)       /*!< CMPOCA (Bit 1)                                        */
+ #define R_ADC0_ADCMPANSER_CMPOCA_Msk       (0x2UL)     /*!< CMPOCA (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCMPANSER_CMPTSA_Pos       (0UL)       /*!< CMPTSA (Bit 0)                                        */
+ #define R_ADC0_ADCMPANSER_CMPTSA_Msk       (0x1UL)     /*!< CMPTSA (Bitfield-Mask: 0x01)                          */
+/* =======================================================  ADCMPLER  ======================================================== */
+ #define R_ADC0_ADCMPLER_CMPLOCA_Pos        (1UL)       /*!< CMPLOCA (Bit 1)                                       */
+ #define R_ADC0_ADCMPLER_CMPLOCA_Msk        (0x2UL)     /*!< CMPLOCA (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADCMPLER_CMPLTSA_Pos        (0UL)       /*!< CMPLTSA (Bit 0)                                       */
+ #define R_ADC0_ADCMPLER_CMPLTSA_Msk        (0x1UL)     /*!< CMPLTSA (Bitfield-Mask: 0x01)                         */
+/* =======================================================  ADCMPANSR  ======================================================= */
+ #define R_ADC0_ADCMPANSR_CMPCHA_Pos        (0UL)       /*!< CMPCHA (Bit 0)                                        */
+ #define R_ADC0_ADCMPANSR_CMPCHA_Msk        (0x1UL)     /*!< CMPCHA (Bitfield-Mask: 0x01)                          */
+/* ========================================================  ADCMPLR  ======================================================== */
+ #define R_ADC0_ADCMPLR_CMPLCHA_Pos         (0UL)       /*!< CMPLCHA (Bit 0)                                       */
+ #define R_ADC0_ADCMPLR_CMPLCHA_Msk         (0x1UL)     /*!< CMPLCHA (Bitfield-Mask: 0x01)                         */
+/* =======================================================  ADCMPDR0  ======================================================== */
+ #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos       (0UL)       /*!< ADCMPDR0 (Bit 0)                                      */
+ #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk       (0xffffUL)  /*!< ADCMPDR0 (Bitfield-Mask: 0xffff)                      */
+/* =======================================================  ADCMPDR1  ======================================================== */
+ #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos       (0UL)       /*!< ADCMPDR1 (Bit 0)                                      */
+ #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk       (0xffffUL)  /*!< ADCMPDR1 (Bitfield-Mask: 0xffff)                      */
+/* ========================================================  ADCMPSR  ======================================================== */
+ #define R_ADC0_ADCMPSR_CMPSTCHA_Pos        (0UL)       /*!< CMPSTCHA (Bit 0)                                      */
+ #define R_ADC0_ADCMPSR_CMPSTCHA_Msk        (0x1UL)     /*!< CMPSTCHA (Bitfield-Mask: 0x01)                        */
+/* =======================================================  ADCMPSER  ======================================================== */
+ #define R_ADC0_ADCMPSER_CMPSTOCA_Pos       (1UL)       /*!< CMPSTOCA (Bit 1)                                      */
+ #define R_ADC0_ADCMPSER_CMPSTOCA_Msk       (0x2UL)     /*!< CMPSTOCA (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADCMPSER_CMPSTTSA_Pos       (0UL)       /*!< CMPSTTSA (Bit 0)                                      */
+ #define R_ADC0_ADCMPSER_CMPSTTSA_Msk       (0x1UL)     /*!< CMPSTTSA (Bitfield-Mask: 0x01)                        */
+/* =======================================================  ADCMPBNSR  ======================================================= */
+ #define R_ADC0_ADCMPBNSR_CMPLB_Pos         (7UL)       /*!< CMPLB (Bit 7)                                         */
+ #define R_ADC0_ADCMPBNSR_CMPLB_Msk         (0x80UL)    /*!< CMPLB (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCMPBNSR_CMPCHB_Pos        (0UL)       /*!< CMPCHB (Bit 0)                                        */
+ #define R_ADC0_ADCMPBNSR_CMPCHB_Msk        (0x3fUL)    /*!< CMPCHB (Bitfield-Mask: 0x3f)                          */
+/* =======================================================  ADWINLLB  ======================================================== */
+ #define R_ADC0_ADWINLLB_ADWINLLB_Pos       (0UL)       /*!< ADWINLLB (Bit 0)                                      */
+ #define R_ADC0_ADWINLLB_ADWINLLB_Msk       (0xffffUL)  /*!< ADWINLLB (Bitfield-Mask: 0xffff)                      */
+/* =======================================================  ADWINULB  ======================================================== */
+ #define R_ADC0_ADWINULB_ADWINULB_Pos       (0UL)       /*!< ADWINULB (Bit 0)                                      */
+ #define R_ADC0_ADWINULB_ADWINULB_Msk       (0xffffUL)  /*!< ADWINULB (Bitfield-Mask: 0xffff)                      */
+/* =======================================================  ADCMPBSR  ======================================================== */
+ #define R_ADC0_ADCMPBSR_CMPSTB_Pos         (0UL)       /*!< CMPSTB (Bit 0)                                        */
+ #define R_ADC0_ADCMPBSR_CMPSTB_Msk         (0x1UL)     /*!< CMPSTB (Bitfield-Mask: 0x01)                          */
+/* ========================================================  ADSSTRL  ======================================================== */
+ #define R_ADC0_ADSSTRL_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
+ #define R_ADC0_ADSSTRL_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
+/* ========================================================  ADSSTRT  ======================================================== */
+ #define R_ADC0_ADSSTRT_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
+ #define R_ADC0_ADSSTRT_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
+/* ========================================================  ADSSTRO  ======================================================== */
+ #define R_ADC0_ADSSTRO_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
+ #define R_ADC0_ADSSTRO_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
+/* ========================================================  ADSSTR  ========================================================= */
+ #define R_ADC0_ADSSTR_SST_Pos              (0UL)       /*!< SST (Bit 0)                                           */
+ #define R_ADC0_ADSSTR_SST_Msk              (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
+/* ========================================================  ADPGACR  ======================================================== */
+ #define R_ADC0_ADPGACR_P002GEN_Pos         (11UL)      /*!< P002GEN (Bit 11)                                      */
+ #define R_ADC0_ADPGACR_P002GEN_Msk         (0x800UL)   /*!< P002GEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADPGACR_P002ENAMP_Pos       (10UL)      /*!< P002ENAMP (Bit 10)                                    */
+ #define R_ADC0_ADPGACR_P002ENAMP_Msk       (0x400UL)   /*!< P002ENAMP (Bitfield-Mask: 0x01)                       */
+ #define R_ADC0_ADPGACR_P002SEL1_Pos        (9UL)       /*!< P002SEL1 (Bit 9)                                      */
+ #define R_ADC0_ADPGACR_P002SEL1_Msk        (0x200UL)   /*!< P002SEL1 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P002SEL0_Pos        (8UL)       /*!< P002SEL0 (Bit 8)                                      */
+ #define R_ADC0_ADPGACR_P002SEL0_Msk        (0x100UL)   /*!< P002SEL0 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P001GEN_Pos         (7UL)       /*!< P001GEN (Bit 7)                                       */
+ #define R_ADC0_ADPGACR_P001GEN_Msk         (0x80UL)    /*!< P001GEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADPGACR_P001ENAMP_Pos       (6UL)       /*!< P001ENAMP (Bit 6)                                     */
+ #define R_ADC0_ADPGACR_P001ENAMP_Msk       (0x40UL)    /*!< P001ENAMP (Bitfield-Mask: 0x01)                       */
+ #define R_ADC0_ADPGACR_P001SEL1_Pos        (5UL)       /*!< P001SEL1 (Bit 5)                                      */
+ #define R_ADC0_ADPGACR_P001SEL1_Msk        (0x20UL)    /*!< P001SEL1 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P001SEL0_Pos        (4UL)       /*!< P001SEL0 (Bit 4)                                      */
+ #define R_ADC0_ADPGACR_P001SEL0_Msk        (0x10UL)    /*!< P001SEL0 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P000GEN_Pos         (3UL)       /*!< P000GEN (Bit 3)                                       */
+ #define R_ADC0_ADPGACR_P000GEN_Msk         (0x8UL)     /*!< P000GEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADPGACR_P000ENAMP_Pos       (2UL)       /*!< P000ENAMP (Bit 2)                                     */
+ #define R_ADC0_ADPGACR_P000ENAMP_Msk       (0x4UL)     /*!< P000ENAMP (Bitfield-Mask: 0x01)                       */
+ #define R_ADC0_ADPGACR_P000SEL1_Pos        (1UL)       /*!< P000SEL1 (Bit 1)                                      */
+ #define R_ADC0_ADPGACR_P000SEL1_Msk        (0x2UL)     /*!< P000SEL1 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P000SEL0_Pos        (0UL)       /*!< P000SEL0 (Bit 0)                                      */
+ #define R_ADC0_ADPGACR_P000SEL0_Msk        (0x1UL)     /*!< P000SEL0 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P003SEL0_Pos        (12UL)      /*!< P003SEL0 (Bit 12)                                     */
+ #define R_ADC0_ADPGACR_P003SEL0_Msk        (0x1000UL)  /*!< P003SEL0 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P003SEL1_Pos        (13UL)      /*!< P003SEL1 (Bit 13)                                     */
+ #define R_ADC0_ADPGACR_P003SEL1_Msk        (0x2000UL)  /*!< P003SEL1 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P003ENAMP_Pos       (14UL)      /*!< P003ENAMP (Bit 14)                                    */
+ #define R_ADC0_ADPGACR_P003ENAMP_Msk       (0x4000UL)  /*!< P003ENAMP (Bitfield-Mask: 0x01)                       */
+ #define R_ADC0_ADPGACR_P003GEN_Pos         (15UL)      /*!< P003GEN (Bit 15)                                      */
+ #define R_ADC0_ADPGACR_P003GEN_Msk         (0x8000UL)  /*!< P003GEN (Bitfield-Mask: 0x01)                         */
+/* =========================================================  ADRD  ========================================================== */
+ #define R_ADC0_ADRD_AD_Pos                 (0UL)       /*!< AD (Bit 0)                                            */
+ #define R_ADC0_ADRD_AD_Msk                 (0xffffUL)  /*!< AD (Bitfield-Mask: 0xffff)                            */
+/* =========================================================  ADRST  ========================================================= */
+ #define R_ADC0_ADRST_DIAGST_Pos            (0UL)       /*!< DIAGST (Bit 0)                                        */
+ #define R_ADC0_ADRST_DIAGST_Msk            (0x3UL)     /*!< DIAGST (Bitfield-Mask: 0x03)                          */
+/* ======================================================  VREFAMPCNT  ======================================================= */
+ #define R_ADC0_VREFAMPCNT_VREFADCG_Pos     (1UL)       /*!< VREFADCG (Bit 1)                                      */
+ #define R_ADC0_VREFAMPCNT_VREFADCG_Msk     (0x6UL)     /*!< VREFADCG (Bitfield-Mask: 0x03)                        */
+ #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos    (3UL)       /*!< VREFADCEN (Bit 3)                                     */
+ #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk    (0x8UL)     /*!< VREFADCEN (Bitfield-Mask: 0x01)                       */
+ #define R_ADC0_VREFAMPCNT_ADSLP_Pos        (7UL)       /*!< ADSLP (Bit 7)                                         */
+ #define R_ADC0_VREFAMPCNT_ADSLP_Msk        (0x80UL)    /*!< ADSLP (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_VREFAMPCNT_OLDETEN_Pos      (0UL)       /*!< OLDETEN (Bit 0)                                       */
+ #define R_ADC0_VREFAMPCNT_OLDETEN_Msk      (0x1UL)     /*!< OLDETEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_VREFAMPCNT_BGREN_Pos        (4UL)       /*!< BGREN (Bit 4)                                         */
+ #define R_ADC0_VREFAMPCNT_BGREN_Msk        (0x10UL)    /*!< BGREN (Bitfield-Mask: 0x01)                           */
+/* =======================================================  ADCALEXE  ======================================================== */
+ #define R_ADC0_ADCALEXE_CALEXE_Pos         (7UL)       /*!< CALEXE (Bit 7)                                        */
+ #define R_ADC0_ADCALEXE_CALEXE_Msk         (0x80UL)    /*!< CALEXE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCALEXE_CALMON_Pos         (6UL)       /*!< CALMON (Bit 6)                                        */
+ #define R_ADC0_ADCALEXE_CALMON_Msk         (0x40UL)    /*!< CALMON (Bitfield-Mask: 0x01)                          */
+/* ========================================================  ADANIM  ========================================================= */
+ #define R_ADC0_ADANIM_ANIM_Pos             (0UL)       /*!< ANIM (Bit 0)                                          */
+ #define R_ADC0_ADANIM_ANIM_Msk             (0x1UL)     /*!< ANIM (Bitfield-Mask: 0x01)                            */
+/* =======================================================  ADPGAGS0  ======================================================== */
+ #define R_ADC0_ADPGAGS0_P002GAIN_Pos       (8UL)       /*!< P002GAIN (Bit 8)                                      */
+ #define R_ADC0_ADPGAGS0_P002GAIN_Msk       (0xf00UL)   /*!< P002GAIN (Bitfield-Mask: 0x0f)                        */
+ #define R_ADC0_ADPGAGS0_P001GAIN_Pos       (4UL)       /*!< P001GAIN (Bit 4)                                      */
+ #define R_ADC0_ADPGAGS0_P001GAIN_Msk       (0xf0UL)    /*!< P001GAIN (Bitfield-Mask: 0x0f)                        */
+ #define R_ADC0_ADPGAGS0_P000GAIN_Pos       (0UL)       /*!< P000GAIN (Bit 0)                                      */
+ #define R_ADC0_ADPGAGS0_P000GAIN_Msk       (0xfUL)     /*!< P000GAIN (Bitfield-Mask: 0x0f)                        */
+ #define R_ADC0_ADPGAGS0_P003GAIN_Pos       (12UL)      /*!< P003GAIN (Bit 12)                                     */
+ #define R_ADC0_ADPGAGS0_P003GAIN_Msk       (0xf000UL)  /*!< P003GAIN (Bitfield-Mask: 0x0f)                        */
+/* =======================================================  ADPGADCR0  ======================================================= */
+ #define R_ADC0_ADPGADCR0_P003DG_Pos        (12UL)      /*!< P003DG (Bit 12)                                       */
+ #define R_ADC0_ADPGADCR0_P003DG_Msk        (0x3000UL)  /*!< P003DG (Bitfield-Mask: 0x03)                          */
+ #define R_ADC0_ADPGADCR0_P002DEN_Pos       (11UL)      /*!< P002DEN (Bit 11)                                      */
+ #define R_ADC0_ADPGADCR0_P002DEN_Msk       (0x800UL)   /*!< P002DEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADPGADCR0_P002DG_Pos        (8UL)       /*!< P002DG (Bit 8)                                        */
+ #define R_ADC0_ADPGADCR0_P002DG_Msk        (0x300UL)   /*!< P002DG (Bitfield-Mask: 0x03)                          */
+ #define R_ADC0_ADPGADCR0_P001DEN_Pos       (7UL)       /*!< P001DEN (Bit 7)                                       */
+ #define R_ADC0_ADPGADCR0_P001DEN_Msk       (0x80UL)    /*!< P001DEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADPGADCR0_P001DG_Pos        (4UL)       /*!< P001DG (Bit 4)                                        */
+ #define R_ADC0_ADPGADCR0_P001DG_Msk        (0x30UL)    /*!< P001DG (Bitfield-Mask: 0x03)                          */
+ #define R_ADC0_ADPGADCR0_P000DEN_Pos       (3UL)       /*!< P000DEN (Bit 3)                                       */
+ #define R_ADC0_ADPGADCR0_P000DEN_Msk       (0x8UL)     /*!< P000DEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADPGADCR0_P000DG_Pos        (0UL)       /*!< P000DG (Bit 0)                                        */
+ #define R_ADC0_ADPGADCR0_P000DG_Msk        (0x3UL)     /*!< P000DG (Bitfield-Mask: 0x03)                          */
+ #define R_ADC0_ADPGADCR0_P003DEN_Pos       (15UL)      /*!< P003DEN (Bit 15)                                      */
+ #define R_ADC0_ADPGADCR0_P003DEN_Msk       (0x8000UL)  /*!< P003DEN (Bitfield-Mask: 0x01)                         */
+/* =========================================================  ADREF  ========================================================= */
+ #define R_ADC0_ADREF_ADF_Pos               (0UL)       /*!< ADF (Bit 0)                                           */
+ #define R_ADC0_ADREF_ADF_Msk               (0x1UL)     /*!< ADF (Bitfield-Mask: 0x01)                             */
+ #define R_ADC0_ADREF_ADSCACT_Pos           (7UL)       /*!< ADSCACT (Bit 7)                                       */
+ #define R_ADC0_ADREF_ADSCACT_Msk           (0x80UL)    /*!< ADSCACT (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ADEXREF  ======================================================== */
+ #define R_ADC0_ADEXREF_GBADF_Pos           (0UL)       /*!< GBADF (Bit 0)                                         */
+ #define R_ADC0_ADEXREF_GBADF_Msk           (0x1UL)     /*!< GBADF (Bitfield-Mask: 0x01)                           */
+/* =======================================================  ADAMPOFF  ======================================================== */
+ #define R_ADC0_ADAMPOFF_OPOFF_Pos          (0UL)       /*!< OPOFF (Bit 0)                                         */
+ #define R_ADC0_ADAMPOFF_OPOFF_Msk          (0xffUL)    /*!< OPOFF (Bitfield-Mask: 0xff)                           */
+/* ========================================================  ADTSTPR  ======================================================== */
+ #define R_ADC0_ADTSTPR_PRO_Pos             (0UL)       /*!< PRO (Bit 0)                                           */
+ #define R_ADC0_ADTSTPR_PRO_Msk             (0x1UL)     /*!< PRO (Bitfield-Mask: 0x01)                             */
+ #define R_ADC0_ADTSTPR_B0WI_Pos            (1UL)       /*!< B0WI (Bit 1)                                          */
+ #define R_ADC0_ADTSTPR_B0WI_Msk            (0x2UL)     /*!< B0WI (Bitfield-Mask: 0x01)                            */
+/* =======================================================  ADDDACER  ======================================================== */
+ #define R_ADC0_ADDDACER_WRION_Pos          (0UL)       /*!< WRION (Bit 0)                                         */
+ #define R_ADC0_ADDDACER_WRION_Msk          (0x1fUL)    /*!< WRION (Bitfield-Mask: 0x1f)                           */
+ #define R_ADC0_ADDDACER_WRIOFF_Pos         (8UL)       /*!< WRIOFF (Bit 8)                                        */
+ #define R_ADC0_ADDDACER_WRIOFF_Msk         (0x1f00UL)  /*!< WRIOFF (Bitfield-Mask: 0x1f)                          */
+ #define R_ADC0_ADDDACER_ADHS_Pos           (15UL)      /*!< ADHS (Bit 15)                                         */
+ #define R_ADC0_ADDDACER_ADHS_Msk           (0x8000UL)  /*!< ADHS (Bitfield-Mask: 0x01)                            */
+/* =======================================================  ADEXTSTR  ======================================================== */
+ #define R_ADC0_ADEXTSTR_SHTEST_Pos         (0UL)       /*!< SHTEST (Bit 0)                                        */
+ #define R_ADC0_ADEXTSTR_SHTEST_Msk         (0x7UL)     /*!< SHTEST (Bitfield-Mask: 0x07)                          */
+ #define R_ADC0_ADEXTSTR_SWTST_Pos          (4UL)       /*!< SWTST (Bit 4)                                         */
+ #define R_ADC0_ADEXTSTR_SWTST_Msk          (0x30UL)    /*!< SWTST (Bitfield-Mask: 0x03)                           */
+ #define R_ADC0_ADEXTSTR_SHTRM_Pos          (8UL)       /*!< SHTRM (Bit 8)                                         */
+ #define R_ADC0_ADEXTSTR_SHTRM_Msk          (0x300UL)   /*!< SHTRM (Bitfield-Mask: 0x03)                           */
+ #define R_ADC0_ADEXTSTR_ADTRM3_Pos         (11UL)      /*!< ADTRM3 (Bit 11)                                       */
+ #define R_ADC0_ADEXTSTR_ADTRM3_Msk         (0x800UL)   /*!< ADTRM3 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADEXTSTR_ADTRM2_Pos         (12UL)      /*!< ADTRM2 (Bit 12)                                       */
+ #define R_ADC0_ADEXTSTR_ADTRM2_Msk         (0x3000UL)  /*!< ADTRM2 (Bitfield-Mask: 0x03)                          */
+ #define R_ADC0_ADEXTSTR_ADTRM1_Pos         (14UL)      /*!< ADTRM1 (Bit 14)                                       */
+ #define R_ADC0_ADEXTSTR_ADTRM1_Msk         (0xc000UL)  /*!< ADTRM1 (Bitfield-Mask: 0x03)                          */
+/* ========================================================  ADTSTRA  ======================================================== */
+ #define R_ADC0_ADTSTRA_ATBUSSEL_Pos        (0UL)       /*!< ATBUSSEL (Bit 0)                                      */
+ #define R_ADC0_ADTSTRA_ATBUSSEL_Msk        (0x1UL)     /*!< ATBUSSEL (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADTSTRA_TSTSWREF_Pos        (1UL)       /*!< TSTSWREF (Bit 1)                                      */
+ #define R_ADC0_ADTSTRA_TSTSWREF_Msk        (0xeUL)     /*!< TSTSWREF (Bitfield-Mask: 0x07)                        */
+ #define R_ADC0_ADTSTRA_OCSW_Pos            (5UL)       /*!< OCSW (Bit 5)                                          */
+ #define R_ADC0_ADTSTRA_OCSW_Msk            (0x20UL)    /*!< OCSW (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADTSTRA_TSSW_Pos            (6UL)       /*!< TSSW (Bit 6)                                          */
+ #define R_ADC0_ADTSTRA_TSSW_Msk            (0x40UL)    /*!< TSSW (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADTSTRA_ADTEST_AD_Pos       (8UL)       /*!< ADTEST_AD (Bit 8)                                     */
+ #define R_ADC0_ADTSTRA_ADTEST_AD_Msk       (0xf00UL)   /*!< ADTEST_AD (Bitfield-Mask: 0x0f)                       */
+ #define R_ADC0_ADTSTRA_ADTEST_IO_Pos       (12UL)      /*!< ADTEST_IO (Bit 12)                                    */
+ #define R_ADC0_ADTSTRA_ADTEST_IO_Msk       (0xf000UL)  /*!< ADTEST_IO (Bitfield-Mask: 0x0f)                       */
+/* ========================================================  ADTSTRB  ======================================================== */
+ #define R_ADC0_ADTSTRB_ADVAL_Pos           (0UL)       /*!< ADVAL (Bit 0)                                         */
+ #define R_ADC0_ADTSTRB_ADVAL_Msk           (0x7fffUL)  /*!< ADVAL (Bitfield-Mask: 0x7fff)                         */
+/* ========================================================  ADTSTRC  ======================================================== */
+ #define R_ADC0_ADTSTRC_ADMD_Pos            (0UL)       /*!< ADMD (Bit 0)                                          */
+ #define R_ADC0_ADTSTRC_ADMD_Msk            (0xffUL)    /*!< ADMD (Bitfield-Mask: 0xff)                            */
+ #define R_ADC0_ADTSTRC_SYNCERR_Pos         (12UL)      /*!< SYNCERR (Bit 12)                                      */
+ #define R_ADC0_ADTSTRC_SYNCERR_Msk         (0x1000UL)  /*!< SYNCERR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ADTSTRD  ======================================================== */
+ #define R_ADC0_ADTSTRD_ADVAL16_Pos         (0UL)       /*!< ADVAL16 (Bit 0)                                       */
+ #define R_ADC0_ADTSTRD_ADVAL16_Msk         (0x1UL)     /*!< ADVAL16 (Bitfield-Mask: 0x01)                         */
+/* =======================================================  ADSWTSTR0  ======================================================= */
+ #define R_ADC0_ADSWTSTR0_CHSW00_Pos        (0UL)       /*!< CHSW00 (Bit 0)                                        */
+ #define R_ADC0_ADSWTSTR0_CHSW00_Msk        (0x1UL)     /*!< CHSW00 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR0_CHSW01_Pos        (1UL)       /*!< CHSW01 (Bit 1)                                        */
+ #define R_ADC0_ADSWTSTR0_CHSW01_Msk        (0x2UL)     /*!< CHSW01 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR0_CHSW02_Pos        (2UL)       /*!< CHSW02 (Bit 2)                                        */
+ #define R_ADC0_ADSWTSTR0_CHSW02_Msk        (0x4UL)     /*!< CHSW02 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR0_CHSW03_Pos        (3UL)       /*!< CHSW03 (Bit 3)                                        */
+ #define R_ADC0_ADSWTSTR0_CHSW03_Msk        (0x8UL)     /*!< CHSW03 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR0_CHSW04_Pos        (4UL)       /*!< CHSW04 (Bit 4)                                        */
+ #define R_ADC0_ADSWTSTR0_CHSW04_Msk        (0x10UL)    /*!< CHSW04 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR0_CHSW05_Pos        (5UL)       /*!< CHSW05 (Bit 5)                                        */
+ #define R_ADC0_ADSWTSTR0_CHSW05_Msk        (0x20UL)    /*!< CHSW05 (Bitfield-Mask: 0x01)                          */
+/* =======================================================  ADSWTSTR1  ======================================================= */
+ #define R_ADC0_ADSWTSTR1_CHSW16_Pos        (0UL)       /*!< CHSW16 (Bit 0)                                        */
+ #define R_ADC0_ADSWTSTR1_CHSW16_Msk        (0x1UL)     /*!< CHSW16 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR1_CHSW17_Pos        (1UL)       /*!< CHSW17 (Bit 1)                                        */
+ #define R_ADC0_ADSWTSTR1_CHSW17_Msk        (0x2UL)     /*!< CHSW17 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR1_CHSW18_Pos        (2UL)       /*!< CHSW18 (Bit 2)                                        */
+ #define R_ADC0_ADSWTSTR1_CHSW18_Msk        (0x4UL)     /*!< CHSW18 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR1_CHSW19_Pos        (3UL)       /*!< CHSW19 (Bit 3)                                        */
+ #define R_ADC0_ADSWTSTR1_CHSW19_Msk        (0x8UL)     /*!< CHSW19 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR1_CHSW20_Pos        (4UL)       /*!< CHSW20 (Bit 4)                                        */
+ #define R_ADC0_ADSWTSTR1_CHSW20_Msk        (0x10UL)    /*!< CHSW20 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR1_CHSW21_Pos        (5UL)       /*!< CHSW21 (Bit 5)                                        */
+ #define R_ADC0_ADSWTSTR1_CHSW21_Msk        (0x20UL)    /*!< CHSW21 (Bitfield-Mask: 0x01)                          */
+/* =======================================================  ADSWTSTR2  ======================================================= */
+ #define R_ADC0_ADSWTSTR2_EX0SW_Pos         (0UL)       /*!< EX0SW (Bit 0)                                         */
+ #define R_ADC0_ADSWTSTR2_EX0SW_Msk         (0x1UL)     /*!< EX0SW (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADSWTSTR2_EX1SW_Pos         (1UL)       /*!< EX1SW (Bit 1)                                         */
+ #define R_ADC0_ADSWTSTR2_EX1SW_Msk         (0x2UL)     /*!< EX1SW (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos       (4UL)       /*!< SHBYPS0 (Bit 4)                                       */
+ #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk       (0x10UL)    /*!< SHBYPS0 (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos       (5UL)       /*!< SHBYPS1 (Bit 5)                                       */
+ #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk       (0x20UL)    /*!< SHBYPS1 (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos       (6UL)       /*!< SHBYPS2 (Bit 6)                                       */
+ #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk       (0x40UL)    /*!< SHBYPS2 (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADSWTSTR2_GRP0SW_Pos        (8UL)       /*!< GRP0SW (Bit 8)                                        */
+ #define R_ADC0_ADSWTSTR2_GRP0SW_Msk        (0x100UL)   /*!< GRP0SW (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR2_GRP1SW_Pos        (9UL)       /*!< GRP1SW (Bit 9)                                        */
+ #define R_ADC0_ADSWTSTR2_GRP1SW_Msk        (0x200UL)   /*!< GRP1SW (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR2_GRP2SW_Pos        (10UL)      /*!< GRP2SW (Bit 10)                                       */
+ #define R_ADC0_ADSWTSTR2_GRP2SW_Msk        (0x400UL)   /*!< GRP2SW (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR2_GRP3SW_Pos        (11UL)      /*!< GRP3SW (Bit 11)                                       */
+ #define R_ADC0_ADSWTSTR2_GRP3SW_Msk        (0x800UL)   /*!< GRP3SW (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos      (12UL)      /*!< GRPEX1SW (Bit 12)                                     */
+ #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk      (0x1000UL)  /*!< GRPEX1SW (Bitfield-Mask: 0x01)                        */
+/* ========================================================  ADSWCR  ========================================================= */
+ #define R_ADC0_ADSWCR_ADSWREF_Pos          (0UL)       /*!< ADSWREF (Bit 0)                                       */
+ #define R_ADC0_ADSWCR_ADSWREF_Msk          (0x7UL)     /*!< ADSWREF (Bitfield-Mask: 0x07)                         */
+ #define R_ADC0_ADSWCR_SHSWREF_Pos          (4UL)       /*!< SHSWREF (Bit 4)                                       */
+ #define R_ADC0_ADSWCR_SHSWREF_Msk          (0x70UL)    /*!< SHSWREF (Bitfield-Mask: 0x07)                         */
+/* ========================================================  ADGSCS  ========================================================= */
+ #define R_ADC0_ADGSCS_CHSELGB_Pos          (0UL)       /*!< CHSELGB (Bit 0)                                       */
+ #define R_ADC0_ADGSCS_CHSELGB_Msk          (0xffUL)    /*!< CHSELGB (Bitfield-Mask: 0xff)                         */
+ #define R_ADC0_ADGSCS_CHSELGA_Pos          (8UL)       /*!< CHSELGA (Bit 8)                                       */
+ #define R_ADC0_ADGSCS_CHSELGA_Msk          (0xff00UL)  /*!< CHSELGA (Bitfield-Mask: 0xff)                         */
+/* =========================================================  ADSER  ========================================================= */
+ #define R_ADC0_ADSER_SMPEX_Pos             (7UL)       /*!< SMPEX (Bit 7)                                         */
+ #define R_ADC0_ADSER_SMPEX_Msk             (0x80UL)    /*!< SMPEX (Bitfield-Mask: 0x01)                           */
+/* ========================================================  ADBUF0  ========================================================= */
+ #define R_ADC0_ADBUF0_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF0_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF1  ========================================================= */
+ #define R_ADC0_ADBUF1_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF1_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF2  ========================================================= */
+ #define R_ADC0_ADBUF2_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF2_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF3  ========================================================= */
+ #define R_ADC0_ADBUF3_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF3_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF4  ========================================================= */
+ #define R_ADC0_ADBUF4_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF4_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF5  ========================================================= */
+ #define R_ADC0_ADBUF5_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF5_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF6  ========================================================= */
+ #define R_ADC0_ADBUF6_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF6_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF7  ========================================================= */
+ #define R_ADC0_ADBUF7_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF7_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF8  ========================================================= */
+ #define R_ADC0_ADBUF8_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF8_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF9  ========================================================= */
+ #define R_ADC0_ADBUF9_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF9_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF10  ======================================================== */
+ #define R_ADC0_ADBUF10_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF10_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF11  ======================================================== */
+ #define R_ADC0_ADBUF11_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF11_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF12  ======================================================== */
+ #define R_ADC0_ADBUF12_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF12_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF13  ======================================================== */
+ #define R_ADC0_ADBUF13_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF13_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF14  ======================================================== */
+ #define R_ADC0_ADBUF14_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF14_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUF15  ======================================================== */
+ #define R_ADC0_ADBUF15_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
+ #define R_ADC0_ADBUF15_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ADBUFEN  ======================================================== */
+ #define R_ADC0_ADBUFEN_BUFEN_Pos           (0UL)       /*!< BUFEN (Bit 0)                                         */
+ #define R_ADC0_ADBUFEN_BUFEN_Msk           (0x1UL)     /*!< BUFEN (Bitfield-Mask: 0x01)                           */
+/* =======================================================  ADBUFPTR  ======================================================== */
+ #define R_ADC0_ADBUFPTR_BUFPTR_Pos         (0UL)       /*!< BUFPTR (Bit 0)                                        */
+ #define R_ADC0_ADBUFPTR_BUFPTR_Msk         (0xfUL)     /*!< BUFPTR (Bitfield-Mask: 0x0f)                          */
+ #define R_ADC0_ADBUFPTR_PTROVF_Pos         (4UL)       /*!< PTROVF (Bit 4)                                        */
+ #define R_ADC0_ADBUFPTR_PTROVF_Msk         (0x10UL)    /*!< PTROVF (Bitfield-Mask: 0x01)                          */
+/* =======================================================  ADPGADBS0  ======================================================= */
+ #define R_ADC0_ADPGADBS0_P0BIAS_Pos        (0UL)       /*!< P0BIAS (Bit 0)                                        */
+ #define R_ADC0_ADPGADBS0_P0BIAS_Msk        (0x1UL)     /*!< P0BIAS (Bitfield-Mask: 0x01)                          */
+/* =======================================================  ADPGADBS1  ======================================================= */
+ #define R_ADC0_ADPGADBS1_P3BIAS_Pos        (0UL)       /*!< P3BIAS (Bit 0)                                        */
+ #define R_ADC0_ADPGADBS1_P3BIAS_Msk        (0x1UL)     /*!< P3BIAS (Bitfield-Mask: 0x01)                          */
+/* =======================================================  ADREFMON  ======================================================== */
+ #define R_ADC0_ADREFMON_PGAMON_Pos         (0UL)       /*!< PGAMON (Bit 0)                                        */
+ #define R_ADC0_ADREFMON_PGAMON_Msk         (0x7UL)     /*!< PGAMON (Bitfield-Mask: 0x07)                          */
+ #define R_ADC0_ADREFMON_MONSEL_Pos         (16UL)      /*!< MONSEL (Bit 16)                                       */
+ #define R_ADC0_ADREFMON_MONSEL_Msk         (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f)                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_PSCU                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  PSARB  ========================================================= */
+ #define R_PSCU_PSARB_PSARB1_Pos     (1UL)          /*!< PSARB1 (Bit 1)                                        */
+ #define R_PSCU_PSARB_PSARB1_Msk     (0x2UL)        /*!< PSARB1 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARB_PSARB2_Pos     (2UL)          /*!< PSARB2 (Bit 2)                                        */
+ #define R_PSCU_PSARB_PSARB2_Msk     (0x4UL)        /*!< PSARB2 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARB_PSARB3_Pos     (3UL)          /*!< PSARB3 (Bit 3)                                        */
+ #define R_PSCU_PSARB_PSARB3_Msk     (0x8UL)        /*!< PSARB3 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARB_PSARB6_Pos     (6UL)          /*!< PSARB6 (Bit 6)                                        */
+ #define R_PSCU_PSARB_PSARB6_Msk     (0x40UL)       /*!< PSARB6 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARB_PSARB7_Pos     (7UL)          /*!< PSARB7 (Bit 7)                                        */
+ #define R_PSCU_PSARB_PSARB7_Msk     (0x80UL)       /*!< PSARB7 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARB_PSARB8_Pos     (8UL)          /*!< PSARB8 (Bit 8)                                        */
+ #define R_PSCU_PSARB_PSARB8_Msk     (0x100UL)      /*!< PSARB8 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARB_PSARB9_Pos     (9UL)          /*!< PSARB9 (Bit 9)                                        */
+ #define R_PSCU_PSARB_PSARB9_Msk     (0x200UL)      /*!< PSARB9 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARB_PSARB11_Pos    (11UL)         /*!< PSARB11 (Bit 11)                                      */
+ #define R_PSCU_PSARB_PSARB11_Msk    (0x800UL)      /*!< PSARB11 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB12_Pos    (12UL)         /*!< PSARB12 (Bit 12)                                      */
+ #define R_PSCU_PSARB_PSARB12_Msk    (0x1000UL)     /*!< PSARB12 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB15_Pos    (15UL)         /*!< PSARB15 (Bit 15)                                      */
+ #define R_PSCU_PSARB_PSARB15_Msk    (0x8000UL)     /*!< PSARB15 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB16_Pos    (16UL)         /*!< PSARB16 (Bit 16)                                      */
+ #define R_PSCU_PSARB_PSARB16_Msk    (0x10000UL)    /*!< PSARB16 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB18_Pos    (18UL)         /*!< PSARB18 (Bit 18)                                      */
+ #define R_PSCU_PSARB_PSARB18_Msk    (0x40000UL)    /*!< PSARB18 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB19_Pos    (19UL)         /*!< PSARB19 (Bit 19)                                      */
+ #define R_PSCU_PSARB_PSARB19_Msk    (0x80000UL)    /*!< PSARB19 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB22_Pos    (22UL)         /*!< PSARB22 (Bit 22)                                      */
+ #define R_PSCU_PSARB_PSARB22_Msk    (0x400000UL)   /*!< PSARB22 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB23_Pos    (23UL)         /*!< PSARB23 (Bit 23)                                      */
+ #define R_PSCU_PSARB_PSARB23_Msk    (0x800000UL)   /*!< PSARB23 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB24_Pos    (24UL)         /*!< PSARB24 (Bit 24)                                      */
+ #define R_PSCU_PSARB_PSARB24_Msk    (0x1000000UL)  /*!< PSARB24 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB25_Pos    (25UL)         /*!< PSARB25 (Bit 25)                                      */
+ #define R_PSCU_PSARB_PSARB25_Msk    (0x2000000UL)  /*!< PSARB25 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB26_Pos    (26UL)         /*!< PSARB26 (Bit 26)                                      */
+ #define R_PSCU_PSARB_PSARB26_Msk    (0x4000000UL)  /*!< PSARB26 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB27_Pos    (27UL)         /*!< PSARB27 (Bit 27)                                      */
+ #define R_PSCU_PSARB_PSARB27_Msk    (0x8000000UL)  /*!< PSARB27 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB28_Pos    (28UL)         /*!< PSARB28 (Bit 28)                                      */
+ #define R_PSCU_PSARB_PSARB28_Msk    (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB29_Pos    (29UL)         /*!< PSARB29 (Bit 29)                                      */
+ #define R_PSCU_PSARB_PSARB29_Msk    (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB30_Pos    (30UL)         /*!< PSARB30 (Bit 30)                                      */
+ #define R_PSCU_PSARB_PSARB30_Msk    (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARB_PSARB31_Pos    (31UL)         /*!< PSARB31 (Bit 31)                                      */
+ #define R_PSCU_PSARB_PSARB31_Msk    (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01)                         */
+/* =========================================================  PSARC  ========================================================= */
+ #define R_PSCU_PSARC_PSARC0_Pos     (0UL)          /*!< PSARC0 (Bit 0)                                        */
+ #define R_PSCU_PSARC_PSARC0_Msk     (0x1UL)        /*!< PSARC0 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARC_PSARC1_Pos     (1UL)          /*!< PSARC1 (Bit 1)                                        */
+ #define R_PSCU_PSARC_PSARC1_Msk     (0x2UL)        /*!< PSARC1 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARC_PSARC3_Pos     (3UL)          /*!< PSARC3 (Bit 3)                                        */
+ #define R_PSCU_PSARC_PSARC3_Msk     (0x8UL)        /*!< PSARC3 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARC_PSARC8_Pos     (8UL)          /*!< PSARC8 (Bit 8)                                        */
+ #define R_PSCU_PSARC_PSARC8_Msk     (0x100UL)      /*!< PSARC8 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARC_PSARC12_Pos    (12UL)         /*!< PSARC12 (Bit 12)                                      */
+ #define R_PSCU_PSARC_PSARC12_Msk    (0x1000UL)     /*!< PSARC12 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARC_PSARC13_Pos    (13UL)         /*!< PSARC13 (Bit 13)                                      */
+ #define R_PSCU_PSARC_PSARC13_Msk    (0x2000UL)     /*!< PSARC13 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARC_PSARC20_Pos    (20UL)         /*!< PSARC20 (Bit 20)                                      */
+ #define R_PSCU_PSARC_PSARC20_Msk    (0x100000UL)   /*!< PSARC20 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARC_PSARC27_Pos    (27UL)         /*!< PSARC27 (Bit 27)                                      */
+ #define R_PSCU_PSARC_PSARC27_Msk    (0x8000000UL)  /*!< PSARC27 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARC_PSARC31_Pos    (31UL)         /*!< PSARC31 (Bit 31)                                      */
+ #define R_PSCU_PSARC_PSARC31_Msk    (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01)                         */
+/* =========================================================  PSARD  ========================================================= */
+ #define R_PSCU_PSARD_PSARD0_Pos     (0UL)          /*!< PSARD0 (Bit 0)                                        */
+ #define R_PSCU_PSARD_PSARD0_Msk     (0x1UL)        /*!< PSARD0 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARD_PSARD1_Pos     (1UL)          /*!< PSARD1 (Bit 1)                                        */
+ #define R_PSCU_PSARD_PSARD1_Msk     (0x2UL)        /*!< PSARD1 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARD_PSARD2_Pos     (2UL)          /*!< PSARD2 (Bit 2)                                        */
+ #define R_PSCU_PSARD_PSARD2_Msk     (0x4UL)        /*!< PSARD2 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARD_PSARD3_Pos     (3UL)          /*!< PSARD3 (Bit 3)                                        */
+ #define R_PSCU_PSARD_PSARD3_Msk     (0x8UL)        /*!< PSARD3 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARD_PSARD11_Pos    (11UL)         /*!< PSARD11 (Bit 11)                                      */
+ #define R_PSCU_PSARD_PSARD11_Msk    (0x800UL)      /*!< PSARD11 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD12_Pos    (12UL)         /*!< PSARD12 (Bit 12)                                      */
+ #define R_PSCU_PSARD_PSARD12_Msk    (0x1000UL)     /*!< PSARD12 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD13_Pos    (13UL)         /*!< PSARD13 (Bit 13)                                      */
+ #define R_PSCU_PSARD_PSARD13_Msk    (0x2000UL)     /*!< PSARD13 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD14_Pos    (14UL)         /*!< PSARD14 (Bit 14)                                      */
+ #define R_PSCU_PSARD_PSARD14_Msk    (0x4000UL)     /*!< PSARD14 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD15_Pos    (15UL)         /*!< PSARD15 (Bit 15)                                      */
+ #define R_PSCU_PSARD_PSARD15_Msk    (0x8000UL)     /*!< PSARD15 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD16_Pos    (16UL)         /*!< PSARD16 (Bit 16)                                      */
+ #define R_PSCU_PSARD_PSARD16_Msk    (0x10000UL)    /*!< PSARD16 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD19_Pos    (19UL)         /*!< PSARD19 (Bit 19)                                      */
+ #define R_PSCU_PSARD_PSARD19_Msk    (0x80000UL)    /*!< PSARD19 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD20_Pos    (20UL)         /*!< PSARD20 (Bit 20)                                      */
+ #define R_PSCU_PSARD_PSARD20_Msk    (0x100000UL)   /*!< PSARD20 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD22_Pos    (22UL)         /*!< PSARD22 (Bit 22)                                      */
+ #define R_PSCU_PSARD_PSARD22_Msk    (0x400000UL)   /*!< PSARD22 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD25_Pos    (25UL)         /*!< PSARD25 (Bit 25)                                      */
+ #define R_PSCU_PSARD_PSARD25_Msk    (0x2000000UL)  /*!< PSARD25 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD26_Pos    (26UL)         /*!< PSARD26 (Bit 26)                                      */
+ #define R_PSCU_PSARD_PSARD26_Msk    (0x4000000UL)  /*!< PSARD26 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD27_Pos    (27UL)         /*!< PSARD27 (Bit 27)                                      */
+ #define R_PSCU_PSARD_PSARD27_Msk    (0x8000000UL)  /*!< PSARD27 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARD_PSARD28_Pos    (28UL)         /*!< PSARD28 (Bit 28)                                      */
+ #define R_PSCU_PSARD_PSARD28_Msk    (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01)                         */
+/* =========================================================  PSARE  ========================================================= */
+ #define R_PSCU_PSARE_PSARE0_Pos     (0UL)          /*!< PSARE0 (Bit 0)                                        */
+ #define R_PSCU_PSARE_PSARE0_Msk     (0x1UL)        /*!< PSARE0 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARE_PSARE1_Pos     (1UL)          /*!< PSARE1 (Bit 1)                                        */
+ #define R_PSCU_PSARE_PSARE1_Msk     (0x2UL)        /*!< PSARE1 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARE_PSARE2_Pos     (2UL)          /*!< PSARE2 (Bit 2)                                        */
+ #define R_PSCU_PSARE_PSARE2_Msk     (0x4UL)        /*!< PSARE2 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_PSARE_PSARE14_Pos    (14UL)         /*!< PSARE14 (Bit 14)                                      */
+ #define R_PSCU_PSARE_PSARE14_Msk    (0x4000UL)     /*!< PSARE14 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE15_Pos    (15UL)         /*!< PSARE15 (Bit 15)                                      */
+ #define R_PSCU_PSARE_PSARE15_Msk    (0x8000UL)     /*!< PSARE15 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE22_Pos    (22UL)         /*!< PSARE22 (Bit 22)                                      */
+ #define R_PSCU_PSARE_PSARE22_Msk    (0x400000UL)   /*!< PSARE22 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE23_Pos    (23UL)         /*!< PSARE23 (Bit 23)                                      */
+ #define R_PSCU_PSARE_PSARE23_Msk    (0x800000UL)   /*!< PSARE23 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE24_Pos    (24UL)         /*!< PSARE24 (Bit 24)                                      */
+ #define R_PSCU_PSARE_PSARE24_Msk    (0x1000000UL)  /*!< PSARE24 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE25_Pos    (25UL)         /*!< PSARE25 (Bit 25)                                      */
+ #define R_PSCU_PSARE_PSARE25_Msk    (0x2000000UL)  /*!< PSARE25 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE26_Pos    (26UL)         /*!< PSARE26 (Bit 26)                                      */
+ #define R_PSCU_PSARE_PSARE26_Msk    (0x4000000UL)  /*!< PSARE26 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE27_Pos    (27UL)         /*!< PSARE27 (Bit 27)                                      */
+ #define R_PSCU_PSARE_PSARE27_Msk    (0x8000000UL)  /*!< PSARE27 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE28_Pos    (28UL)         /*!< PSARE28 (Bit 28)                                      */
+ #define R_PSCU_PSARE_PSARE28_Msk    (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE29_Pos    (29UL)         /*!< PSARE29 (Bit 29)                                      */
+ #define R_PSCU_PSARE_PSARE29_Msk    (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE30_Pos    (30UL)         /*!< PSARE30 (Bit 30)                                      */
+ #define R_PSCU_PSARE_PSARE30_Msk    (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01)                         */
+ #define R_PSCU_PSARE_PSARE31_Pos    (31UL)         /*!< PSARE31 (Bit 31)                                      */
+ #define R_PSCU_PSARE_PSARE31_Msk    (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01)                         */
+/* =========================================================  MSSAR  ========================================================= */
+ #define R_PSCU_MSSAR_MSSAR0_Pos     (0UL)          /*!< MSSAR0 (Bit 0)                                        */
+ #define R_PSCU_MSSAR_MSSAR0_Msk     (0x1UL)        /*!< MSSAR0 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_MSSAR_MSSAR1_Pos     (1UL)          /*!< MSSAR1 (Bit 1)                                        */
+ #define R_PSCU_MSSAR_MSSAR1_Msk     (0x2UL)        /*!< MSSAR1 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_MSSAR_MSSAR2_Pos     (2UL)          /*!< MSSAR2 (Bit 2)                                        */
+ #define R_PSCU_MSSAR_MSSAR2_Msk     (0x4UL)        /*!< MSSAR2 (Bitfield-Mask: 0x01)                          */
+ #define R_PSCU_MSSAR_MSSAR3_Pos     (3UL)          /*!< MSSAR3 (Bit 3)                                        */
+ #define R_PSCU_MSSAR_MSSAR3_Msk     (0x8UL)        /*!< MSSAR3 (Bitfield-Mask: 0x01)                          */
+/* =======================================================  CFSAMONA  ======================================================== */
+ #define R_PSCU_CFSAMONA_CFS2_Pos    (15UL)         /*!< CFS2 (Bit 15)                                         */
+ #define R_PSCU_CFSAMONA_CFS2_Msk    (0xff8000UL)   /*!< CFS2 (Bitfield-Mask: 0x1ff)                           */
+/* =======================================================  CFSAMONB  ======================================================== */
+ #define R_PSCU_CFSAMONB_CFS1_Pos    (10UL)         /*!< CFS1 (Bit 10)                                         */
+ #define R_PSCU_CFSAMONB_CFS1_Msk    (0xfffc00UL)   /*!< CFS1 (Bitfield-Mask: 0x3fff)                          */
+/* ========================================================  DFSAMON  ======================================================== */
+ #define R_PSCU_DFSAMON_DFS_Pos      (10UL)         /*!< DFS (Bit 10)                                          */
+ #define R_PSCU_DFSAMON_DFS_Msk      (0xfc00UL)     /*!< DFS (Bitfield-Mask: 0x3f)                             */
+/* ========================================================  SSAMONA  ======================================================== */
+ #define R_PSCU_SSAMONA_SS2_Pos      (13UL)         /*!< SS2 (Bit 13)                                          */
+ #define R_PSCU_SSAMONA_SS2_Msk      (0x1fe000UL)   /*!< SS2 (Bitfield-Mask: 0xff)                             */
+/* ========================================================  SSAMONB  ======================================================== */
+ #define R_PSCU_SSAMONB_SS1_Pos      (10UL)         /*!< SS1 (Bit 10)                                          */
+ #define R_PSCU_SSAMONB_SS1_Msk      (0x1ffc00UL)   /*!< SS1 (Bitfield-Mask: 0x7ff)                            */
+/* ========================================================  DLMMON  ========================================================= */
+ #define R_PSCU_DLMMON_DLMMON_Pos    (0UL)          /*!< DLMMON (Bit 0)                                        */
+ #define R_PSCU_DLMMON_DLMMON_Msk    (0xfUL)        /*!< DLMMON (Bitfield-Mask: 0x0f)                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_BUS                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CSRECEN  ======================================================== */
+ #define R_BUS_CSRECEN_RCVENM_Pos    (8UL)     /*!< RCVENM (Bit 8)                                        */
+ #define R_BUS_CSRECEN_RCVENM_Msk    (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01)                          */
+ #define R_BUS_CSRECEN_RCVEN_Pos     (0UL)     /*!< RCVEN (Bit 0)                                         */
+ #define R_BUS_CSRECEN_RCVEN_Msk     (0x1UL)   /*!< RCVEN (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                           R_CAC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  CACR0  ========================================================= */
+ #define R_CAC_CACR0_CFME_Pos         (0UL)      /*!< CFME (Bit 0)                                          */
+ #define R_CAC_CACR0_CFME_Msk         (0x1UL)    /*!< CFME (Bitfield-Mask: 0x01)                            */
+/* =========================================================  CACR1  ========================================================= */
+ #define R_CAC_CACR1_EDGES_Pos        (6UL)      /*!< EDGES (Bit 6)                                         */
+ #define R_CAC_CACR1_EDGES_Msk        (0xc0UL)   /*!< EDGES (Bitfield-Mask: 0x03)                           */
+ #define R_CAC_CACR1_TCSS_Pos         (4UL)      /*!< TCSS (Bit 4)                                          */
+ #define R_CAC_CACR1_TCSS_Msk         (0x30UL)   /*!< TCSS (Bitfield-Mask: 0x03)                            */
+ #define R_CAC_CACR1_FMCS_Pos         (1UL)      /*!< FMCS (Bit 1)                                          */
+ #define R_CAC_CACR1_FMCS_Msk         (0xeUL)    /*!< FMCS (Bitfield-Mask: 0x07)                            */
+ #define R_CAC_CACR1_CACREFE_Pos      (0UL)      /*!< CACREFE (Bit 0)                                       */
+ #define R_CAC_CACR1_CACREFE_Msk      (0x1UL)    /*!< CACREFE (Bitfield-Mask: 0x01)                         */
+/* =========================================================  CACR2  ========================================================= */
+ #define R_CAC_CACR2_DFS_Pos          (6UL)      /*!< DFS (Bit 6)                                           */
+ #define R_CAC_CACR2_DFS_Msk          (0xc0UL)   /*!< DFS (Bitfield-Mask: 0x03)                             */
+ #define R_CAC_CACR2_RCDS_Pos         (4UL)      /*!< RCDS (Bit 4)                                          */
+ #define R_CAC_CACR2_RCDS_Msk         (0x30UL)   /*!< RCDS (Bitfield-Mask: 0x03)                            */
+ #define R_CAC_CACR2_RSCS_Pos         (1UL)      /*!< RSCS (Bit 1)                                          */
+ #define R_CAC_CACR2_RSCS_Msk         (0xeUL)    /*!< RSCS (Bitfield-Mask: 0x07)                            */
+ #define R_CAC_CACR2_RPS_Pos          (0UL)      /*!< RPS (Bit 0)                                           */
+ #define R_CAC_CACR2_RPS_Msk          (0x1UL)    /*!< RPS (Bitfield-Mask: 0x01)                             */
+/* =========================================================  CAICR  ========================================================= */
+ #define R_CAC_CAICR_OVFFCL_Pos       (6UL)      /*!< OVFFCL (Bit 6)                                        */
+ #define R_CAC_CAICR_OVFFCL_Msk       (0x40UL)   /*!< OVFFCL (Bitfield-Mask: 0x01)                          */
+ #define R_CAC_CAICR_MENDFCL_Pos      (5UL)      /*!< MENDFCL (Bit 5)                                       */
+ #define R_CAC_CAICR_MENDFCL_Msk      (0x20UL)   /*!< MENDFCL (Bitfield-Mask: 0x01)                         */
+ #define R_CAC_CAICR_FERRFCL_Pos      (4UL)      /*!< FERRFCL (Bit 4)                                       */
+ #define R_CAC_CAICR_FERRFCL_Msk      (0x10UL)   /*!< FERRFCL (Bitfield-Mask: 0x01)                         */
+ #define R_CAC_CAICR_OVFIE_Pos        (2UL)      /*!< OVFIE (Bit 2)                                         */
+ #define R_CAC_CAICR_OVFIE_Msk        (0x4UL)    /*!< OVFIE (Bitfield-Mask: 0x01)                           */
+ #define R_CAC_CAICR_MENDIE_Pos       (1UL)      /*!< MENDIE (Bit 1)                                        */
+ #define R_CAC_CAICR_MENDIE_Msk       (0x2UL)    /*!< MENDIE (Bitfield-Mask: 0x01)                          */
+ #define R_CAC_CAICR_FERRIE_Pos       (0UL)      /*!< FERRIE (Bit 0)                                        */
+ #define R_CAC_CAICR_FERRIE_Msk       (0x1UL)    /*!< FERRIE (Bitfield-Mask: 0x01)                          */
+/* =========================================================  CASTR  ========================================================= */
+ #define R_CAC_CASTR_OVFF_Pos         (2UL)      /*!< OVFF (Bit 2)                                          */
+ #define R_CAC_CASTR_OVFF_Msk         (0x4UL)    /*!< OVFF (Bitfield-Mask: 0x01)                            */
+ #define R_CAC_CASTR_MENDF_Pos        (1UL)      /*!< MENDF (Bit 1)                                         */
+ #define R_CAC_CASTR_MENDF_Msk        (0x2UL)    /*!< MENDF (Bitfield-Mask: 0x01)                           */
+ #define R_CAC_CASTR_FERRF_Pos        (0UL)      /*!< FERRF (Bit 0)                                         */
+ #define R_CAC_CASTR_FERRF_Msk        (0x1UL)    /*!< FERRF (Bitfield-Mask: 0x01)                           */
+/* ========================================================  CAULVR  ========================================================= */
+ #define R_CAC_CAULVR_CAULVR_Pos      (0UL)      /*!< CAULVR (Bit 0)                                        */
+ #define R_CAC_CAULVR_CAULVR_Msk      (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  CALLVR  ========================================================= */
+ #define R_CAC_CALLVR_CALLVR_Pos      (0UL)      /*!< CALLVR (Bit 0)                                        */
+ #define R_CAC_CALLVR_CALLVR_Msk      (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  CACNTBR  ======================================================== */
+ #define R_CAC_CACNTBR_CACNTBR_Pos    (0UL)      /*!< CACNTBR (Bit 0)                                       */
+ #define R_CAC_CACNTBR_CACNTBR_Msk    (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff)                       */
+
+/* =========================================================================================================================== */
+/* ================                                         R_CANFD0                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CFDGCFG  ======================================================== */
+ #define R_CANFD_CFDGCFG_TPRI_Pos                (0UL)          /*!< TPRI (Bit 0)                                          */
+ #define R_CANFD_CFDGCFG_TPRI_Msk                (0x1UL)        /*!< TPRI (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGCFG_DCE_Pos                 (1UL)          /*!< DCE (Bit 1)                                           */
+ #define R_CANFD_CFDGCFG_DCE_Msk                 (0x2UL)        /*!< DCE (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGCFG_DRE_Pos                 (2UL)          /*!< DRE (Bit 2)                                           */
+ #define R_CANFD_CFDGCFG_DRE_Msk                 (0x4UL)        /*!< DRE (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGCFG_MME_Pos                 (3UL)          /*!< MME (Bit 3)                                           */
+ #define R_CANFD_CFDGCFG_MME_Msk                 (0x8UL)        /*!< MME (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGCFG_DCS_Pos                 (4UL)          /*!< DCS (Bit 4)                                           */
+ #define R_CANFD_CFDGCFG_DCS_Msk                 (0x10UL)       /*!< DCS (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGCFG_CMPOC_Pos               (5UL)          /*!< CMPOC (Bit 5)                                         */
+ #define R_CANFD_CFDGCFG_CMPOC_Msk               (0x20UL)       /*!< CMPOC (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGCFG_TSP_Pos                 (8UL)          /*!< TSP (Bit 8)                                           */
+ #define R_CANFD_CFDGCFG_TSP_Msk                 (0xf00UL)      /*!< TSP (Bitfield-Mask: 0x0f)                             */
+ #define R_CANFD_CFDGCFG_TSSS_Pos                (12UL)         /*!< TSSS (Bit 12)                                         */
+ #define R_CANFD_CFDGCFG_TSSS_Msk                (0x1000UL)     /*!< TSSS (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGCFG_ITRCP_Pos               (16UL)         /*!< ITRCP (Bit 16)                                        */
+ #define R_CANFD_CFDGCFG_ITRCP_Msk               (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  CFDGCTR  ======================================================== */
+ #define R_CANFD_CFDGCTR_GMDC_Pos                (0UL)          /*!< GMDC (Bit 0)                                          */
+ #define R_CANFD_CFDGCTR_GMDC_Msk                (0x3UL)        /*!< GMDC (Bitfield-Mask: 0x03)                            */
+ #define R_CANFD_CFDGCTR_GSLPR_Pos               (2UL)          /*!< GSLPR (Bit 2)                                         */
+ #define R_CANFD_CFDGCTR_GSLPR_Msk               (0x4UL)        /*!< GSLPR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGCTR_DEIE_Pos                (8UL)          /*!< DEIE (Bit 8)                                          */
+ #define R_CANFD_CFDGCTR_DEIE_Msk                (0x100UL)      /*!< DEIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGCTR_MEIE_Pos                (9UL)          /*!< MEIE (Bit 9)                                          */
+ #define R_CANFD_CFDGCTR_MEIE_Msk                (0x200UL)      /*!< MEIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGCTR_THLEIE_Pos              (10UL)         /*!< THLEIE (Bit 10)                                       */
+ #define R_CANFD_CFDGCTR_THLEIE_Msk              (0x400UL)      /*!< THLEIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDGCTR_CMPOFIE_Pos             (11UL)         /*!< CMPOFIE (Bit 11)                                      */
+ #define R_CANFD_CFDGCTR_CMPOFIE_Msk             (0x800UL)      /*!< CMPOFIE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGCTR_TSRST_Pos               (16UL)         /*!< TSRST (Bit 16)                                        */
+ #define R_CANFD_CFDGCTR_TSRST_Msk               (0x10000UL)    /*!< TSRST (Bitfield-Mask: 0x01)                           */
+/* ========================================================  CFDGSTS  ======================================================== */
+ #define R_CANFD_CFDGSTS_GRSTSTS_Pos             (0UL)          /*!< GRSTSTS (Bit 0)                                       */
+ #define R_CANFD_CFDGSTS_GRSTSTS_Msk             (0x1UL)        /*!< GRSTSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGSTS_GHLTSTS_Pos             (1UL)          /*!< GHLTSTS (Bit 1)                                       */
+ #define R_CANFD_CFDGSTS_GHLTSTS_Msk             (0x2UL)        /*!< GHLTSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGSTS_GSLPSTS_Pos             (2UL)          /*!< GSLPSTS (Bit 2)                                       */
+ #define R_CANFD_CFDGSTS_GSLPSTS_Msk             (0x4UL)        /*!< GSLPSTS (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDGSTS_GRAMINIT_Pos            (3UL)          /*!< GRAMINIT (Bit 3)                                      */
+ #define R_CANFD_CFDGSTS_GRAMINIT_Msk            (0x8UL)        /*!< GRAMINIT (Bitfield-Mask: 0x01)                        */
+/* =======================================================  CFDGERFL  ======================================================== */
+ #define R_CANFD_CFDGERFL_DEF_Pos                (0UL)          /*!< DEF (Bit 0)                                           */
+ #define R_CANFD_CFDGERFL_DEF_Msk                (0x1UL)        /*!< DEF (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGERFL_MES_Pos                (1UL)          /*!< MES (Bit 1)                                           */
+ #define R_CANFD_CFDGERFL_MES_Msk                (0x2UL)        /*!< MES (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDGERFL_THLES_Pos              (2UL)          /*!< THLES (Bit 2)                                         */
+ #define R_CANFD_CFDGERFL_THLES_Msk              (0x4UL)        /*!< THLES (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGERFL_CMPOF_Pos              (3UL)          /*!< CMPOF (Bit 3)                                         */
+ #define R_CANFD_CFDGERFL_CMPOF_Msk              (0x8UL)        /*!< CMPOF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGERFL_EEF0_Pos               (16UL)         /*!< EEF0 (Bit 16)                                         */
+ #define R_CANFD_CFDGERFL_EEF0_Msk               (0x10000UL)    /*!< EEF0 (Bitfield-Mask: 0x01)                            */
+/* ========================================================  CFDGTSC  ======================================================== */
+ #define R_CANFD_CFDGTSC_TS_Pos                  (0UL)          /*!< TS (Bit 0)                                            */
+ #define R_CANFD_CFDGTSC_TS_Msk                  (0xffffUL)     /*!< TS (Bitfield-Mask: 0xffff)                            */
+/* ======================================================  CFDGAFLECTR  ====================================================== */
+ #define R_CANFD_CFDGAFLECTR_AFLPN_Pos           (0UL)          /*!< AFLPN (Bit 0)                                         */
+ #define R_CANFD_CFDGAFLECTR_AFLPN_Msk           (0xfUL)        /*!< AFLPN (Bitfield-Mask: 0x0f)                           */
+ #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos          (8UL)          /*!< AFLDAE (Bit 8)                                        */
+ #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk          (0x100UL)      /*!< AFLDAE (Bitfield-Mask: 0x01)                          */
+/* ======================================================  CFDGAFLCFG0  ====================================================== */
+ #define R_CANFD_CFDGAFLCFG0_RNC1_Pos            (0UL)          /*!< RNC1 (Bit 0)                                          */
+ #define R_CANFD_CFDGAFLCFG0_RNC1_Msk            (0x1ffUL)      /*!< RNC1 (Bitfield-Mask: 0x1ff)                           */
+ #define R_CANFD_CFDGAFLCFG0_RNC0_Pos            (16UL)         /*!< RNC0 (Bit 16)                                         */
+ #define R_CANFD_CFDGAFLCFG0_RNC0_Msk            (0x1ff0000UL)  /*!< RNC0 (Bitfield-Mask: 0x1ff)                           */
+/* ========================================================  CFDRMNB  ======================================================== */
+ #define R_CANFD_CFDRMNB_NRXMB_Pos               (0UL)          /*!< NRXMB (Bit 0)                                         */
+ #define R_CANFD_CFDRMNB_NRXMB_Msk               (0xffUL)       /*!< NRXMB (Bitfield-Mask: 0xff)                           */
+ #define R_CANFD_CFDRMNB_RMPLS_Pos               (8UL)          /*!< RMPLS (Bit 8)                                         */
+ #define R_CANFD_CFDRMNB_RMPLS_Msk               (0x700UL)      /*!< RMPLS (Bitfield-Mask: 0x07)                           */
+/* =======================================================  CFDRMND0  ======================================================== */
+ #define R_CANFD_CFDRMND0_RMNSu_Pos              (0UL)          /*!< RMNSu (Bit 0)                                         */
+ #define R_CANFD_CFDRMND0_RMNSu_Msk              (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff)                     */
+/* =======================================================  CFDRMIEC  ======================================================== */
+ #define R_CANFD_CFDRMIEC_RMIE_Pos               (0UL)          /*!< RMIE (Bit 0)                                          */
+ #define R_CANFD_CFDRMIEC_RMIE_Msk               (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff)                      */
+/* ========================================================  CFDRFCC  ======================================================== */
+ #define R_CANFD_CFDRFCC_RFE_Pos                 (0UL)          /*!< RFE (Bit 0)                                           */
+ #define R_CANFD_CFDRFCC_RFE_Msk                 (0x1UL)        /*!< RFE (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDRFCC_RFIE_Pos                (1UL)          /*!< RFIE (Bit 1)                                          */
+ #define R_CANFD_CFDRFCC_RFIE_Msk                (0x2UL)        /*!< RFIE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDRFCC_RFPLS_Pos               (4UL)          /*!< RFPLS (Bit 4)                                         */
+ #define R_CANFD_CFDRFCC_RFPLS_Msk               (0x70UL)       /*!< RFPLS (Bitfield-Mask: 0x07)                           */
+ #define R_CANFD_CFDRFCC_RFDC_Pos                (8UL)          /*!< RFDC (Bit 8)                                          */
+ #define R_CANFD_CFDRFCC_RFDC_Msk                (0x700UL)      /*!< RFDC (Bitfield-Mask: 0x07)                            */
+ #define R_CANFD_CFDRFCC_RFIM_Pos                (12UL)         /*!< RFIM (Bit 12)                                         */
+ #define R_CANFD_CFDRFCC_RFIM_Msk                (0x1000UL)     /*!< RFIM (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDRFCC_RFIGCV_Pos              (13UL)         /*!< RFIGCV (Bit 13)                                       */
+ #define R_CANFD_CFDRFCC_RFIGCV_Msk              (0xe000UL)     /*!< RFIGCV (Bitfield-Mask: 0x07)                          */
+/* =======================================================  CFDRFSTS  ======================================================== */
+ #define R_CANFD_CFDRFSTS_RFEMP_Pos              (0UL)          /*!< RFEMP (Bit 0)                                         */
+ #define R_CANFD_CFDRFSTS_RFEMP_Msk              (0x1UL)        /*!< RFEMP (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRFSTS_RFFLL_Pos              (1UL)          /*!< RFFLL (Bit 1)                                         */
+ #define R_CANFD_CFDRFSTS_RFFLL_Msk              (0x2UL)        /*!< RFFLL (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRFSTS_RFMLT_Pos              (2UL)          /*!< RFMLT (Bit 2)                                         */
+ #define R_CANFD_CFDRFSTS_RFMLT_Msk              (0x4UL)        /*!< RFMLT (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDRFSTS_RFIF_Pos               (3UL)          /*!< RFIF (Bit 3)                                          */
+ #define R_CANFD_CFDRFSTS_RFIF_Msk               (0x8UL)        /*!< RFIF (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDRFSTS_RFMC_Pos               (8UL)          /*!< RFMC (Bit 8)                                          */
+ #define R_CANFD_CFDRFSTS_RFMC_Msk               (0xff00UL)     /*!< RFMC (Bitfield-Mask: 0xff)                            */
+/* =======================================================  CFDRFPCTR  ======================================================= */
+ #define R_CANFD_CFDRFPCTR_RFPC_Pos              (0UL)          /*!< RFPC (Bit 0)                                          */
+ #define R_CANFD_CFDRFPCTR_RFPC_Msk              (0xffUL)       /*!< RFPC (Bitfield-Mask: 0xff)                            */
+/* ========================================================  CFDCFCC  ======================================================== */
+ #define R_CANFD_CFDCFCC_CFE_Pos                 (0UL)          /*!< CFE (Bit 0)                                           */
+ #define R_CANFD_CFDCFCC_CFE_Msk                 (0x1UL)        /*!< CFE (Bitfield-Mask: 0x01)                             */
+ #define R_CANFD_CFDCFCC_CFRXIE_Pos              (1UL)          /*!< CFRXIE (Bit 1)                                        */
+ #define R_CANFD_CFDCFCC_CFRXIE_Msk              (0x2UL)        /*!< CFRXIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFCC_CFTXIE_Pos              (2UL)          /*!< CFTXIE (Bit 2)                                        */
+ #define R_CANFD_CFDCFCC_CFTXIE_Msk              (0x4UL)        /*!< CFTXIE (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFCC_CFPLS_Pos               (4UL)          /*!< CFPLS (Bit 4)                                         */
+ #define R_CANFD_CFDCFCC_CFPLS_Msk               (0x70UL)       /*!< CFPLS (Bitfield-Mask: 0x07)                           */
+ #define R_CANFD_CFDCFCC_CFM_Pos                 (8UL)          /*!< CFM (Bit 8)                                           */
+ #define R_CANFD_CFDCFCC_CFM_Msk                 (0x300UL)      /*!< CFM (Bitfield-Mask: 0x03)                             */
+ #define R_CANFD_CFDCFCC_CFITSS_Pos              (10UL)         /*!< CFITSS (Bit 10)                                       */
+ #define R_CANFD_CFDCFCC_CFITSS_Msk              (0x400UL)      /*!< CFITSS (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFCC_CFITR_Pos               (11UL)         /*!< CFITR (Bit 11)                                        */
+ #define R_CANFD_CFDCFCC_CFITR_Msk               (0x800UL)      /*!< CFITR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCFCC_CFIM_Pos                (12UL)         /*!< CFIM (Bit 12)                                         */
+ #define R_CANFD_CFDCFCC_CFIM_Msk                (0x1000UL)     /*!< CFIM (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDCFCC_CFIGCV_Pos              (13UL)         /*!< CFIGCV (Bit 13)                                       */
+ #define R_CANFD_CFDCFCC_CFIGCV_Msk              (0xe000UL)     /*!< CFIGCV (Bitfield-Mask: 0x07)                          */
+ #define R_CANFD_CFDCFCC_CFTML_Pos               (16UL)         /*!< CFTML (Bit 16)                                        */
+ #define R_CANFD_CFDCFCC_CFTML_Msk               (0x1f0000UL)   /*!< CFTML (Bitfield-Mask: 0x1f)                           */
+ #define R_CANFD_CFDCFCC_CFDC_Pos                (21UL)         /*!< CFDC (Bit 21)                                         */
+ #define R_CANFD_CFDCFCC_CFDC_Msk                (0xe00000UL)   /*!< CFDC (Bitfield-Mask: 0x07)                            */
+ #define R_CANFD_CFDCFCC_CFITT_Pos               (24UL)         /*!< CFITT (Bit 24)                                        */
+ #define R_CANFD_CFDCFCC_CFITT_Msk               (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff)                           */
+/* =======================================================  CFDCFSTS  ======================================================== */
+ #define R_CANFD_CFDCFSTS_CFEMP_Pos              (0UL)          /*!< CFEMP (Bit 0)                                         */
+ #define R_CANFD_CFDCFSTS_CFEMP_Msk              (0x1UL)        /*!< CFEMP (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCFSTS_CFFLL_Pos              (1UL)          /*!< CFFLL (Bit 1)                                         */
+ #define R_CANFD_CFDCFSTS_CFFLL_Msk              (0x2UL)        /*!< CFFLL (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCFSTS_CFMLT_Pos              (2UL)          /*!< CFMLT (Bit 2)                                         */
+ #define R_CANFD_CFDCFSTS_CFMLT_Msk              (0x4UL)        /*!< CFMLT (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDCFSTS_CFRXIF_Pos             (3UL)          /*!< CFRXIF (Bit 3)                                        */
+ #define R_CANFD_CFDCFSTS_CFRXIF_Msk             (0x8UL)        /*!< CFRXIF (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFSTS_CFTXIF_Pos             (4UL)          /*!< CFTXIF (Bit 4)                                        */
+ #define R_CANFD_CFDCFSTS_CFTXIF_Msk             (0x10UL)       /*!< CFTXIF (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDCFSTS_CFMC_Pos               (8UL)          /*!< CFMC (Bit 8)                                          */
+ #define R_CANFD_CFDCFSTS_CFMC_Msk               (0xff00UL)     /*!< CFMC (Bitfield-Mask: 0xff)                            */
+/* =======================================================  CFDCFPCTR  ======================================================= */
+ #define R_CANFD_CFDCFPCTR_CFPC_Pos              (0UL)          /*!< CFPC (Bit 0)                                          */
+ #define R_CANFD_CFDCFPCTR_CFPC_Msk              (0xffUL)       /*!< CFPC (Bitfield-Mask: 0xff)                            */
+/* =======================================================  CFDFESTS  ======================================================== */
+ #define R_CANFD_CFDFESTS_RFXEMP_Pos             (0UL)          /*!< RFXEMP (Bit 0)                                        */
+ #define R_CANFD_CFDFESTS_RFXEMP_Msk             (0x3UL)        /*!< RFXEMP (Bitfield-Mask: 0x03)                          */
+ #define R_CANFD_CFDFESTS_CFXEMP_Pos             (8UL)          /*!< CFXEMP (Bit 8)                                        */
+ #define R_CANFD_CFDFESTS_CFXEMP_Msk             (0x100UL)      /*!< CFXEMP (Bitfield-Mask: 0x01)                          */
+/* =======================================================  CFDFFSTS  ======================================================== */
+ #define R_CANFD_CFDFFSTS_RFXFLL_Pos             (0UL)          /*!< RFXFLL (Bit 0)                                        */
+ #define R_CANFD_CFDFFSTS_RFXFLL_Msk             (0x3UL)        /*!< RFXFLL (Bitfield-Mask: 0x03)                          */
+ #define R_CANFD_CFDFFSTS_CFXFLL_Pos             (8UL)          /*!< CFXFLL (Bit 8)                                        */
+ #define R_CANFD_CFDFFSTS_CFXFLL_Msk             (0x100UL)      /*!< CFXFLL (Bitfield-Mask: 0x01)                          */
+/* =======================================================  CFDFMSTS  ======================================================== */
+ #define R_CANFD_CFDFMSTS_RFXMLT_Pos             (0UL)          /*!< RFXMLT (Bit 0)                                        */
+ #define R_CANFD_CFDFMSTS_RFXMLT_Msk             (0x3UL)        /*!< RFXMLT (Bitfield-Mask: 0x03)                          */
+ #define R_CANFD_CFDFMSTS_CFXMLT_Pos             (8UL)          /*!< CFXMLT (Bit 8)                                        */
+ #define R_CANFD_CFDFMSTS_CFXMLT_Msk             (0x100UL)      /*!< CFXMLT (Bitfield-Mask: 0x01)                          */
+/* =======================================================  CFDRFISTS  ======================================================= */
+ #define R_CANFD_CFDRFISTS_RFXIF_Pos             (0UL)          /*!< RFXIF (Bit 0)                                         */
+ #define R_CANFD_CFDRFISTS_RFXIF_Msk             (0x1UL)        /*!< RFXIF (Bitfield-Mask: 0x01)                           */
+/* ========================================================  CFDTMC  ========================================================= */
+ #define R_CANFD_CFDTMC_TMTR_Pos                 (0UL)          /*!< TMTR (Bit 0)                                          */
+ #define R_CANFD_CFDTMC_TMTR_Msk                 (0x1UL)        /*!< TMTR (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDTMC_TMTAR_Pos                (1UL)          /*!< TMTAR (Bit 1)                                         */
+ #define R_CANFD_CFDTMC_TMTAR_Msk                (0x2UL)        /*!< TMTAR (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTMC_TMOM_Pos                 (2UL)          /*!< TMOM (Bit 2)                                          */
+ #define R_CANFD_CFDTMC_TMOM_Msk                 (0x4UL)        /*!< TMOM (Bitfield-Mask: 0x01)                            */
+/* =======================================================  CFDTMSTS  ======================================================== */
+ #define R_CANFD_CFDTMSTS_TMTSTS_Pos             (0UL)          /*!< TMTSTS (Bit 0)                                        */
+ #define R_CANFD_CFDTMSTS_TMTSTS_Msk             (0x1UL)        /*!< TMTSTS (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTMSTS_TMTRF_Pos              (1UL)          /*!< TMTRF (Bit 1)                                         */
+ #define R_CANFD_CFDTMSTS_TMTRF_Msk              (0x6UL)        /*!< TMTRF (Bitfield-Mask: 0x03)                           */
+ #define R_CANFD_CFDTMSTS_TMTRM_Pos              (3UL)          /*!< TMTRM (Bit 3)                                         */
+ #define R_CANFD_CFDTMSTS_TMTRM_Msk              (0x8UL)        /*!< TMTRM (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTMSTS_TMTARM_Pos             (4UL)          /*!< TMTARM (Bit 4)                                        */
+ #define R_CANFD_CFDTMSTS_TMTARM_Msk             (0x10UL)       /*!< TMTARM (Bitfield-Mask: 0x01)                          */
+/* ======================================================  CFDTMTRSTS  ======================================================= */
+ #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos      (0UL)          /*!< CFDTMTRSTSg (Bit 0)                                   */
+ #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk      (0xfUL)        /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f)                     */
+/* ======================================================  CFDTMTARSTS  ====================================================== */
+ #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos    (0UL)          /*!< CFDTMTARSTSg (Bit 0)                                  */
+ #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk    (0xfUL)        /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f)                    */
+/* ======================================================  CFDTMTCSTS  ======================================================= */
+ #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos      (0UL)          /*!< CFDTMTCSTSg (Bit 0)                                   */
+ #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk      (0xfUL)        /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f)                     */
+/* ======================================================  CFDTMTASTS  ======================================================= */
+ #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos      (0UL)          /*!< CFDTMTASTSg (Bit 0)                                   */
+ #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk      (0xfUL)        /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f)                     */
+/* =======================================================  CFDTMIEC  ======================================================== */
+ #define R_CANFD_CFDTMIEC_TMIEg_Pos              (0UL)          /*!< TMIEg (Bit 0)                                         */
+ #define R_CANFD_CFDTMIEC_TMIEg_Msk              (0xfUL)        /*!< TMIEg (Bitfield-Mask: 0x0f)                           */
+/* =======================================================  CFDTXQCC0  ======================================================= */
+ #define R_CANFD_CFDTXQCC0_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
+ #define R_CANFD_CFDTXQCC0_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
+ #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDTXQCC0_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
+ #define R_CANFD_CFDTXQCC0_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTXQCC0_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
+ #define R_CANFD_CFDTXQCC0_TXQDC_Msk             (0x300UL)      /*!< TXQDC (Bitfield-Mask: 0x03)                           */
+/* ======================================================  CFDTXQSTS0  ======================================================= */
+ #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
+ #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
+ #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
+ #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDTXQSTS0_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
+ #define R_CANFD_CFDTXQSTS0_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
+/* ======================================================  CFDTXQPCTR0  ====================================================== */
+ #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
+ #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
+/* =======================================================  CFDTHLCC  ======================================================== */
+ #define R_CANFD_CFDTHLCC_THLE_Pos               (0UL)          /*!< THLE (Bit 0)                                          */
+ #define R_CANFD_CFDTHLCC_THLE_Msk               (0x1UL)        /*!< THLE (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDTHLCC_THLIE_Pos              (8UL)          /*!< THLIE (Bit 8)                                         */
+ #define R_CANFD_CFDTHLCC_THLIE_Msk              (0x100UL)      /*!< THLIE (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTHLCC_THLIM_Pos              (9UL)          /*!< THLIM (Bit 9)                                         */
+ #define R_CANFD_CFDTHLCC_THLIM_Msk              (0x200UL)      /*!< THLIM (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTHLCC_THLDTE_Pos             (10UL)         /*!< THLDTE (Bit 10)                                       */
+ #define R_CANFD_CFDTHLCC_THLDTE_Msk             (0x400UL)      /*!< THLDTE (Bitfield-Mask: 0x01)                          */
+/* =======================================================  CFDTHLSTS  ======================================================= */
+ #define R_CANFD_CFDTHLSTS_THLEMP_Pos            (0UL)          /*!< THLEMP (Bit 0)                                        */
+ #define R_CANFD_CFDTHLSTS_THLEMP_Msk            (0x1UL)        /*!< THLEMP (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTHLSTS_THLFLL_Pos            (1UL)          /*!< THLFLL (Bit 1)                                        */
+ #define R_CANFD_CFDTHLSTS_THLFLL_Msk            (0x2UL)        /*!< THLFLL (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTHLSTS_THLELT_Pos            (2UL)          /*!< THLELT (Bit 2)                                        */
+ #define R_CANFD_CFDTHLSTS_THLELT_Msk            (0x4UL)        /*!< THLELT (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDTHLSTS_THLIF_Pos             (3UL)          /*!< THLIF (Bit 3)                                         */
+ #define R_CANFD_CFDTHLSTS_THLIF_Msk             (0x8UL)        /*!< THLIF (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDTHLSTS_THLMC_Pos             (8UL)          /*!< THLMC (Bit 8)                                         */
+ #define R_CANFD_CFDTHLSTS_THLMC_Msk             (0x3f00UL)     /*!< THLMC (Bitfield-Mask: 0x3f)                           */
+/* ======================================================  CFDTHLPCTR  ======================================================= */
+ #define R_CANFD_CFDTHLPCTR_THLPC_Pos            (0UL)          /*!< THLPC (Bit 0)                                         */
+ #define R_CANFD_CFDTHLPCTR_THLPC_Msk            (0xffUL)       /*!< THLPC (Bitfield-Mask: 0xff)                           */
+/* =====================================================  CFDGTINTSTS0  ====================================================== */
+ #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos          (0UL)          /*!< TSIF0 (Bit 0)                                         */
+ #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk          (0x1UL)        /*!< TSIF0 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos          (1UL)          /*!< TAIF0 (Bit 1)                                         */
+ #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk          (0x2UL)        /*!< TAIF0 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos          (2UL)          /*!< TQIF0 (Bit 2)                                         */
+ #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk          (0x4UL)        /*!< TQIF0 (Bitfield-Mask: 0x01)                           */
+ #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos         (3UL)          /*!< CFTIF0 (Bit 3)                                        */
+ #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk         (0x8UL)        /*!< CFTIF0 (Bitfield-Mask: 0x01)                          */
+ #define R_CANFD_CFDGTINTSTS0_THIF0_Pos          (4UL)          /*!< THIF0 (Bit 4)                                         */
+ #define R_CANFD_CFDGTINTSTS0_THIF0_Msk          (0x10UL)       /*!< THIF0 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  CFDGTSTCFG  ======================================================= */
+ #define R_CANFD_CFDGTSTCFG_RTMPS_Pos            (16UL)         /*!< RTMPS (Bit 16)                                        */
+ #define R_CANFD_CFDGTSTCFG_RTMPS_Msk            (0x3ff0000UL)  /*!< RTMPS (Bitfield-Mask: 0x3ff)                          */
+/* ======================================================  CFDGTSTCTR  ======================================================= */
+ #define R_CANFD_CFDGTSTCTR_RTME_Pos             (2UL)          /*!< RTME (Bit 2)                                          */
+ #define R_CANFD_CFDGTSTCTR_RTME_Msk             (0x4UL)        /*!< RTME (Bitfield-Mask: 0x01)                            */
+/* =======================================================  CFDGFDCFG  ======================================================= */
+ #define R_CANFD_CFDGFDCFG_RPED_Pos              (0UL)          /*!< RPED (Bit 0)                                          */
+ #define R_CANFD_CFDGFDCFG_RPED_Msk              (0x1UL)        /*!< RPED (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGFDCFG_TSCCFG_Pos            (8UL)          /*!< TSCCFG (Bit 8)                                        */
+ #define R_CANFD_CFDGFDCFG_TSCCFG_Msk            (0x300UL)      /*!< TSCCFG (Bitfield-Mask: 0x03)                          */
+/* =======================================================  CFDGLOCKK  ======================================================= */
+ #define R_CANFD_CFDGLOCKK_LOCK_Pos              (0UL)          /*!< LOCK (Bit 0)                                          */
+ #define R_CANFD_CFDGLOCKK_LOCK_Msk              (0xffffUL)     /*!< LOCK (Bitfield-Mask: 0xffff)                          */
+/* =====================================================  CFDGAFLIGNENT  ===================================================== */
+ #define R_CANFD_CFDGAFLIGNENT_IRN_Pos           (0UL)          /*!< IRN (Bit 0)                                           */
+ #define R_CANFD_CFDGAFLIGNENT_IRN_Msk           (0x1fUL)       /*!< IRN (Bitfield-Mask: 0x1f)                             */
+/* =====================================================  CFDGAFLIGNCTR  ===================================================== */
+ #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos          (0UL)          /*!< IREN (Bit 0)                                          */
+ #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk          (0x1UL)        /*!< IREN (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos           (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk           (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+/* =======================================================  CFDCDTCT  ======================================================== */
+ #define R_CANFD_CFDCDTCT_RFDMAE0_Pos            (0UL)          /*!< RFDMAE0 (Bit 0)                                       */
+ #define R_CANFD_CFDCDTCT_RFDMAE0_Msk            (0x1UL)        /*!< RFDMAE0 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_RFDMAE1_Pos            (1UL)          /*!< RFDMAE1 (Bit 1)                                       */
+ #define R_CANFD_CFDCDTCT_RFDMAE1_Msk            (0x2UL)        /*!< RFDMAE1 (Bitfield-Mask: 0x01)                         */
+ #define R_CANFD_CFDCDTCT_CFDMAE0_Pos            (8UL)          /*!< CFDMAE0 (Bit 8)                                       */
+ #define R_CANFD_CFDCDTCT_CFDMAE0_Msk            (0x100UL)      /*!< CFDMAE0 (Bitfield-Mask: 0x01)                         */
+/* =======================================================  CFDCDTSTS  ======================================================= */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos         (0UL)          /*!< RFDMASTS0 (Bit 0)                                     */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk         (0x1UL)        /*!< RFDMASTS0 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos         (1UL)          /*!< RFDMASTS1 (Bit 1)                                     */
+ #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk         (0x2UL)        /*!< RFDMASTS1 (Bitfield-Mask: 0x01)                       */
+ #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos         (8UL)          /*!< CFDMASTS0 (Bit 8)                                     */
+ #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk         (0x100UL)      /*!< CFDMASTS0 (Bitfield-Mask: 0x01)                       */
+/* =======================================================  CFDGRSTC  ======================================================== */
+ #define R_CANFD_CFDGRSTC_SRST_Pos               (0UL)          /*!< SRST (Bit 0)                                          */
+ #define R_CANFD_CFDGRSTC_SRST_Msk               (0x1UL)        /*!< SRST (Bitfield-Mask: 0x01)                            */
+ #define R_CANFD_CFDGRSTC_KEY_Pos                (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_CANFD_CFDGRSTC_KEY_Msk                (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+/* =======================================================  CFDRPGACC  ======================================================= */
+ #define R_CANFD_CFDRPGACC_RDTA_Pos              (0UL)          /*!< RDTA (Bit 0)                                          */
+ #define R_CANFD_CFDRPGACC_RDTA_Msk              (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff)                      */
+
+/* =========================================================================================================================== */
+/* ================                                           R_CRC                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CRCCR0  ========================================================= */
+ #define R_CRC_CRCCR0_DORCLR_Pos          (7UL)          /*!< DORCLR (Bit 7)                                        */
+ #define R_CRC_CRCCR0_DORCLR_Msk          (0x80UL)       /*!< DORCLR (Bitfield-Mask: 0x01)                          */
+ #define R_CRC_CRCCR0_LMS_Pos             (6UL)          /*!< LMS (Bit 6)                                           */
+ #define R_CRC_CRCCR0_LMS_Msk             (0x40UL)       /*!< LMS (Bitfield-Mask: 0x01)                             */
+ #define R_CRC_CRCCR0_GPS_Pos             (0UL)          /*!< GPS (Bit 0)                                           */
+ #define R_CRC_CRCCR0_GPS_Msk             (0x7UL)        /*!< GPS (Bitfield-Mask: 0x07)                             */
+/* ========================================================  CRCCR1  ========================================================= */
+ #define R_CRC_CRCCR1_CRCSEN_Pos          (7UL)          /*!< CRCSEN (Bit 7)                                        */
+ #define R_CRC_CRCCR1_CRCSEN_Msk          (0x80UL)       /*!< CRCSEN (Bitfield-Mask: 0x01)                          */
+ #define R_CRC_CRCCR1_CRCSWR_Pos          (6UL)          /*!< CRCSWR (Bit 6)                                        */
+ #define R_CRC_CRCCR1_CRCSWR_Msk          (0x40UL)       /*!< CRCSWR (Bitfield-Mask: 0x01)                          */
+/* ========================================================  CRCDIR  ========================================================= */
+ #define R_CRC_CRCDIR_CRCDIR_Pos          (0UL)          /*!< CRCDIR (Bit 0)                                        */
+ #define R_CRC_CRCDIR_CRCDIR_Msk          (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff)                    */
+/* =======================================================  CRCDIR_BY  ======================================================= */
+ #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos    (0UL)          /*!< CRCDIR_BY (Bit 0)                                     */
+ #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk    (0xffUL)       /*!< CRCDIR_BY (Bitfield-Mask: 0xff)                       */
+/* ========================================================  CRCDOR  ========================================================= */
+ #define R_CRC_CRCDOR_CRCDOR_Pos          (0UL)          /*!< CRCDOR (Bit 0)                                        */
+ #define R_CRC_CRCDOR_CRCDOR_Msk          (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff)                    */
+/* =======================================================  CRCDOR_HA  ======================================================= */
+ #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos    (0UL)          /*!< CRCDOR_HA (Bit 0)                                     */
+ #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk    (0xffffUL)     /*!< CRCDOR_HA (Bitfield-Mask: 0xffff)                     */
+/* =======================================================  CRCDOR_BY  ======================================================= */
+ #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos    (0UL)          /*!< CRCDOR_BY (Bit 0)                                     */
+ #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk    (0xffUL)       /*!< CRCDOR_BY (Bitfield-Mask: 0xff)                       */
+/* ========================================================  CRCSAR  ========================================================= */
+ #define R_CRC_CRCSAR_CRCSA_Pos           (0UL)          /*!< CRCSA (Bit 0)                                         */
+ #define R_CRC_CRCSAR_CRCSA_Msk           (0x3fffUL)     /*!< CRCSA (Bitfield-Mask: 0x3fff)                         */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DAC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DACR  ========================================================== */
+ #define R_DAC_DACR_DAE_Pos            (5UL)      /*!< DAE (Bit 5)                                           */
+ #define R_DAC_DACR_DAE_Msk            (0x20UL)   /*!< DAE (Bitfield-Mask: 0x01)                             */
+ #define R_DAC_DACR_DAOE_Pos           (6UL)      /*!< DAOE (Bit 6)                                          */
+ #define R_DAC_DACR_DAOE_Msk           (0x40UL)   /*!< DAOE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  DADR  ========================================================== */
+ #define R_DAC_DADR_DADR_Pos           (0UL)      /*!< DADR (Bit 0)                                          */
+ #define R_DAC_DADR_DADR_Msk           (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  DADPR  ========================================================= */
+ #define R_DAC_DADPR_DPSEL_Pos         (7UL)      /*!< DPSEL (Bit 7)                                         */
+ #define R_DAC_DADPR_DPSEL_Msk         (0x80UL)   /*!< DPSEL (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DAADSCR  ======================================================== */
+ #define R_DAC_DAADSCR_DAADST_Pos      (7UL)      /*!< DAADST (Bit 7)                                        */
+ #define R_DAC_DAADSCR_DAADST_Msk      (0x80UL)   /*!< DAADST (Bitfield-Mask: 0x01)                          */
+/* =======================================================  DAVREFCR  ======================================================== */
+ #define R_DAC_DAVREFCR_REF_Pos        (0UL)      /*!< REF (Bit 0)                                           */
+ #define R_DAC_DAVREFCR_REF_Msk        (0x7UL)    /*!< REF (Bitfield-Mask: 0x07)                             */
+/* =========================================================  DAPC  ========================================================== */
+ #define R_DAC_DAPC_PUMPEN_Pos         (0UL)      /*!< PUMPEN (Bit 0)                                        */
+ #define R_DAC_DAPC_PUMPEN_Msk         (0x1UL)    /*!< PUMPEN (Bitfield-Mask: 0x01)                          */
+/* ========================================================  DAAMPCR  ======================================================== */
+ #define R_DAC_DAAMPCR_DAAMP_Pos       (6UL)      /*!< DAAMP (Bit 6)                                         */
+ #define R_DAC_DAAMPCR_DAAMP_Msk       (0x40UL)   /*!< DAAMP (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DAASWCR  ======================================================== */
+ #define R_DAC_DAASWCR_DAASW1_Pos      (7UL)      /*!< DAASW1 (Bit 7)                                        */
+ #define R_DAC_DAASWCR_DAASW1_Msk      (0x80UL)   /*!< DAASW1 (Bitfield-Mask: 0x01)                          */
+ #define R_DAC_DAASWCR_DAASW0_Pos      (6UL)      /*!< DAASW0 (Bit 6)                                        */
+ #define R_DAC_DAASWCR_DAASW0_Msk      (0x40UL)   /*!< DAASW0 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  DAADUSR  ======================================================== */
+ #define R_DAC_DAADUSR_AMADSEL0_Pos    (0UL)      /*!< AMADSEL0 (Bit 0)                                      */
+ #define R_DAC_DAADUSR_AMADSEL0_Msk    (0x1UL)    /*!< AMADSEL0 (Bitfield-Mask: 0x01)                        */
+ #define R_DAC_DAADUSR_AMADSEL1_Pos    (1UL)      /*!< AMADSEL1 (Bit 1)                                      */
+ #define R_DAC_DAADUSR_AMADSEL1_Msk    (0x2UL)    /*!< AMADSEL1 (Bitfield-Mask: 0x01)                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DEBUG                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  DBGSTR  ========================================================= */
+ #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos        (28UL)         /*!< CDBGPWRUPREQ (Bit 28)                                 */
+ #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk        (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01)                    */
+ #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos        (29UL)         /*!< CDBGPWRUPACK (Bit 29)                                 */
+ #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk        (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01)                    */
+/* =======================================================  DBGSTOPCR  ======================================================= */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos     (24UL)         /*!< DBGSTOP_RPER (Bit 24)                                 */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk     (0x1000000UL)  /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01)                    */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos      (16UL)         /*!< DBGSTOP_LVD (Bit 16)                                  */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk      (0x10000UL)    /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01)                     */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos    (25UL)         /*!< DBGSTOP_RECCR (Bit 25)                                */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk    (0x2000000UL)  /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01)                   */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos     (0UL)          /*!< DBGSTOP_IWDT (Bit 0)                                  */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk     (0x1UL)        /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01)                    */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos      (1UL)          /*!< DBGSTOP_WDT (Bit 1)                                   */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk      (0x2UL)        /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01)                     */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos     (31UL)         /*!< DBGSTOP_CPER (Bit 31)                                 */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk     (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01)                    */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DMA                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DMAST  ========================================================= */
+ #define R_DMA_DMAST_DMST_Pos         (0UL)       /*!< DMST (Bit 0)                                          */
+ #define R_DMA_DMAST_DMST_Msk         (0x1UL)     /*!< DMST (Bitfield-Mask: 0x01)                            */
+/* ========================================================  DMECHR  ========================================================= */
+ #define R_DMA_DMECHR_DMECH_Pos       (0UL)       /*!< DMECH (Bit 0)                                         */
+ #define R_DMA_DMECHR_DMECH_Msk       (0x7UL)     /*!< DMECH (Bitfield-Mask: 0x07)                           */
+ #define R_DMA_DMECHR_DMECHSAM_Pos    (8UL)       /*!< DMECHSAM (Bit 8)                                      */
+ #define R_DMA_DMECHR_DMECHSAM_Msk    (0x100UL)   /*!< DMECHSAM (Bitfield-Mask: 0x01)                        */
+ #define R_DMA_DMECHR_DMESTA_Pos      (16UL)      /*!< DMESTA (Bit 16)                                       */
+ #define R_DMA_DMECHR_DMESTA_Msk      (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01)                          */
+/* =========================================================  DELSR  ========================================================= */
+ #define R_DMA_DELSR_IR_Pos           (16UL)      /*!< IR (Bit 16)                                           */
+ #define R_DMA_DELSR_IR_Msk           (0x10000UL) /*!< IR (Bitfield-Mask: 0x01)                              */
+ #define R_DMA_DELSR_DELS_Pos         (0UL)       /*!< DELS (Bit 0)                                          */
+ #define R_DMA_DELSR_DELS_Msk         (0x1ffUL)   /*!< DELS (Bitfield-Mask: 0x1ff)                           */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DMAC0                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DMSAR  ========================================================= */
+ #define R_DMAC0_DMSAR_DMSAR_Pos     (0UL)          /*!< DMSAR (Bit 0)                                         */
+ #define R_DMAC0_DMSAR_DMSAR_Msk     (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  DMDAR  ========================================================= */
+ #define R_DMAC0_DMDAR_DMDAR_Pos     (0UL)          /*!< DMDAR (Bit 0)                                         */
+ #define R_DMAC0_DMDAR_DMDAR_Msk     (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  DMCRA  ========================================================= */
+ #define R_DMAC0_DMCRA_DMCRAH_Pos    (16UL)         /*!< DMCRAH (Bit 16)                                       */
+ #define R_DMAC0_DMCRA_DMCRAH_Msk    (0x3ff0000UL)  /*!< DMCRAH (Bitfield-Mask: 0x3ff)                         */
+ #define R_DMAC0_DMCRA_DMCRAL_Pos    (0UL)          /*!< DMCRAL (Bit 0)                                        */
+ #define R_DMAC0_DMCRA_DMCRAL_Msk    (0xffffUL)     /*!< DMCRAL (Bitfield-Mask: 0xffff)                        */
+/* =========================================================  DMCRB  ========================================================= */
+ #define R_DMAC0_DMCRB_DMCRBL_Pos    (0UL)          /*!< DMCRBL (Bit 0)                                        */
+ #define R_DMAC0_DMCRB_DMCRBL_Msk    (0xffffUL)     /*!< DMCRBL (Bitfield-Mask: 0xffff)                        */
+ #define R_DMAC0_DMCRB_DMCRBH_Pos    (16UL)         /*!< DMCRBH (Bit 16)                                       */
+ #define R_DMAC0_DMCRB_DMCRBH_Msk    (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff)                        */
+/* =========================================================  DMTMD  ========================================================= */
+ #define R_DMAC0_DMTMD_MD_Pos        (14UL)         /*!< MD (Bit 14)                                           */
+ #define R_DMAC0_DMTMD_MD_Msk        (0xc000UL)     /*!< MD (Bitfield-Mask: 0x03)                              */
+ #define R_DMAC0_DMTMD_DTS_Pos       (12UL)         /*!< DTS (Bit 12)                                          */
+ #define R_DMAC0_DMTMD_DTS_Msk       (0x3000UL)     /*!< DTS (Bitfield-Mask: 0x03)                             */
+ #define R_DMAC0_DMTMD_SZ_Pos        (8UL)          /*!< SZ (Bit 8)                                            */
+ #define R_DMAC0_DMTMD_SZ_Msk        (0x300UL)      /*!< SZ (Bitfield-Mask: 0x03)                              */
+ #define R_DMAC0_DMTMD_DCTG_Pos      (0UL)          /*!< DCTG (Bit 0)                                          */
+ #define R_DMAC0_DMTMD_DCTG_Msk      (0x3UL)        /*!< DCTG (Bitfield-Mask: 0x03)                            */
+ #define R_DMAC0_DMTMD_TKP_Pos       (10UL)         /*!< TKP (Bit 10)                                          */
+ #define R_DMAC0_DMTMD_TKP_Msk       (0x400UL)      /*!< TKP (Bitfield-Mask: 0x01)                             */
+/* =========================================================  DMINT  ========================================================= */
+ #define R_DMAC0_DMINT_DTIE_Pos      (4UL)          /*!< DTIE (Bit 4)                                          */
+ #define R_DMAC0_DMINT_DTIE_Msk      (0x10UL)       /*!< DTIE (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_DMINT_ESIE_Pos      (3UL)          /*!< ESIE (Bit 3)                                          */
+ #define R_DMAC0_DMINT_ESIE_Msk      (0x8UL)        /*!< ESIE (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_DMINT_RPTIE_Pos     (2UL)          /*!< RPTIE (Bit 2)                                         */
+ #define R_DMAC0_DMINT_RPTIE_Msk     (0x4UL)        /*!< RPTIE (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_DMINT_SARIE_Pos     (1UL)          /*!< SARIE (Bit 1)                                         */
+ #define R_DMAC0_DMINT_SARIE_Msk     (0x2UL)        /*!< SARIE (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_DMINT_DARIE_Pos     (0UL)          /*!< DARIE (Bit 0)                                         */
+ #define R_DMAC0_DMINT_DARIE_Msk     (0x1UL)        /*!< DARIE (Bitfield-Mask: 0x01)                           */
+/* =========================================================  DMAMD  ========================================================= */
+ #define R_DMAC0_DMAMD_SM_Pos        (14UL)         /*!< SM (Bit 14)                                           */
+ #define R_DMAC0_DMAMD_SM_Msk        (0xc000UL)     /*!< SM (Bitfield-Mask: 0x03)                              */
+ #define R_DMAC0_DMAMD_SARA_Pos      (8UL)          /*!< SARA (Bit 8)                                          */
+ #define R_DMAC0_DMAMD_SARA_Msk      (0x1f00UL)     /*!< SARA (Bitfield-Mask: 0x1f)                            */
+ #define R_DMAC0_DMAMD_DM_Pos        (6UL)          /*!< DM (Bit 6)                                            */
+ #define R_DMAC0_DMAMD_DM_Msk        (0xc0UL)       /*!< DM (Bitfield-Mask: 0x03)                              */
+ #define R_DMAC0_DMAMD_DARA_Pos      (0UL)          /*!< DARA (Bit 0)                                          */
+ #define R_DMAC0_DMAMD_DARA_Msk      (0x1fUL)       /*!< DARA (Bitfield-Mask: 0x1f)                            */
+ #define R_DMAC0_DMAMD_DADR_Pos      (5UL)          /*!< DADR (Bit 5)                                          */
+ #define R_DMAC0_DMAMD_DADR_Msk      (0x20UL)       /*!< DADR (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_DMAMD_SADR_Pos      (13UL)         /*!< SADR (Bit 13)                                         */
+ #define R_DMAC0_DMAMD_SADR_Msk      (0x2000UL)     /*!< SADR (Bitfield-Mask: 0x01)                            */
+/* =========================================================  DMOFR  ========================================================= */
+ #define R_DMAC0_DMOFR_DMOFR_Pos     (0UL)          /*!< DMOFR (Bit 0)                                         */
+ #define R_DMAC0_DMOFR_DMOFR_Msk     (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  DMCNT  ========================================================= */
+ #define R_DMAC0_DMCNT_DTE_Pos       (0UL)          /*!< DTE (Bit 0)                                           */
+ #define R_DMAC0_DMCNT_DTE_Msk       (0x1UL)        /*!< DTE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  DMREQ  ========================================================= */
+ #define R_DMAC0_DMREQ_CLRS_Pos      (4UL)          /*!< CLRS (Bit 4)                                          */
+ #define R_DMAC0_DMREQ_CLRS_Msk      (0x10UL)       /*!< CLRS (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_DMREQ_SWREQ_Pos     (0UL)          /*!< SWREQ (Bit 0)                                         */
+ #define R_DMAC0_DMREQ_SWREQ_Msk     (0x1UL)        /*!< SWREQ (Bitfield-Mask: 0x01)                           */
+/* =========================================================  DMSTS  ========================================================= */
+ #define R_DMAC0_DMSTS_ACT_Pos       (7UL)          /*!< ACT (Bit 7)                                           */
+ #define R_DMAC0_DMSTS_ACT_Msk       (0x80UL)       /*!< ACT (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_DMSTS_DTIF_Pos      (4UL)          /*!< DTIF (Bit 4)                                          */
+ #define R_DMAC0_DMSTS_DTIF_Msk      (0x10UL)       /*!< DTIF (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_DMSTS_ESIF_Pos      (0UL)          /*!< ESIF (Bit 0)                                          */
+ #define R_DMAC0_DMSTS_ESIF_Msk      (0x1UL)        /*!< ESIF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  DMSRR  ========================================================= */
+/* =========================================================  DMDRR  ========================================================= */
+/* =========================================================  DMSBS  ========================================================= */
+ #define R_DMAC0_DMSBS_DMSBSL_Pos    (0UL)          /*!< DMSBSL (Bit 0)                                        */
+ #define R_DMAC0_DMSBS_DMSBSL_Msk    (0xffffUL)     /*!< DMSBSL (Bitfield-Mask: 0xffff)                        */
+ #define R_DMAC0_DMSBS_DMSBSH_Pos    (16UL)         /*!< DMSBSH (Bit 16)                                       */
+ #define R_DMAC0_DMSBS_DMSBSH_Msk    (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff)                        */
+/* =========================================================  DMDBS  ========================================================= */
+ #define R_DMAC0_DMDBS_DMDBSL_Pos    (0UL)          /*!< DMDBSL (Bit 0)                                        */
+ #define R_DMAC0_DMDBS_DMDBSL_Msk    (0xffffUL)     /*!< DMDBSL (Bitfield-Mask: 0xffff)                        */
+ #define R_DMAC0_DMDBS_DMDBSH_Pos    (16UL)         /*!< DMDBSH (Bit 16)                                       */
+ #define R_DMAC0_DMDBS_DMDBSH_Msk    (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff)                        */
+/* =========================================================  DMBWR  ========================================================= */
+ #define R_DMAC0_DMBWR_BWE_Pos       (0UL)          /*!< BWE (Bit 0)                                           */
+ #define R_DMAC0_DMBWR_BWE_Msk       (0x1UL)        /*!< BWE (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DOC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DOCR  ========================================================== */
+ #define R_DOC_DOCR_DOPCFCL_Pos    (6UL)      /*!< DOPCFCL (Bit 6)                                       */
+ #define R_DOC_DOCR_DOPCFCL_Msk    (0x40UL)   /*!< DOPCFCL (Bitfield-Mask: 0x01)                         */
+ #define R_DOC_DOCR_DOPCF_Pos      (5UL)      /*!< DOPCF (Bit 5)                                         */
+ #define R_DOC_DOCR_DOPCF_Msk      (0x20UL)   /*!< DOPCF (Bitfield-Mask: 0x01)                           */
+ #define R_DOC_DOCR_DCSEL_Pos      (2UL)      /*!< DCSEL (Bit 2)                                         */
+ #define R_DOC_DOCR_DCSEL_Msk      (0x4UL)    /*!< DCSEL (Bitfield-Mask: 0x01)                           */
+ #define R_DOC_DOCR_OMS_Pos        (0UL)      /*!< OMS (Bit 0)                                           */
+ #define R_DOC_DOCR_OMS_Msk        (0x3UL)    /*!< OMS (Bitfield-Mask: 0x03)                             */
+/* =========================================================  DODIR  ========================================================= */
+ #define R_DOC_DODIR_DODIR_Pos     (0UL)      /*!< DODIR (Bit 0)                                         */
+ #define R_DOC_DODIR_DODIR_Msk     (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  DODSR  ========================================================= */
+ #define R_DOC_DODSR_DODSR_Pos     (0UL)      /*!< DODSR (Bit 0)                                         */
+ #define R_DOC_DODSR_DODSR_Msk     (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff)                         */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DTC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DTCCR  ========================================================= */
+ #define R_DTC_DTCCR_RRS_Pos         (4UL)          /*!< RRS (Bit 4)                                           */
+ #define R_DTC_DTCCR_RRS_Msk         (0x10UL)       /*!< RRS (Bitfield-Mask: 0x01)                             */
+/* ========================================================  DTCVBR  ========================================================= */
+ #define R_DTC_DTCVBR_DTCVBR_Pos     (0UL)          /*!< DTCVBR (Bit 0)                                        */
+ #define R_DTC_DTCVBR_DTCVBR_Msk     (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff)                    */
+/* =========================================================  DTCST  ========================================================= */
+ #define R_DTC_DTCST_DTCST_Pos       (0UL)          /*!< DTCST (Bit 0)                                         */
+ #define R_DTC_DTCST_DTCST_Msk       (0x1UL)        /*!< DTCST (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DTCSTS  ========================================================= */
+ #define R_DTC_DTCSTS_ACT_Pos        (15UL)         /*!< ACT (Bit 15)                                          */
+ #define R_DTC_DTCSTS_ACT_Msk        (0x8000UL)     /*!< ACT (Bitfield-Mask: 0x01)                             */
+ #define R_DTC_DTCSTS_VECN_Pos       (0UL)          /*!< VECN (Bit 0)                                          */
+ #define R_DTC_DTCSTS_VECN_Msk       (0xffUL)       /*!< VECN (Bitfield-Mask: 0xff)                            */
+/* =======================================================  DTCCR_SEC  ======================================================= */
+ #define R_DTC_DTCCR_SEC_RRSS_Pos    (4UL)          /*!< RRSS (Bit 4)                                          */
+ #define R_DTC_DTCCR_SEC_RRSS_Msk    (0x10UL)       /*!< RRSS (Bitfield-Mask: 0x01)                            */
+/* ======================================================  DTCVBR_SEC  ======================================================= */
+/* =========================================================  DTEVR  ========================================================= */
+ #define R_DTC_DTEVR_DTEV_Pos        (0UL)          /*!< DTEV (Bit 0)                                          */
+ #define R_DTC_DTEVR_DTEV_Msk        (0xffUL)       /*!< DTEV (Bitfield-Mask: 0xff)                            */
+ #define R_DTC_DTEVR_DTEVSAM_Pos     (8UL)          /*!< DTEVSAM (Bit 8)                                       */
+ #define R_DTC_DTEVR_DTEVSAM_Msk     (0x100UL)      /*!< DTEVSAM (Bitfield-Mask: 0x01)                         */
+ #define R_DTC_DTEVR_DTESTA_Pos      (16UL)         /*!< DTESTA (Bit 16)                                       */
+ #define R_DTC_DTEVR_DTESTA_Msk      (0x10000UL)    /*!< DTESTA (Bitfield-Mask: 0x01)                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ELC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ELCR  ========================================================== */
+ #define R_ELC_ELCR_ELCON_Pos         (7UL)      /*!< ELCON (Bit 7)                                         */
+ #define R_ELC_ELCR_ELCON_Msk         (0x80UL)   /*!< ELCON (Bitfield-Mask: 0x01)                           */
+/* ========================================================  ELCSARA  ======================================================== */
+ #define R_ELC_ELCSARA_ELCR_Pos       (0UL)      /*!< ELCR (Bit 0)                                          */
+ #define R_ELC_ELCSARA_ELCR_Msk       (0x1UL)    /*!< ELCR (Bitfield-Mask: 0x01)                            */
+ #define R_ELC_ELCSARA_ELSEGR0_Pos    (1UL)      /*!< ELSEGR0 (Bit 1)                                       */
+ #define R_ELC_ELCSARA_ELSEGR0_Msk    (0x2UL)    /*!< ELSEGR0 (Bitfield-Mask: 0x01)                         */
+ #define R_ELC_ELCSARA_ELSEGR1_Pos    (2UL)      /*!< ELSEGR1 (Bit 2)                                       */
+ #define R_ELC_ELCSARA_ELSEGR1_Msk    (0x4UL)    /*!< ELSEGR1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ELCSARB  ======================================================== */
+ #define R_ELC_ELCSARB_ELSR0_Pos      (0UL)      /*!< ELSR0 (Bit 0)                                         */
+ #define R_ELC_ELCSARB_ELSR0_Msk      (0x1UL)    /*!< ELSR0 (Bitfield-Mask: 0x01)                           */
+ #define R_ELC_ELCSARB_ELSR1_Pos      (1UL)      /*!< ELSR1 (Bit 1)                                         */
+ #define R_ELC_ELCSARB_ELSR1_Msk      (0x2UL)    /*!< ELSR1 (Bitfield-Mask: 0x01)                           */
+ #define R_ELC_ELCSARB_ELSR2_Pos      (2UL)      /*!< ELSR2 (Bit 2)                                         */
+ #define R_ELC_ELCSARB_ELSR2_Msk      (0x4UL)    /*!< ELSR2 (Bitfield-Mask: 0x01)                           */
+ #define R_ELC_ELCSARB_ELSR3_Pos      (3UL)      /*!< ELSR3 (Bit 3)                                         */
+ #define R_ELC_ELCSARB_ELSR3_Msk      (0x8UL)    /*!< ELSR3 (Bitfield-Mask: 0x01)                           */
+ #define R_ELC_ELCSARB_ELSR4_Pos      (4UL)      /*!< ELSR4 (Bit 4)                                         */
+ #define R_ELC_ELCSARB_ELSR4_Msk      (0x10UL)   /*!< ELSR4 (Bitfield-Mask: 0x01)                           */
+ #define R_ELC_ELCSARB_ELSR5_Pos      (5UL)      /*!< ELSR5 (Bit 5)                                         */
+ #define R_ELC_ELCSARB_ELSR5_Msk      (0x20UL)   /*!< ELSR5 (Bitfield-Mask: 0x01)                           */
+ #define R_ELC_ELCSARB_ELSR6_Pos      (6UL)      /*!< ELSR6 (Bit 6)                                         */
+ #define R_ELC_ELCSARB_ELSR6_Msk      (0x40UL)   /*!< ELSR6 (Bitfield-Mask: 0x01)                           */
+ #define R_ELC_ELCSARB_ELSR7_Pos      (7UL)      /*!< ELSR7 (Bit 7)                                         */
+ #define R_ELC_ELCSARB_ELSR7_Msk      (0x80UL)   /*!< ELSR7 (Bitfield-Mask: 0x01)                           */
+ #define R_ELC_ELCSARB_ELSR8_Pos      (8UL)      /*!< ELSR8 (Bit 8)                                         */
+ #define R_ELC_ELCSARB_ELSR8_Msk      (0x100UL)  /*!< ELSR8 (Bitfield-Mask: 0x01)                           */
+ #define R_ELC_ELCSARB_ELSR9_Pos      (9UL)      /*!< ELSR9 (Bit 9)                                         */
+ #define R_ELC_ELCSARB_ELSR9_Msk      (0x200UL)  /*!< ELSR9 (Bitfield-Mask: 0x01)                           */
+ #define R_ELC_ELCSARB_ELSR10_Pos     (10UL)     /*!< ELSR10 (Bit 10)                                       */
+ #define R_ELC_ELCSARB_ELSR10_Msk     (0x400UL)  /*!< ELSR10 (Bitfield-Mask: 0x01)                          */
+ #define R_ELC_ELCSARB_ELSR11_Pos     (11UL)     /*!< ELSR11 (Bit 11)                                       */
+ #define R_ELC_ELCSARB_ELSR11_Msk     (0x800UL)  /*!< ELSR11 (Bitfield-Mask: 0x01)                          */
+ #define R_ELC_ELCSARB_ELSR12_Pos     (12UL)     /*!< ELSR12 (Bit 12)                                       */
+ #define R_ELC_ELCSARB_ELSR12_Msk     (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01)                          */
+ #define R_ELC_ELCSARB_ELSR13_Pos     (13UL)     /*!< ELSR13 (Bit 13)                                       */
+ #define R_ELC_ELCSARB_ELSR13_Msk     (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01)                          */
+ #define R_ELC_ELCSARB_ELSR14_Pos     (14UL)     /*!< ELSR14 (Bit 14)                                       */
+ #define R_ELC_ELCSARB_ELSR14_Msk     (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01)                          */
+ #define R_ELC_ELCSARB_ELSR15_Pos     (15UL)     /*!< ELSR15 (Bit 15)                                       */
+ #define R_ELC_ELCSARB_ELSR15_Msk     (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  ELCSARC  ======================================================== */
+ #define R_ELC_ELCSARC_ELSR16_Pos     (0UL)      /*!< ELSR16 (Bit 0)                                        */
+ #define R_ELC_ELCSARC_ELSR16_Msk     (0x1UL)    /*!< ELSR16 (Bitfield-Mask: 0x01)                          */
+ #define R_ELC_ELCSARC_ELSR17_Pos     (1UL)      /*!< ELSR17 (Bit 1)                                        */
+ #define R_ELC_ELCSARC_ELSR17_Msk     (0x2UL)    /*!< ELSR17 (Bitfield-Mask: 0x01)                          */
+ #define R_ELC_ELCSARC_ELSR18_Pos     (2UL)      /*!< ELSR18 (Bit 2)                                        */
+ #define R_ELC_ELCSARC_ELSR18_Msk     (0x4UL)    /*!< ELSR18 (Bitfield-Mask: 0x01)                          */
+
+/* =========================================================================================================================== */
+/* ================                                       R_FACI_HP_CMD                                       ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================  FACI_CMD16  ======================================================= */
+/* =======================================================  FACI_CMD8  ======================================================= */
+
+/* =========================================================================================================================== */
+/* ================                                         R_FACI_HP                                         ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  FASTAT  ========================================================= */
+ #define R_FACI_HP_FASTAT_CFAE_Pos         (7UL)          /*!< CFAE (Bit 7)                                          */
+ #define R_FACI_HP_FASTAT_CFAE_Msk         (0x80UL)       /*!< CFAE (Bitfield-Mask: 0x01)                            */
+ #define R_FACI_HP_FASTAT_CMDLK_Pos        (4UL)          /*!< CMDLK (Bit 4)                                         */
+ #define R_FACI_HP_FASTAT_CMDLK_Msk        (0x10UL)       /*!< CMDLK (Bitfield-Mask: 0x01)                           */
+ #define R_FACI_HP_FASTAT_DFAE_Pos         (3UL)          /*!< DFAE (Bit 3)                                          */
+ #define R_FACI_HP_FASTAT_DFAE_Msk         (0x8UL)        /*!< DFAE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  FAEINT  ========================================================= */
+ #define R_FACI_HP_FAEINT_CFAEIE_Pos       (7UL)          /*!< CFAEIE (Bit 7)                                        */
+ #define R_FACI_HP_FAEINT_CFAEIE_Msk       (0x80UL)       /*!< CFAEIE (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FAEINT_CMDLKIE_Pos      (4UL)          /*!< CMDLKIE (Bit 4)                                       */
+ #define R_FACI_HP_FAEINT_CMDLKIE_Msk      (0x10UL)       /*!< CMDLKIE (Bitfield-Mask: 0x01)                         */
+ #define R_FACI_HP_FAEINT_DFAEIE_Pos       (3UL)          /*!< DFAEIE (Bit 3)                                        */
+ #define R_FACI_HP_FAEINT_DFAEIE_Msk       (0x8UL)        /*!< DFAEIE (Bitfield-Mask: 0x01)                          */
+/* ========================================================  FRDYIE  ========================================================= */
+ #define R_FACI_HP_FRDYIE_FRDYIE_Pos       (0UL)          /*!< FRDYIE (Bit 0)                                        */
+ #define R_FACI_HP_FRDYIE_FRDYIE_Msk       (0x1UL)        /*!< FRDYIE (Bitfield-Mask: 0x01)                          */
+/* ========================================================  FSADDR  ========================================================= */
+ #define R_FACI_HP_FSADDR_FSA_Pos          (0UL)          /*!< FSA (Bit 0)                                           */
+ #define R_FACI_HP_FSADDR_FSA_Msk          (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  FEADDR  ========================================================= */
+ #define R_FACI_HP_FEADDR_FEA_Pos          (0UL)          /*!< FEA (Bit 0)                                           */
+ #define R_FACI_HP_FEADDR_FEA_Msk          (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  FMEPROT  ======================================================== */
+ #define R_FACI_HP_FMEPROT_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_FACI_HP_FMEPROT_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_FACI_HP_FMEPROT_CEPROT_Pos      (0UL)          /*!< CEPROT (Bit 0)                                        */
+ #define R_FACI_HP_FMEPROT_CEPROT_Msk      (0x1UL)        /*!< CEPROT (Bitfield-Mask: 0x01)                          */
+/* ========================================================  FBPROT0  ======================================================== */
+ #define R_FACI_HP_FBPROT0_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_FACI_HP_FBPROT0_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_FACI_HP_FBPROT0_BPCN0_Pos       (0UL)          /*!< BPCN0 (Bit 0)                                         */
+ #define R_FACI_HP_FBPROT0_BPCN0_Msk       (0x1UL)        /*!< BPCN0 (Bitfield-Mask: 0x01)                           */
+/* ========================================================  FBPROT1  ======================================================== */
+ #define R_FACI_HP_FBPROT1_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_FACI_HP_FBPROT1_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_FACI_HP_FBPROT1_BPCN1_Pos       (0UL)          /*!< BPCN1 (Bit 0)                                         */
+ #define R_FACI_HP_FBPROT1_BPCN1_Msk       (0x1UL)        /*!< BPCN1 (Bitfield-Mask: 0x01)                           */
+/* ========================================================  FSTATR  ========================================================= */
+ #define R_FACI_HP_FSTATR_ILGCOMERR_Pos    (23UL)         /*!< ILGCOMERR (Bit 23)                                    */
+ #define R_FACI_HP_FSTATR_ILGCOMERR_Msk    (0x800000UL)   /*!< ILGCOMERR (Bitfield-Mask: 0x01)                       */
+ #define R_FACI_HP_FSTATR_FESETERR_Pos     (22UL)         /*!< FESETERR (Bit 22)                                     */
+ #define R_FACI_HP_FSTATR_FESETERR_Msk     (0x400000UL)   /*!< FESETERR (Bitfield-Mask: 0x01)                        */
+ #define R_FACI_HP_FSTATR_SECERR_Pos       (21UL)         /*!< SECERR (Bit 21)                                       */
+ #define R_FACI_HP_FSTATR_SECERR_Msk       (0x200000UL)   /*!< SECERR (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_OTERR_Pos        (20UL)         /*!< OTERR (Bit 20)                                        */
+ #define R_FACI_HP_FSTATR_OTERR_Msk        (0x100000UL)   /*!< OTERR (Bitfield-Mask: 0x01)                           */
+ #define R_FACI_HP_FSTATR_FRDY_Pos         (15UL)         /*!< FRDY (Bit 15)                                         */
+ #define R_FACI_HP_FSTATR_FRDY_Msk         (0x8000UL)     /*!< FRDY (Bitfield-Mask: 0x01)                            */
+ #define R_FACI_HP_FSTATR_ILGLERR_Pos      (14UL)         /*!< ILGLERR (Bit 14)                                      */
+ #define R_FACI_HP_FSTATR_ILGLERR_Msk      (0x4000UL)     /*!< ILGLERR (Bitfield-Mask: 0x01)                         */
+ #define R_FACI_HP_FSTATR_ERSERR_Pos       (13UL)         /*!< ERSERR (Bit 13)                                       */
+ #define R_FACI_HP_FSTATR_ERSERR_Msk       (0x2000UL)     /*!< ERSERR (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_PRGERR_Pos       (12UL)         /*!< PRGERR (Bit 12)                                       */
+ #define R_FACI_HP_FSTATR_PRGERR_Msk       (0x1000UL)     /*!< PRGERR (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_SUSRDY_Pos       (11UL)         /*!< SUSRDY (Bit 11)                                       */
+ #define R_FACI_HP_FSTATR_SUSRDY_Msk       (0x800UL)      /*!< SUSRDY (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_DBFULL_Pos       (10UL)         /*!< DBFULL (Bit 10)                                       */
+ #define R_FACI_HP_FSTATR_DBFULL_Msk       (0x400UL)      /*!< DBFULL (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_ERSSPD_Pos       (9UL)          /*!< ERSSPD (Bit 9)                                        */
+ #define R_FACI_HP_FSTATR_ERSSPD_Msk       (0x200UL)      /*!< ERSSPD (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_PRGSPD_Pos       (8UL)          /*!< PRGSPD (Bit 8)                                        */
+ #define R_FACI_HP_FSTATR_PRGSPD_Msk       (0x100UL)      /*!< PRGSPD (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_FLWEERR_Pos      (6UL)          /*!< FLWEERR (Bit 6)                                       */
+ #define R_FACI_HP_FSTATR_FLWEERR_Msk      (0x40UL)       /*!< FLWEERR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  FENTRYR  ======================================================== */
+ #define R_FACI_HP_FENTRYR_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_FACI_HP_FENTRYR_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_FACI_HP_FENTRYR_FENTRYD_Pos     (7UL)          /*!< FENTRYD (Bit 7)                                       */
+ #define R_FACI_HP_FENTRYR_FENTRYD_Msk     (0x80UL)       /*!< FENTRYD (Bitfield-Mask: 0x01)                         */
+ #define R_FACI_HP_FENTRYR_FENTRYC_Pos     (0UL)          /*!< FENTRYC (Bit 0)                                       */
+ #define R_FACI_HP_FENTRYR_FENTRYC_Msk     (0x1UL)        /*!< FENTRYC (Bitfield-Mask: 0x01)                         */
+/* =======================================================  FSUINITR  ======================================================== */
+ #define R_FACI_HP_FSUINITR_KEY_Pos        (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_FACI_HP_FSUINITR_KEY_Msk        (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_FACI_HP_FSUINITR_SUINIT_Pos     (0UL)          /*!< SUINIT (Bit 0)                                        */
+ #define R_FACI_HP_FSUINITR_SUINIT_Msk     (0x1UL)        /*!< SUINIT (Bitfield-Mask: 0x01)                          */
+/* =========================================================  FCMDR  ========================================================= */
+ #define R_FACI_HP_FCMDR_CMDR_Pos          (8UL)          /*!< CMDR (Bit 8)                                          */
+ #define R_FACI_HP_FCMDR_CMDR_Msk          (0xff00UL)     /*!< CMDR (Bitfield-Mask: 0xff)                            */
+ #define R_FACI_HP_FCMDR_PCMDR_Pos         (0UL)          /*!< PCMDR (Bit 0)                                         */
+ #define R_FACI_HP_FCMDR_PCMDR_Msk         (0xffUL)       /*!< PCMDR (Bitfield-Mask: 0xff)                           */
+/* ========================================================  FBCCNT  ========================================================= */
+ #define R_FACI_HP_FBCCNT_BCDIR_Pos        (0UL)          /*!< BCDIR (Bit 0)                                         */
+ #define R_FACI_HP_FBCCNT_BCDIR_Msk        (0x1UL)        /*!< BCDIR (Bitfield-Mask: 0x01)                           */
+/* ========================================================  FBCSTAT  ======================================================== */
+ #define R_FACI_HP_FBCSTAT_BCST_Pos        (0UL)          /*!< BCST (Bit 0)                                          */
+ #define R_FACI_HP_FBCSTAT_BCST_Msk        (0x1UL)        /*!< BCST (Bitfield-Mask: 0x01)                            */
+/* ========================================================  FPSADDR  ======================================================== */
+ #define R_FACI_HP_FPSADDR_PSADR_Pos       (0UL)          /*!< PSADR (Bit 0)                                         */
+ #define R_FACI_HP_FPSADDR_PSADR_Msk       (0x7ffffUL)    /*!< PSADR (Bitfield-Mask: 0x7ffff)                        */
+/* ========================================================  FAWMON  ========================================================= */
+ #define R_FACI_HP_FAWMON_BTFLG_Pos        (31UL)         /*!< BTFLG (Bit 31)                                        */
+ #define R_FACI_HP_FAWMON_BTFLG_Msk        (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01)                           */
+ #define R_FACI_HP_FAWMON_FAWE_Pos         (16UL)         /*!< FAWE (Bit 16)                                         */
+ #define R_FACI_HP_FAWMON_FAWE_Msk         (0x7ff0000UL)  /*!< FAWE (Bitfield-Mask: 0x7ff)                           */
+ #define R_FACI_HP_FAWMON_FSPR_Pos         (15UL)         /*!< FSPR (Bit 15)                                         */
+ #define R_FACI_HP_FAWMON_FSPR_Msk         (0x8000UL)     /*!< FSPR (Bitfield-Mask: 0x01)                            */
+ #define R_FACI_HP_FAWMON_FAWS_Pos         (0UL)          /*!< FAWS (Bit 0)                                          */
+ #define R_FACI_HP_FAWMON_FAWS_Msk         (0x7ffUL)      /*!< FAWS (Bitfield-Mask: 0x7ff)                           */
+/* =========================================================  FCPSR  ========================================================= */
+ #define R_FACI_HP_FCPSR_ESUSPMD_Pos       (0UL)          /*!< ESUSPMD (Bit 0)                                       */
+ #define R_FACI_HP_FCPSR_ESUSPMD_Msk       (0x1UL)        /*!< ESUSPMD (Bitfield-Mask: 0x01)                         */
+/* ========================================================  FPCKAR  ========================================================= */
+ #define R_FACI_HP_FPCKAR_KEY_Pos          (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_FACI_HP_FPCKAR_KEY_Msk          (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_FACI_HP_FPCKAR_PCKA_Pos         (0UL)          /*!< PCKA (Bit 0)                                          */
+ #define R_FACI_HP_FPCKAR_PCKA_Msk         (0xffUL)       /*!< PCKA (Bitfield-Mask: 0xff)                            */
+/* ========================================================  FSUACR  ========================================================= */
+ #define R_FACI_HP_FSUACR_KEY_Pos          (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_FACI_HP_FSUACR_KEY_Msk          (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_FACI_HP_FSUACR_SAS_Pos          (0UL)          /*!< SAS (Bit 0)                                           */
+ #define R_FACI_HP_FSUACR_SAS_Msk          (0x3UL)        /*!< SAS (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                         R_FCACHE                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  FCACHEE  ======================================================== */
+ #define R_FCACHE_FCACHEE_FCACHEEN_Pos     (0UL)     /*!< FCACHEEN (Bit 0)                                      */
+ #define R_FCACHE_FCACHEE_FCACHEEN_Msk     (0x1UL)   /*!< FCACHEEN (Bitfield-Mask: 0x01)                        */
+/* =======================================================  FCACHEIV  ======================================================== */
+ #define R_FCACHE_FCACHEIV_FCACHEIV_Pos    (0UL)     /*!< FCACHEIV (Bit 0)                                      */
+ #define R_FCACHE_FCACHEIV_FCACHEIV_Msk    (0x1UL)   /*!< FCACHEIV (Bitfield-Mask: 0x01)                        */
+/* =========================================================  FLWT  ========================================================== */
+ #define R_FCACHE_FLWT_FLWT_Pos            (0UL)     /*!< FLWT (Bit 0)                                          */
+ #define R_FCACHE_FLWT_FLWT_Msk            (0x7UL)   /*!< FLWT (Bitfield-Mask: 0x07)                            */
+/* =========================================================  FSAR  ========================================================== */
+ #define R_FCACHE_FSAR_FLWTSA_Pos          (0UL)     /*!< FLWTSA (Bit 0)                                        */
+ #define R_FCACHE_FSAR_FLWTSA_Msk          (0x1UL)   /*!< FLWTSA (Bitfield-Mask: 0x01)                          */
+ #define R_FCACHE_FSAR_FCKMHZSA_Pos        (8UL)     /*!< FCKMHZSA (Bit 8)                                      */
+ #define R_FCACHE_FSAR_FCKMHZSA_Msk        (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01)                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_GPT0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  GTWP  ========================================================== */
+ #define R_GPT0_GTWP_PRKEY_Pos             (8UL)          /*!< PRKEY (Bit 8)                                         */
+ #define R_GPT0_GTWP_PRKEY_Msk             (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
+ #define R_GPT0_GTWP_WP_Pos                (0UL)          /*!< WP (Bit 0)                                            */
+ #define R_GPT0_GTWP_WP_Msk                (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
+ #define R_GPT0_GTWP_STRWP_Pos             (1UL)          /*!< STRWP (Bit 1)                                         */
+ #define R_GPT0_GTWP_STRWP_Msk             (0x2UL)        /*!< STRWP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTWP_STPWP_Pos             (2UL)          /*!< STPWP (Bit 2)                                         */
+ #define R_GPT0_GTWP_STPWP_Msk             (0x4UL)        /*!< STPWP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTWP_CLRWP_Pos             (3UL)          /*!< CLRWP (Bit 3)                                         */
+ #define R_GPT0_GTWP_CLRWP_Msk             (0x8UL)        /*!< CLRWP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTWP_CMNWP_Pos             (4UL)          /*!< CMNWP (Bit 4)                                         */
+ #define R_GPT0_GTWP_CMNWP_Msk             (0x10UL)       /*!< CMNWP (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTSTR  ========================================================= */
+ #define R_GPT0_GTSTR_CSTRT_Pos            (0UL)          /*!< CSTRT (Bit 0)                                         */
+ #define R_GPT0_GTSTR_CSTRT_Msk            (0x1UL)        /*!< CSTRT (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTSTP  ========================================================= */
+ #define R_GPT0_GTSTP_CSTOP_Pos            (0UL)          /*!< CSTOP (Bit 0)                                         */
+ #define R_GPT0_GTSTP_CSTOP_Msk            (0x1UL)        /*!< CSTOP (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTCLR  ========================================================= */
+ #define R_GPT0_GTCLR_CCLR_Pos             (0UL)          /*!< CCLR (Bit 0)                                          */
+ #define R_GPT0_GTCLR_CCLR_Msk             (0x1UL)        /*!< CCLR (Bitfield-Mask: 0x01)                            */
+/* =========================================================  GTSSR  ========================================================= */
+ #define R_GPT0_GTSSR_CSTRT_Pos            (31UL)         /*!< CSTRT (Bit 31)                                        */
+ #define R_GPT0_GTSSR_CSTRT_Msk            (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSSR_SSELC_Pos            (16UL)         /*!< SSELC (Bit 16)                                        */
+ #define R_GPT0_GTSSR_SSELC_Msk            (0x10000UL)    /*!< SSELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSSR_SSCBFAH_Pos          (15UL)         /*!< SSCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTSSR_SSCBFAH_Msk          (0x8000UL)     /*!< SSCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCBFAL_Pos          (14UL)         /*!< SSCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTSSR_SSCBFAL_Msk          (0x4000UL)     /*!< SSCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCBRAH_Pos          (13UL)         /*!< SSCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTSSR_SSCBRAH_Msk          (0x2000UL)     /*!< SSCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCBRAL_Pos          (12UL)         /*!< SSCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTSSR_SSCBRAL_Msk          (0x1000UL)     /*!< SSCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCAFBH_Pos          (11UL)         /*!< SSCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTSSR_SSCAFBH_Msk          (0x800UL)      /*!< SSCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCAFBL_Pos          (10UL)         /*!< SSCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTSSR_SSCAFBL_Msk          (0x400UL)      /*!< SSCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCARBH_Pos          (9UL)          /*!< SSCARBH (Bit 9)                                       */
+ #define R_GPT0_GTSSR_SSCARBH_Msk          (0x200UL)      /*!< SSCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCARBL_Pos          (8UL)          /*!< SSCARBL (Bit 8)                                       */
+ #define R_GPT0_GTSSR_SSCARBL_Msk          (0x100UL)      /*!< SSCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSGTRGF_Pos          (1UL)          /*!< SSGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTSSR_SSGTRGF_Msk          (0x2UL)        /*!< SSGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSGTRGR_Pos          (0UL)          /*!< SSGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTSSR_SSGTRGR_Msk          (0x1UL)        /*!< SSGTRGR (Bitfield-Mask: 0x01)                         */
+/* =========================================================  GTPSR  ========================================================= */
+ #define R_GPT0_GTPSR_CSTOP_Pos            (31UL)         /*!< CSTOP (Bit 31)                                        */
+ #define R_GPT0_GTPSR_CSTOP_Msk            (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTPSR_PSELC_Pos            (16UL)         /*!< PSELC (Bit 16)                                        */
+ #define R_GPT0_GTPSR_PSELC_Msk            (0x10000UL)    /*!< PSELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTPSR_PSCBFAH_Pos          (15UL)         /*!< PSCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTPSR_PSCBFAH_Msk          (0x8000UL)     /*!< PSCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCBFAL_Pos          (14UL)         /*!< PSCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTPSR_PSCBFAL_Msk          (0x4000UL)     /*!< PSCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCBRAH_Pos          (13UL)         /*!< PSCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTPSR_PSCBRAH_Msk          (0x2000UL)     /*!< PSCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCBRAL_Pos          (12UL)         /*!< PSCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTPSR_PSCBRAL_Msk          (0x1000UL)     /*!< PSCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCAFBH_Pos          (11UL)         /*!< PSCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTPSR_PSCAFBH_Msk          (0x800UL)      /*!< PSCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCAFBL_Pos          (10UL)         /*!< PSCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTPSR_PSCAFBL_Msk          (0x400UL)      /*!< PSCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCARBH_Pos          (9UL)          /*!< PSCARBH (Bit 9)                                       */
+ #define R_GPT0_GTPSR_PSCARBH_Msk          (0x200UL)      /*!< PSCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCARBL_Pos          (8UL)          /*!< PSCARBL (Bit 8)                                       */
+ #define R_GPT0_GTPSR_PSCARBL_Msk          (0x100UL)      /*!< PSCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSGTRGF_Pos          (1UL)          /*!< PSGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTPSR_PSGTRGF_Msk          (0x2UL)        /*!< PSGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSGTRGR_Pos          (0UL)          /*!< PSGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTPSR_PSGTRGR_Msk          (0x1UL)        /*!< PSGTRGR (Bitfield-Mask: 0x01)                         */
+/* =========================================================  GTCSR  ========================================================= */
+ #define R_GPT0_GTCSR_CCLR_Pos             (31UL)         /*!< CCLR (Bit 31)                                         */
+ #define R_GPT0_GTCSR_CCLR_Msk             (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTCSR_CP1CCE_Pos           (27UL)         /*!< CP1CCE (Bit 27)                                       */
+ #define R_GPT0_GTCSR_CP1CCE_Msk           (0x8000000UL)  /*!< CP1CCE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTCSR_CSCMSC_Pos           (24UL)         /*!< CSCMSC (Bit 24)                                       */
+ #define R_GPT0_GTCSR_CSCMSC_Msk           (0x7000000UL)  /*!< CSCMSC (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTCSR_CSELC_Pos            (16UL)         /*!< CSELC (Bit 16)                                        */
+ #define R_GPT0_GTCSR_CSELC_Msk            (0x10000UL)    /*!< CSELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCSR_CSCBFAH_Pos          (15UL)         /*!< CSCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTCSR_CSCBFAH_Msk          (0x8000UL)     /*!< CSCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCBFAL_Pos          (14UL)         /*!< CSCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTCSR_CSCBFAL_Msk          (0x4000UL)     /*!< CSCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCBRAH_Pos          (13UL)         /*!< CSCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTCSR_CSCBRAH_Msk          (0x2000UL)     /*!< CSCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCBRAL_Pos          (12UL)         /*!< CSCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTCSR_CSCBRAL_Msk          (0x1000UL)     /*!< CSCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCAFBH_Pos          (11UL)         /*!< CSCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTCSR_CSCAFBH_Msk          (0x800UL)      /*!< CSCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCAFBL_Pos          (10UL)         /*!< CSCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTCSR_CSCAFBL_Msk          (0x400UL)      /*!< CSCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCARBH_Pos          (9UL)          /*!< CSCARBH (Bit 9)                                       */
+ #define R_GPT0_GTCSR_CSCARBH_Msk          (0x200UL)      /*!< CSCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCARBL_Pos          (8UL)          /*!< CSCARBL (Bit 8)                                       */
+ #define R_GPT0_GTCSR_CSCARBL_Msk          (0x100UL)      /*!< CSCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSGTRGF_Pos          (1UL)          /*!< CSGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTCSR_CSGTRGF_Msk          (0x2UL)        /*!< CSGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSGTRGR_Pos          (0UL)          /*!< CSGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTCSR_CSGTRGR_Msk          (0x1UL)        /*!< CSGTRGR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTUPSR  ========================================================= */
+ #define R_GPT0_GTUPSR_USILVL_Pos          (24UL)         /*!< USILVL (Bit 24)                                       */
+ #define R_GPT0_GTUPSR_USILVL_Msk          (0xf000000UL)  /*!< USILVL (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTUPSR_USELC_Pos           (16UL)         /*!< USELC (Bit 16)                                        */
+ #define R_GPT0_GTUPSR_USELC_Msk           (0x10000UL)    /*!< USELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTUPSR_USCBFAH_Pos         (15UL)         /*!< USCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTUPSR_USCBFAH_Msk         (0x8000UL)     /*!< USCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCBFAL_Pos         (14UL)         /*!< USCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTUPSR_USCBFAL_Msk         (0x4000UL)     /*!< USCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCBRAH_Pos         (13UL)         /*!< USCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTUPSR_USCBRAH_Msk         (0x2000UL)     /*!< USCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCBRAL_Pos         (12UL)         /*!< USCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTUPSR_USCBRAL_Msk         (0x1000UL)     /*!< USCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCAFBH_Pos         (11UL)         /*!< USCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTUPSR_USCAFBH_Msk         (0x800UL)      /*!< USCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCAFBL_Pos         (10UL)         /*!< USCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTUPSR_USCAFBL_Msk         (0x400UL)      /*!< USCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCARBH_Pos         (9UL)          /*!< USCARBH (Bit 9)                                       */
+ #define R_GPT0_GTUPSR_USCARBH_Msk         (0x200UL)      /*!< USCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCARBL_Pos         (8UL)          /*!< USCARBL (Bit 8)                                       */
+ #define R_GPT0_GTUPSR_USCARBL_Msk         (0x100UL)      /*!< USCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USGTRGF_Pos         (1UL)          /*!< USGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTUPSR_USGTRGF_Msk         (0x2UL)        /*!< USGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USGTRGR_Pos         (0UL)          /*!< USGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTUPSR_USGTRGR_Msk         (0x1UL)        /*!< USGTRGR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTDNSR  ========================================================= */
+ #define R_GPT0_GTDNSR_DSILVL_Pos          (24UL)         /*!< DSILVL (Bit 24)                                       */
+ #define R_GPT0_GTDNSR_DSILVL_Msk          (0xf000000UL)  /*!< DSILVL (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTDNSR_DSELC_Pos           (16UL)         /*!< DSELC (Bit 16)                                        */
+ #define R_GPT0_GTDNSR_DSELC_Msk           (0x10000UL)    /*!< DSELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTDNSR_DSCBFAH_Pos         (15UL)         /*!< DSCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTDNSR_DSCBFAH_Msk         (0x8000UL)     /*!< DSCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCBFAL_Pos         (14UL)         /*!< DSCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTDNSR_DSCBFAL_Msk         (0x4000UL)     /*!< DSCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCBRAH_Pos         (13UL)         /*!< DSCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTDNSR_DSCBRAH_Msk         (0x2000UL)     /*!< DSCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCBRAL_Pos         (12UL)         /*!< DSCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTDNSR_DSCBRAL_Msk         (0x1000UL)     /*!< DSCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCAFBH_Pos         (11UL)         /*!< DSCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTDNSR_DSCAFBH_Msk         (0x800UL)      /*!< DSCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCAFBL_Pos         (10UL)         /*!< DSCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTDNSR_DSCAFBL_Msk         (0x400UL)      /*!< DSCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCARBH_Pos         (9UL)          /*!< DSCARBH (Bit 9)                                       */
+ #define R_GPT0_GTDNSR_DSCARBH_Msk         (0x200UL)      /*!< DSCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCARBL_Pos         (8UL)          /*!< DSCARBL (Bit 8)                                       */
+ #define R_GPT0_GTDNSR_DSCARBL_Msk         (0x100UL)      /*!< DSCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSGTRGF_Pos         (1UL)          /*!< DSGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTDNSR_DSGTRGF_Msk         (0x2UL)        /*!< DSGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSGTRGR_Pos         (0UL)          /*!< DSGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTDNSR_DSGTRGR_Msk         (0x1UL)        /*!< DSGTRGR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTICASR  ======================================================== */
+ #define R_GPT0_GTICASR_ASELC_Pos          (16UL)         /*!< ASELC (Bit 16)                                        */
+ #define R_GPT0_GTICASR_ASELC_Msk          (0x10000UL)    /*!< ASELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICASR_ASCBFAH_Pos        (15UL)         /*!< ASCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTICASR_ASCBFAH_Msk        (0x8000UL)     /*!< ASCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCBFAL_Pos        (14UL)         /*!< ASCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTICASR_ASCBFAL_Msk        (0x4000UL)     /*!< ASCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCBRAH_Pos        (13UL)         /*!< ASCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTICASR_ASCBRAH_Msk        (0x2000UL)     /*!< ASCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCBRAL_Pos        (12UL)         /*!< ASCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTICASR_ASCBRAL_Msk        (0x1000UL)     /*!< ASCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCAFBH_Pos        (11UL)         /*!< ASCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTICASR_ASCAFBH_Msk        (0x800UL)      /*!< ASCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCAFBL_Pos        (10UL)         /*!< ASCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTICASR_ASCAFBL_Msk        (0x400UL)      /*!< ASCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCARBH_Pos        (9UL)          /*!< ASCARBH (Bit 9)                                       */
+ #define R_GPT0_GTICASR_ASCARBH_Msk        (0x200UL)      /*!< ASCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCARBL_Pos        (8UL)          /*!< ASCARBL (Bit 8)                                       */
+ #define R_GPT0_GTICASR_ASCARBL_Msk        (0x100UL)      /*!< ASCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASGTRGF_Pos        (1UL)          /*!< ASGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTICASR_ASGTRGF_Msk        (0x2UL)        /*!< ASGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASGTRGR_Pos        (0UL)          /*!< ASGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTICASR_ASGTRGR_Msk        (0x1UL)        /*!< ASGTRGR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTICBSR  ======================================================== */
+ #define R_GPT0_GTICBSR_BSELC_Pos          (16UL)         /*!< BSELC (Bit 16)                                        */
+ #define R_GPT0_GTICBSR_BSELC_Msk          (0x10000UL)    /*!< BSELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICBSR_BSCBFAH_Pos        (15UL)         /*!< BSCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTICBSR_BSCBFAH_Msk        (0x8000UL)     /*!< BSCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCBFAL_Pos        (14UL)         /*!< BSCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTICBSR_BSCBFAL_Msk        (0x4000UL)     /*!< BSCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCBRAH_Pos        (13UL)         /*!< BSCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTICBSR_BSCBRAH_Msk        (0x2000UL)     /*!< BSCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCBRAL_Pos        (12UL)         /*!< BSCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTICBSR_BSCBRAL_Msk        (0x1000UL)     /*!< BSCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCAFBH_Pos        (11UL)         /*!< BSCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTICBSR_BSCAFBH_Msk        (0x800UL)      /*!< BSCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCAFBL_Pos        (10UL)         /*!< BSCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTICBSR_BSCAFBL_Msk        (0x400UL)      /*!< BSCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCARBH_Pos        (9UL)          /*!< BSCARBH (Bit 9)                                       */
+ #define R_GPT0_GTICBSR_BSCARBH_Msk        (0x200UL)      /*!< BSCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCARBL_Pos        (8UL)          /*!< BSCARBL (Bit 8)                                       */
+ #define R_GPT0_GTICBSR_BSCARBL_Msk        (0x100UL)      /*!< BSCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSGTRGF_Pos        (1UL)          /*!< BSGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTICBSR_BSGTRGF_Msk        (0x2UL)        /*!< BSGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
+/* =========================================================  GTCR  ========================================================== */
+ #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
+ #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTCR_TPCS_Pos              (23UL)         /*!< TPCS (Bit 23)                                         */
+ #define R_GPT0_GTCR_TPCS_Msk              (0x7800000UL)  /*!< TPCS (Bitfield-Mask: 0x0f)                            */
+ #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
+ #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
+ #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
+ #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
+ #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
+ #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
+ #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
+/* =======================================================  GTUDDTYC  ======================================================== */
+ #define R_GPT0_GTUDDTYC_OBDTYR_Pos        (27UL)         /*!< OBDTYR (Bit 27)                                       */
+ #define R_GPT0_GTUDDTYC_OBDTYR_Msk        (0x8000000UL)  /*!< OBDTYR (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTUDDTYC_OBDTYF_Pos        (26UL)         /*!< OBDTYF (Bit 26)                                       */
+ #define R_GPT0_GTUDDTYC_OBDTYF_Msk        (0x4000000UL)  /*!< OBDTYF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTUDDTYC_OBDTY_Pos         (24UL)         /*!< OBDTY (Bit 24)                                        */
+ #define R_GPT0_GTUDDTYC_OBDTY_Msk         (0x3000000UL)  /*!< OBDTY (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTUDDTYC_OADTYR_Pos        (19UL)         /*!< OADTYR (Bit 19)                                       */
+ #define R_GPT0_GTUDDTYC_OADTYR_Msk        (0x80000UL)    /*!< OADTYR (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTUDDTYC_OADTYF_Pos        (18UL)         /*!< OADTYF (Bit 18)                                       */
+ #define R_GPT0_GTUDDTYC_OADTYF_Msk        (0x40000UL)    /*!< OADTYF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTUDDTYC_OADTY_Pos         (16UL)         /*!< OADTY (Bit 16)                                        */
+ #define R_GPT0_GTUDDTYC_OADTY_Msk         (0x30000UL)    /*!< OADTY (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTUDDTYC_UDF_Pos           (1UL)          /*!< UDF (Bit 1)                                           */
+ #define R_GPT0_GTUDDTYC_UDF_Msk           (0x2UL)        /*!< UDF (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTUDDTYC_UD_Pos            (0UL)          /*!< UD (Bit 0)                                            */
+ #define R_GPT0_GTUDDTYC_UD_Msk            (0x1UL)        /*!< UD (Bitfield-Mask: 0x01)                              */
+/* =========================================================  GTIOR  ========================================================= */
+ #define R_GPT0_GTIOR_NFCSB_Pos            (30UL)         /*!< NFCSB (Bit 30)                                        */
+ #define R_GPT0_GTIOR_NFCSB_Msk            (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTIOR_NFBEN_Pos            (29UL)         /*!< NFBEN (Bit 29)                                        */
+ #define R_GPT0_GTIOR_NFBEN_Msk            (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTIOR_OBEOCD_Pos           (27UL)         /*!< OBEOCD (Bit 27)                                       */
+ #define R_GPT0_GTIOR_OBEOCD_Msk           (0x8000000UL)  /*!< OBEOCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTIOR_OBDF_Pos             (25UL)         /*!< OBDF (Bit 25)                                         */
+ #define R_GPT0_GTIOR_OBDF_Msk             (0x6000000UL)  /*!< OBDF (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTIOR_OBE_Pos              (24UL)         /*!< OBE (Bit 24)                                          */
+ #define R_GPT0_GTIOR_OBE_Msk              (0x1000000UL)  /*!< OBE (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTIOR_OBHLD_Pos            (23UL)         /*!< OBHLD (Bit 23)                                        */
+ #define R_GPT0_GTIOR_OBHLD_Msk            (0x800000UL)   /*!< OBHLD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTIOR_OBDFLT_Pos           (22UL)         /*!< OBDFLT (Bit 22)                                       */
+ #define R_GPT0_GTIOR_OBDFLT_Msk           (0x400000UL)   /*!< OBDFLT (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTIOR_GTIOB_Pos            (16UL)         /*!< GTIOB (Bit 16)                                        */
+ #define R_GPT0_GTIOR_GTIOB_Msk            (0x1f0000UL)   /*!< GTIOB (Bitfield-Mask: 0x1f)                           */
+ #define R_GPT0_GTIOR_NFCSA_Pos            (14UL)         /*!< NFCSA (Bit 14)                                        */
+ #define R_GPT0_GTIOR_NFCSA_Msk            (0xc000UL)     /*!< NFCSA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTIOR_NFAEN_Pos            (13UL)         /*!< NFAEN (Bit 13)                                        */
+ #define R_GPT0_GTIOR_NFAEN_Msk            (0x2000UL)     /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTIOR_PSYE_Pos             (12UL)         /*!< PSYE (Bit 12)                                         */
+ #define R_GPT0_GTIOR_PSYE_Msk             (0x1000UL)     /*!< PSYE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTIOR_OAEOCD_Pos           (11UL)         /*!< OAEOCD (Bit 11)                                       */
+ #define R_GPT0_GTIOR_OAEOCD_Msk           (0x800UL)      /*!< OAEOCD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTIOR_OADF_Pos             (9UL)          /*!< OADF (Bit 9)                                          */
+ #define R_GPT0_GTIOR_OADF_Msk             (0x600UL)      /*!< OADF (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTIOR_OAE_Pos              (8UL)          /*!< OAE (Bit 8)                                           */
+ #define R_GPT0_GTIOR_OAE_Msk              (0x100UL)      /*!< OAE (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTIOR_OAHLD_Pos            (7UL)          /*!< OAHLD (Bit 7)                                         */
+ #define R_GPT0_GTIOR_OAHLD_Msk            (0x80UL)       /*!< OAHLD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTIOR_OADFLT_Pos           (6UL)          /*!< OADFLT (Bit 6)                                        */
+ #define R_GPT0_GTIOR_OADFLT_Msk           (0x40UL)       /*!< OADFLT (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTIOR_CPSCIR_Pos           (5UL)          /*!< CPSCIR (Bit 5)                                        */
+ #define R_GPT0_GTIOR_CPSCIR_Msk           (0x20UL)       /*!< CPSCIR (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
+ #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
+/* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
+ #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
+ #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
+ #define R_GPT0_GTINTAD_GRPABH_Msk         (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTINTAD_GRPDTE_Pos         (28UL)         /*!< GRPDTE (Bit 28)                                       */
+ #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
+ #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
+ #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
+ #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
+ #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
+/* =========================================================  GTST  ========================================================== */
+ #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
+ #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTST_OABHF_Pos             (29UL)         /*!< OABHF (Bit 29)                                        */
+ #define R_GPT0_GTST_OABHF_Msk             (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTST_DTEF_Pos              (28UL)         /*!< DTEF (Bit 28)                                         */
+ #define R_GPT0_GTST_DTEF_Msk              (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_ODF_Pos               (24UL)         /*!< ODF (Bit 24)                                          */
+ #define R_GPT0_GTST_ODF_Msk               (0x1000000UL)  /*!< ODF (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTST_ADTRBDF_Pos           (19UL)         /*!< ADTRBDF (Bit 19)                                      */
+ #define R_GPT0_GTST_ADTRBDF_Msk           (0x80000UL)    /*!< ADTRBDF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTST_ADTRBUF_Pos           (18UL)         /*!< ADTRBUF (Bit 18)                                      */
+ #define R_GPT0_GTST_ADTRBUF_Msk           (0x40000UL)    /*!< ADTRBUF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTST_ADTRADF_Pos           (17UL)         /*!< ADTRADF (Bit 17)                                      */
+ #define R_GPT0_GTST_ADTRADF_Msk           (0x20000UL)    /*!< ADTRADF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTST_ADTRAUF_Pos           (16UL)         /*!< ADTRAUF (Bit 16)                                      */
+ #define R_GPT0_GTST_ADTRAUF_Msk           (0x10000UL)    /*!< ADTRAUF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTST_TUCF_Pos              (15UL)         /*!< TUCF (Bit 15)                                         */
+ #define R_GPT0_GTST_TUCF_Msk              (0x8000UL)     /*!< TUCF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_ITCNT_Pos             (8UL)          /*!< ITCNT (Bit 8)                                         */
+ #define R_GPT0_GTST_ITCNT_Msk             (0x700UL)      /*!< ITCNT (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTST_TCFPU_Pos             (7UL)          /*!< TCFPU (Bit 7)                                         */
+ #define R_GPT0_GTST_TCFPU_Msk             (0x80UL)       /*!< TCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTST_TCFPO_Pos             (6UL)          /*!< TCFPO (Bit 6)                                         */
+ #define R_GPT0_GTST_TCFPO_Msk             (0x40UL)       /*!< TCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTST_TCFF_Pos              (5UL)          /*!< TCFF (Bit 5)                                          */
+ #define R_GPT0_GTST_TCFF_Msk              (0x20UL)       /*!< TCFF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_TCFE_Pos              (4UL)          /*!< TCFE (Bit 4)                                          */
+ #define R_GPT0_GTST_TCFE_Msk              (0x10UL)       /*!< TCFE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_TCFD_Pos              (3UL)          /*!< TCFD (Bit 3)                                          */
+ #define R_GPT0_GTST_TCFD_Msk              (0x8UL)        /*!< TCFD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_TCFC_Pos              (2UL)          /*!< TCFC (Bit 2)                                          */
+ #define R_GPT0_GTST_TCFC_Msk              (0x4UL)        /*!< TCFC (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_TCFB_Pos              (1UL)          /*!< TCFB (Bit 1)                                          */
+ #define R_GPT0_GTST_TCFB_Msk              (0x2UL)        /*!< TCFB (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_TCFA_Pos              (0UL)          /*!< TCFA (Bit 0)                                          */
+ #define R_GPT0_GTST_TCFA_Msk              (0x1UL)        /*!< TCFA (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_PCF_Pos               (31UL)         /*!< PCF (Bit 31)                                          */
+ #define R_GPT0_GTST_PCF_Msk               (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01)                             */
+/* =========================================================  GTBER  ========================================================= */
+ #define R_GPT0_GTBER_ADTDB_Pos            (30UL)         /*!< ADTDB (Bit 30)                                        */
+ #define R_GPT0_GTBER_ADTDB_Msk            (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER_ADTTB_Pos            (28UL)         /*!< ADTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER_ADTTB_Msk            (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER_ADTDA_Pos            (26UL)         /*!< ADTDA (Bit 26)                                        */
+ #define R_GPT0_GTBER_ADTDA_Msk            (0x4000000UL)  /*!< ADTDA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER_ADTTA_Pos            (24UL)         /*!< ADTTA (Bit 24)                                        */
+ #define R_GPT0_GTBER_ADTTA_Msk            (0x3000000UL)  /*!< ADTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER_CCRSWT_Pos           (22UL)         /*!< CCRSWT (Bit 22)                                       */
+ #define R_GPT0_GTBER_CCRSWT_Msk           (0x400000UL)   /*!< CCRSWT (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER_PR_Pos               (20UL)         /*!< PR (Bit 20)                                           */
+ #define R_GPT0_GTBER_PR_Msk               (0x300000UL)   /*!< PR (Bitfield-Mask: 0x03)                              */
+ #define R_GPT0_GTBER_CCRB_Pos             (18UL)         /*!< CCRB (Bit 18)                                         */
+ #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
+ #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
+ #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
+ #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
+ #define R_GPT0_GTBER_BD2_Msk              (0x4UL)        /*!< BD2 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTBER_BD1_Pos              (1UL)          /*!< BD1 (Bit 1)                                           */
+ #define R_GPT0_GTBER_BD1_Msk              (0x2UL)        /*!< BD1 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTBER_BD0_Pos              (0UL)          /*!< BD0 (Bit 0)                                           */
+ #define R_GPT0_GTBER_BD0_Msk              (0x1UL)        /*!< BD0 (Bitfield-Mask: 0x01)                             */
+/* =========================================================  GTITC  ========================================================= */
+ #define R_GPT0_GTITC_ADTBL_Pos            (14UL)         /*!< ADTBL (Bit 14)                                        */
+ #define R_GPT0_GTITC_ADTBL_Msk            (0x4000UL)     /*!< ADTBL (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTITC_ADTAL_Pos            (12UL)         /*!< ADTAL (Bit 12)                                        */
+ #define R_GPT0_GTITC_ADTAL_Msk            (0x1000UL)     /*!< ADTAL (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTITC_IVTT_Pos             (8UL)          /*!< IVTT (Bit 8)                                          */
+ #define R_GPT0_GTITC_IVTT_Msk             (0x700UL)      /*!< IVTT (Bitfield-Mask: 0x07)                            */
+ #define R_GPT0_GTITC_IVTC_Pos             (6UL)          /*!< IVTC (Bit 6)                                          */
+ #define R_GPT0_GTITC_IVTC_Msk             (0xc0UL)       /*!< IVTC (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTITC_ITLF_Pos             (5UL)          /*!< ITLF (Bit 5)                                          */
+ #define R_GPT0_GTITC_ITLF_Msk             (0x20UL)       /*!< ITLF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTITC_ITLE_Pos             (4UL)          /*!< ITLE (Bit 4)                                          */
+ #define R_GPT0_GTITC_ITLE_Msk             (0x10UL)       /*!< ITLE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTITC_ITLD_Pos             (3UL)          /*!< ITLD (Bit 3)                                          */
+ #define R_GPT0_GTITC_ITLD_Msk             (0x8UL)        /*!< ITLD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTITC_ITLC_Pos             (2UL)          /*!< ITLC (Bit 2)                                          */
+ #define R_GPT0_GTITC_ITLC_Msk             (0x4UL)        /*!< ITLC (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTITC_ITLB_Pos             (1UL)          /*!< ITLB (Bit 1)                                          */
+ #define R_GPT0_GTITC_ITLB_Msk             (0x2UL)        /*!< ITLB (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTITC_ITLA_Pos             (0UL)          /*!< ITLA (Bit 0)                                          */
+ #define R_GPT0_GTITC_ITLA_Msk             (0x1UL)        /*!< ITLA (Bitfield-Mask: 0x01)                            */
+/* =========================================================  GTCNT  ========================================================= */
+ #define R_GPT0_GTCNT_GTCNT_Pos            (0UL)          /*!< GTCNT (Bit 0)                                         */
+ #define R_GPT0_GTCNT_GTCNT_Msk            (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  GTCCR  ========================================================= */
+ #define R_GPT0_GTCCR_GTCCR_Pos            (0UL)          /*!< GTCCR (Bit 0)                                         */
+ #define R_GPT0_GTCCR_GTCCR_Msk            (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  GTPR  ========================================================== */
+ #define R_GPT0_GTPR_GTPR_Pos              (0UL)          /*!< GTPR (Bit 0)                                          */
+ #define R_GPT0_GTPR_GTPR_Msk              (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  GTPBR  ========================================================= */
+ #define R_GPT0_GTPBR_GTPBR_Pos            (0UL)          /*!< GTPBR (Bit 0)                                         */
+ #define R_GPT0_GTPBR_GTPBR_Msk            (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  GTPDBR  ========================================================= */
+ #define R_GPT0_GTPDBR_GTPDBR_Pos          (0UL)          /*!< GTPDBR (Bit 0)                                        */
+ #define R_GPT0_GTPDBR_GTPDBR_Msk          (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  GTADTRA  ======================================================== */
+ #define R_GPT0_GTADTRA_GTADTRA_Pos        (0UL)          /*!< GTADTRA (Bit 0)                                       */
+ #define R_GPT0_GTADTRA_GTADTRA_Msk        (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff)                   */
+/* ========================================================  GTADTRB  ======================================================== */
+ #define R_GPT0_GTADTRB_GTADTRB_Pos        (0UL)          /*!< GTADTRB (Bit 0)                                       */
+ #define R_GPT0_GTADTRB_GTADTRB_Msk        (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff)                   */
+/* =======================================================  GTADTBRA  ======================================================== */
+ #define R_GPT0_GTADTBRA_GTADTBRA_Pos      (0UL)          /*!< GTADTBRA (Bit 0)                                      */
+ #define R_GPT0_GTADTBRA_GTADTBRA_Msk      (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff)                  */
+/* =======================================================  GTADTBRB  ======================================================== */
+ #define R_GPT0_GTADTBRB_GTADTBRB_Pos      (0UL)          /*!< GTADTBRB (Bit 0)                                      */
+ #define R_GPT0_GTADTBRB_GTADTBRB_Msk      (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff)                  */
+/* =======================================================  GTADTDBRA  ======================================================= */
+ #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos    (0UL)          /*!< GTADTDBRA (Bit 0)                                     */
+ #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk    (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff)                 */
+/* =======================================================  GTADTDBRB  ======================================================= */
+ #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos    (0UL)          /*!< GTADTDBRB (Bit 0)                                     */
+ #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk    (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff)                 */
+/* ========================================================  GTDTCR  ========================================================= */
+ #define R_GPT0_GTDTCR_TDFER_Pos           (8UL)          /*!< TDFER (Bit 8)                                         */
+ #define R_GPT0_GTDTCR_TDFER_Msk           (0x100UL)      /*!< TDFER (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTDTCR_TDBDE_Pos           (5UL)          /*!< TDBDE (Bit 5)                                         */
+ #define R_GPT0_GTDTCR_TDBDE_Msk           (0x20UL)       /*!< TDBDE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTDTCR_TDBUE_Pos           (4UL)          /*!< TDBUE (Bit 4)                                         */
+ #define R_GPT0_GTDTCR_TDBUE_Msk           (0x10UL)       /*!< TDBUE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTDTCR_TDE_Pos             (0UL)          /*!< TDE (Bit 0)                                           */
+ #define R_GPT0_GTDTCR_TDE_Msk             (0x1UL)        /*!< TDE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  GTDVU  ========================================================= */
+ #define R_GPT0_GTDVU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
+ #define R_GPT0_GTDVU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  GTDVD  ========================================================= */
+ #define R_GPT0_GTDVD_GTDVD_Pos            (0UL)          /*!< GTDVD (Bit 0)                                         */
+ #define R_GPT0_GTDVD_GTDVD_Msk            (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  GTDBU  ========================================================= */
+ #define R_GPT0_GTDBU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
+ #define R_GPT0_GTDBU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  GTDBD  ========================================================= */
+ #define R_GPT0_GTDBD_GTDBD_Pos            (0UL)          /*!< GTDBD (Bit 0)                                         */
+ #define R_GPT0_GTDBD_GTDBD_Msk            (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  GTSOS  ========================================================= */
+ #define R_GPT0_GTSOS_SOS_Pos              (0UL)          /*!< SOS (Bit 0)                                           */
+ #define R_GPT0_GTSOS_SOS_Msk              (0x3UL)        /*!< SOS (Bitfield-Mask: 0x03)                             */
+/* ========================================================  GTSOTR  ========================================================= */
+ #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
+ #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
+/* ========================================================  GTICLF  ========================================================= */
+ #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
+ #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTICLF_ICLFSELC_Pos        (4UL)          /*!< ICLFSELC (Bit 4)                                      */
+ #define R_GPT0_GTICLF_ICLFSELC_Msk        (0x3f0UL)      /*!< ICLFSELC (Bitfield-Mask: 0x3f)                        */
+ #define R_GPT0_GTICLF_ICLFB_Pos           (16UL)         /*!< ICLFB (Bit 16)                                        */
+ #define R_GPT0_GTICLF_ICLFB_Msk           (0x70000UL)    /*!< ICLFB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTICLF_ICLFSELD_Pos        (20UL)         /*!< ICLFSELD (Bit 20)                                     */
+ #define R_GPT0_GTICLF_ICLFSELD_Msk        (0x3f00000UL)  /*!< ICLFSELD (Bitfield-Mask: 0x3f)                        */
+/* =========================================================  GTPC  ========================================================== */
+ #define R_GPT0_GTPC_PCEN_Pos              (0UL)          /*!< PCEN (Bit 0)                                          */
+ #define R_GPT0_GTPC_PCEN_Msk              (0x1UL)        /*!< PCEN (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTPC_ASTP_Pos              (8UL)          /*!< ASTP (Bit 8)                                          */
+ #define R_GPT0_GTPC_ASTP_Msk              (0x100UL)      /*!< ASTP (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTPC_PCNT_Pos              (16UL)         /*!< PCNT (Bit 16)                                         */
+ #define R_GPT0_GTPC_PCNT_Msk              (0xfff0000UL)  /*!< PCNT (Bitfield-Mask: 0xfff)                           */
+/* ========================================================  GTSECSR  ======================================================== */
+ #define R_GPT0_GTSECSR_SECSEL0_Pos        (0UL)          /*!< SECSEL0 (Bit 0)                                       */
+ #define R_GPT0_GTSECSR_SECSEL0_Msk        (0x1UL)        /*!< SECSEL0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSECSR_SECSEL1_Pos        (1UL)          /*!< SECSEL1 (Bit 1)                                       */
+ #define R_GPT0_GTSECSR_SECSEL1_Msk        (0x2UL)        /*!< SECSEL1 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSECSR_SECSEL2_Pos        (2UL)          /*!< SECSEL2 (Bit 2)                                       */
+ #define R_GPT0_GTSECSR_SECSEL2_Msk        (0x4UL)        /*!< SECSEL2 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSECSR_SECSEL3_Pos        (3UL)          /*!< SECSEL3 (Bit 3)                                       */
+ #define R_GPT0_GTSECSR_SECSEL3_Msk        (0x8UL)        /*!< SECSEL3 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSECSR_SECSEL4_Pos        (4UL)          /*!< SECSEL4 (Bit 4)                                       */
+ #define R_GPT0_GTSECSR_SECSEL4_Msk        (0x10UL)       /*!< SECSEL4 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSECSR_SECSEL5_Pos        (5UL)          /*!< SECSEL5 (Bit 5)                                       */
+ #define R_GPT0_GTSECSR_SECSEL5_Msk        (0x20UL)       /*!< SECSEL5 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSECSR_SECSEL6_Pos        (6UL)          /*!< SECSEL6 (Bit 6)                                       */
+ #define R_GPT0_GTSECSR_SECSEL6_Msk        (0x40UL)       /*!< SECSEL6 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSECSR_SECSEL7_Pos        (7UL)          /*!< SECSEL7 (Bit 7)                                       */
+ #define R_GPT0_GTSECSR_SECSEL7_Msk        (0x80UL)       /*!< SECSEL7 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSECSR_SECSEL8_Pos        (8UL)          /*!< SECSEL8 (Bit 8)                                       */
+ #define R_GPT0_GTSECSR_SECSEL8_Msk        (0x100UL)      /*!< SECSEL8 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSECSR_SECSEL9_Pos        (9UL)          /*!< SECSEL9 (Bit 9)                                       */
+ #define R_GPT0_GTSECSR_SECSEL9_Msk        (0x200UL)      /*!< SECSEL9 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTSECR  ========================================================= */
+ #define R_GPT0_GTSECR_SBDCE_Pos           (0UL)          /*!< SBDCE (Bit 0)                                         */
+ #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
+ #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
+ #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
+ #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
+ #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
+ #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
+ #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
+ #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTBER2  ========================================================= */
+ #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
+ #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
+ #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
+ #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
+ #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
+ #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
+ #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
+ #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
+ #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
+ #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
+ #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
+ #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
+ #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
+ #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
+ #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
+ #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
+ #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
+ #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
+ #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
+ #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTOLBR  ========================================================= */
+ #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
+ #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
+ #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
+ #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  GTICCR  ========================================================= */
+ #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
+ #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
+ #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
+ #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
+ #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
+ #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
+ #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
+ #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
+ #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
+ #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
+ #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
+ #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
+ #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
+ #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
+ #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
+ #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
+ #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
+ #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
+ #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
+ #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
+ #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
+
+/* =========================================================================================================================== */
+/* ================                                         R_GPT_OPS                                         ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  OPSCR  ========================================================= */
+ #define R_GPT_OPS_OPSCR_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_GPT_OPS_OPSCR_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+ #define R_GPT_OPS_OPSCR_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_GPT_OPS_OPSCR_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_OPS_OPSCR_GODF_Pos     (26UL)         /*!< GODF (Bit 26)                                         */
+ #define R_GPT_OPS_OPSCR_GODF_Msk     (0x4000000UL)  /*!< GODF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_OPS_OPSCR_GRP_Pos      (24UL)         /*!< GRP (Bit 24)                                          */
+ #define R_GPT_OPS_OPSCR_GRP_Msk      (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
+ #define R_GPT_OPS_OPSCR_ALIGN_Pos    (21UL)         /*!< ALIGN (Bit 21)                                        */
+ #define R_GPT_OPS_OPSCR_ALIGN_Msk    (0x200000UL)   /*!< ALIGN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT_OPS_OPSCR_RV_Pos       (20UL)         /*!< RV (Bit 20)                                           */
+ #define R_GPT_OPS_OPSCR_RV_Msk       (0x100000UL)   /*!< RV (Bitfield-Mask: 0x01)                              */
+ #define R_GPT_OPS_OPSCR_INV_Pos      (19UL)         /*!< INV (Bit 19)                                          */
+ #define R_GPT_OPS_OPSCR_INV_Msk      (0x80000UL)    /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_GPT_OPS_OPSCR_N_Pos        (18UL)         /*!< N (Bit 18)                                            */
+ #define R_GPT_OPS_OPSCR_N_Msk        (0x40000UL)    /*!< N (Bitfield-Mask: 0x01)                               */
+ #define R_GPT_OPS_OPSCR_P_Pos        (17UL)         /*!< P (Bit 17)                                            */
+ #define R_GPT_OPS_OPSCR_P_Msk        (0x20000UL)    /*!< P (Bitfield-Mask: 0x01)                               */
+ #define R_GPT_OPS_OPSCR_FB_Pos       (16UL)         /*!< FB (Bit 16)                                           */
+ #define R_GPT_OPS_OPSCR_FB_Msk       (0x10000UL)    /*!< FB (Bitfield-Mask: 0x01)                              */
+ #define R_GPT_OPS_OPSCR_EN_Pos       (8UL)          /*!< EN (Bit 8)                                            */
+ #define R_GPT_OPS_OPSCR_EN_Msk       (0x100UL)      /*!< EN (Bitfield-Mask: 0x01)                              */
+ #define R_GPT_OPS_OPSCR_W_Pos        (6UL)          /*!< W (Bit 6)                                             */
+ #define R_GPT_OPS_OPSCR_W_Msk        (0x40UL)       /*!< W (Bitfield-Mask: 0x01)                               */
+ #define R_GPT_OPS_OPSCR_V_Pos        (5UL)          /*!< V (Bit 5)                                             */
+ #define R_GPT_OPS_OPSCR_V_Msk        (0x20UL)       /*!< V (Bitfield-Mask: 0x01)                               */
+ #define R_GPT_OPS_OPSCR_U_Pos        (4UL)          /*!< U (Bit 4)                                             */
+ #define R_GPT_OPS_OPSCR_U_Msk        (0x10UL)       /*!< U (Bitfield-Mask: 0x01)                               */
+ #define R_GPT_OPS_OPSCR_WF_Pos       (2UL)          /*!< WF (Bit 2)                                            */
+ #define R_GPT_OPS_OPSCR_WF_Msk       (0x4UL)        /*!< WF (Bitfield-Mask: 0x01)                              */
+ #define R_GPT_OPS_OPSCR_VF_Pos       (1UL)          /*!< VF (Bit 1)                                            */
+ #define R_GPT_OPS_OPSCR_VF_Msk       (0x2UL)        /*!< VF (Bitfield-Mask: 0x01)                              */
+ #define R_GPT_OPS_OPSCR_UF_Pos       (0UL)          /*!< UF (Bit 0)                                            */
+ #define R_GPT_OPS_OPSCR_UF_Msk       (0x1UL)        /*!< UF (Bitfield-Mask: 0x01)                              */
+
+/* =========================================================================================================================== */
+/* ================                                        R_GPT_POEG0                                        ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  POEGG  ========================================================= */
+ #define R_GPT_POEG0_POEGG_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_GPT_POEG0_POEGG_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+ #define R_GPT_POEG0_POEGG_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_GPT_POEG0_POEGG_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_POEG0_POEGG_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_GPT_POEG0_POEGG_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_GPT_POEG0_POEGG_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_GPT_POEG0_POEGG_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_GPT_POEG0_POEGG_CDRE_Pos     (8UL)          /*!< CDRE (Bit 8)                                          */
+ #define R_GPT_POEG0_POEGG_CDRE_Msk     (0x100UL)      /*!< CDRE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_POEG0_POEGG_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_GPT_POEG0_POEGG_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT_POEG0_POEGG_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_GPT_POEG0_POEGG_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_POEG0_POEGG_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_GPT_POEG0_POEGG_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_POEG0_POEGG_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_GPT_POEG0_POEGG_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_GPT_POEG0_POEGG_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_GPT_POEG0_POEGG_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT_POEG0_POEGG_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_GPT_POEG0_POEGG_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_POEG0_POEGG_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_GPT_POEG0_POEGG_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ICU                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  IRQCR  ========================================================= */
+ #define R_ICU_IRQCR_FLTEN_Pos           (7UL)          /*!< FLTEN (Bit 7)                                         */
+ #define R_ICU_IRQCR_FLTEN_Msk           (0x80UL)       /*!< FLTEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_IRQCR_FCLKSEL_Pos         (4UL)          /*!< FCLKSEL (Bit 4)                                       */
+ #define R_ICU_IRQCR_FCLKSEL_Msk         (0x30UL)       /*!< FCLKSEL (Bitfield-Mask: 0x03)                         */
+ #define R_ICU_IRQCR_IRQMD_Pos           (0UL)          /*!< IRQMD (Bit 0)                                         */
+ #define R_ICU_IRQCR_IRQMD_Msk           (0x3UL)        /*!< IRQMD (Bitfield-Mask: 0x03)                           */
+/* =========================================================  NMISR  ========================================================= */
+ #define R_ICU_NMISR_SPEST_Pos           (12UL)         /*!< SPEST (Bit 12)                                        */
+ #define R_ICU_NMISR_SPEST_Msk           (0x1000UL)     /*!< SPEST (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMISR_BUSMST_Pos          (11UL)         /*!< BUSMST (Bit 11)                                       */
+ #define R_ICU_NMISR_BUSMST_Msk          (0x800UL)      /*!< BUSMST (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMISR_BUSSST_Pos          (10UL)         /*!< BUSSST (Bit 10)                                       */
+ #define R_ICU_NMISR_BUSSST_Msk          (0x400UL)      /*!< BUSSST (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMISR_RECCST_Pos          (9UL)          /*!< RECCST (Bit 9)                                        */
+ #define R_ICU_NMISR_RECCST_Msk          (0x200UL)      /*!< RECCST (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMISR_RPEST_Pos           (8UL)          /*!< RPEST (Bit 8)                                         */
+ #define R_ICU_NMISR_RPEST_Msk           (0x100UL)      /*!< RPEST (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMISR_NMIST_Pos           (7UL)          /*!< NMIST (Bit 7)                                         */
+ #define R_ICU_NMISR_NMIST_Msk           (0x80UL)       /*!< NMIST (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMISR_OSTST_Pos           (6UL)          /*!< OSTST (Bit 6)                                         */
+ #define R_ICU_NMISR_OSTST_Msk           (0x40UL)       /*!< OSTST (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMISR_VBATTST_Pos         (4UL)          /*!< VBATTST (Bit 4)                                       */
+ #define R_ICU_NMISR_VBATTST_Msk         (0x10UL)       /*!< VBATTST (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMISR_LVD2ST_Pos          (3UL)          /*!< LVD2ST (Bit 3)                                        */
+ #define R_ICU_NMISR_LVD2ST_Msk          (0x8UL)        /*!< LVD2ST (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMISR_LVD1ST_Pos          (2UL)          /*!< LVD1ST (Bit 2)                                        */
+ #define R_ICU_NMISR_LVD1ST_Msk          (0x4UL)        /*!< LVD1ST (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMISR_WDTST_Pos           (1UL)          /*!< WDTST (Bit 1)                                         */
+ #define R_ICU_NMISR_WDTST_Msk           (0x2UL)        /*!< WDTST (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMISR_IWDTST_Pos          (0UL)          /*!< IWDTST (Bit 0)                                        */
+ #define R_ICU_NMISR_IWDTST_Msk          (0x1UL)        /*!< IWDTST (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMISR_TZFST_Pos           (13UL)         /*!< TZFST (Bit 13)                                        */
+ #define R_ICU_NMISR_TZFST_Msk           (0x2000UL)     /*!< TZFST (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMISR_CPEST_Pos           (15UL)         /*!< CPEST (Bit 15)                                        */
+ #define R_ICU_NMISR_CPEST_Msk           (0x8000UL)     /*!< CPEST (Bitfield-Mask: 0x01)                           */
+/* =========================================================  NMIER  ========================================================= */
+ #define R_ICU_NMIER_SPEEN_Pos           (12UL)         /*!< SPEEN (Bit 12)                                        */
+ #define R_ICU_NMIER_SPEEN_Msk           (0x1000UL)     /*!< SPEEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMIER_BUSMEN_Pos          (11UL)         /*!< BUSMEN (Bit 11)                                       */
+ #define R_ICU_NMIER_BUSMEN_Msk          (0x800UL)      /*!< BUSMEN (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMIER_BUSSEN_Pos          (10UL)         /*!< BUSSEN (Bit 10)                                       */
+ #define R_ICU_NMIER_BUSSEN_Msk          (0x400UL)      /*!< BUSSEN (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMIER_RECCEN_Pos          (9UL)          /*!< RECCEN (Bit 9)                                        */
+ #define R_ICU_NMIER_RECCEN_Msk          (0x200UL)      /*!< RECCEN (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMIER_RPEEN_Pos           (8UL)          /*!< RPEEN (Bit 8)                                         */
+ #define R_ICU_NMIER_RPEEN_Msk           (0x100UL)      /*!< RPEEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMIER_NMIEN_Pos           (7UL)          /*!< NMIEN (Bit 7)                                         */
+ #define R_ICU_NMIER_NMIEN_Msk           (0x80UL)       /*!< NMIEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMIER_OSTEN_Pos           (6UL)          /*!< OSTEN (Bit 6)                                         */
+ #define R_ICU_NMIER_OSTEN_Msk           (0x40UL)       /*!< OSTEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMIER_VBATTEN_Pos         (4UL)          /*!< VBATTEN (Bit 4)                                       */
+ #define R_ICU_NMIER_VBATTEN_Msk         (0x10UL)       /*!< VBATTEN (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMIER_LVD2EN_Pos          (3UL)          /*!< LVD2EN (Bit 3)                                        */
+ #define R_ICU_NMIER_LVD2EN_Msk          (0x8UL)        /*!< LVD2EN (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMIER_LVD1EN_Pos          (2UL)          /*!< LVD1EN (Bit 2)                                        */
+ #define R_ICU_NMIER_LVD1EN_Msk          (0x4UL)        /*!< LVD1EN (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMIER_WDTEN_Pos           (1UL)          /*!< WDTEN (Bit 1)                                         */
+ #define R_ICU_NMIER_WDTEN_Msk           (0x2UL)        /*!< WDTEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMIER_IWDTEN_Pos          (0UL)          /*!< IWDTEN (Bit 0)                                        */
+ #define R_ICU_NMIER_IWDTEN_Msk          (0x1UL)        /*!< IWDTEN (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMIER_TZFEN_Pos           (13UL)         /*!< TZFEN (Bit 13)                                        */
+ #define R_ICU_NMIER_TZFEN_Msk           (0x2000UL)     /*!< TZFEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMIER_CPEEN_Pos           (15UL)         /*!< CPEEN (Bit 15)                                        */
+ #define R_ICU_NMIER_CPEEN_Msk           (0x8000UL)     /*!< CPEEN (Bitfield-Mask: 0x01)                           */
+/* ========================================================  NMICLR  ========================================================= */
+ #define R_ICU_NMICLR_SPECLR_Pos         (12UL)         /*!< SPECLR (Bit 12)                                       */
+ #define R_ICU_NMICLR_SPECLR_Msk         (0x1000UL)     /*!< SPECLR (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMICLR_BUSMCLR_Pos        (11UL)         /*!< BUSMCLR (Bit 11)                                      */
+ #define R_ICU_NMICLR_BUSMCLR_Msk        (0x800UL)      /*!< BUSMCLR (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMICLR_BUSSCLR_Pos        (10UL)         /*!< BUSSCLR (Bit 10)                                      */
+ #define R_ICU_NMICLR_BUSSCLR_Msk        (0x400UL)      /*!< BUSSCLR (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMICLR_RECCCLR_Pos        (9UL)          /*!< RECCCLR (Bit 9)                                       */
+ #define R_ICU_NMICLR_RECCCLR_Msk        (0x200UL)      /*!< RECCCLR (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMICLR_RPECLR_Pos         (8UL)          /*!< RPECLR (Bit 8)                                        */
+ #define R_ICU_NMICLR_RPECLR_Msk         (0x100UL)      /*!< RPECLR (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMICLR_NMICLR_Pos         (7UL)          /*!< NMICLR (Bit 7)                                        */
+ #define R_ICU_NMICLR_NMICLR_Msk         (0x80UL)       /*!< NMICLR (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMICLR_OSTCLR_Pos         (6UL)          /*!< OSTCLR (Bit 6)                                        */
+ #define R_ICU_NMICLR_OSTCLR_Msk         (0x40UL)       /*!< OSTCLR (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMICLR_VBATTCLR_Pos       (4UL)          /*!< VBATTCLR (Bit 4)                                      */
+ #define R_ICU_NMICLR_VBATTCLR_Msk       (0x10UL)       /*!< VBATTCLR (Bitfield-Mask: 0x01)                        */
+ #define R_ICU_NMICLR_LVD2CLR_Pos        (3UL)          /*!< LVD2CLR (Bit 3)                                       */
+ #define R_ICU_NMICLR_LVD2CLR_Msk        (0x8UL)        /*!< LVD2CLR (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMICLR_LVD1CLR_Pos        (2UL)          /*!< LVD1CLR (Bit 2)                                       */
+ #define R_ICU_NMICLR_LVD1CLR_Msk        (0x4UL)        /*!< LVD1CLR (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMICLR_WDTCLR_Pos         (1UL)          /*!< WDTCLR (Bit 1)                                        */
+ #define R_ICU_NMICLR_WDTCLR_Msk         (0x2UL)        /*!< WDTCLR (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMICLR_IWDTCLR_Pos        (0UL)          /*!< IWDTCLR (Bit 0)                                       */
+ #define R_ICU_NMICLR_IWDTCLR_Msk        (0x1UL)        /*!< IWDTCLR (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMICLR_TZFCLR_Pos         (13UL)         /*!< TZFCLR (Bit 13)                                       */
+ #define R_ICU_NMICLR_TZFCLR_Msk         (0x2000UL)     /*!< TZFCLR (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMICLR_CPECLR_Pos         (15UL)         /*!< CPECLR (Bit 15)                                       */
+ #define R_ICU_NMICLR_CPECLR_Msk         (0x8000UL)     /*!< CPECLR (Bitfield-Mask: 0x01)                          */
+/* =========================================================  NMICR  ========================================================= */
+ #define R_ICU_NMICR_NFLTEN_Pos          (7UL)          /*!< NFLTEN (Bit 7)                                        */
+ #define R_ICU_NMICR_NFLTEN_Msk          (0x80UL)       /*!< NFLTEN (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMICR_NFCLKSEL_Pos        (4UL)          /*!< NFCLKSEL (Bit 4)                                      */
+ #define R_ICU_NMICR_NFCLKSEL_Msk        (0x30UL)       /*!< NFCLKSEL (Bitfield-Mask: 0x03)                        */
+ #define R_ICU_NMICR_NMIMD_Pos           (0UL)          /*!< NMIMD (Bit 0)                                         */
+ #define R_ICU_NMICR_NMIMD_Msk           (0x1UL)        /*!< NMIMD (Bitfield-Mask: 0x01)                           */
+/* =========================================================  IELSR  ========================================================= */
+ #define R_ICU_IELSR_DTCE_Pos            (24UL)         /*!< DTCE (Bit 24)                                         */
+ #define R_ICU_IELSR_DTCE_Msk            (0x1000000UL)  /*!< DTCE (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_IELSR_IR_Pos              (16UL)         /*!< IR (Bit 16)                                           */
+ #define R_ICU_IELSR_IR_Msk              (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
+ #define R_ICU_IELSR_IELS_Pos            (0UL)          /*!< IELS (Bit 0)                                          */
+ #define R_ICU_IELSR_IELS_Msk            (0x1ffUL)      /*!< IELS (Bitfield-Mask: 0x1ff)                           */
+/* =========================================================  DELSR  ========================================================= */
+ #define R_ICU_DELSR_IR_Pos              (16UL)         /*!< IR (Bit 16)                                           */
+ #define R_ICU_DELSR_IR_Msk              (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
+ #define R_ICU_DELSR_DELS_Pos            (0UL)          /*!< DELS (Bit 0)                                          */
+ #define R_ICU_DELSR_DELS_Msk            (0x1ffUL)      /*!< DELS (Bitfield-Mask: 0x1ff)                           */
+/* ========================================================  SELSR0  ========================================================= */
+ #define R_ICU_SELSR0_SELS_Pos           (0UL)          /*!< SELS (Bit 0)                                          */
+ #define R_ICU_SELSR0_SELS_Msk           (0x1ffUL)      /*!< SELS (Bitfield-Mask: 0x1ff)                           */
+/* =========================================================  WUPEN  ========================================================= */
+ #define R_ICU_WUPEN_IIC0WUPEN_Pos       (31UL)         /*!< IIC0WUPEN (Bit 31)                                    */
+ #define R_ICU_WUPEN_IIC0WUPEN_Msk       (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01)                       */
+ #define R_ICU_WUPEN_AGT1CBWUPEN_Pos     (30UL)         /*!< AGT1CBWUPEN (Bit 30)                                  */
+ #define R_ICU_WUPEN_AGT1CBWUPEN_Msk     (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01)                     */
+ #define R_ICU_WUPEN_AGT1CAWUPEN_Pos     (29UL)         /*!< AGT1CAWUPEN (Bit 29)                                  */
+ #define R_ICU_WUPEN_AGT1CAWUPEN_Msk     (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01)                     */
+ #define R_ICU_WUPEN_AGT1UDWUPEN_Pos     (28UL)         /*!< AGT1UDWUPEN (Bit 28)                                  */
+ #define R_ICU_WUPEN_AGT1UDWUPEN_Msk     (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01)                     */
+ #define R_ICU_WUPEN_USBFSWUPEN_Pos      (27UL)         /*!< USBFSWUPEN (Bit 27)                                   */
+ #define R_ICU_WUPEN_USBFSWUPEN_Msk      (0x8000000UL)  /*!< USBFSWUPEN (Bitfield-Mask: 0x01)                      */
+ #define R_ICU_WUPEN_USBHSWUPEN_Pos      (26UL)         /*!< USBHSWUPEN (Bit 26)                                   */
+ #define R_ICU_WUPEN_USBHSWUPEN_Msk      (0x4000000UL)  /*!< USBHSWUPEN (Bitfield-Mask: 0x01)                      */
+ #define R_ICU_WUPEN_RTCPRDWUPEN_Pos     (25UL)         /*!< RTCPRDWUPEN (Bit 25)                                  */
+ #define R_ICU_WUPEN_RTCPRDWUPEN_Msk     (0x2000000UL)  /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01)                     */
+ #define R_ICU_WUPEN_RTCALMWUPEN_Pos     (24UL)         /*!< RTCALMWUPEN (Bit 24)                                  */
+ #define R_ICU_WUPEN_RTCALMWUPEN_Msk     (0x1000000UL)  /*!< RTCALMWUPEN (Bitfield-Mask: 0x01)                     */
+ #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos    (23UL)         /*!< ACMPLP0WUPEN (Bit 23)                                 */
+ #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk    (0x800000UL)   /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01)                    */
+ #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos    (22UL)         /*!< ACMPHS0WUPEN (Bit 22)                                 */
+ #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk    (0x400000UL)   /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01)                    */
+ #define R_ICU_WUPEN_VBATTWUPEN_Pos      (20UL)         /*!< VBATTWUPEN (Bit 20)                                   */
+ #define R_ICU_WUPEN_VBATTWUPEN_Msk      (0x100000UL)   /*!< VBATTWUPEN (Bitfield-Mask: 0x01)                      */
+ #define R_ICU_WUPEN_LVD2WUPEN_Pos       (19UL)         /*!< LVD2WUPEN (Bit 19)                                    */
+ #define R_ICU_WUPEN_LVD2WUPEN_Msk       (0x80000UL)    /*!< LVD2WUPEN (Bitfield-Mask: 0x01)                       */
+ #define R_ICU_WUPEN_LVD1WUPEN_Pos       (18UL)         /*!< LVD1WUPEN (Bit 18)                                    */
+ #define R_ICU_WUPEN_LVD1WUPEN_Msk       (0x40000UL)    /*!< LVD1WUPEN (Bitfield-Mask: 0x01)                       */
+ #define R_ICU_WUPEN_KEYWUPEN_Pos        (17UL)         /*!< KEYWUPEN (Bit 17)                                     */
+ #define R_ICU_WUPEN_KEYWUPEN_Msk        (0x20000UL)    /*!< KEYWUPEN (Bitfield-Mask: 0x01)                        */
+ #define R_ICU_WUPEN_IWDTWUPEN_Pos       (16UL)         /*!< IWDTWUPEN (Bit 16)                                    */
+ #define R_ICU_WUPEN_IWDTWUPEN_Msk       (0x10000UL)    /*!< IWDTWUPEN (Bitfield-Mask: 0x01)                       */
+ #define R_ICU_WUPEN_IRQWUPEN_Pos        (0UL)          /*!< IRQWUPEN (Bit 0)                                      */
+ #define R_ICU_WUPEN_IRQWUPEN_Msk        (0x1UL)        /*!< IRQWUPEN (Bitfield-Mask: 0x01)                        */
+/* ========================================================  WUPEN1  ========================================================= */
+ #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos    (0UL)          /*!< AGT3UDWUPEN (Bit 0)                                   */
+ #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk    (0x1UL)        /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01)                     */
+ #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos    (1UL)          /*!< AGT3CAWUPEN (Bit 1)                                   */
+ #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk    (0x2UL)        /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01)                     */
+ #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos    (2UL)          /*!< AGT3CBWUPEN (Bit 2)                                   */
+ #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk    (0x4UL)        /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01)                     */
+/* =========================================================  IELEN  ========================================================= */
+ #define R_ICU_IELEN_IELEN_Pos           (1UL)          /*!< IELEN (Bit 1)                                         */
+ #define R_ICU_IELEN_IELEN_Msk           (0x2UL)        /*!< IELEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_IELEN_RTCINTEN_Pos        (0UL)          /*!< RTCINTEN (Bit 0)                                      */
+ #define R_ICU_IELEN_RTCINTEN_Msk        (0x1UL)        /*!< RTCINTEN (Bitfield-Mask: 0x01)                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_IIC0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ICCR1  ========================================================= */
+ #define R_IIC0_ICCR1_ICE_Pos        (7UL)    /*!< ICE (Bit 7)                                           */
+ #define R_IIC0_ICCR1_ICE_Msk        (0x80UL) /*!< ICE (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICCR1_IICRST_Pos     (6UL)    /*!< IICRST (Bit 6)                                        */
+ #define R_IIC0_ICCR1_IICRST_Msk     (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01)                          */
+ #define R_IIC0_ICCR1_CLO_Pos        (5UL)    /*!< CLO (Bit 5)                                           */
+ #define R_IIC0_ICCR1_CLO_Msk        (0x20UL) /*!< CLO (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICCR1_SOWP_Pos       (4UL)    /*!< SOWP (Bit 4)                                          */
+ #define R_IIC0_ICCR1_SOWP_Msk       (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_SCLO_Pos       (3UL)    /*!< SCLO (Bit 3)                                          */
+ #define R_IIC0_ICCR1_SCLO_Msk       (0x8UL)  /*!< SCLO (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_SDAO_Pos       (2UL)    /*!< SDAO (Bit 2)                                          */
+ #define R_IIC0_ICCR1_SDAO_Msk       (0x4UL)  /*!< SDAO (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_SCLI_Pos       (1UL)    /*!< SCLI (Bit 1)                                          */
+ #define R_IIC0_ICCR1_SCLI_Msk       (0x2UL)  /*!< SCLI (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_SDAI_Pos       (0UL)    /*!< SDAI (Bit 0)                                          */
+ #define R_IIC0_ICCR1_SDAI_Msk       (0x1UL)  /*!< SDAI (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICCR2  ========================================================= */
+ #define R_IIC0_ICCR2_BBSY_Pos       (7UL)    /*!< BBSY (Bit 7)                                          */
+ #define R_IIC0_ICCR2_BBSY_Msk       (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR2_MST_Pos        (6UL)    /*!< MST (Bit 6)                                           */
+ #define R_IIC0_ICCR2_MST_Msk        (0x40UL) /*!< MST (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICCR2_TRS_Pos        (5UL)    /*!< TRS (Bit 5)                                           */
+ #define R_IIC0_ICCR2_TRS_Msk        (0x20UL) /*!< TRS (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICCR2_SP_Pos         (3UL)    /*!< SP (Bit 3)                                            */
+ #define R_IIC0_ICCR2_SP_Msk         (0x8UL)  /*!< SP (Bitfield-Mask: 0x01)                              */
+ #define R_IIC0_ICCR2_RS_Pos         (2UL)    /*!< RS (Bit 2)                                            */
+ #define R_IIC0_ICCR2_RS_Msk         (0x4UL)  /*!< RS (Bitfield-Mask: 0x01)                              */
+ #define R_IIC0_ICCR2_ST_Pos         (1UL)    /*!< ST (Bit 1)                                            */
+ #define R_IIC0_ICCR2_ST_Msk         (0x2UL)  /*!< ST (Bitfield-Mask: 0x01)                              */
+/* =========================================================  ICMR1  ========================================================= */
+ #define R_IIC0_ICMR1_MTWP_Pos       (7UL)    /*!< MTWP (Bit 7)                                          */
+ #define R_IIC0_ICMR1_MTWP_Msk       (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR1_CKS_Pos        (4UL)    /*!< CKS (Bit 4)                                           */
+ #define R_IIC0_ICMR1_CKS_Msk        (0x70UL) /*!< CKS (Bitfield-Mask: 0x07)                             */
+ #define R_IIC0_ICMR1_BCWP_Pos       (3UL)    /*!< BCWP (Bit 3)                                          */
+ #define R_IIC0_ICMR1_BCWP_Msk       (0x8UL)  /*!< BCWP (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR1_BC_Pos         (0UL)    /*!< BC (Bit 0)                                            */
+ #define R_IIC0_ICMR1_BC_Msk         (0x7UL)  /*!< BC (Bitfield-Mask: 0x07)                              */
+/* =========================================================  ICMR2  ========================================================= */
+ #define R_IIC0_ICMR2_DLCS_Pos       (7UL)    /*!< DLCS (Bit 7)                                          */
+ #define R_IIC0_ICMR2_DLCS_Msk       (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR2_SDDL_Pos       (4UL)    /*!< SDDL (Bit 4)                                          */
+ #define R_IIC0_ICMR2_SDDL_Msk       (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07)                            */
+ #define R_IIC0_ICMR2_TMOH_Pos       (2UL)    /*!< TMOH (Bit 2)                                          */
+ #define R_IIC0_ICMR2_TMOH_Msk       (0x4UL)  /*!< TMOH (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR2_TMOL_Pos       (1UL)    /*!< TMOL (Bit 1)                                          */
+ #define R_IIC0_ICMR2_TMOL_Msk       (0x2UL)  /*!< TMOL (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR2_TMOS_Pos       (0UL)    /*!< TMOS (Bit 0)                                          */
+ #define R_IIC0_ICMR2_TMOS_Msk       (0x1UL)  /*!< TMOS (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICMR3  ========================================================= */
+ #define R_IIC0_ICMR3_SMBS_Pos       (7UL)    /*!< SMBS (Bit 7)                                          */
+ #define R_IIC0_ICMR3_SMBS_Msk       (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR3_WAIT_Pos       (6UL)    /*!< WAIT (Bit 6)                                          */
+ #define R_IIC0_ICMR3_WAIT_Msk       (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR3_RDRFS_Pos      (5UL)    /*!< RDRFS (Bit 5)                                         */
+ #define R_IIC0_ICMR3_RDRFS_Msk      (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICMR3_ACKWP_Pos      (4UL)    /*!< ACKWP (Bit 4)                                         */
+ #define R_IIC0_ICMR3_ACKWP_Msk      (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICMR3_ACKBT_Pos      (3UL)    /*!< ACKBT (Bit 3)                                         */
+ #define R_IIC0_ICMR3_ACKBT_Msk      (0x8UL)  /*!< ACKBT (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICMR3_ACKBR_Pos      (2UL)    /*!< ACKBR (Bit 2)                                         */
+ #define R_IIC0_ICMR3_ACKBR_Msk      (0x4UL)  /*!< ACKBR (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICMR3_NF_Pos         (0UL)    /*!< NF (Bit 0)                                            */
+ #define R_IIC0_ICMR3_NF_Msk         (0x3UL)  /*!< NF (Bitfield-Mask: 0x03)                              */
+/* =========================================================  ICFER  ========================================================= */
+ #define R_IIC0_ICFER_FMPE_Pos       (7UL)    /*!< FMPE (Bit 7)                                          */
+ #define R_IIC0_ICFER_FMPE_Msk       (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_SCLE_Pos       (6UL)    /*!< SCLE (Bit 6)                                          */
+ #define R_IIC0_ICFER_SCLE_Msk       (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_NFE_Pos        (5UL)    /*!< NFE (Bit 5)                                           */
+ #define R_IIC0_ICFER_NFE_Msk        (0x20UL) /*!< NFE (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICFER_NACKE_Pos      (4UL)    /*!< NACKE (Bit 4)                                         */
+ #define R_IIC0_ICFER_NACKE_Msk      (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICFER_SALE_Pos       (3UL)    /*!< SALE (Bit 3)                                          */
+ #define R_IIC0_ICFER_SALE_Msk       (0x8UL)  /*!< SALE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_NALE_Pos       (2UL)    /*!< NALE (Bit 2)                                          */
+ #define R_IIC0_ICFER_NALE_Msk       (0x4UL)  /*!< NALE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_MALE_Pos       (1UL)    /*!< MALE (Bit 1)                                          */
+ #define R_IIC0_ICFER_MALE_Msk       (0x2UL)  /*!< MALE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_TMOE_Pos       (0UL)    /*!< TMOE (Bit 0)                                          */
+ #define R_IIC0_ICFER_TMOE_Msk       (0x1UL)  /*!< TMOE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICSER  ========================================================= */
+ #define R_IIC0_ICSER_HOAE_Pos       (7UL)    /*!< HOAE (Bit 7)                                          */
+ #define R_IIC0_ICSER_HOAE_Msk       (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSER_DIDE_Pos       (5UL)    /*!< DIDE (Bit 5)                                          */
+ #define R_IIC0_ICSER_DIDE_Msk       (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSER_GCAE_Pos       (3UL)    /*!< GCAE (Bit 3)                                          */
+ #define R_IIC0_ICSER_GCAE_Msk       (0x8UL)  /*!< GCAE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSER_SAR2E_Pos      (2UL)    /*!< SAR2E (Bit 2)                                         */
+ #define R_IIC0_ICSER_SAR2E_Msk      (0x4UL)  /*!< SAR2E (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSER_SAR1E_Pos      (1UL)    /*!< SAR1E (Bit 1)                                         */
+ #define R_IIC0_ICSER_SAR1E_Msk      (0x2UL)  /*!< SAR1E (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSER_SAR0E_Pos      (0UL)    /*!< SAR0E (Bit 0)                                         */
+ #define R_IIC0_ICSER_SAR0E_Msk      (0x1UL)  /*!< SAR0E (Bitfield-Mask: 0x01)                           */
+/* =========================================================  ICIER  ========================================================= */
+ #define R_IIC0_ICIER_TIE_Pos        (7UL)    /*!< TIE (Bit 7)                                           */
+ #define R_IIC0_ICIER_TIE_Msk        (0x80UL) /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICIER_TEIE_Pos       (6UL)    /*!< TEIE (Bit 6)                                          */
+ #define R_IIC0_ICIER_TEIE_Msk       (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICIER_RIE_Pos        (5UL)    /*!< RIE (Bit 5)                                           */
+ #define R_IIC0_ICIER_RIE_Msk        (0x20UL) /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICIER_NAKIE_Pos      (4UL)    /*!< NAKIE (Bit 4)                                         */
+ #define R_IIC0_ICIER_NAKIE_Msk      (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICIER_SPIE_Pos       (3UL)    /*!< SPIE (Bit 3)                                          */
+ #define R_IIC0_ICIER_SPIE_Msk       (0x8UL)  /*!< SPIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICIER_STIE_Pos       (2UL)    /*!< STIE (Bit 2)                                          */
+ #define R_IIC0_ICIER_STIE_Msk       (0x4UL)  /*!< STIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICIER_ALIE_Pos       (1UL)    /*!< ALIE (Bit 1)                                          */
+ #define R_IIC0_ICIER_ALIE_Msk       (0x2UL)  /*!< ALIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICIER_TMOIE_Pos      (0UL)    /*!< TMOIE (Bit 0)                                         */
+ #define R_IIC0_ICIER_TMOIE_Msk      (0x1UL)  /*!< TMOIE (Bitfield-Mask: 0x01)                           */
+/* =========================================================  ICSR1  ========================================================= */
+ #define R_IIC0_ICSR1_HOA_Pos        (7UL)    /*!< HOA (Bit 7)                                           */
+ #define R_IIC0_ICSR1_HOA_Msk        (0x80UL) /*!< HOA (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICSR1_DID_Pos        (5UL)    /*!< DID (Bit 5)                                           */
+ #define R_IIC0_ICSR1_DID_Msk        (0x20UL) /*!< DID (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICSR1_GCA_Pos        (3UL)    /*!< GCA (Bit 3)                                           */
+ #define R_IIC0_ICSR1_GCA_Msk        (0x8UL)  /*!< GCA (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICSR1_AAS2_Pos       (2UL)    /*!< AAS2 (Bit 2)                                          */
+ #define R_IIC0_ICSR1_AAS2_Msk       (0x4UL)  /*!< AAS2 (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR1_AAS1_Pos       (1UL)    /*!< AAS1 (Bit 1)                                          */
+ #define R_IIC0_ICSR1_AAS1_Msk       (0x2UL)  /*!< AAS1 (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR1_AAS0_Pos       (0UL)    /*!< AAS0 (Bit 0)                                          */
+ #define R_IIC0_ICSR1_AAS0_Msk       (0x1UL)  /*!< AAS0 (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICSR2  ========================================================= */
+ #define R_IIC0_ICSR2_TDRE_Pos       (7UL)    /*!< TDRE (Bit 7)                                          */
+ #define R_IIC0_ICSR2_TDRE_Msk       (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR2_TEND_Pos       (6UL)    /*!< TEND (Bit 6)                                          */
+ #define R_IIC0_ICSR2_TEND_Msk       (0x40UL) /*!< TEND (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR2_RDRF_Pos       (5UL)    /*!< RDRF (Bit 5)                                          */
+ #define R_IIC0_ICSR2_RDRF_Msk       (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR2_NACKF_Pos      (4UL)    /*!< NACKF (Bit 4)                                         */
+ #define R_IIC0_ICSR2_NACKF_Msk      (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSR2_STOP_Pos       (3UL)    /*!< STOP (Bit 3)                                          */
+ #define R_IIC0_ICSR2_STOP_Msk       (0x8UL)  /*!< STOP (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR2_START_Pos      (2UL)    /*!< START (Bit 2)                                         */
+ #define R_IIC0_ICSR2_START_Msk      (0x4UL)  /*!< START (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSR2_AL_Pos         (1UL)    /*!< AL (Bit 1)                                            */
+ #define R_IIC0_ICSR2_AL_Msk         (0x2UL)  /*!< AL (Bitfield-Mask: 0x01)                              */
+ #define R_IIC0_ICSR2_TMOF_Pos       (0UL)    /*!< TMOF (Bit 0)                                          */
+ #define R_IIC0_ICSR2_TMOF_Msk       (0x1UL)  /*!< TMOF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICBRL  ========================================================= */
+ #define R_IIC0_ICBRL_BRL_Pos        (0UL)    /*!< BRL (Bit 0)                                           */
+ #define R_IIC0_ICBRL_BRL_Msk        (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f)                             */
+/* =========================================================  ICBRH  ========================================================= */
+ #define R_IIC0_ICBRH_BRH_Pos        (0UL)    /*!< BRH (Bit 0)                                           */
+ #define R_IIC0_ICBRH_BRH_Msk        (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f)                             */
+/* =========================================================  ICDRT  ========================================================= */
+ #define R_IIC0_ICDRT_ICDRT_Pos      (0UL)    /*!< ICDRT (Bit 0)                                         */
+ #define R_IIC0_ICDRT_ICDRT_Msk      (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff)                           */
+/* =========================================================  ICDRR  ========================================================= */
+ #define R_IIC0_ICDRR_ICDRR_Pos      (0UL)    /*!< ICDRR (Bit 0)                                         */
+ #define R_IIC0_ICDRR_ICDRR_Msk      (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff)                           */
+/* =========================================================  ICWUR  ========================================================= */
+ #define R_IIC0_ICWUR_WUE_Pos        (7UL)    /*!< WUE (Bit 7)                                           */
+ #define R_IIC0_ICWUR_WUE_Msk        (0x80UL) /*!< WUE (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICWUR_WUIE_Pos       (6UL)    /*!< WUIE (Bit 6)                                          */
+ #define R_IIC0_ICWUR_WUIE_Msk       (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICWUR_WUF_Pos        (5UL)    /*!< WUF (Bit 5)                                           */
+ #define R_IIC0_ICWUR_WUF_Msk        (0x20UL) /*!< WUF (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICWUR_WUACK_Pos      (4UL)    /*!< WUACK (Bit 4)                                         */
+ #define R_IIC0_ICWUR_WUACK_Msk      (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICWUR_WUAFA_Pos      (0UL)    /*!< WUAFA (Bit 0)                                         */
+ #define R_IIC0_ICWUR_WUAFA_Msk      (0x1UL)  /*!< WUAFA (Bitfield-Mask: 0x01)                           */
+/* ========================================================  ICWUR2  ========================================================= */
+ #define R_IIC0_ICWUR2_WUSYF_Pos     (2UL)    /*!< WUSYF (Bit 2)                                         */
+ #define R_IIC0_ICWUR2_WUSYF_Msk     (0x4UL)  /*!< WUSYF (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICWUR2_WUASYF_Pos    (1UL)    /*!< WUASYF (Bit 1)                                        */
+ #define R_IIC0_ICWUR2_WUASYF_Msk    (0x2UL)  /*!< WUASYF (Bitfield-Mask: 0x01)                          */
+ #define R_IIC0_ICWUR2_WUSEN_Pos     (0UL)    /*!< WUSEN (Bit 0)                                         */
+ #define R_IIC0_ICWUR2_WUSEN_Msk     (0x1UL)  /*!< WUSEN (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                          R_IWDT                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  IWDTRR  ========================================================= */
+ #define R_IWDT_IWDTRR_IWDTRR_Pos       (0UL)      /*!< IWDTRR (Bit 0)                                        */
+ #define R_IWDT_IWDTRR_IWDTRR_Msk       (0xffUL)   /*!< IWDTRR (Bitfield-Mask: 0xff)                          */
+/* ========================================================  IWDTCR  ========================================================= */
+ #define R_IWDT_IWDTCR_RPSS_Pos         (12UL)     /*!< RPSS (Bit 12)                                         */
+ #define R_IWDT_IWDTCR_RPSS_Msk         (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
+ #define R_IWDT_IWDTCR_RPES_Pos         (8UL)      /*!< RPES (Bit 8)                                          */
+ #define R_IWDT_IWDTCR_RPES_Msk         (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
+ #define R_IWDT_IWDTCR_CKS_Pos          (4UL)      /*!< CKS (Bit 4)                                           */
+ #define R_IWDT_IWDTCR_CKS_Msk          (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
+ #define R_IWDT_IWDTCR_TOPS_Pos         (0UL)      /*!< TOPS (Bit 0)                                          */
+ #define R_IWDT_IWDTCR_TOPS_Msk         (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
+/* ========================================================  IWDTSR  ========================================================= */
+ #define R_IWDT_IWDTSR_REFEF_Pos        (15UL)     /*!< REFEF (Bit 15)                                        */
+ #define R_IWDT_IWDTSR_REFEF_Msk        (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
+ #define R_IWDT_IWDTSR_UNDFF_Pos        (14UL)     /*!< UNDFF (Bit 14)                                        */
+ #define R_IWDT_IWDTSR_UNDFF_Msk        (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
+ #define R_IWDT_IWDTSR_CNTVAL_Pos       (0UL)      /*!< CNTVAL (Bit 0)                                        */
+ #define R_IWDT_IWDTSR_CNTVAL_Msk       (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
+/* ========================================================  IWDTRCR  ======================================================== */
+ #define R_IWDT_IWDTRCR_RSTIRQS_Pos     (7UL)      /*!< RSTIRQS (Bit 7)                                       */
+ #define R_IWDT_IWDTRCR_RSTIRQS_Msk     (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
+/* =======================================================  IWDTCSTPR  ======================================================= */
+ #define R_IWDT_IWDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
+ #define R_IWDT_IWDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_I3C0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  PRTS  ========================================================== */
+ #define R_I3C0_PRTS_PRTMD_Pos          (0UL)          /*!< PRTMD (Bit 0)                                         */
+ #define R_I3C0_PRTS_PRTMD_Msk          (0x1UL)        /*!< PRTMD (Bitfield-Mask: 0x01)                           */
+/* =========================================================  CECTL  ========================================================= */
+ #define R_I3C0_CECTL_CLKE_Pos          (0UL)          /*!< CLKE (Bit 0)                                          */
+ #define R_I3C0_CECTL_CLKE_Msk          (0x1UL)        /*!< CLKE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  BCTL  ========================================================== */
+ #define R_I3C0_BCTL_INCBA_Pos          (0UL)          /*!< INCBA (Bit 0)                                         */
+ #define R_I3C0_BCTL_INCBA_Msk          (0x1UL)        /*!< INCBA (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_BCTL_BMDS_Pos           (7UL)          /*!< BMDS (Bit 7)                                          */
+ #define R_I3C0_BCTL_BMDS_Msk           (0x80UL)       /*!< BMDS (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_BCTL_HJACKCTL_Pos       (8UL)          /*!< HJACKCTL (Bit 8)                                      */
+ #define R_I3C0_BCTL_HJACKCTL_Msk       (0x100UL)      /*!< HJACKCTL (Bitfield-Mask: 0x01)                        */
+ #define R_I3C0_BCTL_ABT_Pos            (29UL)         /*!< ABT (Bit 29)                                          */
+ #define R_I3C0_BCTL_ABT_Msk            (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01)                             */
+ #define R_I3C0_BCTL_RSM_Pos            (30UL)         /*!< RSM (Bit 30)                                          */
+ #define R_I3C0_BCTL_RSM_Msk            (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01)                             */
+ #define R_I3C0_BCTL_BUSE_Pos           (31UL)         /*!< BUSE (Bit 31)                                         */
+ #define R_I3C0_BCTL_BUSE_Msk           (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  MSDVAD  ========================================================= */
+ #define R_I3C0_MSDVAD_MDYAD_Pos        (16UL)         /*!< MDYAD (Bit 16)                                        */
+ #define R_I3C0_MSDVAD_MDYAD_Msk        (0x7f0000UL)   /*!< MDYAD (Bitfield-Mask: 0x7f)                           */
+ #define R_I3C0_MSDVAD_MDYADV_Pos       (31UL)         /*!< MDYADV (Bit 31)                                       */
+ #define R_I3C0_MSDVAD_MDYADV_Msk       (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01)                          */
+/* ========================================================  RSTCTL  ========================================================= */
+ #define R_I3C0_RSTCTL_RI3CRST_Pos      (0UL)          /*!< RI3CRST (Bit 0)                                       */
+ #define R_I3C0_RSTCTL_RI3CRST_Msk      (0x1UL)        /*!< RI3CRST (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_RSTCTL_CMDQRST_Pos      (1UL)          /*!< CMDQRST (Bit 1)                                       */
+ #define R_I3C0_RSTCTL_CMDQRST_Msk      (0x2UL)        /*!< CMDQRST (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_RSTCTL_RSPQRST_Pos      (2UL)          /*!< RSPQRST (Bit 2)                                       */
+ #define R_I3C0_RSTCTL_RSPQRST_Msk      (0x4UL)        /*!< RSPQRST (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_RSTCTL_TDBRST_Pos       (3UL)          /*!< TDBRST (Bit 3)                                        */
+ #define R_I3C0_RSTCTL_TDBRST_Msk       (0x8UL)        /*!< TDBRST (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_RSTCTL_RDBRST_Pos       (4UL)          /*!< RDBRST (Bit 4)                                        */
+ #define R_I3C0_RSTCTL_RDBRST_Msk       (0x10UL)       /*!< RDBRST (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_RSTCTL_IBIQRST_Pos      (5UL)          /*!< IBIQRST (Bit 5)                                       */
+ #define R_I3C0_RSTCTL_IBIQRST_Msk      (0x20UL)       /*!< IBIQRST (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_RSTCTL_RSQRST_Pos       (6UL)          /*!< RSQRST (Bit 6)                                        */
+ #define R_I3C0_RSTCTL_RSQRST_Msk       (0x40UL)       /*!< RSQRST (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_RSTCTL_INTLRST_Pos      (16UL)         /*!< INTLRST (Bit 16)                                      */
+ #define R_I3C0_RSTCTL_INTLRST_Msk      (0x10000UL)    /*!< INTLRST (Bitfield-Mask: 0x01)                         */
+/* =========================================================  PRSST  ========================================================= */
+ #define R_I3C0_PRSST_CRMS_Pos          (2UL)          /*!< CRMS (Bit 2)                                          */
+ #define R_I3C0_PRSST_CRMS_Msk          (0x4UL)        /*!< CRMS (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_PRSST_TRMD_Pos          (4UL)          /*!< TRMD (Bit 4)                                          */
+ #define R_I3C0_PRSST_TRMD_Msk          (0x10UL)       /*!< TRMD (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_PRSST_PRSSTWP_Pos       (7UL)          /*!< PRSSTWP (Bit 7)                                       */
+ #define R_I3C0_PRSST_PRSSTWP_Msk       (0x80UL)       /*!< PRSSTWP (Bitfield-Mask: 0x01)                         */
+/* =========================================================  INST  ========================================================== */
+ #define R_I3C0_INST_INEF_Pos           (10UL)         /*!< INEF (Bit 10)                                         */
+ #define R_I3C0_INST_INEF_Msk           (0x400UL)      /*!< INEF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  INSTE  ========================================================= */
+ #define R_I3C0_INSTE_INEE_Pos          (10UL)         /*!< INEE (Bit 10)                                         */
+ #define R_I3C0_INSTE_INEE_Msk          (0x400UL)      /*!< INEE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  INIE  ========================================================== */
+ #define R_I3C0_INIE_INEIE_Pos          (10UL)         /*!< INEIE (Bit 10)                                        */
+ #define R_I3C0_INIE_INEIE_Msk          (0x400UL)      /*!< INEIE (Bitfield-Mask: 0x01)                           */
+/* ========================================================  INSTFC  ========================================================= */
+ #define R_I3C0_INSTFC_INEFC_Pos        (10UL)         /*!< INEFC (Bit 10)                                        */
+ #define R_I3C0_INSTFC_INEFC_Msk        (0x400UL)      /*!< INEFC (Bitfield-Mask: 0x01)                           */
+/* =========================================================  DVCT  ========================================================== */
+ #define R_I3C0_DVCT_IDX_Pos            (19UL)         /*!< IDX (Bit 19)                                          */
+ #define R_I3C0_DVCT_IDX_Msk            (0xf80000UL)   /*!< IDX (Bitfield-Mask: 0x1f)                             */
+/* ========================================================  IBINCTL  ======================================================== */
+ #define R_I3C0_IBINCTL_NRHJCTL_Pos     (0UL)          /*!< NRHJCTL (Bit 0)                                       */
+ #define R_I3C0_IBINCTL_NRHJCTL_Msk     (0x1UL)        /*!< NRHJCTL (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_IBINCTL_NRMRCTL_Pos     (1UL)          /*!< NRMRCTL (Bit 1)                                       */
+ #define R_I3C0_IBINCTL_NRMRCTL_Msk     (0x2UL)        /*!< NRMRCTL (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_IBINCTL_NRSIRCTL_Pos    (3UL)          /*!< NRSIRCTL (Bit 3)                                      */
+ #define R_I3C0_IBINCTL_NRSIRCTL_Msk    (0x8UL)        /*!< NRSIRCTL (Bitfield-Mask: 0x01)                        */
+/* =========================================================  BFCTL  ========================================================= */
+ #define R_I3C0_BFCTL_MALE_Pos          (0UL)          /*!< MALE (Bit 0)                                          */
+ #define R_I3C0_BFCTL_MALE_Msk          (0x1UL)        /*!< MALE (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_BFCTL_NALE_Pos          (1UL)          /*!< NALE (Bit 1)                                          */
+ #define R_I3C0_BFCTL_NALE_Msk          (0x2UL)        /*!< NALE (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_BFCTL_SALE_Pos          (2UL)          /*!< SALE (Bit 2)                                          */
+ #define R_I3C0_BFCTL_SALE_Msk          (0x4UL)        /*!< SALE (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_BFCTL_SCSYNE_Pos        (8UL)          /*!< SCSYNE (Bit 8)                                        */
+ #define R_I3C0_BFCTL_SCSYNE_Msk        (0x100UL)      /*!< SCSYNE (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_BFCTL_SMBS_Pos          (12UL)         /*!< SMBS (Bit 12)                                         */
+ #define R_I3C0_BFCTL_SMBS_Msk          (0x1000UL)     /*!< SMBS (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_BFCTL_FMPE_Pos          (14UL)         /*!< FMPE (Bit 14)                                         */
+ #define R_I3C0_BFCTL_FMPE_Msk          (0x4000UL)     /*!< FMPE (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_BFCTL_HSME_Pos          (15UL)         /*!< HSME (Bit 15)                                         */
+ #define R_I3C0_BFCTL_HSME_Msk          (0x8000UL)     /*!< HSME (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SVCTL  ========================================================= */
+ #define R_I3C0_SVCTL_GCAE_Pos          (0UL)          /*!< GCAE (Bit 0)                                          */
+ #define R_I3C0_SVCTL_GCAE_Msk          (0x1UL)        /*!< GCAE (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_SVCTL_HSMCE_Pos         (5UL)          /*!< HSMCE (Bit 5)                                         */
+ #define R_I3C0_SVCTL_HSMCE_Msk         (0x20UL)       /*!< HSMCE (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SVCTL_DVIDE_Pos         (6UL)          /*!< DVIDE (Bit 6)                                         */
+ #define R_I3C0_SVCTL_DVIDE_Msk         (0x40UL)       /*!< DVIDE (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SVCTL_HOAE_Pos          (15UL)         /*!< HOAE (Bit 15)                                         */
+ #define R_I3C0_SVCTL_HOAE_Msk          (0x8000UL)     /*!< HOAE (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_SVCTL_SVAEn_Pos         (16UL)         /*!< SVAEn (Bit 16)                                        */
+ #define R_I3C0_SVCTL_SVAEn_Msk         (0x10000UL)    /*!< SVAEn (Bitfield-Mask: 0x01)                           */
+/* =======================================================  REFCKCTL  ======================================================== */
+ #define R_I3C0_REFCKCTL_IREFCKS_Pos    (0UL)          /*!< IREFCKS (Bit 0)                                       */
+ #define R_I3C0_REFCKCTL_IREFCKS_Msk    (0x7UL)        /*!< IREFCKS (Bitfield-Mask: 0x07)                         */
+/* =========================================================  STDBR  ========================================================= */
+ #define R_I3C0_STDBR_SBRLO_Pos         (0UL)          /*!< SBRLO (Bit 0)                                         */
+ #define R_I3C0_STDBR_SBRLO_Msk         (0xffUL)       /*!< SBRLO (Bitfield-Mask: 0xff)                           */
+ #define R_I3C0_STDBR_SBRHO_Pos         (8UL)          /*!< SBRHO (Bit 8)                                         */
+ #define R_I3C0_STDBR_SBRHO_Msk         (0xff00UL)     /*!< SBRHO (Bitfield-Mask: 0xff)                           */
+ #define R_I3C0_STDBR_SBRLP_Pos         (16UL)         /*!< SBRLP (Bit 16)                                        */
+ #define R_I3C0_STDBR_SBRLP_Msk         (0x3f0000UL)   /*!< SBRLP (Bitfield-Mask: 0x3f)                           */
+ #define R_I3C0_STDBR_SBRHP_Pos         (24UL)         /*!< SBRHP (Bit 24)                                        */
+ #define R_I3C0_STDBR_SBRHP_Msk         (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f)                           */
+ #define R_I3C0_STDBR_DSBRPO_Pos        (31UL)         /*!< DSBRPO (Bit 31)                                       */
+ #define R_I3C0_STDBR_DSBRPO_Msk        (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01)                          */
+/* =========================================================  EXTBR  ========================================================= */
+ #define R_I3C0_EXTBR_EBRLO_Pos         (0UL)          /*!< EBRLO (Bit 0)                                         */
+ #define R_I3C0_EXTBR_EBRLO_Msk         (0xffUL)       /*!< EBRLO (Bitfield-Mask: 0xff)                           */
+ #define R_I3C0_EXTBR_EBRHO_Pos         (8UL)          /*!< EBRHO (Bit 8)                                         */
+ #define R_I3C0_EXTBR_EBRHO_Msk         (0xff00UL)     /*!< EBRHO (Bitfield-Mask: 0xff)                           */
+ #define R_I3C0_EXTBR_EBRLP_Pos         (16UL)         /*!< EBRLP (Bit 16)                                        */
+ #define R_I3C0_EXTBR_EBRLP_Msk         (0x3f0000UL)   /*!< EBRLP (Bitfield-Mask: 0x3f)                           */
+ #define R_I3C0_EXTBR_EBRHP_Pos         (24UL)         /*!< EBRHP (Bit 24)                                        */
+ #define R_I3C0_EXTBR_EBRHP_Msk         (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f)                           */
+/* ========================================================  BFRECDT  ======================================================== */
+ #define R_I3C0_BFRECDT_FRECYC_Pos      (0UL)          /*!< FRECYC (Bit 0)                                        */
+ #define R_I3C0_BFRECDT_FRECYC_Msk      (0x1ffUL)      /*!< FRECYC (Bitfield-Mask: 0x1ff)                         */
+/* ========================================================  BAVLCDT  ======================================================== */
+ #define R_I3C0_BAVLCDT_AVLCYC_Pos      (0UL)          /*!< AVLCYC (Bit 0)                                        */
+ #define R_I3C0_BAVLCDT_AVLCYC_Msk      (0x1ffUL)      /*!< AVLCYC (Bitfield-Mask: 0x1ff)                         */
+/* ========================================================  BIDLCDT  ======================================================== */
+ #define R_I3C0_BIDLCDT_IDLCYC_Pos      (0UL)          /*!< IDLCYC (Bit 0)                                        */
+ #define R_I3C0_BIDLCDT_IDLCYC_Msk      (0x3ffffUL)    /*!< IDLCYC (Bitfield-Mask: 0x3ffff)                       */
+/* ========================================================  OUTCTL  ========================================================= */
+ #define R_I3C0_OUTCTL_SDOC_Pos         (0UL)          /*!< SDOC (Bit 0)                                          */
+ #define R_I3C0_OUTCTL_SDOC_Msk         (0x1UL)        /*!< SDOC (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_OUTCTL_SCOC_Pos         (1UL)          /*!< SCOC (Bit 1)                                          */
+ #define R_I3C0_OUTCTL_SCOC_Msk         (0x2UL)        /*!< SCOC (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_OUTCTL_SOCWP_Pos        (2UL)          /*!< SOCWP (Bit 2)                                         */
+ #define R_I3C0_OUTCTL_SOCWP_Msk        (0x4UL)        /*!< SOCWP (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_OUTCTL_EXCYC_Pos        (4UL)          /*!< EXCYC (Bit 4)                                         */
+ #define R_I3C0_OUTCTL_EXCYC_Msk        (0x10UL)       /*!< EXCYC (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_OUTCTL_SDOD_Pos         (8UL)          /*!< SDOD (Bit 8)                                          */
+ #define R_I3C0_OUTCTL_SDOD_Msk         (0x700UL)      /*!< SDOD (Bitfield-Mask: 0x07)                            */
+ #define R_I3C0_OUTCTL_SDODCS_Pos       (15UL)         /*!< SDODCS (Bit 15)                                       */
+ #define R_I3C0_OUTCTL_SDODCS_Msk       (0x8000UL)     /*!< SDODCS (Bitfield-Mask: 0x01)                          */
+/* =========================================================  INCTL  ========================================================= */
+ #define R_I3C0_INCTL_DNFS_Pos          (0UL)          /*!< DNFS (Bit 0)                                          */
+ #define R_I3C0_INCTL_DNFS_Msk          (0xfUL)        /*!< DNFS (Bitfield-Mask: 0x0f)                            */
+ #define R_I3C0_INCTL_DNFE_Pos          (4UL)          /*!< DNFE (Bit 4)                                          */
+ #define R_I3C0_INCTL_DNFE_Msk          (0x10UL)       /*!< DNFE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  TMOCTL  ========================================================= */
+ #define R_I3C0_TMOCTL_TODTS_Pos        (0UL)          /*!< TODTS (Bit 0)                                         */
+ #define R_I3C0_TMOCTL_TODTS_Msk        (0x3UL)        /*!< TODTS (Bitfield-Mask: 0x03)                           */
+ #define R_I3C0_TMOCTL_TOLCTL_Pos       (4UL)          /*!< TOLCTL (Bit 4)                                        */
+ #define R_I3C0_TMOCTL_TOLCTL_Msk       (0x10UL)       /*!< TOLCTL (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_TMOCTL_TOHCTL_Pos       (5UL)          /*!< TOHCTL (Bit 5)                                        */
+ #define R_I3C0_TMOCTL_TOHCTL_Msk       (0x20UL)       /*!< TOHCTL (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_TMOCTL_TOMDS_Pos        (6UL)          /*!< TOMDS (Bit 6)                                         */
+ #define R_I3C0_TMOCTL_TOMDS_Msk        (0xc0UL)       /*!< TOMDS (Bitfield-Mask: 0x03)                           */
+/* =========================================================  WUCTL  ========================================================= */
+ #define R_I3C0_WUCTL_WUACKS_Pos        (0UL)          /*!< WUACKS (Bit 0)                                        */
+ #define R_I3C0_WUCTL_WUACKS_Msk        (0x1UL)        /*!< WUACKS (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_WUCTL_WUANFS_Pos        (4UL)          /*!< WUANFS (Bit 4)                                        */
+ #define R_I3C0_WUCTL_WUANFS_Msk        (0x10UL)       /*!< WUANFS (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_WUCTL_WUFSYNE_Pos       (6UL)          /*!< WUFSYNE (Bit 6)                                       */
+ #define R_I3C0_WUCTL_WUFSYNE_Msk       (0x40UL)       /*!< WUFSYNE (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_WUCTL_WUFE_Pos          (7UL)          /*!< WUFE (Bit 7)                                          */
+ #define R_I3C0_WUCTL_WUFE_Msk          (0x80UL)       /*!< WUFE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  ACKCTL  ========================================================= */
+ #define R_I3C0_ACKCTL_ACKR_Pos         (0UL)          /*!< ACKR (Bit 0)                                          */
+ #define R_I3C0_ACKCTL_ACKR_Msk         (0x1UL)        /*!< ACKR (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_ACKCTL_ACKT_Pos         (1UL)          /*!< ACKT (Bit 1)                                          */
+ #define R_I3C0_ACKCTL_ACKT_Msk         (0x2UL)        /*!< ACKT (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_ACKCTL_ACKTWP_Pos       (2UL)          /*!< ACKTWP (Bit 2)                                        */
+ #define R_I3C0_ACKCTL_ACKTWP_Msk       (0x4UL)        /*!< ACKTWP (Bitfield-Mask: 0x01)                          */
+/* =======================================================  SCSTRCTL  ======================================================== */
+ #define R_I3C0_SCSTRCTL_ACKTWE_Pos     (0UL)          /*!< ACKTWE (Bit 0)                                        */
+ #define R_I3C0_SCSTRCTL_ACKTWE_Msk     (0x1UL)        /*!< ACKTWE (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_SCSTRCTL_RWE_Pos        (1UL)          /*!< RWE (Bit 1)                                           */
+ #define R_I3C0_SCSTRCTL_RWE_Msk        (0x2UL)        /*!< RWE (Bitfield-Mask: 0x01)                             */
+/* =======================================================  SCSTLCTL  ======================================================== */
+ #define R_I3C0_SCSTLCTL_STLCYC_Pos     (0UL)          /*!< STLCYC (Bit 0)                                        */
+ #define R_I3C0_SCSTLCTL_STLCYC_Msk     (0xffffUL)     /*!< STLCYC (Bitfield-Mask: 0xffff)                        */
+ #define R_I3C0_SCSTLCTL_AAPE_Pos       (28UL)         /*!< AAPE (Bit 28)                                         */
+ #define R_I3C0_SCSTLCTL_AAPE_Msk       (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_SCSTLCTL_TRAPE_Pos      (29UL)         /*!< TRAPE (Bit 29)                                        */
+ #define R_I3C0_SCSTLCTL_TRAPE_Msk      (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SCSTLCTL_PARPE_Pos      (30UL)         /*!< PARPE (Bit 30)                                        */
+ #define R_I3C0_SCSTLCTL_PARPE_Msk      (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SCSTLCTL_ACKPE_Pos      (31UL)         /*!< ACKPE (Bit 31)                                        */
+ #define R_I3C0_SCSTLCTL_ACKPE_Msk      (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01)                           */
+/* ========================================================  SVTDLG0  ======================================================== */
+ #define R_I3C0_SVTDLG0_STDLG_Pos       (16UL)         /*!< STDLG (Bit 16)                                        */
+ #define R_I3C0_SVTDLG0_STDLG_Msk       (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  CNDCTL  ========================================================= */
+ #define R_I3C0_CNDCTL_STCND_Pos        (0UL)          /*!< STCND (Bit 0)                                         */
+ #define R_I3C0_CNDCTL_STCND_Msk        (0x1UL)        /*!< STCND (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_CNDCTL_SRCND_Pos        (1UL)          /*!< SRCND (Bit 1)                                         */
+ #define R_I3C0_CNDCTL_SRCND_Msk        (0x2UL)        /*!< SRCND (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_CNDCTL_SPCND_Pos        (2UL)          /*!< SPCND (Bit 2)                                         */
+ #define R_I3C0_CNDCTL_SPCND_Msk        (0x4UL)        /*!< SPCND (Bitfield-Mask: 0x01)                           */
+/* ========================================================  NCMDQP  ========================================================= */
+/* ========================================================  NRSPQP  ========================================================= */
+/* ========================================================  NTDTBP0  ======================================================== */
+/* ========================================================  NIBIQP  ========================================================= */
+/* =========================================================  NRSQP  ========================================================= */
+/* ========================================================  NQTHCTL  ======================================================== */
+ #define R_I3C0_NQTHCTL_CMDQTH_Pos      (0UL)          /*!< CMDQTH (Bit 0)                                        */
+ #define R_I3C0_NQTHCTL_CMDQTH_Msk      (0xffUL)       /*!< CMDQTH (Bitfield-Mask: 0xff)                          */
+ #define R_I3C0_NQTHCTL_RSPQTH_Pos      (8UL)          /*!< RSPQTH (Bit 8)                                        */
+ #define R_I3C0_NQTHCTL_RSPQTH_Msk      (0xff00UL)     /*!< RSPQTH (Bitfield-Mask: 0xff)                          */
+ #define R_I3C0_NQTHCTL_IBIDSSZ_Pos     (16UL)         /*!< IBIDSSZ (Bit 16)                                      */
+ #define R_I3C0_NQTHCTL_IBIDSSZ_Msk     (0xff0000UL)   /*!< IBIDSSZ (Bitfield-Mask: 0xff)                         */
+ #define R_I3C0_NQTHCTL_IBIQTH_Pos      (24UL)         /*!< IBIQTH (Bit 24)                                       */
+ #define R_I3C0_NQTHCTL_IBIQTH_Msk      (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff)                          */
+/* =======================================================  NTBTHCTL0  ======================================================= */
+ #define R_I3C0_NTBTHCTL0_TXDBTH_Pos    (0UL)          /*!< TXDBTH (Bit 0)                                        */
+ #define R_I3C0_NTBTHCTL0_TXDBTH_Msk    (0x7UL)        /*!< TXDBTH (Bitfield-Mask: 0x07)                          */
+ #define R_I3C0_NTBTHCTL0_RXDBTH_Pos    (8UL)          /*!< RXDBTH (Bit 8)                                        */
+ #define R_I3C0_NTBTHCTL0_RXDBTH_Msk    (0x700UL)      /*!< RXDBTH (Bitfield-Mask: 0x07)                          */
+ #define R_I3C0_NTBTHCTL0_TXSTTH_Pos    (16UL)         /*!< TXSTTH (Bit 16)                                       */
+ #define R_I3C0_NTBTHCTL0_TXSTTH_Msk    (0x70000UL)    /*!< TXSTTH (Bitfield-Mask: 0x07)                          */
+ #define R_I3C0_NTBTHCTL0_RXSTTH_Pos    (24UL)         /*!< RXSTTH (Bit 24)                                       */
+ #define R_I3C0_NTBTHCTL0_RXSTTH_Msk    (0x7000000UL)  /*!< RXSTTH (Bitfield-Mask: 0x07)                          */
+/* =======================================================  NRQTHCTL  ======================================================== */
+ #define R_I3C0_NRQTHCTL_RSQTH_Pos      (0UL)          /*!< RSQTH (Bit 0)                                         */
+ #define R_I3C0_NRQTHCTL_RSQTH_Msk      (0xffUL)       /*!< RSQTH (Bitfield-Mask: 0xff)                           */
+/* ==========================================================  BST  ========================================================== */
+ #define R_I3C0_BST_STCNDDF_Pos         (0UL)          /*!< STCNDDF (Bit 0)                                       */
+ #define R_I3C0_BST_STCNDDF_Msk         (0x1UL)        /*!< STCNDDF (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_BST_SPCNDDF_Pos         (1UL)          /*!< SPCNDDF (Bit 1)                                       */
+ #define R_I3C0_BST_SPCNDDF_Msk         (0x2UL)        /*!< SPCNDDF (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_BST_HDREXDF_Pos         (2UL)          /*!< HDREXDF (Bit 2)                                       */
+ #define R_I3C0_BST_HDREXDF_Msk         (0x4UL)        /*!< HDREXDF (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_BST_NACKDF_Pos          (4UL)          /*!< NACKDF (Bit 4)                                        */
+ #define R_I3C0_BST_NACKDF_Msk          (0x10UL)       /*!< NACKDF (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_BST_TENDF_Pos           (8UL)          /*!< TENDF (Bit 8)                                         */
+ #define R_I3C0_BST_TENDF_Msk           (0x100UL)      /*!< TENDF (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_BST_ALF_Pos             (16UL)         /*!< ALF (Bit 16)                                          */
+ #define R_I3C0_BST_ALF_Msk             (0x10000UL)    /*!< ALF (Bitfield-Mask: 0x01)                             */
+ #define R_I3C0_BST_TODF_Pos            (20UL)         /*!< TODF (Bit 20)                                         */
+ #define R_I3C0_BST_TODF_Msk            (0x100000UL)   /*!< TODF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  BSTE  ========================================================== */
+ #define R_I3C0_BSTE_STCNDDE_Pos        (0UL)          /*!< STCNDDE (Bit 0)                                       */
+ #define R_I3C0_BSTE_STCNDDE_Msk        (0x1UL)        /*!< STCNDDE (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_BSTE_SPCNDDE_Pos        (1UL)          /*!< SPCNDDE (Bit 1)                                       */
+ #define R_I3C0_BSTE_SPCNDDE_Msk        (0x2UL)        /*!< SPCNDDE (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_BSTE_HDREXDE_Pos        (2UL)          /*!< HDREXDE (Bit 2)                                       */
+ #define R_I3C0_BSTE_HDREXDE_Msk        (0x4UL)        /*!< HDREXDE (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_BSTE_NACKDE_Pos         (4UL)          /*!< NACKDE (Bit 4)                                        */
+ #define R_I3C0_BSTE_NACKDE_Msk         (0x10UL)       /*!< NACKDE (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_BSTE_TENDE_Pos          (8UL)          /*!< TENDE (Bit 8)                                         */
+ #define R_I3C0_BSTE_TENDE_Msk          (0x100UL)      /*!< TENDE (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_BSTE_ALE_Pos            (16UL)         /*!< ALE (Bit 16)                                          */
+ #define R_I3C0_BSTE_ALE_Msk            (0x10000UL)    /*!< ALE (Bitfield-Mask: 0x01)                             */
+ #define R_I3C0_BSTE_TODE_Pos           (20UL)         /*!< TODE (Bit 20)                                         */
+ #define R_I3C0_BSTE_TODE_Msk           (0x100000UL)   /*!< TODE (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  BIE  ========================================================== */
+ #define R_I3C0_BIE_STCNDDIE_Pos        (0UL)          /*!< STCNDDIE (Bit 0)                                      */
+ #define R_I3C0_BIE_STCNDDIE_Msk        (0x1UL)        /*!< STCNDDIE (Bitfield-Mask: 0x01)                        */
+ #define R_I3C0_BIE_SPCNDDIE_Pos        (1UL)          /*!< SPCNDDIE (Bit 1)                                      */
+ #define R_I3C0_BIE_SPCNDDIE_Msk        (0x2UL)        /*!< SPCNDDIE (Bitfield-Mask: 0x01)                        */
+ #define R_I3C0_BIE_HDREXDIE_Pos        (2UL)          /*!< HDREXDIE (Bit 2)                                      */
+ #define R_I3C0_BIE_HDREXDIE_Msk        (0x4UL)        /*!< HDREXDIE (Bitfield-Mask: 0x01)                        */
+ #define R_I3C0_BIE_NACKDIE_Pos         (4UL)          /*!< NACKDIE (Bit 4)                                       */
+ #define R_I3C0_BIE_NACKDIE_Msk         (0x10UL)       /*!< NACKDIE (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_BIE_TENDIE_Pos          (8UL)          /*!< TENDIE (Bit 8)                                        */
+ #define R_I3C0_BIE_TENDIE_Msk          (0x100UL)      /*!< TENDIE (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_BIE_ALIE_Pos            (16UL)         /*!< ALIE (Bit 16)                                         */
+ #define R_I3C0_BIE_ALIE_Msk            (0x10000UL)    /*!< ALIE (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_BIE_TODIE_Pos           (20UL)         /*!< TODIE (Bit 20)                                        */
+ #define R_I3C0_BIE_TODIE_Msk           (0x100000UL)   /*!< TODIE (Bitfield-Mask: 0x01)                           */
+/* =========================================================  BSTFC  ========================================================= */
+ #define R_I3C0_BSTFC_STCNDDFC_Pos      (0UL)          /*!< STCNDDFC (Bit 0)                                      */
+ #define R_I3C0_BSTFC_STCNDDFC_Msk      (0x1UL)        /*!< STCNDDFC (Bitfield-Mask: 0x01)                        */
+ #define R_I3C0_BSTFC_SPCNDDFC_Pos      (1UL)          /*!< SPCNDDFC (Bit 1)                                      */
+ #define R_I3C0_BSTFC_SPCNDDFC_Msk      (0x2UL)        /*!< SPCNDDFC (Bitfield-Mask: 0x01)                        */
+ #define R_I3C0_BSTFC_HDREXDFC_Pos      (2UL)          /*!< HDREXDFC (Bit 2)                                      */
+ #define R_I3C0_BSTFC_HDREXDFC_Msk      (0x4UL)        /*!< HDREXDFC (Bitfield-Mask: 0x01)                        */
+ #define R_I3C0_BSTFC_NACKDFC_Pos       (4UL)          /*!< NACKDFC (Bit 4)                                       */
+ #define R_I3C0_BSTFC_NACKDFC_Msk       (0x10UL)       /*!< NACKDFC (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_BSTFC_TENDFC_Pos        (8UL)          /*!< TENDFC (Bit 8)                                        */
+ #define R_I3C0_BSTFC_TENDFC_Msk        (0x100UL)      /*!< TENDFC (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_BSTFC_ALFC_Pos          (16UL)         /*!< ALFC (Bit 16)                                         */
+ #define R_I3C0_BSTFC_ALFC_Msk          (0x10000UL)    /*!< ALFC (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_BSTFC_TODFC_Pos         (20UL)         /*!< TODFC (Bit 20)                                        */
+ #define R_I3C0_BSTFC_TODFC_Msk         (0x100000UL)   /*!< TODFC (Bitfield-Mask: 0x01)                           */
+/* =========================================================  NTST  ========================================================== */
+ #define R_I3C0_NTST_TDBEF0_Pos         (0UL)          /*!< TDBEF0 (Bit 0)                                        */
+ #define R_I3C0_NTST_TDBEF0_Msk         (0x1UL)        /*!< TDBEF0 (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_NTST_RDBFF0_Pos         (1UL)          /*!< RDBFF0 (Bit 1)                                        */
+ #define R_I3C0_NTST_RDBFF0_Msk         (0x2UL)        /*!< RDBFF0 (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_NTST_IBIQEFF_Pos        (2UL)          /*!< IBIQEFF (Bit 2)                                       */
+ #define R_I3C0_NTST_IBIQEFF_Msk        (0x4UL)        /*!< IBIQEFF (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_NTST_CMDQEF_Pos         (3UL)          /*!< CMDQEF (Bit 3)                                        */
+ #define R_I3C0_NTST_CMDQEF_Msk         (0x8UL)        /*!< CMDQEF (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_NTST_RSPQFF_Pos         (4UL)          /*!< RSPQFF (Bit 4)                                        */
+ #define R_I3C0_NTST_RSPQFF_Msk         (0x10UL)       /*!< RSPQFF (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_NTST_TABTF_Pos          (5UL)          /*!< TABTF (Bit 5)                                         */
+ #define R_I3C0_NTST_TABTF_Msk          (0x20UL)       /*!< TABTF (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_NTST_TEF_Pos            (9UL)          /*!< TEF (Bit 9)                                           */
+ #define R_I3C0_NTST_TEF_Msk            (0x200UL)      /*!< TEF (Bitfield-Mask: 0x01)                             */
+ #define R_I3C0_NTST_RSQFF_Pos          (20UL)         /*!< RSQFF (Bit 20)                                        */
+ #define R_I3C0_NTST_RSQFF_Msk          (0x100000UL)   /*!< RSQFF (Bitfield-Mask: 0x01)                           */
+/* =========================================================  NTSTE  ========================================================= */
+ #define R_I3C0_NTSTE_TDBEE0_Pos        (0UL)          /*!< TDBEE0 (Bit 0)                                        */
+ #define R_I3C0_NTSTE_TDBEE0_Msk        (0x1UL)        /*!< TDBEE0 (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_NTSTE_RDBFE0_Pos        (1UL)          /*!< RDBFE0 (Bit 1)                                        */
+ #define R_I3C0_NTSTE_RDBFE0_Msk        (0x2UL)        /*!< RDBFE0 (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_NTSTE_IBIQEFE_Pos       (2UL)          /*!< IBIQEFE (Bit 2)                                       */
+ #define R_I3C0_NTSTE_IBIQEFE_Msk       (0x4UL)        /*!< IBIQEFE (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_NTSTE_CMDQEE_Pos        (3UL)          /*!< CMDQEE (Bit 3)                                        */
+ #define R_I3C0_NTSTE_CMDQEE_Msk        (0x8UL)        /*!< CMDQEE (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_NTSTE_RSPQFE_Pos        (4UL)          /*!< RSPQFE (Bit 4)                                        */
+ #define R_I3C0_NTSTE_RSPQFE_Msk        (0x10UL)       /*!< RSPQFE (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_NTSTE_TABTE_Pos         (5UL)          /*!< TABTE (Bit 5)                                         */
+ #define R_I3C0_NTSTE_TABTE_Msk         (0x20UL)       /*!< TABTE (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_NTSTE_TEE_Pos           (9UL)          /*!< TEE (Bit 9)                                           */
+ #define R_I3C0_NTSTE_TEE_Msk           (0x200UL)      /*!< TEE (Bitfield-Mask: 0x01)                             */
+ #define R_I3C0_NTSTE_RSQFE_Pos         (20UL)         /*!< RSQFE (Bit 20)                                        */
+ #define R_I3C0_NTSTE_RSQFE_Msk         (0x100000UL)   /*!< RSQFE (Bitfield-Mask: 0x01)                           */
+/* =========================================================  NTIE  ========================================================== */
+ #define R_I3C0_NTIE_TDBEIE0_Pos        (0UL)          /*!< TDBEIE0 (Bit 0)                                       */
+ #define R_I3C0_NTIE_TDBEIE0_Msk        (0x1UL)        /*!< TDBEIE0 (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_NTIE_RDBFIE0_Pos        (1UL)          /*!< RDBFIE0 (Bit 1)                                       */
+ #define R_I3C0_NTIE_RDBFIE0_Msk        (0x2UL)        /*!< RDBFIE0 (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_NTIE_IBIQEFIE_Pos       (2UL)          /*!< IBIQEFIE (Bit 2)                                      */
+ #define R_I3C0_NTIE_IBIQEFIE_Msk       (0x4UL)        /*!< IBIQEFIE (Bitfield-Mask: 0x01)                        */
+ #define R_I3C0_NTIE_CMDQEIE_Pos        (3UL)          /*!< CMDQEIE (Bit 3)                                       */
+ #define R_I3C0_NTIE_CMDQEIE_Msk        (0x8UL)        /*!< CMDQEIE (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_NTIE_RSPQFIE_Pos        (4UL)          /*!< RSPQFIE (Bit 4)                                       */
+ #define R_I3C0_NTIE_RSPQFIE_Msk        (0x10UL)       /*!< RSPQFIE (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_NTIE_TABTIE_Pos         (5UL)          /*!< TABTIE (Bit 5)                                        */
+ #define R_I3C0_NTIE_TABTIE_Msk         (0x20UL)       /*!< TABTIE (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_NTIE_TEIE_Pos           (9UL)          /*!< TEIE (Bit 9)                                          */
+ #define R_I3C0_NTIE_TEIE_Msk           (0x200UL)      /*!< TEIE (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_NTIE_RSQFIE_Pos         (20UL)         /*!< RSQFIE (Bit 20)                                       */
+ #define R_I3C0_NTIE_RSQFIE_Msk         (0x100000UL)   /*!< RSQFIE (Bitfield-Mask: 0x01)                          */
+/* ========================================================  NTSTFC  ========================================================= */
+ #define R_I3C0_NTSTFC_TDBEFC0_Pos      (0UL)          /*!< TDBEFC0 (Bit 0)                                       */
+ #define R_I3C0_NTSTFC_TDBEFC0_Msk      (0x1UL)        /*!< TDBEFC0 (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_NTSTFC_RDBFFC0_Pos      (1UL)          /*!< RDBFFC0 (Bit 1)                                       */
+ #define R_I3C0_NTSTFC_RDBFFC0_Msk      (0x2UL)        /*!< RDBFFC0 (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_NTSTFC_IBIQEFFC_Pos     (2UL)          /*!< IBIQEFFC (Bit 2)                                      */
+ #define R_I3C0_NTSTFC_IBIQEFFC_Msk     (0x4UL)        /*!< IBIQEFFC (Bitfield-Mask: 0x01)                        */
+ #define R_I3C0_NTSTFC_CMDQEFC_Pos      (3UL)          /*!< CMDQEFC (Bit 3)                                       */
+ #define R_I3C0_NTSTFC_CMDQEFC_Msk      (0x8UL)        /*!< CMDQEFC (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_NTSTFC_RSPQFFC_Pos      (4UL)          /*!< RSPQFFC (Bit 4)                                       */
+ #define R_I3C0_NTSTFC_RSPQFFC_Msk      (0x10UL)       /*!< RSPQFFC (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_NTSTFC_TABTFC_Pos       (5UL)          /*!< TABTFC (Bit 5)                                        */
+ #define R_I3C0_NTSTFC_TABTFC_Msk       (0x20UL)       /*!< TABTFC (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_NTSTFC_TEFC_Pos         (9UL)          /*!< TEFC (Bit 9)                                          */
+ #define R_I3C0_NTSTFC_TEFC_Msk         (0x200UL)      /*!< TEFC (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_NTSTFC_RSQFFC_Pos       (20UL)         /*!< RSQFFC (Bit 20)                                       */
+ #define R_I3C0_NTSTFC_RSQFFC_Msk       (0x100000UL)   /*!< RSQFFC (Bitfield-Mask: 0x01)                          */
+/* =========================================================  BCST  ========================================================== */
+ #define R_I3C0_BCST_BFREF_Pos          (0UL)          /*!< BFREF (Bit 0)                                         */
+ #define R_I3C0_BCST_BFREF_Msk          (0x1UL)        /*!< BFREF (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_BCST_BAVLF_Pos          (1UL)          /*!< BAVLF (Bit 1)                                         */
+ #define R_I3C0_BCST_BAVLF_Msk          (0x2UL)        /*!< BAVLF (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_BCST_BIDLF_Pos          (2UL)          /*!< BIDLF (Bit 2)                                         */
+ #define R_I3C0_BCST_BIDLF_Msk          (0x4UL)        /*!< BIDLF (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SVST  ========================================================== */
+ #define R_I3C0_SVST_GCAF_Pos           (0UL)          /*!< GCAF (Bit 0)                                          */
+ #define R_I3C0_SVST_GCAF_Msk           (0x1UL)        /*!< GCAF (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_SVST_HSMCF_Pos          (5UL)          /*!< HSMCF (Bit 5)                                         */
+ #define R_I3C0_SVST_HSMCF_Msk          (0x20UL)       /*!< HSMCF (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SVST_DVIDF_Pos          (6UL)          /*!< DVIDF (Bit 6)                                         */
+ #define R_I3C0_SVST_DVIDF_Msk          (0x40UL)       /*!< DVIDF (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SVST_HOAF_Pos           (15UL)         /*!< HOAF (Bit 15)                                         */
+ #define R_I3C0_SVST_HOAF_Msk           (0x8000UL)     /*!< HOAF (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_SVST_SVAFn_Pos          (16UL)         /*!< SVAFn (Bit 16)                                        */
+ #define R_I3C0_SVST_SVAFn_Msk          (0x10000UL)    /*!< SVAFn (Bitfield-Mask: 0x01)                           */
+/* =========================================================  WUST  ========================================================== */
+ #define R_I3C0_WUST_WUASYNF_Pos        (0UL)          /*!< WUASYNF (Bit 0)                                       */
+ #define R_I3C0_WUST_WUASYNF_Msk        (0x1UL)        /*!< WUASYNF (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DATBAS0  ======================================================== */
+ #define R_I3C0_DATBAS0_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
+ #define R_I3C0_DATBAS0_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
+ #define R_I3C0_DATBAS0_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
+ #define R_I3C0_DATBAS0_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS0_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
+ #define R_I3C0_DATBAS0_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS0_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
+ #define R_I3C0_DATBAS0_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_DATBAS0_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
+ #define R_I3C0_DATBAS0_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS0_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
+ #define R_I3C0_DATBAS0_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
+ #define R_I3C0_DATBAS0_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
+ #define R_I3C0_DATBAS0_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
+ #define R_I3C0_DATBAS0_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
+ #define R_I3C0_DATBAS0_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DATBAS1  ======================================================== */
+ #define R_I3C0_DATBAS1_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
+ #define R_I3C0_DATBAS1_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
+ #define R_I3C0_DATBAS1_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
+ #define R_I3C0_DATBAS1_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS1_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
+ #define R_I3C0_DATBAS1_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS1_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
+ #define R_I3C0_DATBAS1_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_DATBAS1_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
+ #define R_I3C0_DATBAS1_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS1_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
+ #define R_I3C0_DATBAS1_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
+ #define R_I3C0_DATBAS1_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
+ #define R_I3C0_DATBAS1_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
+ #define R_I3C0_DATBAS1_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
+ #define R_I3C0_DATBAS1_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DATBAS2  ======================================================== */
+ #define R_I3C0_DATBAS2_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
+ #define R_I3C0_DATBAS2_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
+ #define R_I3C0_DATBAS2_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
+ #define R_I3C0_DATBAS2_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS2_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
+ #define R_I3C0_DATBAS2_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS2_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
+ #define R_I3C0_DATBAS2_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_DATBAS2_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
+ #define R_I3C0_DATBAS2_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS2_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
+ #define R_I3C0_DATBAS2_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
+ #define R_I3C0_DATBAS2_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
+ #define R_I3C0_DATBAS2_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
+ #define R_I3C0_DATBAS2_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
+ #define R_I3C0_DATBAS2_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DATBAS3  ======================================================== */
+ #define R_I3C0_DATBAS3_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
+ #define R_I3C0_DATBAS3_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
+ #define R_I3C0_DATBAS3_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
+ #define R_I3C0_DATBAS3_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS3_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
+ #define R_I3C0_DATBAS3_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS3_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
+ #define R_I3C0_DATBAS3_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_DATBAS3_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
+ #define R_I3C0_DATBAS3_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_DATBAS3_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
+ #define R_I3C0_DATBAS3_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
+ #define R_I3C0_DATBAS3_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
+ #define R_I3C0_DATBAS3_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
+ #define R_I3C0_DATBAS3_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
+ #define R_I3C0_DATBAS3_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
+/* =======================================================  EXDATBAS  ======================================================== */
+ #define R_I3C0_EXDATBAS_EDSTAD_Pos     (0UL)          /*!< EDSTAD (Bit 0)                                        */
+ #define R_I3C0_EXDATBAS_EDSTAD_Msk     (0x7fUL)       /*!< EDSTAD (Bitfield-Mask: 0x7f)                          */
+ #define R_I3C0_EXDATBAS_EDDYAD_Pos     (16UL)         /*!< EDDYAD (Bit 16)                                       */
+ #define R_I3C0_EXDATBAS_EDDYAD_Msk     (0xff0000UL)   /*!< EDDYAD (Bitfield-Mask: 0xff)                          */
+ #define R_I3C0_EXDATBAS_EDNACK_Pos     (29UL)         /*!< EDNACK (Bit 29)                                       */
+ #define R_I3C0_EXDATBAS_EDNACK_Msk     (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03)                          */
+ #define R_I3C0_EXDATBAS_EDTYP_Pos      (31UL)         /*!< EDTYP (Bit 31)                                        */
+ #define R_I3C0_EXDATBAS_EDTYP_Msk      (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01)                           */
+/* =======================================================  SDATBAS0  ======================================================== */
+ #define R_I3C0_SDATBAS0_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
+ #define R_I3C0_SDATBAS0_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
+ #define R_I3C0_SDATBAS0_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
+ #define R_I3C0_SDATBAS0_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_SDATBAS0_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
+ #define R_I3C0_SDATBAS0_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_SDATBAS0_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
+ #define R_I3C0_SDATBAS0_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
+/* =======================================================  SDATBAS1  ======================================================== */
+ #define R_I3C0_SDATBAS1_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
+ #define R_I3C0_SDATBAS1_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
+ #define R_I3C0_SDATBAS1_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
+ #define R_I3C0_SDATBAS1_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_SDATBAS1_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
+ #define R_I3C0_SDATBAS1_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_SDATBAS1_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
+ #define R_I3C0_SDATBAS1_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
+/* =======================================================  SDATBAS2  ======================================================== */
+ #define R_I3C0_SDATBAS2_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
+ #define R_I3C0_SDATBAS2_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
+ #define R_I3C0_SDATBAS2_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
+ #define R_I3C0_SDATBAS2_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_SDATBAS2_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
+ #define R_I3C0_SDATBAS2_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
+ #define R_I3C0_SDATBAS2_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
+ #define R_I3C0_SDATBAS2_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
+/* ========================================================  MSDCT0  ========================================================= */
+ #define R_I3C0_MSDCT0_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
+ #define R_I3C0_MSDCT0_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT0_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
+ #define R_I3C0_MSDCT0_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT0_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
+ #define R_I3C0_MSDCT0_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT0_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
+ #define R_I3C0_MSDCT0_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT0_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
+ #define R_I3C0_MSDCT0_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
+/* ========================================================  MSDCT1  ========================================================= */
+ #define R_I3C0_MSDCT1_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
+ #define R_I3C0_MSDCT1_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT1_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
+ #define R_I3C0_MSDCT1_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT1_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
+ #define R_I3C0_MSDCT1_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT1_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
+ #define R_I3C0_MSDCT1_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT1_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
+ #define R_I3C0_MSDCT1_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
+/* ========================================================  MSDCT2  ========================================================= */
+ #define R_I3C0_MSDCT2_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
+ #define R_I3C0_MSDCT2_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT2_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
+ #define R_I3C0_MSDCT2_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT2_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
+ #define R_I3C0_MSDCT2_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT2_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
+ #define R_I3C0_MSDCT2_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT2_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
+ #define R_I3C0_MSDCT2_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
+/* ========================================================  MSDCT3  ========================================================= */
+ #define R_I3C0_MSDCT3_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
+ #define R_I3C0_MSDCT3_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT3_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
+ #define R_I3C0_MSDCT3_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT3_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
+ #define R_I3C0_MSDCT3_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT3_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
+ #define R_I3C0_MSDCT3_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_MSDCT3_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
+ #define R_I3C0_MSDCT3_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
+/* =========================================================  SVDCT  ========================================================= */
+ #define R_I3C0_SVDCT_TDCR_Pos          (0UL)          /*!< TDCR (Bit 0)                                          */
+ #define R_I3C0_SVDCT_TDCR_Msk          (0xffUL)       /*!< TDCR (Bitfield-Mask: 0xff)                            */
+ #define R_I3C0_SVDCT_TBCR0_Pos         (8UL)          /*!< TBCR0 (Bit 8)                                         */
+ #define R_I3C0_SVDCT_TBCR0_Msk         (0x100UL)      /*!< TBCR0 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SVDCT_TBCR1_Pos         (9UL)          /*!< TBCR1 (Bit 9)                                         */
+ #define R_I3C0_SVDCT_TBCR1_Msk         (0x200UL)      /*!< TBCR1 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SVDCT_TBCR2_Pos         (10UL)         /*!< TBCR2 (Bit 10)                                        */
+ #define R_I3C0_SVDCT_TBCR2_Msk         (0x400UL)      /*!< TBCR2 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SVDCT_TBCR3_Pos         (11UL)         /*!< TBCR3 (Bit 11)                                        */
+ #define R_I3C0_SVDCT_TBCR3_Msk         (0x800UL)      /*!< TBCR3 (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SVDCT_TBCR76_Pos        (14UL)         /*!< TBCR76 (Bit 14)                                       */
+ #define R_I3C0_SVDCT_TBCR76_Msk        (0xc000UL)     /*!< TBCR76 (Bitfield-Mask: 0x03)                          */
+/* =======================================================  SDCTPIDL  ======================================================== */
+/* =======================================================  SDCTPIDH  ======================================================== */
+/* ========================================================  SVDVAD0  ======================================================== */
+ #define R_I3C0_SVDVAD0_SVAD_Pos        (16UL)         /*!< SVAD (Bit 16)                                         */
+ #define R_I3C0_SVDVAD0_SVAD_Msk        (0x3ff0000UL)  /*!< SVAD (Bitfield-Mask: 0x3ff)                           */
+ #define R_I3C0_SVDVAD0_SADLG_Pos       (27UL)         /*!< SADLG (Bit 27)                                        */
+ #define R_I3C0_SVDVAD0_SADLG_Msk       (0x8000000UL)  /*!< SADLG (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_SVDVAD0_SSTADV_Pos      (30UL)         /*!< SSTADV (Bit 30)                                       */
+ #define R_I3C0_SVDVAD0_SSTADV_Msk      (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_SVDVAD0_SDYADV_Pos      (31UL)         /*!< SDYADV (Bit 31)                                       */
+ #define R_I3C0_SVDVAD0_SDYADV_Msk      (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01)                          */
+/* ========================================================  CSECMD  ========================================================= */
+ #define R_I3C0_CSECMD_SVIRQE_Pos       (0UL)          /*!< SVIRQE (Bit 0)                                        */
+ #define R_I3C0_CSECMD_SVIRQE_Msk       (0x1UL)        /*!< SVIRQE (Bitfield-Mask: 0x01)                          */
+ #define R_I3C0_CSECMD_MSRQE_Pos        (1UL)          /*!< MSRQE (Bit 1)                                         */
+ #define R_I3C0_CSECMD_MSRQE_Msk        (0x2UL)        /*!< MSRQE (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_CSECMD_HJEVE_Pos        (3UL)          /*!< HJEVE (Bit 3)                                         */
+ #define R_I3C0_CSECMD_HJEVE_Msk        (0x8UL)        /*!< HJEVE (Bitfield-Mask: 0x01)                           */
+/* ========================================================  CEACTST  ======================================================== */
+ #define R_I3C0_CEACTST_ACTST_Pos       (0UL)          /*!< ACTST (Bit 0)                                         */
+ #define R_I3C0_CEACTST_ACTST_Msk       (0xfUL)        /*!< ACTST (Bitfield-Mask: 0x0f)                           */
+/* =========================================================  CMWLG  ========================================================= */
+ #define R_I3C0_CMWLG_MWLG_Pos          (0UL)          /*!< MWLG (Bit 0)                                          */
+ #define R_I3C0_CMWLG_MWLG_Msk          (0xffffUL)     /*!< MWLG (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  CMRLG  ========================================================= */
+ #define R_I3C0_CMRLG_MRLG_Pos          (0UL)          /*!< MRLG (Bit 0)                                          */
+ #define R_I3C0_CMRLG_MRLG_Msk          (0xffffUL)     /*!< MRLG (Bitfield-Mask: 0xffff)                          */
+ #define R_I3C0_CMRLG_IBIPSZ_Pos        (16UL)         /*!< IBIPSZ (Bit 16)                                       */
+ #define R_I3C0_CMRLG_IBIPSZ_Msk        (0xff0000UL)   /*!< IBIPSZ (Bitfield-Mask: 0xff)                          */
+/* ========================================================  CETSTMD  ======================================================== */
+ #define R_I3C0_CETSTMD_TSTMD_Pos       (0UL)          /*!< TSTMD (Bit 0)                                         */
+ #define R_I3C0_CETSTMD_TSTMD_Msk       (0xffUL)       /*!< TSTMD (Bitfield-Mask: 0xff)                           */
+/* ========================================================  CGDVST  ========================================================= */
+ #define R_I3C0_CGDVST_PNDINT_Pos       (0UL)          /*!< PNDINT (Bit 0)                                        */
+ #define R_I3C0_CGDVST_PNDINT_Msk       (0xfUL)        /*!< PNDINT (Bitfield-Mask: 0x0f)                          */
+ #define R_I3C0_CGDVST_PRTE_Pos         (5UL)          /*!< PRTE (Bit 5)                                          */
+ #define R_I3C0_CGDVST_PRTE_Msk         (0x20UL)       /*!< PRTE (Bitfield-Mask: 0x01)                            */
+ #define R_I3C0_CGDVST_ACTMD_Pos        (6UL)          /*!< ACTMD (Bit 6)                                         */
+ #define R_I3C0_CGDVST_ACTMD_Msk        (0xc0UL)       /*!< ACTMD (Bitfield-Mask: 0x03)                           */
+ #define R_I3C0_CGDVST_VDRSV_Pos        (8UL)          /*!< VDRSV (Bit 8)                                         */
+ #define R_I3C0_CGDVST_VDRSV_Msk        (0xff00UL)     /*!< VDRSV (Bitfield-Mask: 0xff)                           */
+/* ========================================================  CMDSPW  ========================================================= */
+ #define R_I3C0_CMDSPW_MSWDR_Pos        (0UL)          /*!< MSWDR (Bit 0)                                         */
+ #define R_I3C0_CMDSPW_MSWDR_Msk        (0x7UL)        /*!< MSWDR (Bitfield-Mask: 0x07)                           */
+/* ========================================================  CMDSPR  ========================================================= */
+ #define R_I3C0_CMDSPR_MSRDR_Pos        (0UL)          /*!< MSRDR (Bit 0)                                         */
+ #define R_I3C0_CMDSPR_MSRDR_Msk        (0x7UL)        /*!< MSRDR (Bitfield-Mask: 0x07)                           */
+ #define R_I3C0_CMDSPR_CDTTIM_Pos       (3UL)          /*!< CDTTIM (Bit 3)                                        */
+ #define R_I3C0_CMDSPR_CDTTIM_Msk       (0x38UL)       /*!< CDTTIM (Bitfield-Mask: 0x07)                          */
+/* ========================================================  CMDSPT  ========================================================= */
+ #define R_I3C0_CMDSPT_MRTTIM_Pos       (0UL)          /*!< MRTTIM (Bit 0)                                        */
+ #define R_I3C0_CMDSPT_MRTTIM_Msk       (0xffffffUL)   /*!< MRTTIM (Bitfield-Mask: 0xffffff)                      */
+ #define R_I3C0_CMDSPT_MRTE_Pos         (31UL)         /*!< MRTE (Bit 31)                                         */
+ #define R_I3C0_CMDSPT_MRTE_Msk         (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  CETSM  ========================================================= */
+ #define R_I3C0_CETSM_FREQ_Pos          (8UL)          /*!< FREQ (Bit 8)                                          */
+ #define R_I3C0_CETSM_FREQ_Msk          (0xff00UL)     /*!< FREQ (Bitfield-Mask: 0xff)                            */
+ #define R_I3C0_CETSM_INAC_Pos          (16UL)         /*!< INAC (Bit 16)                                         */
+ #define R_I3C0_CETSM_INAC_Msk          (0xff0000UL)   /*!< INAC (Bitfield-Mask: 0xff)                            */
+/* ========================================================  BITCNT  ========================================================= */
+ #define R_I3C0_BITCNT_BCNT_Pos         (0UL)          /*!< BCNT (Bit 0)                                          */
+ #define R_I3C0_BITCNT_BCNT_Msk         (0x1fUL)       /*!< BCNT (Bitfield-Mask: 0x1f)                            */
+ #define R_I3C0_BITCNT_BCNTWP_Pos       (7UL)          /*!< BCNTWP (Bit 7)                                        */
+ #define R_I3C0_BITCNT_BCNTWP_Msk       (0x80UL)       /*!< BCNTWP (Bitfield-Mask: 0x01)                          */
+/* ========================================================  NQSTLV  ========================================================= */
+ #define R_I3C0_NQSTLV_CMDQFLV_Pos      (0UL)          /*!< CMDQFLV (Bit 0)                                       */
+ #define R_I3C0_NQSTLV_CMDQFLV_Msk      (0xffUL)       /*!< CMDQFLV (Bitfield-Mask: 0xff)                         */
+ #define R_I3C0_NQSTLV_RSPQLV_Pos       (8UL)          /*!< RSPQLV (Bit 8)                                        */
+ #define R_I3C0_NQSTLV_RSPQLV_Msk       (0xff00UL)     /*!< RSPQLV (Bitfield-Mask: 0xff)                          */
+ #define R_I3C0_NQSTLV_IBIQLV_Pos       (16UL)         /*!< IBIQLV (Bit 16)                                       */
+ #define R_I3C0_NQSTLV_IBIQLV_Msk       (0xff0000UL)   /*!< IBIQLV (Bitfield-Mask: 0xff)                          */
+ #define R_I3C0_NQSTLV_IBISCNT_Pos      (24UL)         /*!< IBISCNT (Bit 24)                                      */
+ #define R_I3C0_NQSTLV_IBISCNT_Msk      (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f)                         */
+/* =======================================================  NDBSTLV0  ======================================================== */
+ #define R_I3C0_NDBSTLV0_TDBFLV_Pos     (0UL)          /*!< TDBFLV (Bit 0)                                        */
+ #define R_I3C0_NDBSTLV0_TDBFLV_Msk     (0xffUL)       /*!< TDBFLV (Bitfield-Mask: 0xff)                          */
+ #define R_I3C0_NDBSTLV0_RDBLV_Pos      (8UL)          /*!< RDBLV (Bit 8)                                         */
+ #define R_I3C0_NDBSTLV0_RDBLV_Msk      (0xff00UL)     /*!< RDBLV (Bitfield-Mask: 0xff)                           */
+/* =======================================================  NRSQSTLV  ======================================================== */
+ #define R_I3C0_NRSQSTLV_RSQLV_Pos      (0UL)          /*!< RSQLV (Bit 0)                                         */
+ #define R_I3C0_NRSQSTLV_RSQLV_Msk      (0xffUL)       /*!< RSQLV (Bitfield-Mask: 0xff)                           */
+/* ========================================================  PRSTDBG  ======================================================== */
+ #define R_I3C0_PRSTDBG_SCILV_Pos       (0UL)          /*!< SCILV (Bit 0)                                         */
+ #define R_I3C0_PRSTDBG_SCILV_Msk       (0x1UL)        /*!< SCILV (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_PRSTDBG_SDILV_Pos       (1UL)          /*!< SDILV (Bit 1)                                         */
+ #define R_I3C0_PRSTDBG_SDILV_Msk       (0x2UL)        /*!< SDILV (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_PRSTDBG_SCOLV_Pos       (2UL)          /*!< SCOLV (Bit 2)                                         */
+ #define R_I3C0_PRSTDBG_SCOLV_Msk       (0x4UL)        /*!< SCOLV (Bitfield-Mask: 0x01)                           */
+ #define R_I3C0_PRSTDBG_SDOLV_Pos       (3UL)          /*!< SDOLV (Bit 3)                                         */
+ #define R_I3C0_PRSTDBG_SDOLV_Msk       (0x8UL)        /*!< SDOLV (Bitfield-Mask: 0x01)                           */
+/* =======================================================  MSERRCNT  ======================================================== */
+ #define R_I3C0_MSERRCNT_M2ECNT_Pos     (0UL)          /*!< M2ECNT (Bit 0)                                        */
+ #define R_I3C0_MSERRCNT_M2ECNT_Msk     (0xffUL)       /*!< M2ECNT (Bitfield-Mask: 0xff)                          */
+
+/* =========================================================================================================================== */
+/* ================                                        R_MPU_SPMON                                        ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MSTP                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  MSTPCRA  ======================================================== */
+ #define R_MSTP_MSTPCRA_MSTPA22_Pos    (22UL)         /*!< MSTPA22 (Bit 22)                                      */
+ #define R_MSTP_MSTPCRA_MSTPA22_Msk    (0x400000UL)   /*!< MSTPA22 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRA_MSTPA7_Pos     (7UL)          /*!< MSTPA7 (Bit 7)                                        */
+ #define R_MSTP_MSTPCRA_MSTPA7_Msk     (0x80UL)       /*!< MSTPA7 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRA_MSTPA0_Pos     (0UL)          /*!< MSTPA0 (Bit 0)                                        */
+ #define R_MSTP_MSTPCRA_MSTPA0_Msk     (0x1UL)        /*!< MSTPA0 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  MSTPCRB  ======================================================== */
+ #define R_MSTP_MSTPCRB_MSTPB31_Pos    (31UL)         /*!< MSTPB31 (Bit 31)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB31_Msk    (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB30_Pos    (30UL)         /*!< MSTPB30 (Bit 30)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB30_Msk    (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB29_Pos    (29UL)         /*!< MSTPB29 (Bit 29)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB29_Msk    (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB28_Pos    (28UL)         /*!< MSTPB28 (Bit 28)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB28_Msk    (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB27_Pos    (27UL)         /*!< MSTPB27 (Bit 27)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB27_Msk    (0x8000000UL)  /*!< MSTPB27 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB26_Pos    (26UL)         /*!< MSTPB26 (Bit 26)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB26_Msk    (0x4000000UL)  /*!< MSTPB26 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB25_Pos    (25UL)         /*!< MSTPB25 (Bit 25)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB25_Msk    (0x2000000UL)  /*!< MSTPB25 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB24_Pos    (24UL)         /*!< MSTPB24 (Bit 24)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB24_Msk    (0x1000000UL)  /*!< MSTPB24 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB23_Pos    (23UL)         /*!< MSTPB23 (Bit 23)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB23_Msk    (0x800000UL)   /*!< MSTPB23 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB22_Pos    (22UL)         /*!< MSTPB22 (Bit 22)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB22_Msk    (0x400000UL)   /*!< MSTPB22 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB19_Pos    (19UL)         /*!< MSTPB19 (Bit 19)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB19_Msk    (0x80000UL)    /*!< MSTPB19 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB18_Pos    (18UL)         /*!< MSTPB18 (Bit 18)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB18_Msk    (0x40000UL)    /*!< MSTPB18 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB16_Pos    (16UL)         /*!< MSTPB16 (Bit 16)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB16_Msk    (0x10000UL)    /*!< MSTPB16 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB15_Pos    (15UL)         /*!< MSTPB15 (Bit 15)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB15_Msk    (0x8000UL)     /*!< MSTPB15 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB14_Pos    (14UL)         /*!< MSTPB14 (Bit 14)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB14_Msk    (0x4000UL)     /*!< MSTPB14 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB13_Pos    (13UL)         /*!< MSTPB13 (Bit 13)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB13_Msk    (0x2000UL)     /*!< MSTPB13 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB12_Pos    (12UL)         /*!< MSTPB12 (Bit 12)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB12_Msk    (0x1000UL)     /*!< MSTPB12 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB11_Pos    (11UL)         /*!< MSTPB11 (Bit 11)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB11_Msk    (0x800UL)      /*!< MSTPB11 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB9_Pos     (9UL)          /*!< MSTPB9 (Bit 9)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB9_Msk     (0x200UL)      /*!< MSTPB9 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRB_MSTPB8_Pos     (8UL)          /*!< MSTPB8 (Bit 8)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB8_Msk     (0x100UL)      /*!< MSTPB8 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRB_MSTPB7_Pos     (7UL)          /*!< MSTPB7 (Bit 7)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB7_Msk     (0x80UL)       /*!< MSTPB7 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRB_MSTPB6_Pos     (6UL)          /*!< MSTPB6 (Bit 6)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB6_Msk     (0x40UL)       /*!< MSTPB6 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRB_MSTPB5_Pos     (5UL)          /*!< MSTPB5 (Bit 5)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB5_Msk     (0x20UL)       /*!< MSTPB5 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRB_MSTPB3_Pos     (3UL)          /*!< MSTPB3 (Bit 3)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB3_Msk     (0x8UL)        /*!< MSTPB3 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRB_MSTPB2_Pos     (2UL)          /*!< MSTPB2 (Bit 2)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB2_Msk     (0x4UL)        /*!< MSTPB2 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRB_MSTPB1_Pos     (1UL)          /*!< MSTPB1 (Bit 1)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB1_Msk     (0x2UL)        /*!< MSTPB1 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  MSTPCRC  ======================================================== */
+ #define R_MSTP_MSTPCRC_MSTPC31_Pos    (31UL)         /*!< MSTPC31 (Bit 31)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC31_Msk    (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC28_Pos    (28UL)         /*!< MSTPC28 (Bit 28)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC28_Msk    (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC27_Pos    (27UL)         /*!< MSTPC27 (Bit 27)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC27_Msk    (0x8000000UL)  /*!< MSTPC27 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC21_Pos    (21UL)         /*!< MSTPC21 (Bit 21)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC21_Msk    (0x200000UL)   /*!< MSTPC21 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC20_Pos    (20UL)         /*!< MSTPC20 (Bit 20)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC20_Msk    (0x100000UL)   /*!< MSTPC20 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC15_Pos    (15UL)         /*!< MSTPC15 (Bit 15)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC15_Msk    (0x8000UL)     /*!< MSTPC15 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC14_Pos    (14UL)         /*!< MSTPC14 (Bit 14)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC14_Msk    (0x4000UL)     /*!< MSTPC14 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC13_Pos    (13UL)         /*!< MSTPC13 (Bit 13)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC13_Msk    (0x2000UL)     /*!< MSTPC13 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC12_Pos    (12UL)         /*!< MSTPC12 (Bit 12)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC12_Msk    (0x1000UL)     /*!< MSTPC12 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC11_Pos    (11UL)         /*!< MSTPC11 (Bit 11)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC11_Msk    (0x800UL)      /*!< MSTPC11 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC9_Pos     (9UL)          /*!< MSTPC9 (Bit 9)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC9_Msk     (0x200UL)      /*!< MSTPC9 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC8_Pos     (8UL)          /*!< MSTPC8 (Bit 8)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC8_Msk     (0x100UL)      /*!< MSTPC8 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC7_Pos     (7UL)          /*!< MSTPC7 (Bit 7)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC7_Msk     (0x80UL)       /*!< MSTPC7 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC6_Pos     (6UL)          /*!< MSTPC6 (Bit 6)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC6_Msk     (0x40UL)       /*!< MSTPC6 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC5_Pos     (5UL)          /*!< MSTPC5 (Bit 5)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC5_Msk     (0x20UL)       /*!< MSTPC5 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC4_Pos     (4UL)          /*!< MSTPC4 (Bit 4)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC4_Msk     (0x10UL)       /*!< MSTPC4 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC3_Pos     (3UL)          /*!< MSTPC3 (Bit 3)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC3_Msk     (0x8UL)        /*!< MSTPC3 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC2_Pos     (2UL)          /*!< MSTPC2 (Bit 2)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC2_Msk     (0x4UL)        /*!< MSTPC2 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC1_Pos     (1UL)          /*!< MSTPC1 (Bit 1)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC1_Msk     (0x2UL)        /*!< MSTPC1 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC0_Pos     (0UL)          /*!< MSTPC0 (Bit 0)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC0_Msk     (0x1UL)        /*!< MSTPC0 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  MSTPCRD  ======================================================== */
+ #define R_MSTP_MSTPCRD_MSTPD31_Pos    (31UL)         /*!< MSTPD31 (Bit 31)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD31_Msk    (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD29_Pos    (29UL)         /*!< MSTPD29 (Bit 29)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD29_Msk    (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD28_Pos    (28UL)         /*!< MSTPD28 (Bit 28)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD28_Msk    (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD27_Pos    (27UL)         /*!< MSTPD27 (Bit 27)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD27_Msk    (0x8000000UL)  /*!< MSTPD27 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD26_Pos    (26UL)         /*!< MSTPD26 (Bit 26)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD26_Msk    (0x4000000UL)  /*!< MSTPD26 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD25_Pos    (25UL)         /*!< MSTPD25 (Bit 25)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD25_Msk    (0x2000000UL)  /*!< MSTPD25 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD24_Pos    (24UL)         /*!< MSTPD24 (Bit 24)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD24_Msk    (0x1000000UL)  /*!< MSTPD24 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD23_Pos    (23UL)         /*!< MSTPD23 (Bit 23)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD23_Msk    (0x800000UL)   /*!< MSTPD23 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD22_Pos    (22UL)         /*!< MSTPD22 (Bit 22)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD22_Msk    (0x400000UL)   /*!< MSTPD22 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD20_Pos    (20UL)         /*!< MSTPD20 (Bit 20)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD20_Msk    (0x100000UL)   /*!< MSTPD20 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD19_Pos    (19UL)         /*!< MSTPD19 (Bit 19)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD19_Msk    (0x80000UL)    /*!< MSTPD19 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD18_Pos    (18UL)         /*!< MSTPD18 (Bit 18)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD18_Msk    (0x40000UL)    /*!< MSTPD18 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD17_Pos    (17UL)         /*!< MSTPD17 (Bit 17)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD17_Msk    (0x20000UL)    /*!< MSTPD17 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD16_Pos    (16UL)         /*!< MSTPD16 (Bit 16)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD16_Msk    (0x10000UL)    /*!< MSTPD16 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD15_Pos    (15UL)         /*!< MSTPD15 (Bit 15)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD15_Msk    (0x8000UL)     /*!< MSTPD15 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD14_Pos    (14UL)         /*!< MSTPD14 (Bit 14)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD14_Msk    (0x4000UL)     /*!< MSTPD14 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD13_Pos    (13UL)         /*!< MSTPD13 (Bit 13)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD13_Msk    (0x2000UL)     /*!< MSTPD13 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD12_Pos    (12UL)         /*!< MSTPD12 (Bit 12)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD12_Msk    (0x1000UL)     /*!< MSTPD12 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD11_Pos    (11UL)         /*!< MSTPD11 (Bit 11)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD11_Msk    (0x800UL)      /*!< MSTPD11 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD10_Pos    (10UL)         /*!< MSTPD10 (Bit 10)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD10_Msk    (0x400UL)      /*!< MSTPD10 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD9_Pos     (9UL)          /*!< MSTPD9 (Bit 9)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD9_Msk     (0x200UL)      /*!< MSTPD9 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRD_MSTPD8_Pos     (8UL)          /*!< MSTPD8 (Bit 8)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD8_Msk     (0x100UL)      /*!< MSTPD8 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRD_MSTPD7_Pos     (7UL)          /*!< MSTPD7 (Bit 7)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD7_Msk     (0x80UL)       /*!< MSTPD7 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRD_MSTPD6_Pos     (6UL)          /*!< MSTPD6 (Bit 6)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD6_Msk     (0x40UL)       /*!< MSTPD6 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRD_MSTPD5_Pos     (5UL)          /*!< MSTPD5 (Bit 5)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD5_Msk     (0x20UL)       /*!< MSTPD5 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRD_MSTPD3_Pos     (3UL)          /*!< MSTPD3 (Bit 3)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD3_Msk     (0x8UL)        /*!< MSTPD3 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRD_MSTPD2_Pos     (2UL)          /*!< MSTPD2 (Bit 2)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD2_Msk     (0x4UL)        /*!< MSTPD2 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRD_MSTPD1_Pos     (1UL)          /*!< MSTPD1 (Bit 1)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD1_Msk     (0x2UL)        /*!< MSTPD1 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRD_MSTPD0_Pos     (0UL)          /*!< MSTPD0 (Bit 0)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD0_Msk     (0x1UL)        /*!< MSTPD0 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  MSTPCRE  ======================================================== */
+ #define R_MSTP_MSTPCRE_MSTPE4_Pos     (4UL)          /*!< MSTPE4 (Bit 4)                                        */
+ #define R_MSTP_MSTPCRE_MSTPE4_Msk     (0x10UL)       /*!< MSTPE4 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRE_MSTPE14_Pos    (14UL)         /*!< MSTPE14 (Bit 14)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE14_Msk    (0x4000UL)     /*!< MSTPE14 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE15_Pos    (15UL)         /*!< MSTPE15 (Bit 15)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE15_Msk    (0x8000UL)     /*!< MSTPE15 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE22_Pos    (22UL)         /*!< MSTPE22 (Bit 22)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE22_Msk    (0x400000UL)   /*!< MSTPE22 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE23_Pos    (23UL)         /*!< MSTPE23 (Bit 23)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE23_Msk    (0x800000UL)   /*!< MSTPE23 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE24_Pos    (24UL)         /*!< MSTPE24 (Bit 24)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE24_Msk    (0x1000000UL)  /*!< MSTPE24 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE25_Pos    (25UL)         /*!< MSTPE25 (Bit 25)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE25_Msk    (0x2000000UL)  /*!< MSTPE25 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE26_Pos    (26UL)         /*!< MSTPE26 (Bit 26)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE26_Msk    (0x4000000UL)  /*!< MSTPE26 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE27_Pos    (27UL)         /*!< MSTPE27 (Bit 27)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE27_Msk    (0x8000000UL)  /*!< MSTPE27 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE28_Pos    (28UL)         /*!< MSTPE28 (Bit 28)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE28_Msk    (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE29_Pos    (29UL)         /*!< MSTPE29 (Bit 29)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE29_Msk    (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE30_Pos    (30UL)         /*!< MSTPE30 (Bit 30)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE30_Msk    (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRE_MSTPE31_Pos    (31UL)         /*!< MSTPE31 (Bit 31)                                      */
+ #define R_MSTP_MSTPCRE_MSTPE31_Msk    (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_PORT0                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  PCNTR1  ========================================================= */
+ #define R_PORT0_PCNTR1_PODR_Pos    (16UL)         /*!< PODR (Bit 16)                                         */
+ #define R_PORT0_PCNTR1_PODR_Msk    (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff)                          */
+ #define R_PORT0_PCNTR1_PDR_Pos     (0UL)          /*!< PDR (Bit 0)                                           */
+ #define R_PORT0_PCNTR1_PDR_Msk     (0xffffUL)     /*!< PDR (Bitfield-Mask: 0xffff)                           */
+/* =========================================================  PODR  ========================================================== */
+ #define R_PORT0_PODR_PODR_Pos      (0UL)          /*!< PODR (Bit 0)                                          */
+ #define R_PORT0_PODR_PODR_Msk      (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  PDR  ========================================================== */
+ #define R_PORT0_PDR_PDR_Pos        (0UL)          /*!< PDR (Bit 0)                                           */
+ #define R_PORT0_PDR_PDR_Msk        (0x1UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
+/* ========================================================  PCNTR2  ========================================================= */
+ #define R_PORT0_PCNTR2_EIDR_Pos    (16UL)         /*!< EIDR (Bit 16)                                         */
+ #define R_PORT0_PCNTR2_EIDR_Msk    (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff)                          */
+ #define R_PORT0_PCNTR2_PIDR_Pos    (0UL)          /*!< PIDR (Bit 0)                                          */
+ #define R_PORT0_PCNTR2_PIDR_Msk    (0xffffUL)     /*!< PIDR (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  EIDR  ========================================================== */
+ #define R_PORT0_EIDR_EIDR_Pos      (0UL)          /*!< EIDR (Bit 0)                                          */
+ #define R_PORT0_EIDR_EIDR_Msk      (0x1UL)        /*!< EIDR (Bitfield-Mask: 0x01)                            */
+/* =========================================================  PIDR  ========================================================== */
+ #define R_PORT0_PIDR_PIDR_Pos      (0UL)          /*!< PIDR (Bit 0)                                          */
+ #define R_PORT0_PIDR_PIDR_Msk      (0x1UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  PCNTR3  ========================================================= */
+ #define R_PORT0_PCNTR3_PORR_Pos    (16UL)         /*!< PORR (Bit 16)                                         */
+ #define R_PORT0_PCNTR3_PORR_Msk    (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff)                          */
+ #define R_PORT0_PCNTR3_POSR_Pos    (0UL)          /*!< POSR (Bit 0)                                          */
+ #define R_PORT0_PCNTR3_POSR_Msk    (0xffffUL)     /*!< POSR (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  PORR  ========================================================== */
+ #define R_PORT0_PORR_PORR_Pos      (0UL)          /*!< PORR (Bit 0)                                          */
+ #define R_PORT0_PORR_PORR_Msk      (0x1UL)        /*!< PORR (Bitfield-Mask: 0x01)                            */
+/* =========================================================  POSR  ========================================================== */
+ #define R_PORT0_POSR_POSR_Pos      (0UL)          /*!< POSR (Bit 0)                                          */
+ #define R_PORT0_POSR_POSR_Msk      (0x1UL)        /*!< POSR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  PCNTR4  ========================================================= */
+ #define R_PORT0_PCNTR4_EORR_Pos    (16UL)         /*!< EORR (Bit 16)                                         */
+ #define R_PORT0_PCNTR4_EORR_Msk    (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff)                          */
+ #define R_PORT0_PCNTR4_EOSR_Pos    (0UL)          /*!< EOSR (Bit 0)                                          */
+ #define R_PORT0_PCNTR4_EOSR_Msk    (0xffffUL)     /*!< EOSR (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  EORR  ========================================================== */
+ #define R_PORT0_EORR_EORR_Pos      (0UL)          /*!< EORR (Bit 0)                                          */
+ #define R_PORT0_EORR_EORR_Msk      (0x1UL)        /*!< EORR (Bitfield-Mask: 0x01)                            */
+/* =========================================================  EOSR  ========================================================== */
+ #define R_PORT0_EOSR_EOSR_Pos      (0UL)          /*!< EOSR (Bit 0)                                          */
+ #define R_PORT0_EOSR_EOSR_Msk      (0x1UL)        /*!< EOSR (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_PFS                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_PMISC                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  PFENET  ========================================================= */
+ #define R_PMISC_PFENET_PHYMODE1_Pos    (5UL)    /*!< PHYMODE1 (Bit 5)                                      */
+ #define R_PMISC_PFENET_PHYMODE1_Msk    (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01)                        */
+ #define R_PMISC_PFENET_PHYMODE0_Pos    (4UL)    /*!< PHYMODE0 (Bit 4)                                      */
+ #define R_PMISC_PFENET_PHYMODE0_Msk    (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01)                        */
+/* =========================================================  PWPR  ========================================================== */
+ #define R_PMISC_PWPR_PFSWE_Pos         (6UL)    /*!< PFSWE (Bit 6)                                         */
+ #define R_PMISC_PWPR_PFSWE_Msk         (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
+ #define R_PMISC_PWPR_B0WI_Pos          (7UL)    /*!< B0WI (Bit 7)                                          */
+ #define R_PMISC_PWPR_B0WI_Msk          (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
+/* =========================================================  PWPRS  ========================================================= */
+ #define R_PMISC_PWPRS_PFSWE_Pos        (6UL)    /*!< PFSWE (Bit 6)                                         */
+ #define R_PMISC_PWPRS_PFSWE_Msk        (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
+ #define R_PMISC_PWPRS_B0WI_Pos         (7UL)    /*!< B0WI (Bit 7)                                          */
+ #define R_PMISC_PWPRS_B0WI_Msk         (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_QSPI                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  SFMSMD  ========================================================= */
+ #define R_QSPI_SFMSMD_SFMCCE_Pos       (15UL)         /*!< SFMCCE (Bit 15)                                       */
+ #define R_QSPI_SFMSMD_SFMCCE_Msk       (0x8000UL)     /*!< SFMCCE (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSMD_SFMOSW_Pos       (11UL)         /*!< SFMOSW (Bit 11)                                       */
+ #define R_QSPI_SFMSMD_SFMOSW_Msk       (0x800UL)      /*!< SFMOSW (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSMD_SFMOHW_Pos       (10UL)         /*!< SFMOHW (Bit 10)                                       */
+ #define R_QSPI_SFMSMD_SFMOHW_Msk       (0x400UL)      /*!< SFMOHW (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSMD_SFMOEX_Pos       (9UL)          /*!< SFMOEX (Bit 9)                                        */
+ #define R_QSPI_SFMSMD_SFMOEX_Msk       (0x200UL)      /*!< SFMOEX (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSMD_SFMMD3_Pos       (8UL)          /*!< SFMMD3 (Bit 8)                                        */
+ #define R_QSPI_SFMSMD_SFMMD3_Msk       (0x100UL)      /*!< SFMMD3 (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSMD_SFMPAE_Pos       (7UL)          /*!< SFMPAE (Bit 7)                                        */
+ #define R_QSPI_SFMSMD_SFMPAE_Msk       (0x80UL)       /*!< SFMPAE (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSMD_SFMPFE_Pos       (6UL)          /*!< SFMPFE (Bit 6)                                        */
+ #define R_QSPI_SFMSMD_SFMPFE_Msk       (0x40UL)       /*!< SFMPFE (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSMD_SFMSE_Pos        (4UL)          /*!< SFMSE (Bit 4)                                         */
+ #define R_QSPI_SFMSMD_SFMSE_Msk        (0x30UL)       /*!< SFMSE (Bitfield-Mask: 0x03)                           */
+ #define R_QSPI_SFMSMD_SFMRM_Pos        (0UL)          /*!< SFMRM (Bit 0)                                         */
+ #define R_QSPI_SFMSMD_SFMRM_Msk        (0x7UL)        /*!< SFMRM (Bitfield-Mask: 0x07)                           */
+/* ========================================================  SFMSSC  ========================================================= */
+ #define R_QSPI_SFMSSC_SFMSLD_Pos       (5UL)          /*!< SFMSLD (Bit 5)                                        */
+ #define R_QSPI_SFMSSC_SFMSLD_Msk       (0x20UL)       /*!< SFMSLD (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSSC_SFMSHD_Pos       (4UL)          /*!< SFMSHD (Bit 4)                                        */
+ #define R_QSPI_SFMSSC_SFMSHD_Msk       (0x10UL)       /*!< SFMSHD (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSSC_SFMSW_Pos        (0UL)          /*!< SFMSW (Bit 0)                                         */
+ #define R_QSPI_SFMSSC_SFMSW_Msk        (0xfUL)        /*!< SFMSW (Bitfield-Mask: 0x0f)                           */
+/* ========================================================  SFMSKC  ========================================================= */
+ #define R_QSPI_SFMSKC_SFMDTY_Pos       (5UL)          /*!< SFMDTY (Bit 5)                                        */
+ #define R_QSPI_SFMSKC_SFMDTY_Msk       (0x20UL)       /*!< SFMDTY (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSKC_SFMDV_Pos        (0UL)          /*!< SFMDV (Bit 0)                                         */
+ #define R_QSPI_SFMSKC_SFMDV_Msk        (0x1fUL)       /*!< SFMDV (Bitfield-Mask: 0x1f)                           */
+/* ========================================================  SFMSST  ========================================================= */
+ #define R_QSPI_SFMSST_PFOFF_Pos        (7UL)          /*!< PFOFF (Bit 7)                                         */
+ #define R_QSPI_SFMSST_PFOFF_Msk        (0x80UL)       /*!< PFOFF (Bitfield-Mask: 0x01)                           */
+ #define R_QSPI_SFMSST_PFFUL_Pos        (6UL)          /*!< PFFUL (Bit 6)                                         */
+ #define R_QSPI_SFMSST_PFFUL_Msk        (0x40UL)       /*!< PFFUL (Bitfield-Mask: 0x01)                           */
+ #define R_QSPI_SFMSST_PFCNT_Pos        (0UL)          /*!< PFCNT (Bit 0)                                         */
+ #define R_QSPI_SFMSST_PFCNT_Msk        (0x1fUL)       /*!< PFCNT (Bitfield-Mask: 0x1f)                           */
+/* ========================================================  SFMCOM  ========================================================= */
+ #define R_QSPI_SFMCOM_SFMD_Pos         (0UL)          /*!< SFMD (Bit 0)                                          */
+ #define R_QSPI_SFMCOM_SFMD_Msk         (0xffUL)       /*!< SFMD (Bitfield-Mask: 0xff)                            */
+/* ========================================================  SFMCMD  ========================================================= */
+ #define R_QSPI_SFMCMD_DCOM_Pos         (0UL)          /*!< DCOM (Bit 0)                                          */
+ #define R_QSPI_SFMCMD_DCOM_Msk         (0x1UL)        /*!< DCOM (Bitfield-Mask: 0x01)                            */
+/* ========================================================  SFMCST  ========================================================= */
+ #define R_QSPI_SFMCST_EROMR_Pos        (7UL)          /*!< EROMR (Bit 7)                                         */
+ #define R_QSPI_SFMCST_EROMR_Msk        (0x80UL)       /*!< EROMR (Bitfield-Mask: 0x01)                           */
+ #define R_QSPI_SFMCST_COMBSY_Pos       (0UL)          /*!< COMBSY (Bit 0)                                        */
+ #define R_QSPI_SFMCST_COMBSY_Msk       (0x1UL)        /*!< COMBSY (Bitfield-Mask: 0x01)                          */
+/* ========================================================  SFMSIC  ========================================================= */
+ #define R_QSPI_SFMSIC_SFMCIC_Pos       (0UL)          /*!< SFMCIC (Bit 0)                                        */
+ #define R_QSPI_SFMSIC_SFMCIC_Msk       (0xffUL)       /*!< SFMCIC (Bitfield-Mask: 0xff)                          */
+/* ========================================================  SFMSAC  ========================================================= */
+ #define R_QSPI_SFMSAC_SFM4BC_Pos       (4UL)          /*!< SFM4BC (Bit 4)                                        */
+ #define R_QSPI_SFMSAC_SFM4BC_Msk       (0x10UL)       /*!< SFM4BC (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSAC_SFMAS_Pos        (0UL)          /*!< SFMAS (Bit 0)                                         */
+ #define R_QSPI_SFMSAC_SFMAS_Msk        (0x3UL)        /*!< SFMAS (Bitfield-Mask: 0x03)                           */
+/* ========================================================  SFMSDC  ========================================================= */
+ #define R_QSPI_SFMSDC_SFMXD_Pos        (8UL)          /*!< SFMXD (Bit 8)                                         */
+ #define R_QSPI_SFMSDC_SFMXD_Msk        (0xff00UL)     /*!< SFMXD (Bitfield-Mask: 0xff)                           */
+ #define R_QSPI_SFMSDC_SFMXEN_Pos       (7UL)          /*!< SFMXEN (Bit 7)                                        */
+ #define R_QSPI_SFMSDC_SFMXEN_Msk       (0x80UL)       /*!< SFMXEN (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSDC_SFMXST_Pos       (6UL)          /*!< SFMXST (Bit 6)                                        */
+ #define R_QSPI_SFMSDC_SFMXST_Msk       (0x40UL)       /*!< SFMXST (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSDC_SFMDN_Pos        (0UL)          /*!< SFMDN (Bit 0)                                         */
+ #define R_QSPI_SFMSDC_SFMDN_Msk        (0xfUL)        /*!< SFMDN (Bitfield-Mask: 0x0f)                           */
+/* ========================================================  SFMSPC  ========================================================= */
+ #define R_QSPI_SFMSPC_SFMSDE_Pos       (4UL)          /*!< SFMSDE (Bit 4)                                        */
+ #define R_QSPI_SFMSPC_SFMSDE_Msk       (0x10UL)       /*!< SFMSDE (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSPC_SFMSPI_Pos       (0UL)          /*!< SFMSPI (Bit 0)                                        */
+ #define R_QSPI_SFMSPC_SFMSPI_Msk       (0x3UL)        /*!< SFMSPI (Bitfield-Mask: 0x03)                          */
+/* ========================================================  SFMPMD  ========================================================= */
+ #define R_QSPI_SFMPMD_SFMWPL_Pos       (2UL)          /*!< SFMWPL (Bit 2)                                        */
+ #define R_QSPI_SFMPMD_SFMWPL_Msk       (0x4UL)        /*!< SFMWPL (Bitfield-Mask: 0x01)                          */
+/* ========================================================  SFMCNT1  ======================================================== */
+ #define R_QSPI_SFMCNT1_QSPI_EXT_Pos    (26UL)         /*!< QSPI_EXT (Bit 26)                                     */
+ #define R_QSPI_SFMCNT1_QSPI_EXT_Msk    (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           R_RTC                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  R64CNT  ========================================================= */
+ #define R_RTC_R64CNT_F1HZ_Pos        (6UL)      /*!< F1HZ (Bit 6)                                          */
+ #define R_RTC_R64CNT_F1HZ_Msk        (0x40UL)   /*!< F1HZ (Bitfield-Mask: 0x01)                            */
+ #define R_RTC_R64CNT_F2HZ_Pos        (5UL)      /*!< F2HZ (Bit 5)                                          */
+ #define R_RTC_R64CNT_F2HZ_Msk        (0x20UL)   /*!< F2HZ (Bitfield-Mask: 0x01)                            */
+ #define R_RTC_R64CNT_F4HZ_Pos        (4UL)      /*!< F4HZ (Bit 4)                                          */
+ #define R_RTC_R64CNT_F4HZ_Msk        (0x10UL)   /*!< F4HZ (Bitfield-Mask: 0x01)                            */
+ #define R_RTC_R64CNT_F8HZ_Pos        (3UL)      /*!< F8HZ (Bit 3)                                          */
+ #define R_RTC_R64CNT_F8HZ_Msk        (0x8UL)    /*!< F8HZ (Bitfield-Mask: 0x01)                            */
+ #define R_RTC_R64CNT_F16HZ_Pos       (2UL)      /*!< F16HZ (Bit 2)                                         */
+ #define R_RTC_R64CNT_F16HZ_Msk       (0x4UL)    /*!< F16HZ (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_R64CNT_F32HZ_Pos       (1UL)      /*!< F32HZ (Bit 1)                                         */
+ #define R_RTC_R64CNT_F32HZ_Msk       (0x2UL)    /*!< F32HZ (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_R64CNT_F64HZ_Pos       (0UL)      /*!< F64HZ (Bit 0)                                         */
+ #define R_RTC_R64CNT_F64HZ_Msk       (0x1UL)    /*!< F64HZ (Bitfield-Mask: 0x01)                           */
+/* ========================================================  RSECCNT  ======================================================== */
+ #define R_RTC_RSECCNT_SEC10_Pos      (4UL)      /*!< SEC10 (Bit 4)                                         */
+ #define R_RTC_RSECCNT_SEC10_Msk      (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
+ #define R_RTC_RSECCNT_SEC1_Pos       (0UL)      /*!< SEC1 (Bit 0)                                          */
+ #define R_RTC_RSECCNT_SEC1_Msk       (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  BCNT0  ========================================================= */
+ #define R_RTC_BCNT0_BCNT0_Pos        (0UL)      /*!< BCNT0 (Bit 0)                                         */
+ #define R_RTC_BCNT0_BCNT0_Msk        (0xffUL)   /*!< BCNT0 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  RMINCNT  ======================================================== */
+ #define R_RTC_RMINCNT_MIN10_Pos      (4UL)      /*!< MIN10 (Bit 4)                                         */
+ #define R_RTC_RMINCNT_MIN10_Msk      (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
+ #define R_RTC_RMINCNT_MIN1_Pos       (0UL)      /*!< MIN1 (Bit 0)                                          */
+ #define R_RTC_RMINCNT_MIN1_Msk       (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  BCNT1  ========================================================= */
+ #define R_RTC_BCNT1_BCNT1_Pos        (0UL)      /*!< BCNT1 (Bit 0)                                         */
+ #define R_RTC_BCNT1_BCNT1_Msk        (0xffUL)   /*!< BCNT1 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  RHRCNT  ========================================================= */
+ #define R_RTC_RHRCNT_PM_Pos          (6UL)      /*!< PM (Bit 6)                                            */
+ #define R_RTC_RHRCNT_PM_Msk          (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
+ #define R_RTC_RHRCNT_HR10_Pos        (4UL)      /*!< HR10 (Bit 4)                                          */
+ #define R_RTC_RHRCNT_HR10_Msk        (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
+ #define R_RTC_RHRCNT_HR1_Pos         (0UL)      /*!< HR1 (Bit 0)                                           */
+ #define R_RTC_RHRCNT_HR1_Msk         (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  BCNT2  ========================================================= */
+ #define R_RTC_BCNT2_BCNT2_Pos        (0UL)      /*!< BCNT2 (Bit 0)                                         */
+ #define R_RTC_BCNT2_BCNT2_Msk        (0xffUL)   /*!< BCNT2 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  RWKCNT  ========================================================= */
+ #define R_RTC_RWKCNT_DAYW_Pos        (0UL)      /*!< DAYW (Bit 0)                                          */
+ #define R_RTC_RWKCNT_DAYW_Msk        (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
+/* =========================================================  BCNT3  ========================================================= */
+ #define R_RTC_BCNT3_BCNT3_Pos        (0UL)      /*!< BCNT3 (Bit 0)                                         */
+ #define R_RTC_BCNT3_BCNT3_Msk        (0xffUL)   /*!< BCNT3 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  RDAYCNT  ======================================================== */
+ #define R_RTC_RDAYCNT_DATE10_Pos     (4UL)      /*!< DATE10 (Bit 4)                                        */
+ #define R_RTC_RDAYCNT_DATE10_Msk     (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
+ #define R_RTC_RDAYCNT_DATE1_Pos      (0UL)      /*!< DATE1 (Bit 0)                                         */
+ #define R_RTC_RDAYCNT_DATE1_Msk      (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
+/* ========================================================  RMONCNT  ======================================================== */
+ #define R_RTC_RMONCNT_MON10_Pos      (4UL)      /*!< MON10 (Bit 4)                                         */
+ #define R_RTC_RMONCNT_MON10_Msk      (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RMONCNT_MON1_Pos       (0UL)      /*!< MON1 (Bit 0)                                          */
+ #define R_RTC_RMONCNT_MON1_Msk       (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  RYRCNT  ========================================================= */
+ #define R_RTC_RYRCNT_YR10_Pos        (4UL)      /*!< YR10 (Bit 4)                                          */
+ #define R_RTC_RYRCNT_YR10_Msk        (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
+ #define R_RTC_RYRCNT_YR1_Pos         (0UL)      /*!< YR1 (Bit 0)                                           */
+ #define R_RTC_RYRCNT_YR1_Msk         (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
+/* ========================================================  RSECAR  ========================================================= */
+ #define R_RTC_RSECAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RSECAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RSECAR_SEC10_Pos       (4UL)      /*!< SEC10 (Bit 4)                                         */
+ #define R_RTC_RSECAR_SEC10_Msk       (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
+ #define R_RTC_RSECAR_SEC1_Pos        (0UL)      /*!< SEC1 (Bit 0)                                          */
+ #define R_RTC_RSECAR_SEC1_Msk        (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  BCNT0AR  ======================================================== */
+ #define R_RTC_BCNT0AR_BCNT0AR_Pos    (0UL)      /*!< BCNT0AR (Bit 0)                                       */
+ #define R_RTC_BCNT0AR_BCNT0AR_Msk    (0xffUL)   /*!< BCNT0AR (Bitfield-Mask: 0xff)                         */
+/* ========================================================  RMINAR  ========================================================= */
+ #define R_RTC_RMINAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RMINAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RMINAR_MIN10_Pos       (4UL)      /*!< MIN10 (Bit 4)                                         */
+ #define R_RTC_RMINAR_MIN10_Msk       (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
+ #define R_RTC_RMINAR_MIN1_Pos        (0UL)      /*!< MIN1 (Bit 0)                                          */
+ #define R_RTC_RMINAR_MIN1_Msk        (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  BCNT1AR  ======================================================== */
+ #define R_RTC_BCNT1AR_BCNT1AR_Pos    (0UL)      /*!< BCNT1AR (Bit 0)                                       */
+ #define R_RTC_BCNT1AR_BCNT1AR_Msk    (0xffUL)   /*!< BCNT1AR (Bitfield-Mask: 0xff)                         */
+/* =========================================================  RHRAR  ========================================================= */
+ #define R_RTC_RHRAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RHRAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RHRAR_PM_Pos           (6UL)      /*!< PM (Bit 6)                                            */
+ #define R_RTC_RHRAR_PM_Msk           (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
+ #define R_RTC_RHRAR_HR10_Pos         (4UL)      /*!< HR10 (Bit 4)                                          */
+ #define R_RTC_RHRAR_HR10_Msk         (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
+ #define R_RTC_RHRAR_HR1_Pos          (0UL)      /*!< HR1 (Bit 0)                                           */
+ #define R_RTC_RHRAR_HR1_Msk          (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
+/* ========================================================  BCNT2AR  ======================================================== */
+ #define R_RTC_BCNT2AR_BCNT2AR_Pos    (0UL)      /*!< BCNT2AR (Bit 0)                                       */
+ #define R_RTC_BCNT2AR_BCNT2AR_Msk    (0xffUL)   /*!< BCNT2AR (Bitfield-Mask: 0xff)                         */
+/* =========================================================  RWKAR  ========================================================= */
+ #define R_RTC_RWKAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RWKAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RWKAR_DAYW_Pos         (0UL)      /*!< DAYW (Bit 0)                                          */
+ #define R_RTC_RWKAR_DAYW_Msk         (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
+/* ========================================================  BCNT3AR  ======================================================== */
+ #define R_RTC_BCNT3AR_BCNT3AR_Pos    (0UL)      /*!< BCNT3AR (Bit 0)                                       */
+ #define R_RTC_BCNT3AR_BCNT3AR_Msk    (0xffUL)   /*!< BCNT3AR (Bitfield-Mask: 0xff)                         */
+/* ========================================================  RDAYAR  ========================================================= */
+ #define R_RTC_RDAYAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RDAYAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RDAYAR_DATE10_Pos      (4UL)      /*!< DATE10 (Bit 4)                                        */
+ #define R_RTC_RDAYAR_DATE10_Msk      (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
+ #define R_RTC_RDAYAR_DATE1_Pos       (0UL)      /*!< DATE1 (Bit 0)                                         */
+ #define R_RTC_RDAYAR_DATE1_Msk       (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
+/* =======================================================  BCNT0AER  ======================================================== */
+ #define R_RTC_BCNT0AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
+ #define R_RTC_BCNT0AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
+/* ========================================================  RMONAR  ========================================================= */
+ #define R_RTC_RMONAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RMONAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RMONAR_MON10_Pos       (4UL)      /*!< MON10 (Bit 4)                                         */
+ #define R_RTC_RMONAR_MON10_Msk       (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RMONAR_MON1_Pos        (0UL)      /*!< MON1 (Bit 0)                                          */
+ #define R_RTC_RMONAR_MON1_Msk        (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
+/* =======================================================  BCNT1AER  ======================================================== */
+ #define R_RTC_BCNT1AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
+ #define R_RTC_BCNT1AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
+/* =========================================================  RYRAR  ========================================================= */
+ #define R_RTC_RYRAR_YR10_Pos         (4UL)      /*!< YR10 (Bit 4)                                          */
+ #define R_RTC_RYRAR_YR10_Msk         (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
+ #define R_RTC_RYRAR_YR1_Pos          (0UL)      /*!< YR1 (Bit 0)                                           */
+ #define R_RTC_RYRAR_YR1_Msk          (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
+/* =======================================================  BCNT2AER  ======================================================== */
+ #define R_RTC_BCNT2AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
+ #define R_RTC_BCNT2AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
+/* ========================================================  RYRAREN  ======================================================== */
+ #define R_RTC_RYRAREN_ENB_Pos        (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RYRAREN_ENB_Msk        (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+/* =======================================================  BCNT3AER  ======================================================== */
+ #define R_RTC_BCNT3AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
+ #define R_RTC_BCNT3AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
+/* =========================================================  RCR1  ========================================================== */
+ #define R_RTC_RCR1_PES_Pos           (4UL)      /*!< PES (Bit 4)                                           */
+ #define R_RTC_RCR1_PES_Msk           (0xf0UL)   /*!< PES (Bitfield-Mask: 0x0f)                             */
+ #define R_RTC_RCR1_RTCOS_Pos         (3UL)      /*!< RTCOS (Bit 3)                                         */
+ #define R_RTC_RCR1_RTCOS_Msk         (0x8UL)    /*!< RTCOS (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR1_PIE_Pos           (2UL)      /*!< PIE (Bit 2)                                           */
+ #define R_RTC_RCR1_PIE_Msk           (0x4UL)    /*!< PIE (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RCR1_CIE_Pos           (1UL)      /*!< CIE (Bit 1)                                           */
+ #define R_RTC_RCR1_CIE_Msk           (0x2UL)    /*!< CIE (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RCR1_AIE_Pos           (0UL)      /*!< AIE (Bit 0)                                           */
+ #define R_RTC_RCR1_AIE_Msk           (0x1UL)    /*!< AIE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  RCR2  ========================================================== */
+ #define R_RTC_RCR2_CNTMD_Pos         (7UL)      /*!< CNTMD (Bit 7)                                         */
+ #define R_RTC_RCR2_CNTMD_Msk         (0x80UL)   /*!< CNTMD (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR2_HR24_Pos          (6UL)      /*!< HR24 (Bit 6)                                          */
+ #define R_RTC_RCR2_HR24_Msk          (0x40UL)   /*!< HR24 (Bitfield-Mask: 0x01)                            */
+ #define R_RTC_RCR2_AADJP_Pos         (5UL)      /*!< AADJP (Bit 5)                                         */
+ #define R_RTC_RCR2_AADJP_Msk         (0x20UL)   /*!< AADJP (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR2_AADJE_Pos         (4UL)      /*!< AADJE (Bit 4)                                         */
+ #define R_RTC_RCR2_AADJE_Msk         (0x10UL)   /*!< AADJE (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR2_RTCOE_Pos         (3UL)      /*!< RTCOE (Bit 3)                                         */
+ #define R_RTC_RCR2_RTCOE_Msk         (0x8UL)    /*!< RTCOE (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR2_ADJ30_Pos         (2UL)      /*!< ADJ30 (Bit 2)                                         */
+ #define R_RTC_RCR2_ADJ30_Msk         (0x4UL)    /*!< ADJ30 (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR2_RESET_Pos         (1UL)      /*!< RESET (Bit 1)                                         */
+ #define R_RTC_RCR2_RESET_Msk         (0x2UL)    /*!< RESET (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR2_START_Pos         (0UL)      /*!< START (Bit 0)                                         */
+ #define R_RTC_RCR2_START_Msk         (0x1UL)    /*!< START (Bitfield-Mask: 0x01)                           */
+/* =========================================================  RCR4  ========================================================== */
+ #define R_RTC_RCR4_RCKSEL_Pos        (0UL)      /*!< RCKSEL (Bit 0)                                        */
+ #define R_RTC_RCR4_RCKSEL_Msk        (0x1UL)    /*!< RCKSEL (Bitfield-Mask: 0x01)                          */
+ #define R_RTC_RCR4_ROPSEL_Pos        (7UL)      /*!< ROPSEL (Bit 7)                                        */
+ #define R_RTC_RCR4_ROPSEL_Msk        (0x80UL)   /*!< ROPSEL (Bitfield-Mask: 0x01)                          */
+/* =========================================================  RFRH  ========================================================== */
+ #define R_RTC_RFRH_RFC16_Pos         (0UL)      /*!< RFC16 (Bit 0)                                         */
+ #define R_RTC_RFRH_RFC16_Msk         (0x1UL)    /*!< RFC16 (Bitfield-Mask: 0x01)                           */
+/* =========================================================  RFRL  ========================================================== */
+ #define R_RTC_RFRL_RFC_Pos           (0UL)      /*!< RFC (Bit 0)                                           */
+ #define R_RTC_RFRL_RFC_Msk           (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff)                           */
+/* =========================================================  RADJ  ========================================================== */
+ #define R_RTC_RADJ_PMADJ_Pos         (6UL)      /*!< PMADJ (Bit 6)                                         */
+ #define R_RTC_RADJ_PMADJ_Msk         (0xc0UL)   /*!< PMADJ (Bitfield-Mask: 0x03)                           */
+ #define R_RTC_RADJ_ADJ_Pos           (0UL)      /*!< ADJ (Bit 0)                                           */
+ #define R_RTC_RADJ_ADJ_Msk           (0x3fUL)   /*!< ADJ (Bitfield-Mask: 0x3f)                             */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SCI0                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  SMR  ========================================================== */
+ #define R_SCI0_SMR_CM_Pos              (7UL)      /*!< CM (Bit 7)                                            */
+ #define R_SCI0_SMR_CM_Msk              (0x80UL)   /*!< CM (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_CHR_Pos             (6UL)      /*!< CHR (Bit 6)                                           */
+ #define R_SCI0_SMR_CHR_Msk             (0x40UL)   /*!< CHR (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SMR_PE_Pos              (5UL)      /*!< PE (Bit 5)                                            */
+ #define R_SCI0_SMR_PE_Msk              (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_PM_Pos              (4UL)      /*!< PM (Bit 4)                                            */
+ #define R_SCI0_SMR_PM_Msk              (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_STOP_Pos            (3UL)      /*!< STOP (Bit 3)                                          */
+ #define R_SCI0_SMR_STOP_Msk            (0x8UL)    /*!< STOP (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SMR_MP_Pos              (2UL)      /*!< MP (Bit 2)                                            */
+ #define R_SCI0_SMR_MP_Msk              (0x4UL)    /*!< MP (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_CKS_Pos             (0UL)      /*!< CKS (Bit 0)                                           */
+ #define R_SCI0_SMR_CKS_Msk             (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
+/* =======================================================  SMR_SMCI  ======================================================== */
+ #define R_SCI0_SMR_SMCI_GM_Pos         (7UL)      /*!< GM (Bit 7)                                            */
+ #define R_SCI0_SMR_SMCI_GM_Msk         (0x80UL)   /*!< GM (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_SMCI_BLK_Pos        (6UL)      /*!< BLK (Bit 6)                                           */
+ #define R_SCI0_SMR_SMCI_BLK_Msk        (0x40UL)   /*!< BLK (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SMR_SMCI_PE_Pos         (5UL)      /*!< PE (Bit 5)                                            */
+ #define R_SCI0_SMR_SMCI_PE_Msk         (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_SMCI_PM_Pos         (4UL)      /*!< PM (Bit 4)                                            */
+ #define R_SCI0_SMR_SMCI_PM_Msk         (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_SMCI_BCP_Pos        (2UL)      /*!< BCP (Bit 2)                                           */
+ #define R_SCI0_SMR_SMCI_BCP_Msk        (0xcUL)    /*!< BCP (Bitfield-Mask: 0x03)                             */
+ #define R_SCI0_SMR_SMCI_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
+ #define R_SCI0_SMR_SMCI_CKS_Msk        (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
+/* ==========================================================  BRR  ========================================================== */
+ #define R_SCI0_BRR_BRR_Pos             (0UL)      /*!< BRR (Bit 0)                                           */
+ #define R_SCI0_BRR_BRR_Msk             (0xffUL)   /*!< BRR (Bitfield-Mask: 0xff)                             */
+/* ==========================================================  SCR  ========================================================== */
+ #define R_SCI0_SCR_TIE_Pos             (7UL)      /*!< TIE (Bit 7)                                           */
+ #define R_SCI0_SCR_TIE_Msk             (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SCR_RIE_Pos             (6UL)      /*!< RIE (Bit 6)                                           */
+ #define R_SCI0_SCR_RIE_Msk             (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SCR_TE_Pos              (5UL)      /*!< TE (Bit 5)                                            */
+ #define R_SCI0_SCR_TE_Msk              (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SCR_RE_Pos              (4UL)      /*!< RE (Bit 4)                                            */
+ #define R_SCI0_SCR_RE_Msk              (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SCR_MPIE_Pos            (3UL)      /*!< MPIE (Bit 3)                                          */
+ #define R_SCI0_SCR_MPIE_Msk            (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCR_TEIE_Pos            (2UL)      /*!< TEIE (Bit 2)                                          */
+ #define R_SCI0_SCR_TEIE_Msk            (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCR_CKE_Pos             (0UL)      /*!< CKE (Bit 0)                                           */
+ #define R_SCI0_SCR_CKE_Msk             (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
+/* =======================================================  SCR_SMCI  ======================================================== */
+ #define R_SCI0_SCR_SMCI_TIE_Pos        (7UL)      /*!< TIE (Bit 7)                                           */
+ #define R_SCI0_SCR_SMCI_TIE_Msk        (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SCR_SMCI_RIE_Pos        (6UL)      /*!< RIE (Bit 6)                                           */
+ #define R_SCI0_SCR_SMCI_RIE_Msk        (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SCR_SMCI_TE_Pos         (5UL)      /*!< TE (Bit 5)                                            */
+ #define R_SCI0_SCR_SMCI_TE_Msk         (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SCR_SMCI_RE_Pos         (4UL)      /*!< RE (Bit 4)                                            */
+ #define R_SCI0_SCR_SMCI_RE_Msk         (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SCR_SMCI_MPIE_Pos       (3UL)      /*!< MPIE (Bit 3)                                          */
+ #define R_SCI0_SCR_SMCI_MPIE_Msk       (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCR_SMCI_TEIE_Pos       (2UL)      /*!< TEIE (Bit 2)                                          */
+ #define R_SCI0_SCR_SMCI_TEIE_Msk       (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCR_SMCI_CKE_Pos        (0UL)      /*!< CKE (Bit 0)                                           */
+ #define R_SCI0_SCR_SMCI_CKE_Msk        (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
+/* ==========================================================  TDR  ========================================================== */
+ #define R_SCI0_TDR_TDR_Pos             (0UL)      /*!< TDR (Bit 0)                                           */
+ #define R_SCI0_TDR_TDR_Msk             (0xffUL)   /*!< TDR (Bitfield-Mask: 0xff)                             */
+/* ==========================================================  SSR  ========================================================== */
+ #define R_SCI0_SSR_TDRE_Pos            (7UL)      /*!< TDRE (Bit 7)                                          */
+ #define R_SCI0_SSR_TDRE_Msk            (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_RDRF_Pos            (6UL)      /*!< RDRF (Bit 6)                                          */
+ #define R_SCI0_SSR_RDRF_Msk            (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_ORER_Pos            (5UL)      /*!< ORER (Bit 5)                                          */
+ #define R_SCI0_SSR_ORER_Msk            (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_FER_Pos             (4UL)      /*!< FER (Bit 4)                                           */
+ #define R_SCI0_SSR_FER_Msk             (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_PER_Pos             (3UL)      /*!< PER (Bit 3)                                           */
+ #define R_SCI0_SSR_PER_Msk             (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_TEND_Pos            (2UL)      /*!< TEND (Bit 2)                                          */
+ #define R_SCI0_SSR_TEND_Msk            (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_MPB_Pos             (1UL)      /*!< MPB (Bit 1)                                           */
+ #define R_SCI0_SSR_MPB_Msk             (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_MPBT_Pos            (0UL)      /*!< MPBT (Bit 0)                                          */
+ #define R_SCI0_SSR_MPBT_Msk            (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
+/* =======================================================  SSR_FIFO  ======================================================== */
+ #define R_SCI0_SSR_FIFO_TDFE_Pos       (7UL)      /*!< TDFE (Bit 7)                                          */
+ #define R_SCI0_SSR_FIFO_TDFE_Msk       (0x80UL)   /*!< TDFE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_FIFO_RDF_Pos        (6UL)      /*!< RDF (Bit 6)                                           */
+ #define R_SCI0_SSR_FIFO_RDF_Msk        (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_FIFO_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
+ #define R_SCI0_SSR_FIFO_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_FIFO_FER_Pos        (4UL)      /*!< FER (Bit 4)                                           */
+ #define R_SCI0_SSR_FIFO_FER_Msk        (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_FIFO_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
+ #define R_SCI0_SSR_FIFO_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_FIFO_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
+ #define R_SCI0_SSR_FIFO_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_FIFO_DR_Pos         (0UL)      /*!< DR (Bit 0)                                            */
+ #define R_SCI0_SSR_FIFO_DR_Msk         (0x1UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
+/* =======================================================  SSR_SMCI  ======================================================== */
+ #define R_SCI0_SSR_SMCI_TDRE_Pos       (7UL)      /*!< TDRE (Bit 7)                                          */
+ #define R_SCI0_SSR_SMCI_TDRE_Msk       (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_SMCI_RDRF_Pos       (6UL)      /*!< RDRF (Bit 6)                                          */
+ #define R_SCI0_SSR_SMCI_RDRF_Msk       (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_SMCI_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
+ #define R_SCI0_SSR_SMCI_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_SMCI_ERS_Pos        (4UL)      /*!< ERS (Bit 4)                                           */
+ #define R_SCI0_SSR_SMCI_ERS_Msk        (0x10UL)   /*!< ERS (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_SMCI_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
+ #define R_SCI0_SSR_SMCI_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_SMCI_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
+ #define R_SCI0_SSR_SMCI_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_SMCI_MPB_Pos        (1UL)      /*!< MPB (Bit 1)                                           */
+ #define R_SCI0_SSR_SMCI_MPB_Msk        (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_SMCI_MPBT_Pos       (0UL)      /*!< MPBT (Bit 0)                                          */
+ #define R_SCI0_SSR_SMCI_MPBT_Msk       (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  RDR  ========================================================== */
+ #define R_SCI0_RDR_RDR_Pos             (0UL)      /*!< RDR (Bit 0)                                           */
+ #define R_SCI0_RDR_RDR_Msk             (0xffUL)   /*!< RDR (Bitfield-Mask: 0xff)                             */
+/* =========================================================  SCMR  ========================================================== */
+ #define R_SCI0_SCMR_BCP2_Pos           (7UL)      /*!< BCP2 (Bit 7)                                          */
+ #define R_SCI0_SCMR_BCP2_Msk           (0x80UL)   /*!< BCP2 (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCMR_CHR1_Pos           (4UL)      /*!< CHR1 (Bit 4)                                          */
+ #define R_SCI0_SCMR_CHR1_Msk           (0x10UL)   /*!< CHR1 (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCMR_SDIR_Pos           (3UL)      /*!< SDIR (Bit 3)                                          */
+ #define R_SCI0_SCMR_SDIR_Msk           (0x8UL)    /*!< SDIR (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCMR_SINV_Pos           (2UL)      /*!< SINV (Bit 2)                                          */
+ #define R_SCI0_SCMR_SINV_Msk           (0x4UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCMR_SMIF_Pos           (0UL)      /*!< SMIF (Bit 0)                                          */
+ #define R_SCI0_SCMR_SMIF_Msk           (0x1UL)    /*!< SMIF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SEMR  ========================================================== */
+ #define R_SCI0_SEMR_RXDESEL_Pos        (7UL)      /*!< RXDESEL (Bit 7)                                       */
+ #define R_SCI0_SEMR_RXDESEL_Msk        (0x80UL)   /*!< RXDESEL (Bitfield-Mask: 0x01)                         */
+ #define R_SCI0_SEMR_BGDM_Pos           (6UL)      /*!< BGDM (Bit 6)                                          */
+ #define R_SCI0_SEMR_BGDM_Msk           (0x40UL)   /*!< BGDM (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SEMR_NFEN_Pos           (5UL)      /*!< NFEN (Bit 5)                                          */
+ #define R_SCI0_SEMR_NFEN_Msk           (0x20UL)   /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SEMR_ABCS_Pos           (4UL)      /*!< ABCS (Bit 4)                                          */
+ #define R_SCI0_SEMR_ABCS_Msk           (0x10UL)   /*!< ABCS (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SEMR_ABCSE_Pos          (3UL)      /*!< ABCSE (Bit 3)                                         */
+ #define R_SCI0_SEMR_ABCSE_Msk          (0x8UL)    /*!< ABCSE (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_SEMR_BRME_Pos           (2UL)      /*!< BRME (Bit 2)                                          */
+ #define R_SCI0_SEMR_BRME_Msk           (0x4UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SEMR_PADIS_Pos          (1UL)      /*!< PADIS (Bit 1)                                         */
+ #define R_SCI0_SEMR_PADIS_Msk          (0x2UL)    /*!< PADIS (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_SEMR_ACS0_Pos           (0UL)      /*!< ACS0 (Bit 0)                                          */
+ #define R_SCI0_SEMR_ACS0_Msk           (0x1UL)    /*!< ACS0 (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SNFR  ========================================================== */
+ #define R_SCI0_SNFR_NFCS_Pos           (0UL)      /*!< NFCS (Bit 0)                                          */
+ #define R_SCI0_SNFR_NFCS_Msk           (0x7UL)    /*!< NFCS (Bitfield-Mask: 0x07)                            */
+/* =========================================================  SIMR1  ========================================================= */
+ #define R_SCI0_SIMR1_IICDL_Pos         (3UL)      /*!< IICDL (Bit 3)                                         */
+ #define R_SCI0_SIMR1_IICDL_Msk         (0xf8UL)   /*!< IICDL (Bitfield-Mask: 0x1f)                           */
+ #define R_SCI0_SIMR1_IICM_Pos          (0UL)      /*!< IICM (Bit 0)                                          */
+ #define R_SCI0_SIMR1_IICM_Msk          (0x1UL)    /*!< IICM (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SIMR2  ========================================================= */
+ #define R_SCI0_SIMR2_IICACKT_Pos       (5UL)      /*!< IICACKT (Bit 5)                                       */
+ #define R_SCI0_SIMR2_IICACKT_Msk       (0x20UL)   /*!< IICACKT (Bitfield-Mask: 0x01)                         */
+ #define R_SCI0_SIMR2_IICCSC_Pos        (1UL)      /*!< IICCSC (Bit 1)                                        */
+ #define R_SCI0_SIMR2_IICCSC_Msk        (0x2UL)    /*!< IICCSC (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_SIMR2_IICINTM_Pos       (0UL)      /*!< IICINTM (Bit 0)                                       */
+ #define R_SCI0_SIMR2_IICINTM_Msk       (0x1UL)    /*!< IICINTM (Bitfield-Mask: 0x01)                         */
+/* =========================================================  SIMR3  ========================================================= */
+ #define R_SCI0_SIMR3_IICSCLS_Pos       (6UL)      /*!< IICSCLS (Bit 6)                                       */
+ #define R_SCI0_SIMR3_IICSCLS_Msk       (0xc0UL)   /*!< IICSCLS (Bitfield-Mask: 0x03)                         */
+ #define R_SCI0_SIMR3_IICSDAS_Pos       (4UL)      /*!< IICSDAS (Bit 4)                                       */
+ #define R_SCI0_SIMR3_IICSDAS_Msk       (0x30UL)   /*!< IICSDAS (Bitfield-Mask: 0x03)                         */
+ #define R_SCI0_SIMR3_IICSTIF_Pos       (3UL)      /*!< IICSTIF (Bit 3)                                       */
+ #define R_SCI0_SIMR3_IICSTIF_Msk       (0x8UL)    /*!< IICSTIF (Bitfield-Mask: 0x01)                         */
+ #define R_SCI0_SIMR3_IICSTPREQ_Pos     (2UL)      /*!< IICSTPREQ (Bit 2)                                     */
+ #define R_SCI0_SIMR3_IICSTPREQ_Msk     (0x4UL)    /*!< IICSTPREQ (Bitfield-Mask: 0x01)                       */
+ #define R_SCI0_SIMR3_IICRSTAREQ_Pos    (1UL)      /*!< IICRSTAREQ (Bit 1)                                    */
+ #define R_SCI0_SIMR3_IICRSTAREQ_Msk    (0x2UL)    /*!< IICRSTAREQ (Bitfield-Mask: 0x01)                      */
+ #define R_SCI0_SIMR3_IICSTAREQ_Pos     (0UL)      /*!< IICSTAREQ (Bit 0)                                     */
+ #define R_SCI0_SIMR3_IICSTAREQ_Msk     (0x1UL)    /*!< IICSTAREQ (Bitfield-Mask: 0x01)                       */
+/* =========================================================  SISR  ========================================================== */
+ #define R_SCI0_SISR_IICACKR_Pos        (0UL)      /*!< IICACKR (Bit 0)                                       */
+ #define R_SCI0_SISR_IICACKR_Msk        (0x1UL)    /*!< IICACKR (Bitfield-Mask: 0x01)                         */
+/* =========================================================  SPMR  ========================================================== */
+ #define R_SCI0_SPMR_CKPH_Pos           (7UL)      /*!< CKPH (Bit 7)                                          */
+ #define R_SCI0_SPMR_CKPH_Msk           (0x80UL)   /*!< CKPH (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SPMR_CKPOL_Pos          (6UL)      /*!< CKPOL (Bit 6)                                         */
+ #define R_SCI0_SPMR_CKPOL_Msk          (0x40UL)   /*!< CKPOL (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_SPMR_MFF_Pos            (4UL)      /*!< MFF (Bit 4)                                           */
+ #define R_SCI0_SPMR_MFF_Msk            (0x10UL)   /*!< MFF (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SPMR_CSTPEN_Pos         (3UL)      /*!< CSTPEN (Bit 3)                                        */
+ #define R_SCI0_SPMR_CSTPEN_Msk         (0x8UL)    /*!< CSTPEN (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_SPMR_MSS_Pos            (2UL)      /*!< MSS (Bit 2)                                           */
+ #define R_SCI0_SPMR_MSS_Msk            (0x4UL)    /*!< MSS (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SPMR_CTSE_Pos           (1UL)      /*!< CTSE (Bit 1)                                          */
+ #define R_SCI0_SPMR_CTSE_Msk           (0x2UL)    /*!< CTSE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SPMR_SSE_Pos            (0UL)      /*!< SSE (Bit 0)                                           */
+ #define R_SCI0_SPMR_SSE_Msk            (0x1UL)    /*!< SSE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TDRHL  ========================================================= */
+ #define R_SCI0_TDRHL_TDRHL_Pos         (0UL)      /*!< TDRHL (Bit 0)                                         */
+ #define R_SCI0_TDRHL_TDRHL_Msk         (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  FTDRHL  ========================================================= */
+ #define R_SCI0_FTDRHL_MPBT_Pos         (9UL)      /*!< MPBT (Bit 9)                                          */
+ #define R_SCI0_FTDRHL_MPBT_Msk         (0x200UL)  /*!< MPBT (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_FTDRHL_TDAT_Pos         (0UL)      /*!< TDAT (Bit 0)                                          */
+ #define R_SCI0_FTDRHL_TDAT_Msk         (0x1ffUL)  /*!< TDAT (Bitfield-Mask: 0x1ff)                           */
+/* =========================================================  FTDRH  ========================================================= */
+ #define R_SCI0_FTDRH_MPBT_Pos          (1UL)      /*!< MPBT (Bit 1)                                          */
+ #define R_SCI0_FTDRH_MPBT_Msk          (0x2UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_FTDRH_TDATH_Pos         (0UL)      /*!< TDATH (Bit 0)                                         */
+ #define R_SCI0_FTDRH_TDATH_Msk         (0x1UL)    /*!< TDATH (Bitfield-Mask: 0x01)                           */
+/* =========================================================  FTDRL  ========================================================= */
+ #define R_SCI0_FTDRL_TDATL_Pos         (0UL)      /*!< TDATL (Bit 0)                                         */
+ #define R_SCI0_FTDRL_TDATL_Msk         (0xffUL)   /*!< TDATL (Bitfield-Mask: 0xff)                           */
+/* =========================================================  RDRHL  ========================================================= */
+ #define R_SCI0_RDRHL_RDRHL_Pos         (0UL)      /*!< RDRHL (Bit 0)                                         */
+ #define R_SCI0_RDRHL_RDRHL_Msk         (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  FRDRHL  ========================================================= */
+ #define R_SCI0_FRDRHL_RDF_Pos          (14UL)     /*!< RDF (Bit 14)                                          */
+ #define R_SCI0_FRDRHL_RDF_Msk          (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRHL_ORER_Pos         (13UL)     /*!< ORER (Bit 13)                                         */
+ #define R_SCI0_FRDRHL_ORER_Msk         (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_FRDRHL_FER_Pos          (12UL)     /*!< FER (Bit 12)                                          */
+ #define R_SCI0_FRDRHL_FER_Msk          (0x1000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRHL_PER_Pos          (11UL)     /*!< PER (Bit 11)                                          */
+ #define R_SCI0_FRDRHL_PER_Msk          (0x800UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRHL_DR_Pos           (10UL)     /*!< DR (Bit 10)                                           */
+ #define R_SCI0_FRDRHL_DR_Msk           (0x400UL)  /*!< DR (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_FRDRHL_MPB_Pos          (9UL)      /*!< MPB (Bit 9)                                           */
+ #define R_SCI0_FRDRHL_MPB_Msk          (0x200UL)  /*!< MPB (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRHL_RDAT_Pos         (0UL)      /*!< RDAT (Bit 0)                                          */
+ #define R_SCI0_FRDRHL_RDAT_Msk         (0x1ffUL)  /*!< RDAT (Bitfield-Mask: 0x1ff)                           */
+/* =========================================================  FRDRH  ========================================================= */
+ #define R_SCI0_FRDRH_RDF_Pos           (6UL)      /*!< RDF (Bit 6)                                           */
+ #define R_SCI0_FRDRH_RDF_Msk           (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRH_ORER_Pos          (5UL)      /*!< ORER (Bit 5)                                          */
+ #define R_SCI0_FRDRH_ORER_Msk          (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_FRDRH_FER_Pos           (4UL)      /*!< FER (Bit 4)                                           */
+ #define R_SCI0_FRDRH_FER_Msk           (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRH_PER_Pos           (3UL)      /*!< PER (Bit 3)                                           */
+ #define R_SCI0_FRDRH_PER_Msk           (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRH_DR_Pos            (2UL)      /*!< DR (Bit 2)                                            */
+ #define R_SCI0_FRDRH_DR_Msk            (0x4UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_FRDRH_MPB_Pos           (1UL)      /*!< MPB (Bit 1)                                           */
+ #define R_SCI0_FRDRH_MPB_Msk           (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRH_RDATH_Pos         (0UL)      /*!< RDATH (Bit 0)                                         */
+ #define R_SCI0_FRDRH_RDATH_Msk         (0x1UL)    /*!< RDATH (Bitfield-Mask: 0x01)                           */
+/* =========================================================  FRDRL  ========================================================= */
+ #define R_SCI0_FRDRL_RDATL_Pos         (0UL)      /*!< RDATL (Bit 0)                                         */
+ #define R_SCI0_FRDRL_RDATL_Msk         (0xffUL)   /*!< RDATL (Bitfield-Mask: 0xff)                           */
+/* =========================================================  MDDR  ========================================================== */
+ #define R_SCI0_MDDR_MDDR_Pos           (0UL)      /*!< MDDR (Bit 0)                                          */
+ #define R_SCI0_MDDR_MDDR_Msk           (0xffUL)   /*!< MDDR (Bitfield-Mask: 0xff)                            */
+/* =========================================================  DCCR  ========================================================== */
+ #define R_SCI0_DCCR_DCME_Pos           (7UL)      /*!< DCME (Bit 7)                                          */
+ #define R_SCI0_DCCR_DCME_Msk           (0x80UL)   /*!< DCME (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_DCCR_IDSEL_Pos          (6UL)      /*!< IDSEL (Bit 6)                                         */
+ #define R_SCI0_DCCR_IDSEL_Msk          (0x40UL)   /*!< IDSEL (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_DCCR_DFER_Pos           (4UL)      /*!< DFER (Bit 4)                                          */
+ #define R_SCI0_DCCR_DFER_Msk           (0x10UL)   /*!< DFER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_DCCR_DPER_Pos           (3UL)      /*!< DPER (Bit 3)                                          */
+ #define R_SCI0_DCCR_DPER_Msk           (0x8UL)    /*!< DPER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_DCCR_DCMF_Pos           (0UL)      /*!< DCMF (Bit 0)                                          */
+ #define R_SCI0_DCCR_DCMF_Msk           (0x1UL)    /*!< DCMF (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  FCR  ========================================================== */
+ #define R_SCI0_FCR_RSTRG_Pos           (12UL)     /*!< RSTRG (Bit 12)                                        */
+ #define R_SCI0_FCR_RSTRG_Msk           (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f)                           */
+ #define R_SCI0_FCR_RTRG_Pos            (8UL)      /*!< RTRG (Bit 8)                                          */
+ #define R_SCI0_FCR_RTRG_Msk            (0xf00UL)  /*!< RTRG (Bitfield-Mask: 0x0f)                            */
+ #define R_SCI0_FCR_TTRG_Pos            (4UL)      /*!< TTRG (Bit 4)                                          */
+ #define R_SCI0_FCR_TTRG_Msk            (0xf0UL)   /*!< TTRG (Bitfield-Mask: 0x0f)                            */
+ #define R_SCI0_FCR_DRES_Pos            (3UL)      /*!< DRES (Bit 3)                                          */
+ #define R_SCI0_FCR_DRES_Msk            (0x8UL)    /*!< DRES (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_FCR_TFRST_Pos           (2UL)      /*!< TFRST (Bit 2)                                         */
+ #define R_SCI0_FCR_TFRST_Msk           (0x4UL)    /*!< TFRST (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_FCR_RFRST_Pos           (1UL)      /*!< RFRST (Bit 1)                                         */
+ #define R_SCI0_FCR_RFRST_Msk           (0x2UL)    /*!< RFRST (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_FCR_FM_Pos              (0UL)      /*!< FM (Bit 0)                                            */
+ #define R_SCI0_FCR_FM_Msk              (0x1UL)    /*!< FM (Bitfield-Mask: 0x01)                              */
+/* ==========================================================  FDR  ========================================================== */
+ #define R_SCI0_FDR_T_Pos               (8UL)      /*!< T (Bit 8)                                             */
+ #define R_SCI0_FDR_T_Msk               (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f)                               */
+ #define R_SCI0_FDR_R_Pos               (0UL)      /*!< R (Bit 0)                                             */
+ #define R_SCI0_FDR_R_Msk               (0x1fUL)   /*!< R (Bitfield-Mask: 0x1f)                               */
+/* ==========================================================  LSR  ========================================================== */
+ #define R_SCI0_LSR_PNUM_Pos            (8UL)      /*!< PNUM (Bit 8)                                          */
+ #define R_SCI0_LSR_PNUM_Msk            (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f)                            */
+ #define R_SCI0_LSR_FNUM_Pos            (2UL)      /*!< FNUM (Bit 2)                                          */
+ #define R_SCI0_LSR_FNUM_Msk            (0x7cUL)   /*!< FNUM (Bitfield-Mask: 0x1f)                            */
+ #define R_SCI0_LSR_ORER_Pos            (0UL)      /*!< ORER (Bit 0)                                          */
+ #define R_SCI0_LSR_ORER_Msk            (0x1UL)    /*!< ORER (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  CDR  ========================================================== */
+ #define R_SCI0_CDR_CMPD_Pos            (0UL)      /*!< CMPD (Bit 0)                                          */
+ #define R_SCI0_CDR_CMPD_Msk            (0x1ffUL)  /*!< CMPD (Bitfield-Mask: 0x1ff)                           */
+/* =========================================================  SPTR  ========================================================== */
+ #define R_SCI0_SPTR_SPB2IO_Pos         (2UL)      /*!< SPB2IO (Bit 2)                                        */
+ #define R_SCI0_SPTR_SPB2IO_Msk         (0x4UL)    /*!< SPB2IO (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_SPTR_SPB2DT_Pos         (1UL)      /*!< SPB2DT (Bit 1)                                        */
+ #define R_SCI0_SPTR_SPB2DT_Msk         (0x2UL)    /*!< SPB2DT (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_SPTR_RXDMON_Pos         (0UL)      /*!< RXDMON (Bit 0)                                        */
+ #define R_SCI0_SPTR_RXDMON_Msk         (0x1UL)    /*!< RXDMON (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_SPTR_RINV_Pos           (4UL)      /*!< RINV (Bit 4)                                          */
+ #define R_SCI0_SPTR_RINV_Msk           (0x10UL)   /*!< RINV (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SPTR_TINV_Pos           (5UL)      /*!< TINV (Bit 5)                                          */
+ #define R_SCI0_SPTR_TINV_Msk           (0x20UL)   /*!< TINV (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SPTR_ASEN_Pos           (6UL)      /*!< ASEN (Bit 6)                                          */
+ #define R_SCI0_SPTR_ASEN_Msk           (0x40UL)   /*!< ASEN (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SPTR_ATEN_Pos           (7UL)      /*!< ATEN (Bit 7)                                          */
+ #define R_SCI0_SPTR_ATEN_Msk           (0x80UL)   /*!< ATEN (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ACTR  ========================================================== */
+ #define R_SCI0_ACTR_AST_Pos            (0UL)      /*!< AST (Bit 0)                                           */
+ #define R_SCI0_ACTR_AST_Msk            (0x7UL)    /*!< AST (Bitfield-Mask: 0x07)                             */
+ #define R_SCI0_ACTR_AJD_Pos            (3UL)      /*!< AJD (Bit 3)                                           */
+ #define R_SCI0_ACTR_AJD_Msk            (0x8UL)    /*!< AJD (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_ACTR_ATT_Pos            (4UL)      /*!< ATT (Bit 4)                                           */
+ #define R_SCI0_ACTR_ATT_Msk            (0x70UL)   /*!< ATT (Bitfield-Mask: 0x07)                             */
+ #define R_SCI0_ACTR_AET_Pos            (7UL)      /*!< AET (Bit 7)                                           */
+ #define R_SCI0_ACTR_AET_Msk            (0x80UL)   /*!< AET (Bitfield-Mask: 0x01)                             */
+/* =========================================================  ESMER  ========================================================= */
+ #define R_SCI0_ESMER_ESME_Pos          (0UL)      /*!< ESME (Bit 0)                                          */
+ #define R_SCI0_ESMER_ESME_Msk          (0x1UL)    /*!< ESME (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  CR0  ========================================================== */
+ #define R_SCI0_CR0_SFSF_Pos            (1UL)      /*!< SFSF (Bit 1)                                          */
+ #define R_SCI0_CR0_SFSF_Msk            (0x2UL)    /*!< SFSF (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CR0_RXDSF_Pos           (2UL)      /*!< RXDSF (Bit 2)                                         */
+ #define R_SCI0_CR0_RXDSF_Msk           (0x4UL)    /*!< RXDSF (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_CR0_BRME_Pos            (3UL)      /*!< BRME (Bit 3)                                          */
+ #define R_SCI0_CR0_BRME_Msk            (0x8UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  CR1  ========================================================== */
+ #define R_SCI0_CR1_BFE_Pos             (0UL)      /*!< BFE (Bit 0)                                           */
+ #define R_SCI0_CR1_BFE_Msk             (0x1UL)    /*!< BFE (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_CR1_CF0RE_Pos           (1UL)      /*!< CF0RE (Bit 1)                                         */
+ #define R_SCI0_CR1_CF0RE_Msk           (0x2UL)    /*!< CF0RE (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_CR1_CF1DS_Pos           (2UL)      /*!< CF1DS (Bit 2)                                         */
+ #define R_SCI0_CR1_CF1DS_Msk           (0xcUL)    /*!< CF1DS (Bitfield-Mask: 0x03)                           */
+ #define R_SCI0_CR1_PIBE_Pos            (4UL)      /*!< PIBE (Bit 4)                                          */
+ #define R_SCI0_CR1_PIBE_Msk            (0x10UL)   /*!< PIBE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_CR1_PIBS_Pos            (5UL)      /*!< PIBS (Bit 5)                                          */
+ #define R_SCI0_CR1_PIBS_Msk            (0xe0UL)   /*!< PIBS (Bitfield-Mask: 0x07)                            */
+/* ==========================================================  CR2  ========================================================== */
+ #define R_SCI0_CR2_DFCS_Pos            (0UL)      /*!< DFCS (Bit 0)                                          */
+ #define R_SCI0_CR2_DFCS_Msk            (0x7UL)    /*!< DFCS (Bitfield-Mask: 0x07)                            */
+ #define R_SCI0_CR2_BCCS_Pos            (4UL)      /*!< BCCS (Bit 4)                                          */
+ #define R_SCI0_CR2_BCCS_Msk            (0x30UL)   /*!< BCCS (Bitfield-Mask: 0x03)                            */
+ #define R_SCI0_CR2_RTS_Pos             (6UL)      /*!< RTS (Bit 6)                                           */
+ #define R_SCI0_CR2_RTS_Msk             (0xc0UL)   /*!< RTS (Bitfield-Mask: 0x03)                             */
+/* ==========================================================  CR3  ========================================================== */
+ #define R_SCI0_CR3_SDST_Pos            (0UL)      /*!< SDST (Bit 0)                                          */
+ #define R_SCI0_CR3_SDST_Msk            (0x1UL)    /*!< SDST (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  PCR  ========================================================== */
+ #define R_SCI0_PCR_TXDXPS_Pos          (0UL)      /*!< TXDXPS (Bit 0)                                        */
+ #define R_SCI0_PCR_TXDXPS_Msk          (0x1UL)    /*!< TXDXPS (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_PCR_RXDXPS_Pos          (1UL)      /*!< RXDXPS (Bit 1)                                        */
+ #define R_SCI0_PCR_RXDXPS_Msk          (0x2UL)    /*!< RXDXPS (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_PCR_SHARPS_Pos          (4UL)      /*!< SHARPS (Bit 4)                                        */
+ #define R_SCI0_PCR_SHARPS_Msk          (0x10UL)   /*!< SHARPS (Bitfield-Mask: 0x01)                          */
+/* ==========================================================  ICR  ========================================================== */
+ #define R_SCI0_ICR_BFDIE_Pos           (0UL)      /*!< BFDIE (Bit 0)                                         */
+ #define R_SCI0_ICR_BFDIE_Msk           (0x1UL)    /*!< BFDIE (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_ICR_CF0MIE_Pos          (1UL)      /*!< CF0MIE (Bit 1)                                        */
+ #define R_SCI0_ICR_CF0MIE_Msk          (0x2UL)    /*!< CF0MIE (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_ICR_CF1MIE_Pos          (2UL)      /*!< CF1MIE (Bit 2)                                        */
+ #define R_SCI0_ICR_CF1MIE_Msk          (0x4UL)    /*!< CF1MIE (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_ICR_PIBDIE_Pos          (3UL)      /*!< PIBDIE (Bit 3)                                        */
+ #define R_SCI0_ICR_PIBDIE_Msk          (0x8UL)    /*!< PIBDIE (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_ICR_BCDIE_Pos           (4UL)      /*!< BCDIE (Bit 4)                                         */
+ #define R_SCI0_ICR_BCDIE_Msk           (0x10UL)   /*!< BCDIE (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_ICR_AEDIE_Pos           (5UL)      /*!< AEDIE (Bit 5)                                         */
+ #define R_SCI0_ICR_AEDIE_Msk           (0x20UL)   /*!< AEDIE (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  STR  ========================================================== */
+ #define R_SCI0_STR_BFDF_Pos            (0UL)      /*!< BFDF (Bit 0)                                          */
+ #define R_SCI0_STR_BFDF_Msk            (0x1UL)    /*!< BFDF (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_STR_CF0MF_Pos           (1UL)      /*!< CF0MF (Bit 1)                                         */
+ #define R_SCI0_STR_CF0MF_Msk           (0x2UL)    /*!< CF0MF (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_STR_CF1MF_Pos           (2UL)      /*!< CF1MF (Bit 2)                                         */
+ #define R_SCI0_STR_CF1MF_Msk           (0x4UL)    /*!< CF1MF (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_STR_PIBDF_Pos           (3UL)      /*!< PIBDF (Bit 3)                                         */
+ #define R_SCI0_STR_PIBDF_Msk           (0x8UL)    /*!< PIBDF (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_STR_BCDF_Pos            (4UL)      /*!< BCDF (Bit 4)                                          */
+ #define R_SCI0_STR_BCDF_Msk            (0x10UL)   /*!< BCDF (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_STR_AEDF_Pos            (5UL)      /*!< AEDF (Bit 5)                                          */
+ #define R_SCI0_STR_AEDF_Msk            (0x20UL)   /*!< AEDF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  STCR  ========================================================== */
+ #define R_SCI0_STCR_BFDCL_Pos          (0UL)      /*!< BFDCL (Bit 0)                                         */
+ #define R_SCI0_STCR_BFDCL_Msk          (0x1UL)    /*!< BFDCL (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_STCR_CF0MCL_Pos         (1UL)      /*!< CF0MCL (Bit 1)                                        */
+ #define R_SCI0_STCR_CF0MCL_Msk         (0x2UL)    /*!< CF0MCL (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_STCR_CF1MCL_Pos         (2UL)      /*!< CF1MCL (Bit 2)                                        */
+ #define R_SCI0_STCR_CF1MCL_Msk         (0x4UL)    /*!< CF1MCL (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_STCR_PIBDCL_Pos         (3UL)      /*!< PIBDCL (Bit 3)                                        */
+ #define R_SCI0_STCR_PIBDCL_Msk         (0x8UL)    /*!< PIBDCL (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_STCR_BCDCL_Pos          (4UL)      /*!< BCDCL (Bit 4)                                         */
+ #define R_SCI0_STCR_BCDCL_Msk          (0x10UL)   /*!< BCDCL (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_STCR_AEDCL_Pos          (5UL)      /*!< AEDCL (Bit 5)                                         */
+ #define R_SCI0_STCR_AEDCL_Msk          (0x20UL)   /*!< AEDCL (Bitfield-Mask: 0x01)                           */
+/* =========================================================  CF0DR  ========================================================= */
+/* =========================================================  CF0CR  ========================================================= */
+ #define R_SCI0_CF0CR_CF0CE0_Pos        (0UL)      /*!< CF0CE0 (Bit 0)                                        */
+ #define R_SCI0_CF0CR_CF0CE0_Msk        (0x1UL)    /*!< CF0CE0 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF0CR_CF0CE1_Pos        (1UL)      /*!< CF0CE1 (Bit 1)                                        */
+ #define R_SCI0_CF0CR_CF0CE1_Msk        (0x2UL)    /*!< CF0CE1 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF0CR_CF0CE2_Pos        (2UL)      /*!< CF0CE2 (Bit 2)                                        */
+ #define R_SCI0_CF0CR_CF0CE2_Msk        (0x4UL)    /*!< CF0CE2 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF0CR_CF0CE3_Pos        (3UL)      /*!< CF0CE3 (Bit 3)                                        */
+ #define R_SCI0_CF0CR_CF0CE3_Msk        (0x8UL)    /*!< CF0CE3 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF0CR_CF0CE4_Pos        (4UL)      /*!< CF0CE4 (Bit 4)                                        */
+ #define R_SCI0_CF0CR_CF0CE4_Msk        (0x10UL)   /*!< CF0CE4 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF0CR_CF0CE5_Pos        (5UL)      /*!< CF0CE5 (Bit 5)                                        */
+ #define R_SCI0_CF0CR_CF0CE5_Msk        (0x20UL)   /*!< CF0CE5 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF0CR_CF0CE6_Pos        (6UL)      /*!< CF0CE6 (Bit 6)                                        */
+ #define R_SCI0_CF0CR_CF0CE6_Msk        (0x40UL)   /*!< CF0CE6 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF0CR_CF0CE7_Pos        (7UL)      /*!< CF0CE7 (Bit 7)                                        */
+ #define R_SCI0_CF0CR_CF0CE7_Msk        (0x80UL)   /*!< CF0CE7 (Bitfield-Mask: 0x01)                          */
+/* =========================================================  CF0RR  ========================================================= */
+/* ========================================================  PCF1DR  ========================================================= */
+/* ========================================================  SCF1DR  ========================================================= */
+/* =========================================================  CF1CR  ========================================================= */
+ #define R_SCI0_CF1CR_CF1CE0_Pos        (0UL)    /*!< CF1CE0 (Bit 0)                                        */
+ #define R_SCI0_CF1CR_CF1CE0_Msk        (0x1UL)  /*!< CF1CE0 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF1CR_CF1CE1_Pos        (1UL)    /*!< CF1CE1 (Bit 1)                                        */
+ #define R_SCI0_CF1CR_CF1CE1_Msk        (0x2UL)  /*!< CF1CE1 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF1CR_CF1CE2_Pos        (2UL)    /*!< CF1CE2 (Bit 2)                                        */
+ #define R_SCI0_CF1CR_CF1CE2_Msk        (0x4UL)  /*!< CF1CE2 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF1CR_CF1CE3_Pos        (3UL)    /*!< CF1CE3 (Bit 3)                                        */
+ #define R_SCI0_CF1CR_CF1CE3_Msk        (0x8UL)  /*!< CF1CE3 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF1CR_CF1CE4_Pos        (4UL)    /*!< CF1CE4 (Bit 4)                                        */
+ #define R_SCI0_CF1CR_CF1CE4_Msk        (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF1CR_CF1CE5_Pos        (5UL)    /*!< CF1CE5 (Bit 5)                                        */
+ #define R_SCI0_CF1CR_CF1CE5_Msk        (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF1CR_CF1CE6_Pos        (6UL)    /*!< CF1CE6 (Bit 6)                                        */
+ #define R_SCI0_CF1CR_CF1CE6_Msk        (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_CF1CR_CF1CE7_Pos        (7UL)    /*!< CF1CE7 (Bit 7)                                        */
+ #define R_SCI0_CF1CR_CF1CE7_Msk        (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01)                          */
+/* =========================================================  CF1RR  ========================================================= */
+/* ==========================================================  TCR  ========================================================== */
+ #define R_SCI0_TCR_TCST_Pos            (0UL)    /*!< TCST (Bit 0)                                          */
+ #define R_SCI0_TCR_TCST_Msk            (0x1UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  TMR  ========================================================== */
+ #define R_SCI0_TMR_TOMS_Pos            (0UL)    /*!< TOMS (Bit 0)                                          */
+ #define R_SCI0_TMR_TOMS_Msk            (0x3UL)  /*!< TOMS (Bitfield-Mask: 0x03)                            */
+ #define R_SCI0_TMR_TWRC_Pos            (3UL)    /*!< TWRC (Bit 3)                                          */
+ #define R_SCI0_TMR_TWRC_Msk            (0x8UL)  /*!< TWRC (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_TMR_TCSS_Pos            (4UL)    /*!< TCSS (Bit 4)                                          */
+ #define R_SCI0_TMR_TCSS_Msk            (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07)                            */
+/* =========================================================  TPRE  ========================================================== */
+/* =========================================================  TCNT  ========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SPI0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SPCR  ========================================================== */
+ #define R_SPI0_SPCR_SPRIE_Pos      (7UL)    /*!< SPRIE (Bit 7)                                         */
+ #define R_SPI0_SPCR_SPRIE_Msk      (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR_SPE_Pos        (6UL)    /*!< SPE (Bit 6)                                           */
+ #define R_SPI0_SPCR_SPE_Msk        (0x40UL) /*!< SPE (Bitfield-Mask: 0x01)                             */
+ #define R_SPI0_SPCR_SPTIE_Pos      (5UL)    /*!< SPTIE (Bit 5)                                         */
+ #define R_SPI0_SPCR_SPTIE_Msk      (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR_SPEIE_Pos      (4UL)    /*!< SPEIE (Bit 4)                                         */
+ #define R_SPI0_SPCR_SPEIE_Msk      (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR_MSTR_Pos       (3UL)    /*!< MSTR (Bit 3)                                          */
+ #define R_SPI0_SPCR_MSTR_Msk       (0x8UL)  /*!< MSTR (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR_MODFEN_Pos     (2UL)    /*!< MODFEN (Bit 2)                                        */
+ #define R_SPI0_SPCR_MODFEN_Msk     (0x4UL)  /*!< MODFEN (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCR_TXMD_Pos       (1UL)    /*!< TXMD (Bit 1)                                          */
+ #define R_SPI0_SPCR_TXMD_Msk       (0x2UL)  /*!< TXMD (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR_SPMS_Pos       (0UL)    /*!< SPMS (Bit 0)                                          */
+ #define R_SPI0_SPCR_SPMS_Msk       (0x1UL)  /*!< SPMS (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SSLP  ========================================================== */
+ #define R_SPI0_SSLP_SSL3P_Pos      (3UL)    /*!< SSL3P (Bit 3)                                         */
+ #define R_SPI0_SSLP_SSL3P_Msk      (0x8UL)  /*!< SSL3P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL2P_Pos      (2UL)    /*!< SSL2P (Bit 2)                                         */
+ #define R_SPI0_SSLP_SSL2P_Msk      (0x4UL)  /*!< SSL2P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL1P_Pos      (1UL)    /*!< SSL1P (Bit 1)                                         */
+ #define R_SPI0_SSLP_SSL1P_Msk      (0x2UL)  /*!< SSL1P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL0P_Pos      (0UL)    /*!< SSL0P (Bit 0)                                         */
+ #define R_SPI0_SSLP_SSL0P_Msk      (0x1UL)  /*!< SSL0P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL4P_Pos      (4UL)    /*!< SSL4P (Bit 4)                                         */
+ #define R_SPI0_SSLP_SSL4P_Msk      (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL5P_Pos      (5UL)    /*!< SSL5P (Bit 5)                                         */
+ #define R_SPI0_SSLP_SSL5P_Msk      (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL6P_Pos      (6UL)    /*!< SSL6P (Bit 6)                                         */
+ #define R_SPI0_SSLP_SSL6P_Msk      (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL7P_Pos      (7UL)    /*!< SSL7P (Bit 7)                                         */
+ #define R_SPI0_SSLP_SSL7P_Msk      (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SPPCR  ========================================================= */
+ #define R_SPI0_SPPCR_MOIFE_Pos     (5UL)    /*!< MOIFE (Bit 5)                                         */
+ #define R_SPI0_SPPCR_MOIFE_Msk     (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPPCR_MOIFV_Pos     (4UL)    /*!< MOIFV (Bit 4)                                         */
+ #define R_SPI0_SPPCR_MOIFV_Msk     (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPPCR_SPLP2_Pos     (1UL)    /*!< SPLP2 (Bit 1)                                         */
+ #define R_SPI0_SPPCR_SPLP2_Msk     (0x2UL)  /*!< SPLP2 (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPPCR_SPLP_Pos      (0UL)    /*!< SPLP (Bit 0)                                          */
+ #define R_SPI0_SPPCR_SPLP_Msk      (0x1UL)  /*!< SPLP (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SPSR  ========================================================== */
+ #define R_SPI0_SPSR_SPRF_Pos       (7UL)    /*!< SPRF (Bit 7)                                          */
+ #define R_SPI0_SPSR_SPRF_Msk       (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_SPTEF_Pos      (5UL)    /*!< SPTEF (Bit 5)                                         */
+ #define R_SPI0_SPSR_SPTEF_Msk      (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSR_UDRF_Pos       (4UL)    /*!< UDRF (Bit 4)                                          */
+ #define R_SPI0_SPSR_UDRF_Msk       (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_PERF_Pos       (3UL)    /*!< PERF (Bit 3)                                          */
+ #define R_SPI0_SPSR_PERF_Msk       (0x8UL)  /*!< PERF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_MODF_Pos       (2UL)    /*!< MODF (Bit 2)                                          */
+ #define R_SPI0_SPSR_MODF_Msk       (0x4UL)  /*!< MODF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_IDLNF_Pos      (1UL)    /*!< IDLNF (Bit 1)                                         */
+ #define R_SPI0_SPSR_IDLNF_Msk      (0x2UL)  /*!< IDLNF (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSR_OVRF_Pos       (0UL)    /*!< OVRF (Bit 0)                                          */
+ #define R_SPI0_SPSR_OVRF_Msk       (0x1UL)  /*!< OVRF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_CENDF_Pos      (6UL)    /*!< CENDF (Bit 6)                                         */
+ #define R_SPI0_SPSR_CENDF_Msk      (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SPDR  ========================================================== */
+/* ========================================================  SPDR_HA  ======================================================== */
+/* ========================================================  SPDR_BY  ======================================================== */
+/* =========================================================  SPSCR  ========================================================= */
+ #define R_SPI0_SPSCR_SPSLN_Pos     (0UL)      /*!< SPSLN (Bit 0)                                         */
+ #define R_SPI0_SPSCR_SPSLN_Msk     (0x7UL)    /*!< SPSLN (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SPBR  ========================================================== */
+ #define R_SPI0_SPBR_SPR_Pos        (0UL)      /*!< SPR (Bit 0)                                           */
+ #define R_SPI0_SPBR_SPR_Msk        (0xffUL)   /*!< SPR (Bitfield-Mask: 0xff)                             */
+/* =========================================================  SPDCR  ========================================================= */
+ #define R_SPI0_SPDCR_SPBYT_Pos     (6UL)      /*!< SPBYT (Bit 6)                                         */
+ #define R_SPI0_SPDCR_SPBYT_Msk     (0x40UL)   /*!< SPBYT (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPDCR_SPLW_Pos      (5UL)      /*!< SPLW (Bit 5)                                          */
+ #define R_SPI0_SPDCR_SPLW_Msk      (0x20UL)   /*!< SPLW (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPDCR_SPRDTD_Pos    (4UL)      /*!< SPRDTD (Bit 4)                                        */
+ #define R_SPI0_SPDCR_SPRDTD_Msk    (0x10UL)   /*!< SPRDTD (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPDCR_SPFC_Pos      (0UL)      /*!< SPFC (Bit 0)                                          */
+ #define R_SPI0_SPDCR_SPFC_Msk      (0x3UL)    /*!< SPFC (Bitfield-Mask: 0x03)                            */
+ #define R_SPI0_SPDCR_SLSEL_Pos     (2UL)      /*!< SLSEL (Bit 2)                                         */
+ #define R_SPI0_SPDCR_SLSEL_Msk     (0xcUL)    /*!< SLSEL (Bitfield-Mask: 0x03)                           */
+/* =========================================================  SPCKD  ========================================================= */
+ #define R_SPI0_SPCKD_SCKDL_Pos     (0UL)      /*!< SCKDL (Bit 0)                                         */
+ #define R_SPI0_SPCKD_SCKDL_Msk     (0x7UL)    /*!< SCKDL (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SSLND  ========================================================= */
+ #define R_SPI0_SSLND_SLNDL_Pos     (0UL)      /*!< SLNDL (Bit 0)                                         */
+ #define R_SPI0_SSLND_SLNDL_Msk     (0x7UL)    /*!< SLNDL (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SPND  ========================================================== */
+ #define R_SPI0_SPND_SPNDL_Pos      (0UL)      /*!< SPNDL (Bit 0)                                         */
+ #define R_SPI0_SPND_SPNDL_Msk      (0x7UL)    /*!< SPNDL (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SPCR2  ========================================================= */
+ #define R_SPI0_SPCR2_SCKASE_Pos    (4UL)      /*!< SCKASE (Bit 4)                                        */
+ #define R_SPI0_SPCR2_SCKASE_Msk    (0x10UL)   /*!< SCKASE (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCR2_PTE_Pos       (3UL)      /*!< PTE (Bit 3)                                           */
+ #define R_SPI0_SPCR2_PTE_Msk       (0x8UL)    /*!< PTE (Bitfield-Mask: 0x01)                             */
+ #define R_SPI0_SPCR2_SPIIE_Pos     (2UL)      /*!< SPIIE (Bit 2)                                         */
+ #define R_SPI0_SPCR2_SPIIE_Msk     (0x4UL)    /*!< SPIIE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR2_SPOE_Pos      (1UL)      /*!< SPOE (Bit 1)                                          */
+ #define R_SPI0_SPCR2_SPOE_Msk      (0x2UL)    /*!< SPOE (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR2_SPPE_Pos      (0UL)      /*!< SPPE (Bit 0)                                          */
+ #define R_SPI0_SPCR2_SPPE_Msk      (0x1UL)    /*!< SPPE (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR2_SPTDDL_Pos    (5UL)      /*!< SPTDDL (Bit 5)                                        */
+ #define R_SPI0_SPCR2_SPTDDL_Msk    (0xe0UL)   /*!< SPTDDL (Bitfield-Mask: 0x07)                          */
+/* =========================================================  SPCMD  ========================================================= */
+ #define R_SPI0_SPCMD_SCKDEN_Pos    (15UL)     /*!< SCKDEN (Bit 15)                                       */
+ #define R_SPI0_SPCMD_SCKDEN_Msk    (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCMD_SLNDEN_Pos    (14UL)     /*!< SLNDEN (Bit 14)                                       */
+ #define R_SPI0_SPCMD_SLNDEN_Msk    (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCMD_SPNDEN_Pos    (13UL)     /*!< SPNDEN (Bit 13)                                       */
+ #define R_SPI0_SPCMD_SPNDEN_Msk    (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCMD_LSBF_Pos      (12UL)     /*!< LSBF (Bit 12)                                         */
+ #define R_SPI0_SPCMD_LSBF_Msk      (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCMD_SPB_Pos       (8UL)      /*!< SPB (Bit 8)                                           */
+ #define R_SPI0_SPCMD_SPB_Msk       (0xf00UL)  /*!< SPB (Bitfield-Mask: 0x0f)                             */
+ #define R_SPI0_SPCMD_SSLKP_Pos     (7UL)      /*!< SSLKP (Bit 7)                                         */
+ #define R_SPI0_SPCMD_SSLKP_Msk     (0x80UL)   /*!< SSLKP (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCMD_SSLA_Pos      (4UL)      /*!< SSLA (Bit 4)                                          */
+ #define R_SPI0_SPCMD_SSLA_Msk      (0x70UL)   /*!< SSLA (Bitfield-Mask: 0x07)                            */
+ #define R_SPI0_SPCMD_BRDV_Pos      (2UL)      /*!< BRDV (Bit 2)                                          */
+ #define R_SPI0_SPCMD_BRDV_Msk      (0xcUL)    /*!< BRDV (Bitfield-Mask: 0x03)                            */
+ #define R_SPI0_SPCMD_CPOL_Pos      (1UL)      /*!< CPOL (Bit 1)                                          */
+ #define R_SPI0_SPCMD_CPOL_Msk      (0x2UL)    /*!< CPOL (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCMD_CPHA_Pos      (0UL)      /*!< CPHA (Bit 0)                                          */
+ #define R_SPI0_SPCMD_CPHA_Msk      (0x1UL)    /*!< CPHA (Bitfield-Mask: 0x01)                            */
+/* ========================================================  SPDCR2  ========================================================= */
+ #define R_SPI0_SPDCR2_BYSW_Pos     (0UL)      /*!< BYSW (Bit 0)                                          */
+ #define R_SPI0_SPDCR2_BYSW_Msk     (0x1UL)    /*!< BYSW (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPDCR2_SINV_Pos     (1UL)      /*!< SINV (Bit 1)                                          */
+ #define R_SPI0_SPDCR2_SINV_Msk     (0x2UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SPSSR  ========================================================= */
+ #define R_SPI0_SPSSR_SPCP_Pos      (0UL)      /*!< SPCP (Bit 0)                                          */
+ #define R_SPI0_SPSSR_SPCP_Msk      (0x7UL)    /*!< SPCP (Bitfield-Mask: 0x07)                            */
+ #define R_SPI0_SPSSR_SPECM_Pos     (4UL)      /*!< SPECM (Bit 4)                                         */
+ #define R_SPI0_SPSSR_SPECM_Msk     (0x70UL)   /*!< SPECM (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SPCR3  ========================================================= */
+ #define R_SPI0_SPCR3_ETXMD_Pos     (0UL)      /*!< ETXMD (Bit 0)                                         */
+ #define R_SPI0_SPCR3_ETXMD_Msk     (0x1UL)    /*!< ETXMD (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR3_BFDS_Pos      (1UL)      /*!< BFDS (Bit 1)                                          */
+ #define R_SPI0_SPCR3_BFDS_Msk      (0x2UL)    /*!< BFDS (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR3_CENDIE_Pos    (4UL)      /*!< CENDIE (Bit 4)                                        */
+ #define R_SPI0_SPCR3_CENDIE_Msk    (0x10UL)   /*!< CENDIE (Bitfield-Mask: 0x01)                          */
+/* =========================================================  SPPR  ========================================================== */
+ #define R_SPI0_SPPR_BUFWID_Pos     (4UL)      /*!< BUFWID (Bit 4)                                        */
+ #define R_SPI0_SPPR_BUFWID_Msk     (0x10UL)   /*!< BUFWID (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPPR_BUFNUM_Pos     (8UL)      /*!< BUFNUM (Bit 8)                                        */
+ #define R_SPI0_SPPR_BUFNUM_Msk     (0x700UL)  /*!< BUFNUM (Bitfield-Mask: 0x07)                          */
+ #define R_SPI0_SPPR_CMDNUM_Pos     (12UL)     /*!< CMDNUM (Bit 12)                                       */
+ #define R_SPI0_SPPR_CMDNUM_Msk     (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f)                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SRAM                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  PARIOAD  ======================================================== */
+ #define R_SRAM_PARIOAD_OAD_Pos            (0UL)    /*!< OAD (Bit 0)                                           */
+ #define R_SRAM_PARIOAD_OAD_Msk            (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
+/* =======================================================  SRAMPRCR  ======================================================== */
+ #define R_SRAM_SRAMPRCR_KW_Pos            (1UL)    /*!< KW (Bit 1)                                            */
+ #define R_SRAM_SRAMPRCR_KW_Msk            (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
+ #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos      (0UL)    /*!< SRAMPRCR (Bit 0)                                      */
+ #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk      (0x1UL)  /*!< SRAMPRCR (Bitfield-Mask: 0x01)                        */
+/* =======================================================  SRAMWTSC  ======================================================== */
+/* ========================================================  ECCMODE  ======================================================== */
+ #define R_SRAM_ECCMODE_ECCMOD_Pos         (0UL)    /*!< ECCMOD (Bit 0)                                        */
+ #define R_SRAM_ECCMODE_ECCMOD_Msk         (0x3UL)  /*!< ECCMOD (Bitfield-Mask: 0x03)                          */
+/* ========================================================  ECC2STS  ======================================================== */
+ #define R_SRAM_ECC2STS_ECC2ERR_Pos        (0UL)    /*!< ECC2ERR (Bit 0)                                       */
+ #define R_SRAM_ECC2STS_ECC2ERR_Msk        (0x1UL)  /*!< ECC2ERR (Bitfield-Mask: 0x01)                         */
+/* =======================================================  ECC1STSEN  ======================================================= */
+ #define R_SRAM_ECC1STSEN_E1STSEN_Pos      (0UL)    /*!< E1STSEN (Bit 0)                                       */
+ #define R_SRAM_ECC1STSEN_E1STSEN_Msk      (0x1UL)  /*!< E1STSEN (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ECC1STS  ======================================================== */
+ #define R_SRAM_ECC1STS_ECC1ERR_Pos        (0UL)    /*!< ECC1ERR (Bit 0)                                       */
+ #define R_SRAM_ECC1STS_ECC1ERR_Msk        (0x1UL)  /*!< ECC1ERR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ECCPRCR  ======================================================== */
+ #define R_SRAM_ECCPRCR_KW_Pos             (1UL)    /*!< KW (Bit 1)                                            */
+ #define R_SRAM_ECCPRCR_KW_Msk             (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
+ #define R_SRAM_ECCPRCR_ECCPRCR_Pos        (0UL)    /*!< ECCPRCR (Bit 0)                                       */
+ #define R_SRAM_ECCPRCR_ECCPRCR_Msk        (0x1UL)  /*!< ECCPRCR (Bitfield-Mask: 0x01)                         */
+/* =======================================================  ECCPRCR2  ======================================================== */
+ #define R_SRAM_ECCPRCR2_KW2_Pos           (1UL)    /*!< KW2 (Bit 1)                                           */
+ #define R_SRAM_ECCPRCR2_KW2_Msk           (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f)                             */
+ #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos      (0UL)    /*!< ECCPRCR2 (Bit 0)                                      */
+ #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk      (0x1UL)  /*!< ECCPRCR2 (Bitfield-Mask: 0x01)                        */
+/* ========================================================  ECCETST  ======================================================== */
+ #define R_SRAM_ECCETST_TSTBYP_Pos         (0UL)    /*!< TSTBYP (Bit 0)                                        */
+ #define R_SRAM_ECCETST_TSTBYP_Msk         (0x1UL)  /*!< TSTBYP (Bitfield-Mask: 0x01)                          */
+/* ========================================================  ECCOAD  ========================================================= */
+ #define R_SRAM_ECCOAD_OAD_Pos             (0UL)    /*!< OAD (Bit 0)                                           */
+ #define R_SRAM_ECCOAD_OAD_Msk             (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
+/* =======================================================  SRAMPRCR2  ======================================================= */
+ #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos    (0UL)    /*!< SRAMPRCR2 (Bit 0)                                     */
+ #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk    (0x1UL)  /*!< SRAMPRCR2 (Bitfield-Mask: 0x01)                       */
+ #define R_SRAM_SRAMPRCR2_KW_Pos           (1UL)    /*!< KW (Bit 1)                                            */
+ #define R_SRAM_SRAMPRCR2_KW_Msk           (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SSI0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SSICR  ========================================================= */
+ #define R_SSI0_SSICR_CKS_Pos          (30UL)         /*!< CKS (Bit 30)                                          */
+ #define R_SSI0_SSICR_CKS_Msk          (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSICR_TUIEN_Pos        (29UL)         /*!< TUIEN (Bit 29)                                        */
+ #define R_SSI0_SSICR_TUIEN_Msk        (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSICR_TOIEN_Pos        (28UL)         /*!< TOIEN (Bit 28)                                        */
+ #define R_SSI0_SSICR_TOIEN_Msk        (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSICR_RUIEN_Pos        (27UL)         /*!< RUIEN (Bit 27)                                        */
+ #define R_SSI0_SSICR_RUIEN_Msk        (0x8000000UL)  /*!< RUIEN (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSICR_ROIEN_Pos        (26UL)         /*!< ROIEN (Bit 26)                                        */
+ #define R_SSI0_SSICR_ROIEN_Msk        (0x4000000UL)  /*!< ROIEN (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSICR_IIEN_Pos         (25UL)         /*!< IIEN (Bit 25)                                         */
+ #define R_SSI0_SSICR_IIEN_Msk         (0x2000000UL)  /*!< IIEN (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSICR_FRM_Pos          (22UL)         /*!< FRM (Bit 22)                                          */
+ #define R_SSI0_SSICR_FRM_Msk          (0xc00000UL)   /*!< FRM (Bitfield-Mask: 0x03)                             */
+ #define R_SSI0_SSICR_DWL_Pos          (19UL)         /*!< DWL (Bit 19)                                          */
+ #define R_SSI0_SSICR_DWL_Msk          (0x380000UL)   /*!< DWL (Bitfield-Mask: 0x07)                             */
+ #define R_SSI0_SSICR_SWL_Pos          (16UL)         /*!< SWL (Bit 16)                                          */
+ #define R_SSI0_SSICR_SWL_Msk          (0x70000UL)    /*!< SWL (Bitfield-Mask: 0x07)                             */
+ #define R_SSI0_SSICR_MST_Pos          (14UL)         /*!< MST (Bit 14)                                          */
+ #define R_SSI0_SSICR_MST_Msk          (0x4000UL)     /*!< MST (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSICR_BCKP_Pos         (13UL)         /*!< BCKP (Bit 13)                                         */
+ #define R_SSI0_SSICR_BCKP_Msk         (0x2000UL)     /*!< BCKP (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSICR_LRCKP_Pos        (12UL)         /*!< LRCKP (Bit 12)                                        */
+ #define R_SSI0_SSICR_LRCKP_Msk        (0x1000UL)     /*!< LRCKP (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSICR_SPDP_Pos         (11UL)         /*!< SPDP (Bit 11)                                         */
+ #define R_SSI0_SSICR_SPDP_Msk         (0x800UL)      /*!< SPDP (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSICR_SDTA_Pos         (10UL)         /*!< SDTA (Bit 10)                                         */
+ #define R_SSI0_SSICR_SDTA_Msk         (0x400UL)      /*!< SDTA (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSICR_PDTA_Pos         (9UL)          /*!< PDTA (Bit 9)                                          */
+ #define R_SSI0_SSICR_PDTA_Msk         (0x200UL)      /*!< PDTA (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSICR_DEL_Pos          (8UL)          /*!< DEL (Bit 8)                                           */
+ #define R_SSI0_SSICR_DEL_Msk          (0x100UL)      /*!< DEL (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSICR_CKDV_Pos         (4UL)          /*!< CKDV (Bit 4)                                          */
+ #define R_SSI0_SSICR_CKDV_Msk         (0xf0UL)       /*!< CKDV (Bitfield-Mask: 0x0f)                            */
+ #define R_SSI0_SSICR_MUEN_Pos         (3UL)          /*!< MUEN (Bit 3)                                          */
+ #define R_SSI0_SSICR_MUEN_Msk         (0x8UL)        /*!< MUEN (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSICR_TEN_Pos          (1UL)          /*!< TEN (Bit 1)                                           */
+ #define R_SSI0_SSICR_TEN_Msk          (0x2UL)        /*!< TEN (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSICR_REN_Pos          (0UL)          /*!< REN (Bit 0)                                           */
+ #define R_SSI0_SSICR_REN_Msk          (0x1UL)        /*!< REN (Bitfield-Mask: 0x01)                             */
+/* =========================================================  SSISR  ========================================================= */
+ #define R_SSI0_SSISR_TUIRQ_Pos        (29UL)         /*!< TUIRQ (Bit 29)                                        */
+ #define R_SSI0_SSISR_TUIRQ_Msk        (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSISR_TOIRQ_Pos        (28UL)         /*!< TOIRQ (Bit 28)                                        */
+ #define R_SSI0_SSISR_TOIRQ_Msk        (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSISR_RUIRQ_Pos        (27UL)         /*!< RUIRQ (Bit 27)                                        */
+ #define R_SSI0_SSISR_RUIRQ_Msk        (0x8000000UL)  /*!< RUIRQ (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSISR_ROIRQ_Pos        (26UL)         /*!< ROIRQ (Bit 26)                                        */
+ #define R_SSI0_SSISR_ROIRQ_Msk        (0x4000000UL)  /*!< ROIRQ (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSISR_IIRQ_Pos         (25UL)         /*!< IIRQ (Bit 25)                                         */
+ #define R_SSI0_SSISR_IIRQ_Msk         (0x2000000UL)  /*!< IIRQ (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSISR_TCHNO_Pos        (5UL)          /*!< TCHNO (Bit 5)                                         */
+ #define R_SSI0_SSISR_TCHNO_Msk        (0x60UL)       /*!< TCHNO (Bitfield-Mask: 0x03)                           */
+ #define R_SSI0_SSISR_TSWNO_Pos        (4UL)          /*!< TSWNO (Bit 4)                                         */
+ #define R_SSI0_SSISR_TSWNO_Msk        (0x10UL)       /*!< TSWNO (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSISR_RCHNO_Pos        (2UL)          /*!< RCHNO (Bit 2)                                         */
+ #define R_SSI0_SSISR_RCHNO_Msk        (0xcUL)        /*!< RCHNO (Bitfield-Mask: 0x03)                           */
+ #define R_SSI0_SSISR_RSWNO_Pos        (1UL)          /*!< RSWNO (Bit 1)                                         */
+ #define R_SSI0_SSISR_RSWNO_Msk        (0x2UL)        /*!< RSWNO (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSISR_IDST_Pos         (0UL)          /*!< IDST (Bit 0)                                          */
+ #define R_SSI0_SSISR_IDST_Msk         (0x1UL)        /*!< IDST (Bitfield-Mask: 0x01)                            */
+/* ========================================================  SSIFCR  ========================================================= */
+ #define R_SSI0_SSIFCR_AUCKE_Pos       (31UL)         /*!< AUCKE (Bit 31)                                        */
+ #define R_SSI0_SSIFCR_AUCKE_Msk       (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSIFCR_SSIRST_Pos      (16UL)         /*!< SSIRST (Bit 16)                                       */
+ #define R_SSI0_SSIFCR_SSIRST_Msk      (0x10000UL)    /*!< SSIRST (Bitfield-Mask: 0x01)                          */
+ #define R_SSI0_SSIFCR_TTRG_Pos        (6UL)          /*!< TTRG (Bit 6)                                          */
+ #define R_SSI0_SSIFCR_TTRG_Msk        (0xc0UL)       /*!< TTRG (Bitfield-Mask: 0x03)                            */
+ #define R_SSI0_SSIFCR_RTRG_Pos        (4UL)          /*!< RTRG (Bit 4)                                          */
+ #define R_SSI0_SSIFCR_RTRG_Msk        (0x30UL)       /*!< RTRG (Bitfield-Mask: 0x03)                            */
+ #define R_SSI0_SSIFCR_TIE_Pos         (3UL)          /*!< TIE (Bit 3)                                           */
+ #define R_SSI0_SSIFCR_TIE_Msk         (0x8UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSIFCR_RIE_Pos         (2UL)          /*!< RIE (Bit 2)                                           */
+ #define R_SSI0_SSIFCR_RIE_Msk         (0x4UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSIFCR_TFRST_Pos       (1UL)          /*!< TFRST (Bit 1)                                         */
+ #define R_SSI0_SSIFCR_TFRST_Msk       (0x2UL)        /*!< TFRST (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSIFCR_RFRST_Pos       (0UL)          /*!< RFRST (Bit 0)                                         */
+ #define R_SSI0_SSIFCR_RFRST_Msk       (0x1UL)        /*!< RFRST (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSIFCR_BSW_Pos         (11UL)         /*!< BSW (Bit 11)                                          */
+ #define R_SSI0_SSIFCR_BSW_Msk         (0x800UL)      /*!< BSW (Bitfield-Mask: 0x01)                             */
+/* ========================================================  SSIFSR  ========================================================= */
+ #define R_SSI0_SSIFSR_TDC_Pos         (24UL)         /*!< TDC (Bit 24)                                          */
+ #define R_SSI0_SSIFSR_TDC_Msk         (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f)                             */
+ #define R_SSI0_SSIFSR_TDE_Pos         (16UL)         /*!< TDE (Bit 16)                                          */
+ #define R_SSI0_SSIFSR_TDE_Msk         (0x10000UL)    /*!< TDE (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSIFSR_RDC_Pos         (8UL)          /*!< RDC (Bit 8)                                           */
+ #define R_SSI0_SSIFSR_RDC_Msk         (0x3f00UL)     /*!< RDC (Bitfield-Mask: 0x3f)                             */
+ #define R_SSI0_SSIFSR_RDF_Pos         (0UL)          /*!< RDF (Bit 0)                                           */
+ #define R_SSI0_SSIFSR_RDF_Msk         (0x1UL)        /*!< RDF (Bitfield-Mask: 0x01)                             */
+/* ========================================================  SSIFTDR  ======================================================== */
+ #define R_SSI0_SSIFTDR_SSIFTDR_Pos    (0UL)          /*!< SSIFTDR (Bit 0)                                       */
+ #define R_SSI0_SSIFTDR_SSIFTDR_Msk    (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff)                   */
+/* =======================================================  SSIFTDR16  ======================================================= */
+/* =======================================================  SSIFTDR8  ======================================================== */
+/* ========================================================  SSIFRDR  ======================================================== */
+ #define R_SSI0_SSIFRDR_SSIFRDR_Pos    (0UL)          /*!< SSIFRDR (Bit 0)                                       */
+ #define R_SSI0_SSIFRDR_SSIFRDR_Msk    (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff)                   */
+/* =======================================================  SSIFRDR16  ======================================================= */
+/* =======================================================  SSIFRDR8  ======================================================== */
+/* ========================================================  SSIOFR  ========================================================= */
+ #define R_SSI0_SSIOFR_BCKASTP_Pos     (9UL)          /*!< BCKASTP (Bit 9)                                       */
+ #define R_SSI0_SSIOFR_BCKASTP_Msk     (0x200UL)      /*!< BCKASTP (Bitfield-Mask: 0x01)                         */
+ #define R_SSI0_SSIOFR_LRCONT_Pos      (8UL)          /*!< LRCONT (Bit 8)                                        */
+ #define R_SSI0_SSIOFR_LRCONT_Msk      (0x100UL)      /*!< LRCONT (Bitfield-Mask: 0x01)                          */
+ #define R_SSI0_SSIOFR_OMOD_Pos        (0UL)          /*!< OMOD (Bit 0)                                          */
+ #define R_SSI0_SSIOFR_OMOD_Msk        (0x3UL)        /*!< OMOD (Bitfield-Mask: 0x03)                            */
+/* ========================================================  SSISCR  ========================================================= */
+ #define R_SSI0_SSISCR_TDES_Pos        (8UL)          /*!< TDES (Bit 8)                                          */
+ #define R_SSI0_SSISCR_TDES_Msk        (0x1f00UL)     /*!< TDES (Bitfield-Mask: 0x1f)                            */
+ #define R_SSI0_SSISCR_RDFS_Pos        (0UL)          /*!< RDFS (Bit 0)                                          */
+ #define R_SSI0_SSISCR_RDFS_Msk        (0x1fUL)       /*!< RDFS (Bitfield-Mask: 0x1f)                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SYSTEM                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SBYCR  ========================================================= */
+ #define R_SYSTEM_SBYCR_SSBY_Pos                   (15UL)         /*!< SSBY (Bit 15)                                         */
+ #define R_SYSTEM_SBYCR_SSBY_Msk                   (0x8000UL)     /*!< SSBY (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_SBYCR_OPE_Pos                    (14UL)         /*!< OPE (Bit 14)                                          */
+ #define R_SYSTEM_SBYCR_OPE_Msk                    (0x4000UL)     /*!< OPE (Bitfield-Mask: 0x01)                             */
+/* ========================================================  MSTPCRA  ======================================================== */
+ #define R_SYSTEM_MSTPCRA_MSTPA22_Pos              (22UL)         /*!< MSTPA22 (Bit 22)                                      */
+ #define R_SYSTEM_MSTPCRA_MSTPA22_Msk              (0x400000UL)   /*!< MSTPA22 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_MSTPCRA_MSTPA7_Pos               (7UL)          /*!< MSTPA7 (Bit 7)                                        */
+ #define R_SYSTEM_MSTPCRA_MSTPA7_Msk               (0x80UL)       /*!< MSTPA7 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_MSTPCRA_MSTPA6_Pos               (6UL)          /*!< MSTPA6 (Bit 6)                                        */
+ #define R_SYSTEM_MSTPCRA_MSTPA6_Msk               (0x40UL)       /*!< MSTPA6 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_MSTPCRA_MSTPA5_Pos               (5UL)          /*!< MSTPA5 (Bit 5)                                        */
+ #define R_SYSTEM_MSTPCRA_MSTPA5_Msk               (0x20UL)       /*!< MSTPA5 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_MSTPCRA_MSTPA1_Pos               (1UL)          /*!< MSTPA1 (Bit 1)                                        */
+ #define R_SYSTEM_MSTPCRA_MSTPA1_Msk               (0x2UL)        /*!< MSTPA1 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_MSTPCRA_MSTPA0_Pos               (0UL)          /*!< MSTPA0 (Bit 0)                                        */
+ #define R_SYSTEM_MSTPCRA_MSTPA0_Msk               (0x1UL)        /*!< MSTPA0 (Bitfield-Mask: 0x01)                          */
+/* =======================================================  SCKDIVCR  ======================================================== */
+ #define R_SYSTEM_SCKDIVCR_FCK_Pos                 (28UL)         /*!< FCK (Bit 28)                                          */
+ #define R_SYSTEM_SCKDIVCR_FCK_Msk                 (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07)                             */
+ #define R_SYSTEM_SCKDIVCR_ICK_Pos                 (24UL)         /*!< ICK (Bit 24)                                          */
+ #define R_SYSTEM_SCKDIVCR_ICK_Msk                 (0x7000000UL)  /*!< ICK (Bitfield-Mask: 0x07)                             */
+ #define R_SYSTEM_SCKDIVCR_BCK_Pos                 (16UL)         /*!< BCK (Bit 16)                                          */
+ #define R_SYSTEM_SCKDIVCR_BCK_Msk                 (0x70000UL)    /*!< BCK (Bitfield-Mask: 0x07)                             */
+ #define R_SYSTEM_SCKDIVCR_PCKA_Pos                (12UL)         /*!< PCKA (Bit 12)                                         */
+ #define R_SYSTEM_SCKDIVCR_PCKA_Msk                (0x7000UL)     /*!< PCKA (Bitfield-Mask: 0x07)                            */
+ #define R_SYSTEM_SCKDIVCR_PCKB_Pos                (8UL)          /*!< PCKB (Bit 8)                                          */
+ #define R_SYSTEM_SCKDIVCR_PCKB_Msk                (0x700UL)      /*!< PCKB (Bitfield-Mask: 0x07)                            */
+ #define R_SYSTEM_SCKDIVCR_PCKC_Pos                (4UL)          /*!< PCKC (Bit 4)                                          */
+ #define R_SYSTEM_SCKDIVCR_PCKC_Msk                (0x70UL)       /*!< PCKC (Bitfield-Mask: 0x07)                            */
+ #define R_SYSTEM_SCKDIVCR_PCKD_Pos                (0UL)          /*!< PCKD (Bit 0)                                          */
+ #define R_SYSTEM_SCKDIVCR_PCKD_Msk                (0x7UL)        /*!< PCKD (Bitfield-Mask: 0x07)                            */
+/* =======================================================  SCKDIVCR2  ======================================================= */
+ #define R_SYSTEM_SCKDIVCR2_UCK_Pos                (4UL)          /*!< UCK (Bit 4)                                           */
+ #define R_SYSTEM_SCKDIVCR2_UCK_Msk                (0x70UL)       /*!< UCK (Bitfield-Mask: 0x07)                             */
+/* ========================================================  SCKSCR  ========================================================= */
+ #define R_SYSTEM_SCKSCR_CKSEL_Pos                 (0UL)          /*!< CKSEL (Bit 0)                                         */
+ #define R_SYSTEM_SCKSCR_CKSEL_Msk                 (0x7UL)        /*!< CKSEL (Bitfield-Mask: 0x07)                           */
+/* ========================================================  PLLCCR  ========================================================= */
+ #define R_SYSTEM_PLLCCR_PLLMUL_Pos                (8UL)          /*!< PLLMUL (Bit 8)                                        */
+ #define R_SYSTEM_PLLCCR_PLLMUL_Msk                (0x3f00UL)     /*!< PLLMUL (Bitfield-Mask: 0x3f)                          */
+ #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos              (4UL)          /*!< PLSRCSEL (Bit 4)                                      */
+ #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk              (0x10UL)       /*!< PLSRCSEL (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_PLLCCR_PLIDIV_Pos                (0UL)          /*!< PLIDIV (Bit 0)                                        */
+ #define R_SYSTEM_PLLCCR_PLIDIV_Msk                (0x3UL)        /*!< PLIDIV (Bitfield-Mask: 0x03)                          */
+/* =========================================================  PLLCR  ========================================================= */
+ #define R_SYSTEM_PLLCR_PLLSTP_Pos                 (0UL)          /*!< PLLSTP (Bit 0)                                        */
+ #define R_SYSTEM_PLLCR_PLLSTP_Msk                 (0x1UL)        /*!< PLLSTP (Bitfield-Mask: 0x01)                          */
+/* ========================================================  PLLCCR2  ======================================================== */
+ #define R_SYSTEM_PLLCCR2_PLODIV_Pos               (6UL)          /*!< PLODIV (Bit 6)                                        */
+ #define R_SYSTEM_PLLCCR2_PLODIV_Msk               (0xc0UL)       /*!< PLODIV (Bitfield-Mask: 0x03)                          */
+ #define R_SYSTEM_PLLCCR2_PLLMUL_Pos               (0UL)          /*!< PLLMUL (Bit 0)                                        */
+ #define R_SYSTEM_PLLCCR2_PLLMUL_Msk               (0x1fUL)       /*!< PLLMUL (Bitfield-Mask: 0x1f)                          */
+/* =========================================================  BCKCR  ========================================================= */
+ #define R_SYSTEM_BCKCR_BCLKDIV_Pos                (0UL)          /*!< BCLKDIV (Bit 0)                                       */
+ #define R_SYSTEM_BCKCR_BCLKDIV_Msk                (0x1UL)        /*!< BCLKDIV (Bitfield-Mask: 0x01)                         */
+/* ========================================================  MEMWAIT  ======================================================== */
+ #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos              (0UL)          /*!< MEMWAIT (Bit 0)                                       */
+ #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk              (0x1UL)        /*!< MEMWAIT (Bitfield-Mask: 0x01)                         */
+/* ========================================================  MOSCCR  ========================================================= */
+ #define R_SYSTEM_MOSCCR_MOSTP_Pos                 (0UL)          /*!< MOSTP (Bit 0)                                         */
+ #define R_SYSTEM_MOSCCR_MOSTP_Msk                 (0x1UL)        /*!< MOSTP (Bitfield-Mask: 0x01)                           */
+/* ========================================================  HOCOCR  ========================================================= */
+ #define R_SYSTEM_HOCOCR_HCSTP_Pos                 (0UL)          /*!< HCSTP (Bit 0)                                         */
+ #define R_SYSTEM_HOCOCR_HCSTP_Msk                 (0x1UL)        /*!< HCSTP (Bitfield-Mask: 0x01)                           */
+/* ========================================================  MOCOCR  ========================================================= */
+ #define R_SYSTEM_MOCOCR_MCSTP_Pos                 (0UL)          /*!< MCSTP (Bit 0)                                         */
+ #define R_SYSTEM_MOCOCR_MCSTP_Msk                 (0x1UL)        /*!< MCSTP (Bitfield-Mask: 0x01)                           */
+/* ========================================================  FLLCR1  ========================================================= */
+ #define R_SYSTEM_FLLCR1_FLLEN_Pos                 (0UL)          /*!< FLLEN (Bit 0)                                         */
+ #define R_SYSTEM_FLLCR1_FLLEN_Msk                 (0x1UL)        /*!< FLLEN (Bitfield-Mask: 0x01)                           */
+/* ========================================================  FLLCR2  ========================================================= */
+ #define R_SYSTEM_FLLCR2_FLLCNTL_Pos               (0UL)          /*!< FLLCNTL (Bit 0)                                       */
+ #define R_SYSTEM_FLLCR2_FLLCNTL_Msk               (0x7ffUL)      /*!< FLLCNTL (Bitfield-Mask: 0x7ff)                        */
+/* =========================================================  OSCSF  ========================================================= */
+ #define R_SYSTEM_OSCSF_PLLSF_Pos                  (5UL)          /*!< PLLSF (Bit 5)                                         */
+ #define R_SYSTEM_OSCSF_PLLSF_Msk                  (0x20UL)       /*!< PLLSF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_OSCSF_MOSCSF_Pos                 (3UL)          /*!< MOSCSF (Bit 3)                                        */
+ #define R_SYSTEM_OSCSF_MOSCSF_Msk                 (0x8UL)        /*!< MOSCSF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_OSCSF_HOCOSF_Pos                 (0UL)          /*!< HOCOSF (Bit 0)                                        */
+ #define R_SYSTEM_OSCSF_HOCOSF_Msk                 (0x1UL)        /*!< HOCOSF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_OSCSF_PLL2SF_Pos                 (6UL)          /*!< PLL2SF (Bit 6)                                        */
+ #define R_SYSTEM_OSCSF_PLL2SF_Msk                 (0x40UL)       /*!< PLL2SF (Bitfield-Mask: 0x01)                          */
+/* =========================================================  CKOCR  ========================================================= */
+ #define R_SYSTEM_CKOCR_CKOEN_Pos                  (7UL)          /*!< CKOEN (Bit 7)                                         */
+ #define R_SYSTEM_CKOCR_CKOEN_Msk                  (0x80UL)       /*!< CKOEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_CKOCR_CKODIV_Pos                 (4UL)          /*!< CKODIV (Bit 4)                                        */
+ #define R_SYSTEM_CKOCR_CKODIV_Msk                 (0x70UL)       /*!< CKODIV (Bitfield-Mask: 0x07)                          */
+ #define R_SYSTEM_CKOCR_CKOSEL_Pos                 (0UL)          /*!< CKOSEL (Bit 0)                                        */
+ #define R_SYSTEM_CKOCR_CKOSEL_Msk                 (0x7UL)        /*!< CKOSEL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  TRCKCR  ========================================================= */
+ #define R_SYSTEM_TRCKCR_TRCKEN_Pos                (7UL)          /*!< TRCKEN (Bit 7)                                        */
+ #define R_SYSTEM_TRCKCR_TRCKEN_Msk                (0x80UL)       /*!< TRCKEN (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_TRCKCR_TRCK_Pos                  (0UL)          /*!< TRCK (Bit 0)                                          */
+ #define R_SYSTEM_TRCKCR_TRCK_Msk                  (0xfUL)        /*!< TRCK (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  OSTDCR  ========================================================= */
+ #define R_SYSTEM_OSTDCR_OSTDE_Pos                 (7UL)          /*!< OSTDE (Bit 7)                                         */
+ #define R_SYSTEM_OSTDCR_OSTDE_Msk                 (0x80UL)       /*!< OSTDE (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_OSTDCR_OSTDIE_Pos                (0UL)          /*!< OSTDIE (Bit 0)                                        */
+ #define R_SYSTEM_OSTDCR_OSTDIE_Msk                (0x1UL)        /*!< OSTDIE (Bitfield-Mask: 0x01)                          */
+/* ========================================================  OSTDSR  ========================================================= */
+ #define R_SYSTEM_OSTDSR_OSTDF_Pos                 (0UL)          /*!< OSTDF (Bit 0)                                         */
+ #define R_SYSTEM_OSTDSR_OSTDF_Msk                 (0x1UL)        /*!< OSTDF (Bitfield-Mask: 0x01)                           */
+/* =========================================================  LPOPT  ========================================================= */
+ #define R_SYSTEM_LPOPT_LPOPTEN_Pos                (7UL)          /*!< LPOPTEN (Bit 7)                                       */
+ #define R_SYSTEM_LPOPT_LPOPTEN_Msk                (0x80UL)       /*!< LPOPTEN (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos              (3UL)          /*!< BPFCLKDIS (Bit 3)                                     */
+ #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk              (0x8UL)        /*!< BPFCLKDIS (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_LPOPT_DCLKDIS_Pos                (1UL)          /*!< DCLKDIS (Bit 1)                                       */
+ #define R_SYSTEM_LPOPT_DCLKDIS_Msk                (0x6UL)        /*!< DCLKDIS (Bitfield-Mask: 0x03)                         */
+ #define R_SYSTEM_LPOPT_MPUDIS_Pos                 (0UL)          /*!< MPUDIS (Bit 0)                                        */
+ #define R_SYSTEM_LPOPT_MPUDIS_Msk                 (0x1UL)        /*!< MPUDIS (Bitfield-Mask: 0x01)                          */
+/* =======================================================  SLCDSCKCR  ======================================================= */
+ #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos           (7UL)          /*!< LCDSCKEN (Bit 7)                                      */
+ #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk           (0x80UL)       /*!< LCDSCKEN (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos          (0UL)          /*!< LCDSCKSEL (Bit 0)                                     */
+ #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk          (0x7UL)        /*!< LCDSCKSEL (Bitfield-Mask: 0x07)                       */
+/* ========================================================  EBCKOCR  ======================================================== */
+ #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos              (0UL)          /*!< EBCKOEN (Bit 0)                                       */
+ #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk              (0x1UL)        /*!< EBCKOEN (Bitfield-Mask: 0x01)                         */
+/* ========================================================  SDCKOCR  ======================================================== */
+ #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos              (0UL)          /*!< SDCKOEN (Bit 0)                                       */
+ #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk              (0x1UL)        /*!< SDCKOEN (Bitfield-Mask: 0x01)                         */
+/* =======================================================  MOCOUTCR  ======================================================== */
+ #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos            (0UL)          /*!< MOCOUTRM (Bit 0)                                      */
+ #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk            (0xffUL)       /*!< MOCOUTRM (Bitfield-Mask: 0xff)                        */
+/* =======================================================  HOCOUTCR  ======================================================== */
+ #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos            (0UL)          /*!< HOCOUTRM (Bit 0)                                      */
+ #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk            (0xffUL)       /*!< HOCOUTRM (Bitfield-Mask: 0xff)                        */
+/* =========================================================  SNZCR  ========================================================= */
+ #define R_SYSTEM_SNZCR_SNZE_Pos                   (7UL)          /*!< SNZE (Bit 7)                                          */
+ #define R_SYSTEM_SNZCR_SNZE_Msk                   (0x80UL)       /*!< SNZE (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_SNZCR_SNZDTCEN_Pos               (1UL)          /*!< SNZDTCEN (Bit 1)                                      */
+ #define R_SYSTEM_SNZCR_SNZDTCEN_Msk               (0x2UL)        /*!< SNZDTCEN (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SNZCR_RXDREQEN_Pos               (0UL)          /*!< RXDREQEN (Bit 0)                                      */
+ #define R_SYSTEM_SNZCR_RXDREQEN_Msk               (0x1UL)        /*!< RXDREQEN (Bitfield-Mask: 0x01)                        */
+/* ========================================================  SNZEDCR  ======================================================== */
+ #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos            (7UL)          /*!< SCI0UMTED (Bit 7)                                     */
+ #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk            (0x80UL)       /*!< SCI0UMTED (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos             (6UL)          /*!< AD1UMTED (Bit 6)                                      */
+ #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk             (0x40UL)       /*!< AD1UMTED (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SNZEDCR_AD1MATED_Pos             (5UL)          /*!< AD1MATED (Bit 5)                                      */
+ #define R_SYSTEM_SNZEDCR_AD1MATED_Msk             (0x20UL)       /*!< AD1MATED (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos             (4UL)          /*!< AD0UMTED (Bit 4)                                      */
+ #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk             (0x10UL)       /*!< AD0UMTED (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SNZEDCR_AD0MATED_Pos             (3UL)          /*!< AD0MATED (Bit 3)                                      */
+ #define R_SYSTEM_SNZEDCR_AD0MATED_Msk             (0x8UL)        /*!< AD0MATED (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos             (2UL)          /*!< DTCNZRED (Bit 2)                                      */
+ #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk             (0x4UL)        /*!< DTCNZRED (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SNZEDCR_DTCZRED_Pos              (1UL)          /*!< DTCZRED (Bit 1)                                       */
+ #define R_SYSTEM_SNZEDCR_DTCZRED_Msk              (0x2UL)        /*!< DTCZRED (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos            (0UL)          /*!< AGT1UNFED (Bit 0)                                     */
+ #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk            (0x1UL)        /*!< AGT1UNFED (Bitfield-Mask: 0x01)                       */
+/* =======================================================  SNZREQCR  ======================================================== */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos          (30UL)         /*!< SNZREQEN30 (Bit 30)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk          (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos          (29UL)         /*!< SNZREQEN29 (Bit 29)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk          (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos          (28UL)         /*!< SNZREQEN28 (Bit 28)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk          (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos          (25UL)         /*!< SNZREQEN25 (Bit 25)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk          (0x2000000UL)  /*!< SNZREQEN25 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos          (24UL)         /*!< SNZREQEN24 (Bit 24)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk          (0x1000000UL)  /*!< SNZREQEN24 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos          (23UL)         /*!< SNZREQEN23 (Bit 23)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk          (0x800000UL)   /*!< SNZREQEN23 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos          (22UL)         /*!< SNZREQEN22 (Bit 22)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk          (0x400000UL)   /*!< SNZREQEN22 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos          (17UL)         /*!< SNZREQEN17 (Bit 17)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk          (0x20000UL)    /*!< SNZREQEN17 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos            (0UL)          /*!< SNZREQEN (Bit 0)                                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk            (0x1UL)        /*!< SNZREQEN (Bitfield-Mask: 0x01)                        */
+/* ========================================================  FLSTOP  ========================================================= */
+ #define R_SYSTEM_FLSTOP_FLSTPF_Pos                (4UL)          /*!< FLSTPF (Bit 4)                                        */
+ #define R_SYSTEM_FLSTOP_FLSTPF_Msk                (0x10UL)       /*!< FLSTPF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_FLSTOP_FLSTOP_Pos                (0UL)          /*!< FLSTOP (Bit 0)                                        */
+ #define R_SYSTEM_FLSTOP_FLSTOP_Msk                (0x1UL)        /*!< FLSTOP (Bitfield-Mask: 0x01)                          */
+/* =========================================================  PSMCR  ========================================================= */
+ #define R_SYSTEM_PSMCR_PSMC_Pos                   (0UL)          /*!< PSMC (Bit 0)                                          */
+ #define R_SYSTEM_PSMCR_PSMC_Msk                   (0x3UL)        /*!< PSMC (Bitfield-Mask: 0x03)                            */
+/* =========================================================  OPCCR  ========================================================= */
+ #define R_SYSTEM_OPCCR_OPCMTSF_Pos                (4UL)          /*!< OPCMTSF (Bit 4)                                       */
+ #define R_SYSTEM_OPCCR_OPCMTSF_Msk                (0x10UL)       /*!< OPCMTSF (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_OPCCR_OPCM_Pos                   (0UL)          /*!< OPCM (Bit 0)                                          */
+ #define R_SYSTEM_OPCCR_OPCM_Msk                   (0x3UL)        /*!< OPCM (Bitfield-Mask: 0x03)                            */
+/* ========================================================  SOPCCR  ========================================================= */
+ #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos              (4UL)          /*!< SOPCMTSF (Bit 4)                                      */
+ #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk              (0x10UL)       /*!< SOPCMTSF (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SOPCCR_SOPCM_Pos                 (0UL)          /*!< SOPCM (Bit 0)                                         */
+ #define R_SYSTEM_SOPCCR_SOPCM_Msk                 (0x1UL)        /*!< SOPCM (Bitfield-Mask: 0x01)                           */
+/* =======================================================  MOSCWTCR  ======================================================== */
+ #define R_SYSTEM_MOSCWTCR_MSTS_Pos                (0UL)          /*!< MSTS (Bit 0)                                          */
+ #define R_SYSTEM_MOSCWTCR_MSTS_Msk                (0xfUL)        /*!< MSTS (Bitfield-Mask: 0x0f)                            */
+/* =======================================================  HOCOWTCR  ======================================================== */
+ #define R_SYSTEM_HOCOWTCR_HSTS_Pos                (0UL)          /*!< HSTS (Bit 0)                                          */
+ #define R_SYSTEM_HOCOWTCR_HSTS_Msk                (0x7UL)        /*!< HSTS (Bitfield-Mask: 0x07)                            */
+/* ========================================================  RSTSR1  ========================================================= */
+ #define R_SYSTEM_RSTSR1_SPERF_Pos                 (12UL)         /*!< SPERF (Bit 12)                                        */
+ #define R_SYSTEM_RSTSR1_SPERF_Msk                 (0x1000UL)     /*!< SPERF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_RSTSR1_BUSMRF_Pos                (11UL)         /*!< BUSMRF (Bit 11)                                       */
+ #define R_SYSTEM_RSTSR1_BUSMRF_Msk                (0x800UL)      /*!< BUSMRF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_RSTSR1_BUSSRF_Pos                (10UL)         /*!< BUSSRF (Bit 10)                                       */
+ #define R_SYSTEM_RSTSR1_BUSSRF_Msk                (0x400UL)      /*!< BUSSRF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_RSTSR1_REERF_Pos                 (9UL)          /*!< REERF (Bit 9)                                         */
+ #define R_SYSTEM_RSTSR1_REERF_Msk                 (0x200UL)      /*!< REERF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_RSTSR1_RPERF_Pos                 (8UL)          /*!< RPERF (Bit 8)                                         */
+ #define R_SYSTEM_RSTSR1_RPERF_Msk                 (0x100UL)      /*!< RPERF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_RSTSR1_SWRF_Pos                  (2UL)          /*!< SWRF (Bit 2)                                          */
+ #define R_SYSTEM_RSTSR1_SWRF_Msk                  (0x4UL)        /*!< SWRF (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_RSTSR1_WDTRF_Pos                 (1UL)          /*!< WDTRF (Bit 1)                                         */
+ #define R_SYSTEM_RSTSR1_WDTRF_Msk                 (0x2UL)        /*!< WDTRF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_RSTSR1_IWDTRF_Pos                (0UL)          /*!< IWDTRF (Bit 0)                                        */
+ #define R_SYSTEM_RSTSR1_IWDTRF_Msk                (0x1UL)        /*!< IWDTRF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_RSTSR1_TZERF_Pos                 (13UL)         /*!< TZERF (Bit 13)                                        */
+ #define R_SYSTEM_RSTSR1_TZERF_Msk                 (0x2000UL)     /*!< TZERF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_RSTSR1_CPERF_Pos                 (15UL)         /*!< CPERF (Bit 15)                                        */
+ #define R_SYSTEM_RSTSR1_CPERF_Msk                 (0x8000UL)     /*!< CPERF (Bitfield-Mask: 0x01)                           */
+/* ========================================================  STCONR  ========================================================= */
+ #define R_SYSTEM_STCONR_STCON_Pos                 (0UL)          /*!< STCON (Bit 0)                                         */
+ #define R_SYSTEM_STCONR_STCON_Msk                 (0x3UL)        /*!< STCON (Bitfield-Mask: 0x03)                           */
+/* ========================================================  LVD1CR1  ======================================================== */
+ #define R_SYSTEM_LVD1CR1_IRQSEL_Pos               (2UL)          /*!< IRQSEL (Bit 2)                                        */
+ #define R_SYSTEM_LVD1CR1_IRQSEL_Msk               (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_LVD1CR1_IDTSEL_Pos               (0UL)          /*!< IDTSEL (Bit 0)                                        */
+ #define R_SYSTEM_LVD1CR1_IDTSEL_Msk               (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
+/* ========================================================  LVD2CR1  ======================================================== */
+ #define R_SYSTEM_LVD2CR1_IRQSEL_Pos               (2UL)          /*!< IRQSEL (Bit 2)                                        */
+ #define R_SYSTEM_LVD2CR1_IRQSEL_Msk               (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_LVD2CR1_IDTSEL_Pos               (0UL)          /*!< IDTSEL (Bit 0)                                        */
+ #define R_SYSTEM_LVD2CR1_IDTSEL_Msk               (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
+/* ======================================================  USBCKCR_ALT  ====================================================== */
+ #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos        (0UL)          /*!< USBCLKSEL (Bit 0)                                     */
+ #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk        (0x1UL)        /*!< USBCLKSEL (Bitfield-Mask: 0x01)                       */
+/* =======================================================  SDADCCKCR  ======================================================= */
+ #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos         (0UL)          /*!< SDADCCKSEL (Bit 0)                                    */
+ #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk         (0x1UL)        /*!< SDADCCKSEL (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos          (7UL)          /*!< SDADCCKEN (Bit 7)                                     */
+ #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk          (0x80UL)       /*!< SDADCCKEN (Bitfield-Mask: 0x01)                       */
+/* ========================================================  LVD1SR  ========================================================= */
+ #define R_SYSTEM_LVD1SR_MON_Pos                   (1UL)          /*!< MON (Bit 1)                                           */
+ #define R_SYSTEM_LVD1SR_MON_Msk                   (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
+ #define R_SYSTEM_LVD1SR_DET_Pos                   (0UL)          /*!< DET (Bit 0)                                           */
+ #define R_SYSTEM_LVD1SR_DET_Msk                   (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
+/* ========================================================  LVD2SR  ========================================================= */
+ #define R_SYSTEM_LVD2SR_MON_Pos                   (1UL)          /*!< MON (Bit 1)                                           */
+ #define R_SYSTEM_LVD2SR_MON_Msk                   (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
+ #define R_SYSTEM_LVD2SR_DET_Pos                   (0UL)          /*!< DET (Bit 0)                                           */
+ #define R_SYSTEM_LVD2SR_DET_Msk                   (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
+/* =========================================================  PRCR  ========================================================== */
+ #define R_SYSTEM_PRCR_PRKEY_Pos                   (8UL)          /*!< PRKEY (Bit 8)                                         */
+ #define R_SYSTEM_PRCR_PRKEY_Msk                   (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
+ #define R_SYSTEM_PRCR_PRC3_Pos                    (3UL)          /*!< PRC3 (Bit 3)                                          */
+ #define R_SYSTEM_PRCR_PRC3_Msk                    (0x8UL)        /*!< PRC3 (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_PRCR_PRC1_Pos                    (1UL)          /*!< PRC1 (Bit 1)                                          */
+ #define R_SYSTEM_PRCR_PRC1_Msk                    (0x2UL)        /*!< PRC1 (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_PRCR_PRC0_Pos                    (0UL)          /*!< PRC0 (Bit 0)                                          */
+ #define R_SYSTEM_PRCR_PRC0_Msk                    (0x1UL)        /*!< PRC0 (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_PRCR_PRC4_Pos                    (4UL)          /*!< PRC4 (Bit 4)                                          */
+ #define R_SYSTEM_PRCR_PRC4_Msk                    (0x10UL)       /*!< PRC4 (Bitfield-Mask: 0x01)                            */
+/* ========================================================  DPSIER0  ======================================================== */
+ #define R_SYSTEM_DPSIER0_DIRQE_Pos                (0UL)          /*!< DIRQE (Bit 0)                                         */
+ #define R_SYSTEM_DPSIER0_DIRQE_Msk                (0x1UL)        /*!< DIRQE (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DPSIER1  ======================================================== */
+ #define R_SYSTEM_DPSIER1_DIRQE_Pos                (0UL)          /*!< DIRQE (Bit 0)                                         */
+ #define R_SYSTEM_DPSIER1_DIRQE_Msk                (0x1UL)        /*!< DIRQE (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DPSIER2  ======================================================== */
+ #define R_SYSTEM_DPSIER2_DNMIE_Pos                (4UL)          /*!< DNMIE (Bit 4)                                         */
+ #define R_SYSTEM_DPSIER2_DNMIE_Msk                (0x10UL)       /*!< DNMIE (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_DPSIER2_DRTCAIE_Pos              (3UL)          /*!< DRTCAIE (Bit 3)                                       */
+ #define R_SYSTEM_DPSIER2_DRTCAIE_Msk              (0x8UL)        /*!< DRTCAIE (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos             (2UL)          /*!< DTRTCIIE (Bit 2)                                      */
+ #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk             (0x4UL)        /*!< DTRTCIIE (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_DPSIER2_DLVD2IE_Pos              (1UL)          /*!< DLVD2IE (Bit 1)                                       */
+ #define R_SYSTEM_DPSIER2_DLVD2IE_Msk              (0x2UL)        /*!< DLVD2IE (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPSIER2_DLVD1IE_Pos              (0UL)          /*!< DLVD1IE (Bit 0)                                       */
+ #define R_SYSTEM_DPSIER2_DLVD1IE_Msk              (0x1UL)        /*!< DLVD1IE (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DPSIER3  ======================================================== */
+ #define R_SYSTEM_DPSIER3_DAGT1IE_Pos              (2UL)          /*!< DAGT1IE (Bit 2)                                       */
+ #define R_SYSTEM_DPSIER3_DAGT1IE_Msk              (0x4UL)        /*!< DAGT1IE (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos             (1UL)          /*!< DUSBHSIE (Bit 1)                                      */
+ #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk             (0x2UL)        /*!< DUSBHSIE (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos             (0UL)          /*!< DUSBFSIE (Bit 0)                                      */
+ #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk             (0x1UL)        /*!< DUSBFSIE (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_DPSIER3_DAGT3IE_Pos              (3UL)          /*!< DAGT3IE (Bit 3)                                       */
+ #define R_SYSTEM_DPSIER3_DAGT3IE_Msk              (0x8UL)        /*!< DAGT3IE (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DPSIFR0  ======================================================== */
+ #define R_SYSTEM_DPSIFR0_DIRQF_Pos                (0UL)          /*!< DIRQF (Bit 0)                                         */
+ #define R_SYSTEM_DPSIFR0_DIRQF_Msk                (0x1UL)        /*!< DIRQF (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DPSIFR1  ======================================================== */
+ #define R_SYSTEM_DPSIFR1_DIRQF_Pos                (0UL)          /*!< DIRQF (Bit 0)                                         */
+ #define R_SYSTEM_DPSIFR1_DIRQF_Msk                (0x1UL)        /*!< DIRQF (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DPSIFR2  ======================================================== */
+ #define R_SYSTEM_DPSIFR2_DNMIF_Pos                (4UL)          /*!< DNMIF (Bit 4)                                         */
+ #define R_SYSTEM_DPSIFR2_DNMIF_Msk                (0x10UL)       /*!< DNMIF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos              (3UL)          /*!< DRTCAIF (Bit 3)                                       */
+ #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk              (0x8UL)        /*!< DRTCAIF (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos             (2UL)          /*!< DTRTCIIF (Bit 2)                                      */
+ #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk             (0x4UL)        /*!< DTRTCIIF (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos              (1UL)          /*!< DLVD2IF (Bit 1)                                       */
+ #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk              (0x2UL)        /*!< DLVD2IF (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos              (0UL)          /*!< DLVD1IF (Bit 0)                                       */
+ #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk              (0x1UL)        /*!< DLVD1IF (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DPSIFR3  ======================================================== */
+ #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos              (2UL)          /*!< DAGT1IF (Bit 2)                                       */
+ #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk              (0x4UL)        /*!< DAGT1IF (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos             (1UL)          /*!< DUSBHSIF (Bit 1)                                      */
+ #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk             (0x2UL)        /*!< DUSBHSIF (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos             (0UL)          /*!< DUSBFSIF (Bit 0)                                      */
+ #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk             (0x1UL)        /*!< DUSBFSIF (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos              (3UL)          /*!< DAGT3IF (Bit 3)                                       */
+ #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk              (0x8UL)        /*!< DAGT3IF (Bitfield-Mask: 0x01)                         */
+/* =======================================================  DPSIEGR0  ======================================================== */
+ #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos              (0UL)          /*!< DIRQEG (Bit 0)                                        */
+ #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk              (0x1UL)        /*!< DIRQEG (Bitfield-Mask: 0x01)                          */
+/* =======================================================  DPSIEGR1  ======================================================== */
+ #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos              (0UL)          /*!< DIRQEG (Bit 0)                                        */
+ #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk              (0x1UL)        /*!< DIRQEG (Bitfield-Mask: 0x01)                          */
+/* =======================================================  DPSIEGR2  ======================================================== */
+ #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos              (4UL)          /*!< DNMIEG (Bit 4)                                        */
+ #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk              (0x10UL)       /*!< DNMIEG (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos            (1UL)          /*!< DLVD2IEG (Bit 1)                                      */
+ #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk            (0x2UL)        /*!< DLVD2IEG (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos            (0UL)          /*!< DLVD1IEG (Bit 0)                                      */
+ #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk            (0x1UL)        /*!< DLVD1IEG (Bitfield-Mask: 0x01)                        */
+/* ========================================================  DPSBYCR  ======================================================== */
+ #define R_SYSTEM_DPSBYCR_DPSBY_Pos                (7UL)          /*!< DPSBY (Bit 7)                                         */
+ #define R_SYSTEM_DPSBYCR_DPSBY_Msk                (0x80UL)       /*!< DPSBY (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_DPSBYCR_IOKEEP_Pos               (6UL)          /*!< IOKEEP (Bit 6)                                        */
+ #define R_SYSTEM_DPSBYCR_IOKEEP_Msk               (0x40UL)       /*!< IOKEEP (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos              (0UL)          /*!< DEEPCUT (Bit 0)                                       */
+ #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk              (0x3UL)        /*!< DEEPCUT (Bitfield-Mask: 0x03)                         */
+/* ========================================================  SYOCDCR  ======================================================== */
+ #define R_SYSTEM_SYOCDCR_DBGEN_Pos                (7UL)          /*!< DBGEN (Bit 7)                                         */
+ #define R_SYSTEM_SYOCDCR_DBGEN_Msk                (0x80UL)       /*!< DBGEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_SYOCDCR_DOCDF_Pos                (0UL)          /*!< DOCDF (Bit 0)                                         */
+ #define R_SYSTEM_SYOCDCR_DOCDF_Msk                (0x1UL)        /*!< DOCDF (Bitfield-Mask: 0x01)                           */
+/* =========================================================  MOMCR  ========================================================= */
+ #define R_SYSTEM_MOMCR_AUTODRVEN_Pos              (7UL)          /*!< AUTODRVEN (Bit 7)                                     */
+ #define R_SYSTEM_MOMCR_AUTODRVEN_Msk              (0x80UL)       /*!< AUTODRVEN (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_MOMCR_MOSEL_Pos                  (6UL)          /*!< MOSEL (Bit 6)                                         */
+ #define R_SYSTEM_MOMCR_MOSEL_Msk                  (0x40UL)       /*!< MOSEL (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_MOMCR_MODRV0_Pos                 (4UL)          /*!< MODRV0 (Bit 4)                                        */
+ #define R_SYSTEM_MOMCR_MODRV0_Msk                 (0x30UL)       /*!< MODRV0 (Bitfield-Mask: 0x03)                          */
+ #define R_SYSTEM_MOMCR_MODRV1_Pos                 (3UL)          /*!< MODRV1 (Bit 3)                                        */
+ #define R_SYSTEM_MOMCR_MODRV1_Msk                 (0x8UL)        /*!< MODRV1 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  RSTSR0  ========================================================= */
+ #define R_SYSTEM_RSTSR0_DPSRSTF_Pos               (7UL)          /*!< DPSRSTF (Bit 7)                                       */
+ #define R_SYSTEM_RSTSR0_DPSRSTF_Msk               (0x80UL)       /*!< DPSRSTF (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_RSTSR0_LVD2RF_Pos                (3UL)          /*!< LVD2RF (Bit 3)                                        */
+ #define R_SYSTEM_RSTSR0_LVD2RF_Msk                (0x8UL)        /*!< LVD2RF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_RSTSR0_LVD1RF_Pos                (2UL)          /*!< LVD1RF (Bit 2)                                        */
+ #define R_SYSTEM_RSTSR0_LVD1RF_Msk                (0x4UL)        /*!< LVD1RF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_RSTSR0_LVD0RF_Pos                (1UL)          /*!< LVD0RF (Bit 1)                                        */
+ #define R_SYSTEM_RSTSR0_LVD0RF_Msk                (0x2UL)        /*!< LVD0RF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_RSTSR0_PORF_Pos                  (0UL)          /*!< PORF (Bit 0)                                          */
+ #define R_SYSTEM_RSTSR0_PORF_Msk                  (0x1UL)        /*!< PORF (Bitfield-Mask: 0x01)                            */
+/* ========================================================  RSTSR2  ========================================================= */
+ #define R_SYSTEM_RSTSR2_CWSF_Pos                  (0UL)          /*!< CWSF (Bit 0)                                          */
+ #define R_SYSTEM_RSTSR2_CWSF_Msk                  (0x1UL)        /*!< CWSF (Bitfield-Mask: 0x01)                            */
+/* ========================================================  LVCMPCR  ======================================================== */
+ #define R_SYSTEM_LVCMPCR_LVD2E_Pos                (6UL)          /*!< LVD2E (Bit 6)                                         */
+ #define R_SYSTEM_LVCMPCR_LVD2E_Msk                (0x40UL)       /*!< LVD2E (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_LVCMPCR_LVD1E_Pos                (5UL)          /*!< LVD1E (Bit 5)                                         */
+ #define R_SYSTEM_LVCMPCR_LVD1E_Msk                (0x20UL)       /*!< LVD1E (Bitfield-Mask: 0x01)                           */
+/* =======================================================  LVD1CMPCR  ======================================================= */
+ #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos            (0UL)          /*!< LVD1LVL (Bit 0)                                       */
+ #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk            (0x1fUL)       /*!< LVD1LVL (Bitfield-Mask: 0x1f)                         */
+ #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos              (7UL)          /*!< LVD1E (Bit 7)                                         */
+ #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk              (0x80UL)       /*!< LVD1E (Bitfield-Mask: 0x01)                           */
+/* ========================================================  LVDLVLR  ======================================================== */
+ #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos              (5UL)          /*!< LVD2LVL (Bit 5)                                       */
+ #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk              (0xe0UL)       /*!< LVD2LVL (Bitfield-Mask: 0x07)                         */
+ #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos              (0UL)          /*!< LVD1LVL (Bit 0)                                       */
+ #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk              (0x1fUL)       /*!< LVD1LVL (Bitfield-Mask: 0x1f)                         */
+/* =======================================================  LVD2CMPCR  ======================================================= */
+ #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos            (0UL)          /*!< LVD2LVL (Bit 0)                                       */
+ #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk            (0x7UL)        /*!< LVD2LVL (Bitfield-Mask: 0x07)                         */
+ #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos              (7UL)          /*!< LVD2E (Bit 7)                                         */
+ #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk              (0x80UL)       /*!< LVD2E (Bitfield-Mask: 0x01)                           */
+/* ========================================================  LVD1CR0  ======================================================== */
+ #define R_SYSTEM_LVD1CR0_RN_Pos                   (7UL)          /*!< RN (Bit 7)                                            */
+ #define R_SYSTEM_LVD1CR0_RN_Msk                   (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
+ #define R_SYSTEM_LVD1CR0_RI_Pos                   (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_SYSTEM_LVD1CR0_RI_Msk                   (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_SYSTEM_LVD1CR0_FSAMP_Pos                (4UL)          /*!< FSAMP (Bit 4)                                         */
+ #define R_SYSTEM_LVD1CR0_FSAMP_Msk                (0x30UL)       /*!< FSAMP (Bitfield-Mask: 0x03)                           */
+ #define R_SYSTEM_LVD1CR0_CMPE_Pos                 (2UL)          /*!< CMPE (Bit 2)                                          */
+ #define R_SYSTEM_LVD1CR0_CMPE_Msk                 (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_LVD1CR0_DFDIS_Pos                (1UL)          /*!< DFDIS (Bit 1)                                         */
+ #define R_SYSTEM_LVD1CR0_DFDIS_Msk                (0x2UL)        /*!< DFDIS (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_LVD1CR0_RIE_Pos                  (0UL)          /*!< RIE (Bit 0)                                           */
+ #define R_SYSTEM_LVD1CR0_RIE_Msk                  (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
+/* ========================================================  LVD2CR0  ======================================================== */
+ #define R_SYSTEM_LVD2CR0_RN_Pos                   (7UL)          /*!< RN (Bit 7)                                            */
+ #define R_SYSTEM_LVD2CR0_RN_Msk                   (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
+ #define R_SYSTEM_LVD2CR0_RI_Pos                   (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_SYSTEM_LVD2CR0_RI_Msk                   (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_SYSTEM_LVD2CR0_FSAMP_Pos                (4UL)          /*!< FSAMP (Bit 4)                                         */
+ #define R_SYSTEM_LVD2CR0_FSAMP_Msk                (0x30UL)       /*!< FSAMP (Bitfield-Mask: 0x03)                           */
+ #define R_SYSTEM_LVD2CR0_CMPE_Pos                 (2UL)          /*!< CMPE (Bit 2)                                          */
+ #define R_SYSTEM_LVD2CR0_CMPE_Msk                 (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_LVD2CR0_DFDIS_Pos                (1UL)          /*!< DFDIS (Bit 1)                                         */
+ #define R_SYSTEM_LVD2CR0_DFDIS_Msk                (0x2UL)        /*!< DFDIS (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_LVD2CR0_RIE_Pos                  (0UL)          /*!< RIE (Bit 0)                                           */
+ #define R_SYSTEM_LVD2CR0_RIE_Msk                  (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
+/* ========================================================  VBTCR1  ========================================================= */
+ #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos              (0UL)          /*!< BPWSWSTP (Bit 0)                                      */
+ #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk              (0x1UL)        /*!< BPWSWSTP (Bitfield-Mask: 0x01)                        */
+/* ========================================================  DCDCCTL  ======================================================== */
+ #define R_SYSTEM_DCDCCTL_PD_Pos                   (7UL)          /*!< PD (Bit 7)                                            */
+ #define R_SYSTEM_DCDCCTL_PD_Msk                   (0x80UL)       /*!< PD (Bitfield-Mask: 0x01)                              */
+ #define R_SYSTEM_DCDCCTL_FST_Pos                  (6UL)          /*!< FST (Bit 6)                                           */
+ #define R_SYSTEM_DCDCCTL_FST_Msk                  (0x40UL)       /*!< FST (Bitfield-Mask: 0x01)                             */
+ #define R_SYSTEM_DCDCCTL_LCBOOST_Pos              (5UL)          /*!< LCBOOST (Bit 5)                                       */
+ #define R_SYSTEM_DCDCCTL_LCBOOST_Msk              (0x20UL)       /*!< LCBOOST (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DCDCCTL_STOPZA_Pos               (4UL)          /*!< STOPZA (Bit 4)                                        */
+ #define R_SYSTEM_DCDCCTL_STOPZA_Msk               (0x10UL)       /*!< STOPZA (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DCDCCTL_OCPEN_Pos                (1UL)          /*!< OCPEN (Bit 1)                                         */
+ #define R_SYSTEM_DCDCCTL_OCPEN_Msk                (0x2UL)        /*!< OCPEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_DCDCCTL_DCDCON_Pos               (0UL)          /*!< DCDCON (Bit 0)                                        */
+ #define R_SYSTEM_DCDCCTL_DCDCON_Msk               (0x1UL)        /*!< DCDCON (Bitfield-Mask: 0x01)                          */
+/* ========================================================  VCCSEL  ========================================================= */
+ #define R_SYSTEM_VCCSEL_VCCSEL_Pos                (0UL)          /*!< VCCSEL (Bit 0)                                        */
+ #define R_SYSTEM_VCCSEL_VCCSEL_Msk                (0x3UL)        /*!< VCCSEL (Bitfield-Mask: 0x03)                          */
+/* ========================================================  LDOSCR  ========================================================= */
+ #define R_SYSTEM_LDOSCR_LDOSTP0_Pos               (0UL)          /*!< LDOSTP0 (Bit 0)                                       */
+ #define R_SYSTEM_LDOSCR_LDOSTP0_Msk               (0x1UL)        /*!< LDOSTP0 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_LDOSCR_LDOSTP1_Pos               (1UL)          /*!< LDOSTP1 (Bit 1)                                       */
+ #define R_SYSTEM_LDOSCR_LDOSTP1_Msk               (0x2UL)        /*!< LDOSTP1 (Bitfield-Mask: 0x01)                         */
+/* =======================================================  PL2LDOSCR  ======================================================= */
+ #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos          (0UL)          /*!< PL2LDOSTP (Bit 0)                                     */
+ #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk          (0x1UL)        /*!< PL2LDOSTP (Bitfield-Mask: 0x01)                       */
+/* ========================================================  SOSCCR  ========================================================= */
+ #define R_SYSTEM_SOSCCR_SOSTP_Pos                 (0UL)          /*!< SOSTP (Bit 0)                                         */
+ #define R_SYSTEM_SOSCCR_SOSTP_Msk                 (0x1UL)        /*!< SOSTP (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SOMCR  ========================================================= */
+ #define R_SYSTEM_SOMCR_SODRV_Pos                  (0UL)          /*!< SODRV (Bit 0)                                         */
+ #define R_SYSTEM_SOMCR_SODRV_Msk                  (0x3UL)        /*!< SODRV (Bitfield-Mask: 0x03)                           */
+/* ========================================================  LOCOCR  ========================================================= */
+ #define R_SYSTEM_LOCOCR_LCSTP_Pos                 (0UL)          /*!< LCSTP (Bit 0)                                         */
+ #define R_SYSTEM_LOCOCR_LCSTP_Msk                 (0x1UL)        /*!< LCSTP (Bitfield-Mask: 0x01)                           */
+/* =======================================================  LOCOUTCR  ======================================================== */
+ #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos            (0UL)          /*!< LOCOUTRM (Bit 0)                                      */
+ #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk            (0xffUL)       /*!< LOCOUTRM (Bitfield-Mask: 0xff)                        */
+/* ========================================================  VBTCR2  ========================================================= */
+ #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos             (6UL)          /*!< VBTLVDLVL (Bit 6)                                     */
+ #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk             (0xc0UL)       /*!< VBTLVDLVL (Bitfield-Mask: 0x03)                       */
+ #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos              (4UL)          /*!< VBTLVDEN (Bit 4)                                      */
+ #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk              (0x10UL)       /*!< VBTLVDEN (Bitfield-Mask: 0x01)                        */
+/* =========================================================  VBTSR  ========================================================= */
+ #define R_SYSTEM_VBTSR_VBTRVLD_Pos                (4UL)          /*!< VBTRVLD (Bit 4)                                       */
+ #define R_SYSTEM_VBTSR_VBTRVLD_Msk                (0x10UL)       /*!< VBTRVLD (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_VBTSR_VBTBLDF_Pos                (1UL)          /*!< VBTBLDF (Bit 1)                                       */
+ #define R_SYSTEM_VBTSR_VBTBLDF_Msk                (0x2UL)        /*!< VBTBLDF (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_VBTSR_VBTRDF_Pos                 (0UL)          /*!< VBTRDF (Bit 0)                                        */
+ #define R_SYSTEM_VBTSR_VBTRDF_Msk                 (0x1UL)        /*!< VBTRDF (Bitfield-Mask: 0x01)                          */
+/* =======================================================  VBTCMPCR  ======================================================== */
+ #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos             (0UL)          /*!< VBTCMPE (Bit 0)                                       */
+ #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk             (0x1UL)        /*!< VBTCMPE (Bitfield-Mask: 0x01)                         */
+/* =======================================================  VBTLVDICR  ======================================================= */
+ #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos         (1UL)          /*!< VBTLVDISEL (Bit 1)                                    */
+ #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk         (0x2UL)        /*!< VBTLVDISEL (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos           (0UL)          /*!< VBTLVDIE (Bit 0)                                      */
+ #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk           (0x1UL)        /*!< VBTLVDIE (Bitfield-Mask: 0x01)                        */
+/* =======================================================  VBTWCTLR  ======================================================== */
+ #define R_SYSTEM_VBTWCTLR_VWEN_Pos                (0UL)          /*!< VWEN (Bit 0)                                          */
+ #define R_SYSTEM_VBTWCTLR_VWEN_Msk                (0x1UL)        /*!< VWEN (Bitfield-Mask: 0x01)                            */
+/* ======================================================  VBTWCH0OTSR  ====================================================== */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos       (5UL)          /*!< CH0VAGTUTE (Bit 5)                                    */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk       (0x20UL)       /*!< CH0VAGTUTE (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos       (4UL)          /*!< CH0VRTCATE (Bit 4)                                    */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk       (0x10UL)       /*!< CH0VRTCATE (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos        (3UL)          /*!< CH0VRTCTE (Bit 3)                                     */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk        (0x8UL)        /*!< CH0VRTCTE (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos        (2UL)          /*!< CH0VCH2TE (Bit 2)                                     */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk        (0x4UL)        /*!< CH0VCH2TE (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos        (1UL)          /*!< CH0VCH1TE (Bit 1)                                     */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk        (0x2UL)        /*!< CH0VCH1TE (Bitfield-Mask: 0x01)                       */
+/* ======================================================  VBTWCH1OTSR  ====================================================== */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos       (5UL)          /*!< CH1VAGTUTE (Bit 5)                                    */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk       (0x20UL)       /*!< CH1VAGTUTE (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos       (4UL)          /*!< CH1VRTCATE (Bit 4)                                    */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk       (0x10UL)       /*!< CH1VRTCATE (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos        (3UL)          /*!< CH1VRTCTE (Bit 3)                                     */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk        (0x8UL)        /*!< CH1VRTCTE (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos        (2UL)          /*!< CH1VCH2TE (Bit 2)                                     */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk        (0x4UL)        /*!< CH1VCH2TE (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos        (0UL)          /*!< CH1VCH0TE (Bit 0)                                     */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk        (0x1UL)        /*!< CH1VCH0TE (Bitfield-Mask: 0x01)                       */
+/* ======================================================  VBTWCH2OTSR  ====================================================== */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos       (5UL)          /*!< CH2VAGTUTE (Bit 5)                                    */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk       (0x20UL)       /*!< CH2VAGTUTE (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos       (4UL)          /*!< CH2VRTCATE (Bit 4)                                    */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk       (0x10UL)       /*!< CH2VRTCATE (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos        (3UL)          /*!< CH2VRTCTE (Bit 3)                                     */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk        (0x8UL)        /*!< CH2VRTCTE (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos        (1UL)          /*!< CH2VCH1TE (Bit 1)                                     */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk        (0x2UL)        /*!< CH2VCH1TE (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos        (0UL)          /*!< CH2VCH0TE (Bit 0)                                     */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk        (0x1UL)        /*!< CH2VCH0TE (Bitfield-Mask: 0x01)                       */
+/* =======================================================  VBTICTLR  ======================================================== */
+ #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos            (2UL)          /*!< VCH2INEN (Bit 2)                                      */
+ #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk            (0x4UL)        /*!< VCH2INEN (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos            (1UL)          /*!< VCH1INEN (Bit 1)                                      */
+ #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk            (0x2UL)        /*!< VCH1INEN (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos            (0UL)          /*!< VCH0INEN (Bit 0)                                      */
+ #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk            (0x1UL)        /*!< VCH0INEN (Bitfield-Mask: 0x01)                        */
+/* =======================================================  VBTOCTLR  ======================================================== */
+ #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos           (5UL)          /*!< VOUT2LSEL (Bit 5)                                     */
+ #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk           (0x20UL)       /*!< VOUT2LSEL (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos           (4UL)          /*!< VCOU1LSEL (Bit 4)                                     */
+ #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk           (0x10UL)       /*!< VCOU1LSEL (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos           (3UL)          /*!< VOUT0LSEL (Bit 3)                                     */
+ #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk           (0x8UL)        /*!< VOUT0LSEL (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos             (2UL)          /*!< VCH2OEN (Bit 2)                                       */
+ #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk             (0x4UL)        /*!< VCH2OEN (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos             (1UL)          /*!< VCH1OEN (Bit 1)                                       */
+ #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk             (0x2UL)        /*!< VCH1OEN (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos             (0UL)          /*!< VCH0OEN (Bit 0)                                       */
+ #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk             (0x1UL)        /*!< VCH0OEN (Bitfield-Mask: 0x01)                         */
+/* ========================================================  VBTWTER  ======================================================== */
+ #define R_SYSTEM_VBTWTER_VAGTUE_Pos               (5UL)          /*!< VAGTUE (Bit 5)                                        */
+ #define R_SYSTEM_VBTWTER_VAGTUE_Msk               (0x20UL)       /*!< VAGTUE (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWTER_VRTCAE_Pos               (4UL)          /*!< VRTCAE (Bit 4)                                        */
+ #define R_SYSTEM_VBTWTER_VRTCAE_Msk               (0x10UL)       /*!< VRTCAE (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWTER_VRTCIE_Pos               (3UL)          /*!< VRTCIE (Bit 3)                                        */
+ #define R_SYSTEM_VBTWTER_VRTCIE_Msk               (0x8UL)        /*!< VRTCIE (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWTER_VCH2E_Pos                (2UL)          /*!< VCH2E (Bit 2)                                         */
+ #define R_SYSTEM_VBTWTER_VCH2E_Msk                (0x4UL)        /*!< VCH2E (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_VBTWTER_VCH1E_Pos                (1UL)          /*!< VCH1E (Bit 1)                                         */
+ #define R_SYSTEM_VBTWTER_VCH1E_Msk                (0x2UL)        /*!< VCH1E (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_VBTWTER_VCH0E_Pos                (0UL)          /*!< VCH0E (Bit 0)                                         */
+ #define R_SYSTEM_VBTWTER_VCH0E_Msk                (0x1UL)        /*!< VCH0E (Bitfield-Mask: 0x01)                           */
+/* ========================================================  VBTWEGR  ======================================================== */
+ #define R_SYSTEM_VBTWEGR_VCH2EG_Pos               (2UL)          /*!< VCH2EG (Bit 2)                                        */
+ #define R_SYSTEM_VBTWEGR_VCH2EG_Msk               (0x4UL)        /*!< VCH2EG (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWEGR_VCH1EG_Pos               (1UL)          /*!< VCH1EG (Bit 1)                                        */
+ #define R_SYSTEM_VBTWEGR_VCH1EG_Msk               (0x2UL)        /*!< VCH1EG (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWEGR_VCH0EG_Pos               (0UL)          /*!< VCH0EG (Bit 0)                                        */
+ #define R_SYSTEM_VBTWEGR_VCH0EG_Msk               (0x1UL)        /*!< VCH0EG (Bitfield-Mask: 0x01)                          */
+/* ========================================================  VBTWFR  ========================================================= */
+ #define R_SYSTEM_VBTWFR_VAGTUF_Pos                (5UL)          /*!< VAGTUF (Bit 5)                                        */
+ #define R_SYSTEM_VBTWFR_VAGTUF_Msk                (0x20UL)       /*!< VAGTUF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWFR_VRTCAF_Pos                (4UL)          /*!< VRTCAF (Bit 4)                                        */
+ #define R_SYSTEM_VBTWFR_VRTCAF_Msk                (0x10UL)       /*!< VRTCAF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWFR_VRTCIF_Pos                (3UL)          /*!< VRTCIF (Bit 3)                                        */
+ #define R_SYSTEM_VBTWFR_VRTCIF_Msk                (0x8UL)        /*!< VRTCIF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWFR_VCH2F_Pos                 (2UL)          /*!< VCH2F (Bit 2)                                         */
+ #define R_SYSTEM_VBTWFR_VCH2F_Msk                 (0x4UL)        /*!< VCH2F (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_VBTWFR_VCH1F_Pos                 (1UL)          /*!< VCH1F (Bit 1)                                         */
+ #define R_SYSTEM_VBTWFR_VCH1F_Msk                 (0x2UL)        /*!< VCH1F (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_VBTWFR_VCH0F_Pos                 (0UL)          /*!< VCH0F (Bit 0)                                         */
+ #define R_SYSTEM_VBTWFR_VCH0F_Msk                 (0x1UL)        /*!< VCH0F (Bitfield-Mask: 0x01)                           */
+/* ========================================================  VBTBKR  ========================================================= */
+ #define R_SYSTEM_VBTBKR_VBTBKR_Pos                (0UL)          /*!< VBTBKR (Bit 0)                                        */
+ #define R_SYSTEM_VBTBKR_VBTBKR_Msk                (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
+/* ========================================================  FWEPROR  ======================================================== */
+ #define R_SYSTEM_FWEPROR_FLWE_Pos                 (0UL)          /*!< FLWE (Bit 0)                                          */
+ #define R_SYSTEM_FWEPROR_FLWE_Msk                 (0x3UL)        /*!< FLWE (Bitfield-Mask: 0x03)                            */
+/* ========================================================  PLL2CCR  ======================================================== */
+ #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos              (0UL)          /*!< PL2IDIV (Bit 0)                                       */
+ #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk              (0x3UL)        /*!< PL2IDIV (Bitfield-Mask: 0x03)                         */
+ #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos            (4UL)          /*!< PL2SRCSEL (Bit 4)                                     */
+ #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk            (0x10UL)       /*!< PL2SRCSEL (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos              (8UL)          /*!< PLL2MUL (Bit 8)                                       */
+ #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk              (0x3f00UL)     /*!< PLL2MUL (Bitfield-Mask: 0x3f)                         */
+/* ========================================================  PLL2CR  ========================================================= */
+ #define R_SYSTEM_PLL2CR_PLL2STP_Pos               (0UL)          /*!< PLL2STP (Bit 0)                                       */
+ #define R_SYSTEM_PLL2CR_PLL2STP_Msk               (0x1UL)        /*!< PLL2STP (Bitfield-Mask: 0x01)                         */
+/* ======================================================  USBCKDIVCR  ======================================================= */
+ #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos          (0UL)          /*!< USBCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk          (0x7UL)        /*!< USBCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  OCTACKDIVCR  ====================================================== */
+ #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos        (0UL)          /*!< OCTACKDIV (Bit 0)                                     */
+ #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk        (0x7UL)        /*!< OCTACKDIV (Bitfield-Mask: 0x07)                       */
+/* =====================================================  SCISPICKDIVCR  ===================================================== */
+ #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos    (0UL)          /*!< SCISPICKDIV (Bit 0)                                   */
+ #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk    (0x7UL)        /*!< SCISPICKDIV (Bitfield-Mask: 0x07)                     */
+/* =====================================================  CANFDCKDIVCR  ====================================================== */
+ #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos      (0UL)          /*!< CANFDCKDIV (Bit 0)                                    */
+ #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk      (0x7UL)        /*!< CANFDCKDIV (Bitfield-Mask: 0x07)                      */
+/* ======================================================  GPTCKDIVCR  ======================================================= */
+ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos          (0UL)          /*!< GPTCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk          (0x7UL)        /*!< GPTCKDIV (Bitfield-Mask: 0x07)                        */
+/* =====================================================  USB60CKDIVCR  ====================================================== */
+ #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos      (0UL)          /*!< USB60CKDIV (Bit 0)                                    */
+ #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk      (0x7UL)        /*!< USB60CKDIV (Bitfield-Mask: 0x07)                      */
+/* ======================================================  CECCKDIVCR  ======================================================= */
+ #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  I3CCKDIVCR  ======================================================= */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  IICCKDIVCR  ======================================================= */
+ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
+/* ========================================================  USBCKCR  ======================================================== */
+ #define R_SYSTEM_USBCKCR_USBCKSEL_Pos             (0UL)          /*!< USBCKSEL (Bit 0)                                      */
+ #define R_SYSTEM_USBCKCR_USBCKSEL_Msk             (0x7UL)        /*!< USBCKSEL (Bitfield-Mask: 0x07)                        */
+ #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos            (6UL)          /*!< USBCKSREQ (Bit 6)                                     */
+ #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk            (0x40UL)       /*!< USBCKSREQ (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos            (7UL)          /*!< USBCKSRDY (Bit 7)                                     */
+ #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk            (0x80UL)       /*!< USBCKSRDY (Bitfield-Mask: 0x01)                       */
+/* =======================================================  OCTACKCR  ======================================================== */
+ #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos           (0UL)          /*!< OCTACKSEL (Bit 0)                                     */
+ #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk           (0x7UL)        /*!< OCTACKSEL (Bitfield-Mask: 0x07)                       */
+ #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos          (6UL)          /*!< OCTACKSREQ (Bit 6)                                    */
+ #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk          (0x40UL)       /*!< OCTACKSREQ (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos          (7UL)          /*!< OCTACKSRDY (Bit 7)                                    */
+ #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk          (0x80UL)       /*!< OCTACKSRDY (Bitfield-Mask: 0x01)                      */
+/* ======================================================  SCISPICKCR  ======================================================= */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos       (0UL)          /*!< SCISPICKSEL (Bit 0)                                   */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk       (0x7UL)        /*!< SCISPICKSEL (Bitfield-Mask: 0x07)                     */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos      (6UL)          /*!< SCISPICKSREQ (Bit 6)                                  */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk      (0x40UL)       /*!< SCISPICKSREQ (Bitfield-Mask: 0x01)                    */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos      (7UL)          /*!< SCISPICKSRDY (Bit 7)                                  */
+ #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk      (0x80UL)       /*!< SCISPICKSRDY (Bitfield-Mask: 0x01)                    */
+/* =======================================================  CANFDCKCR  ======================================================= */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos         (0UL)          /*!< CANFDCKSEL (Bit 0)                                    */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk         (0x7UL)        /*!< CANFDCKSEL (Bitfield-Mask: 0x07)                      */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos        (6UL)          /*!< CANFDCKSREQ (Bit 6)                                   */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk        (0x40UL)       /*!< CANFDCKSREQ (Bitfield-Mask: 0x01)                     */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos        (7UL)          /*!< CANFDCKSRDY (Bit 7)                                   */
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk        (0x80UL)       /*!< CANFDCKSRDY (Bitfield-Mask: 0x01)                     */
+/* ========================================================  GPTCKCR  ======================================================== */
+ #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos             (0UL)          /*!< GPTCKSEL (Bit 0)                                      */
+ #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk             (0x7UL)        /*!< GPTCKSEL (Bitfield-Mask: 0x07)                        */
+ #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos            (6UL)          /*!< GPTCKSREQ (Bit 6)                                     */
+ #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk            (0x40UL)       /*!< GPTCKSREQ (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos            (7UL)          /*!< GPTCKSRDY (Bit 7)                                     */
+ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk            (0x80UL)       /*!< GPTCKSRDY (Bitfield-Mask: 0x01)                       */
+/* =======================================================  USB60CKCR  ======================================================= */
+ #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos         (0UL)          /*!< USB60CKSEL (Bit 0)                                    */
+ #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk         (0xfUL)        /*!< USB60CKSEL (Bitfield-Mask: 0x0f)                      */
+ #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos        (6UL)          /*!< USB60CKSREQ (Bit 6)                                   */
+ #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk        (0x40UL)       /*!< USB60CKSREQ (Bitfield-Mask: 0x01)                     */
+ #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos        (7UL)          /*!< USB60CKSRDY (Bit 7)                                   */
+ #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk        (0x80UL)       /*!< USB60CKSRDY (Bitfield-Mask: 0x01)                     */
+/* ========================================================  CECCKCR  ======================================================== */
+ #define R_SYSTEM_CECCKCR_CECCKSEL_Pos             (0UL)          /*!< CECCKSEL (Bit 0)                                      */
+ #define R_SYSTEM_CECCKCR_CECCKSEL_Msk             (0x7UL)        /*!< CECCKSEL (Bitfield-Mask: 0x07)                        */
+ #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos            (6UL)          /*!< CECCKSREQ (Bit 6)                                     */
+ #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk            (0x40UL)       /*!< CECCKSREQ (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos            (7UL)          /*!< CECCKSRDY (Bit 7)                                     */
+ #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk            (0x80UL)       /*!< CECCKSRDY (Bitfield-Mask: 0x01)                       */
+/* ========================================================  IICCKCR  ======================================================== */
+ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos             (0UL)          /*!< IICCKSEL (Bit 0)                                      */
+ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk             (0x7UL)        /*!< IICCKSEL (Bitfield-Mask: 0x07)                        */
+ #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos            (6UL)          /*!< IICCKSREQ (Bit 6)                                     */
+ #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk            (0x40UL)       /*!< IICCKSREQ (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos            (7UL)          /*!< IICCKSRDY (Bit 7)                                     */
+ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk            (0x80UL)       /*!< IICCKSRDY (Bitfield-Mask: 0x01)                       */
+/* ========================================================  I3CCKCR  ======================================================== */
+ #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos             (0UL)          /*!< I3CCKSEL (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk             (0x7UL)        /*!< I3CCKSEL (Bitfield-Mask: 0x07)                        */
+ #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos            (6UL)          /*!< I3CCKSREQ (Bit 6)                                     */
+ #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk            (0x40UL)       /*!< I3CCKSREQ (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos            (7UL)          /*!< I3CCKSRDY (Bit 7)                                     */
+ #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk            (0x80UL)       /*!< I3CCKSRDY (Bitfield-Mask: 0x01)                       */
+/* =======================================================  SNZREQCR1  ======================================================= */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos          (0UL)          /*!< SNZREQEN0 (Bit 0)                                     */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk          (0x1UL)        /*!< SNZREQEN0 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos          (1UL)          /*!< SNZREQEN1 (Bit 1)                                     */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk          (0x2UL)        /*!< SNZREQEN1 (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos          (2UL)          /*!< SNZREQEN2 (Bit 2)                                     */
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk          (0x4UL)        /*!< SNZREQEN2 (Bitfield-Mask: 0x01)                       */
+/* =======================================================  SNZEDCR1  ======================================================== */
+ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos           (0UL)          /*!< AGT3UNFED (Bit 0)                                     */
+ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk           (0x1UL)        /*!< AGT3UNFED (Bitfield-Mask: 0x01)                       */
+/* ========================================================  CGFSAR  ========================================================= */
+ #define R_SYSTEM_CGFSAR_NONSEC00_Pos              (0UL)          /*!< NONSEC00 (Bit 0)                                      */
+ #define R_SYSTEM_CGFSAR_NONSEC00_Msk              (0x1UL)        /*!< NONSEC00 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC02_Pos              (2UL)          /*!< NONSEC02 (Bit 2)                                      */
+ #define R_SYSTEM_CGFSAR_NONSEC02_Msk              (0x4UL)        /*!< NONSEC02 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC03_Pos              (3UL)          /*!< NONSEC03 (Bit 3)                                      */
+ #define R_SYSTEM_CGFSAR_NONSEC03_Msk              (0x8UL)        /*!< NONSEC03 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC04_Pos              (4UL)          /*!< NONSEC04 (Bit 4)                                      */
+ #define R_SYSTEM_CGFSAR_NONSEC04_Msk              (0x10UL)       /*!< NONSEC04 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC05_Pos              (5UL)          /*!< NONSEC05 (Bit 5)                                      */
+ #define R_SYSTEM_CGFSAR_NONSEC05_Msk              (0x20UL)       /*!< NONSEC05 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC06_Pos              (6UL)          /*!< NONSEC06 (Bit 6)                                      */
+ #define R_SYSTEM_CGFSAR_NONSEC06_Msk              (0x40UL)       /*!< NONSEC06 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC07_Pos              (7UL)          /*!< NONSEC07 (Bit 7)                                      */
+ #define R_SYSTEM_CGFSAR_NONSEC07_Msk              (0x80UL)       /*!< NONSEC07 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC08_Pos              (8UL)          /*!< NONSEC08 (Bit 8)                                      */
+ #define R_SYSTEM_CGFSAR_NONSEC08_Msk              (0x100UL)      /*!< NONSEC08 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC09_Pos              (9UL)          /*!< NONSEC09 (Bit 9)                                      */
+ #define R_SYSTEM_CGFSAR_NONSEC09_Msk              (0x200UL)      /*!< NONSEC09 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC11_Pos              (11UL)         /*!< NONSEC11 (Bit 11)                                     */
+ #define R_SYSTEM_CGFSAR_NONSEC11_Msk              (0x800UL)      /*!< NONSEC11 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC12_Pos              (12UL)         /*!< NONSEC12 (Bit 12)                                     */
+ #define R_SYSTEM_CGFSAR_NONSEC12_Msk              (0x1000UL)     /*!< NONSEC12 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC16_Pos              (16UL)         /*!< NONSEC16 (Bit 16)                                     */
+ #define R_SYSTEM_CGFSAR_NONSEC16_Msk              (0x10000UL)    /*!< NONSEC16 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_CGFSAR_NONSEC17_Pos              (17UL)         /*!< NONSEC17 (Bit 17)                                     */
+ #define R_SYSTEM_CGFSAR_NONSEC17_Msk              (0x20000UL)    /*!< NONSEC17 (Bitfield-Mask: 0x01)                        */
+/* ========================================================  LPMSAR  ========================================================= */
+ #define R_SYSTEM_LPMSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
+ #define R_SYSTEM_LPMSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_LPMSAR_NONSEC2_Pos               (2UL)          /*!< NONSEC2 (Bit 2)                                       */
+ #define R_SYSTEM_LPMSAR_NONSEC2_Msk               (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_LPMSAR_NONSEC4_Pos               (4UL)          /*!< NONSEC4 (Bit 4)                                       */
+ #define R_SYSTEM_LPMSAR_NONSEC4_Msk               (0x10UL)       /*!< NONSEC4 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_LPMSAR_NONSEC8_Pos               (8UL)          /*!< NONSEC8 (Bit 8)                                       */
+ #define R_SYSTEM_LPMSAR_NONSEC8_Msk               (0x100UL)      /*!< NONSEC8 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_LPMSAR_NONSEC9_Pos               (9UL)          /*!< NONSEC9 (Bit 9)                                       */
+ #define R_SYSTEM_LPMSAR_NONSEC9_Msk               (0x200UL)      /*!< NONSEC9 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  LVDSAR  ========================================================= */
+ #define R_SYSTEM_LVDSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
+ #define R_SYSTEM_LVDSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_LVDSAR_NONSEC1_Pos               (1UL)          /*!< NONSEC1 (Bit 1)                                       */
+ #define R_SYSTEM_LVDSAR_NONSEC1_Msk               (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  RSTSAR  ========================================================= */
+ #define R_SYSTEM_RSTSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
+ #define R_SYSTEM_RSTSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_RSTSAR_NONSEC1_Pos               (1UL)          /*!< NONSEC1 (Bit 1)                                       */
+ #define R_SYSTEM_RSTSAR_NONSEC1_Msk               (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_RSTSAR_NONSEC2_Pos               (2UL)          /*!< NONSEC2 (Bit 2)                                       */
+ #define R_SYSTEM_RSTSAR_NONSEC2_Msk               (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  BBFSAR  ========================================================= */
+ #define R_SYSTEM_BBFSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
+ #define R_SYSTEM_BBFSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_BBFSAR_NONSEC1_Pos               (1UL)          /*!< NONSEC1 (Bit 1)                                       */
+ #define R_SYSTEM_BBFSAR_NONSEC1_Msk               (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_BBFSAR_NONSEC2_Pos               (2UL)          /*!< NONSEC2 (Bit 2)                                       */
+ #define R_SYSTEM_BBFSAR_NONSEC2_Msk               (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_BBFSAR_NONSEC16_Pos              (16UL)         /*!< NONSEC16 (Bit 16)                                     */
+ #define R_SYSTEM_BBFSAR_NONSEC16_Msk              (0x10000UL)    /*!< NONSEC16 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_BBFSAR_NONSEC17_Pos              (17UL)         /*!< NONSEC17 (Bit 17)                                     */
+ #define R_SYSTEM_BBFSAR_NONSEC17_Msk              (0x20000UL)    /*!< NONSEC17 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_BBFSAR_NONSEC18_Pos              (18UL)         /*!< NONSEC18 (Bit 18)                                     */
+ #define R_SYSTEM_BBFSAR_NONSEC18_Msk              (0x40000UL)    /*!< NONSEC18 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_BBFSAR_NONSEC19_Pos              (19UL)         /*!< NONSEC19 (Bit 19)                                     */
+ #define R_SYSTEM_BBFSAR_NONSEC19_Msk              (0x80000UL)    /*!< NONSEC19 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_BBFSAR_NONSEC20_Pos              (20UL)         /*!< NONSEC20 (Bit 20)                                     */
+ #define R_SYSTEM_BBFSAR_NONSEC20_Msk              (0x100000UL)   /*!< NONSEC20 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_BBFSAR_NONSEC21_Pos              (21UL)         /*!< NONSEC21 (Bit 21)                                     */
+ #define R_SYSTEM_BBFSAR_NONSEC21_Msk              (0x200000UL)   /*!< NONSEC21 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_BBFSAR_NONSEC22_Pos              (22UL)         /*!< NONSEC22 (Bit 22)                                     */
+ #define R_SYSTEM_BBFSAR_NONSEC22_Msk              (0x400000UL)   /*!< NONSEC22 (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_BBFSAR_NONSEC23_Pos              (23UL)         /*!< NONSEC23 (Bit 23)                                     */
+ #define R_SYSTEM_BBFSAR_NONSEC23_Msk              (0x800000UL)   /*!< NONSEC23 (Bitfield-Mask: 0x01)                        */
+/* ========================================================  DPFSAR  ========================================================= */
+ #define R_SYSTEM_DPFSAR_DPFSA0_Pos                (0UL)          /*!< DPFSA0 (Bit 0)                                        */
+ #define R_SYSTEM_DPFSAR_DPFSA0_Msk                (0x1UL)        /*!< DPFSA0 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPFSAR_DPFSA1_Pos                (1UL)          /*!< DPFSA1 (Bit 1)                                        */
+ #define R_SYSTEM_DPFSAR_DPFSA1_Msk                (0x2UL)        /*!< DPFSA1 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPFSAR_DPFSA2_Pos                (2UL)          /*!< DPFSA2 (Bit 2)                                        */
+ #define R_SYSTEM_DPFSAR_DPFSA2_Msk                (0x4UL)        /*!< DPFSA2 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPFSAR_DPFSA3_Pos                (3UL)          /*!< DPFSA3 (Bit 3)                                        */
+ #define R_SYSTEM_DPFSAR_DPFSA3_Msk                (0x8UL)        /*!< DPFSA3 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPFSAR_DPFSA4_Pos                (4UL)          /*!< DPFSA4 (Bit 4)                                        */
+ #define R_SYSTEM_DPFSAR_DPFSA4_Msk                (0x10UL)       /*!< DPFSA4 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPFSAR_DPFSA5_Pos                (5UL)          /*!< DPFSA5 (Bit 5)                                        */
+ #define R_SYSTEM_DPFSAR_DPFSA5_Msk                (0x20UL)       /*!< DPFSA5 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPFSAR_DPFSA6_Pos                (6UL)          /*!< DPFSA6 (Bit 6)                                        */
+ #define R_SYSTEM_DPFSAR_DPFSA6_Msk                (0x40UL)       /*!< DPFSA6 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPFSAR_DPFSA7_Pos                (7UL)          /*!< DPFSA7 (Bit 7)                                        */
+ #define R_SYSTEM_DPFSAR_DPFSA7_Msk                (0x80UL)       /*!< DPFSA7 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPFSAR_DPFSA8_Pos                (8UL)          /*!< DPFSA8 (Bit 8)                                        */
+ #define R_SYSTEM_DPFSAR_DPFSA8_Msk                (0x100UL)      /*!< DPFSA8 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPFSAR_DPFSA9_Pos                (9UL)          /*!< DPFSA9 (Bit 9)                                        */
+ #define R_SYSTEM_DPFSAR_DPFSA9_Msk                (0x200UL)      /*!< DPFSA9 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPFSAR_DPFSA10_Pos               (10UL)         /*!< DPFSA10 (Bit 10)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA10_Msk               (0x400UL)      /*!< DPFSA10 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA11_Pos               (11UL)         /*!< DPFSA11 (Bit 11)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA11_Msk               (0x800UL)      /*!< DPFSA11 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA12_Pos               (12UL)         /*!< DPFSA12 (Bit 12)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA12_Msk               (0x1000UL)     /*!< DPFSA12 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA13_Pos               (13UL)         /*!< DPFSA13 (Bit 13)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA13_Msk               (0x2000UL)     /*!< DPFSA13 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA14_Pos               (14UL)         /*!< DPFSA14 (Bit 14)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA14_Msk               (0x4000UL)     /*!< DPFSA14 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA15_Pos               (15UL)         /*!< DPFSA15 (Bit 15)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA15_Msk               (0x8000UL)     /*!< DPFSA15 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA16_Pos               (16UL)         /*!< DPFSA16 (Bit 16)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA16_Msk               (0x10000UL)    /*!< DPFSA16 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA17_Pos               (17UL)         /*!< DPFSA17 (Bit 17)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA17_Msk               (0x20000UL)    /*!< DPFSA17 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA18_Pos               (18UL)         /*!< DPFSA18 (Bit 18)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA18_Msk               (0x40000UL)    /*!< DPFSA18 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA19_Pos               (19UL)         /*!< DPFSA19 (Bit 19)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA19_Msk               (0x80000UL)    /*!< DPFSA19 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA20_Pos               (20UL)         /*!< DPFSA20 (Bit 20)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA20_Msk               (0x100000UL)   /*!< DPFSA20 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA24_Pos               (24UL)         /*!< DPFSA24 (Bit 24)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA24_Msk               (0x1000000UL)  /*!< DPFSA24 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA26_Pos               (26UL)         /*!< DPFSA26 (Bit 26)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA26_Msk               (0x4000000UL)  /*!< DPFSA26 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPFSAR_DPFSA27_Pos               (27UL)         /*!< DPFSA27 (Bit 27)                                      */
+ #define R_SYSTEM_DPFSAR_DPFSA27_Msk               (0x8000000UL)  /*!< DPFSA27 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DPSWCR  ========================================================= */
+ #define R_SYSTEM_DPSWCR_WTSTS_Pos                 (0UL)          /*!< WTSTS (Bit 0)                                         */
+ #define R_SYSTEM_DPSWCR_WTSTS_Msk                 (0x3fUL)       /*!< WTSTS (Bitfield-Mask: 0x3f)                           */
+/* ======================================================  VBATTMNSELR  ====================================================== */
+ #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos       (0UL)          /*!< VBATTMNSEL (Bit 0)                                    */
+ #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk       (0x1UL)        /*!< VBATTMNSEL (Bitfield-Mask: 0x01)                      */
+/* =======================================================  VBATTMONR  ======================================================= */
+ #define R_SYSTEM_VBATTMONR_VBATTMON_Pos           (0UL)          /*!< VBATTMON (Bit 0)                                      */
+ #define R_SYSTEM_VBATTMONR_VBATTMON_Msk           (0x1UL)        /*!< VBATTMON (Bitfield-Mask: 0x01)                        */
+/* ========================================================  VBTBER  ========================================================= */
+ #define R_SYSTEM_VBTBER_VBAE_Pos                  (3UL)          /*!< VBAE (Bit 3)                                          */
+ #define R_SYSTEM_VBTBER_VBAE_Msk                  (0x8UL)        /*!< VBAE (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_TSN_CAL                                         ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  TSCDR  ========================================================= */
+ #define R_TSN_CAL_TSCDR_TSCDR_Pos    (0UL)          /*!< TSCDR (Bit 0)                                         */
+ #define R_TSN_CAL_TSCDR_TSCDR_Msk    (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff)                     */
+
+/* =========================================================================================================================== */
+/* ================                                        R_TSN_CTRL                                         ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  TSCR  ========================================================== */
+ #define R_TSN_CTRL_TSCR_TSEN_Pos    (7UL)    /*!< TSEN (Bit 7)                                          */
+ #define R_TSN_CTRL_TSCR_TSEN_Msk    (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01)                            */
+ #define R_TSN_CTRL_TSCR_TSOE_Pos    (4UL)    /*!< TSOE (Bit 4)                                          */
+ #define R_TSN_CTRL_TSCR_TSOE_Msk    (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_USB_FS0                                         ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  SYSCFG  ========================================================= */
+ #define R_USB_FS0_SYSCFG_SCKE_Pos         (10UL)     /*!< SCKE (Bit 10)                                         */
+ #define R_USB_FS0_SYSCFG_SCKE_Msk         (0x400UL)  /*!< SCKE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_SYSCFG_CNEN_Pos         (8UL)      /*!< CNEN (Bit 8)                                          */
+ #define R_USB_FS0_SYSCFG_CNEN_Msk         (0x100UL)  /*!< CNEN (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_SYSCFG_DCFM_Pos         (6UL)      /*!< DCFM (Bit 6)                                          */
+ #define R_USB_FS0_SYSCFG_DCFM_Msk         (0x40UL)   /*!< DCFM (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_SYSCFG_DRPD_Pos         (5UL)      /*!< DRPD (Bit 5)                                          */
+ #define R_USB_FS0_SYSCFG_DRPD_Msk         (0x20UL)   /*!< DRPD (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_SYSCFG_DPRPU_Pos        (4UL)      /*!< DPRPU (Bit 4)                                         */
+ #define R_USB_FS0_SYSCFG_DPRPU_Msk        (0x10UL)   /*!< DPRPU (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_SYSCFG_DMRPU_Pos        (3UL)      /*!< DMRPU (Bit 3)                                         */
+ #define R_USB_FS0_SYSCFG_DMRPU_Msk        (0x8UL)    /*!< DMRPU (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_SYSCFG_USBE_Pos         (0UL)      /*!< USBE (Bit 0)                                          */
+ #define R_USB_FS0_SYSCFG_USBE_Msk         (0x1UL)    /*!< USBE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  BUSWAIT  ======================================================== */
+ #define R_USB_FS0_BUSWAIT_BWAIT_Pos       (0UL)      /*!< BWAIT (Bit 0)                                         */
+ #define R_USB_FS0_BUSWAIT_BWAIT_Msk       (0xfUL)    /*!< BWAIT (Bitfield-Mask: 0x0f)                           */
+/* ========================================================  SYSSTS0  ======================================================== */
+ #define R_USB_FS0_SYSSTS0_OVCMON_Pos      (14UL)     /*!< OVCMON (Bit 14)                                       */
+ #define R_USB_FS0_SYSSTS0_OVCMON_Msk      (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03)                          */
+ #define R_USB_FS0_SYSSTS0_HTACT_Pos       (6UL)      /*!< HTACT (Bit 6)                                         */
+ #define R_USB_FS0_SYSSTS0_HTACT_Msk       (0x40UL)   /*!< HTACT (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_SYSSTS0_SOFEA_Pos       (5UL)      /*!< SOFEA (Bit 5)                                         */
+ #define R_USB_FS0_SYSSTS0_SOFEA_Msk       (0x20UL)   /*!< SOFEA (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_SYSSTS0_IDMON_Pos       (2UL)      /*!< IDMON (Bit 2)                                         */
+ #define R_USB_FS0_SYSSTS0_IDMON_Msk       (0x4UL)    /*!< IDMON (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_SYSSTS0_LNST_Pos        (0UL)      /*!< LNST (Bit 0)                                          */
+ #define R_USB_FS0_SYSSTS0_LNST_Msk        (0x3UL)    /*!< LNST (Bitfield-Mask: 0x03)                            */
+/* ========================================================  PLLSTA  ========================================================= */
+ #define R_USB_FS0_PLLSTA_PLLLOCK_Pos      (0UL)      /*!< PLLLOCK (Bit 0)                                       */
+ #define R_USB_FS0_PLLSTA_PLLLOCK_Msk      (0x1UL)    /*!< PLLLOCK (Bitfield-Mask: 0x01)                         */
+/* =======================================================  DVSTCTR0  ======================================================== */
+ #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos    (11UL)     /*!< HNPBTOA (Bit 11)                                      */
+ #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk    (0x800UL)  /*!< HNPBTOA (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DVSTCTR0_EXICEN_Pos     (10UL)     /*!< EXICEN (Bit 10)                                       */
+ #define R_USB_FS0_DVSTCTR0_EXICEN_Msk     (0x400UL)  /*!< EXICEN (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos     (9UL)      /*!< VBUSEN (Bit 9)                                        */
+ #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk     (0x200UL)  /*!< VBUSEN (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DVSTCTR0_WKUP_Pos       (8UL)      /*!< WKUP (Bit 8)                                          */
+ #define R_USB_FS0_DVSTCTR0_WKUP_Msk       (0x100UL)  /*!< WKUP (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_DVSTCTR0_RWUPE_Pos      (7UL)      /*!< RWUPE (Bit 7)                                         */
+ #define R_USB_FS0_DVSTCTR0_RWUPE_Msk      (0x80UL)   /*!< RWUPE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DVSTCTR0_USBRST_Pos     (6UL)      /*!< USBRST (Bit 6)                                        */
+ #define R_USB_FS0_DVSTCTR0_USBRST_Msk     (0x40UL)   /*!< USBRST (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DVSTCTR0_RESUME_Pos     (5UL)      /*!< RESUME (Bit 5)                                        */
+ #define R_USB_FS0_DVSTCTR0_RESUME_Msk     (0x20UL)   /*!< RESUME (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DVSTCTR0_UACT_Pos       (4UL)      /*!< UACT (Bit 4)                                          */
+ #define R_USB_FS0_DVSTCTR0_UACT_Msk       (0x10UL)   /*!< UACT (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_DVSTCTR0_RHST_Pos       (0UL)      /*!< RHST (Bit 0)                                          */
+ #define R_USB_FS0_DVSTCTR0_RHST_Msk       (0x7UL)    /*!< RHST (Bitfield-Mask: 0x07)                            */
+/* =======================================================  TESTMODE  ======================================================== */
+ #define R_USB_FS0_TESTMODE_UTST_Pos       (0UL)      /*!< UTST (Bit 0)                                          */
+ #define R_USB_FS0_TESTMODE_UTST_Msk       (0xfUL)    /*!< UTST (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  CFIFOL  ========================================================= */
+/* ========================================================  CFIFOLL  ======================================================== */
+/* =========================================================  CFIFO  ========================================================= */
+/* ========================================================  CFIFOH  ========================================================= */
+/* ========================================================  CFIFOHH  ======================================================== */
+/* ========================================================  D0FIFOL  ======================================================== */
+/* =======================================================  D0FIFOLL  ======================================================== */
+/* ========================================================  D0FIFO  ========================================================= */
+/* ========================================================  D0FIFOH  ======================================================== */
+/* =======================================================  D0FIFOHH  ======================================================== */
+/* ========================================================  D1FIFOL  ======================================================== */
+/* =======================================================  D1FIFOLL  ======================================================== */
+/* ========================================================  D1FIFO  ========================================================= */
+/* ========================================================  D1FIFOH  ======================================================== */
+/* =======================================================  D1FIFOHH  ======================================================== */
+/* =======================================================  CFIFOSEL  ======================================================== */
+ #define R_USB_FS0_CFIFOSEL_RCNT_Pos            (15UL)       /*!< RCNT (Bit 15)                                         */
+ #define R_USB_FS0_CFIFOSEL_RCNT_Msk            (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_CFIFOSEL_REW_Pos             (14UL)       /*!< REW (Bit 14)                                          */
+ #define R_USB_FS0_CFIFOSEL_REW_Msk             (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
+ #define R_USB_FS0_CFIFOSEL_MBW_Pos             (10UL)       /*!< MBW (Bit 10)                                          */
+ #define R_USB_FS0_CFIFOSEL_MBW_Msk             (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
+ #define R_USB_FS0_CFIFOSEL_BIGEND_Pos          (8UL)        /*!< BIGEND (Bit 8)                                        */
+ #define R_USB_FS0_CFIFOSEL_BIGEND_Msk          (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_CFIFOSEL_ISEL_Pos            (5UL)        /*!< ISEL (Bit 5)                                          */
+ #define R_USB_FS0_CFIFOSEL_ISEL_Msk            (0x20UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos         (0UL)        /*!< CURPIPE (Bit 0)                                       */
+ #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk         (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  CFIFOCTR  ======================================================== */
+ #define R_USB_FS0_CFIFOCTR_BVAL_Pos            (15UL)       /*!< BVAL (Bit 15)                                         */
+ #define R_USB_FS0_CFIFOCTR_BVAL_Msk            (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_CFIFOCTR_BCLR_Pos            (14UL)       /*!< BCLR (Bit 14)                                         */
+ #define R_USB_FS0_CFIFOCTR_BCLR_Msk            (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_CFIFOCTR_FRDY_Pos            (13UL)       /*!< FRDY (Bit 13)                                         */
+ #define R_USB_FS0_CFIFOCTR_FRDY_Msk            (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_CFIFOCTR_DTLN_Pos            (0UL)        /*!< DTLN (Bit 0)                                          */
+ #define R_USB_FS0_CFIFOCTR_DTLN_Msk            (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
+/* =======================================================  D0FIFOSEL  ======================================================= */
+ #define R_USB_FS0_D0FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
+ #define R_USB_FS0_D0FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D0FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
+ #define R_USB_FS0_D0FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
+ #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
+ #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_D0FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
+ #define R_USB_FS0_D0FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_D0FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
+ #define R_USB_FS0_D0FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
+ #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
+ #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
+ #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  D0FIFOCTR  ======================================================= */
+ #define R_USB_FS0_D0FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
+ #define R_USB_FS0_D0FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D0FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
+ #define R_USB_FS0_D0FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D0FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
+ #define R_USB_FS0_D0FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D0FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
+ #define R_USB_FS0_D0FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
+/* =======================================================  D1FIFOSEL  ======================================================= */
+ #define R_USB_FS0_D1FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
+ #define R_USB_FS0_D1FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D1FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
+ #define R_USB_FS0_D1FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
+ #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
+ #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_D1FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
+ #define R_USB_FS0_D1FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_D1FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
+ #define R_USB_FS0_D1FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
+ #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
+ #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
+ #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  D1FIFOCTR  ======================================================= */
+ #define R_USB_FS0_D1FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
+ #define R_USB_FS0_D1FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D1FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
+ #define R_USB_FS0_D1FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D1FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
+ #define R_USB_FS0_D1FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D1FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
+ #define R_USB_FS0_D1FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
+/* ========================================================  INTENB0  ======================================================== */
+ #define R_USB_FS0_INTENB0_VBSE_Pos             (15UL)       /*!< VBSE (Bit 15)                                         */
+ #define R_USB_FS0_INTENB0_VBSE_Msk             (0x8000UL)   /*!< VBSE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTENB0_RSME_Pos             (14UL)       /*!< RSME (Bit 14)                                         */
+ #define R_USB_FS0_INTENB0_RSME_Msk             (0x4000UL)   /*!< RSME (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTENB0_SOFE_Pos             (13UL)       /*!< SOFE (Bit 13)                                         */
+ #define R_USB_FS0_INTENB0_SOFE_Msk             (0x2000UL)   /*!< SOFE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTENB0_DVSE_Pos             (12UL)       /*!< DVSE (Bit 12)                                         */
+ #define R_USB_FS0_INTENB0_DVSE_Msk             (0x1000UL)   /*!< DVSE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTENB0_CTRE_Pos             (11UL)       /*!< CTRE (Bit 11)                                         */
+ #define R_USB_FS0_INTENB0_CTRE_Msk             (0x800UL)    /*!< CTRE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTENB0_BEMPE_Pos            (10UL)       /*!< BEMPE (Bit 10)                                        */
+ #define R_USB_FS0_INTENB0_BEMPE_Msk            (0x400UL)    /*!< BEMPE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTENB0_NRDYE_Pos            (9UL)        /*!< NRDYE (Bit 9)                                         */
+ #define R_USB_FS0_INTENB0_NRDYE_Msk            (0x200UL)    /*!< NRDYE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTENB0_BRDYE_Pos            (8UL)        /*!< BRDYE (Bit 8)                                         */
+ #define R_USB_FS0_INTENB0_BRDYE_Msk            (0x100UL)    /*!< BRDYE (Bitfield-Mask: 0x01)                           */
+/* ========================================================  INTENB1  ======================================================== */
+ #define R_USB_FS0_INTENB1_OVRCRE_Pos           (15UL)       /*!< OVRCRE (Bit 15)                                       */
+ #define R_USB_FS0_INTENB1_OVRCRE_Msk           (0x8000UL)   /*!< OVRCRE (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_INTENB1_BCHGE_Pos            (14UL)       /*!< BCHGE (Bit 14)                                        */
+ #define R_USB_FS0_INTENB1_BCHGE_Msk            (0x4000UL)   /*!< BCHGE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTENB1_DTCHE_Pos            (12UL)       /*!< DTCHE (Bit 12)                                        */
+ #define R_USB_FS0_INTENB1_DTCHE_Msk            (0x1000UL)   /*!< DTCHE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTENB1_ATTCHE_Pos           (11UL)       /*!< ATTCHE (Bit 11)                                       */
+ #define R_USB_FS0_INTENB1_ATTCHE_Msk           (0x800UL)    /*!< ATTCHE (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_INTENB1_EOFERRE_Pos          (6UL)        /*!< EOFERRE (Bit 6)                                       */
+ #define R_USB_FS0_INTENB1_EOFERRE_Msk          (0x40UL)     /*!< EOFERRE (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_INTENB1_SIGNE_Pos            (5UL)        /*!< SIGNE (Bit 5)                                         */
+ #define R_USB_FS0_INTENB1_SIGNE_Msk            (0x20UL)     /*!< SIGNE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTENB1_SACKE_Pos            (4UL)        /*!< SACKE (Bit 4)                                         */
+ #define R_USB_FS0_INTENB1_SACKE_Msk            (0x10UL)     /*!< SACKE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTENB1_PDDETINTE0_Pos       (0UL)        /*!< PDDETINTE0 (Bit 0)                                    */
+ #define R_USB_FS0_INTENB1_PDDETINTE0_Msk       (0x1UL)      /*!< PDDETINTE0 (Bitfield-Mask: 0x01)                      */
+/* ========================================================  BRDYENB  ======================================================== */
+ #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos        (0UL)        /*!< PIPEBRDYE (Bit 0)                                     */
+ #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk        (0x1UL)      /*!< PIPEBRDYE (Bitfield-Mask: 0x01)                       */
+/* ========================================================  NRDYENB  ======================================================== */
+ #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos        (0UL)        /*!< PIPENRDYE (Bit 0)                                     */
+ #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk        (0x1UL)      /*!< PIPENRDYE (Bitfield-Mask: 0x01)                       */
+/* ========================================================  BEMPENB  ======================================================== */
+ #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos        (0UL)        /*!< PIPEBEMPE (Bit 0)                                     */
+ #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk        (0x1UL)      /*!< PIPEBEMPE (Bitfield-Mask: 0x01)                       */
+/* ========================================================  SOFCFG  ========================================================= */
+ #define R_USB_FS0_SOFCFG_TRNENSEL_Pos          (8UL)        /*!< TRNENSEL (Bit 8)                                      */
+ #define R_USB_FS0_SOFCFG_TRNENSEL_Msk          (0x100UL)    /*!< TRNENSEL (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_SOFCFG_BRDYM_Pos             (6UL)        /*!< BRDYM (Bit 6)                                         */
+ #define R_USB_FS0_SOFCFG_BRDYM_Msk             (0x40UL)     /*!< BRDYM (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_SOFCFG_INTL_Pos              (5UL)        /*!< INTL (Bit 5)                                          */
+ #define R_USB_FS0_SOFCFG_INTL_Msk              (0x20UL)     /*!< INTL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_SOFCFG_EDGESTS_Pos           (4UL)        /*!< EDGESTS (Bit 4)                                       */
+ #define R_USB_FS0_SOFCFG_EDGESTS_Msk           (0x10UL)     /*!< EDGESTS (Bitfield-Mask: 0x01)                         */
+/* ========================================================  PHYSET  ========================================================= */
+ #define R_USB_FS0_PHYSET_HSEB_Pos              (15UL)       /*!< HSEB (Bit 15)                                         */
+ #define R_USB_FS0_PHYSET_HSEB_Msk              (0x8000UL)   /*!< HSEB (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_PHYSET_REPSTART_Pos          (11UL)       /*!< REPSTART (Bit 11)                                     */
+ #define R_USB_FS0_PHYSET_REPSTART_Msk          (0x800UL)    /*!< REPSTART (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_PHYSET_REPSEL_Pos            (8UL)        /*!< REPSEL (Bit 8)                                        */
+ #define R_USB_FS0_PHYSET_REPSEL_Msk            (0x300UL)    /*!< REPSEL (Bitfield-Mask: 0x03)                          */
+ #define R_USB_FS0_PHYSET_CLKSEL_Pos            (4UL)        /*!< CLKSEL (Bit 4)                                        */
+ #define R_USB_FS0_PHYSET_CLKSEL_Msk            (0x30UL)     /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
+ #define R_USB_FS0_PHYSET_CDPEN_Pos             (3UL)        /*!< CDPEN (Bit 3)                                         */
+ #define R_USB_FS0_PHYSET_CDPEN_Msk             (0x8UL)      /*!< CDPEN (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PHYSET_PLLRESET_Pos          (1UL)        /*!< PLLRESET (Bit 1)                                      */
+ #define R_USB_FS0_PHYSET_PLLRESET_Msk          (0x2UL)      /*!< PLLRESET (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_PHYSET_DIRPD_Pos             (0UL)        /*!< DIRPD (Bit 0)                                         */
+ #define R_USB_FS0_PHYSET_DIRPD_Msk             (0x1UL)      /*!< DIRPD (Bitfield-Mask: 0x01)                           */
+/* ========================================================  INTSTS0  ======================================================== */
+ #define R_USB_FS0_INTSTS0_VBINT_Pos            (15UL)       /*!< VBINT (Bit 15)                                        */
+ #define R_USB_FS0_INTSTS0_VBINT_Msk            (0x8000UL)   /*!< VBINT (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTSTS0_RESM_Pos             (14UL)       /*!< RESM (Bit 14)                                         */
+ #define R_USB_FS0_INTSTS0_RESM_Msk             (0x4000UL)   /*!< RESM (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_SOFR_Pos             (13UL)       /*!< SOFR (Bit 13)                                         */
+ #define R_USB_FS0_INTSTS0_SOFR_Msk             (0x2000UL)   /*!< SOFR (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_DVST_Pos             (12UL)       /*!< DVST (Bit 12)                                         */
+ #define R_USB_FS0_INTSTS0_DVST_Msk             (0x1000UL)   /*!< DVST (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_CTRT_Pos             (11UL)       /*!< CTRT (Bit 11)                                         */
+ #define R_USB_FS0_INTSTS0_CTRT_Msk             (0x800UL)    /*!< CTRT (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_BEMP_Pos             (10UL)       /*!< BEMP (Bit 10)                                         */
+ #define R_USB_FS0_INTSTS0_BEMP_Msk             (0x400UL)    /*!< BEMP (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_NRDY_Pos             (9UL)        /*!< NRDY (Bit 9)                                          */
+ #define R_USB_FS0_INTSTS0_NRDY_Msk             (0x200UL)    /*!< NRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_BRDY_Pos             (8UL)        /*!< BRDY (Bit 8)                                          */
+ #define R_USB_FS0_INTSTS0_BRDY_Msk             (0x100UL)    /*!< BRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_VBSTS_Pos            (7UL)        /*!< VBSTS (Bit 7)                                         */
+ #define R_USB_FS0_INTSTS0_VBSTS_Msk            (0x80UL)     /*!< VBSTS (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTSTS0_DVSQ_Pos             (4UL)        /*!< DVSQ (Bit 4)                                          */
+ #define R_USB_FS0_INTSTS0_DVSQ_Msk             (0x70UL)     /*!< DVSQ (Bitfield-Mask: 0x07)                            */
+ #define R_USB_FS0_INTSTS0_VALID_Pos            (3UL)        /*!< VALID (Bit 3)                                         */
+ #define R_USB_FS0_INTSTS0_VALID_Msk            (0x8UL)      /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTSTS0_CTSQ_Pos             (0UL)        /*!< CTSQ (Bit 0)                                          */
+ #define R_USB_FS0_INTSTS0_CTSQ_Msk             (0x7UL)      /*!< CTSQ (Bitfield-Mask: 0x07)                            */
+/* ========================================================  INTSTS1  ======================================================== */
+ #define R_USB_FS0_INTSTS1_OVRCR_Pos            (15UL)       /*!< OVRCR (Bit 15)                                        */
+ #define R_USB_FS0_INTSTS1_OVRCR_Msk            (0x8000UL)   /*!< OVRCR (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTSTS1_BCHG_Pos             (14UL)       /*!< BCHG (Bit 14)                                         */
+ #define R_USB_FS0_INTSTS1_BCHG_Msk             (0x4000UL)   /*!< BCHG (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS1_DTCH_Pos             (12UL)       /*!< DTCH (Bit 12)                                         */
+ #define R_USB_FS0_INTSTS1_DTCH_Msk             (0x1000UL)   /*!< DTCH (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS1_ATTCH_Pos            (11UL)       /*!< ATTCH (Bit 11)                                        */
+ #define R_USB_FS0_INTSTS1_ATTCH_Msk            (0x800UL)    /*!< ATTCH (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTSTS1_L1RSMEND_Pos         (9UL)        /*!< L1RSMEND (Bit 9)                                      */
+ #define R_USB_FS0_INTSTS1_L1RSMEND_Msk         (0x200UL)    /*!< L1RSMEND (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_INTSTS1_LPMEND_Pos           (8UL)        /*!< LPMEND (Bit 8)                                        */
+ #define R_USB_FS0_INTSTS1_LPMEND_Msk           (0x100UL)    /*!< LPMEND (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_INTSTS1_EOFERR_Pos           (6UL)        /*!< EOFERR (Bit 6)                                        */
+ #define R_USB_FS0_INTSTS1_EOFERR_Msk           (0x40UL)     /*!< EOFERR (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_INTSTS1_SIGN_Pos             (5UL)        /*!< SIGN (Bit 5)                                          */
+ #define R_USB_FS0_INTSTS1_SIGN_Msk             (0x20UL)     /*!< SIGN (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS1_SACK_Pos             (4UL)        /*!< SACK (Bit 4)                                          */
+ #define R_USB_FS0_INTSTS1_SACK_Msk             (0x10UL)     /*!< SACK (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS1_PDDETINT0_Pos        (0UL)        /*!< PDDETINT0 (Bit 0)                                     */
+ #define R_USB_FS0_INTSTS1_PDDETINT0_Msk        (0x1UL)      /*!< PDDETINT0 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  BRDYSTS  ======================================================== */
+ #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos         (0UL)        /*!< PIPEBRDY (Bit 0)                                      */
+ #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk         (0x1UL)      /*!< PIPEBRDY (Bitfield-Mask: 0x01)                        */
+/* ========================================================  NRDYSTS  ======================================================== */
+ #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos         (0UL)        /*!< PIPENRDY (Bit 0)                                      */
+ #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk         (0x1UL)      /*!< PIPENRDY (Bitfield-Mask: 0x01)                        */
+/* ========================================================  BEMPSTS  ======================================================== */
+ #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos         (0UL)        /*!< PIPEBEMP (Bit 0)                                      */
+ #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk         (0x1UL)      /*!< PIPEBEMP (Bitfield-Mask: 0x01)                        */
+/* ========================================================  FRMNUM  ========================================================= */
+ #define R_USB_FS0_FRMNUM_OVRN_Pos              (15UL)       /*!< OVRN (Bit 15)                                         */
+ #define R_USB_FS0_FRMNUM_OVRN_Msk              (0x8000UL)   /*!< OVRN (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_FRMNUM_CRCE_Pos              (14UL)       /*!< CRCE (Bit 14)                                         */
+ #define R_USB_FS0_FRMNUM_CRCE_Msk              (0x4000UL)   /*!< CRCE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_FRMNUM_FRNM_Pos              (0UL)        /*!< FRNM (Bit 0)                                          */
+ #define R_USB_FS0_FRMNUM_FRNM_Msk              (0x7ffUL)    /*!< FRNM (Bitfield-Mask: 0x7ff)                           */
+/* ========================================================  UFRMNUM  ======================================================== */
+ #define R_USB_FS0_UFRMNUM_DVCHG_Pos            (15UL)       /*!< DVCHG (Bit 15)                                        */
+ #define R_USB_FS0_UFRMNUM_DVCHG_Msk            (0x8000UL)   /*!< DVCHG (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_UFRMNUM_UFRNM_Pos            (0UL)        /*!< UFRNM (Bit 0)                                         */
+ #define R_USB_FS0_UFRMNUM_UFRNM_Msk            (0x7UL)      /*!< UFRNM (Bitfield-Mask: 0x07)                           */
+/* ========================================================  USBADDR  ======================================================== */
+ #define R_USB_FS0_USBADDR_STSRECOV0_Pos        (8UL)        /*!< STSRECOV0 (Bit 8)                                     */
+ #define R_USB_FS0_USBADDR_STSRECOV0_Msk        (0x700UL)    /*!< STSRECOV0 (Bitfield-Mask: 0x07)                       */
+ #define R_USB_FS0_USBADDR_USBADDR_Pos          (0UL)        /*!< USBADDR (Bit 0)                                       */
+ #define R_USB_FS0_USBADDR_USBADDR_Msk          (0x7fUL)     /*!< USBADDR (Bitfield-Mask: 0x7f)                         */
+/* ========================================================  USBREQ  ========================================================= */
+ #define R_USB_FS0_USBREQ_BREQUEST_Pos          (8UL)        /*!< BREQUEST (Bit 8)                                      */
+ #define R_USB_FS0_USBREQ_BREQUEST_Msk          (0xff00UL)   /*!< BREQUEST (Bitfield-Mask: 0xff)                        */
+ #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos     (0UL)        /*!< BMREQUESTTYPE (Bit 0)                                 */
+ #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk     (0xffUL)     /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff)                   */
+/* ========================================================  USBVAL  ========================================================= */
+ #define R_USB_FS0_USBVAL_WVALUE_Pos            (0UL)        /*!< WVALUE (Bit 0)                                        */
+ #define R_USB_FS0_USBVAL_WVALUE_Msk            (0xffffUL)   /*!< WVALUE (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  USBINDX  ======================================================== */
+ #define R_USB_FS0_USBINDX_WINDEX_Pos           (0UL)        /*!< WINDEX (Bit 0)                                        */
+ #define R_USB_FS0_USBINDX_WINDEX_Msk           (0xffffUL)   /*!< WINDEX (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  USBLENG  ======================================================== */
+ #define R_USB_FS0_USBLENG_WLENGTH_Pos          (0UL)        /*!< WLENGTH (Bit 0)                                       */
+ #define R_USB_FS0_USBLENG_WLENGTH_Msk          (0xffffUL)   /*!< WLENGTH (Bitfield-Mask: 0xffff)                       */
+/* ========================================================  DCPCFG  ========================================================= */
+ #define R_USB_FS0_DCPCFG_CNTMD_Pos             (8UL)        /*!< CNTMD (Bit 8)                                         */
+ #define R_USB_FS0_DCPCFG_CNTMD_Msk             (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DCPCFG_SHTNAK_Pos            (7UL)        /*!< SHTNAK (Bit 7)                                        */
+ #define R_USB_FS0_DCPCFG_SHTNAK_Msk            (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DCPCFG_DIR_Pos               (4UL)        /*!< DIR (Bit 4)                                           */
+ #define R_USB_FS0_DCPCFG_DIR_Msk               (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
+/* ========================================================  DCPMAXP  ======================================================== */
+ #define R_USB_FS0_DCPMAXP_DEVSEL_Pos           (12UL)       /*!< DEVSEL (Bit 12)                                       */
+ #define R_USB_FS0_DCPMAXP_DEVSEL_Msk           (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
+ #define R_USB_FS0_DCPMAXP_MXPS_Pos             (0UL)        /*!< MXPS (Bit 0)                                          */
+ #define R_USB_FS0_DCPMAXP_MXPS_Msk             (0x7fUL)     /*!< MXPS (Bitfield-Mask: 0x7f)                            */
+/* ========================================================  DCPCTR  ========================================================= */
+ #define R_USB_FS0_DCPCTR_BSTS_Pos              (15UL)       /*!< BSTS (Bit 15)                                         */
+ #define R_USB_FS0_DCPCTR_BSTS_Msk              (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_DCPCTR_SUREQ_Pos             (14UL)       /*!< SUREQ (Bit 14)                                        */
+ #define R_USB_FS0_DCPCTR_SUREQ_Msk             (0x4000UL)   /*!< SUREQ (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DCPCTR_SUREQCLR_Pos          (11UL)       /*!< SUREQCLR (Bit 11)                                     */
+ #define R_USB_FS0_DCPCTR_SUREQCLR_Msk          (0x800UL)    /*!< SUREQCLR (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_DCPCTR_SQCLR_Pos             (8UL)        /*!< SQCLR (Bit 8)                                         */
+ #define R_USB_FS0_DCPCTR_SQCLR_Msk             (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DCPCTR_SQSET_Pos             (7UL)        /*!< SQSET (Bit 7)                                         */
+ #define R_USB_FS0_DCPCTR_SQSET_Msk             (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DCPCTR_SQMON_Pos             (6UL)        /*!< SQMON (Bit 6)                                         */
+ #define R_USB_FS0_DCPCTR_SQMON_Msk             (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DCPCTR_PBUSY_Pos             (5UL)        /*!< PBUSY (Bit 5)                                         */
+ #define R_USB_FS0_DCPCTR_PBUSY_Msk             (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DCPCTR_CCPL_Pos              (2UL)        /*!< CCPL (Bit 2)                                          */
+ #define R_USB_FS0_DCPCTR_CCPL_Msk              (0x4UL)      /*!< CCPL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_DCPCTR_PID_Pos               (0UL)        /*!< PID (Bit 0)                                           */
+ #define R_USB_FS0_DCPCTR_PID_Msk               (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
+/* ========================================================  PIPESEL  ======================================================== */
+ #define R_USB_FS0_PIPESEL_PIPESEL_Pos          (0UL)        /*!< PIPESEL (Bit 0)                                       */
+ #define R_USB_FS0_PIPESEL_PIPESEL_Msk          (0xfUL)      /*!< PIPESEL (Bitfield-Mask: 0x0f)                         */
+/* ========================================================  PIPECFG  ======================================================== */
+ #define R_USB_FS0_PIPECFG_TYPE_Pos             (14UL)       /*!< TYPE (Bit 14)                                         */
+ #define R_USB_FS0_PIPECFG_TYPE_Msk             (0xc000UL)   /*!< TYPE (Bitfield-Mask: 0x03)                            */
+ #define R_USB_FS0_PIPECFG_BFRE_Pos             (10UL)       /*!< BFRE (Bit 10)                                         */
+ #define R_USB_FS0_PIPECFG_BFRE_Msk             (0x400UL)    /*!< BFRE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_PIPECFG_DBLB_Pos             (9UL)        /*!< DBLB (Bit 9)                                          */
+ #define R_USB_FS0_PIPECFG_DBLB_Msk             (0x200UL)    /*!< DBLB (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_PIPECFG_SHTNAK_Pos           (7UL)        /*!< SHTNAK (Bit 7)                                        */
+ #define R_USB_FS0_PIPECFG_SHTNAK_Msk           (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_PIPECFG_DIR_Pos              (4UL)        /*!< DIR (Bit 4)                                           */
+ #define R_USB_FS0_PIPECFG_DIR_Msk              (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
+ #define R_USB_FS0_PIPECFG_EPNUM_Pos            (0UL)        /*!< EPNUM (Bit 0)                                         */
+ #define R_USB_FS0_PIPECFG_EPNUM_Msk            (0xfUL)      /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
+/* =======================================================  PIPEMAXP  ======================================================== */
+ #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos          (12UL)       /*!< DEVSEL (Bit 12)                                       */
+ #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk          (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
+ #define R_USB_FS0_PIPEMAXP_MXPS_Pos            (0UL)        /*!< MXPS (Bit 0)                                          */
+ #define R_USB_FS0_PIPEMAXP_MXPS_Msk            (0x1ffUL)    /*!< MXPS (Bitfield-Mask: 0x1ff)                           */
+/* =======================================================  PIPEPERI  ======================================================== */
+ #define R_USB_FS0_PIPEPERI_IFIS_Pos            (12UL)       /*!< IFIS (Bit 12)                                         */
+ #define R_USB_FS0_PIPEPERI_IFIS_Msk            (0x1000UL)   /*!< IFIS (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_PIPEPERI_IITV_Pos            (0UL)        /*!< IITV (Bit 0)                                          */
+ #define R_USB_FS0_PIPEPERI_IITV_Msk            (0x7UL)      /*!< IITV (Bitfield-Mask: 0x07)                            */
+/* =======================================================  PIPE_CTR  ======================================================== */
+ #define R_USB_FS0_PIPE_CTR_BSTS_Pos            (15UL)       /*!< BSTS (Bit 15)                                         */
+ #define R_USB_FS0_PIPE_CTR_BSTS_Msk            (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_PIPE_CTR_INBUFM_Pos          (14UL)       /*!< INBUFM (Bit 14)                                       */
+ #define R_USB_FS0_PIPE_CTR_INBUFM_Msk          (0x4000UL)   /*!< INBUFM (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_PIPE_CTR_CSCLR_Pos           (13UL)       /*!< CSCLR (Bit 13)                                        */
+ #define R_USB_FS0_PIPE_CTR_CSCLR_Msk           (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_CSSTS_Pos           (12UL)       /*!< CSSTS (Bit 12)                                        */
+ #define R_USB_FS0_PIPE_CTR_CSSTS_Msk           (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_ATREPM_Pos          (10UL)       /*!< ATREPM (Bit 10)                                       */
+ #define R_USB_FS0_PIPE_CTR_ATREPM_Msk          (0x400UL)    /*!< ATREPM (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_PIPE_CTR_ACLRM_Pos           (9UL)        /*!< ACLRM (Bit 9)                                         */
+ #define R_USB_FS0_PIPE_CTR_ACLRM_Msk           (0x200UL)    /*!< ACLRM (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_SQCLR_Pos           (8UL)        /*!< SQCLR (Bit 8)                                         */
+ #define R_USB_FS0_PIPE_CTR_SQCLR_Msk           (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_SQSET_Pos           (7UL)        /*!< SQSET (Bit 7)                                         */
+ #define R_USB_FS0_PIPE_CTR_SQSET_Msk           (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_SQMON_Pos           (6UL)        /*!< SQMON (Bit 6)                                         */
+ #define R_USB_FS0_PIPE_CTR_SQMON_Msk           (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_PBUSY_Pos           (5UL)        /*!< PBUSY (Bit 5)                                         */
+ #define R_USB_FS0_PIPE_CTR_PBUSY_Msk           (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_PID_Pos             (0UL)        /*!< PID (Bit 0)                                           */
+ #define R_USB_FS0_PIPE_CTR_PID_Msk             (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
+/* ========================================================  DEVADD  ========================================================= */
+ #define R_USB_FS0_DEVADD_UPPHUB_Pos            (11UL)       /*!< UPPHUB (Bit 11)                                       */
+ #define R_USB_FS0_DEVADD_UPPHUB_Msk            (0x7800UL)   /*!< UPPHUB (Bitfield-Mask: 0x0f)                          */
+ #define R_USB_FS0_DEVADD_HUBPORT_Pos           (8UL)        /*!< HUBPORT (Bit 8)                                       */
+ #define R_USB_FS0_DEVADD_HUBPORT_Msk           (0x700UL)    /*!< HUBPORT (Bitfield-Mask: 0x07)                         */
+ #define R_USB_FS0_DEVADD_USBSPD_Pos            (6UL)        /*!< USBSPD (Bit 6)                                        */
+ #define R_USB_FS0_DEVADD_USBSPD_Msk            (0xc0UL)     /*!< USBSPD (Bitfield-Mask: 0x03)                          */
+/* ======================================================  USBBCCTRL0  ======================================================= */
+ #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos     (9UL)        /*!< PDDETSTS0 (Bit 9)                                     */
+ #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk     (0x200UL)    /*!< PDDETSTS0 (Bitfield-Mask: 0x01)                       */
+ #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos    (8UL)        /*!< CHGDETSTS0 (Bit 8)                                    */
+ #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk    (0x100UL)    /*!< CHGDETSTS0 (Bitfield-Mask: 0x01)                      */
+ #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos      (7UL)        /*!< BATCHGE0 (Bit 7)                                      */
+ #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk      (0x80UL)     /*!< BATCHGE0 (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos      (5UL)        /*!< VDMSRCE0 (Bit 5)                                      */
+ #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk      (0x20UL)     /*!< VDMSRCE0 (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos     (4UL)        /*!< IDPSINKE0 (Bit 4)                                     */
+ #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk     (0x10UL)     /*!< IDPSINKE0 (Bitfield-Mask: 0x01)                       */
+ #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos      (3UL)        /*!< VDPSRCE0 (Bit 3)                                      */
+ #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk      (0x8UL)      /*!< VDPSRCE0 (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos     (2UL)        /*!< IDMSINKE0 (Bit 2)                                     */
+ #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk     (0x4UL)      /*!< IDMSINKE0 (Bitfield-Mask: 0x01)                       */
+ #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos      (1UL)        /*!< IDPSRCE0 (Bit 1)                                      */
+ #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk      (0x2UL)      /*!< IDPSRCE0 (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos        (0UL)        /*!< RPDME0 (Bit 0)                                        */
+ #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk        (0x1UL)      /*!< RPDME0 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  UCKSEL  ========================================================= */
+ #define R_USB_FS0_UCKSEL_UCKSELC_Pos           (0UL)        /*!< UCKSELC (Bit 0)                                       */
+ #define R_USB_FS0_UCKSEL_UCKSELC_Msk           (0x1UL)      /*!< UCKSELC (Bitfield-Mask: 0x01)                         */
+/* =========================================================  USBMC  ========================================================= */
+ #define R_USB_FS0_USBMC_VDCEN_Pos              (7UL)        /*!< VDCEN (Bit 7)                                         */
+ #define R_USB_FS0_USBMC_VDCEN_Msk              (0x80UL)     /*!< VDCEN (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_USBMC_VDDUSBE_Pos            (0UL)        /*!< VDDUSBE (Bit 0)                                       */
+ #define R_USB_FS0_USBMC_VDDUSBE_Msk            (0x1UL)      /*!< VDDUSBE (Bitfield-Mask: 0x01)                         */
+/* ========================================================  PHYSLEW  ======================================================== */
+ #define R_USB_FS0_PHYSLEW_SLEWF01_Pos          (3UL)        /*!< SLEWF01 (Bit 3)                                       */
+ #define R_USB_FS0_PHYSLEW_SLEWF01_Msk          (0x8UL)      /*!< SLEWF01 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_PHYSLEW_SLEWF00_Pos          (2UL)        /*!< SLEWF00 (Bit 2)                                       */
+ #define R_USB_FS0_PHYSLEW_SLEWF00_Msk          (0x4UL)      /*!< SLEWF00 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_PHYSLEW_SLEWR01_Pos          (1UL)        /*!< SLEWR01 (Bit 1)                                       */
+ #define R_USB_FS0_PHYSLEW_SLEWR01_Msk          (0x2UL)      /*!< SLEWR01 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_PHYSLEW_SLEWR00_Pos          (0UL)        /*!< SLEWR00 (Bit 0)                                       */
+ #define R_USB_FS0_PHYSLEW_SLEWR00_Msk          (0x1UL)      /*!< SLEWR00 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  LPCTRL  ========================================================= */
+ #define R_USB_FS0_LPCTRL_HWUPM_Pos             (7UL)        /*!< HWUPM (Bit 7)                                         */
+ #define R_USB_FS0_LPCTRL_HWUPM_Msk             (0x80UL)     /*!< HWUPM (Bitfield-Mask: 0x01)                           */
+/* =========================================================  LPSTS  ========================================================= */
+ #define R_USB_FS0_LPSTS_SUSPENDM_Pos           (14UL)       /*!< SUSPENDM (Bit 14)                                     */
+ #define R_USB_FS0_LPSTS_SUSPENDM_Msk           (0x4000UL)   /*!< SUSPENDM (Bitfield-Mask: 0x01)                        */
+/* ========================================================  BCCTRL  ========================================================= */
+ #define R_USB_FS0_BCCTRL_PDDETSTS_Pos          (9UL)        /*!< PDDETSTS (Bit 9)                                      */
+ #define R_USB_FS0_BCCTRL_PDDETSTS_Msk          (0x200UL)    /*!< PDDETSTS (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos         (8UL)        /*!< CHGDETSTS (Bit 8)                                     */
+ #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk         (0x100UL)    /*!< CHGDETSTS (Bitfield-Mask: 0x01)                       */
+ #define R_USB_FS0_BCCTRL_DCPMODE_Pos           (5UL)        /*!< DCPMODE (Bit 5)                                       */
+ #define R_USB_FS0_BCCTRL_DCPMODE_Msk           (0x20UL)     /*!< DCPMODE (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_BCCTRL_VDMSRCE_Pos           (4UL)        /*!< VDMSRCE (Bit 4)                                       */
+ #define R_USB_FS0_BCCTRL_VDMSRCE_Msk           (0x10UL)     /*!< VDMSRCE (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_BCCTRL_IDPSINKE_Pos          (3UL)        /*!< IDPSINKE (Bit 3)                                      */
+ #define R_USB_FS0_BCCTRL_IDPSINKE_Msk          (0x8UL)      /*!< IDPSINKE (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_BCCTRL_VDPSRCE_Pos           (2UL)        /*!< VDPSRCE (Bit 2)                                       */
+ #define R_USB_FS0_BCCTRL_VDPSRCE_Msk           (0x4UL)      /*!< VDPSRCE (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_BCCTRL_IDMSINKE_Pos          (1UL)        /*!< IDMSINKE (Bit 1)                                      */
+ #define R_USB_FS0_BCCTRL_IDMSINKE_Msk          (0x2UL)      /*!< IDMSINKE (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_BCCTRL_IDPSRCE_Pos           (0UL)        /*!< IDPSRCE (Bit 0)                                       */
+ #define R_USB_FS0_BCCTRL_IDPSRCE_Msk           (0x1UL)      /*!< IDPSRCE (Bitfield-Mask: 0x01)                         */
+/* =======================================================  PL1CTRL1  ======================================================== */
+ #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos         (14UL)       /*!< L1EXTMD (Bit 14)                                      */
+ #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk         (0x4000UL)   /*!< L1EXTMD (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos         (8UL)        /*!< HIRDTHR (Bit 8)                                       */
+ #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk         (0xf00UL)    /*!< HIRDTHR (Bitfield-Mask: 0x0f)                         */
+ #define R_USB_FS0_PL1CTRL1_DVSQ_Pos            (4UL)        /*!< DVSQ (Bit 4)                                          */
+ #define R_USB_FS0_PL1CTRL1_DVSQ_Msk            (0xf0UL)     /*!< DVSQ (Bitfield-Mask: 0x0f)                            */
+ #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos        (3UL)        /*!< L1NEGOMD (Bit 3)                                      */
+ #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk        (0x8UL)      /*!< L1NEGOMD (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos        (1UL)        /*!< L1RESPMD (Bit 1)                                      */
+ #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk        (0x6UL)      /*!< L1RESPMD (Bitfield-Mask: 0x03)                        */
+ #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos        (0UL)        /*!< L1RESPEN (Bit 0)                                      */
+ #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk        (0x1UL)      /*!< L1RESPEN (Bitfield-Mask: 0x01)                        */
+/* =======================================================  PL1CTRL2  ======================================================== */
+ #define R_USB_FS0_PL1CTRL2_RWEMON_Pos          (12UL)       /*!< RWEMON (Bit 12)                                       */
+ #define R_USB_FS0_PL1CTRL2_RWEMON_Msk          (0x1000UL)   /*!< RWEMON (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos         (8UL)        /*!< HIRDMON (Bit 8)                                       */
+ #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk         (0xf00UL)    /*!< HIRDMON (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  HL1CTRL1  ======================================================== */
+ #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos        (1UL)        /*!< L1STATUS (Bit 1)                                      */
+ #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk        (0x6UL)      /*!< L1STATUS (Bitfield-Mask: 0x03)                        */
+ #define R_USB_FS0_HL1CTRL1_L1REQ_Pos           (0UL)        /*!< L1REQ (Bit 0)                                         */
+ #define R_USB_FS0_HL1CTRL1_L1REQ_Msk           (0x1UL)      /*!< L1REQ (Bitfield-Mask: 0x01)                           */
+/* =======================================================  HL1CTRL2  ======================================================== */
+ #define R_USB_FS0_HL1CTRL2_BESL_Pos            (15UL)       /*!< BESL (Bit 15)                                         */
+ #define R_USB_FS0_HL1CTRL2_BESL_Msk            (0x8000UL)   /*!< BESL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_HL1CTRL2_L1RWE_Pos           (12UL)       /*!< L1RWE (Bit 12)                                        */
+ #define R_USB_FS0_HL1CTRL2_L1RWE_Msk           (0x1000UL)   /*!< L1RWE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_HL1CTRL2_HIRD_Pos            (8UL)        /*!< HIRD (Bit 8)                                          */
+ #define R_USB_FS0_HL1CTRL2_HIRD_Msk            (0xf00UL)    /*!< HIRD (Bitfield-Mask: 0x0f)                            */
+ #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos          (0UL)        /*!< L1ADDR (Bit 0)                                        */
+ #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk          (0xfUL)      /*!< L1ADDR (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  DPUSR0R  ======================================================== */
+ #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos         (23UL)       /*!< DVBSTSHM (Bit 23)                                     */
+ #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk         (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos          (21UL)       /*!< DOVCBHM (Bit 21)                                      */
+ #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk          (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos          (20UL)       /*!< DOVCAHM (Bit 20)                                      */
+ #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk          (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DPUSR1R  ======================================================== */
+ #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos          (23UL)       /*!< DVBSTSH (Bit 23)                                      */
+ #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk          (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR1R_DOVCBH_Pos           (21UL)       /*!< DOVCBH (Bit 21)                                       */
+ #define R_USB_FS0_DPUSR1R_DOVCBH_Msk           (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR1R_DOVCAH_Pos           (20UL)       /*!< DOVCAH (Bit 20)                                       */
+ #define R_USB_FS0_DPUSR1R_DOVCAH_Msk           (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos         (7UL)        /*!< DVBSTSHE (Bit 7)                                      */
+ #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk         (0x80UL)     /*!< DVBSTSHE (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos          (5UL)        /*!< DOVCBHE (Bit 5)                                       */
+ #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk          (0x20UL)     /*!< DOVCBHE (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos          (4UL)        /*!< DOVCAHE (Bit 4)                                       */
+ #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk          (0x10UL)     /*!< DOVCAHE (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DPUSR2R  ======================================================== */
+ #define R_USB_FS0_DPUSR2R_DMINTE_Pos           (9UL)        /*!< DMINTE (Bit 9)                                        */
+ #define R_USB_FS0_DPUSR2R_DMINTE_Msk           (0x200UL)    /*!< DMINTE (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR2R_DPINTE_Pos           (8UL)        /*!< DPINTE (Bit 8)                                        */
+ #define R_USB_FS0_DPUSR2R_DPINTE_Msk           (0x100UL)    /*!< DPINTE (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR2R_DMVAL_Pos            (5UL)        /*!< DMVAL (Bit 5)                                         */
+ #define R_USB_FS0_DPUSR2R_DMVAL_Msk            (0x20UL)     /*!< DMVAL (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DPUSR2R_DPVAL_Pos            (4UL)        /*!< DPVAL (Bit 4)                                         */
+ #define R_USB_FS0_DPUSR2R_DPVAL_Msk            (0x10UL)     /*!< DPVAL (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DPUSR2R_DMINT_Pos            (1UL)        /*!< DMINT (Bit 1)                                         */
+ #define R_USB_FS0_DPUSR2R_DMINT_Msk            (0x2UL)      /*!< DMINT (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DPUSR2R_DPINT_Pos            (0UL)        /*!< DPINT (Bit 0)                                         */
+ #define R_USB_FS0_DPUSR2R_DPINT_Msk            (0x1UL)      /*!< DPINT (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DPUSRCR  ======================================================== */
+ #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos         (1UL)        /*!< FIXPHYPD (Bit 1)                                      */
+ #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk         (0x2UL)      /*!< FIXPHYPD (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_DPUSRCR_FIXPHY_Pos           (0UL)        /*!< FIXPHY (Bit 0)                                        */
+ #define R_USB_FS0_DPUSRCR_FIXPHY_Msk           (0x1UL)      /*!< FIXPHY (Bitfield-Mask: 0x01)                          */
+/* ======================================================  DPUSR0R_FS  ======================================================= */
+ #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos       (23UL)       /*!< DVBSTS0 (Bit 23)                                      */
+ #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk       (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos        (21UL)       /*!< DOVCB0 (Bit 21)                                       */
+ #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk        (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos        (20UL)       /*!< DOVCA0 (Bit 20)                                       */
+ #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk        (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR0R_FS_DM0_Pos           (17UL)       /*!< DM0 (Bit 17)                                          */
+ #define R_USB_FS0_DPUSR0R_FS_DM0_Msk           (0x20000UL)  /*!< DM0 (Bitfield-Mask: 0x01)                             */
+ #define R_USB_FS0_DPUSR0R_FS_DP0_Pos           (16UL)       /*!< DP0 (Bit 16)                                          */
+ #define R_USB_FS0_DPUSR0R_FS_DP0_Msk           (0x10000UL)  /*!< DP0 (Bitfield-Mask: 0x01)                             */
+ #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos       (4UL)        /*!< FIXPHY0 (Bit 4)                                       */
+ #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk       (0x10UL)     /*!< FIXPHY0 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos         (3UL)        /*!< DRPD0 (Bit 3)                                         */
+ #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk         (0x8UL)      /*!< DRPD0 (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos         (1UL)        /*!< RPUE0 (Bit 1)                                         */
+ #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk         (0x2UL)      /*!< RPUE0 (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos         (0UL)        /*!< SRPC0 (Bit 0)                                         */
+ #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk         (0x1UL)      /*!< SRPC0 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  DPUSR1R_FS  ======================================================= */
+ #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos       (23UL)       /*!< DVBINT0 (Bit 23)                                      */
+ #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk       (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos      (21UL)       /*!< DOVRCRB0 (Bit 21)                                     */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk      (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos      (20UL)       /*!< DOVRCRA0 (Bit 20)                                     */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk      (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos        (17UL)       /*!< DMINT0 (Bit 17)                                       */
+ #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk        (0x20000UL)  /*!< DMINT0 (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos        (16UL)       /*!< DPINT0 (Bit 16)                                       */
+ #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk        (0x10000UL)  /*!< DPINT0 (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos        (7UL)        /*!< DVBSE0 (Bit 7)                                        */
+ #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk        (0x80UL)     /*!< DVBSE0 (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos     (5UL)        /*!< DOVRCRBE0 (Bit 5)                                     */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk     (0x20UL)     /*!< DOVRCRBE0 (Bitfield-Mask: 0x01)                       */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos     (4UL)        /*!< DOVRCRAE0 (Bit 4)                                     */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk     (0x10UL)     /*!< DOVRCRAE0 (Bitfield-Mask: 0x01)                       */
+ #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos       (1UL)        /*!< DMINTE0 (Bit 1)                                       */
+ #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk       (0x2UL)      /*!< DMINTE0 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos       (0UL)        /*!< DPINTE0 (Bit 0)                                       */
+ #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk       (0x1UL)      /*!< DPINTE0 (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                           R_WDT                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  WDTRR  ========================================================= */
+ #define R_WDT_WDTRR_WDTRR_Pos        (0UL)      /*!< WDTRR (Bit 0)                                         */
+ #define R_WDT_WDTRR_WDTRR_Msk        (0xffUL)   /*!< WDTRR (Bitfield-Mask: 0xff)                           */
+/* =========================================================  WDTCR  ========================================================= */
+ #define R_WDT_WDTCR_RPSS_Pos         (12UL)     /*!< RPSS (Bit 12)                                         */
+ #define R_WDT_WDTCR_RPSS_Msk         (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
+ #define R_WDT_WDTCR_RPES_Pos         (8UL)      /*!< RPES (Bit 8)                                          */
+ #define R_WDT_WDTCR_RPES_Msk         (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
+ #define R_WDT_WDTCR_CKS_Pos          (4UL)      /*!< CKS (Bit 4)                                           */
+ #define R_WDT_WDTCR_CKS_Msk          (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
+ #define R_WDT_WDTCR_TOPS_Pos         (0UL)      /*!< TOPS (Bit 0)                                          */
+ #define R_WDT_WDTCR_TOPS_Msk         (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  WDTSR  ========================================================= */
+ #define R_WDT_WDTSR_REFEF_Pos        (15UL)     /*!< REFEF (Bit 15)                                        */
+ #define R_WDT_WDTSR_REFEF_Msk        (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
+ #define R_WDT_WDTSR_UNDFF_Pos        (14UL)     /*!< UNDFF (Bit 14)                                        */
+ #define R_WDT_WDTSR_UNDFF_Msk        (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
+ #define R_WDT_WDTSR_CNTVAL_Pos       (0UL)      /*!< CNTVAL (Bit 0)                                        */
+ #define R_WDT_WDTSR_CNTVAL_Msk       (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
+/* ========================================================  WDTRCR  ========================================================= */
+ #define R_WDT_WDTRCR_RSTIRQS_Pos     (7UL)      /*!< RSTIRQS (Bit 7)                                       */
+ #define R_WDT_WDTRCR_RSTIRQS_Msk     (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
+/* =======================================================  WDTCSTPR  ======================================================== */
+ #define R_WDT_WDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
+ #define R_WDT_WDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_TZF                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  TZFOAD  ========================================================= */
+ #define R_TZF_TZFOAD_OAD_Pos       (0UL)      /*!< OAD (Bit 0)                                           */
+ #define R_TZF_TZFOAD_OAD_Msk       (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
+ #define R_TZF_TZFOAD_KEY_Pos       (8UL)      /*!< KEY (Bit 8)                                           */
+ #define R_TZF_TZFOAD_KEY_Msk       (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
+/* =========================================================  TZFPT  ========================================================= */
+ #define R_TZF_TZFPT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
+ #define R_TZF_TZFPT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
+ #define R_TZF_TZFPT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
+ #define R_TZF_TZFPT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
+/* ========================================================  TZFSAR  ========================================================= */
+ #define R_TZF_TZFSAR_TZFSA0_Pos    (0UL)      /*!< TZFSA0 (Bit 0)                                        */
+ #define R_TZF_TZFSAR_TZFSA0_Msk    (0x1UL)    /*!< TZFSA0 (Bitfield-Mask: 0x01)                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CACHE                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CCACTL  ========================================================= */
+ #define R_CACHE_CCACTL_ENC_Pos     (0UL)    /*!< ENC (Bit 0)                                           */
+ #define R_CACHE_CCACTL_ENC_Msk     (0x1UL)  /*!< ENC (Bitfield-Mask: 0x01)                             */
+/* ========================================================  CCAFCT  ========================================================= */
+ #define R_CACHE_CCAFCT_FC_Pos      (0UL)    /*!< FC (Bit 0)                                            */
+ #define R_CACHE_CCAFCT_FC_Msk      (0x1UL)  /*!< FC (Bitfield-Mask: 0x01)                              */
+/* ========================================================  CCALCF  ========================================================= */
+ #define R_CACHE_CCALCF_CC_Pos      (0UL)    /*!< CC (Bit 0)                                            */
+ #define R_CACHE_CCALCF_CC_Msk      (0x3UL)  /*!< CC (Bitfield-Mask: 0x03)                              */
+/* ========================================================  SCACTL  ========================================================= */
+ #define R_CACHE_SCACTL_ENS_Pos     (0UL)    /*!< ENS (Bit 0)                                           */
+ #define R_CACHE_SCACTL_ENS_Msk     (0x1UL)  /*!< ENS (Bitfield-Mask: 0x01)                             */
+/* ========================================================  SCAFCT  ========================================================= */
+ #define R_CACHE_SCAFCT_FS_Pos      (0UL)    /*!< FS (Bit 0)                                            */
+ #define R_CACHE_SCAFCT_FS_Msk      (0x1UL)  /*!< FS (Bitfield-Mask: 0x01)                              */
+/* ========================================================  SCALCF  ========================================================= */
+ #define R_CACHE_SCALCF_CS_Pos      (0UL)    /*!< CS (Bit 0)                                            */
+ #define R_CACHE_SCALCF_CS_Msk      (0x3UL)  /*!< CS (Bitfield-Mask: 0x03)                              */
+/* ========================================================  CAPOAD  ========================================================= */
+ #define R_CACHE_CAPOAD_OAD_Pos     (0UL)    /*!< OAD (Bit 0)                                           */
+ #define R_CACHE_CAPOAD_OAD_Msk     (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
+/* ========================================================  CAPRCR  ========================================================= */
+ #define R_CACHE_CAPRCR_PRCR_Pos    (0UL)    /*!< PRCR (Bit 0)                                          */
+ #define R_CACHE_CAPRCR_PRCR_Msk    (0x1UL)  /*!< PRCR (Bitfield-Mask: 0x01)                            */
+ #define R_CACHE_CAPRCR_KW_Pos      (1UL)    /*!< KW (Bit 1)                                            */
+ #define R_CACHE_CAPRCR_KW_Msk      (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CPSCU                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  CSAR  ========================================================== */
+ #define R_CPSCU_CSAR_CACHESA_Pos            (0UL)          /*!< CACHESA (Bit 0)                                       */
+ #define R_CPSCU_CSAR_CACHESA_Msk            (0x1UL)        /*!< CACHESA (Bitfield-Mask: 0x01)                         */
+ #define R_CPSCU_CSAR_CACHELSA_Pos           (1UL)          /*!< CACHELSA (Bit 1)                                      */
+ #define R_CPSCU_CSAR_CACHELSA_Msk           (0x2UL)        /*!< CACHELSA (Bitfield-Mask: 0x01)                        */
+ #define R_CPSCU_CSAR_CACHEESA_Pos           (2UL)          /*!< CACHEESA (Bit 2)                                      */
+ #define R_CPSCU_CSAR_CACHEESA_Msk           (0x4UL)        /*!< CACHEESA (Bitfield-Mask: 0x01)                        */
+/* ========================================================  SRAMSAR  ======================================================== */
+ #define R_CPSCU_SRAMSAR_SRAMSA0_Pos         (0UL)          /*!< SRAMSA0 (Bit 0)                                       */
+ #define R_CPSCU_SRAMSAR_SRAMSA0_Msk         (0x1UL)        /*!< SRAMSA0 (Bitfield-Mask: 0x01)                         */
+ #define R_CPSCU_SRAMSAR_SRAMSA1_Pos         (1UL)          /*!< SRAMSA1 (Bit 1)                                       */
+ #define R_CPSCU_SRAMSAR_SRAMSA1_Msk         (0x2UL)        /*!< SRAMSA1 (Bitfield-Mask: 0x01)                         */
+ #define R_CPSCU_SRAMSAR_SRAMSA2_Pos         (2UL)          /*!< SRAMSA2 (Bit 2)                                       */
+ #define R_CPSCU_SRAMSAR_SRAMSA2_Msk         (0x4UL)        /*!< SRAMSA2 (Bitfield-Mask: 0x01)                         */
+/* =======================================================  STBRAMSAR  ======================================================= */
+ #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos       (0UL)          /*!< NSBSTBR (Bit 0)                                       */
+ #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk       (0xfUL)        /*!< NSBSTBR (Bitfield-Mask: 0x0f)                         */
+/* ========================================================  DTCSAR  ========================================================= */
+ #define R_CPSCU_DTCSAR_DTCSTSA_Pos          (0UL)          /*!< DTCSTSA (Bit 0)                                       */
+ #define R_CPSCU_DTCSAR_DTCSTSA_Msk          (0x1UL)        /*!< DTCSTSA (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DMACSAR  ======================================================== */
+ #define R_CPSCU_DMACSAR_DMASTSA_Pos         (0UL)          /*!< DMASTSA (Bit 0)                                       */
+ #define R_CPSCU_DMACSAR_DMASTSA_Msk         (0x1UL)        /*!< DMASTSA (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ICUSARA  ======================================================== */
+ #define R_CPSCU_ICUSARA_SAIRQCRn_Pos        (0UL)          /*!< SAIRQCRn (Bit 0)                                      */
+ #define R_CPSCU_ICUSARA_SAIRQCRn_Msk        (0xffffUL)     /*!< SAIRQCRn (Bitfield-Mask: 0xffff)                      */
+/* ========================================================  ICUSARB  ======================================================== */
+ #define R_CPSCU_ICUSARB_SANMI_Pos           (0UL)          /*!< SANMI (Bit 0)                                         */
+ #define R_CPSCU_ICUSARB_SANMI_Msk           (0x1UL)        /*!< SANMI (Bitfield-Mask: 0x01)                           */
+/* ========================================================  ICUSARC  ======================================================== */
+ #define R_CPSCU_ICUSARC_SADMACn_Pos         (0UL)          /*!< SADMACn (Bit 0)                                       */
+ #define R_CPSCU_ICUSARC_SADMACn_Msk         (0xffUL)       /*!< SADMACn (Bitfield-Mask: 0xff)                         */
+/* ========================================================  ICUSARD  ======================================================== */
+ #define R_CPSCU_ICUSARD_SASELSR0_Pos        (0UL)          /*!< SASELSR0 (Bit 0)                                      */
+ #define R_CPSCU_ICUSARD_SASELSR0_Msk        (0x1UL)        /*!< SASELSR0 (Bitfield-Mask: 0x01)                        */
+/* ========================================================  ICUSARE  ======================================================== */
+ #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos       (16UL)         /*!< SAIWDTWUP (Bit 16)                                    */
+ #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk       (0x10000UL)    /*!< SAIWDTWUP (Bitfield-Mask: 0x01)                       */
+ #define R_CPSCU_ICUSARE_SALVD1WUP_Pos       (18UL)         /*!< SALVD1WUP (Bit 18)                                    */
+ #define R_CPSCU_ICUSARE_SALVD1WUP_Msk       (0x40000UL)    /*!< SALVD1WUP (Bitfield-Mask: 0x01)                       */
+ #define R_CPSCU_ICUSARE_SALVD2WUP_Pos       (19UL)         /*!< SALVD2WUP (Bit 19)                                    */
+ #define R_CPSCU_ICUSARE_SALVD2WUP_Msk       (0x80000UL)    /*!< SALVD2WUP (Bitfield-Mask: 0x01)                       */
+ #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos      (20UL)         /*!< SAVBATTWUP (Bit 20)                                   */
+ #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk      (0x100000UL)   /*!< SAVBATTWUP (Bitfield-Mask: 0x01)                      */
+ #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos     (24UL)         /*!< SARTCALMWUP (Bit 24)                                  */
+ #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk     (0x1000000UL)  /*!< SARTCALMWUP (Bitfield-Mask: 0x01)                     */
+ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos     (25UL)         /*!< SARTCPRDWUP (Bit 25)                                  */
+ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk     (0x2000000UL)  /*!< SARTCPRDWUP (Bitfield-Mask: 0x01)                     */
+ #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos     (27UL)         /*!< SAUSBFS0WUP (Bit 27)                                  */
+ #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk     (0x8000000UL)  /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01)                     */
+ #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos     (28UL)         /*!< SAAGT1UDWUP (Bit 28)                                  */
+ #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk     (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01)                     */
+ #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos     (29UL)         /*!< SAAGT1CAWUP (Bit 29)                                  */
+ #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk     (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01)                     */
+ #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos     (30UL)         /*!< SAAGT1CBWUP (Bit 30)                                  */
+ #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk     (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01)                     */
+ #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos       (31UL)         /*!< SAIIC0WUP (Bit 31)                                    */
+ #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk       (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01)                       */
+/* ========================================================  ICUSARF  ======================================================== */
+ #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos     (0UL)          /*!< SAAGT3UDWUP (Bit 0)                                   */
+ #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk     (0x1UL)        /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01)                     */
+ #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos     (1UL)          /*!< SAAGT3CAWUP (Bit 1)                                   */
+ #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk     (0x2UL)        /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01)                     */
+ #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos     (2UL)          /*!< SAAGT3CBWUP (Bit 2)                                   */
+ #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk     (0x4UL)        /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01)                     */
+ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos    (3UL)          /*!< SACOMPHS0WUP (Bit 3)                                  */
+ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk    (0x8UL)        /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01)                    */
+ #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos      (8UL)          /*!< SAULP0UWUP (Bit 8)                                    */
+ #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk      (0x100UL)      /*!< SAULP0UWUP (Bitfield-Mask: 0x01)                      */
+ #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos      (9UL)          /*!< SAULP0AWUP (Bit 9)                                    */
+ #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk      (0x200UL)      /*!< SAULP0AWUP (Bitfield-Mask: 0x01)                      */
+ #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos      (10UL)         /*!< SAULP0BWUP (Bit 10)                                   */
+ #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk      (0x400UL)      /*!< SAULP0BWUP (Bitfield-Mask: 0x01)                      */
+ #define R_CPSCU_ICUSARF_SAI3CWUP_Pos        (11UL)         /*!< SAI3CWUP (Bit 11)                                     */
+ #define R_CPSCU_ICUSARF_SAI3CWUP_Msk        (0x800UL)      /*!< SAI3CWUP (Bitfield-Mask: 0x01)                        */
+ #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos      (12UL)         /*!< SAULP1UWUP (Bit 12)                                   */
+ #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk      (0x1000UL)     /*!< SAULP1UWUP (Bitfield-Mask: 0x01)                      */
+ #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos      (13UL)         /*!< SAULP1AWUP (Bit 13)                                   */
+ #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk      (0x2000UL)     /*!< SAULP1AWUP (Bitfield-Mask: 0x01)                      */
+ #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos      (14UL)         /*!< SAULP1BWUP (Bit 14)                                   */
+ #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk      (0x4000UL)     /*!< SAULP1BWUP (Bitfield-Mask: 0x01)                      */
+/* ========================================================  ICUSARG  ======================================================== */
+ #define R_CPSCU_ICUSARG_SAIELSRn_Pos        (0UL)          /*!< SAIELSRn (Bit 0)                                      */
+ #define R_CPSCU_ICUSARG_SAIELSRn_Msk        (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
+/* ========================================================  ICUSARH  ======================================================== */
+ #define R_CPSCU_ICUSARH_SAIELSRn_Pos        (0UL)          /*!< SAIELSRn (Bit 0)                                      */
+ #define R_CPSCU_ICUSARH_SAIELSRn_Msk        (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
+/* ========================================================  ICUSARI  ======================================================== */
+ #define R_CPSCU_ICUSARI_SAIELSRn_Pos        (0UL)          /*!< SAIELSRn (Bit 0)                                      */
+ #define R_CPSCU_ICUSARI_SAIELSRn_Msk        (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
+/* ========================================================  BUSSARA  ======================================================== */
+ #define R_CPSCU_BUSSARA_BUSSA0_Pos          (0UL)          /*!< BUSSA0 (Bit 0)                                        */
+ #define R_CPSCU_BUSSARA_BUSSA0_Msk          (0x1UL)        /*!< BUSSA0 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  BUSSARB  ======================================================== */
+ #define R_CPSCU_BUSSARB_BUSSB0_Pos          (0UL)          /*!< BUSSB0 (Bit 0)                                        */
+ #define R_CPSCU_BUSSARB_BUSSB0_Msk          (0x1UL)        /*!< BUSSB0 (Bitfield-Mask: 0x01)                          */
+/* =======================================================  MMPUSARA  ======================================================== */
+ #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos       (0UL)          /*!< MMPUAnSA (Bit 0)                                      */
+ #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk       (0xffUL)       /*!< MMPUAnSA (Bitfield-Mask: 0xff)                        */
+/* =======================================================  MMPUSARB  ======================================================== */
+ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos       (0UL)          /*!< MMPUB0SA (Bit 0)                                      */
+ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk       (0x1UL)        /*!< MMPUB0SA (Bitfield-Mask: 0x01)                        */
+/* ========================================================  DMASARA  ======================================================== */
+ #define R_CPSCU_DMASARA_DMASARAn_Pos        (0UL)          /*!< DMASARAn (Bit 0)                                      */
+ #define R_CPSCU_DMASARA_DMASARAn_Msk        (0xffUL)       /*!< DMASARAn (Bitfield-Mask: 0xff)                        */
+/* ========================================================  CPUDSAR  ======================================================== */
+ #define R_CPSCU_CPUDSAR_CPUDSA0_Pos         (0UL)          /*!< CPUDSA0 (Bit 0)                                       */
+ #define R_CPSCU_CPUDSAR_CPUDSA0_Msk         (0x1UL)        /*!< CPUDSA0 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  TEVTRCR  ======================================================== */
+ #define R_CPSCU_TEVTRCR_TEVTE_Pos           (0UL)          /*!< TEVTE (Bit 0)                                         */
+ #define R_CPSCU_TEVTRCR_TEVTE_Msk           (0x1UL)        /*!< TEVTE (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                           R_CEC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  CADR  ========================================================== */
+ #define R_CEC_CADR_ADR00_Pos            (0UL)      /*!< ADR00 (Bit 0)                                         */
+ #define R_CEC_CADR_ADR00_Msk            (0x1UL)    /*!< ADR00 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR01_Pos            (1UL)      /*!< ADR01 (Bit 1)                                         */
+ #define R_CEC_CADR_ADR01_Msk            (0x2UL)    /*!< ADR01 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR02_Pos            (2UL)      /*!< ADR02 (Bit 2)                                         */
+ #define R_CEC_CADR_ADR02_Msk            (0x4UL)    /*!< ADR02 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR03_Pos            (3UL)      /*!< ADR03 (Bit 3)                                         */
+ #define R_CEC_CADR_ADR03_Msk            (0x8UL)    /*!< ADR03 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR04_Pos            (4UL)      /*!< ADR04 (Bit 4)                                         */
+ #define R_CEC_CADR_ADR04_Msk            (0x10UL)   /*!< ADR04 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR05_Pos            (5UL)      /*!< ADR05 (Bit 5)                                         */
+ #define R_CEC_CADR_ADR05_Msk            (0x20UL)   /*!< ADR05 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR06_Pos            (6UL)      /*!< ADR06 (Bit 6)                                         */
+ #define R_CEC_CADR_ADR06_Msk            (0x40UL)   /*!< ADR06 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR07_Pos            (7UL)      /*!< ADR07 (Bit 7)                                         */
+ #define R_CEC_CADR_ADR07_Msk            (0x80UL)   /*!< ADR07 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR08_Pos            (8UL)      /*!< ADR08 (Bit 8)                                         */
+ #define R_CEC_CADR_ADR08_Msk            (0x100UL)  /*!< ADR08 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR09_Pos            (9UL)      /*!< ADR09 (Bit 9)                                         */
+ #define R_CEC_CADR_ADR09_Msk            (0x200UL)  /*!< ADR09 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR10_Pos            (10UL)     /*!< ADR10 (Bit 10)                                        */
+ #define R_CEC_CADR_ADR10_Msk            (0x400UL)  /*!< ADR10 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR11_Pos            (11UL)     /*!< ADR11 (Bit 11)                                        */
+ #define R_CEC_CADR_ADR11_Msk            (0x800UL)  /*!< ADR11 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR12_Pos            (12UL)     /*!< ADR12 (Bit 12)                                        */
+ #define R_CEC_CADR_ADR12_Msk            (0x1000UL) /*!< ADR12 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR13_Pos            (13UL)     /*!< ADR13 (Bit 13)                                        */
+ #define R_CEC_CADR_ADR13_Msk            (0x2000UL) /*!< ADR13 (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CADR_ADR14_Pos            (14UL)     /*!< ADR14 (Bit 14)                                        */
+ #define R_CEC_CADR_ADR14_Msk            (0x4000UL) /*!< ADR14 (Bitfield-Mask: 0x01)                           */
+/* ========================================================  CECCTL1  ======================================================== */
+ #define R_CEC_CECCTL1_SFT_Pos           (0UL)      /*!< SFT (Bit 0)                                           */
+ #define R_CEC_CECCTL1_SFT_Msk           (0x3UL)    /*!< SFT (Bitfield-Mask: 0x03)                             */
+ #define R_CEC_CECCTL1_CESEL_Pos         (2UL)      /*!< CESEL (Bit 2)                                         */
+ #define R_CEC_CECCTL1_CESEL_Msk         (0xcUL)    /*!< CESEL (Bitfield-Mask: 0x03)                           */
+ #define R_CEC_CECCTL1_STERRD_Pos        (4UL)      /*!< STERRD (Bit 4)                                        */
+ #define R_CEC_CECCTL1_STERRD_Msk        (0x10UL)   /*!< STERRD (Bitfield-Mask: 0x01)                          */
+ #define R_CEC_CECCTL1_BLERRD_Pos        (5UL)      /*!< BLERRD (Bit 5)                                        */
+ #define R_CEC_CECCTL1_BLERRD_Msk        (0x20UL)   /*!< BLERRD (Bitfield-Mask: 0x01)                          */
+ #define R_CEC_CECCTL1_CINTMK_Pos        (6UL)      /*!< CINTMK (Bit 6)                                        */
+ #define R_CEC_CECCTL1_CINTMK_Msk        (0x40UL)   /*!< CINTMK (Bitfield-Mask: 0x01)                          */
+ #define R_CEC_CECCTL1_CDFC_Pos          (7UL)      /*!< CDFC (Bit 7)                                          */
+ #define R_CEC_CECCTL1_CDFC_Msk          (0x80UL)   /*!< CDFC (Bitfield-Mask: 0x01)                            */
+/* =========================================================  STATB  ========================================================= */
+ #define R_CEC_STATB_STATB_Pos           (0UL)      /*!< STATB (Bit 0)                                         */
+ #define R_CEC_STATB_STATB_Msk           (0x1ffUL)  /*!< STATB (Bitfield-Mask: 0x1ff)                          */
+/* =========================================================  STATL  ========================================================= */
+ #define R_CEC_STATL_STATL_Pos           (0UL)      /*!< STATL (Bit 0)                                         */
+ #define R_CEC_STATL_STATL_Msk           (0x1ffUL)  /*!< STATL (Bitfield-Mask: 0x1ff)                          */
+/* =========================================================  LGC0L  ========================================================= */
+ #define R_CEC_LGC0L_LGC0L_Pos           (0UL)      /*!< LGC0L (Bit 0)                                         */
+ #define R_CEC_LGC0L_LGC0L_Msk           (0x1ffUL)  /*!< LGC0L (Bitfield-Mask: 0x1ff)                          */
+/* =========================================================  LGC1L  ========================================================= */
+ #define R_CEC_LGC1L_LGC1L_Pos           (0UL)      /*!< LGC1L (Bit 0)                                         */
+ #define R_CEC_LGC1L_LGC1L_Msk           (0x1ffUL)  /*!< LGC1L (Bitfield-Mask: 0x1ff)                          */
+/* =========================================================  DATB  ========================================================== */
+ #define R_CEC_DATB_DATB_Pos             (0UL)      /*!< DATB (Bit 0)                                          */
+ #define R_CEC_DATB_DATB_Msk             (0x1ffUL)  /*!< DATB (Bitfield-Mask: 0x1ff)                           */
+/* =========================================================  NOMT  ========================================================== */
+ #define R_CEC_NOMT_NOMT_Pos             (0UL)      /*!< NOMT (Bit 0)                                          */
+ #define R_CEC_NOMT_NOMT_Msk             (0x1ffUL)  /*!< NOMT (Bitfield-Mask: 0x1ff)                           */
+/* ========================================================  STATLL  ========================================================= */
+ #define R_CEC_STATLL_STATLL_Pos         (0UL)      /*!< STATLL (Bit 0)                                        */
+ #define R_CEC_STATLL_STATLL_Msk         (0x1ffUL)  /*!< STATLL (Bitfield-Mask: 0x1ff)                         */
+/* ========================================================  STATLH  ========================================================= */
+ #define R_CEC_STATLH_STATLH_Pos         (0UL)      /*!< STATLH (Bit 0)                                        */
+ #define R_CEC_STATLH_STATLH_Msk         (0x1ffUL)  /*!< STATLH (Bitfield-Mask: 0x1ff)                         */
+/* ========================================================  STATBL  ========================================================= */
+ #define R_CEC_STATBL_STATBL_Pos         (0UL)      /*!< STATBL (Bit 0)                                        */
+ #define R_CEC_STATBL_STATBL_Msk         (0x1ffUL)  /*!< STATBL (Bitfield-Mask: 0x1ff)                         */
+/* ========================================================  STATBH  ========================================================= */
+ #define R_CEC_STATBH_STATBH_Pos         (0UL)      /*!< STATBH (Bit 0)                                        */
+ #define R_CEC_STATBH_STATBH_Msk         (0x1ffUL)  /*!< STATBH (Bitfield-Mask: 0x1ff)                         */
+/* ========================================================  LGC0LL  ========================================================= */
+ #define R_CEC_LGC0LL_LGC0LL_Pos         (0UL)      /*!< LGC0LL (Bit 0)                                        */
+ #define R_CEC_LGC0LL_LGC0LL_Msk         (0x1ffUL)  /*!< LGC0LL (Bitfield-Mask: 0x1ff)                         */
+/* ========================================================  LGC0LH  ========================================================= */
+ #define R_CEC_LGC0LH_LGC0LH_Pos         (0UL)      /*!< LGC0LH (Bit 0)                                        */
+ #define R_CEC_LGC0LH_LGC0LH_Msk         (0x1ffUL)  /*!< LGC0LH (Bitfield-Mask: 0x1ff)                         */
+/* ========================================================  LGC1LL  ========================================================= */
+ #define R_CEC_LGC1LL_LGC1LL_Pos         (0UL)      /*!< LGC1LL (Bit 0)                                        */
+ #define R_CEC_LGC1LL_LGC1LL_Msk         (0x1ffUL)  /*!< LGC1LL (Bitfield-Mask: 0x1ff)                         */
+/* ========================================================  LGC1LH  ========================================================= */
+ #define R_CEC_LGC1LH_LGC1LH_Pos         (0UL)      /*!< LGC1LH (Bit 0)                                        */
+ #define R_CEC_LGC1LH_LGC1LH_Msk         (0x1ffUL)  /*!< LGC1LH (Bitfield-Mask: 0x1ff)                         */
+/* =========================================================  DATBL  ========================================================= */
+ #define R_CEC_DATBL_DATBL_Pos           (0UL)      /*!< DATBL (Bit 0)                                         */
+ #define R_CEC_DATBL_DATBL_Msk           (0x1ffUL)  /*!< DATBL (Bitfield-Mask: 0x1ff)                          */
+/* =========================================================  DATBH  ========================================================= */
+ #define R_CEC_DATBH_DATBH_Pos           (0UL)      /*!< DATBH (Bit 0)                                         */
+ #define R_CEC_DATBH_DATBH_Msk           (0x1ffUL)  /*!< DATBH (Bitfield-Mask: 0x1ff)                          */
+/* =========================================================  NOMP  ========================================================== */
+ #define R_CEC_NOMP_NOMP_Pos             (0UL)      /*!< NOMP (Bit 0)                                          */
+ #define R_CEC_NOMP_NOMP_Msk             (0x1ffUL)  /*!< NOMP (Bitfield-Mask: 0x1ff)                           */
+/* ========================================================  CECEXMD  ======================================================== */
+ #define R_CEC_CECEXMD_LERPLEN_Pos       (4UL)      /*!< LERPLEN (Bit 4)                                       */
+ #define R_CEC_CECEXMD_LERPLEN_Msk       (0x10UL)   /*!< LERPLEN (Bitfield-Mask: 0x01)                         */
+ #define R_CEC_CECEXMD_RERCVEN_Pos       (5UL)      /*!< RERCVEN (Bit 5)                                       */
+ #define R_CEC_CECEXMD_RERCVEN_Msk       (0x20UL)   /*!< RERCVEN (Bitfield-Mask: 0x01)                         */
+ #define R_CEC_CECEXMD_RCVINTDSEL_Pos    (7UL)      /*!< RCVINTDSEL (Bit 7)                                    */
+ #define R_CEC_CECEXMD_RCVINTDSEL_Msk    (0x80UL)   /*!< RCVINTDSEL (Bitfield-Mask: 0x01)                      */
+/* =======================================================  CECEXMON  ======================================================== */
+ #define R_CEC_CECEXMON_CECLNMON_Pos     (0UL)      /*!< CECLNMON (Bit 0)                                      */
+ #define R_CEC_CECEXMON_CECLNMON_Msk     (0x1UL)    /*!< CECLNMON (Bitfield-Mask: 0x01)                        */
+ #define R_CEC_CECEXMON_ACKF_Pos         (1UL)      /*!< ACKF (Bit 1)                                          */
+ #define R_CEC_CECEXMON_ACKF_Msk         (0x2UL)    /*!< ACKF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  CTXD  ========================================================== */
+/* =========================================================  CRXD  ========================================================== */
+/* =========================================================  CECES  ========================================================= */
+ #define R_CEC_CECES_OERR_Pos            (0UL)      /*!< OERR (Bit 0)                                          */
+ #define R_CEC_CECES_OERR_Msk            (0x1UL)    /*!< OERR (Bitfield-Mask: 0x01)                            */
+ #define R_CEC_CECES_UERR_Pos            (1UL)      /*!< UERR (Bit 1)                                          */
+ #define R_CEC_CECES_UERR_Msk            (0x2UL)    /*!< UERR (Bitfield-Mask: 0x01)                            */
+ #define R_CEC_CECES_ACKERR_Pos          (2UL)      /*!< ACKERR (Bit 2)                                        */
+ #define R_CEC_CECES_ACKERR_Msk          (0x4UL)    /*!< ACKERR (Bitfield-Mask: 0x01)                          */
+ #define R_CEC_CECES_TERR_Pos            (3UL)      /*!< TERR (Bit 3)                                          */
+ #define R_CEC_CECES_TERR_Msk            (0x8UL)    /*!< TERR (Bitfield-Mask: 0x01)                            */
+ #define R_CEC_CECES_TXERR_Pos           (4UL)      /*!< TXERR (Bit 4)                                         */
+ #define R_CEC_CECES_TXERR_Msk           (0x10UL)   /*!< TXERR (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CECES_AERR_Pos            (5UL)      /*!< AERR (Bit 5)                                          */
+ #define R_CEC_CECES_AERR_Msk            (0x20UL)   /*!< AERR (Bitfield-Mask: 0x01)                            */
+ #define R_CEC_CECES_BLERR_Pos           (6UL)      /*!< BLERR (Bit 6)                                         */
+ #define R_CEC_CECES_BLERR_Msk           (0x40UL)   /*!< BLERR (Bitfield-Mask: 0x01)                           */
+/* =========================================================  CECS  ========================================================== */
+ #define R_CEC_CECS_ADRF_Pos             (0UL)      /*!< ADRF (Bit 0)                                          */
+ #define R_CEC_CECS_ADRF_Msk             (0x1UL)    /*!< ADRF (Bitfield-Mask: 0x01)                            */
+ #define R_CEC_CECS_BUSST_Pos            (1UL)      /*!< BUSST (Bit 1)                                         */
+ #define R_CEC_CECS_BUSST_Msk            (0x2UL)    /*!< BUSST (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CECS_TXST_Pos             (2UL)      /*!< TXST (Bit 2)                                          */
+ #define R_CEC_CECS_TXST_Msk             (0x4UL)    /*!< TXST (Bitfield-Mask: 0x01)                            */
+ #define R_CEC_CECS_EOMF_Pos             (3UL)      /*!< EOMF (Bit 3)                                          */
+ #define R_CEC_CECS_EOMF_Msk             (0x8UL)    /*!< EOMF (Bitfield-Mask: 0x01)                            */
+ #define R_CEC_CECS_ITCEF_Pos            (4UL)      /*!< ITCEF (Bit 4)                                         */
+ #define R_CEC_CECS_ITCEF_Msk            (0x10UL)   /*!< ITCEF (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CECS_SFTST_Pos            (7UL)      /*!< SFTST (Bit 7)                                         */
+ #define R_CEC_CECS_SFTST_Msk            (0x80UL)   /*!< SFTST (Bitfield-Mask: 0x01)                           */
+/* =========================================================  CECFC  ========================================================= */
+ #define R_CEC_CECFC_OCTRG_Pos           (0UL)      /*!< OCTRG (Bit 0)                                         */
+ #define R_CEC_CECFC_OCTRG_Msk           (0x1UL)    /*!< OCTRG (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CECFC_UCTRG_Pos           (1UL)      /*!< UCTRG (Bit 1)                                         */
+ #define R_CEC_CECFC_UCTRG_Msk           (0x2UL)    /*!< UCTRG (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CECFC_ACKCTRG_Pos         (2UL)      /*!< ACKCTRG (Bit 2)                                       */
+ #define R_CEC_CECFC_ACKCTRG_Msk         (0x4UL)    /*!< ACKCTRG (Bitfield-Mask: 0x01)                         */
+ #define R_CEC_CECFC_TCTRG_Pos           (3UL)      /*!< TCTRG (Bit 3)                                         */
+ #define R_CEC_CECFC_TCTRG_Msk           (0x8UL)    /*!< TCTRG (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CECFC_TXCTRG_Pos          (4UL)      /*!< TXCTRG (Bit 4)                                        */
+ #define R_CEC_CECFC_TXCTRG_Msk          (0x10UL)   /*!< TXCTRG (Bitfield-Mask: 0x01)                          */
+ #define R_CEC_CECFC_ACTRG_Pos           (5UL)      /*!< ACTRG (Bit 5)                                         */
+ #define R_CEC_CECFC_ACTRG_Msk           (0x20UL)   /*!< ACTRG (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CECFC_BLCTRG_Pos          (6UL)      /*!< BLCTRG (Bit 6)                                        */
+ #define R_CEC_CECFC_BLCTRG_Msk          (0x40UL)   /*!< BLCTRG (Bitfield-Mask: 0x01)                          */
+/* ========================================================  CECCTL0  ======================================================== */
+ #define R_CEC_CECCTL0_EOM_Pos           (0UL)      /*!< EOM (Bit 0)                                           */
+ #define R_CEC_CECCTL0_EOM_Msk           (0x1UL)    /*!< EOM (Bitfield-Mask: 0x01)                             */
+ #define R_CEC_CECCTL0_CECRXEN_Pos       (1UL)      /*!< CECRXEN (Bit 1)                                       */
+ #define R_CEC_CECCTL0_CECRXEN_Msk       (0x2UL)    /*!< CECRXEN (Bitfield-Mask: 0x01)                         */
+ #define R_CEC_CECCTL0_TXTRG_Pos         (2UL)      /*!< TXTRG (Bit 2)                                         */
+ #define R_CEC_CECCTL0_TXTRG_Msk         (0x4UL)    /*!< TXTRG (Bitfield-Mask: 0x01)                           */
+ #define R_CEC_CECCTL0_CCL_Pos           (3UL)      /*!< CCL (Bit 3)                                           */
+ #define R_CEC_CECCTL0_CCL_Msk           (0x38UL)   /*!< CCL (Bitfield-Mask: 0x07)                             */
+ #define R_CEC_CECCTL0_ACKTEN_Pos        (6UL)      /*!< ACKTEN (Bit 6)                                        */
+ #define R_CEC_CECCTL0_ACKTEN_Msk        (0x40UL)   /*!< ACKTEN (Bitfield-Mask: 0x01)                          */
+ #define R_CEC_CECCTL0_CECE_Pos          (7UL)      /*!< CECE (Bit 7)                                          */
+ #define R_CEC_CECCTL0_CECE_Msk          (0x80UL)   /*!< CECE (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_FLAD                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  FCKMHZ  ========================================================= */
+ #define R_FLAD_FCKMHZ_FCKMHZ_Pos    (0UL)    /*!< FCKMHZ (Bit 0)                                        */
+ #define R_FLAD_FCKMHZ_FCKMHZ_Msk    (0xffUL) /*!< FCKMHZ (Bitfield-Mask: 0xff)                          */
+
+/** @} */ /* End of group PosMask_peripherals */
+
+ #ifdef __cplusplus
+}
+ #endif
+
+#endif                                 /* R7FA6E2BB_H */
+
+/** @} */ /* End of group R7FA6E2BB */
+
+/** @} */ /* End of group Renesas Electronics Corporation */
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h
index b7a284d06..972835fe0 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h
@@ -820,7 +820,8 @@ typedef struct
             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
             uint8_t            : 1;
             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
-            uint8_t            : 2;
+            uint8_t            : 1;
+            __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
         } RTCCR_b;
     };
     __IM uint8_t RESERVED;
@@ -1027,6 +1028,213 @@ typedef struct
     };
 } R_USB_HS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
 
+/**
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
+            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
+            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
+            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
+            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
+            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
+        } AGTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
+            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
+            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
+            uint8_t              : 1;
+        } AGTMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+                                        *   ratio                                                                     */
+            uint8_t           : 4;
+            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
+        } AGTMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+                                        *   mode.                                                                     */
+            uint8_t             : 1;
+            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
+            uint8_t             : 1;
+            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
+            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
+        } AGTIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
+            uint8_t            : 5;
+        } AGTISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
+
+        struct
+        {
+            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
+            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
+            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
+            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
+            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
+            uint8_t              : 1;
+        } AGTCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_b;
+    };
+} R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
+
+        struct
+        {
+            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IM uint16_t                 RESERVED;
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
+} R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
+
+        struct
+        {
+            __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
+} R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_clusters */
 
 /* =========================================================================================================================== */
@@ -1394,16 +1602,17 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
 
     union
     {
-        __IM uint16_t ADDR[28];        /*!< (@ 0x00000020) A/D Data Register                                          */
+        __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
 
         struct
         {
             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
                                         *   storing the result of A/D conversion.                                     */
-        } ADDR_b[28];
+        } ADDR_b[29];
     };
-    __IM uint32_t RESERVED1[2];
-    __IM uint16_t RESERVED2;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+    __IM uint16_t RESERVED3;
 
     union
     {
@@ -1596,7 +1805,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint16_t                : 3;
         } ADSWTSTR2_b;
     };
-    __IM uint16_t RESERVED3;
+    __IM uint16_t RESERVED4;
 
     union
     {
@@ -1658,7 +1867,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 6;
         } ADACSR_b;
     };
-    __IM uint8_t RESERVED4;
+    __IM uint8_t RESERVED5;
 
     union
     {
@@ -1728,7 +1937,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
         } ADSER_b;
     };
-    __IM uint8_t RESERVED5;
+    __IM uint8_t RESERVED6;
 
     union
     {
@@ -1744,7 +1953,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
         } ADHVREFCNT_b;
     };
-    __IM uint8_t RESERVED6;
+    __IM uint8_t RESERVED7;
 
     union
     {
@@ -1762,8 +1971,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t              : 2;
         } ADWINMON_b;
     };
-    __IM uint8_t  RESERVED7;
-    __IM uint16_t RESERVED8;
+    __IM uint8_t  RESERVED8;
+    __IM uint16_t RESERVED9;
 
     union
     {
@@ -1939,7 +2148,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 6;
         } ADCMPSER_b;
     };
-    __IM uint8_t RESERVED9;
+    __IM uint8_t RESERVED10;
 
     union
     {
@@ -1954,7 +2163,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
         } ADCMPBNSR_b;
     };
-    __IM uint8_t RESERVED10;
+    __IM uint8_t RESERVED11;
 
     union
     {
@@ -1993,8 +2202,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 7;
         } ADCMPBSR_b;
     };
-    __IM uint8_t  RESERVED11;
-    __IM uint16_t RESERVED12;
+    __IM uint8_t  RESERVED12;
+    __IM uint16_t RESERVED13;
 
     union
     {
@@ -2198,7 +2407,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 7;
         } ADBUFEN_b;
     };
-    __IM uint8_t RESERVED13;
+    __IM uint8_t RESERVED14;
 
     union
     {
@@ -2212,9 +2421,9 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 3;
         } ADBUFPTR_b;
     };
-    __IM uint8_t  RESERVED14;
-    __IM uint32_t RESERVED15[2];
-    __IM uint8_t  RESERVED16;
+    __IM uint8_t  RESERVED15;
+    __IM uint32_t RESERVED16[2];
+    __IM uint8_t  RESERVED17;
 
     union
     {
@@ -2281,7 +2490,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
         } ADCALEXE_b;
     };
-    __IM uint8_t RESERVED17;
+    __IM uint8_t RESERVED18;
 
     union
     {
@@ -2298,8 +2507,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
         } VREFAMPCNT_b;
     };
-    __IM uint8_t  RESERVED18;
-    __IM uint16_t RESERVED19;
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -2321,8 +2530,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 6;
         } ADRST_b;
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint32_t RESERVED21[41];
+    __IM uint8_t  RESERVED21;
+    __IM uint32_t RESERVED22[41];
 
     union
     {
@@ -2380,7 +2589,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
         } ADPGAGS0_b;
     };
-    __IM uint32_t RESERVED22[3];
+    __IM uint32_t RESERVED23[3];
 
     union
     {
@@ -2407,7 +2616,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
         } ADPGADCR0_b;
     };
-    __IM uint16_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -2436,8 +2645,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 7;
         } ADPGADBS1_b;
     };
-    __IM uint16_t RESERVED24;
-    __IM uint32_t RESERVED25[10];
+    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED26[10];
 
     union
     {
@@ -2453,156 +2662,6 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
     };
 } R_ADC0_Type;                         /*!< Size = 484 (0x1e4)                                                        */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Asynchronous General Purpose Timer (R_AGT0)
- */
-
-typedef struct                         /*!< (@ 0x40084000) R_AGT0 Structure                                           */
-{
-    union
-    {
-        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
-
-        struct
-        {
-            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written
-                                        *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
-                                        *   is forcibly stopped and set to FFFFH.                                     */
-        } AGT_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCRn register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMA_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCR register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMB_b;
-    };
-    __IM uint16_t RESERVED;
-
-    union
-    {
-        __IOM uint8_t AGTCR;           /*!< (@ 0x00000008) AGT Control Register                                       */
-
-        struct
-        {
-            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
-            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
-            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
-            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
-            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
-            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
-        } AGTCR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000009) AGT Mode Register 1                                        */
-
-        struct
-        {
-            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
-            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
-            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
-            uint8_t              : 1;
-        } AGTMR1_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000A) AGT Mode Register 2                                        */
-
-        struct
-        {
-            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
-                                        *   ratio                                                                     */
-            uint8_t           : 4;
-            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
-        } AGTMR2_b;
-    };
-    __IM uint8_t RESERVED1;
-
-    union
-    {
-        __IOM uint8_t AGTIOC;          /*!< (@ 0x0000000C) AGT I/O Control Register                                   */
-
-        struct
-        {
-            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
-                                        *   mode.                                                                     */
-            uint8_t             : 1;
-            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
-            uint8_t             : 1;
-            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
-            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
-        } AGTIOC_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTISR;          /*!< (@ 0x0000000D) AGT Event Pin Select Register                              */
-
-        struct
-        {
-            uint8_t            : 2;
-            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
-            uint8_t            : 5;
-        } AGTISR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTCMSR;         /*!< (@ 0x0000000E) AGT Compare Match Function Select Register                 */
-
-        struct
-        {
-            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
-            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
-            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
-            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
-            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
-            uint8_t              : 1;
-        } AGTCMSR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x0000000F) AGT Pin Select Register                                    */
-
-        struct
-        {
-            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
-            uint8_t            : 2;
-            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
-            uint8_t            : 3;
-        } AGTIOSEL_b;
-    };
-} R_AGT0_Type;                         /*!< Size = 16 (0x10)                                                          */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -4705,46 +4764,99 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            uint32_t : 18;
         } GTSTR_b;
     };
 
@@ -4796,7 +4908,60 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
                                          *   1 means counter stop.                                                     */
-            uint32_t : 18;
+            __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
         } GTSTP_b;
     };
 
@@ -4820,7 +4985,24 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
-            uint32_t             : 18;
+            __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
         } GTCLR_b;
     };
 
@@ -5141,16 +5323,23 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+        __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
 
         struct
         {
-            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
-            uint32_t            : 15;
-            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
-            uint32_t            : 5;
-            __IOM uint32_t TPCS : 3;   /*!< [26..24] Timer Prescaler Select                                           */
-            uint32_t            : 5;
+            __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
+            uint32_t               : 7;
+            __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
+            __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
+            __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
+            __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
+            uint32_t               : 2;
+            __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
+            __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
+            uint32_t               : 4;
+            __IOM uint32_t TPCS    : 3; /*!< [26..24] Timer Prescaler Select                                           */
+            __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
+            uint32_t               : 3;
         } GTCR_b;
     };
 
@@ -5221,13 +5410,36 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
         struct
         {
-            uint32_t               : 24;
-            __IOM uint32_t GRP     : 2; /*!< [25..24] Output Disable Source Select                                     */
+            uint32_t            : 8;
+            __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
+            __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            uint32_t               : 4;
+            __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
             uint32_t               : 2;
-            __IOM uint32_t GRPDTE  : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
-            __IOM uint32_t GRPABH  : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable               */
-            __IOM uint32_t GRPABL  : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
-            __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
+            __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
+            __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
         } GTINTAD_b;
     };
 
@@ -5270,32 +5482,36 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTBER;          /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
 
         struct
         {
-            __IOM uint32_t BD0    : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
-            __IOM uint32_t BD1    : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
-            __IOM uint32_t BD2    : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
-            __IOM uint32_t BD3    : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
-            uint32_t              : 12;
-            __IOM uint32_t CCRA   : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
-            __IOM uint32_t CCRB   : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
-            __IOM uint32_t PR     : 2; /*!< [21..20] GTPR Buffer Operation                                            */
-            __OM uint32_t  CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
-                                        *   is read as 0.                                                             */
+            __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
+            __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+                                         *   is read as 0.                                                             */
             uint32_t             : 1;
-            __IOM uint32_t ADTTA : 2;  /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDA : 1;  /*!< [26..26] GTADTRA Double Buffer Operation                                  */
+            __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
             uint32_t             : 1;
-            __IOM uint32_t ADTTB : 2;  /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDB : 1;  /*!< [30..30] GTADTRB Double Buffer Operation                                  */
+            __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
             uint32_t             : 1;
         } GTBER_b;
     };
@@ -5519,7 +5735,126 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             uint32_t            : 31;
         } GTSOTR_b;
     };
-    __IM uint32_t RESERVED[5];
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
 
     union
     {
@@ -5553,7 +5888,7 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             uint32_t            : 4;
         } GTPC_b;
     };
-    __IM uint32_t RESERVED1[4];
+    __IM uint32_t RESERVED[4];
 
     union
     {
@@ -5595,17 +5930,137 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
         {
             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 4;
             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
-            uint32_t             : 7;
+            __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
+            uint32_t             : 6;
             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
-            uint32_t             : 7;
+            __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
+            uint32_t             : 6;
         } GTSECR_b;
     };
-} R_GPT0_Type;                         /*!< Size = 216 (0xd8)                                                         */
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
+            __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
+                                        *   Disable                                                                   */
+            uint32_t             : 2;
+            __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t             : 1;
+            __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
+                                        *   Transfer Disable                                                          */
+            uint32_t             : 2;
+            __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
+            __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
+            __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
+            __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
+            uint32_t             : 2;
+        } GTBER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
+
+        struct
+        {
+            __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
+            uint32_t              : 11;
+            __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
+            uint32_t              : 11;
+        } GTOLBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
+                                        *                  Capture Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
+            __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
+                                        *   Other Channel GTCCRb Input Capture Source Enable                          */
+            __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
+        } GTICCR_b;
+    };
+} R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_ODC                                         ================ */
@@ -10153,8 +10608,18 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } IICCKDIVCR_b;
         };
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint16_t RESERVED21;
+
+    union
+    {
+        __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
+
+        struct
+        {
+            __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
+            uint8_t                : 5;
+        } I3CCKDIVCR_b;
+    };
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -10281,8 +10746,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
         } I3CCKCR_b;
     };
-    __IM uint16_t RESERVED22;
-    __IM uint32_t RESERVED23[3];
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
 
     union
     {
@@ -10296,8 +10761,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                 : 29;
         } SNZREQCR1_b;
     };
-    __IM uint32_t RESERVED24;
-    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -10312,7 +10777,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
         } SNZCR_b;
     };
-    __IM uint8_t RESERVED26;
+    __IM uint8_t RESERVED25;
 
     union
     {
@@ -10342,7 +10807,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } SNZEDCR1_b;
     };
-    __IM uint16_t RESERVED27;
+    __IM uint16_t RESERVED26;
 
     union
     {
@@ -10385,7 +10850,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 1;
         } SNZREQCR_b;
     };
-    __IM uint16_t RESERVED28;
+    __IM uint16_t RESERVED27;
 
     union
     {
@@ -10423,7 +10888,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 3;
         } OPCCR_b;
     };
-    __IM uint8_t RESERVED29;
+    __IM uint8_t RESERVED28;
 
     union
     {
@@ -10435,7 +10900,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } MOSCWTCR_b;
     };
-    __IM uint8_t RESERVED30[2];
+    __IM uint8_t RESERVED29[2];
 
     union
     {
@@ -10448,7 +10913,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t : 5;
         } HOCOWTCR_b;
     };
-    __IM uint16_t RESERVED31[2];
+    __IM uint16_t RESERVED30[2];
 
     union
     {
@@ -10462,8 +10927,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 3;
         } SOPCCR_b;
     };
-    __IM uint8_t  RESERVED32;
-    __IM uint32_t RESERVED33[5];
+    __IM uint8_t  RESERVED31;
+    __IM uint32_t RESERVED32[5];
 
     union
     {
@@ -10497,8 +10962,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
         } RSTSR1_b;
     };
-    __IM uint16_t RESERVED34;
-    __IM uint32_t RESERVED35[3];
+    __IM uint16_t RESERVED33;
+    __IM uint32_t RESERVED34[3];
 
     union
     {
@@ -10524,8 +10989,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
         } SDADCCKCR_b;
     };
-    __IM uint16_t RESERVED36;
-    __IM uint32_t RESERVED37[3];
+    __IM uint16_t RESERVED35;
+    __IM uint32_t RESERVED36[3];
 
     union
     {
@@ -10580,7 +11045,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t          : 6;
         } LVD2SR_b;
     };
-    __IM uint32_t RESERVED38[183];
+    __IM uint32_t RESERVED37[183];
 
     union
     {
@@ -10608,7 +11073,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 14;
         } CGFSAR_b;
     };
-    __IM uint32_t RESERVED39;
+    __IM uint32_t RESERVED38;
 
     union
     {
@@ -10677,7 +11142,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 8;
         } BBFSAR_b;
     };
-    __IM uint32_t RESERVED40[3];
+    __IM uint32_t RESERVED39[3];
 
     union
     {
@@ -10739,8 +11204,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 4;
         } DPFSAR_b;
     };
-    __IM uint32_t RESERVED41[6];
-    __IM uint16_t RESERVED42;
+    __IM uint32_t RESERVED40[6];
+    __IM uint16_t RESERVED41;
 
     union
     {
@@ -10958,7 +11423,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 3;
         } DPSIEGR2_b;
     };
-    __IM uint8_t RESERVED43;
+    __IM uint8_t RESERVED42;
 
     union
     {
@@ -11016,7 +11481,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } RSTSR2_b;
     };
-    __IM uint8_t RESERVED44;
+    __IM uint8_t RESERVED43;
 
     union
     {
@@ -11033,7 +11498,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                           *   Enable                                                                    */
         } MOMCR_b;
     };
-    __IM uint16_t RESERVED45;
+    __IM uint16_t RESERVED44;
 
     union
     {
@@ -11103,7 +11568,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } LVD2CMPCR_b;
         };
     };
-    __IM uint8_t RESERVED46;
+    __IM uint8_t RESERVED45;
 
     union
     {
@@ -11136,7 +11601,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
         } LVD2CR0_b;
     };
-    __IM uint8_t RESERVED47;
+    __IM uint8_t RESERVED46;
 
     union
     {
@@ -11171,7 +11636,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 7;
         } VBTCR1_b;
     };
-    __IM uint32_t RESERVED48[8];
+    __IM uint32_t RESERVED47[8];
 
     union
     {
@@ -11214,7 +11679,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 6;
         } VCCSEL_b;
     };
-    __IM uint16_t RESERVED49;
+    __IM uint16_t RESERVED48;
 
     union
     {
@@ -11226,9 +11691,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } PL2LDOSCR_b;
     };
-    __IM uint8_t  RESERVED50;
-    __IM uint16_t RESERVED51;
-    __IM uint32_t RESERVED52[14];
+    __IM uint8_t  RESERVED49;
+    __IM uint16_t RESERVED50;
+    __IM uint32_t RESERVED51[14];
 
     union
     {
@@ -11251,8 +11716,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 6;
         } SOMCR_b;
     };
-    __IM uint16_t RESERVED53;
-    __IM uint32_t RESERVED54[3];
+    __IM uint16_t RESERVED52;
+    __IM uint32_t RESERVED53[3];
 
     union
     {
@@ -11264,7 +11729,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 7;
         } LOCOCR_b;
     };
-    __IM uint8_t RESERVED55;
+    __IM uint8_t RESERVED54;
 
     union
     {
@@ -11279,8 +11744,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                          *   trimming bits                                                             */
         } LOCOUTCR_b;
     };
-    __IM uint8_t  RESERVED56;
-    __IM uint32_t RESERVED57[7];
+    __IM uint8_t  RESERVED55;
+    __IM uint32_t RESERVED56[7];
 
     union
     {
@@ -11319,7 +11784,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 7;
         } VBTCMPCR_b;
     };
-    __IM uint8_t RESERVED58;
+    __IM uint8_t RESERVED57;
 
     union
     {
@@ -11333,7 +11798,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                  : 6;
         } VBTLVDICR_b;
     };
-    __IM uint8_t RESERVED59;
+    __IM uint8_t RESERVED58;
 
     union
     {
@@ -11345,7 +11810,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } VBTWCTLR_b;
     };
-    __IM uint8_t RESERVED60;
+    __IM uint8_t RESERVED59;
 
     union
     {
@@ -11480,9 +11945,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } VBTBER_b;
     };
-    __IM uint8_t  RESERVED61;
-    __IM uint16_t RESERVED62;
-    __IM uint32_t RESERVED63[15];
+    __IM uint8_t  RESERVED60;
+    __IM uint16_t RESERVED61;
+    __IM uint32_t RESERVED62[15];
 
     union
     {
@@ -13676,6 +14141,23 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
     };
 } R_USB_HS0_Type;                        /*!< Size = 364 (0x16c)                                                        */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
+ */
+
+typedef struct                          /*!< (@ 0x40084000) R_AGTX0 Structure                                          */
+{
+    union
+    {
+        __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
+        __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
+    };
+} R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_peripherals */
 
 /* =========================================================================================================================== */
@@ -13694,12 +14176,6 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_ACMPHS5_BASE        0x40085500UL
  #define R_ADC0_BASE           0x4005C000UL
  #define R_ADC1_BASE           0x4005C200UL
- #define R_AGT0_BASE           0x40084000UL
- #define R_AGT1_BASE           0x40084100UL
- #define R_AGT2_BASE           0x40084200UL
- #define R_AGT3_BASE           0x40084300UL
- #define R_AGT4_BASE           0x40084400UL
- #define R_AGT5_BASE           0x40084500UL
  #define R_BUS_BASE            0x40003000UL
  #define R_CAC_BASE            0x40044600UL
  #define R_CAN0_BASE           0x40050000UL
@@ -13796,6 +14272,16 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_USB_FS0_BASE        0x40090000UL
  #define R_WDT_BASE            0x40044200UL
  #define R_USB_HS0_BASE        0x40060000UL
+ #define R_AGTX0_BASE          0x40084000UL
+ #define R_AGTX1_BASE          0x40084100UL
+ #define R_AGTX2_BASE          0x40084200UL
+ #define R_AGTX3_BASE          0x40084300UL
+ #define R_AGTX4_BASE          0x40084400UL
+ #define R_AGTX5_BASE          0x40084500UL
+ #define R_AGTX6_BASE          0x40084600UL
+ #define R_AGTX7_BASE          0x40084700UL
+ #define R_AGTX8_BASE          0x40084800UL
+ #define R_AGTX9_BASE          0x40084900UL
 
 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
 
@@ -13815,12 +14301,6 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_ACMPHS5        ((R_ACMPHS0_Type *) R_ACMPHS5_BASE)
  #define R_ADC0           ((R_ADC0_Type *) R_ADC0_BASE)
  #define R_ADC1           ((R_ADC0_Type *) R_ADC1_BASE)
- #define R_AGT0           ((R_AGT0_Type *) R_AGT0_BASE)
- #define R_AGT1           ((R_AGT0_Type *) R_AGT1_BASE)
- #define R_AGT2           ((R_AGT0_Type *) R_AGT2_BASE)
- #define R_AGT3           ((R_AGT0_Type *) R_AGT3_BASE)
- #define R_AGT4           ((R_AGT0_Type *) R_AGT4_BASE)
- #define R_AGT5           ((R_AGT0_Type *) R_AGT5_BASE)
  #define R_BUS            ((R_BUS_Type *) R_BUS_BASE)
  #define R_CAC            ((R_CAC_Type *) R_CAC_BASE)
  #define R_CAN0           ((R_CAN0_Type *) R_CAN0_BASE)
@@ -13917,6 +14397,16 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_USB_FS0        ((R_USB_FS0_Type *) R_USB_FS0_BASE)
  #define R_WDT            ((R_WDT_Type *) R_WDT_BASE)
  #define R_USB_HS0        ((R_USB_HS0_Type *) R_USB_HS0_BASE)
+ #define R_AGTX0          ((R_AGTX0_Type *) R_AGTX0_BASE)
+ #define R_AGTX1          ((R_AGTX0_Type *) R_AGTX1_BASE)
+ #define R_AGTX2          ((R_AGTX0_Type *) R_AGTX2_BASE)
+ #define R_AGTX3          ((R_AGTX0_Type *) R_AGTX3_BASE)
+ #define R_AGTX4          ((R_AGTX0_Type *) R_AGTX4_BASE)
+ #define R_AGTX5          ((R_AGTX0_Type *) R_AGTX5_BASE)
+ #define R_AGTX6          ((R_AGTX0_Type *) R_AGTX6_BASE)
+ #define R_AGTX7          ((R_AGTX0_Type *) R_AGTX7_BASE)
+ #define R_AGTX8          ((R_AGTX0_Type *) R_AGTX8_BASE)
+ #define R_AGTX9          ((R_AGTX0_Type *) R_AGTX9_BASE)
 
 /** @} */ /* End of group Device_Peripheral_declaration */
 
@@ -14284,6 +14774,8 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
 /* =========================================================================================================================== */
 
 /* =========================================================  RTCCR  ========================================================= */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
@@ -14361,6 +14853,101 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
  #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
 
+/* =========================================================================================================================== */
+/* ================                                           CTRL                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  AGTCR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AGTMR1  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
+/* ========================================================  AGTMR2  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
+/* =====================================================  AGTIOSEL_ALT  ====================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+/* ========================================================  AGTIOC  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AGTISR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AGTCMSR  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
+/* =======================================================  AGTIOSEL  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT16                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT32                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
+
 /** @} */ /* End of group PosMask_clusters */
 
 /* =========================================================================================================================== */
@@ -14894,77 +15481,6 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_ADC0_ADREFMON_MONSEL_Pos         (16UL)      /*!< MONSEL (Bit 16)                                       */
  #define R_ADC0_ADREFMON_MONSEL_Msk         (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f)                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/* ==========================================================  AGT  ========================================================== */
- #define R_AGT0_AGT_AGT_Pos           (0UL)      /*!< AGT (Bit 0)                                           */
- #define R_AGT0_AGT_AGT_Msk           (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
-/* ========================================================  AGTCMA  ========================================================= */
- #define R_AGT0_AGTCMA_AGTCMA_Pos     (0UL)      /*!< AGTCMA (Bit 0)                                        */
- #define R_AGT0_AGTCMA_AGTCMA_Msk     (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
-/* ========================================================  AGTCMB  ========================================================= */
- #define R_AGT0_AGTCMB_AGTCMB_Pos     (0UL)      /*!< AGTCMB (Bit 0)                                        */
- #define R_AGT0_AGTCMB_AGTCMB_Msk     (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
-/* =========================================================  AGTCR  ========================================================= */
- #define R_AGT0_AGTCR_TCMBF_Pos       (7UL)      /*!< TCMBF (Bit 7)                                         */
- #define R_AGT0_AGTCR_TCMBF_Msk       (0x80UL)   /*!< TCMBF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCMAF_Pos       (6UL)      /*!< TCMAF (Bit 6)                                         */
- #define R_AGT0_AGTCR_TCMAF_Msk       (0x40UL)   /*!< TCMAF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TUNDF_Pos       (5UL)      /*!< TUNDF (Bit 5)                                         */
- #define R_AGT0_AGTCR_TUNDF_Msk       (0x20UL)   /*!< TUNDF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TEDGF_Pos       (4UL)      /*!< TEDGF (Bit 4)                                         */
- #define R_AGT0_AGTCR_TEDGF_Msk       (0x10UL)   /*!< TEDGF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTOP_Pos       (2UL)      /*!< TSTOP (Bit 2)                                         */
- #define R_AGT0_AGTCR_TSTOP_Msk       (0x4UL)    /*!< TSTOP (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCSTF_Pos       (1UL)      /*!< TCSTF (Bit 1)                                         */
- #define R_AGT0_AGTCR_TCSTF_Msk       (0x2UL)    /*!< TCSTF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTART_Pos      (0UL)      /*!< TSTART (Bit 0)                                        */
- #define R_AGT0_AGTCR_TSTART_Msk      (0x1UL)    /*!< TSTART (Bitfield-Mask: 0x01)                          */
-/* ========================================================  AGTMR1  ========================================================= */
- #define R_AGT0_AGTMR1_TCK_Pos        (4UL)      /*!< TCK (Bit 4)                                           */
- #define R_AGT0_AGTMR1_TCK_Msk        (0x70UL)   /*!< TCK (Bitfield-Mask: 0x07)                             */
- #define R_AGT0_AGTMR1_TEDGPL_Pos     (3UL)      /*!< TEDGPL (Bit 3)                                        */
- #define R_AGT0_AGTMR1_TEDGPL_Msk     (0x8UL)    /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTMR1_TMOD_Pos       (0UL)      /*!< TMOD (Bit 0)                                          */
- #define R_AGT0_AGTMR1_TMOD_Msk       (0x7UL)    /*!< TMOD (Bitfield-Mask: 0x07)                            */
-/* ========================================================  AGTMR2  ========================================================= */
- #define R_AGT0_AGTMR2_LPM_Pos        (7UL)      /*!< LPM (Bit 7)                                           */
- #define R_AGT0_AGTMR2_LPM_Msk        (0x80UL)   /*!< LPM (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTMR2_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
- #define R_AGT0_AGTMR2_CKS_Msk        (0x7UL)    /*!< CKS (Bitfield-Mask: 0x07)                             */
-/* ========================================================  AGTIOC  ========================================================= */
- #define R_AGT0_AGTIOC_TIOGT_Pos      (6UL)      /*!< TIOGT (Bit 6)                                         */
- #define R_AGT0_AGTIOC_TIOGT_Msk      (0xc0UL)   /*!< TIOGT (Bitfield-Mask: 0x03)                           */
- #define R_AGT0_AGTIOC_TIPF_Pos       (4UL)      /*!< TIPF (Bit 4)                                          */
- #define R_AGT0_AGTIOC_TIPF_Msk       (0x30UL)   /*!< TIPF (Bitfield-Mask: 0x03)                            */
- #define R_AGT0_AGTIOC_TOE_Pos        (2UL)      /*!< TOE (Bit 2)                                           */
- #define R_AGT0_AGTIOC_TOE_Msk        (0x4UL)    /*!< TOE (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTIOC_TEDGSEL_Pos    (0UL)      /*!< TEDGSEL (Bit 0)                                       */
- #define R_AGT0_AGTIOC_TEDGSEL_Msk    (0x1UL)    /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
-/* ========================================================  AGTISR  ========================================================= */
- #define R_AGT0_AGTISR_EEPS_Pos       (2UL)      /*!< EEPS (Bit 2)                                          */
- #define R_AGT0_AGTISR_EEPS_Msk       (0x4UL)    /*!< EEPS (Bitfield-Mask: 0x01)                            */
-/* ========================================================  AGTCMSR  ======================================================== */
- #define R_AGT0_AGTCMSR_TOPOLB_Pos    (6UL)      /*!< TOPOLB (Bit 6)                                        */
- #define R_AGT0_AGTCMSR_TOPOLB_Msk    (0x40UL)   /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEB_Pos      (5UL)      /*!< TOEB (Bit 5)                                          */
- #define R_AGT0_AGTCMSR_TOEB_Msk      (0x20UL)   /*!< TOEB (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEB_Pos     (4UL)      /*!< TCMEB (Bit 4)                                         */
- #define R_AGT0_AGTCMSR_TCMEB_Msk     (0x10UL)   /*!< TCMEB (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCMSR_TOPOLA_Pos    (2UL)      /*!< TOPOLA (Bit 2)                                        */
- #define R_AGT0_AGTCMSR_TOPOLA_Msk    (0x4UL)    /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEA_Pos      (1UL)      /*!< TOEA (Bit 1)                                          */
- #define R_AGT0_AGTCMSR_TOEA_Msk      (0x2UL)    /*!< TOEA (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEA_Pos     (0UL)      /*!< TCMEA (Bit 0)                                         */
- #define R_AGT0_AGTCMSR_TCMEA_Msk     (0x1UL)    /*!< TCMEA (Bitfield-Mask: 0x01)                           */
-/* =======================================================  AGTIOSEL  ======================================================== */
- #define R_AGT0_AGTIOSEL_TIES_Pos     (4UL)      /*!< TIES (Bit 4)                                          */
- #define R_AGT0_AGTIOSEL_TIES_Msk     (0x10UL)   /*!< TIES (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTIOSEL_SEL_Pos      (0UL)      /*!< SEL (Bit 0)                                           */
- #define R_AGT0_AGTIOSEL_SEL_Msk      (0x3UL)    /*!< SEL (Bitfield-Mask: 0x03)                             */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -16192,10 +16708,22 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
 /* =========================================================  GTCR  ========================================================== */
+ #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
+ #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTCR_TPCS_Pos              (24UL)         /*!< TPCS (Bit 24)                                         */
  #define R_GPT0_GTCR_TPCS_Msk              (0x7000000UL)  /*!< TPCS (Bitfield-Mask: 0x07)                            */
  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
- #define R_GPT0_GTCR_MD_Msk                (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
+ #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
+ #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
+ #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
+ #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
 /* =======================================================  GTUDDTYC  ======================================================== */
@@ -16253,6 +16781,8 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
 /* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
+ #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
@@ -16261,8 +16791,16 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
- #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
- #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
+ #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
+ #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
+ #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
 /* =========================================================  GTST  ========================================================== */
  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
@@ -16319,6 +16857,8 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
+ #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
@@ -16408,6 +16948,67 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
 /* ========================================================  GTSOTR  ========================================================= */
  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
 /* ========================================================  GTICLF  ========================================================= */
  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
@@ -16450,14 +17051,113 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
+ #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
+ #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTBER2  ========================================================= */
+ #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
+ #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
+ #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
+ #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
+ #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
+ #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
+ #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
+ #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
+ #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
+ #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
+ #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
+ #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
+ #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
+ #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
+ #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
+ #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
+ #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
+ #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
+ #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
+ #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTOLBR  ========================================================= */
+ #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
+ #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
+ #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
+ #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  GTICCR  ========================================================= */
+ #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
+ #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
+ #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
+ #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
+ #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
+ #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
+ #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
+ #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
+ #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
+ #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
+ #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
+ #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
+ #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
+ #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
+ #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
+ #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
+ #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
+ #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
+ #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
+ #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
+ #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_ODC                                         ================ */
@@ -19185,6 +19885,9 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
 /* ======================================================  CECCKDIVCR  ======================================================= */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  I3CCKDIVCR  ======================================================= */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
 /* ======================================================  IICCKDIVCR  ======================================================= */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
@@ -20511,6 +21214,10 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_USB_HS0_DPUSRCR_FIXPHY_Pos          (0UL)        /*!< FIXPHY (Bit 0)                                        */
  #define R_USB_HS0_DPUSRCR_FIXPHY_Msk          (0x1UL)      /*!< FIXPHY (Bitfield-Mask: 0x01)                          */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
 /** @} */ /* End of group PosMask_peripherals */
 
  #ifdef __cplusplus
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h
index 8f65274b2..de10bcead 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h
@@ -820,7 +820,8 @@ typedef struct
             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
             uint8_t            : 1;
             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
-            uint8_t            : 2;
+            uint8_t            : 1;
+            __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
         } RTCCR_b;
     };
     __IM uint8_t RESERVED;
@@ -1027,6 +1028,213 @@ typedef struct
     };
 } R_USB_HS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
 
+/**
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
+            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
+            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
+            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
+            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
+            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
+        } AGTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
+            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
+            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
+            uint8_t              : 1;
+        } AGTMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+                                        *   ratio                                                                     */
+            uint8_t           : 4;
+            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
+        } AGTMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+                                        *   mode.                                                                     */
+            uint8_t             : 1;
+            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
+            uint8_t             : 1;
+            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
+            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
+        } AGTIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
+            uint8_t            : 5;
+        } AGTISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
+
+        struct
+        {
+            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
+            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
+            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
+            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
+            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
+            uint8_t              : 1;
+        } AGTCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_b;
+    };
+} R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
+
+        struct
+        {
+            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IM uint16_t                 RESERVED;
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
+} R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
+
+        struct
+        {
+            __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
+} R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_clusters */
 
 /* =========================================================================================================================== */
@@ -1394,16 +1602,17 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
 
     union
     {
-        __IM uint16_t ADDR[28];        /*!< (@ 0x00000020) A/D Data Register                                          */
+        __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
 
         struct
         {
             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
                                         *   storing the result of A/D conversion.                                     */
-        } ADDR_b[28];
+        } ADDR_b[29];
     };
-    __IM uint32_t RESERVED1[2];
-    __IM uint16_t RESERVED2;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+    __IM uint16_t RESERVED3;
 
     union
     {
@@ -1596,7 +1805,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint16_t                : 3;
         } ADSWTSTR2_b;
     };
-    __IM uint16_t RESERVED3;
+    __IM uint16_t RESERVED4;
 
     union
     {
@@ -1658,7 +1867,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 6;
         } ADACSR_b;
     };
-    __IM uint8_t RESERVED4;
+    __IM uint8_t RESERVED5;
 
     union
     {
@@ -1728,7 +1937,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
         } ADSER_b;
     };
-    __IM uint8_t RESERVED5;
+    __IM uint8_t RESERVED6;
 
     union
     {
@@ -1744,7 +1953,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
         } ADHVREFCNT_b;
     };
-    __IM uint8_t RESERVED6;
+    __IM uint8_t RESERVED7;
 
     union
     {
@@ -1762,8 +1971,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t              : 2;
         } ADWINMON_b;
     };
-    __IM uint8_t  RESERVED7;
-    __IM uint16_t RESERVED8;
+    __IM uint8_t  RESERVED8;
+    __IM uint16_t RESERVED9;
 
     union
     {
@@ -1939,7 +2148,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 6;
         } ADCMPSER_b;
     };
-    __IM uint8_t RESERVED9;
+    __IM uint8_t RESERVED10;
 
     union
     {
@@ -1954,7 +2163,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
         } ADCMPBNSR_b;
     };
-    __IM uint8_t RESERVED10;
+    __IM uint8_t RESERVED11;
 
     union
     {
@@ -1993,8 +2202,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 7;
         } ADCMPBSR_b;
     };
-    __IM uint8_t  RESERVED11;
-    __IM uint16_t RESERVED12;
+    __IM uint8_t  RESERVED12;
+    __IM uint16_t RESERVED13;
 
     union
     {
@@ -2198,7 +2407,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 7;
         } ADBUFEN_b;
     };
-    __IM uint8_t RESERVED13;
+    __IM uint8_t RESERVED14;
 
     union
     {
@@ -2212,9 +2421,9 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 3;
         } ADBUFPTR_b;
     };
-    __IM uint8_t  RESERVED14;
-    __IM uint32_t RESERVED15[2];
-    __IM uint8_t  RESERVED16;
+    __IM uint8_t  RESERVED15;
+    __IM uint32_t RESERVED16[2];
+    __IM uint8_t  RESERVED17;
 
     union
     {
@@ -2281,7 +2490,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
         } ADCALEXE_b;
     };
-    __IM uint8_t RESERVED17;
+    __IM uint8_t RESERVED18;
 
     union
     {
@@ -2298,8 +2507,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
         } VREFAMPCNT_b;
     };
-    __IM uint8_t  RESERVED18;
-    __IM uint16_t RESERVED19;
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -2321,8 +2530,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 6;
         } ADRST_b;
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint32_t RESERVED21[41];
+    __IM uint8_t  RESERVED21;
+    __IM uint32_t RESERVED22[41];
 
     union
     {
@@ -2380,7 +2589,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
         } ADPGAGS0_b;
     };
-    __IM uint32_t RESERVED22[3];
+    __IM uint32_t RESERVED23[3];
 
     union
     {
@@ -2407,7 +2616,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
         } ADPGADCR0_b;
     };
-    __IM uint16_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -2436,8 +2645,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 7;
         } ADPGADBS1_b;
     };
-    __IM uint16_t RESERVED24;
-    __IM uint32_t RESERVED25[10];
+    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED26[10];
 
     union
     {
@@ -2453,156 +2662,6 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
     };
 } R_ADC0_Type;                         /*!< Size = 484 (0x1e4)                                                        */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Asynchronous General Purpose Timer (R_AGT0)
- */
-
-typedef struct                         /*!< (@ 0x40084000) R_AGT0 Structure                                           */
-{
-    union
-    {
-        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
-
-        struct
-        {
-            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written
-                                        *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
-                                        *   is forcibly stopped and set to FFFFH.                                     */
-        } AGT_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCRn register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMA_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCR register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMB_b;
-    };
-    __IM uint16_t RESERVED;
-
-    union
-    {
-        __IOM uint8_t AGTCR;           /*!< (@ 0x00000008) AGT Control Register                                       */
-
-        struct
-        {
-            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
-            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
-            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
-            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
-            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
-            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
-        } AGTCR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000009) AGT Mode Register 1                                        */
-
-        struct
-        {
-            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
-            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
-            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
-            uint8_t              : 1;
-        } AGTMR1_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000A) AGT Mode Register 2                                        */
-
-        struct
-        {
-            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
-                                        *   ratio                                                                     */
-            uint8_t           : 4;
-            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
-        } AGTMR2_b;
-    };
-    __IM uint8_t RESERVED1;
-
-    union
-    {
-        __IOM uint8_t AGTIOC;          /*!< (@ 0x0000000C) AGT I/O Control Register                                   */
-
-        struct
-        {
-            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
-                                        *   mode.                                                                     */
-            uint8_t             : 1;
-            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
-            uint8_t             : 1;
-            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
-            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
-        } AGTIOC_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTISR;          /*!< (@ 0x0000000D) AGT Event Pin Select Register                              */
-
-        struct
-        {
-            uint8_t            : 2;
-            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
-            uint8_t            : 5;
-        } AGTISR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTCMSR;         /*!< (@ 0x0000000E) AGT Compare Match Function Select Register                 */
-
-        struct
-        {
-            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
-            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
-            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
-            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
-            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
-            uint8_t              : 1;
-        } AGTCMSR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x0000000F) AGT Pin Select Register                                    */
-
-        struct
-        {
-            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
-            uint8_t            : 2;
-            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
-            uint8_t            : 3;
-        } AGTIOSEL_b;
-    };
-} R_AGT0_Type;                         /*!< Size = 16 (0x10)                                                          */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -5433,46 +5492,99 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            uint32_t : 18;
         } GTSTR_b;
     };
 
@@ -5524,7 +5636,60 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
                                          *   1 means counter stop.                                                     */
-            uint32_t : 18;
+            __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
         } GTSTP_b;
     };
 
@@ -5548,7 +5713,24 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
-            uint32_t             : 18;
+            __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
         } GTCLR_b;
     };
 
@@ -5869,16 +6051,23 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+        __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
 
         struct
         {
-            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
-            uint32_t            : 15;
-            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
-            uint32_t            : 5;
-            __IOM uint32_t TPCS : 3;   /*!< [26..24] Timer Prescaler Select                                           */
-            uint32_t            : 5;
+            __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
+            uint32_t               : 7;
+            __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
+            __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
+            __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
+            __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
+            uint32_t               : 2;
+            __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
+            __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
+            uint32_t               : 4;
+            __IOM uint32_t TPCS    : 3; /*!< [26..24] Timer Prescaler Select                                           */
+            __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
+            uint32_t               : 3;
         } GTCR_b;
     };
 
@@ -5949,13 +6138,36 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
         struct
         {
-            uint32_t               : 24;
-            __IOM uint32_t GRP     : 2; /*!< [25..24] Output Disable Source Select                                     */
+            uint32_t            : 8;
+            __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
+            __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            uint32_t               : 4;
+            __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
             uint32_t               : 2;
-            __IOM uint32_t GRPDTE  : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
-            __IOM uint32_t GRPABH  : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable               */
-            __IOM uint32_t GRPABL  : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
-            __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
+            __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
+            __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
         } GTINTAD_b;
     };
 
@@ -5998,32 +6210,36 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTBER;          /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
 
         struct
         {
-            __IOM uint32_t BD0    : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
-            __IOM uint32_t BD1    : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
-            __IOM uint32_t BD2    : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
-            __IOM uint32_t BD3    : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
-            uint32_t              : 12;
-            __IOM uint32_t CCRA   : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
-            __IOM uint32_t CCRB   : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
-            __IOM uint32_t PR     : 2; /*!< [21..20] GTPR Buffer Operation                                            */
-            __OM uint32_t  CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
-                                        *   is read as 0.                                                             */
+            __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
+            __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+                                         *   is read as 0.                                                             */
             uint32_t             : 1;
-            __IOM uint32_t ADTTA : 2;  /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDA : 1;  /*!< [26..26] GTADTRA Double Buffer Operation                                  */
+            __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
             uint32_t             : 1;
-            __IOM uint32_t ADTTB : 2;  /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDB : 1;  /*!< [30..30] GTADTRB Double Buffer Operation                                  */
+            __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
             uint32_t             : 1;
         } GTBER_b;
     };
@@ -6247,7 +6463,126 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             uint32_t            : 31;
         } GTSOTR_b;
     };
-    __IM uint32_t RESERVED[5];
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
 
     union
     {
@@ -6281,7 +6616,7 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             uint32_t            : 4;
         } GTPC_b;
     };
-    __IM uint32_t RESERVED1[4];
+    __IM uint32_t RESERVED[4];
 
     union
     {
@@ -6323,17 +6658,137 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
         {
             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 4;
             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
-            uint32_t             : 7;
+            __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
+            uint32_t             : 6;
             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
-            uint32_t             : 7;
+            __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
+            uint32_t             : 6;
         } GTSECR_b;
     };
-} R_GPT0_Type;                         /*!< Size = 216 (0xd8)                                                         */
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
+            __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
+                                        *   Disable                                                                   */
+            uint32_t             : 2;
+            __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t             : 1;
+            __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
+                                        *   Transfer Disable                                                          */
+            uint32_t             : 2;
+            __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
+            __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
+            __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
+            __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
+            uint32_t             : 2;
+        } GTBER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
+
+        struct
+        {
+            __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
+            uint32_t              : 11;
+            __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
+            uint32_t              : 11;
+        } GTOLBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
+                                        *                  Capture Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
+            __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
+                                        *   Other Channel GTCCRb Input Capture Source Enable                          */
+            __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
+        } GTICCR_b;
+    };
+} R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_ODC                                         ================ */
@@ -12134,8 +12589,18 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } IICCKDIVCR_b;
         };
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint16_t RESERVED21;
+
+    union
+    {
+        __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
+
+        struct
+        {
+            __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
+            uint8_t                : 5;
+        } I3CCKDIVCR_b;
+    };
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -12262,8 +12727,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
         } I3CCKCR_b;
     };
-    __IM uint16_t RESERVED22;
-    __IM uint32_t RESERVED23[3];
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
 
     union
     {
@@ -12277,8 +12742,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                 : 29;
         } SNZREQCR1_b;
     };
-    __IM uint32_t RESERVED24;
-    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -12293,7 +12758,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
         } SNZCR_b;
     };
-    __IM uint8_t RESERVED26;
+    __IM uint8_t RESERVED25;
 
     union
     {
@@ -12323,7 +12788,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } SNZEDCR1_b;
     };
-    __IM uint16_t RESERVED27;
+    __IM uint16_t RESERVED26;
 
     union
     {
@@ -12366,7 +12831,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 1;
         } SNZREQCR_b;
     };
-    __IM uint16_t RESERVED28;
+    __IM uint16_t RESERVED27;
 
     union
     {
@@ -12404,7 +12869,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 3;
         } OPCCR_b;
     };
-    __IM uint8_t RESERVED29;
+    __IM uint8_t RESERVED28;
 
     union
     {
@@ -12416,7 +12881,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } MOSCWTCR_b;
     };
-    __IM uint8_t RESERVED30[2];
+    __IM uint8_t RESERVED29[2];
 
     union
     {
@@ -12429,7 +12894,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t : 5;
         } HOCOWTCR_b;
     };
-    __IM uint16_t RESERVED31[2];
+    __IM uint16_t RESERVED30[2];
 
     union
     {
@@ -12443,8 +12908,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 3;
         } SOPCCR_b;
     };
-    __IM uint8_t  RESERVED32;
-    __IM uint32_t RESERVED33[5];
+    __IM uint8_t  RESERVED31;
+    __IM uint32_t RESERVED32[5];
 
     union
     {
@@ -12478,8 +12943,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
         } RSTSR1_b;
     };
-    __IM uint16_t RESERVED34;
-    __IM uint32_t RESERVED35[3];
+    __IM uint16_t RESERVED33;
+    __IM uint32_t RESERVED34[3];
 
     union
     {
@@ -12505,8 +12970,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
         } SDADCCKCR_b;
     };
-    __IM uint16_t RESERVED36;
-    __IM uint32_t RESERVED37[3];
+    __IM uint16_t RESERVED35;
+    __IM uint32_t RESERVED36[3];
 
     union
     {
@@ -12561,7 +13026,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t          : 6;
         } LVD2SR_b;
     };
-    __IM uint32_t RESERVED38[183];
+    __IM uint32_t RESERVED37[183];
 
     union
     {
@@ -12589,7 +13054,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 14;
         } CGFSAR_b;
     };
-    __IM uint32_t RESERVED39;
+    __IM uint32_t RESERVED38;
 
     union
     {
@@ -12658,7 +13123,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 8;
         } BBFSAR_b;
     };
-    __IM uint32_t RESERVED40[3];
+    __IM uint32_t RESERVED39[3];
 
     union
     {
@@ -12720,8 +13185,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 4;
         } DPFSAR_b;
     };
-    __IM uint32_t RESERVED41[6];
-    __IM uint16_t RESERVED42;
+    __IM uint32_t RESERVED40[6];
+    __IM uint16_t RESERVED41;
 
     union
     {
@@ -12939,7 +13404,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 3;
         } DPSIEGR2_b;
     };
-    __IM uint8_t RESERVED43;
+    __IM uint8_t RESERVED42;
 
     union
     {
@@ -12997,7 +13462,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } RSTSR2_b;
     };
-    __IM uint8_t RESERVED44;
+    __IM uint8_t RESERVED43;
 
     union
     {
@@ -13014,7 +13479,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                           *   Enable                                                                    */
         } MOMCR_b;
     };
-    __IM uint16_t RESERVED45;
+    __IM uint16_t RESERVED44;
 
     union
     {
@@ -13084,7 +13549,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } LVD2CMPCR_b;
         };
     };
-    __IM uint8_t RESERVED46;
+    __IM uint8_t RESERVED45;
 
     union
     {
@@ -13117,7 +13582,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
         } LVD2CR0_b;
     };
-    __IM uint8_t RESERVED47;
+    __IM uint8_t RESERVED46;
 
     union
     {
@@ -13152,7 +13617,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 7;
         } VBTCR1_b;
     };
-    __IM uint32_t RESERVED48[8];
+    __IM uint32_t RESERVED47[8];
 
     union
     {
@@ -13195,7 +13660,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 6;
         } VCCSEL_b;
     };
-    __IM uint16_t RESERVED49;
+    __IM uint16_t RESERVED48;
 
     union
     {
@@ -13207,9 +13672,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } PL2LDOSCR_b;
     };
-    __IM uint8_t  RESERVED50;
-    __IM uint16_t RESERVED51;
-    __IM uint32_t RESERVED52[14];
+    __IM uint8_t  RESERVED49;
+    __IM uint16_t RESERVED50;
+    __IM uint32_t RESERVED51[14];
 
     union
     {
@@ -13232,8 +13697,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 6;
         } SOMCR_b;
     };
-    __IM uint16_t RESERVED53;
-    __IM uint32_t RESERVED54[3];
+    __IM uint16_t RESERVED52;
+    __IM uint32_t RESERVED53[3];
 
     union
     {
@@ -13245,7 +13710,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 7;
         } LOCOCR_b;
     };
-    __IM uint8_t RESERVED55;
+    __IM uint8_t RESERVED54;
 
     union
     {
@@ -13260,8 +13725,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                          *   trimming bits                                                             */
         } LOCOUTCR_b;
     };
-    __IM uint8_t  RESERVED56;
-    __IM uint32_t RESERVED57[7];
+    __IM uint8_t  RESERVED55;
+    __IM uint32_t RESERVED56[7];
 
     union
     {
@@ -13300,7 +13765,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 7;
         } VBTCMPCR_b;
     };
-    __IM uint8_t RESERVED58;
+    __IM uint8_t RESERVED57;
 
     union
     {
@@ -13314,7 +13779,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                  : 6;
         } VBTLVDICR_b;
     };
-    __IM uint8_t RESERVED59;
+    __IM uint8_t RESERVED58;
 
     union
     {
@@ -13326,7 +13791,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } VBTWCTLR_b;
     };
-    __IM uint8_t RESERVED60;
+    __IM uint8_t RESERVED59;
 
     union
     {
@@ -13461,9 +13926,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } VBTBER_b;
     };
-    __IM uint8_t  RESERVED61;
-    __IM uint16_t RESERVED62;
-    __IM uint32_t RESERVED63[15];
+    __IM uint8_t  RESERVED60;
+    __IM uint16_t RESERVED61;
+    __IM uint32_t RESERVED62[15];
 
     union
     {
@@ -15657,6 +16122,23 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
     };
 } R_USB_HS0_Type;                        /*!< Size = 364 (0x16c)                                                        */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
+ */
+
+typedef struct                          /*!< (@ 0x40084000) R_AGTX0 Structure                                          */
+{
+    union
+    {
+        __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
+        __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
+    };
+} R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_peripherals */
 
 /* =========================================================================================================================== */
@@ -15675,12 +16157,6 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_ACMPHS5_BASE         0x40085500UL
  #define R_ADC0_BASE            0x4005C000UL
  #define R_ADC1_BASE            0x4005C200UL
- #define R_AGT0_BASE            0x40084000UL
- #define R_AGT1_BASE            0x40084100UL
- #define R_AGT2_BASE            0x40084200UL
- #define R_AGT3_BASE            0x40084300UL
- #define R_AGT4_BASE            0x40084400UL
- #define R_AGT5_BASE            0x40084500UL
  #define R_BUS_BASE             0x40003000UL
  #define R_CAC_BASE             0x40044600UL
  #define R_CAN0_BASE            0x40050000UL
@@ -15782,6 +16258,16 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_USB_FS0_BASE         0x40090000UL
  #define R_WDT_BASE             0x40044200UL
  #define R_USB_HS0_BASE         0x40060000UL
+ #define R_AGTX0_BASE           0x40084000UL
+ #define R_AGTX1_BASE           0x40084100UL
+ #define R_AGTX2_BASE           0x40084200UL
+ #define R_AGTX3_BASE           0x40084300UL
+ #define R_AGTX4_BASE           0x40084400UL
+ #define R_AGTX5_BASE           0x40084500UL
+ #define R_AGTX6_BASE           0x40084600UL
+ #define R_AGTX7_BASE           0x40084700UL
+ #define R_AGTX8_BASE           0x40084800UL
+ #define R_AGTX9_BASE           0x40084900UL
 
 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
 
@@ -15801,12 +16287,6 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_ACMPHS5         ((R_ACMPHS0_Type *) R_ACMPHS5_BASE)
  #define R_ADC0            ((R_ADC0_Type *) R_ADC0_BASE)
  #define R_ADC1            ((R_ADC0_Type *) R_ADC1_BASE)
- #define R_AGT0            ((R_AGT0_Type *) R_AGT0_BASE)
- #define R_AGT1            ((R_AGT0_Type *) R_AGT1_BASE)
- #define R_AGT2            ((R_AGT0_Type *) R_AGT2_BASE)
- #define R_AGT3            ((R_AGT0_Type *) R_AGT3_BASE)
- #define R_AGT4            ((R_AGT0_Type *) R_AGT4_BASE)
- #define R_AGT5            ((R_AGT0_Type *) R_AGT5_BASE)
  #define R_BUS             ((R_BUS_Type *) R_BUS_BASE)
  #define R_CAC             ((R_CAC_Type *) R_CAC_BASE)
  #define R_CAN0            ((R_CAN0_Type *) R_CAN0_BASE)
@@ -15908,6 +16388,16 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_USB_FS0         ((R_USB_FS0_Type *) R_USB_FS0_BASE)
  #define R_WDT             ((R_WDT_Type *) R_WDT_BASE)
  #define R_USB_HS0         ((R_USB_HS0_Type *) R_USB_HS0_BASE)
+ #define R_AGTX0           ((R_AGTX0_Type *) R_AGTX0_BASE)
+ #define R_AGTX1           ((R_AGTX0_Type *) R_AGTX1_BASE)
+ #define R_AGTX2           ((R_AGTX0_Type *) R_AGTX2_BASE)
+ #define R_AGTX3           ((R_AGTX0_Type *) R_AGTX3_BASE)
+ #define R_AGTX4           ((R_AGTX0_Type *) R_AGTX4_BASE)
+ #define R_AGTX5           ((R_AGTX0_Type *) R_AGTX5_BASE)
+ #define R_AGTX6           ((R_AGTX0_Type *) R_AGTX6_BASE)
+ #define R_AGTX7           ((R_AGTX0_Type *) R_AGTX7_BASE)
+ #define R_AGTX8           ((R_AGTX0_Type *) R_AGTX8_BASE)
+ #define R_AGTX9           ((R_AGTX0_Type *) R_AGTX9_BASE)
 
 /** @} */ /* End of group Device_Peripheral_declaration */
 
@@ -16275,6 +16765,8 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
 /* =========================================================================================================================== */
 
 /* =========================================================  RTCCR  ========================================================= */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
@@ -16352,6 +16844,101 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
  #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
 
+/* =========================================================================================================================== */
+/* ================                                           CTRL                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  AGTCR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AGTMR1  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
+/* ========================================================  AGTMR2  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
+/* =====================================================  AGTIOSEL_ALT  ====================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+/* ========================================================  AGTIOC  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AGTISR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AGTCMSR  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
+/* =======================================================  AGTIOSEL  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT16                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT32                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
+
 /** @} */ /* End of group PosMask_clusters */
 
 /* =========================================================================================================================== */
@@ -16885,77 +17472,6 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_ADC0_ADREFMON_MONSEL_Pos         (16UL)      /*!< MONSEL (Bit 16)                                       */
  #define R_ADC0_ADREFMON_MONSEL_Msk         (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f)                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/* ==========================================================  AGT  ========================================================== */
- #define R_AGT0_AGT_AGT_Pos           (0UL)      /*!< AGT (Bit 0)                                           */
- #define R_AGT0_AGT_AGT_Msk           (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
-/* ========================================================  AGTCMA  ========================================================= */
- #define R_AGT0_AGTCMA_AGTCMA_Pos     (0UL)      /*!< AGTCMA (Bit 0)                                        */
- #define R_AGT0_AGTCMA_AGTCMA_Msk     (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
-/* ========================================================  AGTCMB  ========================================================= */
- #define R_AGT0_AGTCMB_AGTCMB_Pos     (0UL)      /*!< AGTCMB (Bit 0)                                        */
- #define R_AGT0_AGTCMB_AGTCMB_Msk     (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
-/* =========================================================  AGTCR  ========================================================= */
- #define R_AGT0_AGTCR_TCMBF_Pos       (7UL)      /*!< TCMBF (Bit 7)                                         */
- #define R_AGT0_AGTCR_TCMBF_Msk       (0x80UL)   /*!< TCMBF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCMAF_Pos       (6UL)      /*!< TCMAF (Bit 6)                                         */
- #define R_AGT0_AGTCR_TCMAF_Msk       (0x40UL)   /*!< TCMAF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TUNDF_Pos       (5UL)      /*!< TUNDF (Bit 5)                                         */
- #define R_AGT0_AGTCR_TUNDF_Msk       (0x20UL)   /*!< TUNDF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TEDGF_Pos       (4UL)      /*!< TEDGF (Bit 4)                                         */
- #define R_AGT0_AGTCR_TEDGF_Msk       (0x10UL)   /*!< TEDGF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTOP_Pos       (2UL)      /*!< TSTOP (Bit 2)                                         */
- #define R_AGT0_AGTCR_TSTOP_Msk       (0x4UL)    /*!< TSTOP (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCSTF_Pos       (1UL)      /*!< TCSTF (Bit 1)                                         */
- #define R_AGT0_AGTCR_TCSTF_Msk       (0x2UL)    /*!< TCSTF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTART_Pos      (0UL)      /*!< TSTART (Bit 0)                                        */
- #define R_AGT0_AGTCR_TSTART_Msk      (0x1UL)    /*!< TSTART (Bitfield-Mask: 0x01)                          */
-/* ========================================================  AGTMR1  ========================================================= */
- #define R_AGT0_AGTMR1_TCK_Pos        (4UL)      /*!< TCK (Bit 4)                                           */
- #define R_AGT0_AGTMR1_TCK_Msk        (0x70UL)   /*!< TCK (Bitfield-Mask: 0x07)                             */
- #define R_AGT0_AGTMR1_TEDGPL_Pos     (3UL)      /*!< TEDGPL (Bit 3)                                        */
- #define R_AGT0_AGTMR1_TEDGPL_Msk     (0x8UL)    /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTMR1_TMOD_Pos       (0UL)      /*!< TMOD (Bit 0)                                          */
- #define R_AGT0_AGTMR1_TMOD_Msk       (0x7UL)    /*!< TMOD (Bitfield-Mask: 0x07)                            */
-/* ========================================================  AGTMR2  ========================================================= */
- #define R_AGT0_AGTMR2_LPM_Pos        (7UL)      /*!< LPM (Bit 7)                                           */
- #define R_AGT0_AGTMR2_LPM_Msk        (0x80UL)   /*!< LPM (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTMR2_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
- #define R_AGT0_AGTMR2_CKS_Msk        (0x7UL)    /*!< CKS (Bitfield-Mask: 0x07)                             */
-/* ========================================================  AGTIOC  ========================================================= */
- #define R_AGT0_AGTIOC_TIOGT_Pos      (6UL)      /*!< TIOGT (Bit 6)                                         */
- #define R_AGT0_AGTIOC_TIOGT_Msk      (0xc0UL)   /*!< TIOGT (Bitfield-Mask: 0x03)                           */
- #define R_AGT0_AGTIOC_TIPF_Pos       (4UL)      /*!< TIPF (Bit 4)                                          */
- #define R_AGT0_AGTIOC_TIPF_Msk       (0x30UL)   /*!< TIPF (Bitfield-Mask: 0x03)                            */
- #define R_AGT0_AGTIOC_TOE_Pos        (2UL)      /*!< TOE (Bit 2)                                           */
- #define R_AGT0_AGTIOC_TOE_Msk        (0x4UL)    /*!< TOE (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTIOC_TEDGSEL_Pos    (0UL)      /*!< TEDGSEL (Bit 0)                                       */
- #define R_AGT0_AGTIOC_TEDGSEL_Msk    (0x1UL)    /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
-/* ========================================================  AGTISR  ========================================================= */
- #define R_AGT0_AGTISR_EEPS_Pos       (2UL)      /*!< EEPS (Bit 2)                                          */
- #define R_AGT0_AGTISR_EEPS_Msk       (0x4UL)    /*!< EEPS (Bitfield-Mask: 0x01)                            */
-/* ========================================================  AGTCMSR  ======================================================== */
- #define R_AGT0_AGTCMSR_TOPOLB_Pos    (6UL)      /*!< TOPOLB (Bit 6)                                        */
- #define R_AGT0_AGTCMSR_TOPOLB_Msk    (0x40UL)   /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEB_Pos      (5UL)      /*!< TOEB (Bit 5)                                          */
- #define R_AGT0_AGTCMSR_TOEB_Msk      (0x20UL)   /*!< TOEB (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEB_Pos     (4UL)      /*!< TCMEB (Bit 4)                                         */
- #define R_AGT0_AGTCMSR_TCMEB_Msk     (0x10UL)   /*!< TCMEB (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCMSR_TOPOLA_Pos    (2UL)      /*!< TOPOLA (Bit 2)                                        */
- #define R_AGT0_AGTCMSR_TOPOLA_Msk    (0x4UL)    /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEA_Pos      (1UL)      /*!< TOEA (Bit 1)                                          */
- #define R_AGT0_AGTCMSR_TOEA_Msk      (0x2UL)    /*!< TOEA (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEA_Pos     (0UL)      /*!< TCMEA (Bit 0)                                         */
- #define R_AGT0_AGTCMSR_TCMEA_Msk     (0x1UL)    /*!< TCMEA (Bitfield-Mask: 0x01)                           */
-/* =======================================================  AGTIOSEL  ======================================================== */
- #define R_AGT0_AGTIOSEL_TIES_Pos     (4UL)      /*!< TIES (Bit 4)                                          */
- #define R_AGT0_AGTIOSEL_TIES_Msk     (0x10UL)   /*!< TIES (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTIOSEL_SEL_Pos      (0UL)      /*!< SEL (Bit 0)                                           */
- #define R_AGT0_AGTIOSEL_SEL_Msk      (0x3UL)    /*!< SEL (Bitfield-Mask: 0x03)                             */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -18477,10 +18993,22 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
 /* =========================================================  GTCR  ========================================================== */
+ #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
+ #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTCR_TPCS_Pos              (24UL)         /*!< TPCS (Bit 24)                                         */
  #define R_GPT0_GTCR_TPCS_Msk              (0x7000000UL)  /*!< TPCS (Bitfield-Mask: 0x07)                            */
  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
- #define R_GPT0_GTCR_MD_Msk                (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
+ #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
+ #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
+ #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
+ #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
 /* =======================================================  GTUDDTYC  ======================================================== */
@@ -18538,6 +19066,8 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
 /* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
+ #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
@@ -18546,8 +19076,16 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
- #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
- #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
+ #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
+ #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
+ #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
 /* =========================================================  GTST  ========================================================== */
  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
@@ -18604,6 +19142,8 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
+ #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
@@ -18693,6 +19233,67 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
 /* ========================================================  GTSOTR  ========================================================= */
  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
 /* ========================================================  GTICLF  ========================================================= */
  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
@@ -18735,14 +19336,113 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
+ #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
+ #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTBER2  ========================================================= */
+ #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
+ #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
+ #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
+ #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
+ #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
+ #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
+ #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
+ #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
+ #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
+ #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
+ #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
+ #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
+ #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
+ #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
+ #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
+ #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
+ #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
+ #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
+ #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
+ #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTOLBR  ========================================================= */
+ #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
+ #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
+ #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
+ #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  GTICCR  ========================================================= */
+ #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
+ #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
+ #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
+ #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
+ #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
+ #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
+ #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
+ #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
+ #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
+ #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
+ #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
+ #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
+ #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
+ #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
+ #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
+ #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
+ #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
+ #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
+ #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
+ #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
+ #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_ODC                                         ================ */
@@ -22169,6 +22869,9 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
 /* ======================================================  CECCKDIVCR  ======================================================= */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  I3CCKDIVCR  ======================================================= */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
 /* ======================================================  IICCKDIVCR  ======================================================= */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
@@ -23495,6 +24198,10 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_USB_HS0_DPUSRCR_FIXPHY_Pos          (0UL)        /*!< FIXPHY (Bit 0)                                        */
  #define R_USB_HS0_DPUSRCR_FIXPHY_Msk          (0x1UL)      /*!< FIXPHY (Bitfield-Mask: 0x01)                          */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
 /** @} */ /* End of group PosMask_peripherals */
 
  #ifdef __cplusplus
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h
index a3866a8e2..d2ab6789b 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h
@@ -1730,7 +1730,8 @@ typedef struct
             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
             uint8_t            : 1;
             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
-            uint8_t            : 2;
+            uint8_t            : 1;
+            __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
         } RTCCR_b;
     };
     __IM uint8_t RESERVED;
@@ -1937,6 +1938,213 @@ typedef struct
     };
 } R_USB_HS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
 
+/**
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
+            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
+            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
+            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
+            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
+            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
+        } AGTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
+            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
+            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
+            uint8_t              : 1;
+        } AGTMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+                                        *   ratio                                                                     */
+            uint8_t           : 4;
+            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
+        } AGTMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+                                        *   mode.                                                                     */
+            uint8_t             : 1;
+            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
+            uint8_t             : 1;
+            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
+            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
+        } AGTIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
+            uint8_t            : 5;
+        } AGTISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
+
+        struct
+        {
+            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
+            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
+            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
+            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
+            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
+            uint8_t              : 1;
+        } AGTCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_b;
+    };
+} R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
+
+        struct
+        {
+            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IM uint16_t                 RESERVED;
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
+} R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
+
+        struct
+        {
+            __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
+} R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_clusters */
 
 /* =========================================================================================================================== */
@@ -2304,16 +2512,17 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
 
     union
     {
-        __IM uint16_t ADDR[28];        /*!< (@ 0x00000020) A/D Data Register                                          */
+        __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
 
         struct
         {
             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
                                         *   storing the result of A/D conversion.                                     */
-        } ADDR_b[28];
+        } ADDR_b[29];
     };
-    __IM uint32_t RESERVED1[2];
-    __IM uint16_t RESERVED2;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+    __IM uint16_t RESERVED3;
 
     union
     {
@@ -2506,7 +2715,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint16_t                : 3;
         } ADSWTSTR2_b;
     };
-    __IM uint16_t RESERVED3;
+    __IM uint16_t RESERVED4;
 
     union
     {
@@ -2568,7 +2777,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 6;
         } ADACSR_b;
     };
-    __IM uint8_t RESERVED4;
+    __IM uint8_t RESERVED5;
 
     union
     {
@@ -2638,7 +2847,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
         } ADSER_b;
     };
-    __IM uint8_t RESERVED5;
+    __IM uint8_t RESERVED6;
 
     union
     {
@@ -2654,7 +2863,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
         } ADHVREFCNT_b;
     };
-    __IM uint8_t RESERVED6;
+    __IM uint8_t RESERVED7;
 
     union
     {
@@ -2672,8 +2881,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t              : 2;
         } ADWINMON_b;
     };
-    __IM uint8_t  RESERVED7;
-    __IM uint16_t RESERVED8;
+    __IM uint8_t  RESERVED8;
+    __IM uint16_t RESERVED9;
 
     union
     {
@@ -2849,7 +3058,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 6;
         } ADCMPSER_b;
     };
-    __IM uint8_t RESERVED9;
+    __IM uint8_t RESERVED10;
 
     union
     {
@@ -2864,7 +3073,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
         } ADCMPBNSR_b;
     };
-    __IM uint8_t RESERVED10;
+    __IM uint8_t RESERVED11;
 
     union
     {
@@ -2903,8 +3112,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 7;
         } ADCMPBSR_b;
     };
-    __IM uint8_t  RESERVED11;
-    __IM uint16_t RESERVED12;
+    __IM uint8_t  RESERVED12;
+    __IM uint16_t RESERVED13;
 
     union
     {
@@ -3108,7 +3317,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 7;
         } ADBUFEN_b;
     };
-    __IM uint8_t RESERVED13;
+    __IM uint8_t RESERVED14;
 
     union
     {
@@ -3122,9 +3331,9 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 3;
         } ADBUFPTR_b;
     };
-    __IM uint8_t  RESERVED14;
-    __IM uint32_t RESERVED15[2];
-    __IM uint8_t  RESERVED16;
+    __IM uint8_t  RESERVED15;
+    __IM uint32_t RESERVED16[2];
+    __IM uint8_t  RESERVED17;
 
     union
     {
@@ -3191,7 +3400,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
         } ADCALEXE_b;
     };
-    __IM uint8_t RESERVED17;
+    __IM uint8_t RESERVED18;
 
     union
     {
@@ -3208,8 +3417,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
         } VREFAMPCNT_b;
     };
-    __IM uint8_t  RESERVED18;
-    __IM uint16_t RESERVED19;
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -3231,8 +3440,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 6;
         } ADRST_b;
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint32_t RESERVED21[41];
+    __IM uint8_t  RESERVED21;
+    __IM uint32_t RESERVED22[41];
 
     union
     {
@@ -3290,7 +3499,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
         } ADPGAGS0_b;
     };
-    __IM uint32_t RESERVED22[3];
+    __IM uint32_t RESERVED23[3];
 
     union
     {
@@ -3317,7 +3526,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
         } ADPGADCR0_b;
     };
-    __IM uint16_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -3346,8 +3555,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 7;
         } ADPGADBS1_b;
     };
-    __IM uint16_t RESERVED24;
-    __IM uint32_t RESERVED25[10];
+    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED26[10];
 
     union
     {
@@ -3363,156 +3572,6 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
     };
 } R_ADC0_Type;                         /*!< Size = 484 (0x1e4)                                                        */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Asynchronous General Purpose Timer (R_AGT0)
- */
-
-typedef struct                         /*!< (@ 0x40084000) R_AGT0 Structure                                           */
-{
-    union
-    {
-        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
-
-        struct
-        {
-            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written
-                                        *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
-                                        *   is forcibly stopped and set to FFFFH.                                     */
-        } AGT_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCRn register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMA_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCR register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMB_b;
-    };
-    __IM uint16_t RESERVED;
-
-    union
-    {
-        __IOM uint8_t AGTCR;           /*!< (@ 0x00000008) AGT Control Register                                       */
-
-        struct
-        {
-            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
-            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
-            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
-            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
-            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
-            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
-        } AGTCR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000009) AGT Mode Register 1                                        */
-
-        struct
-        {
-            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
-            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
-            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
-            uint8_t              : 1;
-        } AGTMR1_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000A) AGT Mode Register 2                                        */
-
-        struct
-        {
-            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
-                                        *   ratio                                                                     */
-            uint8_t           : 4;
-            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
-        } AGTMR2_b;
-    };
-    __IM uint8_t RESERVED1;
-
-    union
-    {
-        __IOM uint8_t AGTIOC;          /*!< (@ 0x0000000C) AGT I/O Control Register                                   */
-
-        struct
-        {
-            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
-                                        *   mode.                                                                     */
-            uint8_t             : 1;
-            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
-            uint8_t             : 1;
-            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
-            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
-        } AGTIOC_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTISR;          /*!< (@ 0x0000000D) AGT Event Pin Select Register                              */
-
-        struct
-        {
-            uint8_t            : 2;
-            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
-            uint8_t            : 5;
-        } AGTISR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTCMSR;         /*!< (@ 0x0000000E) AGT Compare Match Function Select Register                 */
-
-        struct
-        {
-            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
-            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
-            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
-            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
-            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
-            uint8_t              : 1;
-        } AGTCMSR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x0000000F) AGT Pin Select Register                                    */
-
-        struct
-        {
-            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
-            uint8_t            : 2;
-            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
-            uint8_t            : 3;
-        } AGTIOSEL_b;
-    };
-} R_AGT0_Type;                         /*!< Size = 16 (0x10)                                                          */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -8706,46 +8765,99 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            uint32_t : 18;
         } GTSTR_b;
     };
 
@@ -8797,7 +8909,60 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
                                          *   1 means counter stop.                                                     */
-            uint32_t : 18;
+            __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
         } GTSTP_b;
     };
 
@@ -8821,7 +8986,24 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
-            uint32_t             : 18;
+            __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
         } GTCLR_b;
     };
 
@@ -9142,16 +9324,23 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+        __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
 
         struct
         {
-            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
-            uint32_t            : 15;
-            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
-            uint32_t            : 5;
-            __IOM uint32_t TPCS : 3;   /*!< [26..24] Timer Prescaler Select                                           */
-            uint32_t            : 5;
+            __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
+            uint32_t               : 7;
+            __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
+            __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
+            __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
+            __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
+            uint32_t               : 2;
+            __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
+            __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
+            uint32_t               : 4;
+            __IOM uint32_t TPCS    : 3; /*!< [26..24] Timer Prescaler Select                                           */
+            __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
+            uint32_t               : 3;
         } GTCR_b;
     };
 
@@ -9222,13 +9411,36 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
         struct
         {
-            uint32_t               : 24;
-            __IOM uint32_t GRP     : 2; /*!< [25..24] Output Disable Source Select                                     */
+            uint32_t            : 8;
+            __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
+            __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            uint32_t               : 4;
+            __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
             uint32_t               : 2;
-            __IOM uint32_t GRPDTE  : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
-            __IOM uint32_t GRPABH  : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable               */
-            __IOM uint32_t GRPABL  : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
-            __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
+            __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
+            __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
         } GTINTAD_b;
     };
 
@@ -9271,32 +9483,36 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTBER;          /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
 
         struct
         {
-            __IOM uint32_t BD0    : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
-            __IOM uint32_t BD1    : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
-            __IOM uint32_t BD2    : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
-            __IOM uint32_t BD3    : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
-            uint32_t              : 12;
-            __IOM uint32_t CCRA   : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
-            __IOM uint32_t CCRB   : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
-            __IOM uint32_t PR     : 2; /*!< [21..20] GTPR Buffer Operation                                            */
-            __OM uint32_t  CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
-                                        *   is read as 0.                                                             */
+            __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
+            __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+                                         *   is read as 0.                                                             */
             uint32_t             : 1;
-            __IOM uint32_t ADTTA : 2;  /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDA : 1;  /*!< [26..26] GTADTRA Double Buffer Operation                                  */
+            __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
             uint32_t             : 1;
-            __IOM uint32_t ADTTB : 2;  /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDB : 1;  /*!< [30..30] GTADTRB Double Buffer Operation                                  */
+            __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
             uint32_t             : 1;
         } GTBER_b;
     };
@@ -9520,7 +9736,126 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             uint32_t            : 31;
         } GTSOTR_b;
     };
-    __IM uint32_t RESERVED[5];
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
 
     union
     {
@@ -9554,7 +9889,7 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             uint32_t            : 4;
         } GTPC_b;
     };
-    __IM uint32_t RESERVED1[4];
+    __IM uint32_t RESERVED[4];
 
     union
     {
@@ -9596,17 +9931,137 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
         {
             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 4;
             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
-            uint32_t             : 7;
+            __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
+            uint32_t             : 6;
             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
-            uint32_t             : 7;
+            __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
+            uint32_t             : 6;
         } GTSECR_b;
     };
-} R_GPT0_Type;                         /*!< Size = 216 (0xd8)                                                         */
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
+            __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
+                                        *   Disable                                                                   */
+            uint32_t             : 2;
+            __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t             : 1;
+            __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
+                                        *   Transfer Disable                                                          */
+            uint32_t             : 2;
+            __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
+            __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
+            __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
+            __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
+            uint32_t             : 2;
+        } GTBER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
+
+        struct
+        {
+            __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
+            uint32_t              : 11;
+            __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
+            uint32_t              : 11;
+        } GTOLBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
+                                        *                  Capture Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
+            __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
+                                        *   Other Channel GTCCRb Input Capture Source Enable                          */
+            __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
+        } GTICCR_b;
+    };
+} R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_ODC                                         ================ */
@@ -14792,8 +15247,18 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } IICCKDIVCR_b;
         };
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint16_t RESERVED21;
+
+    union
+    {
+        __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
+
+        struct
+        {
+            __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
+            uint8_t                : 5;
+        } I3CCKDIVCR_b;
+    };
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -14920,8 +15385,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
         } I3CCKCR_b;
     };
-    __IM uint16_t RESERVED22;
-    __IM uint32_t RESERVED23[3];
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
 
     union
     {
@@ -14935,8 +15400,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                 : 29;
         } SNZREQCR1_b;
     };
-    __IM uint32_t RESERVED24;
-    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -14951,7 +15416,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
         } SNZCR_b;
     };
-    __IM uint8_t RESERVED26;
+    __IM uint8_t RESERVED25;
 
     union
     {
@@ -14981,7 +15446,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } SNZEDCR1_b;
     };
-    __IM uint16_t RESERVED27;
+    __IM uint16_t RESERVED26;
 
     union
     {
@@ -15024,7 +15489,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 1;
         } SNZREQCR_b;
     };
-    __IM uint16_t RESERVED28;
+    __IM uint16_t RESERVED27;
 
     union
     {
@@ -15062,7 +15527,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 3;
         } OPCCR_b;
     };
-    __IM uint8_t RESERVED29;
+    __IM uint8_t RESERVED28;
 
     union
     {
@@ -15074,7 +15539,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } MOSCWTCR_b;
     };
-    __IM uint8_t RESERVED30[2];
+    __IM uint8_t RESERVED29[2];
 
     union
     {
@@ -15087,7 +15552,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t : 5;
         } HOCOWTCR_b;
     };
-    __IM uint16_t RESERVED31[2];
+    __IM uint16_t RESERVED30[2];
 
     union
     {
@@ -15101,8 +15566,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 3;
         } SOPCCR_b;
     };
-    __IM uint8_t  RESERVED32;
-    __IM uint32_t RESERVED33[5];
+    __IM uint8_t  RESERVED31;
+    __IM uint32_t RESERVED32[5];
 
     union
     {
@@ -15136,8 +15601,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
         } RSTSR1_b;
     };
-    __IM uint16_t RESERVED34;
-    __IM uint32_t RESERVED35[3];
+    __IM uint16_t RESERVED33;
+    __IM uint32_t RESERVED34[3];
 
     union
     {
@@ -15163,8 +15628,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
         } SDADCCKCR_b;
     };
-    __IM uint16_t RESERVED36;
-    __IM uint32_t RESERVED37[3];
+    __IM uint16_t RESERVED35;
+    __IM uint32_t RESERVED36[3];
 
     union
     {
@@ -15219,7 +15684,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t          : 6;
         } LVD2SR_b;
     };
-    __IM uint32_t RESERVED38[183];
+    __IM uint32_t RESERVED37[183];
 
     union
     {
@@ -15247,7 +15712,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 14;
         } CGFSAR_b;
     };
-    __IM uint32_t RESERVED39;
+    __IM uint32_t RESERVED38;
 
     union
     {
@@ -15316,7 +15781,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 8;
         } BBFSAR_b;
     };
-    __IM uint32_t RESERVED40[3];
+    __IM uint32_t RESERVED39[3];
 
     union
     {
@@ -15378,8 +15843,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 4;
         } DPFSAR_b;
     };
-    __IM uint32_t RESERVED41[6];
-    __IM uint16_t RESERVED42;
+    __IM uint32_t RESERVED40[6];
+    __IM uint16_t RESERVED41;
 
     union
     {
@@ -15597,7 +16062,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 3;
         } DPSIEGR2_b;
     };
-    __IM uint8_t RESERVED43;
+    __IM uint8_t RESERVED42;
 
     union
     {
@@ -15655,7 +16120,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } RSTSR2_b;
     };
-    __IM uint8_t RESERVED44;
+    __IM uint8_t RESERVED43;
 
     union
     {
@@ -15672,7 +16137,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                           *   Enable                                                                    */
         } MOMCR_b;
     };
-    __IM uint16_t RESERVED45;
+    __IM uint16_t RESERVED44;
 
     union
     {
@@ -15742,7 +16207,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } LVD2CMPCR_b;
         };
     };
-    __IM uint8_t RESERVED46;
+    __IM uint8_t RESERVED45;
 
     union
     {
@@ -15775,7 +16240,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
         } LVD2CR0_b;
     };
-    __IM uint8_t RESERVED47;
+    __IM uint8_t RESERVED46;
 
     union
     {
@@ -15810,7 +16275,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 7;
         } VBTCR1_b;
     };
-    __IM uint32_t RESERVED48[8];
+    __IM uint32_t RESERVED47[8];
 
     union
     {
@@ -15853,7 +16318,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 6;
         } VCCSEL_b;
     };
-    __IM uint16_t RESERVED49;
+    __IM uint16_t RESERVED48;
 
     union
     {
@@ -15865,9 +16330,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } PL2LDOSCR_b;
     };
-    __IM uint8_t  RESERVED50;
-    __IM uint16_t RESERVED51;
-    __IM uint32_t RESERVED52[14];
+    __IM uint8_t  RESERVED49;
+    __IM uint16_t RESERVED50;
+    __IM uint32_t RESERVED51[14];
 
     union
     {
@@ -15890,8 +16355,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 6;
         } SOMCR_b;
     };
-    __IM uint16_t RESERVED53;
-    __IM uint32_t RESERVED54[3];
+    __IM uint16_t RESERVED52;
+    __IM uint32_t RESERVED53[3];
 
     union
     {
@@ -15903,7 +16368,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 7;
         } LOCOCR_b;
     };
-    __IM uint8_t RESERVED55;
+    __IM uint8_t RESERVED54;
 
     union
     {
@@ -15918,8 +16383,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                          *   trimming bits                                                             */
         } LOCOUTCR_b;
     };
-    __IM uint8_t  RESERVED56;
-    __IM uint32_t RESERVED57[7];
+    __IM uint8_t  RESERVED55;
+    __IM uint32_t RESERVED56[7];
 
     union
     {
@@ -15958,7 +16423,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 7;
         } VBTCMPCR_b;
     };
-    __IM uint8_t RESERVED58;
+    __IM uint8_t RESERVED57;
 
     union
     {
@@ -15972,7 +16437,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                  : 6;
         } VBTLVDICR_b;
     };
-    __IM uint8_t RESERVED59;
+    __IM uint8_t RESERVED58;
 
     union
     {
@@ -15984,7 +16449,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } VBTWCTLR_b;
     };
-    __IM uint8_t RESERVED60;
+    __IM uint8_t RESERVED59;
 
     union
     {
@@ -16119,9 +16584,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } VBTBER_b;
     };
-    __IM uint8_t  RESERVED61;
-    __IM uint16_t RESERVED62;
-    __IM uint32_t RESERVED63[15];
+    __IM uint8_t  RESERVED60;
+    __IM uint16_t RESERVED61;
+    __IM uint32_t RESERVED62[15];
 
     union
     {
@@ -18315,6 +18780,23 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
     };
 } R_USB_HS0_Type;                        /*!< Size = 364 (0x16c)                                                        */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
+ */
+
+typedef struct                          /*!< (@ 0x40084000) R_AGTX0 Structure                                          */
+{
+    union
+    {
+        __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
+        __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
+    };
+} R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_peripherals */
 
 /* =========================================================================================================================== */
@@ -18333,12 +18815,6 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_ACMPHS5_BASE                0x40085500UL
  #define R_ADC0_BASE                   0x4005C000UL
  #define R_ADC1_BASE                   0x4005C200UL
- #define R_AGT0_BASE                   0x40084000UL
- #define R_AGT1_BASE                   0x40084100UL
- #define R_AGT2_BASE                   0x40084200UL
- #define R_AGT3_BASE                   0x40084300UL
- #define R_AGT4_BASE                   0x40084400UL
- #define R_AGT5_BASE                   0x40084500UL
  #define R_BUS_BASE                    0x40003000UL
  #define R_CAC_BASE                    0x40044600UL
  #define R_CAN0_BASE                   0x40050000UL
@@ -18446,6 +18922,16 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_USB_FS0_BASE                0x40090000UL
  #define R_WDT_BASE                    0x40044200UL
  #define R_USB_HS0_BASE                0x40060000UL
+ #define R_AGTX0_BASE                  0x40084000UL
+ #define R_AGTX1_BASE                  0x40084100UL
+ #define R_AGTX2_BASE                  0x40084200UL
+ #define R_AGTX3_BASE                  0x40084300UL
+ #define R_AGTX4_BASE                  0x40084400UL
+ #define R_AGTX5_BASE                  0x40084500UL
+ #define R_AGTX6_BASE                  0x40084600UL
+ #define R_AGTX7_BASE                  0x40084700UL
+ #define R_AGTX8_BASE                  0x40084800UL
+ #define R_AGTX9_BASE                  0x40084900UL
 
 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
 
@@ -18465,12 +18951,6 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_ACMPHS5                ((R_ACMPHS0_Type *) R_ACMPHS5_BASE)
  #define R_ADC0                   ((R_ADC0_Type *) R_ADC0_BASE)
  #define R_ADC1                   ((R_ADC0_Type *) R_ADC1_BASE)
- #define R_AGT0                   ((R_AGT0_Type *) R_AGT0_BASE)
- #define R_AGT1                   ((R_AGT0_Type *) R_AGT1_BASE)
- #define R_AGT2                   ((R_AGT0_Type *) R_AGT2_BASE)
- #define R_AGT3                   ((R_AGT0_Type *) R_AGT3_BASE)
- #define R_AGT4                   ((R_AGT0_Type *) R_AGT4_BASE)
- #define R_AGT5                   ((R_AGT0_Type *) R_AGT5_BASE)
  #define R_BUS                    ((R_BUS_Type *) R_BUS_BASE)
  #define R_CAC                    ((R_CAC_Type *) R_CAC_BASE)
  #define R_CAN0                   ((R_CAN0_Type *) R_CAN0_BASE)
@@ -18578,6 +19058,16 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_USB_FS0                ((R_USB_FS0_Type *) R_USB_FS0_BASE)
  #define R_WDT                    ((R_WDT_Type *) R_WDT_BASE)
  #define R_USB_HS0                ((R_USB_HS0_Type *) R_USB_HS0_BASE)
+ #define R_AGTX0                  ((R_AGTX0_Type *) R_AGTX0_BASE)
+ #define R_AGTX1                  ((R_AGTX0_Type *) R_AGTX1_BASE)
+ #define R_AGTX2                  ((R_AGTX0_Type *) R_AGTX2_BASE)
+ #define R_AGTX3                  ((R_AGTX0_Type *) R_AGTX3_BASE)
+ #define R_AGTX4                  ((R_AGTX0_Type *) R_AGTX4_BASE)
+ #define R_AGTX5                  ((R_AGTX0_Type *) R_AGTX5_BASE)
+ #define R_AGTX6                  ((R_AGTX0_Type *) R_AGTX6_BASE)
+ #define R_AGTX7                  ((R_AGTX0_Type *) R_AGTX7_BASE)
+ #define R_AGTX8                  ((R_AGTX0_Type *) R_AGTX8_BASE)
+ #define R_AGTX9                  ((R_AGTX0_Type *) R_AGTX9_BASE)
 
 /** @} */ /* End of group Device_Peripheral_declaration */
 
@@ -19299,6 +19789,8 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
 /* =========================================================================================================================== */
 
 /* =========================================================  RTCCR  ========================================================= */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
@@ -19376,6 +19868,101 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
  #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
 
+/* =========================================================================================================================== */
+/* ================                                           CTRL                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  AGTCR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AGTMR1  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
+/* ========================================================  AGTMR2  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
+/* =====================================================  AGTIOSEL_ALT  ====================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+/* ========================================================  AGTIOC  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AGTISR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AGTCMSR  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
+/* =======================================================  AGTIOSEL  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT16                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT32                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
+
 /** @} */ /* End of group PosMask_clusters */
 
 /* =========================================================================================================================== */
@@ -19909,77 +20496,6 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_ADC0_ADREFMON_MONSEL_Pos         (16UL)      /*!< MONSEL (Bit 16)                                       */
  #define R_ADC0_ADREFMON_MONSEL_Msk         (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f)                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/* ==========================================================  AGT  ========================================================== */
- #define R_AGT0_AGT_AGT_Pos           (0UL)      /*!< AGT (Bit 0)                                           */
- #define R_AGT0_AGT_AGT_Msk           (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
-/* ========================================================  AGTCMA  ========================================================= */
- #define R_AGT0_AGTCMA_AGTCMA_Pos     (0UL)      /*!< AGTCMA (Bit 0)                                        */
- #define R_AGT0_AGTCMA_AGTCMA_Msk     (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
-/* ========================================================  AGTCMB  ========================================================= */
- #define R_AGT0_AGTCMB_AGTCMB_Pos     (0UL)      /*!< AGTCMB (Bit 0)                                        */
- #define R_AGT0_AGTCMB_AGTCMB_Msk     (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
-/* =========================================================  AGTCR  ========================================================= */
- #define R_AGT0_AGTCR_TCMBF_Pos       (7UL)      /*!< TCMBF (Bit 7)                                         */
- #define R_AGT0_AGTCR_TCMBF_Msk       (0x80UL)   /*!< TCMBF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCMAF_Pos       (6UL)      /*!< TCMAF (Bit 6)                                         */
- #define R_AGT0_AGTCR_TCMAF_Msk       (0x40UL)   /*!< TCMAF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TUNDF_Pos       (5UL)      /*!< TUNDF (Bit 5)                                         */
- #define R_AGT0_AGTCR_TUNDF_Msk       (0x20UL)   /*!< TUNDF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TEDGF_Pos       (4UL)      /*!< TEDGF (Bit 4)                                         */
- #define R_AGT0_AGTCR_TEDGF_Msk       (0x10UL)   /*!< TEDGF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTOP_Pos       (2UL)      /*!< TSTOP (Bit 2)                                         */
- #define R_AGT0_AGTCR_TSTOP_Msk       (0x4UL)    /*!< TSTOP (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCSTF_Pos       (1UL)      /*!< TCSTF (Bit 1)                                         */
- #define R_AGT0_AGTCR_TCSTF_Msk       (0x2UL)    /*!< TCSTF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTART_Pos      (0UL)      /*!< TSTART (Bit 0)                                        */
- #define R_AGT0_AGTCR_TSTART_Msk      (0x1UL)    /*!< TSTART (Bitfield-Mask: 0x01)                          */
-/* ========================================================  AGTMR1  ========================================================= */
- #define R_AGT0_AGTMR1_TCK_Pos        (4UL)      /*!< TCK (Bit 4)                                           */
- #define R_AGT0_AGTMR1_TCK_Msk        (0x70UL)   /*!< TCK (Bitfield-Mask: 0x07)                             */
- #define R_AGT0_AGTMR1_TEDGPL_Pos     (3UL)      /*!< TEDGPL (Bit 3)                                        */
- #define R_AGT0_AGTMR1_TEDGPL_Msk     (0x8UL)    /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTMR1_TMOD_Pos       (0UL)      /*!< TMOD (Bit 0)                                          */
- #define R_AGT0_AGTMR1_TMOD_Msk       (0x7UL)    /*!< TMOD (Bitfield-Mask: 0x07)                            */
-/* ========================================================  AGTMR2  ========================================================= */
- #define R_AGT0_AGTMR2_LPM_Pos        (7UL)      /*!< LPM (Bit 7)                                           */
- #define R_AGT0_AGTMR2_LPM_Msk        (0x80UL)   /*!< LPM (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTMR2_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
- #define R_AGT0_AGTMR2_CKS_Msk        (0x7UL)    /*!< CKS (Bitfield-Mask: 0x07)                             */
-/* ========================================================  AGTIOC  ========================================================= */
- #define R_AGT0_AGTIOC_TIOGT_Pos      (6UL)      /*!< TIOGT (Bit 6)                                         */
- #define R_AGT0_AGTIOC_TIOGT_Msk      (0xc0UL)   /*!< TIOGT (Bitfield-Mask: 0x03)                           */
- #define R_AGT0_AGTIOC_TIPF_Pos       (4UL)      /*!< TIPF (Bit 4)                                          */
- #define R_AGT0_AGTIOC_TIPF_Msk       (0x30UL)   /*!< TIPF (Bitfield-Mask: 0x03)                            */
- #define R_AGT0_AGTIOC_TOE_Pos        (2UL)      /*!< TOE (Bit 2)                                           */
- #define R_AGT0_AGTIOC_TOE_Msk        (0x4UL)    /*!< TOE (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTIOC_TEDGSEL_Pos    (0UL)      /*!< TEDGSEL (Bit 0)                                       */
- #define R_AGT0_AGTIOC_TEDGSEL_Msk    (0x1UL)    /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
-/* ========================================================  AGTISR  ========================================================= */
- #define R_AGT0_AGTISR_EEPS_Pos       (2UL)      /*!< EEPS (Bit 2)                                          */
- #define R_AGT0_AGTISR_EEPS_Msk       (0x4UL)    /*!< EEPS (Bitfield-Mask: 0x01)                            */
-/* ========================================================  AGTCMSR  ======================================================== */
- #define R_AGT0_AGTCMSR_TOPOLB_Pos    (6UL)      /*!< TOPOLB (Bit 6)                                        */
- #define R_AGT0_AGTCMSR_TOPOLB_Msk    (0x40UL)   /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEB_Pos      (5UL)      /*!< TOEB (Bit 5)                                          */
- #define R_AGT0_AGTCMSR_TOEB_Msk      (0x20UL)   /*!< TOEB (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEB_Pos     (4UL)      /*!< TCMEB (Bit 4)                                         */
- #define R_AGT0_AGTCMSR_TCMEB_Msk     (0x10UL)   /*!< TCMEB (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCMSR_TOPOLA_Pos    (2UL)      /*!< TOPOLA (Bit 2)                                        */
- #define R_AGT0_AGTCMSR_TOPOLA_Msk    (0x4UL)    /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEA_Pos      (1UL)      /*!< TOEA (Bit 1)                                          */
- #define R_AGT0_AGTCMSR_TOEA_Msk      (0x2UL)    /*!< TOEA (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEA_Pos     (0UL)      /*!< TCMEA (Bit 0)                                         */
- #define R_AGT0_AGTCMSR_TCMEA_Msk     (0x1UL)    /*!< TCMEA (Bitfield-Mask: 0x01)                           */
-/* =======================================================  AGTIOSEL  ======================================================== */
- #define R_AGT0_AGTIOSEL_TIES_Pos     (4UL)      /*!< TIES (Bit 4)                                          */
- #define R_AGT0_AGTIOSEL_TIES_Msk     (0x10UL)   /*!< TIES (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTIOSEL_SEL_Pos      (0UL)      /*!< SEL (Bit 0)                                           */
- #define R_AGT0_AGTIOSEL_SEL_Msk      (0x3UL)    /*!< SEL (Bitfield-Mask: 0x03)                             */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -22561,10 +23077,22 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
 /* =========================================================  GTCR  ========================================================== */
+ #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
+ #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTCR_TPCS_Pos              (24UL)         /*!< TPCS (Bit 24)                                         */
  #define R_GPT0_GTCR_TPCS_Msk              (0x7000000UL)  /*!< TPCS (Bitfield-Mask: 0x07)                            */
  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
- #define R_GPT0_GTCR_MD_Msk                (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
+ #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
+ #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
+ #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
+ #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
 /* =======================================================  GTUDDTYC  ======================================================== */
@@ -22622,6 +23150,8 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
 /* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
+ #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
@@ -22630,8 +23160,16 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
- #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
- #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
+ #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
+ #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
+ #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
 /* =========================================================  GTST  ========================================================== */
  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
@@ -22688,6 +23226,8 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
+ #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
@@ -22777,6 +23317,67 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
 /* ========================================================  GTSOTR  ========================================================= */
  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
 /* ========================================================  GTICLF  ========================================================= */
  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
@@ -22819,14 +23420,113 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
+ #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
+ #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTBER2  ========================================================= */
+ #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
+ #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
+ #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
+ #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
+ #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
+ #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
+ #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
+ #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
+ #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
+ #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
+ #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
+ #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
+ #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
+ #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
+ #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
+ #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
+ #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
+ #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
+ #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
+ #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTOLBR  ========================================================= */
+ #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
+ #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
+ #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
+ #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  GTICCR  ========================================================= */
+ #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
+ #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
+ #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
+ #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
+ #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
+ #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
+ #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
+ #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
+ #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
+ #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
+ #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
+ #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
+ #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
+ #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
+ #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
+ #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
+ #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
+ #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
+ #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
+ #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
+ #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_ODC                                         ================ */
@@ -25804,6 +26504,9 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
 /* ======================================================  CECCKDIVCR  ======================================================= */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  I3CCKDIVCR  ======================================================= */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
 /* ======================================================  IICCKDIVCR  ======================================================= */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
@@ -27130,6 +27833,10 @@ typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure
  #define R_USB_HS0_DPUSRCR_FIXPHY_Pos          (0UL)        /*!< FIXPHY (Bit 0)                                        */
  #define R_USB_HS0_DPUSRCR_FIXPHY_Msk          (0x1UL)      /*!< FIXPHY (Bitfield-Mask: 0x01)                          */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
 /** @} */ /* End of group PosMask_peripherals */
 
  #ifdef __cplusplus
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h
index 6a90deaa6..44f3bdfaf 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h
@@ -799,7 +799,8 @@ typedef struct
             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
             uint8_t            : 1;
             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
-            uint8_t            : 2;
+            uint8_t            : 1;
+            __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
         } RTCCR_b;
     };
     __IM uint8_t RESERVED;
@@ -1179,6 +1180,213 @@ typedef struct
     };
 } R_USB_HS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
 
+/**
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
+            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
+            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
+            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
+            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
+            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
+        } AGTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
+            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
+            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
+            uint8_t              : 1;
+        } AGTMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+                                        *   ratio                                                                     */
+            uint8_t           : 4;
+            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
+        } AGTMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+                                        *   mode.                                                                     */
+            uint8_t             : 1;
+            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
+            uint8_t             : 1;
+            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
+            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
+        } AGTIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
+            uint8_t            : 5;
+        } AGTISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
+
+        struct
+        {
+            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
+            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
+            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
+            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
+            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
+            uint8_t              : 1;
+        } AGTCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_b;
+    };
+} R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
+
+        struct
+        {
+            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IM uint16_t                 RESERVED;
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
+} R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
+
+        struct
+        {
+            __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
+} R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_clusters */
 
 /* =========================================================================================================================== */
@@ -1471,16 +1679,17 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
 
     union
     {
-        __IM uint16_t ADDR[28];        /*!< (@ 0x00000020) A/D Data Register                                          */
+        __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
 
         struct
         {
             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
                                         *   storing the result of A/D conversion.                                     */
-        } ADDR_b[28];
+        } ADDR_b[29];
     };
-    __IM uint32_t RESERVED1[2];
-    __IM uint16_t RESERVED2;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+    __IM uint16_t RESERVED3;
 
     union
     {
@@ -1673,7 +1882,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint16_t                : 3;
         } ADSWTSTR2_b;
     };
-    __IM uint16_t RESERVED3;
+    __IM uint16_t RESERVED4;
 
     union
     {
@@ -1735,7 +1944,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 6;
         } ADACSR_b;
     };
-    __IM uint8_t RESERVED4;
+    __IM uint8_t RESERVED5;
 
     union
     {
@@ -1805,7 +2014,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
         } ADSER_b;
     };
-    __IM uint8_t RESERVED5;
+    __IM uint8_t RESERVED6;
 
     union
     {
@@ -1821,7 +2030,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
         } ADHVREFCNT_b;
     };
-    __IM uint8_t RESERVED6;
+    __IM uint8_t RESERVED7;
 
     union
     {
@@ -1839,8 +2048,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t              : 2;
         } ADWINMON_b;
     };
-    __IM uint8_t  RESERVED7;
-    __IM uint16_t RESERVED8;
+    __IM uint8_t  RESERVED8;
+    __IM uint16_t RESERVED9;
 
     union
     {
@@ -2016,7 +2225,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 6;
         } ADCMPSER_b;
     };
-    __IM uint8_t RESERVED9;
+    __IM uint8_t RESERVED10;
 
     union
     {
@@ -2031,7 +2240,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
         } ADCMPBNSR_b;
     };
-    __IM uint8_t RESERVED10;
+    __IM uint8_t RESERVED11;
 
     union
     {
@@ -2070,8 +2279,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 7;
         } ADCMPBSR_b;
     };
-    __IM uint8_t  RESERVED11;
-    __IM uint16_t RESERVED12;
+    __IM uint8_t  RESERVED12;
+    __IM uint16_t RESERVED13;
 
     union
     {
@@ -2275,7 +2484,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 7;
         } ADBUFEN_b;
     };
-    __IM uint8_t RESERVED13;
+    __IM uint8_t RESERVED14;
 
     union
     {
@@ -2289,9 +2498,9 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 3;
         } ADBUFPTR_b;
     };
-    __IM uint8_t  RESERVED14;
-    __IM uint32_t RESERVED15[2];
-    __IM uint8_t  RESERVED16;
+    __IM uint8_t  RESERVED15;
+    __IM uint32_t RESERVED16[2];
+    __IM uint8_t  RESERVED17;
 
     union
     {
@@ -2358,7 +2567,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
         } ADCALEXE_b;
     };
-    __IM uint8_t RESERVED17;
+    __IM uint8_t RESERVED18;
 
     union
     {
@@ -2375,8 +2584,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
         } VREFAMPCNT_b;
     };
-    __IM uint8_t  RESERVED18;
-    __IM uint16_t RESERVED19;
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -2398,8 +2607,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 6;
         } ADRST_b;
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint32_t RESERVED21[41];
+    __IM uint8_t  RESERVED21;
+    __IM uint32_t RESERVED22[41];
 
     union
     {
@@ -2457,7 +2666,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
         } ADPGAGS0_b;
     };
-    __IM uint32_t RESERVED22[3];
+    __IM uint32_t RESERVED23[3];
 
     union
     {
@@ -2484,7 +2693,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
         } ADPGADCR0_b;
     };
-    __IM uint16_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -2513,8 +2722,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 7;
         } ADPGADBS1_b;
     };
-    __IM uint16_t RESERVED24;
-    __IM uint32_t RESERVED25[10];
+    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED26[10];
 
     union
     {
@@ -2678,63 +2887,63 @@ typedef struct                         /*!< (@ 0x400E0000) R_PSCU Structure
 
     union
     {
-        __IM uint32_t CFSAMONA;        /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
+        __IOM uint32_t CFSAMONA;       /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
                                         *                  A                                                          */
 
         struct
         {
-            uint32_t           : 15;
-            __IM uint32_t CFS2 : 9;    /*!< [23..15] Code Flash Secure area 2                                         */
-            uint32_t           : 8;
+            uint32_t            : 15;
+            __IOM uint32_t CFS2 : 9;   /*!< [23..15] Code Flash Secure area 2                                         */
+            uint32_t            : 8;
         } CFSAMONA_b;
     };
 
     union
     {
-        __IM uint32_t CFSAMONB;        /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
+        __IOM uint32_t CFSAMONB;       /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
                                         *                  B                                                          */
 
         struct
         {
-            uint32_t           : 10;
-            __IM uint32_t CFS1 : 14;   /*!< [23..10] Code Flash Secure area 1                                         */
-            uint32_t           : 8;
+            uint32_t            : 10;
+            __IOM uint32_t CFS1 : 14;  /*!< [23..10] Code Flash Secure area 1                                         */
+            uint32_t            : 8;
         } CFSAMONB_b;
     };
 
     union
     {
-        __IM uint32_t DFSAMON;         /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register           */
+        __IOM uint32_t DFSAMON;        /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register           */
 
         struct
         {
-            uint32_t          : 10;
-            __IM uint32_t DFS : 6;     /*!< [15..10] Data flash Secure area                                           */
-            uint32_t          : 16;
+            uint32_t           : 10;
+            __IOM uint32_t DFS : 6;    /*!< [15..10] Data flash Secure area                                           */
+            uint32_t           : 16;
         } DFSAMON_b;
     };
 
     union
     {
-        __IM uint32_t SSAMONA;         /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A               */
+        __IOM uint32_t SSAMONA;        /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A               */
 
         struct
         {
-            uint32_t          : 13;
-            __IM uint32_t SS2 : 8;     /*!< [20..13] SRAM Secure area 2                                               */
-            uint32_t          : 11;
+            uint32_t           : 13;
+            __IOM uint32_t SS2 : 8;    /*!< [20..13] SRAM Secure area 2                                               */
+            uint32_t           : 11;
         } SSAMONA_b;
     };
 
     union
     {
-        __IM uint32_t SSAMONB;         /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B               */
+        __IOM uint32_t SSAMONB;        /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B               */
 
         struct
         {
-            uint32_t          : 10;
-            __IM uint32_t SS1 : 11;    /*!< [20..10] SRAM secure area 1                                               */
-            uint32_t          : 11;
+            uint32_t           : 10;
+            __IOM uint32_t SS1 : 11;   /*!< [20..10] SRAM secure area 1                                               */
+            uint32_t           : 11;
         } SSAMONB_b;
     };
 
@@ -2750,156 +2959,6 @@ typedef struct                         /*!< (@ 0x400E0000) R_PSCU Structure
     };
 } R_PSCU_Type;                         /*!< Size = 48 (0x30)                                                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Asynchronous General Purpose Timer (R_AGT0)
- */
-
-typedef struct                         /*!< (@ 0x400E8000) R_AGT0 Structure                                           */
-{
-    union
-    {
-        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
-
-        struct
-        {
-            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written
-                                        *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
-                                        *   is forcibly stopped and set to FFFFH.                                     */
-        } AGT_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCRn register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMA_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCR register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMB_b;
-    };
-    __IM uint16_t RESERVED;
-
-    union
-    {
-        __IOM uint8_t AGTCR;           /*!< (@ 0x00000008) AGT Control Register                                       */
-
-        struct
-        {
-            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
-            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
-            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
-            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
-            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
-            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
-        } AGTCR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000009) AGT Mode Register 1                                        */
-
-        struct
-        {
-            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
-            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
-            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
-            uint8_t              : 1;
-        } AGTMR1_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000A) AGT Mode Register 2                                        */
-
-        struct
-        {
-            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
-                                        *   ratio                                                                     */
-            uint8_t           : 4;
-            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
-        } AGTMR2_b;
-    };
-    __IM uint8_t RESERVED1;
-
-    union
-    {
-        __IOM uint8_t AGTIOC;          /*!< (@ 0x0000000C) AGT I/O Control Register                                   */
-
-        struct
-        {
-            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
-                                        *   mode.                                                                     */
-            uint8_t             : 1;
-            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
-            uint8_t             : 1;
-            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
-            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
-        } AGTIOC_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTISR;          /*!< (@ 0x0000000D) AGT Event Pin Select Register                              */
-
-        struct
-        {
-            uint8_t            : 2;
-            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
-            uint8_t            : 5;
-        } AGTISR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTCMSR;         /*!< (@ 0x0000000E) AGT Compare Match Function Select Register                 */
-
-        struct
-        {
-            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
-            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
-            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
-            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
-            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
-            uint8_t              : 1;
-        } AGTCMSR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x0000000F) AGT Pin Select Register                                    */
-
-        struct
-        {
-            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
-            uint8_t            : 2;
-            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
-            uint8_t            : 3;
-        } AGTIOSEL_b;
-    };
-} R_AGT0_Type;                         /*!< Size = 16 (0x10)                                                          */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -5736,40 +5795,93 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            uint32_t : 18;
         } GTSTR_b;
     };
 
@@ -5821,7 +5933,60 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
                                          *   1 means counter stop.                                                     */
-            uint32_t : 18;
+            __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
         } GTSTP_b;
     };
 
@@ -5845,7 +6010,24 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
-            uint32_t             : 18;
+            __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
         } GTCLR_b;
     };
 
@@ -6166,16 +6348,23 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+        __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
 
         struct
         {
-            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
-            uint32_t            : 15;
-            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
-            uint32_t            : 4;
-            __IOM uint32_t TPCS : 4;   /*!< [26..23] Timer Prescaler Select                                           */
-            uint32_t            : 5;
+            __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
+            uint32_t               : 7;
+            __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
+            __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
+            __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
+            __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
+            uint32_t               : 2;
+            __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
+            __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
+            uint32_t               : 3;
+            __IOM uint32_t TPCS    : 4; /*!< [26..23] Timer Prescaler Select                                           */
+            __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
+            uint32_t               : 3;
         } GTCR_b;
     };
 
@@ -6246,13 +6435,36 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
         struct
         {
-            uint32_t               : 24;
-            __IOM uint32_t GRP     : 2; /*!< [25..24] Output Disable Source Select                                     */
+            uint32_t            : 8;
+            __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
+            __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            uint32_t               : 4;
+            __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
             uint32_t               : 2;
-            __IOM uint32_t GRPDTE  : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
-            __IOM uint32_t GRPABH  : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable               */
-            __IOM uint32_t GRPABL  : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
-            __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
+            __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
+            __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
         } GTINTAD_b;
     };
 
@@ -6295,32 +6507,36 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTBER;          /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
 
         struct
         {
-            __IOM uint32_t BD0    : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
-            __IOM uint32_t BD1    : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
-            __IOM uint32_t BD2    : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
-            __IOM uint32_t BD3    : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
-            uint32_t              : 12;
-            __IOM uint32_t CCRA   : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
-            __IOM uint32_t CCRB   : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
-            __IOM uint32_t PR     : 2; /*!< [21..20] GTPR Buffer Operation                                            */
-            __OM uint32_t  CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
-                                        *   is read as 0.                                                             */
+            __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
+            __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+                                         *   is read as 0.                                                             */
             uint32_t             : 1;
-            __IOM uint32_t ADTTA : 2;  /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDA : 1;  /*!< [26..26] GTADTRA Double Buffer Operation                                  */
+            __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
             uint32_t             : 1;
-            __IOM uint32_t ADTTB : 2;  /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDB : 1;  /*!< [30..30] GTADTRB Double Buffer Operation                                  */
+            __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
             uint32_t             : 1;
         } GTBER_b;
     };
@@ -6544,7 +6760,126 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             uint32_t            : 31;
         } GTSOTR_b;
     };
-    __IM uint32_t RESERVED[5];
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
 
     union
     {
@@ -6578,7 +6913,7 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             uint32_t            : 4;
         } GTPC_b;
     };
-    __IM uint32_t RESERVED1[4];
+    __IM uint32_t RESERVED[4];
 
     union
     {
@@ -6620,17 +6955,137 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
         {
             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 4;
             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
-            uint32_t             : 7;
+            __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
+            uint32_t             : 6;
             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
-            uint32_t             : 7;
+            __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
+            uint32_t             : 6;
         } GTSECR_b;
     };
-} R_GPT0_Type;                         /*!< Size = 216 (0xd8)                                                         */
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
+            __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
+                                        *   Disable                                                                   */
+            uint32_t             : 2;
+            __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t             : 1;
+            __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
+                                        *   Transfer Disable                                                          */
+            uint32_t             : 2;
+            __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
+            __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
+            __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
+            __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
+            uint32_t             : 2;
+        } GTBER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
+
+        struct
+        {
+            __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
+            uint32_t              : 11;
+            __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
+            uint32_t              : 11;
+        } GTOLBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
+                                        *                  Capture Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
+            __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
+                                        *   Other Channel GTCCRb Input Capture Source Enable                          */
+            __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
+        } GTICCR_b;
+    };
+} R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_OPS                                         ================ */
@@ -11215,8 +11670,18 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } IICCKDIVCR_b;
         };
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint16_t RESERVED21;
+
+    union
+    {
+        __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
+
+        struct
+        {
+            __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
+            uint8_t                : 5;
+        } I3CCKDIVCR_b;
+    };
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -11343,8 +11808,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
         } I3CCKCR_b;
     };
-    __IM uint16_t RESERVED22;
-    __IM uint32_t RESERVED23[3];
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
 
     union
     {
@@ -11358,8 +11823,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                 : 29;
         } SNZREQCR1_b;
     };
-    __IM uint32_t RESERVED24;
-    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -11374,7 +11839,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
         } SNZCR_b;
     };
-    __IM uint8_t RESERVED26;
+    __IM uint8_t RESERVED25;
 
     union
     {
@@ -11404,7 +11869,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } SNZEDCR1_b;
     };
-    __IM uint16_t RESERVED27;
+    __IM uint16_t RESERVED26;
 
     union
     {
@@ -11447,7 +11912,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 1;
         } SNZREQCR_b;
     };
-    __IM uint16_t RESERVED28;
+    __IM uint16_t RESERVED27;
 
     union
     {
@@ -11485,7 +11950,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 3;
         } OPCCR_b;
     };
-    __IM uint8_t RESERVED29;
+    __IM uint8_t RESERVED28;
 
     union
     {
@@ -11497,7 +11962,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } MOSCWTCR_b;
     };
-    __IM uint8_t RESERVED30[2];
+    __IM uint8_t RESERVED29[2];
 
     union
     {
@@ -11510,7 +11975,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t : 5;
         } HOCOWTCR_b;
     };
-    __IM uint16_t RESERVED31[2];
+    __IM uint16_t RESERVED30[2];
 
     union
     {
@@ -11524,8 +11989,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 3;
         } SOPCCR_b;
     };
-    __IM uint8_t  RESERVED32;
-    __IM uint32_t RESERVED33[5];
+    __IM uint8_t  RESERVED31;
+    __IM uint32_t RESERVED32[5];
 
     union
     {
@@ -11559,8 +12024,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
         } RSTSR1_b;
     };
-    __IM uint16_t RESERVED34;
-    __IM uint32_t RESERVED35[3];
+    __IM uint16_t RESERVED33;
+    __IM uint32_t RESERVED34[3];
 
     union
     {
@@ -11586,8 +12051,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
         } SDADCCKCR_b;
     };
-    __IM uint16_t RESERVED36;
-    __IM uint32_t RESERVED37[3];
+    __IM uint16_t RESERVED35;
+    __IM uint32_t RESERVED36[3];
 
     union
     {
@@ -11642,7 +12107,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t          : 6;
         } LVD2SR_b;
     };
-    __IM uint32_t RESERVED38[183];
+    __IM uint32_t RESERVED37[183];
 
     union
     {
@@ -11670,7 +12135,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 14;
         } CGFSAR_b;
     };
-    __IM uint32_t RESERVED39;
+    __IM uint32_t RESERVED38;
 
     union
     {
@@ -11739,7 +12204,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 8;
         } BBFSAR_b;
     };
-    __IM uint32_t RESERVED40[3];
+    __IM uint32_t RESERVED39[3];
 
     union
     {
@@ -11801,8 +12266,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 4;
         } DPFSAR_b;
     };
-    __IM uint32_t RESERVED41[6];
-    __IM uint16_t RESERVED42;
+    __IM uint32_t RESERVED40[6];
+    __IM uint16_t RESERVED41;
 
     union
     {
@@ -12020,7 +12485,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 3;
         } DPSIEGR2_b;
     };
-    __IM uint8_t RESERVED43;
+    __IM uint8_t RESERVED42;
 
     union
     {
@@ -12078,7 +12543,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } RSTSR2_b;
     };
-    __IM uint8_t RESERVED44;
+    __IM uint8_t RESERVED43;
 
     union
     {
@@ -12095,7 +12560,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                           *   Enable                                                                    */
         } MOMCR_b;
     };
-    __IM uint16_t RESERVED45;
+    __IM uint16_t RESERVED44;
 
     union
     {
@@ -12165,7 +12630,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } LVD2CMPCR_b;
         };
     };
-    __IM uint8_t RESERVED46;
+    __IM uint8_t RESERVED45;
 
     union
     {
@@ -12198,7 +12663,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
         } LVD2CR0_b;
     };
-    __IM uint8_t RESERVED47;
+    __IM uint8_t RESERVED46;
 
     union
     {
@@ -12233,7 +12698,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 7;
         } VBTCR1_b;
     };
-    __IM uint32_t RESERVED48[8];
+    __IM uint32_t RESERVED47[8];
 
     union
     {
@@ -12276,7 +12741,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 6;
         } VCCSEL_b;
     };
-    __IM uint16_t RESERVED49;
+    __IM uint16_t RESERVED48;
 
     union
     {
@@ -12288,9 +12753,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } PL2LDOSCR_b;
     };
-    __IM uint8_t  RESERVED50;
-    __IM uint16_t RESERVED51;
-    __IM uint32_t RESERVED52[14];
+    __IM uint8_t  RESERVED49;
+    __IM uint16_t RESERVED50;
+    __IM uint32_t RESERVED51[14];
 
     union
     {
@@ -12313,8 +12778,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 6;
         } SOMCR_b;
     };
-    __IM uint16_t RESERVED53;
-    __IM uint32_t RESERVED54[3];
+    __IM uint16_t RESERVED52;
+    __IM uint32_t RESERVED53[3];
 
     union
     {
@@ -12326,7 +12791,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 7;
         } LOCOCR_b;
     };
-    __IM uint8_t RESERVED55;
+    __IM uint8_t RESERVED54;
 
     union
     {
@@ -12341,8 +12806,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                          *   trimming bits                                                             */
         } LOCOUTCR_b;
     };
-    __IM uint8_t  RESERVED56;
-    __IM uint32_t RESERVED57[7];
+    __IM uint8_t  RESERVED55;
+    __IM uint32_t RESERVED56[7];
 
     union
     {
@@ -12381,7 +12846,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 7;
         } VBTCMPCR_b;
     };
-    __IM uint8_t RESERVED58;
+    __IM uint8_t RESERVED57;
 
     union
     {
@@ -12395,7 +12860,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                  : 6;
         } VBTLVDICR_b;
     };
-    __IM uint8_t RESERVED59;
+    __IM uint8_t RESERVED58;
 
     union
     {
@@ -12407,7 +12872,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } VBTWCTLR_b;
     };
-    __IM uint8_t RESERVED60;
+    __IM uint8_t RESERVED59;
 
     union
     {
@@ -12542,9 +13007,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } VBTBER_b;
     };
-    __IM uint8_t  RESERVED61;
-    __IM uint16_t RESERVED62;
-    __IM uint32_t RESERVED63[15];
+    __IM uint8_t  RESERVED60;
+    __IM uint16_t RESERVED61;
+    __IM uint32_t RESERVED62[15];
 
     union
     {
@@ -15496,6 +15961,23 @@ typedef struct                         /*!< (@ 0x40111000) R_USB_HS0 Structure
     };
 } R_USB_HS0_Type;                        /*!< Size = 364 (0x16c)                                                        */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
+ */
+
+typedef struct                          /*!< (@ 0x400E8000) R_AGTX0 Structure                                          */
+{
+    union
+    {
+        __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
+        __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
+    };
+} R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
 /* =========================================================================================================================== */
 /* ================                                          R_FLAD                                           ================ */
 /* =========================================================================================================================== */
@@ -15532,12 +16014,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_ADC0_BASE            0x40170000UL
  #define R_ADC1_BASE            0x40170200UL
  #define R_PSCU_BASE            0x400E0000UL
- #define R_AGT0_BASE            0x400E8000UL
- #define R_AGT1_BASE            0x400E8100UL
- #define R_AGT2_BASE            0x400E8200UL
- #define R_AGT3_BASE            0x400E8300UL
- #define R_AGT4_BASE            0x400E8400UL
- #define R_AGT5_BASE            0x400E8500UL
  #define R_BUS_BASE             0x40003000UL
  #define R_CAC_BASE             0x40083600UL
  #define R_CAN0_BASE            0x400A8000UL
@@ -15636,6 +16112,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_CPSCU_BASE           0x40008000UL
  #define R_OSPI_BASE            0x400A6000UL
  #define R_USB_HS0_BASE         0x40111000UL
+ #define R_AGTX0_BASE           0x400E8000UL
+ #define R_AGTX1_BASE           0x400E8100UL
+ #define R_AGTX2_BASE           0x400E8200UL
+ #define R_AGTX3_BASE           0x400E8300UL
+ #define R_AGTX4_BASE           0x400E8400UL
+ #define R_AGTX5_BASE           0x400E8500UL
+ #define R_AGTX6_BASE           0x400E8600UL
+ #define R_AGTX7_BASE           0x400E8700UL
+ #define R_AGTX8_BASE           0x400E8800UL
+ #define R_AGTX9_BASE           0x400E8900UL
  #define R_FLAD_BASE            0x407FC000UL
 
 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
@@ -15651,12 +16137,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_ADC0            ((R_ADC0_Type *) R_ADC0_BASE)
  #define R_ADC1            ((R_ADC0_Type *) R_ADC1_BASE)
  #define R_PSCU            ((R_PSCU_Type *) R_PSCU_BASE)
- #define R_AGT0            ((R_AGT0_Type *) R_AGT0_BASE)
- #define R_AGT1            ((R_AGT0_Type *) R_AGT1_BASE)
- #define R_AGT2            ((R_AGT0_Type *) R_AGT2_BASE)
- #define R_AGT3            ((R_AGT0_Type *) R_AGT3_BASE)
- #define R_AGT4            ((R_AGT0_Type *) R_AGT4_BASE)
- #define R_AGT5            ((R_AGT0_Type *) R_AGT5_BASE)
 
 /* #define R_BUS                       ((R_BUS_Type*)             R_BUS_BASE) */
  #define R_CAC             ((R_CAC_Type *) R_CAC_BASE)
@@ -15756,6 +16236,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_CPSCU           ((R_CPSCU_Type *) R_CPSCU_BASE)
  #define R_OSPI            ((R_OSPI_Type *) R_OSPI_BASE)
  #define R_USB_HS0         ((R_USB_HS0_Type *) R_USB_HS0_BASE)
+ #define R_AGTX0           ((R_AGTX0_Type *) R_AGTX0_BASE)
+ #define R_AGTX1           ((R_AGTX0_Type *) R_AGTX1_BASE)
+ #define R_AGTX2           ((R_AGTX0_Type *) R_AGTX2_BASE)
+ #define R_AGTX3           ((R_AGTX0_Type *) R_AGTX3_BASE)
+ #define R_AGTX4           ((R_AGTX0_Type *) R_AGTX4_BASE)
+ #define R_AGTX5           ((R_AGTX0_Type *) R_AGTX5_BASE)
+ #define R_AGTX6           ((R_AGTX0_Type *) R_AGTX6_BASE)
+ #define R_AGTX7           ((R_AGTX0_Type *) R_AGTX7_BASE)
+ #define R_AGTX8           ((R_AGTX0_Type *) R_AGTX8_BASE)
+ #define R_AGTX9           ((R_AGTX0_Type *) R_AGTX9_BASE)
  #define R_FLAD            ((R_FLAD_Type *) R_FLAD_BASE)
 
 /** @} */ /* End of group Device_Peripheral_declaration */
@@ -16113,6 +16603,8 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* =========================================================================================================================== */
 
 /* =========================================================  RTCCR  ========================================================= */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
@@ -16273,6 +16765,101 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
  #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
 
+/* =========================================================================================================================== */
+/* ================                                           CTRL                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  AGTCR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AGTMR1  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
+/* ========================================================  AGTMR2  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
+/* =====================================================  AGTIOSEL_ALT  ====================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+/* ========================================================  AGTIOC  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AGTISR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AGTCMSR  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
+/* =======================================================  AGTIOSEL  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT16                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT32                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
+
 /** @} */ /* End of group PosMask_clusters */
 
 /* =========================================================================================================================== */
@@ -16938,77 +17525,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_PSCU_DLMMON_DLMMON_Pos    (0UL)          /*!< DLMMON (Bit 0)                                        */
  #define R_PSCU_DLMMON_DLMMON_Msk    (0xfUL)        /*!< DLMMON (Bitfield-Mask: 0x0f)                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/* ==========================================================  AGT  ========================================================== */
- #define R_AGT0_AGT_AGT_Pos           (0UL)      /*!< AGT (Bit 0)                                           */
- #define R_AGT0_AGT_AGT_Msk           (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
-/* ========================================================  AGTCMA  ========================================================= */
- #define R_AGT0_AGTCMA_AGTCMA_Pos     (0UL)      /*!< AGTCMA (Bit 0)                                        */
- #define R_AGT0_AGTCMA_AGTCMA_Msk     (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
-/* ========================================================  AGTCMB  ========================================================= */
- #define R_AGT0_AGTCMB_AGTCMB_Pos     (0UL)      /*!< AGTCMB (Bit 0)                                        */
- #define R_AGT0_AGTCMB_AGTCMB_Msk     (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
-/* =========================================================  AGTCR  ========================================================= */
- #define R_AGT0_AGTCR_TCMBF_Pos       (7UL)      /*!< TCMBF (Bit 7)                                         */
- #define R_AGT0_AGTCR_TCMBF_Msk       (0x80UL)   /*!< TCMBF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCMAF_Pos       (6UL)      /*!< TCMAF (Bit 6)                                         */
- #define R_AGT0_AGTCR_TCMAF_Msk       (0x40UL)   /*!< TCMAF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TUNDF_Pos       (5UL)      /*!< TUNDF (Bit 5)                                         */
- #define R_AGT0_AGTCR_TUNDF_Msk       (0x20UL)   /*!< TUNDF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TEDGF_Pos       (4UL)      /*!< TEDGF (Bit 4)                                         */
- #define R_AGT0_AGTCR_TEDGF_Msk       (0x10UL)   /*!< TEDGF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTOP_Pos       (2UL)      /*!< TSTOP (Bit 2)                                         */
- #define R_AGT0_AGTCR_TSTOP_Msk       (0x4UL)    /*!< TSTOP (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCSTF_Pos       (1UL)      /*!< TCSTF (Bit 1)                                         */
- #define R_AGT0_AGTCR_TCSTF_Msk       (0x2UL)    /*!< TCSTF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTART_Pos      (0UL)      /*!< TSTART (Bit 0)                                        */
- #define R_AGT0_AGTCR_TSTART_Msk      (0x1UL)    /*!< TSTART (Bitfield-Mask: 0x01)                          */
-/* ========================================================  AGTMR1  ========================================================= */
- #define R_AGT0_AGTMR1_TCK_Pos        (4UL)      /*!< TCK (Bit 4)                                           */
- #define R_AGT0_AGTMR1_TCK_Msk        (0x70UL)   /*!< TCK (Bitfield-Mask: 0x07)                             */
- #define R_AGT0_AGTMR1_TEDGPL_Pos     (3UL)      /*!< TEDGPL (Bit 3)                                        */
- #define R_AGT0_AGTMR1_TEDGPL_Msk     (0x8UL)    /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTMR1_TMOD_Pos       (0UL)      /*!< TMOD (Bit 0)                                          */
- #define R_AGT0_AGTMR1_TMOD_Msk       (0x7UL)    /*!< TMOD (Bitfield-Mask: 0x07)                            */
-/* ========================================================  AGTMR2  ========================================================= */
- #define R_AGT0_AGTMR2_LPM_Pos        (7UL)      /*!< LPM (Bit 7)                                           */
- #define R_AGT0_AGTMR2_LPM_Msk        (0x80UL)   /*!< LPM (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTMR2_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
- #define R_AGT0_AGTMR2_CKS_Msk        (0x7UL)    /*!< CKS (Bitfield-Mask: 0x07)                             */
-/* ========================================================  AGTIOC  ========================================================= */
- #define R_AGT0_AGTIOC_TIOGT_Pos      (6UL)      /*!< TIOGT (Bit 6)                                         */
- #define R_AGT0_AGTIOC_TIOGT_Msk      (0xc0UL)   /*!< TIOGT (Bitfield-Mask: 0x03)                           */
- #define R_AGT0_AGTIOC_TIPF_Pos       (4UL)      /*!< TIPF (Bit 4)                                          */
- #define R_AGT0_AGTIOC_TIPF_Msk       (0x30UL)   /*!< TIPF (Bitfield-Mask: 0x03)                            */
- #define R_AGT0_AGTIOC_TOE_Pos        (2UL)      /*!< TOE (Bit 2)                                           */
- #define R_AGT0_AGTIOC_TOE_Msk        (0x4UL)    /*!< TOE (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTIOC_TEDGSEL_Pos    (0UL)      /*!< TEDGSEL (Bit 0)                                       */
- #define R_AGT0_AGTIOC_TEDGSEL_Msk    (0x1UL)    /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
-/* ========================================================  AGTISR  ========================================================= */
- #define R_AGT0_AGTISR_EEPS_Pos       (2UL)      /*!< EEPS (Bit 2)                                          */
- #define R_AGT0_AGTISR_EEPS_Msk       (0x4UL)    /*!< EEPS (Bitfield-Mask: 0x01)                            */
-/* ========================================================  AGTCMSR  ======================================================== */
- #define R_AGT0_AGTCMSR_TOPOLB_Pos    (6UL)      /*!< TOPOLB (Bit 6)                                        */
- #define R_AGT0_AGTCMSR_TOPOLB_Msk    (0x40UL)   /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEB_Pos      (5UL)      /*!< TOEB (Bit 5)                                          */
- #define R_AGT0_AGTCMSR_TOEB_Msk      (0x20UL)   /*!< TOEB (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEB_Pos     (4UL)      /*!< TCMEB (Bit 4)                                         */
- #define R_AGT0_AGTCMSR_TCMEB_Msk     (0x10UL)   /*!< TCMEB (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCMSR_TOPOLA_Pos    (2UL)      /*!< TOPOLA (Bit 2)                                        */
- #define R_AGT0_AGTCMSR_TOPOLA_Msk    (0x4UL)    /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEA_Pos      (1UL)      /*!< TOEA (Bit 1)                                          */
- #define R_AGT0_AGTCMSR_TOEA_Msk      (0x2UL)    /*!< TOEA (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEA_Pos     (0UL)      /*!< TCMEA (Bit 0)                                         */
- #define R_AGT0_AGTCMSR_TCMEA_Msk     (0x1UL)    /*!< TCMEA (Bitfield-Mask: 0x01)                           */
-/* =======================================================  AGTIOSEL  ======================================================== */
- #define R_AGT0_AGTIOSEL_TIES_Pos     (4UL)      /*!< TIES (Bit 4)                                          */
- #define R_AGT0_AGTIOSEL_TIES_Msk     (0x10UL)   /*!< TIES (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTIOSEL_SEL_Pos      (0UL)      /*!< SEL (Bit 0)                                           */
- #define R_AGT0_AGTIOSEL_SEL_Msk      (0x3UL)    /*!< SEL (Bitfield-Mask: 0x03)                             */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -18530,10 +19046,22 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
 /* =========================================================  GTCR  ========================================================== */
+ #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
+ #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTCR_TPCS_Pos              (23UL)         /*!< TPCS (Bit 23)                                         */
  #define R_GPT0_GTCR_TPCS_Msk              (0x7800000UL)  /*!< TPCS (Bitfield-Mask: 0x0f)                            */
  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
- #define R_GPT0_GTCR_MD_Msk                (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
+ #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
+ #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
+ #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
+ #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
 /* =======================================================  GTUDDTYC  ======================================================== */
@@ -18591,6 +19119,8 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
 /* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
+ #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
@@ -18599,8 +19129,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
- #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
- #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
+ #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
+ #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
+ #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
 /* =========================================================  GTST  ========================================================== */
  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
@@ -18657,6 +19195,8 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
+ #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
@@ -18746,6 +19286,67 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* ========================================================  GTSOTR  ========================================================= */
  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
 /* ========================================================  GTICLF  ========================================================= */
  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
@@ -18788,14 +19389,113 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
+ #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
+ #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTBER2  ========================================================= */
+ #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
+ #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
+ #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
+ #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
+ #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
+ #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
+ #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
+ #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
+ #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
+ #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
+ #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
+ #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
+ #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
+ #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
+ #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
+ #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
+ #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
+ #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
+ #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
+ #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTOLBR  ========================================================= */
+ #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
+ #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
+ #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
+ #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  GTICCR  ========================================================= */
+ #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
+ #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
+ #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
+ #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
+ #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
+ #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
+ #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
+ #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
+ #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
+ #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
+ #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
+ #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
+ #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
+ #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
+ #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
+ #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
+ #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
+ #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
+ #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
+ #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
+ #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_OPS                                         ================ */
@@ -21482,6 +22182,9 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* ======================================================  CECCKDIVCR  ======================================================= */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  I3CCKDIVCR  ======================================================= */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
 /* ======================================================  IICCKDIVCR  ======================================================= */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
@@ -23187,6 +23890,10 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_USB_HS0_DPUSRCR_FIXPHY_Pos          (0UL)        /*!< FIXPHY (Bit 0)                                        */
  #define R_USB_HS0_DPUSRCR_FIXPHY_Msk          (0x1UL)      /*!< FIXPHY (Bitfield-Mask: 0x01)                          */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
 /* =========================================================================================================================== */
 /* ================                                          R_FLAD                                           ================ */
 /* =========================================================================================================================== */
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h
index e1a36a912..11088103d 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h
@@ -1284,7 +1284,8 @@ typedef struct
             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
             uint8_t            : 1;
             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
-            uint8_t            : 2;
+            uint8_t            : 1;
+            __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
         } RTCCR_b;
     };
     __IM uint8_t RESERVED;
@@ -1664,6 +1665,213 @@ typedef struct
     };
 } R_USB_HS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
 
+/**
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
+            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
+            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
+            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
+            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
+            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
+        } AGTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
+            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
+            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
+            uint8_t              : 1;
+        } AGTMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+                                        *   ratio                                                                     */
+            uint8_t           : 4;
+            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
+        } AGTMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+                                        *   mode.                                                                     */
+            uint8_t             : 1;
+            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
+            uint8_t             : 1;
+            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
+            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
+        } AGTIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
+            uint8_t            : 5;
+        } AGTISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
+
+        struct
+        {
+            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
+            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
+            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
+            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
+            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
+            uint8_t              : 1;
+        } AGTCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_b;
+    };
+} R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
+
+        struct
+        {
+            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IM uint16_t                 RESERVED;
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
+} R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
+
+        struct
+        {
+            __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
+} R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_clusters */
 
 /* =========================================================================================================================== */
@@ -1956,16 +2164,17 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
 
     union
     {
-        __IM uint16_t ADDR[28];        /*!< (@ 0x00000020) A/D Data Register                                          */
+        __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
 
         struct
         {
             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
                                         *   storing the result of A/D conversion.                                     */
-        } ADDR_b[28];
+        } ADDR_b[29];
     };
-    __IM uint32_t RESERVED1[2];
-    __IM uint16_t RESERVED2;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+    __IM uint16_t RESERVED3;
 
     union
     {
@@ -2158,7 +2367,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint16_t                : 3;
         } ADSWTSTR2_b;
     };
-    __IM uint16_t RESERVED3;
+    __IM uint16_t RESERVED4;
 
     union
     {
@@ -2220,7 +2429,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 6;
         } ADACSR_b;
     };
-    __IM uint8_t RESERVED4;
+    __IM uint8_t RESERVED5;
 
     union
     {
@@ -2290,7 +2499,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
         } ADSER_b;
     };
-    __IM uint8_t RESERVED5;
+    __IM uint8_t RESERVED6;
 
     union
     {
@@ -2306,7 +2515,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
         } ADHVREFCNT_b;
     };
-    __IM uint8_t RESERVED6;
+    __IM uint8_t RESERVED7;
 
     union
     {
@@ -2324,8 +2533,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t              : 2;
         } ADWINMON_b;
     };
-    __IM uint8_t  RESERVED7;
-    __IM uint16_t RESERVED8;
+    __IM uint8_t  RESERVED8;
+    __IM uint16_t RESERVED9;
 
     union
     {
@@ -2501,7 +2710,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 6;
         } ADCMPSER_b;
     };
-    __IM uint8_t RESERVED9;
+    __IM uint8_t RESERVED10;
 
     union
     {
@@ -2516,7 +2725,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
         } ADCMPBNSR_b;
     };
-    __IM uint8_t RESERVED10;
+    __IM uint8_t RESERVED11;
 
     union
     {
@@ -2555,8 +2764,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 7;
         } ADCMPBSR_b;
     };
-    __IM uint8_t  RESERVED11;
-    __IM uint16_t RESERVED12;
+    __IM uint8_t  RESERVED12;
+    __IM uint16_t RESERVED13;
 
     union
     {
@@ -2760,7 +2969,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 7;
         } ADBUFEN_b;
     };
-    __IM uint8_t RESERVED13;
+    __IM uint8_t RESERVED14;
 
     union
     {
@@ -2774,9 +2983,9 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 3;
         } ADBUFPTR_b;
     };
-    __IM uint8_t  RESERVED14;
-    __IM uint32_t RESERVED15[2];
-    __IM uint8_t  RESERVED16;
+    __IM uint8_t  RESERVED15;
+    __IM uint32_t RESERVED16[2];
+    __IM uint8_t  RESERVED17;
 
     union
     {
@@ -2843,7 +3052,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
         } ADCALEXE_b;
     };
-    __IM uint8_t RESERVED17;
+    __IM uint8_t RESERVED18;
 
     union
     {
@@ -2860,8 +3069,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
         } VREFAMPCNT_b;
     };
-    __IM uint8_t  RESERVED18;
-    __IM uint16_t RESERVED19;
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -2883,8 +3092,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 6;
         } ADRST_b;
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint32_t RESERVED21[41];
+    __IM uint8_t  RESERVED21;
+    __IM uint32_t RESERVED22[41];
 
     union
     {
@@ -2942,7 +3151,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
         } ADPGAGS0_b;
     };
-    __IM uint32_t RESERVED22[3];
+    __IM uint32_t RESERVED23[3];
 
     union
     {
@@ -2969,7 +3178,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
         } ADPGADCR0_b;
     };
-    __IM uint16_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -2998,8 +3207,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 7;
         } ADPGADBS1_b;
     };
-    __IM uint16_t RESERVED24;
-    __IM uint32_t RESERVED25[10];
+    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED26[10];
 
     union
     {
@@ -3163,63 +3372,63 @@ typedef struct                         /*!< (@ 0x400E0000) R_PSCU Structure
 
     union
     {
-        __IM uint32_t CFSAMONA;        /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
+        __IOM uint32_t CFSAMONA;       /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
                                         *                  A                                                          */
 
         struct
         {
-            uint32_t           : 15;
-            __IM uint32_t CFS2 : 9;    /*!< [23..15] Code Flash Secure area 2                                         */
-            uint32_t           : 8;
+            uint32_t            : 15;
+            __IOM uint32_t CFS2 : 9;   /*!< [23..15] Code Flash Secure area 2                                         */
+            uint32_t            : 8;
         } CFSAMONA_b;
     };
 
     union
     {
-        __IM uint32_t CFSAMONB;        /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
+        __IOM uint32_t CFSAMONB;       /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
                                         *                  B                                                          */
 
         struct
         {
-            uint32_t           : 10;
-            __IM uint32_t CFS1 : 14;   /*!< [23..10] Code Flash Secure area 1                                         */
-            uint32_t           : 8;
+            uint32_t            : 10;
+            __IOM uint32_t CFS1 : 14;  /*!< [23..10] Code Flash Secure area 1                                         */
+            uint32_t            : 8;
         } CFSAMONB_b;
     };
 
     union
     {
-        __IM uint32_t DFSAMON;         /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register           */
+        __IOM uint32_t DFSAMON;        /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register           */
 
         struct
         {
-            uint32_t          : 10;
-            __IM uint32_t DFS : 6;     /*!< [15..10] Data flash Secure area                                           */
-            uint32_t          : 16;
+            uint32_t           : 10;
+            __IOM uint32_t DFS : 6;    /*!< [15..10] Data flash Secure area                                           */
+            uint32_t           : 16;
         } DFSAMON_b;
     };
 
     union
     {
-        __IM uint32_t SSAMONA;         /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A               */
+        __IOM uint32_t SSAMONA;        /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A               */
 
         struct
         {
-            uint32_t          : 13;
-            __IM uint32_t SS2 : 8;     /*!< [20..13] SRAM Secure area 2                                               */
-            uint32_t          : 11;
+            uint32_t           : 13;
+            __IOM uint32_t SS2 : 8;    /*!< [20..13] SRAM Secure area 2                                               */
+            uint32_t           : 11;
         } SSAMONA_b;
     };
 
     union
     {
-        __IM uint32_t SSAMONB;         /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B               */
+        __IOM uint32_t SSAMONB;        /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B               */
 
         struct
         {
-            uint32_t          : 10;
-            __IM uint32_t SS1 : 11;    /*!< [20..10] SRAM secure area 1                                               */
-            uint32_t          : 11;
+            uint32_t           : 10;
+            __IOM uint32_t SS1 : 11;   /*!< [20..10] SRAM secure area 1                                               */
+            uint32_t           : 11;
         } SSAMONB_b;
     };
 
@@ -3235,156 +3444,6 @@ typedef struct                         /*!< (@ 0x400E0000) R_PSCU Structure
     };
 } R_PSCU_Type;                         /*!< Size = 48 (0x30)                                                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Asynchronous General Purpose Timer (R_AGT0)
- */
-
-typedef struct                         /*!< (@ 0x400E8000) R_AGT0 Structure                                           */
-{
-    union
-    {
-        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
-
-        struct
-        {
-            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written
-                                        *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
-                                        *   is forcibly stopped and set to FFFFH.                                     */
-        } AGT_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCRn register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMA_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCR register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMB_b;
-    };
-    __IM uint16_t RESERVED;
-
-    union
-    {
-        __IOM uint8_t AGTCR;           /*!< (@ 0x00000008) AGT Control Register                                       */
-
-        struct
-        {
-            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
-            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
-            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
-            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
-            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
-            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
-        } AGTCR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000009) AGT Mode Register 1                                        */
-
-        struct
-        {
-            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
-            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
-            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
-            uint8_t              : 1;
-        } AGTMR1_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000A) AGT Mode Register 2                                        */
-
-        struct
-        {
-            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
-                                        *   ratio                                                                     */
-            uint8_t           : 4;
-            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
-        } AGTMR2_b;
-    };
-    __IM uint8_t RESERVED1;
-
-    union
-    {
-        __IOM uint8_t AGTIOC;          /*!< (@ 0x0000000C) AGT I/O Control Register                                   */
-
-        struct
-        {
-            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
-                                        *   mode.                                                                     */
-            uint8_t             : 1;
-            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
-            uint8_t             : 1;
-            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
-            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
-        } AGTIOC_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTISR;          /*!< (@ 0x0000000D) AGT Event Pin Select Register                              */
-
-        struct
-        {
-            uint8_t            : 2;
-            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
-            uint8_t            : 5;
-        } AGTISR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTCMSR;         /*!< (@ 0x0000000E) AGT Compare Match Function Select Register                 */
-
-        struct
-        {
-            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
-            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
-            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
-            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
-            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
-            uint8_t              : 1;
-        } AGTCMSR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x0000000F) AGT Pin Select Register                                    */
-
-        struct
-        {
-            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
-            uint8_t            : 2;
-            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
-            uint8_t            : 3;
-        } AGTIOSEL_b;
-    };
-} R_AGT0_Type;                         /*!< Size = 16 (0x10)                                                          */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -6868,43 +6927,96 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            uint32_t : 18;
         } GTSTR_b;
     };
 
@@ -6956,7 +7068,60 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
                                          *   1 means counter stop.                                                     */
-            uint32_t : 18;
+            __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
         } GTSTP_b;
     };
 
@@ -6980,7 +7145,24 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
-            uint32_t             : 18;
+            __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
         } GTCLR_b;
     };
 
@@ -7301,16 +7483,23 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+        __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
 
         struct
         {
-            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
-            uint32_t            : 15;
-            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
-            uint32_t            : 4;
-            __IOM uint32_t TPCS : 4;   /*!< [26..23] Timer Prescaler Select                                           */
-            uint32_t            : 5;
+            __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
+            uint32_t               : 7;
+            __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
+            __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
+            __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
+            __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
+            uint32_t               : 2;
+            __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
+            __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
+            uint32_t               : 3;
+            __IOM uint32_t TPCS    : 4; /*!< [26..23] Timer Prescaler Select                                           */
+            __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
+            uint32_t               : 3;
         } GTCR_b;
     };
 
@@ -7381,13 +7570,36 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
         struct
         {
-            uint32_t               : 24;
-            __IOM uint32_t GRP     : 2; /*!< [25..24] Output Disable Source Select                                     */
+            uint32_t            : 8;
+            __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
+            __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            uint32_t               : 4;
+            __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
             uint32_t               : 2;
-            __IOM uint32_t GRPDTE  : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
-            __IOM uint32_t GRPABH  : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable               */
-            __IOM uint32_t GRPABL  : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
-            __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
+            __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
+            __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
         } GTINTAD_b;
     };
 
@@ -7430,32 +7642,36 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTBER;          /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
 
         struct
         {
-            __IOM uint32_t BD0    : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
-            __IOM uint32_t BD1    : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
-            __IOM uint32_t BD2    : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
-            __IOM uint32_t BD3    : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
-            uint32_t              : 12;
-            __IOM uint32_t CCRA   : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
-            __IOM uint32_t CCRB   : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
-            __IOM uint32_t PR     : 2; /*!< [21..20] GTPR Buffer Operation                                            */
-            __OM uint32_t  CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
-                                        *   is read as 0.                                                             */
+            __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
+            __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+                                         *   is read as 0.                                                             */
             uint32_t             : 1;
-            __IOM uint32_t ADTTA : 2;  /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDA : 1;  /*!< [26..26] GTADTRA Double Buffer Operation                                  */
+            __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
             uint32_t             : 1;
-            __IOM uint32_t ADTTB : 2;  /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDB : 1;  /*!< [30..30] GTADTRB Double Buffer Operation                                  */
+            __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
             uint32_t             : 1;
         } GTBER_b;
     };
@@ -7679,7 +7895,126 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             uint32_t            : 31;
         } GTSOTR_b;
     };
-    __IM uint32_t RESERVED[5];
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
 
     union
     {
@@ -7713,7 +8048,7 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             uint32_t            : 4;
         } GTPC_b;
     };
-    __IM uint32_t RESERVED1[4];
+    __IM uint32_t RESERVED[4];
 
     union
     {
@@ -7755,17 +8090,137 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
         {
             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 4;
             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
-            uint32_t             : 7;
+            __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
+            uint32_t             : 6;
             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
-            uint32_t             : 7;
+            __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
+            uint32_t             : 6;
         } GTSECR_b;
     };
-} R_GPT0_Type;                         /*!< Size = 216 (0xd8)                                                         */
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
+            __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
+                                        *   Disable                                                                   */
+            uint32_t             : 2;
+            __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t             : 1;
+            __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
+                                        *   Transfer Disable                                                          */
+            uint32_t             : 2;
+            __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
+            __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
+            __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
+            __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
+            uint32_t             : 2;
+        } GTBER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
+
+        struct
+        {
+            __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
+            uint32_t              : 11;
+            __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
+            uint32_t              : 11;
+        } GTOLBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
+                                        *                  Capture Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
+            __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
+                                        *   Other Channel GTCCRb Input Capture Source Enable                          */
+            __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
+        } GTICCR_b;
+    };
+} R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_OPS                                         ================ */
@@ -13487,8 +13942,18 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } IICCKDIVCR_b;
         };
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint16_t RESERVED21;
+
+    union
+    {
+        __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
+
+        struct
+        {
+            __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
+            uint8_t                : 5;
+        } I3CCKDIVCR_b;
+    };
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -13615,8 +14080,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
         } I3CCKCR_b;
     };
-    __IM uint16_t RESERVED22;
-    __IM uint32_t RESERVED23[3];
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
 
     union
     {
@@ -13630,8 +14095,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                 : 29;
         } SNZREQCR1_b;
     };
-    __IM uint32_t RESERVED24;
-    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -13646,7 +14111,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
         } SNZCR_b;
     };
-    __IM uint8_t RESERVED26;
+    __IM uint8_t RESERVED25;
 
     union
     {
@@ -13676,7 +14141,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } SNZEDCR1_b;
     };
-    __IM uint16_t RESERVED27;
+    __IM uint16_t RESERVED26;
 
     union
     {
@@ -13719,7 +14184,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 1;
         } SNZREQCR_b;
     };
-    __IM uint16_t RESERVED28;
+    __IM uint16_t RESERVED27;
 
     union
     {
@@ -13757,7 +14222,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 3;
         } OPCCR_b;
     };
-    __IM uint8_t RESERVED29;
+    __IM uint8_t RESERVED28;
 
     union
     {
@@ -13769,7 +14234,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } MOSCWTCR_b;
     };
-    __IM uint8_t RESERVED30[2];
+    __IM uint8_t RESERVED29[2];
 
     union
     {
@@ -13782,7 +14247,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t : 5;
         } HOCOWTCR_b;
     };
-    __IM uint16_t RESERVED31[2];
+    __IM uint16_t RESERVED30[2];
 
     union
     {
@@ -13796,8 +14261,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 3;
         } SOPCCR_b;
     };
-    __IM uint8_t  RESERVED32;
-    __IM uint32_t RESERVED33[5];
+    __IM uint8_t  RESERVED31;
+    __IM uint32_t RESERVED32[5];
 
     union
     {
@@ -13831,8 +14296,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
         } RSTSR1_b;
     };
-    __IM uint16_t RESERVED34;
-    __IM uint32_t RESERVED35[3];
+    __IM uint16_t RESERVED33;
+    __IM uint32_t RESERVED34[3];
 
     union
     {
@@ -13858,8 +14323,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
         } SDADCCKCR_b;
     };
-    __IM uint16_t RESERVED36;
-    __IM uint32_t RESERVED37[3];
+    __IM uint16_t RESERVED35;
+    __IM uint32_t RESERVED36[3];
 
     union
     {
@@ -13914,7 +14379,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t          : 6;
         } LVD2SR_b;
     };
-    __IM uint32_t RESERVED38[183];
+    __IM uint32_t RESERVED37[183];
 
     union
     {
@@ -13942,7 +14407,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 14;
         } CGFSAR_b;
     };
-    __IM uint32_t RESERVED39;
+    __IM uint32_t RESERVED38;
 
     union
     {
@@ -14011,7 +14476,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 8;
         } BBFSAR_b;
     };
-    __IM uint32_t RESERVED40[3];
+    __IM uint32_t RESERVED39[3];
 
     union
     {
@@ -14073,8 +14538,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 4;
         } DPFSAR_b;
     };
-    __IM uint32_t RESERVED41[6];
-    __IM uint16_t RESERVED42;
+    __IM uint32_t RESERVED40[6];
+    __IM uint16_t RESERVED41;
 
     union
     {
@@ -14292,7 +14757,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 3;
         } DPSIEGR2_b;
     };
-    __IM uint8_t RESERVED43;
+    __IM uint8_t RESERVED42;
 
     union
     {
@@ -14350,7 +14815,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } RSTSR2_b;
     };
-    __IM uint8_t RESERVED44;
+    __IM uint8_t RESERVED43;
 
     union
     {
@@ -14367,7 +14832,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                           *   Enable                                                                    */
         } MOMCR_b;
     };
-    __IM uint16_t RESERVED45;
+    __IM uint16_t RESERVED44;
 
     union
     {
@@ -14437,7 +14902,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } LVD2CMPCR_b;
         };
     };
-    __IM uint8_t RESERVED46;
+    __IM uint8_t RESERVED45;
 
     union
     {
@@ -14470,7 +14935,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
         } LVD2CR0_b;
     };
-    __IM uint8_t RESERVED47;
+    __IM uint8_t RESERVED46;
 
     union
     {
@@ -14505,7 +14970,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 7;
         } VBTCR1_b;
     };
-    __IM uint32_t RESERVED48[8];
+    __IM uint32_t RESERVED47[8];
 
     union
     {
@@ -14548,7 +15013,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 6;
         } VCCSEL_b;
     };
-    __IM uint16_t RESERVED49;
+    __IM uint16_t RESERVED48;
 
     union
     {
@@ -14560,9 +15025,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } PL2LDOSCR_b;
     };
-    __IM uint8_t  RESERVED50;
-    __IM uint16_t RESERVED51;
-    __IM uint32_t RESERVED52[14];
+    __IM uint8_t  RESERVED49;
+    __IM uint16_t RESERVED50;
+    __IM uint32_t RESERVED51[14];
 
     union
     {
@@ -14585,8 +15050,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 6;
         } SOMCR_b;
     };
-    __IM uint16_t RESERVED53;
-    __IM uint32_t RESERVED54[3];
+    __IM uint16_t RESERVED52;
+    __IM uint32_t RESERVED53[3];
 
     union
     {
@@ -14598,7 +15063,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 7;
         } LOCOCR_b;
     };
-    __IM uint8_t RESERVED55;
+    __IM uint8_t RESERVED54;
 
     union
     {
@@ -14613,8 +15078,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                          *   trimming bits                                                             */
         } LOCOUTCR_b;
     };
-    __IM uint8_t  RESERVED56;
-    __IM uint32_t RESERVED57[7];
+    __IM uint8_t  RESERVED55;
+    __IM uint32_t RESERVED56[7];
 
     union
     {
@@ -14653,7 +15118,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 7;
         } VBTCMPCR_b;
     };
-    __IM uint8_t RESERVED58;
+    __IM uint8_t RESERVED57;
 
     union
     {
@@ -14667,7 +15132,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                  : 6;
         } VBTLVDICR_b;
     };
-    __IM uint8_t RESERVED59;
+    __IM uint8_t RESERVED58;
 
     union
     {
@@ -14679,7 +15144,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } VBTWCTLR_b;
     };
-    __IM uint8_t RESERVED60;
+    __IM uint8_t RESERVED59;
 
     union
     {
@@ -14814,9 +15279,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } VBTBER_b;
     };
-    __IM uint8_t  RESERVED61;
-    __IM uint16_t RESERVED62;
-    __IM uint32_t RESERVED63[15];
+    __IM uint8_t  RESERVED60;
+    __IM uint16_t RESERVED61;
+    __IM uint32_t RESERVED62[15];
 
     union
     {
@@ -14840,7 +15305,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
  * @brief Temperature Sensor (R_TSN_CAL)
  */
 
-typedef struct                         /*!< (@ 0x400F3228) R_TSN_CAL Structure                                        */
+typedef struct                         /*!< (@ 0x407FB17C) R_TSN_CAL Structure                                        */
 {
     union
     {
@@ -18122,6 +18587,23 @@ typedef struct                         /*!< (@ 0x40111000) R_USB_HS0 Structure
     };
 } R_USB_HS0_Type;                        /*!< Size = 364 (0x16c)                                                        */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
+ */
+
+typedef struct                          /*!< (@ 0x400E8000) R_AGTX0 Structure                                          */
+{
+    union
+    {
+        __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
+        __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
+    };
+} R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
 /* =========================================================================================================================== */
 /* ================                                          R_FLAD                                           ================ */
 /* =========================================================================================================================== */
@@ -18158,12 +18640,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_ADC0_BASE            0x40170000UL
  #define R_ADC1_BASE            0x40170200UL
  #define R_PSCU_BASE            0x400E0000UL
- #define R_AGT0_BASE            0x400E8000UL
- #define R_AGT1_BASE            0x400E8100UL
- #define R_AGT2_BASE            0x400E8200UL
- #define R_AGT3_BASE            0x400E8300UL
- #define R_AGT4_BASE            0x400E8400UL
- #define R_AGT5_BASE            0x400E8500UL
  #define R_BUS_BASE             0x40003000UL
  #define R_CAC_BASE             0x40083600UL
  #define R_CANFD_BASE           0x400B0000UL
@@ -18254,7 +18730,7 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_SSI0_BASE            0x4009D000UL
  #define R_SSI1_BASE            0x4009D100UL
  #define R_SYSTEM_BASE          0x4001E000UL
- #define R_TSN_CAL_BASE         0x400F3228UL
+ #define R_TSN_CAL_BASE         0x407FB17CUL
  #define R_TSN_CTRL_BASE        0x400F3000UL
  #define R_USB_FS0_BASE         0x40090000UL
  #define R_WDT_BASE             0x40083400UL
@@ -18264,6 +18740,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_CEC_BASE             0x400AC000UL
  #define R_OSPI_BASE            0x400A6000UL
  #define R_USB_HS0_BASE         0x40111000UL
+ #define R_AGTX0_BASE           0x400E8000UL
+ #define R_AGTX1_BASE           0x400E8100UL
+ #define R_AGTX2_BASE           0x400E8200UL
+ #define R_AGTX3_BASE           0x400E8300UL
+ #define R_AGTX4_BASE           0x400E8400UL
+ #define R_AGTX5_BASE           0x400E8500UL
+ #define R_AGTX6_BASE           0x400E8600UL
+ #define R_AGTX7_BASE           0x400E8700UL
+ #define R_AGTX8_BASE           0x400E8800UL
+ #define R_AGTX9_BASE           0x400E8900UL
  #define R_FLAD_BASE            0x407FC000UL
 
 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
@@ -18279,12 +18765,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_ADC0            ((R_ADC0_Type *) R_ADC0_BASE)
  #define R_ADC1            ((R_ADC0_Type *) R_ADC1_BASE)
  #define R_PSCU            ((R_PSCU_Type *) R_PSCU_BASE)
- #define R_AGT0            ((R_AGT0_Type *) R_AGT0_BASE)
- #define R_AGT1            ((R_AGT0_Type *) R_AGT1_BASE)
- #define R_AGT2            ((R_AGT0_Type *) R_AGT2_BASE)
- #define R_AGT3            ((R_AGT0_Type *) R_AGT3_BASE)
- #define R_AGT4            ((R_AGT0_Type *) R_AGT4_BASE)
- #define R_AGT5            ((R_AGT0_Type *) R_AGT5_BASE)
 
 /* #define R_BUS                       ((R_BUS_Type*)             R_BUS_BASE) */
  #define R_CAC             ((R_CAC_Type *) R_CAC_BASE)
@@ -18386,6 +18866,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_CEC             ((R_CEC_Type *) R_CEC_BASE)
  #define R_OSPI            ((R_OSPI_Type *) R_OSPI_BASE)
  #define R_USB_HS0         ((R_USB_HS0_Type *) R_USB_HS0_BASE)
+ #define R_AGTX0           ((R_AGTX0_Type *) R_AGTX0_BASE)
+ #define R_AGTX1           ((R_AGTX0_Type *) R_AGTX1_BASE)
+ #define R_AGTX2           ((R_AGTX0_Type *) R_AGTX2_BASE)
+ #define R_AGTX3           ((R_AGTX0_Type *) R_AGTX3_BASE)
+ #define R_AGTX4           ((R_AGTX0_Type *) R_AGTX4_BASE)
+ #define R_AGTX5           ((R_AGTX0_Type *) R_AGTX5_BASE)
+ #define R_AGTX6           ((R_AGTX0_Type *) R_AGTX6_BASE)
+ #define R_AGTX7           ((R_AGTX0_Type *) R_AGTX7_BASE)
+ #define R_AGTX8           ((R_AGTX0_Type *) R_AGTX8_BASE)
+ #define R_AGTX9           ((R_AGTX0_Type *) R_AGTX9_BASE)
  #define R_FLAD            ((R_FLAD_Type *) R_FLAD_BASE)
 
 /** @} */ /* End of group Device_Peripheral_declaration */
@@ -19093,6 +19583,8 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* =========================================================================================================================== */
 
 /* =========================================================  RTCCR  ========================================================= */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
@@ -19253,6 +19745,101 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
  #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
 
+/* =========================================================================================================================== */
+/* ================                                           CTRL                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  AGTCR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AGTMR1  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
+/* ========================================================  AGTMR2  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
+/* =====================================================  AGTIOSEL_ALT  ====================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+/* ========================================================  AGTIOC  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AGTISR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AGTCMSR  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
+/* =======================================================  AGTIOSEL  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT16                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT32                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
+
 /** @} */ /* End of group PosMask_clusters */
 
 /* =========================================================================================================================== */
@@ -19918,77 +20505,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_PSCU_DLMMON_DLMMON_Pos    (0UL)          /*!< DLMMON (Bit 0)                                        */
  #define R_PSCU_DLMMON_DLMMON_Msk    (0xfUL)        /*!< DLMMON (Bitfield-Mask: 0x0f)                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/* ==========================================================  AGT  ========================================================== */
- #define R_AGT0_AGT_AGT_Pos           (0UL)      /*!< AGT (Bit 0)                                           */
- #define R_AGT0_AGT_AGT_Msk           (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
-/* ========================================================  AGTCMA  ========================================================= */
- #define R_AGT0_AGTCMA_AGTCMA_Pos     (0UL)      /*!< AGTCMA (Bit 0)                                        */
- #define R_AGT0_AGTCMA_AGTCMA_Msk     (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
-/* ========================================================  AGTCMB  ========================================================= */
- #define R_AGT0_AGTCMB_AGTCMB_Pos     (0UL)      /*!< AGTCMB (Bit 0)                                        */
- #define R_AGT0_AGTCMB_AGTCMB_Msk     (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
-/* =========================================================  AGTCR  ========================================================= */
- #define R_AGT0_AGTCR_TCMBF_Pos       (7UL)      /*!< TCMBF (Bit 7)                                         */
- #define R_AGT0_AGTCR_TCMBF_Msk       (0x80UL)   /*!< TCMBF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCMAF_Pos       (6UL)      /*!< TCMAF (Bit 6)                                         */
- #define R_AGT0_AGTCR_TCMAF_Msk       (0x40UL)   /*!< TCMAF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TUNDF_Pos       (5UL)      /*!< TUNDF (Bit 5)                                         */
- #define R_AGT0_AGTCR_TUNDF_Msk       (0x20UL)   /*!< TUNDF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TEDGF_Pos       (4UL)      /*!< TEDGF (Bit 4)                                         */
- #define R_AGT0_AGTCR_TEDGF_Msk       (0x10UL)   /*!< TEDGF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTOP_Pos       (2UL)      /*!< TSTOP (Bit 2)                                         */
- #define R_AGT0_AGTCR_TSTOP_Msk       (0x4UL)    /*!< TSTOP (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCSTF_Pos       (1UL)      /*!< TCSTF (Bit 1)                                         */
- #define R_AGT0_AGTCR_TCSTF_Msk       (0x2UL)    /*!< TCSTF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTART_Pos      (0UL)      /*!< TSTART (Bit 0)                                        */
- #define R_AGT0_AGTCR_TSTART_Msk      (0x1UL)    /*!< TSTART (Bitfield-Mask: 0x01)                          */
-/* ========================================================  AGTMR1  ========================================================= */
- #define R_AGT0_AGTMR1_TCK_Pos        (4UL)      /*!< TCK (Bit 4)                                           */
- #define R_AGT0_AGTMR1_TCK_Msk        (0x70UL)   /*!< TCK (Bitfield-Mask: 0x07)                             */
- #define R_AGT0_AGTMR1_TEDGPL_Pos     (3UL)      /*!< TEDGPL (Bit 3)                                        */
- #define R_AGT0_AGTMR1_TEDGPL_Msk     (0x8UL)    /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTMR1_TMOD_Pos       (0UL)      /*!< TMOD (Bit 0)                                          */
- #define R_AGT0_AGTMR1_TMOD_Msk       (0x7UL)    /*!< TMOD (Bitfield-Mask: 0x07)                            */
-/* ========================================================  AGTMR2  ========================================================= */
- #define R_AGT0_AGTMR2_LPM_Pos        (7UL)      /*!< LPM (Bit 7)                                           */
- #define R_AGT0_AGTMR2_LPM_Msk        (0x80UL)   /*!< LPM (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTMR2_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
- #define R_AGT0_AGTMR2_CKS_Msk        (0x7UL)    /*!< CKS (Bitfield-Mask: 0x07)                             */
-/* ========================================================  AGTIOC  ========================================================= */
- #define R_AGT0_AGTIOC_TIOGT_Pos      (6UL)      /*!< TIOGT (Bit 6)                                         */
- #define R_AGT0_AGTIOC_TIOGT_Msk      (0xc0UL)   /*!< TIOGT (Bitfield-Mask: 0x03)                           */
- #define R_AGT0_AGTIOC_TIPF_Pos       (4UL)      /*!< TIPF (Bit 4)                                          */
- #define R_AGT0_AGTIOC_TIPF_Msk       (0x30UL)   /*!< TIPF (Bitfield-Mask: 0x03)                            */
- #define R_AGT0_AGTIOC_TOE_Pos        (2UL)      /*!< TOE (Bit 2)                                           */
- #define R_AGT0_AGTIOC_TOE_Msk        (0x4UL)    /*!< TOE (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTIOC_TEDGSEL_Pos    (0UL)      /*!< TEDGSEL (Bit 0)                                       */
- #define R_AGT0_AGTIOC_TEDGSEL_Msk    (0x1UL)    /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
-/* ========================================================  AGTISR  ========================================================= */
- #define R_AGT0_AGTISR_EEPS_Pos       (2UL)      /*!< EEPS (Bit 2)                                          */
- #define R_AGT0_AGTISR_EEPS_Msk       (0x4UL)    /*!< EEPS (Bitfield-Mask: 0x01)                            */
-/* ========================================================  AGTCMSR  ======================================================== */
- #define R_AGT0_AGTCMSR_TOPOLB_Pos    (6UL)      /*!< TOPOLB (Bit 6)                                        */
- #define R_AGT0_AGTCMSR_TOPOLB_Msk    (0x40UL)   /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEB_Pos      (5UL)      /*!< TOEB (Bit 5)                                          */
- #define R_AGT0_AGTCMSR_TOEB_Msk      (0x20UL)   /*!< TOEB (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEB_Pos     (4UL)      /*!< TCMEB (Bit 4)                                         */
- #define R_AGT0_AGTCMSR_TCMEB_Msk     (0x10UL)   /*!< TCMEB (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCMSR_TOPOLA_Pos    (2UL)      /*!< TOPOLA (Bit 2)                                        */
- #define R_AGT0_AGTCMSR_TOPOLA_Msk    (0x4UL)    /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEA_Pos      (1UL)      /*!< TOEA (Bit 1)                                          */
- #define R_AGT0_AGTCMSR_TOEA_Msk      (0x2UL)    /*!< TOEA (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEA_Pos     (0UL)      /*!< TCMEA (Bit 0)                                         */
- #define R_AGT0_AGTCMSR_TCMEA_Msk     (0x1UL)    /*!< TCMEA (Bitfield-Mask: 0x01)                           */
-/* =======================================================  AGTIOSEL  ======================================================== */
- #define R_AGT0_AGTIOSEL_TIES_Pos     (4UL)      /*!< TIES (Bit 4)                                          */
- #define R_AGT0_AGTIOSEL_TIES_Msk     (0x10UL)   /*!< TIES (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTIOSEL_SEL_Pos      (0UL)      /*!< SEL (Bit 0)                                           */
- #define R_AGT0_AGTIOSEL_SEL_Msk      (0x3UL)    /*!< SEL (Bitfield-Mask: 0x03)                             */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -21722,10 +22238,22 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
 /* =========================================================  GTCR  ========================================================== */
+ #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
+ #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTCR_TPCS_Pos              (23UL)         /*!< TPCS (Bit 23)                                         */
  #define R_GPT0_GTCR_TPCS_Msk              (0x7800000UL)  /*!< TPCS (Bitfield-Mask: 0x0f)                            */
  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
- #define R_GPT0_GTCR_MD_Msk                (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
+ #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
+ #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
+ #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
+ #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
 /* =======================================================  GTUDDTYC  ======================================================== */
@@ -21783,6 +22311,8 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
 /* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
+ #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
@@ -21791,8 +22321,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
- #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
- #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
+ #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
+ #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
+ #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
 /* =========================================================  GTST  ========================================================== */
  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
@@ -21849,6 +22387,8 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
+ #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
@@ -21938,6 +22478,67 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* ========================================================  GTSOTR  ========================================================= */
  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
 /* ========================================================  GTICLF  ========================================================= */
  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
@@ -21980,14 +22581,113 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
+ #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
+ #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTBER2  ========================================================= */
+ #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
+ #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
+ #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
+ #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
+ #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
+ #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
+ #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
+ #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
+ #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
+ #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
+ #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
+ #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
+ #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
+ #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
+ #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
+ #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
+ #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
+ #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
+ #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
+ #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTOLBR  ========================================================= */
+ #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
+ #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
+ #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
+ #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  GTICCR  ========================================================= */
+ #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
+ #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
+ #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
+ #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
+ #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
+ #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
+ #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
+ #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
+ #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
+ #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
+ #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
+ #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
+ #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
+ #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
+ #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
+ #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
+ #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
+ #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
+ #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
+ #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
+ #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_OPS                                         ================ */
@@ -25305,6 +26005,9 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* ======================================================  CECCKDIVCR  ======================================================= */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  I3CCKDIVCR  ======================================================= */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
 /* ======================================================  IICCKDIVCR  ======================================================= */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
@@ -27180,6 +27883,10 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_USB_HS0_DPUSRCR_FIXPHY_Pos          (0UL)        /*!< FIXPHY (Bit 0)                                        */
  #define R_USB_HS0_DPUSRCR_FIXPHY_Msk          (0x1UL)      /*!< FIXPHY (Bitfield-Mask: 0x01)                          */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
 /* =========================================================================================================================== */
 /* ================                                          R_FLAD                                           ================ */
 /* =========================================================================================================================== */
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h
index e23d07904..c5ffadf6f 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h
@@ -805,6 +805,213 @@ typedef struct
     __IOM uint16_t PMSAR;              /*!< (@ 0x00000000) Port Security Attribution Register                         */
 } R_PMISC_PMSAR_Type;                  /*!< Size = 2 (0x2)                                                            */
 
+/**
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
+            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
+            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
+            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
+            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
+            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
+        } AGTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
+            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
+            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
+            uint8_t              : 1;
+        } AGTMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+                                        *   ratio                                                                     */
+            uint8_t           : 4;
+            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
+        } AGTMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+                                        *   mode.                                                                     */
+            uint8_t             : 1;
+            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
+            uint8_t             : 1;
+            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
+            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
+        } AGTIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
+            uint8_t            : 5;
+        } AGTISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
+
+        struct
+        {
+            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
+            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
+            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
+            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
+            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
+            uint8_t              : 1;
+        } AGTCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_b;
+    };
+} R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
+
+        struct
+        {
+            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IM uint16_t                 RESERVED;
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
+} R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
+
+        struct
+        {
+            __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
+} R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_clusters */
 
 /* =========================================================================================================================== */
@@ -1172,16 +1379,17 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
 
     union
     {
-        __IM uint16_t ADDR[28];        /*!< (@ 0x00000020) A/D Data Register                                          */
+        __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
 
         struct
         {
             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
                                         *   storing the result of A/D conversion.                                     */
-        } ADDR_b[28];
+        } ADDR_b[29];
     };
-    __IM uint32_t RESERVED1[2];
-    __IM uint16_t RESERVED2;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+    __IM uint16_t RESERVED3;
 
     union
     {
@@ -1374,7 +1582,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint16_t                : 3;
         } ADSWTSTR2_b;
     };
-    __IM uint16_t RESERVED3;
+    __IM uint16_t RESERVED4;
 
     union
     {
@@ -1436,7 +1644,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 6;
         } ADACSR_b;
     };
-    __IM uint8_t RESERVED4;
+    __IM uint8_t RESERVED5;
 
     union
     {
@@ -1506,7 +1714,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
         } ADSER_b;
     };
-    __IM uint8_t RESERVED5;
+    __IM uint8_t RESERVED6;
 
     union
     {
@@ -1522,7 +1730,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
         } ADHVREFCNT_b;
     };
-    __IM uint8_t RESERVED6;
+    __IM uint8_t RESERVED7;
 
     union
     {
@@ -1540,8 +1748,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t              : 2;
         } ADWINMON_b;
     };
-    __IM uint8_t  RESERVED7;
-    __IM uint16_t RESERVED8;
+    __IM uint8_t  RESERVED8;
+    __IM uint16_t RESERVED9;
 
     union
     {
@@ -1717,7 +1925,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 6;
         } ADCMPSER_b;
     };
-    __IM uint8_t RESERVED9;
+    __IM uint8_t RESERVED10;
 
     union
     {
@@ -1732,7 +1940,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
         } ADCMPBNSR_b;
     };
-    __IM uint8_t RESERVED10;
+    __IM uint8_t RESERVED11;
 
     union
     {
@@ -1771,8 +1979,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 7;
         } ADCMPBSR_b;
     };
-    __IM uint8_t  RESERVED11;
-    __IM uint16_t RESERVED12;
+    __IM uint8_t  RESERVED12;
+    __IM uint16_t RESERVED13;
 
     union
     {
@@ -1976,7 +2184,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 7;
         } ADBUFEN_b;
     };
-    __IM uint8_t RESERVED13;
+    __IM uint8_t RESERVED14;
 
     union
     {
@@ -1990,9 +2198,9 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 3;
         } ADBUFPTR_b;
     };
-    __IM uint8_t  RESERVED14;
-    __IM uint32_t RESERVED15[2];
-    __IM uint8_t  RESERVED16;
+    __IM uint8_t  RESERVED15;
+    __IM uint32_t RESERVED16[2];
+    __IM uint8_t  RESERVED17;
 
     union
     {
@@ -2059,7 +2267,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
         } ADCALEXE_b;
     };
-    __IM uint8_t RESERVED17;
+    __IM uint8_t RESERVED18;
 
     union
     {
@@ -2076,8 +2284,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
         } VREFAMPCNT_b;
     };
-    __IM uint8_t  RESERVED18;
-    __IM uint16_t RESERVED19;
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -2099,8 +2307,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t             : 6;
         } ADRST_b;
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint32_t RESERVED21[41];
+    __IM uint8_t  RESERVED21;
+    __IM uint32_t RESERVED22[41];
 
     union
     {
@@ -2158,7 +2366,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
         } ADPGAGS0_b;
     };
-    __IM uint32_t RESERVED22[3];
+    __IM uint32_t RESERVED23[3];
 
     union
     {
@@ -2185,7 +2393,7 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
         } ADPGADCR0_b;
     };
-    __IM uint16_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -2214,8 +2422,8 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
             uint8_t : 7;
         } ADPGADBS1_b;
     };
-    __IM uint16_t RESERVED24;
-    __IM uint32_t RESERVED25[10];
+    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED26[10];
 
     union
     {
@@ -2231,156 +2439,6 @@ typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure
     };
 } R_ADC0_Type;                         /*!< Size = 484 (0x1e4)                                                        */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Asynchronous General Purpose Timer (R_AGT0)
- */
-
-typedef struct                         /*!< (@ 0x40084000) R_AGT0 Structure                                           */
-{
-    union
-    {
-        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
-
-        struct
-        {
-            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written
-                                        *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
-                                        *   is forcibly stopped and set to FFFFH.                                     */
-        } AGT_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCRn register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMA_b;
-    };
-
-    union
-    {
-        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
-
-        struct
-        {
-            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCR register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMB_b;
-    };
-    __IM uint16_t RESERVED;
-
-    union
-    {
-        __IOM uint8_t AGTCR;           /*!< (@ 0x00000008) AGT Control Register                                       */
-
-        struct
-        {
-            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
-            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
-            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
-            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
-            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
-            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
-        } AGTCR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000009) AGT Mode Register 1                                        */
-
-        struct
-        {
-            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
-            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
-            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
-            uint8_t              : 1;
-        } AGTMR1_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000A) AGT Mode Register 2                                        */
-
-        struct
-        {
-            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
-                                        *   ratio                                                                     */
-            uint8_t           : 4;
-            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
-        } AGTMR2_b;
-    };
-    __IM uint8_t RESERVED1;
-
-    union
-    {
-        __IOM uint8_t AGTIOC;          /*!< (@ 0x0000000C) AGT I/O Control Register                                   */
-
-        struct
-        {
-            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
-                                        *   mode.                                                                     */
-            uint8_t             : 1;
-            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
-            uint8_t             : 1;
-            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
-            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
-        } AGTIOC_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTISR;          /*!< (@ 0x0000000D) AGT Event Pin Select Register                              */
-
-        struct
-        {
-            uint8_t            : 2;
-            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
-            uint8_t            : 5;
-        } AGTISR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTCMSR;         /*!< (@ 0x0000000E) AGT Compare Match Function Select Register                 */
-
-        struct
-        {
-            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
-            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
-            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
-            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
-            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
-            uint8_t              : 1;
-        } AGTCMSR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x0000000F) AGT Pin Select Register                                    */
-
-        struct
-        {
-            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
-            uint8_t            : 2;
-            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
-            uint8_t            : 3;
-        } AGTIOSEL_b;
-    };
-} R_AGT0_Type;                         /*!< Size = 16 (0x10)                                                          */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -4240,46 +4298,99 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+            __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            uint32_t : 18;
         } GTSTR_b;
     };
 
@@ -4331,7 +4442,60 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
                                          *   1 means counter stop.                                                     */
-            uint32_t : 18;
+            __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
         } GTSTP_b;
     };
 
@@ -4355,7 +4519,24 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
-            uint32_t             : 18;
+            __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
         } GTCLR_b;
     };
 
@@ -4676,16 +4857,23 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+        __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
 
         struct
         {
-            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
-            uint32_t            : 15;
-            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
-            uint32_t            : 5;
-            __IOM uint32_t TPCS : 3;   /*!< [26..24] Timer Prescaler Select                                           */
-            uint32_t            : 5;
+            __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
+            uint32_t               : 7;
+            __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
+            __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
+            __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
+            __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
+            uint32_t               : 2;
+            __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
+            __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
+            uint32_t               : 4;
+            __IOM uint32_t TPCS    : 3; /*!< [26..24] Timer Prescaler Select                                           */
+            __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
+            uint32_t               : 3;
         } GTCR_b;
     };
 
@@ -4756,13 +4944,36 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
         struct
         {
-            uint32_t               : 24;
-            __IOM uint32_t GRP     : 2; /*!< [25..24] Output Disable Source Select                                     */
+            uint32_t            : 8;
+            __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
+            __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            uint32_t               : 4;
+            __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
             uint32_t               : 2;
-            __IOM uint32_t GRPDTE  : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
-            __IOM uint32_t GRPABH  : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable               */
-            __IOM uint32_t GRPABL  : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
-            __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
+            __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
+            __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
         } GTINTAD_b;
     };
 
@@ -4805,32 +5016,36 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTBER;          /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
 
         struct
         {
-            __IOM uint32_t BD0    : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
-            __IOM uint32_t BD1    : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
-            __IOM uint32_t BD2    : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
-            __IOM uint32_t BD3    : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
-            uint32_t              : 12;
-            __IOM uint32_t CCRA   : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
-            __IOM uint32_t CCRB   : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
-            __IOM uint32_t PR     : 2; /*!< [21..20] GTPR Buffer Operation                                            */
-            __OM uint32_t  CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
-                                        *   is read as 0.                                                             */
+            __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
+            __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+                                         *   is read as 0.                                                             */
             uint32_t             : 1;
-            __IOM uint32_t ADTTA : 2;  /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDA : 1;  /*!< [26..26] GTADTRA Double Buffer Operation                                  */
+            __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
             uint32_t             : 1;
-            __IOM uint32_t ADTTB : 2;  /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDB : 1;  /*!< [30..30] GTADTRB Double Buffer Operation                                  */
+            __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
             uint32_t             : 1;
         } GTBER_b;
     };
@@ -5054,7 +5269,126 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             uint32_t            : 31;
         } GTSOTR_b;
     };
-    __IM uint32_t RESERVED[5];
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
 
     union
     {
@@ -5088,7 +5422,7 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
             uint32_t            : 4;
         } GTPC_b;
     };
-    __IM uint32_t RESERVED1[4];
+    __IM uint32_t RESERVED[4];
 
     union
     {
@@ -5130,17 +5464,137 @@ typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure
         {
             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
-            uint32_t             : 6;
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 4;
             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
-            uint32_t             : 7;
+            __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
+            uint32_t             : 6;
             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
-            uint32_t             : 7;
+            __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
+            uint32_t             : 6;
         } GTSECR_b;
     };
-} R_GPT0_Type;                         /*!< Size = 216 (0xd8)                                                         */
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
+            __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
+                                        *   Disable                                                                   */
+            uint32_t             : 2;
+            __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t             : 1;
+            __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
+                                        *   Transfer Disable                                                          */
+            uint32_t             : 2;
+            __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
+            __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
+            __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
+            __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
+            uint32_t             : 2;
+        } GTBER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
+
+        struct
+        {
+            __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
+            uint32_t              : 11;
+            __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
+            uint32_t              : 11;
+        } GTOLBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
+                                        *                  Capture Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
+            __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
+                                        *   Other Channel GTCCRb Input Capture Source Enable                          */
+            __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
+        } GTICCR_b;
+    };
+} R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_ODC                                         ================ */
@@ -6549,9 +7003,9 @@ typedef struct                         /*!< (@ 0x40040D00) R_PMISC Structure
 
 typedef struct                         /*!< (@ 0x40044000) R_RTC Structure                                            */
 {
-    __IM uint8_t RESERVED[34];
-    __IM uint8_t RCR1;                 /*!< (@ 0x00000022) Reset Control Register 1                                   */
-    __IM uint8_t RESERVED1;
+    __IM uint8_t  RESERVED[34];
+    __IOM uint8_t RCR1;                /*!< (@ 0x00000022) Reset Control Register 1                                   */
+    __IM uint8_t  RESERVED1;
 
     union
     {
@@ -8333,8 +8787,18 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } IICCKDIVCR_b;
         };
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint16_t RESERVED21;
+
+    union
+    {
+        __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
+
+        struct
+        {
+            __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
+            uint8_t                : 5;
+        } I3CCKDIVCR_b;
+    };
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -8461,8 +8925,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
         } I3CCKCR_b;
     };
-    __IM uint16_t RESERVED22;
-    __IM uint32_t RESERVED23[3];
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
 
     union
     {
@@ -8476,8 +8940,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                 : 29;
         } SNZREQCR1_b;
     };
-    __IM uint32_t RESERVED24;
-    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -8492,7 +8956,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
         } SNZCR_b;
     };
-    __IM uint8_t RESERVED26;
+    __IM uint8_t RESERVED25;
 
     union
     {
@@ -8522,7 +8986,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } SNZEDCR1_b;
     };
-    __IM uint16_t RESERVED27;
+    __IM uint16_t RESERVED26;
 
     union
     {
@@ -8565,7 +9029,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 1;
         } SNZREQCR_b;
     };
-    __IM uint16_t RESERVED28;
+    __IM uint16_t RESERVED27;
 
     union
     {
@@ -8603,7 +9067,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 3;
         } OPCCR_b;
     };
-    __IM uint8_t RESERVED29;
+    __IM uint8_t RESERVED28;
 
     union
     {
@@ -8615,7 +9079,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } MOSCWTCR_b;
     };
-    __IM uint8_t RESERVED30[2];
+    __IM uint8_t RESERVED29[2];
 
     union
     {
@@ -8628,7 +9092,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t : 5;
         } HOCOWTCR_b;
     };
-    __IM uint16_t RESERVED31[2];
+    __IM uint16_t RESERVED30[2];
 
     union
     {
@@ -8642,8 +9106,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 3;
         } SOPCCR_b;
     };
-    __IM uint8_t  RESERVED32;
-    __IM uint32_t RESERVED33[5];
+    __IM uint8_t  RESERVED31;
+    __IM uint32_t RESERVED32[5];
 
     union
     {
@@ -8677,8 +9141,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
         } RSTSR1_b;
     };
-    __IM uint16_t RESERVED34;
-    __IM uint32_t RESERVED35[3];
+    __IM uint16_t RESERVED33;
+    __IM uint32_t RESERVED34[3];
 
     union
     {
@@ -8704,8 +9168,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
         } SDADCCKCR_b;
     };
-    __IM uint16_t RESERVED36;
-    __IM uint32_t RESERVED37[3];
+    __IM uint16_t RESERVED35;
+    __IM uint32_t RESERVED36[3];
 
     union
     {
@@ -8760,7 +9224,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t          : 6;
         } LVD2SR_b;
     };
-    __IM uint32_t RESERVED38[183];
+    __IM uint32_t RESERVED37[183];
 
     union
     {
@@ -8788,7 +9252,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 14;
         } CGFSAR_b;
     };
-    __IM uint32_t RESERVED39;
+    __IM uint32_t RESERVED38;
 
     union
     {
@@ -8857,7 +9321,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 8;
         } BBFSAR_b;
     };
-    __IM uint32_t RESERVED40[3];
+    __IM uint32_t RESERVED39[3];
 
     union
     {
@@ -8919,8 +9383,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 4;
         } DPFSAR_b;
     };
-    __IM uint32_t RESERVED41[6];
-    __IM uint16_t RESERVED42;
+    __IM uint32_t RESERVED40[6];
+    __IM uint16_t RESERVED41;
 
     union
     {
@@ -9138,7 +9602,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 3;
         } DPSIEGR2_b;
     };
-    __IM uint8_t RESERVED43;
+    __IM uint8_t RESERVED42;
 
     union
     {
@@ -9196,7 +9660,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } RSTSR2_b;
     };
-    __IM uint8_t RESERVED44;
+    __IM uint8_t RESERVED43;
 
     union
     {
@@ -9213,7 +9677,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                           *   Enable                                                                    */
         } MOMCR_b;
     };
-    __IM uint16_t RESERVED45;
+    __IM uint16_t RESERVED44;
 
     union
     {
@@ -9283,7 +9747,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } LVD2CMPCR_b;
         };
     };
-    __IM uint8_t RESERVED46;
+    __IM uint8_t RESERVED45;
 
     union
     {
@@ -9316,7 +9780,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
         } LVD2CR0_b;
     };
-    __IM uint8_t RESERVED47;
+    __IM uint8_t RESERVED46;
 
     union
     {
@@ -9351,7 +9815,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 7;
         } VBTCR1_b;
     };
-    __IM uint32_t RESERVED48[8];
+    __IM uint32_t RESERVED47[8];
 
     union
     {
@@ -9394,7 +9858,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 6;
         } VCCSEL_b;
     };
-    __IM uint16_t RESERVED49;
+    __IM uint16_t RESERVED48;
 
     union
     {
@@ -9406,9 +9870,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } PL2LDOSCR_b;
     };
-    __IM uint8_t  RESERVED50;
-    __IM uint16_t RESERVED51;
-    __IM uint32_t RESERVED52[14];
+    __IM uint8_t  RESERVED49;
+    __IM uint16_t RESERVED50;
+    __IM uint32_t RESERVED51[14];
 
     union
     {
@@ -9431,8 +9895,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 6;
         } SOMCR_b;
     };
-    __IM uint16_t RESERVED53;
-    __IM uint32_t RESERVED54[3];
+    __IM uint16_t RESERVED52;
+    __IM uint32_t RESERVED53[3];
 
     union
     {
@@ -9444,7 +9908,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 7;
         } LOCOCR_b;
     };
-    __IM uint8_t RESERVED55;
+    __IM uint8_t RESERVED54;
 
     union
     {
@@ -9459,8 +9923,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                          *   trimming bits                                                             */
         } LOCOUTCR_b;
     };
-    __IM uint8_t  RESERVED56;
-    __IM uint32_t RESERVED57[7];
+    __IM uint8_t  RESERVED55;
+    __IM uint32_t RESERVED56[7];
 
     union
     {
@@ -9499,7 +9963,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 7;
         } VBTCMPCR_b;
     };
-    __IM uint8_t RESERVED58;
+    __IM uint8_t RESERVED57;
 
     union
     {
@@ -9513,7 +9977,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                  : 6;
         } VBTLVDICR_b;
     };
-    __IM uint8_t RESERVED59;
+    __IM uint8_t RESERVED58;
 
     union
     {
@@ -9525,7 +9989,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } VBTWCTLR_b;
     };
-    __IM uint8_t RESERVED60;
+    __IM uint8_t RESERVED59;
 
     union
     {
@@ -9660,9 +10124,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } VBTBER_b;
     };
-    __IM uint8_t  RESERVED61;
-    __IM uint16_t RESERVED62;
-    __IM uint32_t RESERVED63[15];
+    __IM uint8_t  RESERVED60;
+    __IM uint16_t RESERVED61;
+    __IM uint32_t RESERVED62[15];
 
     union
     {
@@ -9800,6 +10264,23 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
     __IM uint16_t RESERVED3;
 } R_WDT_Type;                          /*!< Size = 12 (0xc)                                                           */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
+ */
+
+typedef struct                          /*!< (@ 0x40084000) R_AGTX0 Structure                                          */
+{
+    union
+    {
+        __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
+        __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
+    };
+} R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_peripherals */
 
 /* =========================================================================================================================== */
@@ -9818,12 +10299,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_ACMPHS5_BASE        0x40085500UL
  #define R_ADC0_BASE           0x4005C000UL
  #define R_ADC1_BASE           0x4005C200UL
- #define R_AGT0_BASE           0x40084000UL
- #define R_AGT1_BASE           0x40084100UL
- #define R_AGT2_BASE           0x40084200UL
- #define R_AGT3_BASE           0x40084300UL
- #define R_AGT4_BASE           0x40084400UL
- #define R_AGT5_BASE           0x40084500UL
  #define R_BUS_BASE            0x40003000UL
  #define R_CAC_BASE            0x40044600UL
  #define R_CAN0_BASE           0x40050000UL
@@ -9912,6 +10387,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_TSN_CAL_BASE        0x407FB17CUL
  #define R_TSN_CTRL_BASE       0x4005D000UL
  #define R_WDT_BASE            0x40044200UL
+ #define R_AGTX0_BASE          0x40084000UL
+ #define R_AGTX1_BASE          0x40084100UL
+ #define R_AGTX2_BASE          0x40084200UL
+ #define R_AGTX3_BASE          0x40084300UL
+ #define R_AGTX4_BASE          0x40084400UL
+ #define R_AGTX5_BASE          0x40084500UL
+ #define R_AGTX6_BASE          0x40084600UL
+ #define R_AGTX7_BASE          0x40084700UL
+ #define R_AGTX8_BASE          0x40084800UL
+ #define R_AGTX9_BASE          0x40084900UL
 
 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
 
@@ -9931,12 +10416,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_ACMPHS5        ((R_ACMPHS0_Type *) R_ACMPHS5_BASE)
  #define R_ADC0           ((R_ADC0_Type *) R_ADC0_BASE)
  #define R_ADC1           ((R_ADC0_Type *) R_ADC1_BASE)
- #define R_AGT0           ((R_AGT0_Type *) R_AGT0_BASE)
- #define R_AGT1           ((R_AGT0_Type *) R_AGT1_BASE)
- #define R_AGT2           ((R_AGT0_Type *) R_AGT2_BASE)
- #define R_AGT3           ((R_AGT0_Type *) R_AGT3_BASE)
- #define R_AGT4           ((R_AGT0_Type *) R_AGT4_BASE)
- #define R_AGT5           ((R_AGT0_Type *) R_AGT5_BASE)
  #define R_BUS            ((R_BUS_Type *) R_BUS_BASE)
  #define R_CAC            ((R_CAC_Type *) R_CAC_BASE)
  #define R_CAN0           ((R_CAN0_Type *) R_CAN0_BASE)
@@ -10025,6 +10504,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_TSN_CAL        ((R_TSN_CAL_Type *) R_TSN_CAL_BASE)
  #define R_TSN_CTRL       ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
  #define R_WDT            ((R_WDT_Type *) R_WDT_BASE)
+ #define R_AGTX0          ((R_AGTX0_Type *) R_AGTX0_BASE)
+ #define R_AGTX1          ((R_AGTX0_Type *) R_AGTX1_BASE)
+ #define R_AGTX2          ((R_AGTX0_Type *) R_AGTX2_BASE)
+ #define R_AGTX3          ((R_AGTX0_Type *) R_AGTX3_BASE)
+ #define R_AGTX4          ((R_AGTX0_Type *) R_AGTX4_BASE)
+ #define R_AGTX5          ((R_AGTX0_Type *) R_AGTX5_BASE)
+ #define R_AGTX6          ((R_AGTX0_Type *) R_AGTX6_BASE)
+ #define R_AGTX7          ((R_AGTX0_Type *) R_AGTX7_BASE)
+ #define R_AGTX8          ((R_AGTX0_Type *) R_AGTX8_BASE)
+ #define R_AGTX9          ((R_AGTX0_Type *) R_AGTX9_BASE)
 
 /** @} */ /* End of group Device_Peripheral_declaration */
 
@@ -10387,6 +10876,101 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 
 /* =========================================================  PMSAR  ========================================================= */
 
+/* =========================================================================================================================== */
+/* ================                                           CTRL                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  AGTCR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AGTMR1  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
+/* ========================================================  AGTMR2  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
+/* =====================================================  AGTIOSEL_ALT  ====================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+/* ========================================================  AGTIOC  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AGTISR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AGTCMSR  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
+/* =======================================================  AGTIOSEL  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT16                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT32                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
+
 /** @} */ /* End of group PosMask_clusters */
 
 /* =========================================================================================================================== */
@@ -10920,77 +11504,6 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_ADC0_ADREFMON_MONSEL_Pos         (16UL)      /*!< MONSEL (Bit 16)                                       */
  #define R_ADC0_ADREFMON_MONSEL_Msk         (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f)                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGT0                                           ================ */
-/* =========================================================================================================================== */
-
-/* ==========================================================  AGT  ========================================================== */
- #define R_AGT0_AGT_AGT_Pos           (0UL)      /*!< AGT (Bit 0)                                           */
- #define R_AGT0_AGT_AGT_Msk           (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
-/* ========================================================  AGTCMA  ========================================================= */
- #define R_AGT0_AGTCMA_AGTCMA_Pos     (0UL)      /*!< AGTCMA (Bit 0)                                        */
- #define R_AGT0_AGTCMA_AGTCMA_Msk     (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
-/* ========================================================  AGTCMB  ========================================================= */
- #define R_AGT0_AGTCMB_AGTCMB_Pos     (0UL)      /*!< AGTCMB (Bit 0)                                        */
- #define R_AGT0_AGTCMB_AGTCMB_Msk     (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
-/* =========================================================  AGTCR  ========================================================= */
- #define R_AGT0_AGTCR_TCMBF_Pos       (7UL)      /*!< TCMBF (Bit 7)                                         */
- #define R_AGT0_AGTCR_TCMBF_Msk       (0x80UL)   /*!< TCMBF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCMAF_Pos       (6UL)      /*!< TCMAF (Bit 6)                                         */
- #define R_AGT0_AGTCR_TCMAF_Msk       (0x40UL)   /*!< TCMAF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TUNDF_Pos       (5UL)      /*!< TUNDF (Bit 5)                                         */
- #define R_AGT0_AGTCR_TUNDF_Msk       (0x20UL)   /*!< TUNDF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TEDGF_Pos       (4UL)      /*!< TEDGF (Bit 4)                                         */
- #define R_AGT0_AGTCR_TEDGF_Msk       (0x10UL)   /*!< TEDGF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTOP_Pos       (2UL)      /*!< TSTOP (Bit 2)                                         */
- #define R_AGT0_AGTCR_TSTOP_Msk       (0x4UL)    /*!< TSTOP (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TCSTF_Pos       (1UL)      /*!< TCSTF (Bit 1)                                         */
- #define R_AGT0_AGTCR_TCSTF_Msk       (0x2UL)    /*!< TCSTF (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCR_TSTART_Pos      (0UL)      /*!< TSTART (Bit 0)                                        */
- #define R_AGT0_AGTCR_TSTART_Msk      (0x1UL)    /*!< TSTART (Bitfield-Mask: 0x01)                          */
-/* ========================================================  AGTMR1  ========================================================= */
- #define R_AGT0_AGTMR1_TCK_Pos        (4UL)      /*!< TCK (Bit 4)                                           */
- #define R_AGT0_AGTMR1_TCK_Msk        (0x70UL)   /*!< TCK (Bitfield-Mask: 0x07)                             */
- #define R_AGT0_AGTMR1_TEDGPL_Pos     (3UL)      /*!< TEDGPL (Bit 3)                                        */
- #define R_AGT0_AGTMR1_TEDGPL_Msk     (0x8UL)    /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTMR1_TMOD_Pos       (0UL)      /*!< TMOD (Bit 0)                                          */
- #define R_AGT0_AGTMR1_TMOD_Msk       (0x7UL)    /*!< TMOD (Bitfield-Mask: 0x07)                            */
-/* ========================================================  AGTMR2  ========================================================= */
- #define R_AGT0_AGTMR2_LPM_Pos        (7UL)      /*!< LPM (Bit 7)                                           */
- #define R_AGT0_AGTMR2_LPM_Msk        (0x80UL)   /*!< LPM (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTMR2_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
- #define R_AGT0_AGTMR2_CKS_Msk        (0x7UL)    /*!< CKS (Bitfield-Mask: 0x07)                             */
-/* ========================================================  AGTIOC  ========================================================= */
- #define R_AGT0_AGTIOC_TIOGT_Pos      (6UL)      /*!< TIOGT (Bit 6)                                         */
- #define R_AGT0_AGTIOC_TIOGT_Msk      (0xc0UL)   /*!< TIOGT (Bitfield-Mask: 0x03)                           */
- #define R_AGT0_AGTIOC_TIPF_Pos       (4UL)      /*!< TIPF (Bit 4)                                          */
- #define R_AGT0_AGTIOC_TIPF_Msk       (0x30UL)   /*!< TIPF (Bitfield-Mask: 0x03)                            */
- #define R_AGT0_AGTIOC_TOE_Pos        (2UL)      /*!< TOE (Bit 2)                                           */
- #define R_AGT0_AGTIOC_TOE_Msk        (0x4UL)    /*!< TOE (Bitfield-Mask: 0x01)                             */
- #define R_AGT0_AGTIOC_TEDGSEL_Pos    (0UL)      /*!< TEDGSEL (Bit 0)                                       */
- #define R_AGT0_AGTIOC_TEDGSEL_Msk    (0x1UL)    /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
-/* ========================================================  AGTISR  ========================================================= */
- #define R_AGT0_AGTISR_EEPS_Pos       (2UL)      /*!< EEPS (Bit 2)                                          */
- #define R_AGT0_AGTISR_EEPS_Msk       (0x4UL)    /*!< EEPS (Bitfield-Mask: 0x01)                            */
-/* ========================================================  AGTCMSR  ======================================================== */
- #define R_AGT0_AGTCMSR_TOPOLB_Pos    (6UL)      /*!< TOPOLB (Bit 6)                                        */
- #define R_AGT0_AGTCMSR_TOPOLB_Msk    (0x40UL)   /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEB_Pos      (5UL)      /*!< TOEB (Bit 5)                                          */
- #define R_AGT0_AGTCMSR_TOEB_Msk      (0x20UL)   /*!< TOEB (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEB_Pos     (4UL)      /*!< TCMEB (Bit 4)                                         */
- #define R_AGT0_AGTCMSR_TCMEB_Msk     (0x10UL)   /*!< TCMEB (Bitfield-Mask: 0x01)                           */
- #define R_AGT0_AGTCMSR_TOPOLA_Pos    (2UL)      /*!< TOPOLA (Bit 2)                                        */
- #define R_AGT0_AGTCMSR_TOPOLA_Msk    (0x4UL)    /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
- #define R_AGT0_AGTCMSR_TOEA_Pos      (1UL)      /*!< TOEA (Bit 1)                                          */
- #define R_AGT0_AGTCMSR_TOEA_Msk      (0x2UL)    /*!< TOEA (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTCMSR_TCMEA_Pos     (0UL)      /*!< TCMEA (Bit 0)                                         */
- #define R_AGT0_AGTCMSR_TCMEA_Msk     (0x1UL)    /*!< TCMEA (Bitfield-Mask: 0x01)                           */
-/* =======================================================  AGTIOSEL  ======================================================== */
- #define R_AGT0_AGTIOSEL_TIES_Pos     (4UL)      /*!< TIES (Bit 4)                                          */
- #define R_AGT0_AGTIOSEL_TIES_Msk     (0x10UL)   /*!< TIES (Bitfield-Mask: 0x01)                            */
- #define R_AGT0_AGTIOSEL_SEL_Pos      (0UL)      /*!< SEL (Bit 0)                                           */
- #define R_AGT0_AGTIOSEL_SEL_Msk      (0x3UL)    /*!< SEL (Bitfield-Mask: 0x03)                             */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -12114,10 +12627,22 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
 /* =========================================================  GTCR  ========================================================== */
+ #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
+ #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTCR_TPCS_Pos              (24UL)         /*!< TPCS (Bit 24)                                         */
  #define R_GPT0_GTCR_TPCS_Msk              (0x7000000UL)  /*!< TPCS (Bitfield-Mask: 0x07)                            */
  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
- #define R_GPT0_GTCR_MD_Msk                (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
+ #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
+ #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
+ #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
+ #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
 /* =======================================================  GTUDDTYC  ======================================================== */
@@ -12175,6 +12700,8 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
 /* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
+ #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
@@ -12183,8 +12710,16 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
- #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
- #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
+ #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
+ #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
+ #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
 /* =========================================================  GTST  ========================================================== */
  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
@@ -12241,6 +12776,8 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
+ #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
@@ -12330,6 +12867,67 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 /* ========================================================  GTSOTR  ========================================================= */
  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
 /* ========================================================  GTICLF  ========================================================= */
  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
@@ -12372,14 +12970,113 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
+ #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
+ #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTBER2  ========================================================= */
+ #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
+ #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
+ #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
+ #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
+ #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
+ #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
+ #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
+ #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
+ #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
+ #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
+ #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
+ #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
+ #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
+ #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
+ #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
+ #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
+ #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
+ #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
+ #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
+ #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTOLBR  ========================================================= */
+ #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
+ #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
+ #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
+ #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  GTICCR  ========================================================= */
+ #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
+ #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
+ #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
+ #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
+ #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
+ #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
+ #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
+ #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
+ #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
+ #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
+ #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
+ #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
+ #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
+ #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
+ #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
+ #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
+ #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
+ #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
+ #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
+ #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
+ #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
 
 /* =========================================================================================================================== */
 /* ================                                         R_GPT_ODC                                         ================ */
@@ -14498,6 +15195,9 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
 /* ======================================================  CECCKDIVCR  ======================================================= */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  I3CCKDIVCR  ======================================================= */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
 /* ======================================================  IICCKDIVCR  ======================================================= */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
@@ -14757,6 +15457,10 @@ typedef struct                         /*!< (@ 0x40044200) R_WDT Structure
  #define R_WDT_WDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
  #define R_WDT_WDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
 /** @} */ /* End of group PosMask_peripherals */
 
  #ifdef __cplusplus
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h
index 78735ea4d..f43482153 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h
@@ -1237,11 +1237,11 @@ typedef struct
                 __IOM uint32_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
                 uint32_t             : 1;
                 __IOM uint32_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
-                __IOM uint32_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
+                uint32_t             : 1;
                 __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
                 uint32_t             : 3;
                 __IOM uint32_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
-                __IOM uint32_t EOFR  : 2; /*!< [13..12] Event on Falling/Rising                                          */
+                __IOM uint32_t EOFR  : 2; /*!< [13..12] Event on Falling/Event on Rising.                                */
                 __IOM uint32_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
                 __IOM uint32_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
                 __IOM uint32_t PMR   : 1; /*!< [16..16] Port Mode Control                                                */
@@ -1252,59 +1252,42 @@ typedef struct
             } PmnPFS_b;
         };
 
-        struct
+        union
         {
-            union
+            __IOM uint16_t PmnPFS_HA;     /*!< (@ 0x00000000) Pin Function Control Register                              */
+
+            struct
             {
-                struct
-                {
-                    __IM uint16_t RESERVED;
-
-                    union
-                    {
-                        __IOM uint16_t PmnPFS_HA;     /*!< (@ 0x00000002) Pin Function Control Register                              */
-
-                        struct
-                        {
-                            __IOM uint16_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
-                            __IM uint16_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
-                            __IOM uint16_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
-                            uint16_t             : 1;
-                            __IOM uint16_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
-                            __IOM uint16_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
-                            __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
-                            uint16_t             : 3;
-                            __IOM uint16_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
-                            __IOM uint16_t EOFR  : 2; /*!< [13..12] Event on Falling/Rising                                          */
-                            __IOM uint16_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
-                            __IOM uint16_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
-                        } PmnPFS_HA_b;
-                    };
-                };
+                __IOM uint16_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
+                __IM uint16_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
+                __IOM uint16_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
+                uint16_t             : 1;
+                __IOM uint16_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
+                uint16_t             : 1;
+                __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
+                uint16_t             : 3;
+                __IOM uint16_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
+                __IOM uint16_t EOFR  : 2; /*!< [13..12] Event on Falling/Event on Rising.                                */
+                __IOM uint16_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
+                __IOM uint16_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
+            } PmnPFS_HA_b;
+        };
 
-                struct
-                {
-                    __IM uint16_t RESERVED1;
-                    __IM uint8_t  RESERVED2;
-
-                    union
-                    {
-                        __IOM uint8_t PmnPFS_BY;     /*!< (@ 0x00000003) Pin Function Control Register                              */
-
-                        struct
-                        {
-                            __IOM uint8_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
-                            __IM uint8_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
-                            __IOM uint8_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
-                            uint8_t             : 1;
-                            __IOM uint8_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
-                            __IOM uint8_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
-                            __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
-                            uint8_t             : 1;
-                        } PmnPFS_BY_b;
-                    };
-                };
-            };
+        union
+        {
+            __IOM uint8_t PmnPFS_BY;     /*!< (@ 0x00000000) Pin Function Control Register                              */
+
+            struct
+            {
+                __IOM uint8_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
+                __IM uint8_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
+                __IOM uint8_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
+                uint8_t             : 1;
+                __IOM uint8_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
+                uint8_t             : 1;
+                __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
+                uint8_t             : 1;
+            } PmnPFS_BY_b;
         };
     };
 } R_PFS_PORT_PIN_Type;                 /*!< Size = 4 (0x4)                                                            */
@@ -1317,25 +1300,6 @@ typedef struct
     __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects                                       */
 } R_PFS_PORT_Type;                     /*!< Size = 64 (0x40)                                                          */
 
-/**
- * @brief R_PFS_VLSEL [VLSEL] (VLSEL)
- */
-typedef struct
-{
-    __IM uint8_t RESERVED[389];
-
-    union
-    {
-        __IOM uint8_t VL1SEL;          /*!< (@ 0x00000185) VL1 Select Control Register                                */
-
-        struct
-        {
-            __IOM uint8_t SELVL : 1;   /*!< [0..0] VL1 Voltage Connection Switching Control                           */
-            uint8_t             : 7;
-        } VL1SEL_b;
-    };
-} R_PFS_VLSEL_Type;                    /*!< Size = 390 (0x186)                                                        */
-
 /**
  * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register)
  */
@@ -1518,6 +1482,213 @@ typedef struct
     __IM uint32_t RESERVED2[2];
 } R_BUS_B_BUSTZFERR_Type;              /*!< Size = 16 (0x10)                                                          */
 
+/**
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
+            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
+            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
+            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
+            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
+            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
+        } AGTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
+            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
+            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
+            uint8_t              : 1;
+        } AGTMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+                                        *   ratio                                                                     */
+            uint8_t           : 4;
+            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
+        } AGTMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_ALT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+                                        *   mode.                                                                     */
+            uint8_t             : 1;
+            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
+            uint8_t             : 1;
+            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
+            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
+        } AGTIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
+            uint8_t            : 5;
+        } AGTISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
+
+        struct
+        {
+            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
+            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
+            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
+            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
+            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
+            uint8_t              : 1;
+        } AGTCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
+
+        struct
+        {
+            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
+            uint8_t            : 2;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_b;
+    };
+} R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
+
+        struct
+        {
+            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IM uint16_t                 RESERVED;
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
+} R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
+
+        struct
+        {
+            __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
+                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
+                                        *   counter is forcibly stopped and set to FFFFH.                             */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
+} R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
+
 /** @} */ /* End of group Device_Peripheral_clusters */
 
 /* =========================================================================================================================== */
@@ -1885,16 +2056,17 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
 
     union
     {
-        __IM uint16_t ADDR[28];        /*!< (@ 0x00000020) A/D Data Register                                          */
+        __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
 
         struct
         {
             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
                                         *   storing the result of A/D conversion.                                     */
-        } ADDR_b[28];
+        } ADDR_b[29];
     };
-    __IM uint32_t RESERVED1[2];
-    __IM uint16_t RESERVED2;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+    __IM uint16_t RESERVED3;
 
     union
     {
@@ -2087,7 +2259,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint16_t                : 3;
         } ADSWTSTR2_b;
     };
-    __IM uint16_t RESERVED3;
+    __IM uint16_t RESERVED4;
 
     union
     {
@@ -2149,7 +2321,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 6;
         } ADACSR_b;
     };
-    __IM uint8_t RESERVED4;
+    __IM uint8_t RESERVED5;
 
     union
     {
@@ -2219,7 +2391,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
         } ADSER_b;
     };
-    __IM uint8_t RESERVED5;
+    __IM uint8_t RESERVED6;
 
     union
     {
@@ -2235,7 +2407,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
         } ADHVREFCNT_b;
     };
-    __IM uint8_t RESERVED6;
+    __IM uint8_t RESERVED7;
 
     union
     {
@@ -2253,8 +2425,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t              : 2;
         } ADWINMON_b;
     };
-    __IM uint8_t  RESERVED7;
-    __IM uint16_t RESERVED8;
+    __IM uint8_t  RESERVED8;
+    __IM uint16_t RESERVED9;
 
     union
     {
@@ -2430,7 +2602,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 6;
         } ADCMPSER_b;
     };
-    __IM uint8_t RESERVED9;
+    __IM uint8_t RESERVED10;
 
     union
     {
@@ -2445,7 +2617,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
         } ADCMPBNSR_b;
     };
-    __IM uint8_t RESERVED10;
+    __IM uint8_t RESERVED11;
 
     union
     {
@@ -2484,8 +2656,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 7;
         } ADCMPBSR_b;
     };
-    __IM uint8_t  RESERVED11;
-    __IM uint16_t RESERVED12;
+    __IM uint8_t  RESERVED12;
+    __IM uint16_t RESERVED13;
 
     union
     {
@@ -2689,7 +2861,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 7;
         } ADBUFEN_b;
     };
-    __IM uint8_t RESERVED13;
+    __IM uint8_t RESERVED14;
 
     union
     {
@@ -2703,9 +2875,9 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 3;
         } ADBUFPTR_b;
     };
-    __IM uint8_t  RESERVED14;
-    __IM uint32_t RESERVED15[2];
-    __IM uint8_t  RESERVED16;
+    __IM uint8_t  RESERVED15;
+    __IM uint32_t RESERVED16[2];
+    __IM uint8_t  RESERVED17;
 
     union
     {
@@ -2772,7 +2944,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
         } ADCALEXE_b;
     };
-    __IM uint8_t RESERVED17;
+    __IM uint8_t RESERVED18;
 
     union
     {
@@ -2789,8 +2961,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
         } VREFAMPCNT_b;
     };
-    __IM uint8_t  RESERVED18;
-    __IM uint16_t RESERVED19;
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -2812,8 +2984,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t             : 6;
         } ADRST_b;
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint32_t RESERVED21[41];
+    __IM uint8_t  RESERVED21;
+    __IM uint32_t RESERVED22[41];
 
     union
     {
@@ -2871,7 +3043,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
         } ADPGAGS0_b;
     };
-    __IM uint32_t RESERVED22[3];
+    __IM uint32_t RESERVED23[3];
 
     union
     {
@@ -2898,7 +3070,7 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
         } ADPGADCR0_b;
     };
-    __IM uint16_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -2927,8 +3099,8 @@ typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure
             uint8_t : 7;
         } ADPGADBS1_b;
     };
-    __IM uint16_t RESERVED24;
-    __IM uint32_t RESERVED25[10];
+    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED26[10];
 
     union
     {
@@ -3063,254 +3235,106 @@ typedef struct                         /*!< (@ 0x400E0000) R_PSCU Structure
             __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution            */
             __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution            */
             uint32_t               : 6;
-            __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution            */
-            __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution            */
-            __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution            */
-            __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution            */
-            __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution            */
-            __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution            */
-            __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution            */
-            __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution            */
-            __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution            */
-            __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution            */
-        } PSARE_b;
-    };
-
-    union
-    {
-        __IOM uint32_t MSSAR;          /*!< (@ 0x00000014) Module Stop Security Attribution Register                  */
-
-        struct
-        {
-            __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution                       */
-            __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution                       */
-            __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution                        */
-            __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution                        */
-            uint32_t              : 28;
-        } MSSAR_b;
-    };
-
-    union
-    {
-        __IM uint32_t CFSAMONA;        /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
-                                        *                  A                                                          */
-
-        struct
-        {
-            uint32_t           : 15;
-            __IM uint32_t CFS2 : 9;    /*!< [23..15] Code Flash Secure area 2                                         */
-            uint32_t           : 8;
-        } CFSAMONA_b;
-    };
-
-    union
-    {
-        __IM uint32_t CFSAMONB;        /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
-                                        *                  B                                                          */
-
-        struct
-        {
-            uint32_t           : 10;
-            __IM uint32_t CFS1 : 14;   /*!< [23..10] Code Flash Secure area 1                                         */
-            uint32_t           : 8;
-        } CFSAMONB_b;
-    };
-
-    union
-    {
-        __IM uint32_t DFSAMON;         /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register           */
-
-        struct
-        {
-            uint32_t          : 10;
-            __IM uint32_t DFS : 6;     /*!< [15..10] Data flash Secure area                                           */
-            uint32_t          : 16;
-        } DFSAMON_b;
-    };
-
-    union
-    {
-        __IM uint32_t SSAMONA;         /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A               */
-
-        struct
-        {
-            uint32_t          : 13;
-            __IM uint32_t SS2 : 8;     /*!< [20..13] SRAM Secure area 2                                               */
-            uint32_t          : 11;
-        } SSAMONA_b;
-    };
-
-    union
-    {
-        __IM uint32_t SSAMONB;         /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B               */
-
-        struct
-        {
-            uint32_t          : 10;
-            __IM uint32_t SS1 : 11;    /*!< [20..10] SRAM secure area 1                                               */
-            uint32_t          : 11;
-        } SSAMONB_b;
-    };
-
-    union
-    {
-        __IM uint32_t DLMMON;          /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register         */
-
-        struct
-        {
-            __IM uint32_t DLMMON : 4;  /*!< [3..0] Device Lifecycle Management State Monitor                          */
-            uint32_t             : 28;
-        } DLMMON_b;
-    };
-} R_PSCU_Type;                         /*!< Size = 48 (0x30)                                                          */
-
-/* =========================================================================================================================== */
-/* ================                                          R_AGTW0                                          ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief Asynchronous General Purpose Timer (R_AGTW0)
- */
-
-typedef struct                         /*!< (@ 0x400E8000) R_AGTW0 Structure                                          */
-{
-    union
-    {
-        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
-
-        struct
-        {
-            __IOM uint32_t AGT : 32;   /*!< [31..0] 16bit counter and reload registerNOTE : When 1 is written
-                                        *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
-                                        *   is forcibly stopped and set to FFFFH.                                     */
-        } AGT_b;
-    };
-
-    union
-    {
-        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
-
-        struct
-        {
-            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCRn register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMA_b;
-    };
-
-    union
-    {
-        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
-
-        struct
-        {
-            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCR register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMB_b;
+            __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution            */
+            __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution            */
+            __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution            */
+            __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution            */
+            __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution            */
+            __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution            */
+            __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution            */
+            __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution            */
+            __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution            */
+            __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution            */
+        } PSARE_b;
     };
 
     union
     {
-        __IOM uint8_t AGTCR;           /*!< (@ 0x0000000C) AGT Control Register                                       */
+        __IOM uint32_t MSSAR;          /*!< (@ 0x00000014) Module Stop Security Attribution Register                  */
 
         struct
         {
-            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
-            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
-            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
-            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
-            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
-            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
-        } AGTCR_b;
+            __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution                       */
+            __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution                       */
+            __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution                        */
+            __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution                        */
+            uint32_t              : 28;
+        } MSSAR_b;
     };
 
     union
     {
-        __IOM uint8_t AGTMR1;          /*!< (@ 0x0000000D) AGT Mode Register 1                                        */
+        __IOM uint32_t CFSAMONA;       /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
+                                        *                  A                                                          */
 
         struct
         {
-            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
-            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
-            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
-            uint8_t              : 1;
-        } AGTMR1_b;
+            uint32_t            : 15;
+            __IOM uint32_t CFS2 : 9;   /*!< [23..15] Code Flash Secure area 2                                         */
+            uint32_t            : 8;
+        } CFSAMONA_b;
     };
 
     union
     {
-        __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000E) AGT Mode Register 2                                        */
+        __IOM uint32_t CFSAMONB;       /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
+                                        *                  B                                                          */
 
         struct
         {
-            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
-                                        *   ratio                                                                     */
-            uint8_t           : 4;
-            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
-        } AGTMR2_b;
+            uint32_t            : 10;
+            __IOM uint32_t CFS1 : 14;  /*!< [23..10] Code Flash Secure area 1                                         */
+            uint32_t            : 8;
+        } CFSAMONB_b;
     };
-    __IM uint8_t RESERVED;
 
     union
     {
-        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000010) AGT I/O Control Register                                   */
+        __IOM uint32_t DFSAMON;        /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register           */
 
         struct
         {
-            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
-                                        *   mode.                                                                     */
-            uint8_t             : 1;
-            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
-            uint8_t             : 1;
-            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
-            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
-        } AGTIOC_b;
+            uint32_t           : 10;
+            __IOM uint32_t DFS : 6;    /*!< [15..10] Data flash Secure area                                           */
+            uint32_t           : 16;
+        } DFSAMON_b;
     };
 
     union
     {
-        __IOM uint8_t AGTISR;          /*!< (@ 0x00000011) AGT Event Pin Select Register                              */
+        __IOM uint32_t SSAMONA;        /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A               */
 
         struct
         {
-            uint8_t            : 2;
-            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
-            uint8_t            : 5;
-        } AGTISR_b;
+            uint32_t           : 13;
+            __IOM uint32_t SS2 : 8;    /*!< [20..13] SRAM Secure area 2                                               */
+            uint32_t           : 11;
+        } SSAMONA_b;
     };
 
     union
     {
-        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000012) AGT Compare Match Function Select Register                 */
+        __IOM uint32_t SSAMONB;        /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B               */
 
         struct
         {
-            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
-            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
-            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
-            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
-            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
-            uint8_t              : 1;
-        } AGTCMSR_b;
+            uint32_t           : 10;
+            __IOM uint32_t SS1 : 11;   /*!< [20..10] SRAM secure area 1                                               */
+            uint32_t           : 11;
+        } SSAMONB_b;
     };
 
     union
     {
-        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000013) AGT Pin Select Register                                    */
+        __IM uint32_t DLMMON;          /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register         */
 
         struct
         {
-            uint8_t            : 4;
-            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
-            uint8_t            : 3;
-        } AGTIOSEL_b;
+            __IM uint32_t DLMMON : 4;  /*!< [3..0] Device Lifecycle Management State Monitor                          */
+            uint32_t             : 28;
+        } DLMMON_b;
     };
-} R_AGTW0_Type;                        /*!< Size = 20 (0x14)                                                          */
+} R_PSCU_Type;                         /*!< Size = 48 (0x30)                                                          */
 
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
@@ -5315,7 +5339,60 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                          *   means counter running.                                                    */
-            uint32_t : 18;
+            __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
         } GTSTR_b;
     };
 
@@ -5367,7 +5444,60 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
                                          *   1 means counter stop.                                                     */
-            uint32_t : 18;
+            __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
         } GTSTP_b;
     };
 
@@ -5391,7 +5521,24 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
-            uint32_t             : 18;
+            __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
         } GTCLR_b;
     };
 
@@ -5712,16 +5859,23 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+        __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
 
         struct
         {
-            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
-            uint32_t            : 15;
-            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
-            uint32_t            : 4;
-            __IOM uint32_t TPCS : 4;   /*!< [26..23] Timer Prescaler Select                                           */
-            uint32_t            : 5;
+            __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
+            uint32_t               : 7;
+            __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
+            __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
+            __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
+            __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
+            uint32_t               : 2;
+            __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
+            __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
+            uint32_t               : 3;
+            __IOM uint32_t TPCS    : 4; /*!< [26..23] Timer Prescaler Select                                           */
+            __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
+            uint32_t               : 3;
         } GTCR_b;
     };
 
@@ -5792,13 +5946,36 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
         struct
         {
-            uint32_t               : 24;
-            __IOM uint32_t GRP     : 2; /*!< [25..24] Output Disable Source Select                                     */
+            uint32_t            : 8;
+            __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
+                                          *   Clear Enable                                                              */
+            __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
+                                          *   Synchronous Clear Enable                                                  */
+            __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
+            __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
+            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
+                                          *   Start Request Enable                                                      */
+            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
+                                          *   Conversion Start Request Enable                                           */
+            uint32_t               : 4;
+            __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
             uint32_t               : 2;
-            __IOM uint32_t GRPDTE  : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
-            __IOM uint32_t GRPABH  : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable               */
-            __IOM uint32_t GRPABL  : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
-            __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
+            __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
+            __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
         } GTINTAD_b;
     };
 
@@ -5841,32 +6018,36 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTBER;          /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
 
         struct
         {
-            __IOM uint32_t BD0    : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
-            __IOM uint32_t BD1    : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
-            __IOM uint32_t BD2    : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
-            __IOM uint32_t BD3    : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
-            uint32_t              : 12;
-            __IOM uint32_t CCRA   : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
-            __IOM uint32_t CCRB   : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
-            __IOM uint32_t PR     : 2; /*!< [21..20] GTPR Buffer Operation                                            */
-            __OM uint32_t  CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
-                                        *   is read as 0.                                                             */
+            __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
+            __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
+            __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
+            __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
+            uint32_t               : 4;
+            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
+            uint32_t               : 1;
+            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
+            uint32_t               : 5;
+            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
+            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
+            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
+            __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+                                         *   is read as 0.                                                             */
             uint32_t             : 1;
-            __IOM uint32_t ADTTA : 2;  /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDA : 1;  /*!< [26..26] GTADTRA Double Buffer Operation                                  */
+            __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
             uint32_t             : 1;
-            __IOM uint32_t ADTTB : 2;  /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
-                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
-                                        *   at an underflow (in down-counting) or overflow (in up-counting)
-                                        *   is performed.                                                             */
-            __IOM uint32_t ADTDB : 1;  /*!< [30..30] GTADTRB Double Buffer Operation                                  */
+            __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                         *   at an underflow (in down-counting) or overflow (in up-counting)
+                                         *   is performed.                                                             */
+            __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
             uint32_t             : 1;
         } GTBER_b;
     };
@@ -6090,7 +6271,126 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             uint32_t            : 31;
         } GTSOTR_b;
     };
-    __IM uint32_t RESERVED[5];
+
+    union
+    {
+        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
+                                         *                  Signal Monitoring Register                                 */
+
+        struct
+        {
+            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
+                                         *   Enabling                                                                  */
+            uint32_t               : 7;
+            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
+            uint32_t               : 6;
+            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
+                                         *   Enabling                                                                  */
+            uint32_t : 7;
+        } GTADSMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
+                                           *                  Counter Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
+            uint32_t               : 2;
+            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
+            uint32_t               : 4;
+            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
+            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
+                                           *   select                                                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
+            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
+            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
+        } GTEITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 1                                         */
+
+        struct
+        {
+            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
+                                        *   Extended Skipping Function Select                                         */
+            uint32_t             : 1;
+            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
+                                        *   Function Select                                                           */
+            uint32_t             : 1;
+            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
+            uint32_t             : 1;
+            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
+            uint32_t             : 1;
+        } GTEITLI1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
+                                        *                  Setting Register 2                                         */
+
+        struct
+        {
+            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t              : 1;
+            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
+                                        *   Skipping Function Select                                                  */
+            uint32_t : 25;
+        } GTEITLI2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
+                                         *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 5;
+            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
+                                         *   Function Select                                                           */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t               : 1;
+            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
+                                         *   Select                                                                    */
+            uint32_t : 1;
+        } GTEITLB_b;
+    };
 
     union
     {
@@ -6124,7 +6424,7 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
             uint32_t            : 4;
         } GTPC_b;
     };
-    __IM uint32_t RESERVED1[4];
+    __IM uint32_t RESERVED[4];
 
     union
     {
@@ -6159,24 +6459,144 @@ typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure
 
     union
     {
-        __IOM uint32_t GTSECR;         /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous
-                                        *                  Control Register                                           */
+        __IOM uint32_t GTSECR;         /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous
+                                        *                  Control Register                                           */
+
+        struct
+        {
+            __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
+            __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
+            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
+            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
+            uint32_t             : 4;
+            __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
+            __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
+            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
+            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
+            uint32_t             : 4;
+            __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
+            __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
+            uint32_t             : 6;
+            __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
+            __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
+            uint32_t             : 6;
+        } GTSECR_b;
+    };
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
+            __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
+                                        *   Disable                                                                   */
+            uint32_t             : 2;
+            __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
+                                        *   Enable                                                                    */
+            uint32_t             : 1;
+            __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
+                                        *   Disable                                                                   */
+            __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
+                                        *   Transfer Disable                                                          */
+            uint32_t             : 2;
+            __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
+            __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
+            __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
+            __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
+            uint32_t             : 2;
+        } GTBER2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
 
         struct
         {
-            __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
-            __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
-            uint32_t             : 6;
-            __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
-            __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
-            uint32_t             : 6;
-            __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
-            uint32_t             : 7;
-            __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
-            uint32_t             : 7;
-        } GTSECR_b;
+            __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
+            uint32_t              : 11;
+            __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
+            uint32_t              : 11;
+        } GTOLBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
+                                        *                  Capture Control Register                                   */
+
+        struct
+        {
+            __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
+            __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
+                                        *   Channel GTCCRA Input Capture Source Enable                                */
+            __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
+            __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
+                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
+            __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
+                                        *   Other Channel GTCCRb Input Capture Source Enable                          */
+            __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
+                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
+            __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
+                                        *   Source Enable                                                             */
+            __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
+                                        *   Capture Source Enable                                                     */
+            uint32_t              : 5;
+            __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
+        } GTICCR_b;
     };
-} R_GPT0_Type;                         /*!< Size = 216 (0xd8)                                                         */
+} R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
 
 /* =========================================================================================================================== */
 /* ================                                        R_GPT_GTCLK                                        ================ */
@@ -8518,7 +8938,7 @@ typedef struct                         /*!< (@ 0x4001F000) R_PORT0 Structure
 
             union
             {
-                __IOM uint16_t P0DR;           /*!< (@ 0x00000002) Output data register                                       */
+                __IOM uint16_t PODR;           /*!< (@ 0x00000002) Output data register                                       */
 
                 struct
                 {
@@ -8538,7 +8958,7 @@ typedef struct                         /*!< (@ 0x4001F000) R_PORT0 Structure
                     __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data                                                  */
                     __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data                                                  */
                     __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data                                                  */
-                } P0DR_b;
+                } PODR_b;
             };
         };
     };
@@ -8753,14 +9173,10 @@ typedef struct                         /*!< (@ 0x4001F000) R_PORT0 Structure
  * @brief I/O Ports-PFS (R_PFS)
  */
 
-typedef struct                           /*!< (@ 0x4001F800) R_PFS Structure                                            */
+typedef struct                         /*!< (@ 0x4001F800) R_PFS Structure                                            */
 {
-    union
-    {
-        __IOM R_PFS_PORT_Type  PORT[15]; /*!< (@ 0x00000000) Port [0..14]                                               */
-        __IOM R_PFS_VLSEL_Type VLSEL;    /*!< (@ 0x00000000) VLSEL                                                      */
-    };
-} R_PFS_Type;                            /*!< Size = 960 (0x3c0)                                                        */
+    __IOM R_PFS_PORT_Type PORT[15];    /*!< (@ 0x00000000) Port [0..14]                                               */
+} R_PFS_Type;                          /*!< Size = 960 (0x3c0)                                                        */
 
 /* =========================================================================================================================== */
 /* ================                                          R_PMISC                                          ================ */
@@ -10768,8 +11184,18 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } IICCKDIVCR_b;
         };
     };
-    __IM uint8_t  RESERVED20;
-    __IM uint16_t RESERVED21;
+
+    union
+    {
+        __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
+
+        struct
+        {
+            __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
+            uint8_t                : 5;
+        } I3CCKDIVCR_b;
+    };
+    __IM uint16_t RESERVED20;
 
     union
     {
@@ -10896,8 +11322,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
         } I3CCKCR_b;
     };
-    __IM uint16_t RESERVED22;
-    __IM uint32_t RESERVED23[3];
+    __IM uint16_t RESERVED21;
+    __IM uint32_t RESERVED22[3];
 
     union
     {
@@ -10911,8 +11337,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                 : 29;
         } SNZREQCR1_b;
     };
-    __IM uint32_t RESERVED24;
-    __IM uint16_t RESERVED25;
+    __IM uint32_t RESERVED23;
+    __IM uint16_t RESERVED24;
 
     union
     {
@@ -10927,7 +11353,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
         } SNZCR_b;
     };
-    __IM uint8_t RESERVED26;
+    __IM uint8_t RESERVED25;
 
     union
     {
@@ -10957,7 +11383,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } SNZEDCR1_b;
     };
-    __IM uint16_t RESERVED27;
+    __IM uint16_t RESERVED26;
 
     union
     {
@@ -11000,7 +11426,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 1;
         } SNZREQCR_b;
     };
-    __IM uint16_t RESERVED28;
+    __IM uint16_t RESERVED27;
 
     union
     {
@@ -11038,7 +11464,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 3;
         } OPCCR_b;
     };
-    __IM uint8_t RESERVED29;
+    __IM uint8_t RESERVED28;
 
     union
     {
@@ -11050,7 +11476,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } MOSCWTCR_b;
     };
-    __IM uint8_t RESERVED30[2];
+    __IM uint8_t RESERVED29[2];
 
     union
     {
@@ -11063,7 +11489,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t : 5;
         } HOCOWTCR_b;
     };
-    __IM uint16_t RESERVED31[2];
+    __IM uint16_t RESERVED30[2];
 
     union
     {
@@ -11077,8 +11503,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 3;
         } SOPCCR_b;
     };
-    __IM uint8_t  RESERVED32;
-    __IM uint32_t RESERVED33[5];
+    __IM uint8_t  RESERVED31;
+    __IM uint32_t RESERVED32[5];
 
     union
     {
@@ -11112,8 +11538,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
         } RSTSR1_b;
     };
-    __IM uint16_t RESERVED34;
-    __IM uint32_t RESERVED35[3];
+    __IM uint16_t RESERVED33;
+    __IM uint32_t RESERVED34[3];
 
     union
     {
@@ -11139,8 +11565,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
         } SDADCCKCR_b;
     };
-    __IM uint16_t RESERVED36;
-    __IM uint32_t RESERVED37[3];
+    __IM uint16_t RESERVED35;
+    __IM uint32_t RESERVED36[3];
 
     union
     {
@@ -11195,7 +11621,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t          : 6;
         } LVD2SR_b;
     };
-    __IM uint32_t RESERVED38[183];
+    __IM uint32_t RESERVED37[183];
 
     union
     {
@@ -11223,7 +11649,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 14;
         } CGFSAR_b;
     };
-    __IM uint32_t RESERVED39;
+    __IM uint32_t RESERVED38;
 
     union
     {
@@ -11292,7 +11718,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t                : 8;
         } BBFSAR_b;
     };
-    __IM uint32_t RESERVED40[3];
+    __IM uint32_t RESERVED39[3];
 
     union
     {
@@ -11354,8 +11780,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint32_t : 4;
         } DPFSAR_b;
     };
-    __IM uint32_t RESERVED41[6];
-    __IM uint16_t RESERVED42;
+    __IM uint32_t RESERVED40[6];
+    __IM uint16_t RESERVED41;
 
     union
     {
@@ -11573,7 +11999,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 3;
         } DPSIEGR2_b;
     };
-    __IM uint8_t RESERVED43;
+    __IM uint8_t RESERVED42;
 
     union
     {
@@ -11631,7 +12057,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } RSTSR2_b;
     };
-    __IM uint8_t RESERVED44;
+    __IM uint8_t RESERVED43;
 
     union
     {
@@ -11648,7 +12074,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                           *   Enable                                                                    */
         } MOMCR_b;
     };
-    __IM uint16_t RESERVED45;
+    __IM uint16_t RESERVED44;
 
     union
     {
@@ -11718,7 +12144,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             } LVD2CMPCR_b;
         };
     };
-    __IM uint8_t RESERVED46;
+    __IM uint8_t RESERVED45;
 
     union
     {
@@ -11751,7 +12177,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
         } LVD2CR0_b;
     };
-    __IM uint8_t RESERVED47;
+    __IM uint8_t RESERVED46;
 
     union
     {
@@ -11786,7 +12212,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                : 7;
         } VBTCR1_b;
     };
-    __IM uint32_t RESERVED48[8];
+    __IM uint32_t RESERVED47[8];
 
     union
     {
@@ -11829,7 +12255,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t              : 6;
         } VCCSEL_b;
     };
-    __IM uint16_t RESERVED49;
+    __IM uint16_t RESERVED48;
 
     union
     {
@@ -11841,9 +12267,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                 : 7;
         } PL2LDOSCR_b;
     };
-    __IM uint8_t  RESERVED50;
-    __IM uint16_t RESERVED51;
-    __IM uint32_t RESERVED52[14];
+    __IM uint8_t  RESERVED49;
+    __IM uint16_t RESERVED50;
+    __IM uint32_t RESERVED51[14];
 
     union
     {
@@ -11866,8 +12292,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 6;
         } SOMCR_b;
     };
-    __IM uint16_t RESERVED53;
-    __IM uint32_t RESERVED54[3];
+    __IM uint16_t RESERVED52;
+    __IM uint32_t RESERVED53[3];
 
     union
     {
@@ -11879,7 +12305,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t             : 7;
         } LOCOCR_b;
     };
-    __IM uint8_t RESERVED55;
+    __IM uint8_t RESERVED54;
 
     union
     {
@@ -11894,8 +12320,8 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
                                          *   trimming bits                                                             */
         } LOCOUTCR_b;
     };
-    __IM uint8_t  RESERVED56;
-    __IM uint32_t RESERVED57[7];
+    __IM uint8_t  RESERVED55;
+    __IM uint32_t RESERVED56[7];
 
     union
     {
@@ -11934,7 +12360,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t               : 7;
         } VBTCMPCR_b;
     };
-    __IM uint8_t RESERVED58;
+    __IM uint8_t RESERVED57;
 
     union
     {
@@ -11948,7 +12374,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t                  : 6;
         } VBTLVDICR_b;
     };
-    __IM uint8_t RESERVED59;
+    __IM uint8_t RESERVED58;
 
     union
     {
@@ -11960,7 +12386,7 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 7;
         } VBTWCTLR_b;
     };
-    __IM uint8_t RESERVED60;
+    __IM uint8_t RESERVED59;
 
     union
     {
@@ -12095,9 +12521,9 @@ typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure
             uint8_t            : 4;
         } VBTBER_b;
     };
-    __IM uint8_t  RESERVED61;
-    __IM uint16_t RESERVED62;
-    __IM uint32_t RESERVED63[15];
+    __IM uint8_t  RESERVED60;
+    __IM uint16_t RESERVED61;
+    __IM uint32_t RESERVED62[15];
 
     union
     {
@@ -17400,36 +17826,62 @@ typedef struct                         /*!< (@ 0x40118000) R_SCI_B0 Structure
 {
     union
     {
-        __IM uint32_t RDR;             /*!< (@ 0x00000000) Receive Data Register                                      */
+        union
+        {
+            __IM uint32_t RDR;          /*!< (@ 0x00000000) Receive Data Register                                      */
 
-        struct
+            struct
+            {
+                __IM uint32_t RDAT : 9; /*!< [8..0] Serial receive data                                                */
+                __IM uint32_t MPB  : 1; /*!< [9..9] Multi-processor flag                                               */
+                __IM uint32_t DR   : 1; /*!< [10..10] Receive data ready flag                                          */
+                __IM uint32_t FPER : 1; /*!< [11..11] FIFO parity error flag                                           */
+                __IM uint32_t FFER : 1; /*!< [12..12] FIFO framing error flag                                          */
+                uint32_t           : 11;
+                __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error flag                                               */
+                uint32_t           : 2;
+                __IM uint32_t PER  : 1; /*!< [27..27] Parity error flag                                                */
+                __IM uint32_t FER  : 1; /*!< [28..28] Framing error flag                                               */
+                uint32_t           : 3;
+            } RDR_b;
+        };
+
+        union
         {
-            __IM uint32_t RDAT : 9;    /*!< [8..0] Serial receive data                                                */
-            __IM uint32_t MPB  : 1;    /*!< [9..9] Multi-processor flag                                               */
-            __IM uint32_t DR   : 1;    /*!< [10..10] Receive data ready flag                                          */
-            __IM uint32_t FPER : 1;    /*!< [11..11] FIFO parity error flag                                           */
-            __IM uint32_t FFER : 1;    /*!< [12..12] FIFO framing error flag                                          */
-            uint32_t           : 11;
-            __IM uint32_t ORER : 1;    /*!< [24..24] Overrun Error flag                                               */
-            uint32_t           : 2;
-            __IM uint32_t PER  : 1;    /*!< [27..27] Parity error flag                                                */
-            __IM uint32_t FER  : 1;    /*!< [28..28] Framing error flag                                               */
-            uint32_t           : 3;
-        } RDR_b;
+            __IOM uint8_t RDR_BY;       /*!< (@ 0x00000000) Receive Data Register (byte access)                        */
+
+            struct
+            {
+                __IOM uint8_t RDAT : 8; /*!< [7..0] Serial receive data                                                */
+            } RDR_BY_b;
+        };
     };
 
     union
     {
-        __IOM uint32_t TDR;            /*!< (@ 0x00000004) Transmit Data Register                                     */
+        union
+        {
+            __IOM uint32_t TDR;           /*!< (@ 0x00000004) Transmit Data Register                                     */
 
-        struct
+            struct
+            {
+                __IOM uint32_t TDAT  : 9; /*!< [8..0] Serial transmit data                                               */
+                __IOM uint32_t MPBT  : 1; /*!< [9..9] Multi-processor transfer bit flag                                  */
+                uint32_t             : 2;
+                __IOM uint32_t TSYNC : 1; /*!< [12..12] Transmit SYNC data                                               */
+                uint32_t             : 19;
+            } TDR_b;
+        };
+
+        union
         {
-            __IOM uint32_t TDAT  : 9;  /*!< [8..0] Serial transmit data                                               */
-            __IOM uint32_t MPBT  : 1;  /*!< [9..9] Multi-processor transfer bit flag                                  */
-            uint32_t             : 2;
-            __IOM uint32_t TSYNC : 1;  /*!< [12..12] Transmit SYNC data                                               */
-            uint32_t             : 19;
-        } TDR_b;
+            __IOM uint8_t TDR_BY;       /*!< (@ 0x00000004) Transmit Data Register (byte access)                       */
+
+            struct
+            {
+                __IOM uint8_t TDAT : 8; /*!< [7..0] Serial transmit data                                               */
+            } TDR_BY_b;
+        };
     };
 
     union
@@ -18380,6 +18832,23 @@ typedef struct                         /*!< (@ 0x40021000) R_TFU Structure
     };
 } R_TFU_Type;                          /*!< Size = 32 (0x20)                                                          */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
+ */
+
+typedef struct                          /*!< (@ 0x400E8000) R_AGTX0 Structure                                          */
+{
+    union
+    {
+        __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
+        __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
+    };
+} R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
+
 /* =========================================================================================================================== */
 /* ================                                          R_FLAD                                           ================ */
 /* =========================================================================================================================== */
@@ -18422,8 +18891,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_ADC0_BASE           0x40170000UL
  #define R_ADC1_BASE           0x40170200UL
  #define R_PSCU_BASE           0x400E0000UL
- #define R_AGTW0_BASE          0x400E8000UL
- #define R_AGTW1_BASE          0x400E8100UL
  #define R_BUS_BASE            0x40003000UL
  #define R_CAC_BASE            0x40083600UL
  #define R_CANFD_BASE          0x400B0000UL
@@ -18527,6 +18994,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_SPI_B0_BASE         0x4011A000UL
  #define R_SPI_B1_BASE         0x4011A100UL
  #define R_TFU_BASE            0x40021000UL
+ #define R_AGTX0_BASE          0x400E8000UL
+ #define R_AGTX1_BASE          0x400E8100UL
+ #define R_AGTX2_BASE          0x400E8200UL
+ #define R_AGTX3_BASE          0x400E8300UL
+ #define R_AGTX4_BASE          0x400E8400UL
+ #define R_AGTX5_BASE          0x400E8500UL
+ #define R_AGTX6_BASE          0x400E8600UL
+ #define R_AGTX7_BASE          0x400E8700UL
+ #define R_AGTX8_BASE          0x400E8800UL
+ #define R_AGTX9_BASE          0x400E8900UL
  #define R_FLAD_BASE           0x407FC000UL
 
 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
@@ -18548,8 +19025,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_ADC0           ((R_ADC0_Type *) R_ADC0_BASE)
  #define R_ADC1           ((R_ADC0_Type *) R_ADC1_BASE)
  #define R_PSCU           ((R_PSCU_Type *) R_PSCU_BASE)
- #define R_AGTW0          ((R_AGTW0_Type *) R_AGTW0_BASE)
- #define R_AGTW1          ((R_AGTW0_Type *) R_AGTW1_BASE)
 
 /* #define R_BUS                       ((R_BUS_Type*)             R_BUS_BASE) */
  #define R_CAC            ((R_CAC_Type *) R_CAC_BASE)
@@ -18655,6 +19130,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_SPI_B0         ((R_SPI_B0_Type *) R_SPI_B0_BASE)
  #define R_SPI_B1         ((R_SPI_B0_Type *) R_SPI_B1_BASE)
  #define R_TFU            ((R_TFU_Type *) R_TFU_BASE)
+ #define R_AGTX0          ((R_AGTX0_Type *) R_AGTX0_BASE)
+ #define R_AGTX1          ((R_AGTX0_Type *) R_AGTX1_BASE)
+ #define R_AGTX2          ((R_AGTX0_Type *) R_AGTX2_BASE)
+ #define R_AGTX3          ((R_AGTX0_Type *) R_AGTX3_BASE)
+ #define R_AGTX4          ((R_AGTX0_Type *) R_AGTX4_BASE)
+ #define R_AGTX5          ((R_AGTX0_Type *) R_AGTX5_BASE)
+ #define R_AGTX6          ((R_AGTX0_Type *) R_AGTX6_BASE)
+ #define R_AGTX7          ((R_AGTX0_Type *) R_AGTX7_BASE)
+ #define R_AGTX8          ((R_AGTX0_Type *) R_AGTX8_BASE)
+ #define R_AGTX9          ((R_AGTX0_Type *) R_AGTX9_BASE)
  #define R_FLAD           ((R_FLAD_Type *) R_FLAD_BASE)
 
 /** @} */ /* End of group Device_Peripheral_declaration */
@@ -19308,77 +19793,63 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* =========================================================================================================================== */
 
 /* =======================================================  PmnPFS_BY  ======================================================= */
- #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
- #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
- #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos      (5UL)          /*!< PIM (Bit 5)                                           */
- #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk      (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
- #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
- #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
- #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
- #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
- #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
- #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
  #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
  #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
 /* =======================================================  PmnPFS_HA  ======================================================= */
- #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
- #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
- #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos      (5UL)          /*!< PIM (Bit 5)                                           */
- #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk      (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
- #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
- #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
- #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
- #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
- #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
- #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
  #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
  #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
- #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos     (15UL)         /*!< ASEL (Bit 15)                                         */
- #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk     (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
- #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos     (14UL)         /*!< ISEL (Bit 14)                                         */
- #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk     (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
- #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos     (12UL)         /*!< EOFR (Bit 12)                                         */
- #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk     (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
  #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos     (10UL)         /*!< DSCR (Bit 10)                                         */
  #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk     (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos     (12UL)         /*!< EOFR (Bit 12)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk     (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos     (14UL)         /*!< ISEL (Bit 14)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk     (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos     (15UL)         /*!< ASEL (Bit 15)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk     (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
 /* ========================================================  PmnPFS  ========================================================= */
- #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos       (6UL)          /*!< NCODR (Bit 6)                                         */
- #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk       (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
- #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos         (5UL)          /*!< PIM (Bit 5)                                           */
- #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk         (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
- #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos         (4UL)          /*!< PCR (Bit 4)                                           */
- #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk         (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
- #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos         (2UL)          /*!< PDR (Bit 2)                                           */
- #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk         (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
- #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos        (1UL)          /*!< PIDR (Bit 1)                                          */
- #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk        (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
  #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos        (0UL)          /*!< PODR (Bit 0)                                          */
  #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk        (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
- #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos        (15UL)         /*!< ASEL (Bit 15)                                         */
- #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk        (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
- #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos        (14UL)         /*!< ISEL (Bit 14)                                         */
- #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk        (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
- #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos        (12UL)         /*!< EOFR (Bit 12)                                         */
- #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk        (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos        (1UL)          /*!< PIDR (Bit 1)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk        (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos         (2UL)          /*!< PDR (Bit 2)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk         (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos         (4UL)          /*!< PCR (Bit 4)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk         (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos       (6UL)          /*!< NCODR (Bit 6)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk       (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
  #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos        (10UL)         /*!< DSCR (Bit 10)                                         */
  #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk        (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
- #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos        (24UL)         /*!< PSEL (Bit 24)                                         */
- #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk        (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos        (12UL)         /*!< EOFR (Bit 12)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk        (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos        (14UL)         /*!< ISEL (Bit 14)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk        (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos        (15UL)         /*!< ASEL (Bit 15)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk        (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
  #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos         (16UL)         /*!< PMR (Bit 16)                                          */
  #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk         (0x10000UL)    /*!< PMR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos        (24UL)         /*!< PSEL (Bit 24)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk        (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f)                            */
 
 /* =========================================================================================================================== */
 /* ================                                           PORT                                            ================ */
 /* =========================================================================================================================== */
 
-/* =========================================================================================================================== */
-/* ================                                           VLSEL                                           ================ */
-/* =========================================================================================================================== */
-
-/* ========================================================  VL1SEL  ========================================================= */
- #define R_PFS_VLSEL_VL1SEL_SELVL_Pos    (0UL)   /*!< SELVL (Bit 0)                                         */
- #define R_PFS_VLSEL_VL1SEL_SELVL_Msk    (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01)                           */
-
 /* =========================================================================================================================== */
 /* ================                                           PMSAR                                           ================ */
 /* =========================================================================================================================== */
@@ -19468,6 +19939,101 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos    (0UL)          /*!< TRWSTAT (Bit 0)                                       */
  #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk    (0x1UL)        /*!< TRWSTAT (Bitfield-Mask: 0x01)                         */
 
+/* =========================================================================================================================== */
+/* ================                                           CTRL                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  AGTCR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AGTMR1  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
+/* ========================================================  AGTMR2  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
+/* =====================================================  AGTIOSEL_ALT  ====================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+/* ========================================================  AGTIOC  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AGTISR  ========================================================= */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AGTCMSR  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
+/* =======================================================  AGTIOSEL  ======================================================== */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT16                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           AGT32                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
+ #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
+
 /** @} */ /* End of group PosMask_clusters */
 
 /* =========================================================================================================================== */
@@ -20165,75 +20731,6 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_PSCU_DLMMON_DLMMON_Pos    (0UL)          /*!< DLMMON (Bit 0)                                        */
  #define R_PSCU_DLMMON_DLMMON_Msk    (0xfUL)        /*!< DLMMON (Bitfield-Mask: 0x0f)                          */
 
-/* =========================================================================================================================== */
-/* ================                                          R_AGTW0                                          ================ */
-/* =========================================================================================================================== */
-
-/* ==========================================================  AGT  ========================================================== */
- #define R_AGTW0_AGT_AGT_Pos           (0UL)          /*!< AGT (Bit 0)                                           */
- #define R_AGTW0_AGT_AGT_Msk           (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
-/* ========================================================  AGTCMA  ========================================================= */
- #define R_AGTW0_AGTCMA_AGTCMA_Pos     (0UL)          /*!< AGTCMA (Bit 0)                                        */
- #define R_AGTW0_AGTCMA_AGTCMA_Msk     (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
-/* ========================================================  AGTCMB  ========================================================= */
- #define R_AGTW0_AGTCMB_AGTCMB_Pos     (0UL)          /*!< AGTCMB (Bit 0)                                        */
- #define R_AGTW0_AGTCMB_AGTCMB_Msk     (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
-/* =========================================================  AGTCR  ========================================================= */
- #define R_AGTW0_AGTCR_TCMBF_Pos       (7UL)          /*!< TCMBF (Bit 7)                                         */
- #define R_AGTW0_AGTCR_TCMBF_Msk       (0x80UL)       /*!< TCMBF (Bitfield-Mask: 0x01)                           */
- #define R_AGTW0_AGTCR_TCMAF_Pos       (6UL)          /*!< TCMAF (Bit 6)                                         */
- #define R_AGTW0_AGTCR_TCMAF_Msk       (0x40UL)       /*!< TCMAF (Bitfield-Mask: 0x01)                           */
- #define R_AGTW0_AGTCR_TUNDF_Pos       (5UL)          /*!< TUNDF (Bit 5)                                         */
- #define R_AGTW0_AGTCR_TUNDF_Msk       (0x20UL)       /*!< TUNDF (Bitfield-Mask: 0x01)                           */
- #define R_AGTW0_AGTCR_TEDGF_Pos       (4UL)          /*!< TEDGF (Bit 4)                                         */
- #define R_AGTW0_AGTCR_TEDGF_Msk       (0x10UL)       /*!< TEDGF (Bitfield-Mask: 0x01)                           */
- #define R_AGTW0_AGTCR_TSTOP_Pos       (2UL)          /*!< TSTOP (Bit 2)                                         */
- #define R_AGTW0_AGTCR_TSTOP_Msk       (0x4UL)        /*!< TSTOP (Bitfield-Mask: 0x01)                           */
- #define R_AGTW0_AGTCR_TCSTF_Pos       (1UL)          /*!< TCSTF (Bit 1)                                         */
- #define R_AGTW0_AGTCR_TCSTF_Msk       (0x2UL)        /*!< TCSTF (Bitfield-Mask: 0x01)                           */
- #define R_AGTW0_AGTCR_TSTART_Pos      (0UL)          /*!< TSTART (Bit 0)                                        */
- #define R_AGTW0_AGTCR_TSTART_Msk      (0x1UL)        /*!< TSTART (Bitfield-Mask: 0x01)                          */
-/* ========================================================  AGTMR1  ========================================================= */
- #define R_AGTW0_AGTMR1_TCK_Pos        (4UL)          /*!< TCK (Bit 4)                                           */
- #define R_AGTW0_AGTMR1_TCK_Msk        (0x70UL)       /*!< TCK (Bitfield-Mask: 0x07)                             */
- #define R_AGTW0_AGTMR1_TEDGPL_Pos     (3UL)          /*!< TEDGPL (Bit 3)                                        */
- #define R_AGTW0_AGTMR1_TEDGPL_Msk     (0x8UL)        /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
- #define R_AGTW0_AGTMR1_TMOD_Pos       (0UL)          /*!< TMOD (Bit 0)                                          */
- #define R_AGTW0_AGTMR1_TMOD_Msk       (0x7UL)        /*!< TMOD (Bitfield-Mask: 0x07)                            */
-/* ========================================================  AGTMR2  ========================================================= */
- #define R_AGTW0_AGTMR2_LPM_Pos        (7UL)          /*!< LPM (Bit 7)                                           */
- #define R_AGTW0_AGTMR2_LPM_Msk        (0x80UL)       /*!< LPM (Bitfield-Mask: 0x01)                             */
- #define R_AGTW0_AGTMR2_CKS_Pos        (0UL)          /*!< CKS (Bit 0)                                           */
- #define R_AGTW0_AGTMR2_CKS_Msk        (0x7UL)        /*!< CKS (Bitfield-Mask: 0x07)                             */
-/* ========================================================  AGTIOC  ========================================================= */
- #define R_AGTW0_AGTIOC_TIOGT_Pos      (6UL)          /*!< TIOGT (Bit 6)                                         */
- #define R_AGTW0_AGTIOC_TIOGT_Msk      (0xc0UL)       /*!< TIOGT (Bitfield-Mask: 0x03)                           */
- #define R_AGTW0_AGTIOC_TIPF_Pos       (4UL)          /*!< TIPF (Bit 4)                                          */
- #define R_AGTW0_AGTIOC_TIPF_Msk       (0x30UL)       /*!< TIPF (Bitfield-Mask: 0x03)                            */
- #define R_AGTW0_AGTIOC_TOE_Pos        (2UL)          /*!< TOE (Bit 2)                                           */
- #define R_AGTW0_AGTIOC_TOE_Msk        (0x4UL)        /*!< TOE (Bitfield-Mask: 0x01)                             */
- #define R_AGTW0_AGTIOC_TEDGSEL_Pos    (0UL)          /*!< TEDGSEL (Bit 0)                                       */
- #define R_AGTW0_AGTIOC_TEDGSEL_Msk    (0x1UL)        /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
-/* ========================================================  AGTISR  ========================================================= */
- #define R_AGTW0_AGTISR_EEPS_Pos       (2UL)          /*!< EEPS (Bit 2)                                          */
- #define R_AGTW0_AGTISR_EEPS_Msk       (0x4UL)        /*!< EEPS (Bitfield-Mask: 0x01)                            */
-/* ========================================================  AGTCMSR  ======================================================== */
- #define R_AGTW0_AGTCMSR_TOPOLB_Pos    (6UL)          /*!< TOPOLB (Bit 6)                                        */
- #define R_AGTW0_AGTCMSR_TOPOLB_Msk    (0x40UL)       /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
- #define R_AGTW0_AGTCMSR_TOEB_Pos      (5UL)          /*!< TOEB (Bit 5)                                          */
- #define R_AGTW0_AGTCMSR_TOEB_Msk      (0x20UL)       /*!< TOEB (Bitfield-Mask: 0x01)                            */
- #define R_AGTW0_AGTCMSR_TCMEB_Pos     (4UL)          /*!< TCMEB (Bit 4)                                         */
- #define R_AGTW0_AGTCMSR_TCMEB_Msk     (0x10UL)       /*!< TCMEB (Bitfield-Mask: 0x01)                           */
- #define R_AGTW0_AGTCMSR_TOPOLA_Pos    (2UL)          /*!< TOPOLA (Bit 2)                                        */
- #define R_AGTW0_AGTCMSR_TOPOLA_Msk    (0x4UL)        /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
- #define R_AGTW0_AGTCMSR_TOEA_Pos      (1UL)          /*!< TOEA (Bit 1)                                          */
- #define R_AGTW0_AGTCMSR_TOEA_Msk      (0x2UL)        /*!< TOEA (Bitfield-Mask: 0x01)                            */
- #define R_AGTW0_AGTCMSR_TCMEA_Pos     (0UL)          /*!< TCMEA (Bit 0)                                         */
- #define R_AGTW0_AGTCMSR_TCMEA_Msk     (0x1UL)        /*!< TCMEA (Bitfield-Mask: 0x01)                           */
-/* =======================================================  AGTIOSEL  ======================================================== */
- #define R_AGTW0_AGTIOSEL_TIES_Pos     (4UL)          /*!< TIES (Bit 4)                                          */
- #define R_AGTW0_AGTIOSEL_TIES_Msk     (0x10UL)       /*!< TIES (Bitfield-Mask: 0x01)                            */
-
 /* =========================================================================================================================== */
 /* ================                                           R_BUS                                           ================ */
 /* =========================================================================================================================== */
@@ -21247,10 +21744,22 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
 /* =========================================================  GTCR  ========================================================== */
+ #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
+ #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTCR_TPCS_Pos              (23UL)         /*!< TPCS (Bit 23)                                         */
  #define R_GPT0_GTCR_TPCS_Msk              (0x7800000UL)  /*!< TPCS (Bitfield-Mask: 0x0f)                            */
  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
- #define R_GPT0_GTCR_MD_Msk                (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
+ #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
+ #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
+ #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
+ #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
+ #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
+ #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
 /* =======================================================  GTUDDTYC  ======================================================== */
@@ -21308,6 +21817,8 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
 /* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
+ #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
@@ -21316,8 +21827,16 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
- #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
- #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
+ #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
+ #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
+ #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
 /* =========================================================  GTST  ========================================================== */
  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
@@ -21374,6 +21893,8 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
+ #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
@@ -21463,6 +21984,67 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* ========================================================  GTSOTR  ========================================================= */
  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTADSMR  ======================================================== */
+ #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
+ #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
+ #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTEITC  ========================================================= */
+ #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
+ #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
+ #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
+ #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
+ #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
+ #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
+ #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
+ #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
+ #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  GTEITLI1  ======================================================== */
+ #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
+ #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
+ #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
+ #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
+ #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
+ #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
+ #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
+ #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
+ #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
+/* =======================================================  GTEITLI2  ======================================================== */
+ #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
+ #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
+ #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  GTEITLB  ======================================================== */
+ #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
+ #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
+ #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
+ #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
+ #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
+ #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
+ #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
 /* ========================================================  GTICLF  ========================================================= */
  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
@@ -21505,14 +22087,113 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
+ #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
+ #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
+ #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
+ #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
+ #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
+ #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  GTBER2  ========================================================= */
+ #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
+ #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
+ #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
+ #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
+ #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
+ #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
+ #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
+ #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
+ #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
+ #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
+ #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
+ #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
+ #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
+ #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
+ #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
+ #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
+ #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
+ #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
+ #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
+ #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
+/* ========================================================  GTOLBR  ========================================================= */
+ #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
+ #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
+ #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
+ #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  GTICCR  ========================================================= */
+ #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
+ #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
+ #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
+ #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
+ #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
+ #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
+ #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
+ #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
+ #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
+ #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
+ #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
+ #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
+ #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
+ #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
+ #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
+ #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
+ #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
+ #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
+ #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
+ #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
+ #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
+ #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
 
 /* =========================================================================================================================== */
 /* ================                                        R_GPT_GTCLK                                        ================ */
@@ -22910,45 +23591,45 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_PORT0_PCNTR1_PODR_Msk    (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff)                          */
  #define R_PORT0_PCNTR1_PDR_Pos     (0UL)          /*!< PDR (Bit 0)                                           */
  #define R_PORT0_PCNTR1_PDR_Msk     (0xffffUL)     /*!< PDR (Bitfield-Mask: 0xffff)                           */
-/* =========================================================  P0DR  ========================================================== */
- #define R_PORT0_P0DR_PODR_Pos      (0UL)          /*!< PODR (Bit 0)                                          */
- #define R_PORT0_P0DR_PODR_Msk      (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
 /* ==========================================================  PDR  ========================================================== */
  #define R_PORT0_PDR_PDR_Pos        (0UL)          /*!< PDR (Bit 0)                                           */
  #define R_PORT0_PDR_PDR_Msk        (0x1UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
+/* =========================================================  PODR  ========================================================== */
+ #define R_PORT0_PODR_PODR_Pos      (0UL)          /*!< PODR (Bit 0)                                          */
+ #define R_PORT0_PODR_PODR_Msk      (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
 /* ========================================================  PCNTR2  ========================================================= */
  #define R_PORT0_PCNTR2_EIDR_Pos    (16UL)         /*!< EIDR (Bit 16)                                         */
  #define R_PORT0_PCNTR2_EIDR_Msk    (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff)                          */
  #define R_PORT0_PCNTR2_PIDR_Pos    (0UL)          /*!< PIDR (Bit 0)                                          */
  #define R_PORT0_PCNTR2_PIDR_Msk    (0xffffUL)     /*!< PIDR (Bitfield-Mask: 0xffff)                          */
-/* =========================================================  EIDR  ========================================================== */
- #define R_PORT0_EIDR_EIDR_Pos      (0UL)          /*!< EIDR (Bit 0)                                          */
- #define R_PORT0_EIDR_EIDR_Msk      (0x1UL)        /*!< EIDR (Bitfield-Mask: 0x01)                            */
 /* =========================================================  PIDR  ========================================================== */
  #define R_PORT0_PIDR_PIDR_Pos      (0UL)          /*!< PIDR (Bit 0)                                          */
  #define R_PORT0_PIDR_PIDR_Msk      (0x1UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
+/* =========================================================  EIDR  ========================================================== */
+ #define R_PORT0_EIDR_EIDR_Pos      (0UL)          /*!< EIDR (Bit 0)                                          */
+ #define R_PORT0_EIDR_EIDR_Msk      (0x1UL)        /*!< EIDR (Bitfield-Mask: 0x01)                            */
 /* ========================================================  PCNTR3  ========================================================= */
  #define R_PORT0_PCNTR3_PORR_Pos    (16UL)         /*!< PORR (Bit 16)                                         */
  #define R_PORT0_PCNTR3_PORR_Msk    (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff)                          */
  #define R_PORT0_PCNTR3_POSR_Pos    (0UL)          /*!< POSR (Bit 0)                                          */
  #define R_PORT0_PCNTR3_POSR_Msk    (0xffffUL)     /*!< POSR (Bitfield-Mask: 0xffff)                          */
-/* =========================================================  PORR  ========================================================== */
- #define R_PORT0_PORR_PORR_Pos      (0UL)          /*!< PORR (Bit 0)                                          */
- #define R_PORT0_PORR_PORR_Msk      (0x1UL)        /*!< PORR (Bitfield-Mask: 0x01)                            */
 /* =========================================================  POSR  ========================================================== */
  #define R_PORT0_POSR_POSR_Pos      (0UL)          /*!< POSR (Bit 0)                                          */
  #define R_PORT0_POSR_POSR_Msk      (0x1UL)        /*!< POSR (Bitfield-Mask: 0x01)                            */
+/* =========================================================  PORR  ========================================================== */
+ #define R_PORT0_PORR_PORR_Pos      (0UL)          /*!< PORR (Bit 0)                                          */
+ #define R_PORT0_PORR_PORR_Msk      (0x1UL)        /*!< PORR (Bitfield-Mask: 0x01)                            */
 /* ========================================================  PCNTR4  ========================================================= */
  #define R_PORT0_PCNTR4_EORR_Pos    (16UL)         /*!< EORR (Bit 16)                                         */
  #define R_PORT0_PCNTR4_EORR_Msk    (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff)                          */
  #define R_PORT0_PCNTR4_EOSR_Pos    (0UL)          /*!< EOSR (Bit 0)                                          */
  #define R_PORT0_PCNTR4_EOSR_Msk    (0xffffUL)     /*!< EOSR (Bitfield-Mask: 0xffff)                          */
-/* =========================================================  EORR  ========================================================== */
- #define R_PORT0_EORR_EORR_Pos      (0UL)          /*!< EORR (Bit 0)                                          */
- #define R_PORT0_EORR_EORR_Msk      (0x1UL)        /*!< EORR (Bitfield-Mask: 0x01)                            */
 /* =========================================================  EOSR  ========================================================== */
  #define R_PORT0_EOSR_EOSR_Pos      (0UL)          /*!< EOSR (Bit 0)                                          */
  #define R_PORT0_EOSR_EOSR_Msk      (0x1UL)        /*!< EOSR (Bitfield-Mask: 0x01)                            */
+/* =========================================================  EORR  ========================================================== */
+ #define R_PORT0_EORR_EORR_Pos      (0UL)          /*!< EORR (Bit 0)                                          */
+ #define R_PORT0_EORR_EORR_Msk      (0x1UL)        /*!< EORR (Bitfield-Mask: 0x01)                            */
 
 /* =========================================================================================================================== */
 /* ================                                           R_PFS                                           ================ */
@@ -24322,6 +25003,9 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
 /* ======================================================  CECCKDIVCR  ======================================================= */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
+/* ======================================================  I3CCKDIVCR  ======================================================= */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
 /* ======================================================  IICCKDIVCR  ======================================================= */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
@@ -26874,6 +27558,9 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_SCI_B0_RDR_PER_Msk            (0x8000000UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
  #define R_SCI_B0_RDR_FER_Pos            (28UL)         /*!< FER (Bit 28)                                          */
  #define R_SCI_B0_RDR_FER_Msk            (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
+/* ========================================================  RDR_BY  ========================================================= */
+ #define R_SCI_B0_RDR_BY_RDAT_Pos        (0UL)          /*!< RDAT (Bit 0)                                          */
+ #define R_SCI_B0_RDR_BY_RDAT_Msk        (0xffUL)       /*!< RDAT (Bitfield-Mask: 0xff)                            */
 /* ==========================================================  TDR  ========================================================== */
  #define R_SCI_B0_TDR_TDAT_Pos           (0UL)          /*!< TDAT (Bit 0)                                          */
  #define R_SCI_B0_TDR_TDAT_Msk           (0x1ffUL)      /*!< TDAT (Bitfield-Mask: 0x1ff)                           */
@@ -26881,6 +27568,9 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_SCI_B0_TDR_MPBT_Msk           (0x200UL)      /*!< MPBT (Bitfield-Mask: 0x01)                            */
  #define R_SCI_B0_TDR_TSYNC_Pos          (12UL)         /*!< TSYNC (Bit 12)                                        */
  #define R_SCI_B0_TDR_TSYNC_Msk          (0x1000UL)     /*!< TSYNC (Bitfield-Mask: 0x01)                           */
+/* ========================================================  TDR_BY  ========================================================= */
+ #define R_SCI_B0_TDR_BY_TDAT_Pos        (0UL)          /*!< TDAT (Bit 0)                                          */
+ #define R_SCI_B0_TDR_BY_TDAT_Msk        (0xffUL)       /*!< TDAT (Bitfield-Mask: 0xff)                            */
 /* =========================================================  CCR0  ========================================================== */
  #define R_SCI_B0_CCR0_RE_Pos            (0UL)          /*!< RE (Bit 0)                                            */
  #define R_SCI_B0_CCR0_RE_Msk            (0x1UL)        /*!< RE (Bitfield-Mask: 0x01)                              */
@@ -27579,6 +28269,10 @@ typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure
  #define R_TFU_ATDT1_ATDT1_Pos    (0UL)          /*!< ATDT1 (Bit 0)                                         */
  #define R_TFU_ATDT1_ATDT1_Msk    (0xffffffffUL) /*!< ATDT1 (Bitfield-Mask: 0xffffffff)                     */
 
+/* =========================================================================================================================== */
+/* ================                                          R_AGTX0                                          ================ */
+/* =========================================================================================================================== */
+
 /* =========================================================================================================================== */
 /* ================                                          R_FLAD                                           ================ */
 /* =========================================================================================================================== */
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h
index 95a43203b..d3a6489b1 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -66,6 +66,8 @@ extern "C" {
   #include "R7FA2L1AB.h"
  #elif BSP_MCU_GROUP_RA4E1
   #include "R7FA4E10D.h"
+ #elif BSP_MCU_GROUP_RA4E2
+  #include "R7FA4E2B9.h"
  #elif BSP_MCU_GROUP_RA4M1
   #include "R7FA4M1AB.h"
  #elif BSP_MCU_GROUP_RA4M2
@@ -76,6 +78,8 @@ extern "C" {
   #include "R7FA4W1AD.h"
  #elif BSP_MCU_GROUP_RA6E1
   #include "R7FA6E10F.h"
+ #elif BSP_MCU_GROUP_RA6E2
+  #include "R7FA6E2BB.h"
  #elif BSP_MCU_GROUP_RA6M1
   #include "R7FA6M1AD.h"
  #elif BSP_MCU_GROUP_RA6M2
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
index af1e2842b..b61fe0f00 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c
index 7fc7f0a51..d135ed076 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c
index 2fffcd968..d5fbab271 100644
--- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c
+++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -358,6 +358,16 @@ void SystemInit (void)
     /* Initialize SystemCoreClock variable. */
     SystemCoreClockUpdate();
 
+#if BSP_FEATURE_HAS_RTC || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR
+
+    /* For TZ project, it should be called by the secure application, whether RTC module is to be configured as secure or not. */
+ #if !BSP_TZ_NONSECURE_BUILD
+
+    /* Perform RTC reset sequence to avoid unintended operation. */
+    R_BSP_Init_RTC();
+ #endif
+#endif
+
 #if !BSP_CFG_PFS_PROTECT
  #if BSP_TZ_SECURE_BUILD || (BSP_CFG_MCU_PART_SERIES == 8)
     R_PMISC->PWPRS = 0;                              ///< Clear BOWI bit - writing to PFSWE bit enabled
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h b/ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h
index faece4f00..14ce8f0a4 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h
+++ b/ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c
index ecaa49651..b4de2361d 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c
+++ b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -1137,9 +1137,15 @@ static void bsp_clock_freq_var_init (void)
 #endif
 #if BSP_PRV_PLL_SUPPORTED
  #if BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE
+  #if (3U != BSP_FEATURE_CGC_PLLCCR_TYPE)
 
     /* The PLL Is the startup clock. */
     g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_STARTUP_SOURCE_CLOCK_HZ;
+  #else
+    g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL]   = BSP_CFG_PLL1P_FREQUENCY_HZ;
+    g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1Q] = BSP_CFG_PLL1Q_FREQUENCY_HZ;
+    g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1R] = BSP_CFG_PLL1R_FREQUENCY_HZ;
+  #endif
  #else
 
     /* The PLL value will be calculated at initialization. */
@@ -1977,4 +1983,65 @@ uint32_t R_BSP_SourceClockHzGet (fsp_priv_source_clock_t clock)
     return source_clock;
 }
 
+#if BSP_FEATURE_HAS_RTC || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR
+
+/*******************************************************************************************************************//**
+ * RTC Initialization
+ *
+ * Some RTC registers must be initialized after reset to ensure correct operation.
+ * This reset is not performed automatically if the RTC is used in a project as it will
+ * be handled by the RTC driver if needed.
+ **********************************************************************************************************************/
+void R_BSP_Init_RTC (void)
+{
+    /* RA4M3 UM r01uh0893ej0120: Figure 23.14 Initialization procedure */
+
+    /* RCKSEL bit is not initialized after reset. Use LOCO as the default
+     * clock source if it is available. Note RCR4.ROPSEL is also cleared.
+     */
+ #if BSP_PRV_LOCO_USED
+    R_RTC->RCR4 = 1 << R_RTC_RCR4_RCKSEL_Pos;
+ #else
+
+    /* Sses SOSC as clock source, or there is no clock source. */
+    R_RTC->RCR4 = 0;
+ #endif
+
+ #if !BSP_CFG_RTC_USED
+  #if BSP_PRV_LOCO_USED || (BSP_FEATURE_CGC_HAS_SOSC && BSP_CLOCK_CFG_SUBCLOCK_POPULATED)
+
+    /*Wait for 6 clocks: 200 > (6*1000000) / 32K */
+    R_BSP_SoftwareDelay(BSP_PRV_RTC_RESET_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS);
+
+    R_RTC->RCR2 = 0;
+    FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR2, 0);
+
+    R_RTC->RCR2_b.RESET = 1;
+    FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR2_b.RESET, 0);
+
+    /* Disable RTC interrupts */
+    R_RTC->RCR1 = 0;
+
+   #if BSP_FEATURE_RTC_HAS_TCEN
+    for (uint8_t index = 0U; index < BSP_FEATURE_RTC_RTCCR_CHANNELS; index++)
+    {
+        /* RTCCRn.TCEN must be cleared after reset. */
+        R_RTC->RTCCR[index].RTCCR_b.TCEN = 0U;
+        FSP_HARDWARE_REGISTER_WAIT(R_RTC->RTCCR[index].RTCCR_b.TCEN, 0);
+    }
+   #endif
+  #endif
+ #endif
+
+ #if BSP_FEATURE_SYSC_HAS_VBTICTLR
+
+    /* VBTICTLR.VCHnINEN must be cleared after reset. */
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
+    R_SYSTEM->VBTICTLR = 0U;
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
+ #endif
+}
+
+#endif
+
 /** @} (end addtogroup BSP_MCU_PRV) */
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_clocks.h b/ra/fsp/src/bsp/mcu/all/bsp_clocks.h
index 684aa9603..7065a079a 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_clocks.h
+++ b/ra/fsp/src/bsp/mcu/all/bsp_clocks.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -369,6 +369,10 @@ FSP_HEADER
  #define BSP_PRV_FLL_STABILIZATION_TIME_US     (0)
 #endif
 
+#if BSP_FEATURE_HAS_RTC || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR
+ #define BSP_PRV_RTC_RESET_DELAY_US            (200)
+#endif
+
 /* Operating power control modes. */
 #define BSP_PRV_OPERATING_MODE_HIGH_SPEED      (0U) // Should match OPCCR OPCM high speed
 #define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED    (1U) // Should match OPCCR OPCM middle speed
@@ -1095,6 +1099,12 @@ void     bsp_prv_power_change_mstp_clear(uint32_t mstp_clear_bitmask);
 void bsp_prv_prepare_pll(uint32_t pll_freq_hz);
 void bsp_prv_clock_set(uint32_t clock, uint32_t sckdivcr, uint8_t sckdivcr2);
 
+/* RTC Initialization */
+#if BSP_FEATURE_HAS_RTC || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR
+void R_BSP_Init_RTC(void);
+
+#endif
+
 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
 FSP_FOOTER
 
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_common.c b/ra/fsp/src/bsp/mcu/all/bsp_common.c
index 22b7a8763..a7121a54e 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_common.c
+++ b/ra/fsp/src/bsp/mcu/all/bsp_common.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_common.h b/ra/fsp/src/bsp/mcu/all/bsp_common.h
index d4e8006d7..a800ecbf9 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_common.h
+++ b/ra/fsp/src/bsp/mcu/all/bsp_common.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -256,7 +256,6 @@ typedef struct st_bsp_unique_id
  * Exported global variables
  **********************************************************************************************************************/
 uint32_t R_BSP_SourceClockHzGet(fsp_priv_source_clock_t clock);
-
 /***********************************************************************************************************************
  * Global variables (defined in other files)
  **********************************************************************************************************************/
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h b/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h
index 4aed30bf9..a5159d0a3 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h
+++ b/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_delay.c b/ra/fsp/src/bsp/mcu/all/bsp_delay.c
index 1eef5dae9..e51a06216 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_delay.c
+++ b/ra/fsp/src/bsp/mcu/all/bsp_delay.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_delay.h b/ra/fsp/src/bsp/mcu/all/bsp_delay.h
index 7c516b126..8a2c20c0b 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_delay.h
+++ b/ra/fsp/src/bsp/mcu/all/bsp_delay.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c b/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c
index 4555d80c0..797f5c601 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c
+++ b/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h b/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h
index e01de9a77..001fa8e52 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h
+++ b/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_guard.c b/ra/fsp/src/bsp/mcu/all/bsp_guard.c
index 8b1f02197..d9b4df141 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_guard.c
+++ b/ra/fsp/src/bsp/mcu/all/bsp_guard.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_guard.h b/ra/fsp/src/bsp/mcu/all/bsp_guard.h
index 74d324824..ae5bb696e 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_guard.h
+++ b/ra/fsp/src/bsp/mcu/all/bsp_guard.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_io.c b/ra/fsp/src/bsp/mcu/all/bsp_io.c
index aec196554..130761000 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_io.c
+++ b/ra/fsp/src/bsp/mcu/all/bsp_io.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_io.h b/ra/fsp/src/bsp/mcu/all/bsp_io.h
index 4d35e486d..bbd20a481 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_io.h
+++ b/ra/fsp/src/bsp/mcu/all/bsp_io.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_irq.c b/ra/fsp/src/bsp/mcu/all/bsp_irq.c
index 476f29254..5a9faf257 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_irq.c
+++ b/ra/fsp/src/bsp/mcu/all/bsp_irq.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -110,7 +110,7 @@ void bsp_irq_cfg (void)
     R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
 #endif
 
-    for (uint32_t i = 0U; i < BSP_ICU_VECTOR_MAX_ENTRIES; i++)
+    for (uint32_t i = 0U; i < (BSP_ICU_VECTOR_MAX_ENTRIES - BSP_FEATURE_ICU_FIXED_IELSR_COUNT); i++)
     {
         R_ICU->IELSR[i] = (uint32_t) g_interrupt_event_link_select[i];
     }
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_irq.h b/ra/fsp/src/bsp/mcu/all/bsp_irq.h
index 362325e00..baca33c74 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_irq.h
+++ b/ra/fsp/src/bsp/mcu/all/bsp_irq.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h b/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h
index b878e3ca9..26a63083d 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h
+++ b/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h b/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h
index f152ba484..296340106 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h
+++ b/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -24,6 +24,10 @@
 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
 FSP_HEADER
 
+#if __has_include("internal/bsp_module_stop_internal.h")
+ #include "internal/bsp_module_stop_internal.h"
+#endif
+
 /*******************************************************************************************************************//**
  * @addtogroup BSP_MCU
  * @{
@@ -69,8 +73,14 @@ FSP_HEADER
  #define BSP_MSTP_REG_FSP_IP_GPT(channel)       R_MSTP->MSTPCRD
  #define BSP_MSTP_BIT_FSP_IP_GPT(channel)       ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \
                                                   channel) ? (1U << 5U) : (1U << 6U));
- #define BSP_MSTP_REG_FSP_IP_AGT(channel)       R_MSTP->MSTPCRD
- #define BSP_MSTP_BIT_FSP_IP_AGT(channel)       (1U << (3U - channel));
+
+ #ifndef BSP_MSTP_REG_FSP_IP_AGT
+  #define BSP_MSTP_REG_FSP_IP_AGT(channel)      R_MSTP->MSTPCRD
+ #endif
+ #ifndef BSP_MSTP_BIT_FSP_IP_AGT
+  #define BSP_MSTP_BIT_FSP_IP_AGT(channel)      (1U << (3U - channel));
+ #endif
+
  #define BSP_MSTP_REG_FSP_IP_POEG(channel)      R_MSTP->MSTPCRD
  #define BSP_MSTP_BIT_FSP_IP_POEG(channel)      (1U << (14U));
 #else
@@ -114,7 +124,7 @@ FSP_HEADER
 #define BSP_MSTP_REG_FSP_IP_CEC(channel)        R_MSTP->MSTPCRB
 #define BSP_MSTP_BIT_FSP_IP_CEC(channel)        (1U << (3U));
 #define BSP_MSTP_REG_FSP_IP_I3C(channel)        R_MSTP->MSTPCRB
-#define BSP_MSTP_BIT_FSP_IP_I3C(channel)        (1U << (4U));
+#define BSP_MSTP_BIT_FSP_IP_I3C(channel)        (1U << (BSP_FEATURE_I3C_MSTP_OFFSET - channel));
 #define BSP_MSTP_REG_FSP_IP_IRDA(channel)       R_MSTP->MSTPCRB
 #define BSP_MSTP_BIT_FSP_IP_IRDA(channel)       (1U << (5U - channel));
 #define BSP_MSTP_REG_FSP_IP_QSPI(channel)       R_MSTP->MSTPCRB
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c b/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c
index 9c5eed260..03f621cb6 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c
+++ b/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h b/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h
index 66943f7da..c7be65468 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h
+++ b/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c b/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c
index f6fac448e..1e0ff6d48 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c
+++ b/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -62,7 +62,7 @@
 
 #if !BSP_CFG_BOOT_IMAGE
 
- #if BSP_FEATURE_BSP_HAS_OSIS_REG == 1
+ #if BSP_FEATURE_FLASH_SUPPORTS_ID_CODE == 1
 
 /** ID code definitions defined here. */
 BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION (BSP_SECTION_ID_CODE) =
@@ -105,22 +105,25 @@ BSP_DONT_REMOVE static const uint32_t g_bsp_rom_registers[] BSP_PLACE_IN_SECTION
     (uint32_t) BSP_ROM_REG_MPU_CONTROL_SETTING
 };
 
- #elif BSP_FEATURE_BSP_HAS_OSIS_REG == 1
+ #elif BSP_FEATURE_FLASH_SUPPORTS_ID_CODE == 1
 
-    BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_rom_ofs0 =
-        BSP_CFG_ROM_REG_OFS0;
+  #if !BSP_TZ_NONSECURE_BUILD
+BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_rom_ofs0 =
+    BSP_CFG_ROM_REG_OFS0;
+
+BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_sas") g_bsp_rom_sas =
+    0xFFFFFFFF;
 
-    BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_sas") g_bsp_rom_sas =
-        0xFFFFFFFF;
+BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sec") g_bsp_rom_ofs1 =
+    BSP_ROM_REG_OFS1_SETTING;
 
-    BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sec") g_bsp_rom_ofs1 =
-        BSP_ROM_REG_OFS1_SETTING;
+BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec0") g_bsp_rom_bps0 =
+    BSP_CFG_ROM_REG_BPS0;
 
-    BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec0") g_bsp_rom_bps0 =
-        BSP_CFG_ROM_REG_BPS0;
+BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec0") g_bsp_rom_pbps0 =
+    BSP_CFG_ROM_REG_PBPS0;
 
-    BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec0") g_bsp_rom_pbps0 =
-        BSP_CFG_ROM_REG_PBPS0;
+  #endif
 
  #else                                 /* CM33 parts */
 
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c b/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c
index b71f12ba3..2bf2cbbe7 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c
+++ b/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_security.c b/ra/fsp/src/bsp/mcu/all/bsp_security.c
index 237efc404..6a4aef542 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_security.c
+++ b/ra/fsp/src/bsp/mcu/all/bsp_security.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -32,6 +32,9 @@
  #define BSP_PRV_AIRCR_VECTKEY    (0x05FA0000U)
  #define RA_NOT_DEFINED           (0)
 
+/* Branch T3 Instruction (IMM11=-2) */
+ #define BSP_PRV_INFINITE_LOOP    (0xE7FE)
+
 /***********************************************************************************************************************
  * Typedef definitions
  **********************************************************************************************************************/
@@ -55,9 +58,21 @@ typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_nonsecure_func_t)(void);
  #endif
 
  #if   defined(__IAR_SYSTEMS_ICC__) && BSP_TZ_SECURE_BUILD
-  #pragma section=".tz_flash_ns_start"
 
+  #pragma section=".tz_flash_ns_start"
 BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = (uint32_t *) __section_begin(".tz_flash_ns_start");
+  #pragma section="Veneer$$CMSE"
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_flash = (uint32_t *) __section_begin(
+    "Veneer$$CMSE");
+  #pragma section=".tz_ram_ns_start"
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_ram = (uint32_t *) __section_begin(".tz_ram_ns_start");
+  #pragma section=".tz_ram_nsc_start"
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_ram = (uint32_t *) __section_begin(
+    ".tz_ram_nsc_start");
+  #pragma section=".tz_data_flash_ns_start"
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_data_flash = (uint32_t *) __section_begin(
+    ".tz_data_flash_ns_start");
+
  #elif defined(__ARMCC_VERSION)
   #if BSP_FEATURE_BSP_HAS_ITCM
 extern const uint32_t Image$$__tz_ITCM_N$$Base;
@@ -172,8 +187,19 @@ BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_id_code             =
   #endif
 
  #elif defined(__GNUC__)
+
 extern const uint32_t FLASH_NS_IMAGE_START;
-BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = &FLASH_NS_IMAGE_START;
+extern const uint32_t __tz_FLASH_C;
+extern const uint32_t __tz_DATA_FLASH_N;
+extern const uint32_t __tz_RAM_N;
+extern const uint32_t __tz_RAM_C;
+
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash          = &FLASH_NS_IMAGE_START;
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_flash = (uint32_t *) &__tz_FLASH_C;
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_data_flash     = (uint32_t *) &__tz_DATA_FLASH_N;
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_ram            = (uint32_t *) &__tz_RAM_N;
+BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_ram   = (uint32_t *) &__tz_RAM_C;
+
  #endif
 
  #if BSP_TZ_SECURE_BUILD
@@ -199,6 +225,31 @@ void R_BSP_NonSecureEnter (void)
     uint32_t const     * p_ns_reset_address = (uint32_t const *) ((uint32_t) p_ns_vector_table + sizeof(uint32_t));
     bsp_nonsecure_func_t p_ns_reset         = (bsp_nonsecure_func_t) (*p_ns_reset_address);
 
+  #if BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
+
+    /* Check if the NS application exists. If the address of the Reset_Handler is all '1's, then assume that
+     * the NS application has not been programmed.
+     *
+     * If the secure application attempts to jump to an invalid instruction, a HardFault will occur. If the
+     * MCU is in NSECSD state, then the debugger will be unable to connect and program the NS Application. Jumping to
+     * a valid instruction ensures that the debugger will be able to connect.
+     */
+    if (UINT32_MAX == *p_ns_reset_address)
+    {
+        p_ns_reset = (bsp_nonsecure_func_t) gp_start_of_nonsecure_ram;
+
+        /* Write an infinite loop into start of NS RAM (Branch T3 Instruction (b.n <gp_start_of_nonsecure_ram>)). */
+        uint16_t * infinite_loop = (uint16_t *) gp_start_of_nonsecure_ram;
+        *infinite_loop = BSP_PRV_INFINITE_LOOP;
+
+        /* Set the NS stack pointer to a valid location in NS RAM. */
+        __TZ_set_MSP_NS((uint32_t) gp_start_of_nonsecure_ram + 0x20U);
+
+        /* Jump to the infinite loop. */
+        p_ns_reset();
+    }
+  #endif
+
     /* Set the NS vector table address */
     SCB_NS->VTOR = (uint32_t) p_ns_vector_table;
 
@@ -220,6 +271,19 @@ void R_BSP_NonSecureEnter (void)
  **********************************************************************************************************************/
 void R_BSP_SecurityInit (void)
 {
+    /* Disable PRCR for SARs. */
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
+
+  #if 0 == BSP_FEATURE_TZ_HAS_DLM
+
+    /* If DLM is not implemented, then the TrustZone partitions must be set at run-time. */
+    R_PSCU->CFSAMONA = (uint32_t) gp_start_of_nonsecure_flash & R_PSCU_CFSAMONA_CFS2_Msk;
+    R_PSCU->CFSAMONB = (uint32_t) gp_start_of_nonsecure_callable_flash & R_PSCU_CFSAMONB_CFS1_Msk;
+    R_PSCU->DFSAMON  = (uint32_t) gp_start_of_nonsecure_data_flash & R_PSCU_DFSAMON_DFS_Msk;
+    R_PSCU->SSAMONA  = (uint32_t) gp_start_of_nonsecure_ram & R_PSCU_SSAMONA_SS2_Msk;
+    R_PSCU->SSAMONB  = (uint32_t) gp_start_of_nonsecure_callable_ram & R_PSCU_SSAMONB_SS1_Msk;
+  #endif
+
     /* Setting SAU_CTRL.ALLNS to 1 allows the security attribution of all addresses to be set by the IDAU in the
      * system. */
     SAU->CTRL = SAU_CTRL_ALLNS_Msk;
@@ -254,9 +318,6 @@ void R_BSP_SecurityInit (void)
                  ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos) & FPU_FPCCR_CLRONRET_Msk);
   #endif
 
-    /* Disable PRCR for SARs. */
-    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
-
   #if BSP_FEATURE_BSP_HAS_TZFSAR
 
     /* Set TrustZone filter to Secure. */
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_security.h b/ra/fsp/src/bsp/mcu/all/bsp_security.h
index 294f1c6d3..fa938cb52 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_security.h
+++ b/ra/fsp/src/bsp/mcu/all/bsp_security.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_tfu.h b/ra/fsp/src/bsp/mcu/all/bsp_tfu.h
index 3ead89c36..c4367add6 100644
--- a/ra/fsp/src/bsp/mcu/all/bsp_tfu.h
+++ b/ra/fsp/src/bsp/mcu/all/bsp_tfu.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra2a1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra2a1/bsp_elc.h
index 5a65638cf..d30a97e92 100644
--- a/ra/fsp/src/bsp/mcu/ra2a1/bsp_elc.h
+++ b/ra/fsp/src/bsp/mcu/ra2a1/bsp_elc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h
index cb4c0261e..2ab8166cc 100644
--- a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h
+++ b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -81,8 +81,9 @@
 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS                      (0)
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                      (1U)
 
-#define BSP_FEATURE_AGT_HAS_AGTW                             (0U)
+#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT                   (0)
 #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                      (1)
+#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT                     (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                   (0x03)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                          (1)
@@ -127,7 +128,6 @@
 #define BSP_FEATURE_BSP_NUM_PMSAR                            (0U)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK                    (0xFFFF8FFFU)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET                  (12U)
-#define BSP_FEATURE_BSP_HAS_OSIS_REG                         (1U)
 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION         (0U)
 #define BSP_FEATURE_BSP_OSIS_PADDING                         (1)
 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED           (0U)
@@ -206,6 +206,7 @@
 #define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS                     (0) // Feature not available on this MCU TODO_CHECK_FEATURE
 #define BSP_FEATURE_CRYPTO_HAS_RSA                           (0)
 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED                   (0)
+#define BSP_FEATURE_CRYPTO_AES_IP_VERSION                    (1)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5                          (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5B                         (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE7                          (0)
@@ -285,6 +286,7 @@
 #define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NUM_CHANNELS                         (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_MSTP_OFFSET                          (0U) // Feature not available on this MCU
 
 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS                 (0U)
 #define BSP_FEATURE_ICU_HAS_WUPEN1                           (0U)
@@ -359,7 +361,11 @@
 
 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS                (0x0U)
 
+#define BSP_FEATURE_HAS_RTC                                  (1U)
 #define BSP_FEATURE_RTC_HAS_ROPSEL                           (0U)
+#define BSP_FEATURE_RTC_HAS_TCEN                             (0U)
+#define BSP_FEATURE_RTC_RTCCR_CHANNELS                       (0U)
+#define BSP_FEATURE_SYSC_HAS_VBTICTLR                        (0U)
 
 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS               (BSP_FEATURE_SCI_CHANNELS)
 #define BSP_FEATURE_SCI_CHANNELS                             (0x203U)
@@ -396,7 +402,13 @@
 #define BSP_FEATURE_TFU_SUPPORTED                            (0U) // Trigonometric Function Unit (TFU) not available on this MCU
 
 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP                     (1U)
-
 #define BSP_FEATURE_TZ_HAS_TRUSTZONE                         (0U)
+#define BSP_FEATURE_TZ_HAS_DLM                               (0U)
+
+#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM                     (0)
+#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK                  (0U)
+
+#define BSP_FEATURE_CRC_HAS_SNOOP                            (1U)
+#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR               (0x3U)
 
 #endif
diff --git a/ra/fsp/src/bsp/mcu/ra2a1/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra2a1/bsp_mcu_info.h
index 7898095ae..ab9588198 100644
--- a/ra/fsp/src/bsp/mcu/ra2a1/bsp_mcu_info.h
+++ b/ra/fsp/src/bsp/mcu/ra2a1/bsp_mcu_info.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra2e1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra2e1/bsp_elc.h
index 52283e238..79553e925 100644
--- a/ra/fsp/src/bsp/mcu/ra2e1/bsp_elc.h
+++ b/ra/fsp/src/bsp/mcu/ra2e1/bsp_elc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h
index dd0228208..67e29099f 100644
--- a/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h
+++ b/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -81,8 +81,9 @@
 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS                      (0)
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                      (1U)
 
-#define BSP_FEATURE_AGT_HAS_AGTW                             (0U)
+#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT                   (0)
 #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                      (1)
+#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT                     (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                   (0x03)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                          (0)
@@ -127,7 +128,6 @@
 #define BSP_FEATURE_BSP_NUM_PMSAR                            (0U)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK                    (0xFFFF8FFFU)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET                  (12U)
-#define BSP_FEATURE_BSP_HAS_OSIS_REG                         (1U)
 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION         (0U)
 #define BSP_FEATURE_BSP_OSIS_PADDING                         (1)
 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED           (0U)
@@ -204,6 +204,7 @@
 #define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS                     (0) // Feature not available on this MCU TODO_CHECK_FEATURE
 #define BSP_FEATURE_CRYPTO_HAS_RSA                           (0) //
 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED                   (0) //
+#define BSP_FEATURE_CRYPTO_AES_IP_VERSION                    (1)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5                          (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5B                         (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE7                          (0)
@@ -283,6 +284,7 @@
 #define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NUM_CHANNELS                         (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_MSTP_OFFSET                          (0U) // Feature not available on this MCU
 
 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS                 (1U)
 #define BSP_FEATURE_ICU_HAS_WUPEN1                           (0)  // Feature not available on this MCU
@@ -357,7 +359,11 @@
 
 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS                (0x0U)
 
+#define BSP_FEATURE_HAS_RTC                                  (1U)
 #define BSP_FEATURE_RTC_HAS_ROPSEL                           (1U)
+#define BSP_FEATURE_RTC_HAS_TCEN                             (0U)
+#define BSP_FEATURE_RTC_RTCCR_CHANNELS                       (0U)
+#define BSP_FEATURE_SYSC_HAS_VBTICTLR                        (0U)
 
 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS               (BSP_FEATURE_SCI_CHANNELS)
 #define BSP_FEATURE_SCI_CHANNELS                             (0x207U)
@@ -394,7 +400,13 @@
 #define BSP_FEATURE_TFU_SUPPORTED                            (0U) // Trigonometric Function Unit (TFU) not available on this MCU
 
 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP                     (1U)
-
 #define BSP_FEATURE_TZ_HAS_TRUSTZONE                         (0)  // Feature not available on this MCU
+#define BSP_FEATURE_TZ_HAS_DLM                               (0)  // Feature not available on this MCU
+
+#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM                     (0)
+#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK                  (0U)
+
+#define BSP_FEATURE_CRC_HAS_SNOOP                            (1U)
+#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR               (0x3U)
 
 #endif
diff --git a/ra/fsp/src/bsp/mcu/ra2e1/bsp_icu.h b/ra/fsp/src/bsp/mcu/ra2e1/bsp_icu.h
index 24e02ba95..e27ffe83d 100644
--- a/ra/fsp/src/bsp/mcu/ra2e1/bsp_icu.h
+++ b/ra/fsp/src/bsp/mcu/ra2e1/bsp_icu.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra2e1/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra2e1/bsp_mcu_info.h
index 25e10b847..6b5fc2657 100644
--- a/ra/fsp/src/bsp/mcu/ra2e1/bsp_mcu_info.h
+++ b/ra/fsp/src/bsp/mcu/ra2e1/bsp_mcu_info.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra2e2/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra2e2/bsp_elc.h
index 3782281ce..88df517fc 100644
--- a/ra/fsp/src/bsp/mcu/ra2e2/bsp_elc.h
+++ b/ra/fsp/src/bsp/mcu/ra2e2/bsp_elc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h
index 4be9e01ec..a8cd18492 100644
--- a/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h
+++ b/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -81,8 +81,9 @@
 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS                      (0)
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                      (1U)
 
-#define BSP_FEATURE_AGT_HAS_AGTW                             (1U)
+#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT                   (2)
 #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                      (1)
+#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT                     (1) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                   (0x03)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                          (0)
@@ -127,7 +128,6 @@
 #define BSP_FEATURE_BSP_NUM_PMSAR                            (0U)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK                    (0xFFFF8FFFU)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET                  (12U)
-#define BSP_FEATURE_BSP_HAS_OSIS_REG                         (1U)
 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION         (0U)
 #define BSP_FEATURE_BSP_OSIS_PADDING                         (1)
 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED           (0U)
@@ -204,6 +204,7 @@
 #define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS                     (0) // Feature not available on this MCU TODO_CHECK_FEATURE
 #define BSP_FEATURE_CRYPTO_HAS_RSA                           (0) //
 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED                   (0) //
+#define BSP_FEATURE_CRYPTO_AES_IP_VERSION                    (1)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5                          (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5B                         (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE7                          (0)
@@ -283,6 +284,7 @@
 #define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (4U)
 #define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (2U)
 #define BSP_FEATURE_I3C_NUM_CHANNELS                         (1U)
+#define BSP_FEATURE_I3C_MSTP_OFFSET                          (9U)
 
 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS                 (1U)
 #define BSP_FEATURE_ICU_HAS_WUPEN1                           (0) // Feature not available on this MCU
@@ -357,7 +359,11 @@
 
 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS                (0x0U)
 
+#define BSP_FEATURE_HAS_RTC                                  (0U)
 #define BSP_FEATURE_RTC_HAS_ROPSEL                           (0U)
+#define BSP_FEATURE_RTC_HAS_TCEN                             (0U)
+#define BSP_FEATURE_RTC_RTCCR_CHANNELS                       (0U)
+#define BSP_FEATURE_SYSC_HAS_VBTICTLR                        (0U)
 
 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS               (BSP_FEATURE_SCI_CHANNELS)
 #define BSP_FEATURE_SCI_CHANNELS                             (0x200U)
@@ -394,7 +400,13 @@
 #define BSP_FEATURE_TFU_SUPPORTED                            (0U) // Trigonometric Function Unit (TFU) not available on this MCU
 
 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP                     (1U)
-
 #define BSP_FEATURE_TZ_HAS_TRUSTZONE                         (0)  // Feature not available on this MCU
+#define BSP_FEATURE_TZ_HAS_DLM                               (0)  // Feature not available on this MCU
+
+#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM                     (0)
+#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK                  (0U)
+
+#define BSP_FEATURE_CRC_HAS_SNOOP                            (1U)
+#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR               (0x3U)
 
 #endif
diff --git a/ra/fsp/src/bsp/mcu/ra2e2/bsp_icu.h b/ra/fsp/src/bsp/mcu/ra2e2/bsp_icu.h
index 5625e757d..4e89a77b6 100644
--- a/ra/fsp/src/bsp/mcu/ra2e2/bsp_icu.h
+++ b/ra/fsp/src/bsp/mcu/ra2e2/bsp_icu.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra2e2/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra2e2/bsp_mcu_info.h
index bb8b7653f..37676329f 100644
--- a/ra/fsp/src/bsp/mcu/ra2e2/bsp_mcu_info.h
+++ b/ra/fsp/src/bsp/mcu/ra2e2/bsp_mcu_info.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h
index 7a6523d73..8c82f344a 100644
--- a/ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h
+++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h
index eba16b04b..9aa3de261 100644
--- a/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h
+++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -81,8 +81,9 @@
 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS                      (0)
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                      (1U)
 
-#define BSP_FEATURE_AGT_HAS_AGTW                             (0U)
+#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT                   (0)
 #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                      (1)
+#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT                     (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                   (0x03)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                          (0)
@@ -127,7 +128,6 @@
 #define BSP_FEATURE_BSP_NUM_PMSAR                            (0U)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK                    (0xFFFF8FFFU)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET                  (12U)
-#define BSP_FEATURE_BSP_HAS_OSIS_REG                         (1U)
 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION         (0U)
 #define BSP_FEATURE_BSP_OSIS_PADDING                         (1)
 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED           (0U)
@@ -204,6 +204,7 @@
 #define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS                     (0) // Feature not available on this MCU TODO_CHECK_FEATURE
 #define BSP_FEATURE_CRYPTO_HAS_RSA                           (0)
 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED                   (0)
+#define BSP_FEATURE_CRYPTO_AES_IP_VERSION                    (1)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5                          (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5B                         (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE7                          (0)
@@ -283,6 +284,7 @@
 #define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NUM_CHANNELS                         (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_MSTP_OFFSET                          (0U) // Feature not available on this MCU
 
 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS                 (1U)
 #define BSP_FEATURE_ICU_HAS_WUPEN1                           (0U)
@@ -357,7 +359,11 @@
 
 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS                (0x0U)
 
+#define BSP_FEATURE_HAS_RTC                                  (1U)
 #define BSP_FEATURE_RTC_HAS_ROPSEL                           (1U)
+#define BSP_FEATURE_RTC_HAS_TCEN                             (0U)
+#define BSP_FEATURE_RTC_RTCCR_CHANNELS                       (0U)
+#define BSP_FEATURE_SYSC_HAS_VBTICTLR                        (0U)
 
 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS               (BSP_FEATURE_SCI_CHANNELS)
 #define BSP_FEATURE_SCI_CHANNELS                             (0x20FU)
@@ -394,7 +400,13 @@
 #define BSP_FEATURE_TFU_SUPPORTED                            (0U) // Trigonometric Function Unit (TFU) not available on this MCU
 
 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP                     (1U)
-
 #define BSP_FEATURE_TZ_HAS_TRUSTZONE                         (0U)
+#define BSP_FEATURE_TZ_HAS_DLM                               (0U)
+
+#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM                     (0)
+#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK                  (0U)
+
+#define BSP_FEATURE_CRC_HAS_SNOOP                            (1U)
+#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR               (0x3U)
 
 #endif
diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_icu.h b/ra/fsp/src/bsp/mcu/ra2l1/bsp_icu.h
index adcb7a5d9..745f5fd6d 100644
--- a/ra/fsp/src/bsp/mcu/ra2l1/bsp_icu.h
+++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_icu.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra2l1/bsp_mcu_info.h
index 1c3813f34..66eef4137 100644
--- a/ra/fsp/src/bsp/mcu/ra2l1/bsp_mcu_info.h
+++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_mcu_info.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_power.c b/ra/fsp/src/bsp/mcu/ra2l1/bsp_power.c
index f934758f9..77ff0cf95 100644
--- a/ra/fsp/src/bsp/mcu/ra2l1/bsp_power.c
+++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_power.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_power.h b/ra/fsp/src/bsp/mcu/ra2l1/bsp_power.h
index 64f75229c..0cea58432 100644
--- a/ra/fsp/src/bsp/mcu/ra2l1/bsp_power.h
+++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_power.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra4e1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra4e1/bsp_elc.h
index c72178810..fea46fd09 100644
--- a/ra/fsp/src/bsp/mcu/ra4e1/bsp_elc.h
+++ b/ra/fsp/src/bsp/mcu/ra4e1/bsp_elc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h
index 8b4ac4716..e40bf2518 100644
--- a/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h
+++ b/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -85,8 +85,9 @@
 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS                      (0)       // Feature not available on this MCU
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                      (1U)
 
-#define BSP_FEATURE_AGT_HAS_AGTW                             (0)       // Feature not available on this MCU TODO_CHECK_FEATURE
+#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT                   (0)
 #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                      (5)
+#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT                     (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                   (0x2F)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                          (1)
@@ -131,7 +132,6 @@
 #define BSP_FEATURE_BSP_NUM_PMSAR                            (6U)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK                    (0xFFFFF9FFU)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET                  (9U)
-#define BSP_FEATURE_BSP_HAS_OSIS_REG                         (0U)
 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION         (1U)
 #define BSP_FEATURE_BSP_OSIS_PADDING                         (0U)
 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED           (0U)
@@ -208,6 +208,7 @@
 #define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS                     (0) // Feature not available on this MCU TODO_CHECK_FEATURE
 #define BSP_FEATURE_CRYPTO_HAS_RSA                           (0)
 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED                   (0)
+#define BSP_FEATURE_CRYPTO_AES_IP_VERSION                    (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5                          (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5B                         (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE7                          (0)
@@ -287,6 +288,7 @@
 #define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NUM_CHANNELS                         (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_MSTP_OFFSET                          (0U) // Feature not available on this MCU
 
 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS                 (0U)
 #define BSP_FEATURE_ICU_HAS_WUPEN1                           (1U)
@@ -361,7 +363,11 @@
 
 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS                (0x60000000U)
 
+#define BSP_FEATURE_HAS_RTC                                  (1U)
 #define BSP_FEATURE_RTC_HAS_ROPSEL                           (0U)
+#define BSP_FEATURE_RTC_HAS_TCEN                             (1U)
+#define BSP_FEATURE_RTC_RTCCR_CHANNELS                       (1U)
+#define BSP_FEATURE_SYSC_HAS_VBTICTLR                        (1U)
 
 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS               (0x219U)
 #define BSP_FEATURE_SCI_CHANNELS                             (0x219U)
@@ -398,7 +404,13 @@
 #define BSP_FEATURE_TFU_SUPPORTED                            (0U) // Trigonometric Function Unit (TFU) not available on this MCU
 
 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP                     (0U)
-
 #define BSP_FEATURE_TZ_HAS_TRUSTZONE                         (1U)
+#define BSP_FEATURE_TZ_HAS_DLM                               (1U)
+
+#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM                     (0)
+#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK                  (0U)
+
+#define BSP_FEATURE_CRC_HAS_SNOOP                            (0U)
+#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR               (0x0U) // Don't care
 
 #endif
diff --git a/ra/fsp/src/bsp/mcu/ra4e1/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra4e1/bsp_mcu_info.h
index d194e6ce3..911da77d7 100644
--- a/ra/fsp/src/bsp/mcu/ra4e1/bsp_mcu_info.h
+++ b/ra/fsp/src/bsp/mcu/ra4e1/bsp_mcu_info.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra4e2/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra4e2/bsp_elc.h
new file mode 100644
index 000000000..88956a1b4
--- /dev/null
+++ b/ra/fsp/src/bsp/mcu/ra4e2/bsp_elc.h
@@ -0,0 +1,224 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef BSP_ELC_H
+#define BSP_ELC_H
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************
+ * @addtogroup BSP_MCU_RA4E2
+ * @{
+ **********************************************************************************************************************/
+
+/** Sources of event signals to be linked to other peripherals or the CPU
+ * @note This list may change based on based on the device.
+ * */
+typedef enum e_elc_event_ra4e2
+{
+    ELC_EVENT_NONE                   = (0),     // Link disabled
+    ELC_EVENT_ICU_IRQ0               = (0x001), // External pin interrupt 0
+    ELC_EVENT_ICU_IRQ1               = (0x002), // External pin interrupt 1
+    ELC_EVENT_ICU_IRQ2               = (0x003), // External pin interrupt 2
+    ELC_EVENT_ICU_IRQ3               = (0x004), // External pin interrupt 3
+    ELC_EVENT_ICU_IRQ4               = (0x005), // External pin interrupt 4
+    ELC_EVENT_ICU_IRQ5               = (0x006), // External pin interrupt 5
+    ELC_EVENT_ICU_IRQ6               = (0x007), // External pin interrupt 6
+    ELC_EVENT_ICU_IRQ7               = (0x008), // External pin interrupt 7
+    ELC_EVENT_ICU_IRQ8               = (0x009), // External pin interrupt 8
+    ELC_EVENT_ICU_IRQ9               = (0x00A), // External pin interrupt 9
+    ELC_EVENT_ICU_IRQ10              = (0x00B), // External pin interrupt 10
+    ELC_EVENT_ICU_IRQ11              = (0x00C), // External pin interrupt 11
+    ELC_EVENT_ICU_IRQ12              = (0x00D), // External pin interrupt 12
+    ELC_EVENT_ICU_IRQ13              = (0x00E), // External pin interrupt 13
+    ELC_EVENT_ICU_IRQ14              = (0x00F), // External pin interrupt 14
+    ELC_EVENT_DMAC0_INT              = (0x020), // DMAC transfer end 0
+    ELC_EVENT_DMAC1_INT              = (0x021), // DMAC transfer end 1
+    ELC_EVENT_DMAC2_INT              = (0x022), // DMAC transfer end 2
+    ELC_EVENT_DMAC3_INT              = (0x023), // DMAC transfer end 3
+    ELC_EVENT_DMAC4_INT              = (0x024), // DMAC transfer end 4
+    ELC_EVENT_DMAC5_INT              = (0x025), // DMAC transfer end 5
+    ELC_EVENT_DMAC6_INT              = (0x026), // DMAC transfer end 6
+    ELC_EVENT_DMAC7_INT              = (0x027), // DMAC transfer end 7
+    ELC_EVENT_DTC_COMPLETE           = (0x029), // DTC transfer complete
+    ELC_EVENT_DMA_TRANSERR           = (0x02B), // DMA transfer error
+    ELC_EVENT_ICU_SNOOZE_CANCEL      = (0x02D), // Canceling from Snooze mode
+    ELC_EVENT_FCU_FIFERR             = (0x030), // Flash access error interrupt
+    ELC_EVENT_FCU_FRDYI              = (0x031), // Flash ready interrupt
+    ELC_EVENT_LVD_LVD1               = (0x038), // Voltage monitor 1 interrupt
+    ELC_EVENT_LVD_LVD2               = (0x039), // Voltage monitor 2 interrupt
+    ELC_EVENT_CGC_MOSC_STOP          = (0x03B), // Main Clock oscillation stop
+    ELC_EVENT_LPM_SNOOZE_REQUEST     = (0x03C), // Snooze entry
+    ELC_EVENT_AGT0_INT               = (0x040), // AGT interrupt
+    ELC_EVENT_AGT0_COMPARE_A         = (0x041), // Compare match A
+    ELC_EVENT_AGT0_COMPARE_B         = (0x042), // Compare match B
+    ELC_EVENT_AGT1_INT               = (0x043), // AGT interrupt
+    ELC_EVENT_AGT1_COMPARE_A         = (0x044), // Compare match A
+    ELC_EVENT_AGT1_COMPARE_B         = (0x045), // Compare match B
+    ELC_EVENT_IWDT_UNDERFLOW         = (0x052), // IWDT underflow
+    ELC_EVENT_WDT_UNDERFLOW          = (0x053), // WDT underflow
+    ELC_EVENT_RTC_ALARM              = (0x054), // Alarm interrupt
+    ELC_EVENT_RTC_PERIOD             = (0x055), // Periodic interrupt
+    ELC_EVENT_RTC_CARRY              = (0x056), // Carry interrupt
+    ELC_EVENT_CAN_RXF                = (0x059), // Global recieve FIFO interrupt
+    ELC_EVENT_CAN_GLERR              = (0x05A), // Global error
+    ELC_EVENT_CAN_DMAREQ0            = (0x05B), // DMA 0 request
+    ELC_EVENT_CAN_DMAREQ1            = (0x05C), // DMA 1 request
+    ELC_EVENT_CAN0_TX                = (0x063), // Transmit interrupt
+    ELC_EVENT_CAN0_CHERR             = (0x064), // Channel error
+    ELC_EVENT_CAN0_COMFRX            = (0x065), // Common FIFO recieve interrupt
+    ELC_EVENT_CAN0_CF_DMAREQ         = (0x066), // Channel DMA request
+    ELC_EVENT_CAN0_RXMB              = (0x067), // Receive message buffer interrupt
+    ELC_EVENT_USBFS_INT              = (0x06D), // USBFS interrupt
+    ELC_EVENT_USBFS_RESUME           = (0x06E), // USBFS resume interrupt
+    ELC_EVENT_SSI0_TXI               = (0x08A), // Transmit data empty
+    ELC_EVENT_SSI0_RXI               = (0x08B), // Receive data full
+    ELC_EVENT_SSI0_INT               = (0x08D), // Error interrupt
+    ELC_EVENT_CAC_FREQUENCY_ERROR    = (0x09E), // Frequency error interrupt
+    ELC_EVENT_CAC_MEASUREMENT_END    = (0x09F), // Measurement end interrupt
+    ELC_EVENT_CAC_OVERFLOW           = (0x0A0), // Overflow interrupt
+    ELC_EVENT_CEC_INTDA              = (0x0AB), // Data interrupt
+    ELC_EVENT_CEC_INTCE              = (0x0AC), // Communication complete interrupt
+    ELC_EVENT_CEC_INTERR             = (0x0AD), // Error interrupt
+    ELC_EVENT_IOPORT_EVENT_1         = (0x0B1), // Port 1 event
+    ELC_EVENT_IOPORT_EVENT_2         = (0x0B2), // Port 2 event
+    ELC_EVENT_IOPORT_EVENT_3         = (0x0B3), // Port 3 event
+    ELC_EVENT_IOPORT_EVENT_4         = (0x0B4), // Port 4 event
+    ELC_EVENT_ELC_SOFTWARE_EVENT_0   = (0x0B5), // Software event 0
+    ELC_EVENT_ELC_SOFTWARE_EVENT_1   = (0x0B6), // Software event 1
+    ELC_EVENT_POEG0_EVENT            = (0x0B7), // Port Output disable interrupt A
+    ELC_EVENT_POEG1_EVENT            = (0x0B8), // Port Output disable interrupt B
+    ELC_EVENT_POEG2_EVENT            = (0x0B9), // Port Output disable interrupt C
+    ELC_EVENT_POEG3_EVENT            = (0x0BA), // Port Output disable interrupt D
+    ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0C0), // Compare match A
+    ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0C1), // Compare match B
+    ELC_EVENT_GPT0_COMPARE_C         = (0x0C2), // Compare match C
+    ELC_EVENT_GPT0_COMPARE_D         = (0x0C3), // Compare match D
+    ELC_EVENT_GPT0_COMPARE_E         = (0x0C4), // Compare match E
+    ELC_EVENT_GPT0_COMPARE_F         = (0x0C5), // Compare match F
+    ELC_EVENT_GPT0_COUNTER_OVERFLOW  = (0x0C6), // Overflow
+    ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0C7), // Underflow
+    ELC_EVENT_GPT0_PC                = (0x0C8), // Period count function finish
+    ELC_EVENT_GPT0_AD_TRIG_A         = (0x0C9), // A/D converter start request A
+    ELC_EVENT_GPT0_AD_TRIG_B         = (0x0CA), // A/D converter start request B
+    ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0CB), // Compare match A
+    ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CC), // Compare match B
+    ELC_EVENT_GPT1_COMPARE_C         = (0x0CD), // Compare match C
+    ELC_EVENT_GPT1_COMPARE_D         = (0x0CE), // Compare match D
+    ELC_EVENT_GPT1_COMPARE_E         = (0x0CF), // Compare match E
+    ELC_EVENT_GPT1_COMPARE_F         = (0x0D0), // Compare match F
+    ELC_EVENT_GPT1_COUNTER_OVERFLOW  = (0x0D1), // Overflow
+    ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D2), // Underflow
+    ELC_EVENT_GPT1_PC                = (0x0D3), // Period count function finish
+    ELC_EVENT_GPT1_AD_TRIG_A         = (0x0D4), // A/D converter start request A
+    ELC_EVENT_GPT1_AD_TRIG_B         = (0x0D5), // A/D converter start request B
+    ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0EC), // Compare match A
+    ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0ED), // Compare match B
+    ELC_EVENT_GPT4_COMPARE_C         = (0x0EE), // Compare match C
+    ELC_EVENT_GPT4_COMPARE_D         = (0x0EF), // Compare match D
+    ELC_EVENT_GPT4_COMPARE_E         = (0x0F0), // Compare match E
+    ELC_EVENT_GPT4_COMPARE_F         = (0x0F1), // Compare match F
+    ELC_EVENT_GPT4_COUNTER_OVERFLOW  = (0x0F2), // Overflow
+    ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0F3), // Underflow
+    ELC_EVENT_GPT4_PC                = (0x0F4), // Period count function finish
+    ELC_EVENT_GPT4_AD_TRIG_A         = (0x0F5), // A/D converter start request A
+    ELC_EVENT_GPT4_AD_TRIG_B         = (0x0F6), // A/D converter start request B
+    ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0F7), // Compare match A
+    ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0F8), // Compare match B
+    ELC_EVENT_GPT5_COMPARE_C         = (0x0F9), // Compare match C
+    ELC_EVENT_GPT5_COMPARE_D         = (0x0FA), // Compare match D
+    ELC_EVENT_GPT5_COMPARE_E         = (0x0FB), // Compare match E
+    ELC_EVENT_GPT5_COMPARE_F         = (0x0FC), // Compare match F
+    ELC_EVENT_GPT5_COUNTER_OVERFLOW  = (0x0FD), // Overflow
+    ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0FE), // Underflow
+    ELC_EVENT_GPT5_PC                = (0x0FF), // Period count function finish
+    ELC_EVENT_GPT5_AD_TRIG_A         = (0x100), // A/D converter start request A
+    ELC_EVENT_GPT5_AD_TRIG_B         = (0x101), // A/D converter start request B
+    ELC_EVENT_OPS_UVW_EDGE           = (0x15C), // UVW edge event
+    ELC_EVENT_ADC0_SCAN_END          = (0x160), // A/D scan end interrupt
+    ELC_EVENT_ADC0_SCAN_END_B        = (0x161), // A/D scan end interrupt for group B
+    ELC_EVENT_ADC0_WINDOW_A          = (0x162), // Window A Compare match
+    ELC_EVENT_ADC0_WINDOW_B          = (0x163), // Window B Compare match
+    ELC_EVENT_ADC0_COMPARE_MATCH     = (0x164), // Compare match
+    ELC_EVENT_ADC0_COMPARE_MISMATCH  = (0x165), // Compare mismatch
+    ELC_EVENT_SCI0_RXI               = (0x180), // Receive data full
+    ELC_EVENT_SCI0_TXI               = (0x181), // Transmit data empty
+    ELC_EVENT_SCI0_TEI               = (0x182), // Transmit end
+    ELC_EVENT_SCI0_ERI               = (0x183), // Receive error
+    ELC_EVENT_SCI0_AM                = (0x184), // Address match event
+    ELC_EVENT_SCI0_RXI_OR_ERI        = (0x185), // Receive data full/Receive
+    ELC_EVENT_SCI9_RXI               = (0x1B6), // Received data full
+    ELC_EVENT_SCI9_TXI               = (0x1B7), // Transmit data empty
+    ELC_EVENT_SCI9_TEI               = (0x1B8), // Transmit end
+    ELC_EVENT_SCI9_ERI               = (0x1B9), // Receive error
+    ELC_EVENT_SCI9_AM                = (0x1BA), // Address match event
+    ELC_EVENT_SPI0_RXI               = (0x1C4), // Receive buffer full
+    ELC_EVENT_SPI0_TXI               = (0x1C5), // Transmit buffer empty
+    ELC_EVENT_SPI0_IDLE              = (0x1C6), // Idle
+    ELC_EVENT_SPI0_ERI               = (0x1C7), // Error
+    ELC_EVENT_SPI0_TEI               = (0x1C8), // Transmission complete event
+    ELC_EVENT_SPI1_RXI               = (0x1C9), // Receive buffer full
+    ELC_EVENT_SPI1_TXI               = (0x1CA), // Transmit buffer empty
+    ELC_EVENT_SPI1_IDLE              = (0x1CB), // Idle
+    ELC_EVENT_SPI1_ERI               = (0x1CC), // Error
+    ELC_EVENT_SPI1_TEI               = (0x1CD), // Transmission complete event
+    ELC_CAN_MRAM_ERI                 = (0x1D0), // ECC error
+    ELC_EVENT_DOC_INT                = (0x1DB), // Data operation circuit interrupt
+    ELC_EVENT_I3C0_RESPONSE          = (0x1DC), // Response status buffer full
+    ELC_EVENT_I3C0_COMMAND           = (0x1DD), // Command buffer empty
+    ELC_EVENT_I3C0_IBI               = (0x1DE), // IBI status buffer full
+    ELC_EVENT_I3C0_RX                = (0x1DF), // Receive
+    ELC_EVENT_IIC0_RXI               = (0x1DF), // Receive
+    ELC_EVENT_I3C0_TX                = (0x1E0), // Transmit
+    ELC_EVENT_IIC0_TXI               = (0x1E0), // Transmit
+    ELC_EVENT_I3C0_RCV_STATUS        = (0x1E1), // Receive status buffer full
+    ELC_EVENT_I3C0_HRESP             = (0x1E2), // High priority Response status buffer full
+    ELC_EVENT_I3C0_HCMD              = (0x1E3), // High priority Command buffer empty
+    ELC_EVENT_I3C0_HRX               = (0x1E4), // High priority RX buffer full
+    ELC_EVENT_I3C0_HTX               = (0x1E5), // High priority TX buffer empty
+    ELC_EVENT_I3C0_TEND              = (0x1E6), // Transmit end
+    ELC_EVENT_IIC0_TEI               = (0x1E6), // Transmit end
+    ELC_EVENT_I3C0_EEI               = (0x1E7), // Error
+    ELC_EVENT_IIC0_ERI               = (0x1E7), // Error
+    ELC_EVENT_I3C0_STEV              = (0x1E8), // Synchronous timing
+    ELC_EVENT_I3C0_MREFOVF           = (0x1E9), // MREF Counter overflow
+    ELC_EVENT_I3C0_MREFCPT           = (0x1EA), // MREF Capture
+    ELC_EVENT_I3C0_AMEV              = (0x1EB), // Additional Master-initiated bus event
+    ELC_EVENT_I3C0_WU                = (0x1EC), // Wake-up condition detection
+    ELC_EVENT_TRNG_RDREQ             = (0x1F3),
+} elc_event_t;
+
+/** @} (end addtogroup BSP_MCU_RA4E2) */
+
+#endif
diff --git a/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h
new file mode 100644
index 000000000..7f02151f5
--- /dev/null
+++ b/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h
@@ -0,0 +1,413 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef BSP_FEATURE_H
+#define BSP_FEATURE_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration */
+#if (BSP_CFG_XTAL_HZ > (19999999))
+ #define CGC_MAINCLOCK_DRIVE    (0x00U)
+#elif (BSP_CFG_XTAL_HZ > (15999999)) && (BSP_CFG_XTAL_HZ < (20000000))
+ #define CGC_MAINCLOCK_DRIVE    (0x01U)
+#elif (BSP_CFG_XTAL_HZ > (7999999)) && (BSP_CFG_XTAL_HZ < (16000000))
+ #define CGC_MAINCLOCK_DRIVE    (0x02U)
+#else
+ #define CGC_MAINCLOCK_DRIVE    (0x03U)
+#endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US                  (0U) // Feature not available on this MCU
+#define BSP_FEATURE_ACMPHS_VREF                              (0U) // Feature not available on this MCU
+
+#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS             (0)  // Feature not available on this MCU
+#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US                  (0)  // Feature not available on this MCU
+
+#define BSP_FEATURE_ADC_ADDITION_SUPPORTED                   (1U)
+#define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK             (0U)
+#define BSP_FEATURE_ADC_B_TSN_SLOPE                          (0U)
+#define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS                    (0U)
+#define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS                    (0U)
+#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE            (0U)
+#define BSP_FEATURE_ADC_CLOCK_SOURCE                         (FSP_PRIV_CLOCK_PCLKC)
+#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED              (1U)
+#define BSP_FEATURE_ADC_HAS_ADBUF                            (1U)
+#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC                      (1U)
+#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT                     (1U)
+#define BSP_FEATURE_ADC_HAS_ADHVREFCNT                       (0U)
+#define BSP_FEATURE_ADC_HAS_PGA                              (1U)
+#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG                  (1U)
+#define BSP_FEATURE_ADC_HAS_VREFAMPCNT                       (0U)
+#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS                  (12U)
+#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE                    (0U)
+#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME             (4150U)
+#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE          (1U)
+#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK               (0x0000FFFFU)
+#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE            (1U)          // TSCDR is a 32-bit register on this MCU
+#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE                (1U)
+#define BSP_FEATURE_ADC_TSN_SLOPE                            (4000)
+#define BSP_FEATURE_ADC_UNIT_0_CHANNELS                      (0x000139F7U) // 0 to 2, 4 to 8, 11 to 13, 16
+#define BSP_FEATURE_ADC_UNIT_1_CHANNELS                      (0)
+#define BSP_FEATURE_ADC_VALID_UNIT_MASK                      (1U)
+
+#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT                   (2)
+#define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                      (1)
+#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT                     (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
+#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                   (0x3U)
+
+#define BSP_FEATURE_BSP_FLASH_CACHE                          (1)
+#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM              (0U)
+#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER                (0)
+#define BSP_FEATURE_BSP_HAS_ADC_CLOCK                        (0)
+#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK                      (1)
+#define BSP_FEATURE_BSP_HAS_CEC_CLOCK                        (1)
+#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB               (0U)
+#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE                (1)
+#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR                   (0U)
+#define BSP_FEATURE_BSP_HAS_DTCM                             (0) // Feature not available on this MCU
+#define BSP_FEATURE_BSP_HAS_GPT_CLOCK                        (0) // Mutually exclusive with USB60 Clock
+#define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN                  (0)
+#define BSP_FEATURE_BSP_HAS_I3C_CLOCK                        (1)
+#define BSP_FEATURE_BSP_HAS_IIC_CLOCK                        (0U)
+#define BSP_FEATURE_BSP_HAS_ITCM                             (0) // Feature not available on this MCU
+#define BSP_FEATURE_BSP_HAS_LCD_CLOCK                        (0)
+#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK                    (0)
+#define BSP_FEATURE_BSP_HAS_OFS2                             (0)
+#define BSP_FEATURE_BSP_HAS_OFS3                             (0)
+#define BSP_FEATURE_BSP_HAS_SCE5                             (0) // Feature not available on this MCU
+#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2                       (0) // Feature not available on this MCU
+#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK                     (0)
+#define BSP_FEATURE_BSP_HAS_SCI_CLOCK                        (0)
+#define BSP_FEATURE_BSP_HAS_SECURITY_MPU                     (0U)
+#define BSP_FEATURE_BSP_HAS_SPI_CLOCK                        (0)
+#define BSP_FEATURE_BSP_HAS_SP_MON                           (0U)
+#define BSP_FEATURE_BSP_HAS_SYRACCR                          (0U)
+#define BSP_FEATURE_BSP_HAS_TZFSAR                           (1)
+#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ                  (0U) // Feature not available on this MCU
+#define BSP_FEATURE_BSP_HAS_USBCKDIVCR                       (1U) // On the RA4E2 there are specific registers for configuring the USB clock.
+#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV                    (1U)
+#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ                    (1U)
+#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL                    (1U)
+#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT                (0U)
+#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION            (0U)
+#define BSP_FEATURE_BSP_MPU_REGION0_MASK                     (0U) // Feature not available on this MCU
+#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH               (0U) // If MSTPRE is present than the setting is not valid.
+#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE                     (1U)
+#define BSP_FEATURE_BSP_NUM_PMSAR                            (9U)
+#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK                    (0xFFFFF9FFU)
+#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET                  (9U)
+#define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION         (0U)
+#define BSP_FEATURE_BSP_OSIS_PADDING                         (0U)
+#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED           (0U)
+#define BSP_FEATURE_BSP_RESET_TRNG                           (0U)
+#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS        (0U)         // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option).
+#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS        (0U)         // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option).
+#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS          (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC.
+#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS         (50000000U)  // The maximum frequency allowed without having one ROM wait cycle.
+#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS       (0U)         // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option).
+#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS         (0U)         // The maximum frequency allowed without having two ROM wait cycles.
+#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET                     (0U)
+#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER                    (0x01008190U)
+#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP            (0U)
+
+#define BSP_FEATURE_CANFD_FD_SUPPORT                         (BSP_MCU_FEATURE_SET == 'B')
+#define BSP_FEATURE_CANFD_LITE                               (1U)
+#define BSP_FEATURE_CANFD_NUM_CHANNELS                       (1U)
+#define BSP_FEATURE_CANFD_NUM_INSTANCES                      (1U)
+
+#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO                    (0U)
+#define BSP_FEATURE_CAN_CLOCK                                (0U)
+#define BSP_FEATURE_CAN_MCLOCK_ONLY                          (0U)
+#define BSP_FEATURE_CAN_NUM_CHANNELS                         (0U) // RA4E2 has CAN-FD
+
+#define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO                    (1)
+#define BSP_FEATURE_CGC_HAS_BCLK                             (0U)
+#define BSP_FEATURE_CGC_HAS_CPUCLK                           (0U)
+#define BSP_FEATURE_CGC_HAS_FCLK                             (1U)
+#define BSP_FEATURE_CGC_HAS_FLDWAITR                         (0U)
+#define BSP_FEATURE_CGC_HAS_FLL                              (1U)
+#define BSP_FEATURE_CGC_HAS_FLWT                             (1U)
+#define BSP_FEATURE_CGC_HAS_HOCOWTCR                         (0U)
+#define BSP_FEATURE_CGC_HAS_MEMWAIT                          (0U)
+#define BSP_FEATURE_CGC_HAS_PCLKA                            (1U)
+#define BSP_FEATURE_CGC_HAS_PCLKB                            (1U)
+#define BSP_FEATURE_CGC_HAS_PCLKC                            (1U)
+#define BSP_FEATURE_CGC_HAS_PCLKD                            (1U)
+#define BSP_FEATURE_CGC_HAS_PCLKE                            (0U)
+#define BSP_FEATURE_CGC_HAS_PLL                              (1U)
+#define BSP_FEATURE_CGC_HAS_PLL2                             (0U)
+#define BSP_FEATURE_CGC_HAS_SOPCCR                           (1U)
+#define BSP_FEATURE_CGC_HAS_SOSC                             (1U)
+#define BSP_FEATURE_CGC_HAS_SRAMPRCR2                        (1U) // On the RA4E2 there is another register to enable write access for SRAMWTSC.
+#define BSP_FEATURE_CGC_HAS_SRAMWTSC                         (1U)
+#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR                  (0U)
+#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY                  (0U)
+#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE            (0)
+#define BSP_FEATURE_CGC_HOCOWTCR_VALUE                       (6U)
+#define BSP_FEATURE_CGC_ICLK_DIV_RESET                       (BSP_CLOCKS_SYS_CLOCK_DIV_4)
+#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US            (61U)
+#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ                (1000000U) // This MCU does have Low Speed Mode, up to 1MHz
+#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ              (0U)       // This MCU does not have Low Voltage Mode
+#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ             (0U)       // This MCU does not have Middle Speed Mode
+#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US            (15U)
+#define BSP_FEATURE_CGC_MODRV_MASK                           (0x30U)
+#define BSP_FEATURE_CGC_MODRV_SHIFT                          (0x4U)
+#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ                        (240000000U)
+#define BSP_FEATURE_CGC_PLLCCR_TYPE                          (1U)
+#define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ                    (240000000U)
+#define BSP_FEATURE_CGC_PLLCCR_WAIT_US                       (0U) // No wait between setting PLLCCR and clearing PLLSTP
+#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB          (0)
+#define BSP_FEATURE_CGC_SODRV_MASK                           (0x02U)
+#define BSP_FEATURE_CGC_SODRV_SHIFT                          (0x01U)
+#define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET                   (1)
+#define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE                    (0x78)
+#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE                   (0)
+
+#define BSP_FEATURE_CRYPTO_HAS_AES                           (0)
+#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED                   (0)
+#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG                      (0)
+#define BSP_FEATURE_CRYPTO_HAS_ECC                           (0)
+#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED                   (0)
+#define BSP_FEATURE_CRYPTO_HAS_HASH                          (0)
+#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS                     (0) // Feature not available on this MCU
+#define BSP_FEATURE_CRYPTO_HAS_RSA                           (0)
+#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED                   (0)
+#define BSP_FEATURE_CRYPTO_AES_IP_VERSION                    (0)
+#define BSP_FEATURE_CRYPTO_HAS_SCE5                          (0)
+#define BSP_FEATURE_CRYPTO_HAS_SCE5B                         (0)
+#define BSP_FEATURE_CRYPTO_HAS_SCE7                          (0)
+#define BSP_FEATURE_CRYPTO_HAS_SCE9                          (0)
+
+#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT             (0U) // Feature not available on this MCU
+#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT            (0U) // Feature not available on this MCU
+#define BSP_FEATURE_CTSU_HAS_TXVSEL                          (0)  // Feature not available on this MCU
+#define BSP_FEATURE_CTSU_VERSION                             (0)  // Feature not available on this MCU
+
+#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP                      (0)  // Feature not available on this MCU
+#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE               (0)  // Feature not available on this MCU
+#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE                   (0)  // Feature not available on this MCU
+#define BSP_FEATURE_DAC8_MAX_CHANNELS                        (0)  // Feature not available on this MCU
+
+#define BSP_FEATURE_DAC_HAS_CHARGEPUMP                       (0U)
+#define BSP_FEATURE_DAC_HAS_DAVREFCR                         (0U)
+#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE                (1U)
+#define BSP_FEATURE_DAC_HAS_INTERNAL_OUTPUT                  (1U)
+#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER                 (1U)
+#define BSP_FEATURE_DAC_MAX_CHANNELS                         (1U)
+
+#define BSP_FEATURE_DMAC_HAS_DELSR                           (0U)
+#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE               (1U)
+#define BSP_FEATURE_DMAC_MAX_CHANNEL                         (8U)
+
+#define BSP_FEATURE_DOC_VERSION                              (1U)
+
+#define BSP_FEATURE_DWT_CYCCNT                               (1U)          // RA4E2 has Data Watchpoint Cycle Count Register
+
+#define BSP_FEATURE_ELC_PERIPHERAL_MASK                      (0x0083F3FFU) // Positions of event link set registers (ELSRs) available on this MCU
+#define BSP_FEATURE_ELC_VERSION                              (1U)
+
+#define BSP_FEATURE_ETHER_FIFO_DEPTH                         (0U)          // Feature not available on this MCU
+#define BSP_FEATURE_ETHER_MAX_CHANNELS                       (0U)          // Feature not available on this MCU
+#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE                 (0)           // Feature not available on this MCU
+
+#define BSP_FEATURE_FLASH_CODE_FLASH_START                   (0x0U)
+#define BSP_FEATURE_FLASH_DATA_FLASH_START                   (0x08000000U)
+#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START              (0x0U)
+#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE           (0x2000U)
+#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE                 (0x10000U)
+#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE           (0x8000U)
+#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE                   (128U)
+#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE                   (64U)
+#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE                   (4U)
+#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT                     (1)
+#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK              (0)
+#define BSP_FEATURE_FLASH_HP_VERSION                         (40U)
+#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK                    (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT                   (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE                   (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE                   (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE                   (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE                   (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC                 (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_VERSION                         (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW             (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE                   (1) // Feature not available on this MCU
+
+#define BSP_FEATURE_GPTEH_CHANNEL_MASK                       (0)
+
+#define BSP_FEATURE_GPTE_CHANNEL_MASK                        (0x33U)
+
+#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK                   (0x00U)
+#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE              (2U)
+#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID        (0U)
+#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK             (BSP_FEATURE_GPT_VALID_CHANNEL_MASK)
+#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN                  (0U) // Feature not available on this MCU
+#define BSP_FEATURE_GPT_ODC_FREQ_MAX                         (0U) // Feature not available on this MCU
+#define BSP_FEATURE_GPT_ODC_FREQ_MIN                         (0U) // Feature not available on this MCU
+#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK               (0U) // Feature not available on this MCU
+#define BSP_FEATURE_GPT_TPCS_SHIFT                           (0U)
+#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK                   (0x33U)
+
+#define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (8U)
+#define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (16U)
+#define BSP_FEATURE_I3C_NUM_CHANNELS                         (1U)
+#define BSP_FEATURE_I3C_MSTP_OFFSET                          (4U)
+
+#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS                 (0U)
+#define BSP_FEATURE_ICU_HAS_WUPEN1                           (1U)
+#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK                    (0x7FFFU)
+#define BSP_FEATURE_ICU_WUPEN_MASK                           (0x8007B0D7FFFULL) // Note there is another WUPEN1 register
+#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT                    (0U)
+
+#define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER             (5U)
+#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS                     (0x01)
+#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK                 (0x01)
+#define BSP_FEATURE_IIC_FAST_MODE_PLUS                       (0)
+#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK                   (0)
+#define BSP_FEATURE_IIC_VERSION                              (2)
+
+#define BSP_FEATURE_IOPORT_ELC_PORTS                         (0x001EU)
+#define BSP_FEATURE_IOPORT_HAS_ETHERNET                      (0U)
+#define BSP_FEATURE_IOPORT_VERSION                           (1U)
+
+#define BSP_FEATURE_IWDT_CLOCK_FREQUENCY                     (15000UL)
+#define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE        (0U) // Feature not available on this MCU
+
+#define BSP_FEATURE_KINT_HAS_MSTP                            (0U)
+
+#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY                    (0U)
+#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED                 (0U)
+#define BSP_FEATURE_LPM_DPSIEGR_MASK                         (0x135FF3U)
+#define BSP_FEATURE_LPM_DPSIER_MASK                          (0x051F5FF3U)
+#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP                       (0U)
+#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY                     (1U)
+#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT                  (1U)
+#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY                    (1U)
+#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP                   (0U)
+#define BSP_FEATURE_LPM_HAS_LDO_CONTROL                      (0U)
+#define BSP_FEATURE_LPM_HAS_LPSCR                            (0U)
+#define BSP_FEATURE_LPM_HAS_PDRAMSCR                         (0U)
+#define BSP_FEATURE_LPM_HAS_SBYCR_OPE                        (0U)
+#define BSP_FEATURE_LPM_HAS_SBYCR_SSBY                       (1U)
+#define BSP_FEATURE_LPM_HAS_SNOOZE                           (1U)
+#define BSP_FEATURE_LPM_HAS_SNZEDCR1                         (0U)
+#define BSP_FEATURE_LPM_HAS_SNZREQCR1                        (0U)
+#define BSP_FEATURE_LPM_HAS_STCONR                           (0U)
+#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14                     (1U)
+#define BSP_FEATURE_LPM_SNZEDCR_MASK                         (0x0000009FU)
+#define BSP_FEATURE_LPM_SNZREQCR_MASK                        (0x73007FFFU)
+#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED                (0U)
+
+#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER                   (1U)
+#define BSP_FEATURE_LVD_HAS_LVDLVLR                          (0U)
+#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD               (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V
+#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD              (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V
+#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD               (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V
+#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD              (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V
+#define BSP_FEATURE_LVD_STABILIZATION_TIME_US                (10U)                                 // Time in microseconds required for LVD to stabalize
+
+#define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS                   (0U)
+#define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS                   (0U)
+
+#define BSP_FEATURE_OPAMP_BASE_ADDRESS                       (0U)
+#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED                   (0) // Feature not available on this MCU
+#define BSP_FEATURE_OPAMP_HAS_SWITCHES                       (0U)
+#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL                  (0U)
+#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US                (0) // Feature not available on this MCU
+#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US                (0) // Feature not available on this MCU
+#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US                (0) // Feature not available on this MCU
+#define BSP_FEATURE_OPAMP_TRIM_CAPABLE                       (0U)
+#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK               (0U)
+
+#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS              (0x0U)
+#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS              (0x0U)
+
+#define BSP_FEATURE_POEG_CHANNEL_MASK                        (0xFU)
+
+#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS                (0x0U)
+
+#define BSP_FEATURE_HAS_RTC                                  (1U)
+#define BSP_FEATURE_RTC_HAS_ROPSEL                           (0U)
+#define BSP_FEATURE_RTC_HAS_TCEN                             (1U)
+#define BSP_FEATURE_RTC_RTCCR_CHANNELS                       (2U)
+#define BSP_FEATURE_SYSC_HAS_VBTICTLR                        (0U)
+
+#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS               (0x201U)
+#define BSP_FEATURE_SCI_CHANNELS                             (0x201U)
+#define BSP_FEATURE_SCI_CLOCK                                (FSP_PRIV_CLOCK_PCLKA)
+#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS                 (0x201U)
+#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS                   (0x201U)
+#define BSP_FEATURE_SCI_UART_FIFO_DEPTH                      (16U)
+#define BSP_FEATURE_SCI_VERSION                              (1U)
+
+#define BSP_FEATURE_SDHI_CLOCK                               (0)    // Feature not available on this MCU
+#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION                  (0)    // Feature not available on this MCU
+#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT            (0)    // Feature not available on this MCU
+#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC                  (0)    // Feature not available on this MCU
+#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK                  (0)    // Feature not available on this MCU
+
+#define BSP_FEATURE_SDRAM_START_ADDRESS                      (0x0U) // Feature not available on this MCU
+
+#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE                   (0)    // Feature not available on this MCU
+#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN              (0)    // Feature not available on this MCU
+#define BSP_FEATURE_SLCDC_MAX_NUM_SEG                        (0)    // Feature not available on this MCU
+
+#define BSP_FEATURE_SPI_CLK                                  (FSP_PRIV_CLOCK_PCLKA)
+#define BSP_FEATURE_SPI_HAS_SPCR3                            (1U)
+#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP                   (1U)
+#define BSP_FEATURE_SPI_MAX_CHANNEL                          (2U)
+#define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK    (0x3U)
+
+#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE          (0x01U)
+
+#define BSP_FEATURE_SSI_FIFO_NUM_STAGES                      (32U)
+#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK                   (0x01U)
+
+#define BSP_FEATURE_TFU_SUPPORTED                            (0U)
+
+#define BSP_FEATURE_TRNG_HAS_MODULE_STOP                     (1U)
+#define BSP_FEATURE_TZ_HAS_TRUSTZONE                         (1U)
+#define BSP_FEATURE_TZ_HAS_DLM                               (0U)
+
+#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM                     (0)
+#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK                  (0U)
+
+#define BSP_FEATURE_CRC_HAS_SNOOP                            (0U)
+#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR               (0x0U)
+
+#endif
diff --git a/ra/fsp/src/bsp/mcu/ra4e2/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra4e2/bsp_mcu_info.h
new file mode 100644
index 000000000..599a749d7
--- /dev/null
+++ b/ra/fsp/src/bsp/mcu/ra4e2/bsp_mcu_info.h
@@ -0,0 +1,58 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup BSP_MCU
+ * @defgroup BSP_MCU_RA4E2 RA4E2
+ * @includedoc config_bsp_ra4e2_fsp.html
+ * @{
+ **********************************************************************************************************************/
+
+/** @} (end defgroup BSP_MCU_RA4E2) */
+
+#ifndef BSP_MCU_INFO_H
+#define BSP_MCU_INFO_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/* BSP MCU Specific Includes. */
+#include "bsp_elc.h"
+#include "bsp_feature.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+typedef elc_event_t bsp_interrupt_event_t;
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+#endif
diff --git a/ra/fsp/src/bsp/mcu/ra4m1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra4m1/bsp_elc.h
index b2e603431..edf704c7f 100644
--- a/ra/fsp/src/bsp/mcu/ra4m1/bsp_elc.h
+++ b/ra/fsp/src/bsp/mcu/ra4m1/bsp_elc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h
index b8c1f4c53..6ad823147 100644
--- a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h
+++ b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -81,8 +81,9 @@
 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS                      (0)
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                      (1U)
 
-#define BSP_FEATURE_AGT_HAS_AGTW                             (0U)
+#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT                   (0)
 #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                      (1)
+#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT                     (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                   (0x03)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                          (1)
@@ -127,7 +128,6 @@
 #define BSP_FEATURE_BSP_NUM_PMSAR                            (0U)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK                    (0xFFFF8FFFU)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET                  (12U)
-#define BSP_FEATURE_BSP_HAS_OSIS_REG                         (1U)
 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION         (0U)
 #define BSP_FEATURE_BSP_OSIS_PADDING                         (1)
 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED           (0U)
@@ -206,6 +206,7 @@
 #define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS                     (0) // Feature not available on this MCU TODO_CHECK_FEATURE
 #define BSP_FEATURE_CRYPTO_HAS_RSA                           (0)
 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED                   (0)
+#define BSP_FEATURE_CRYPTO_AES_IP_VERSION                    (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5                          (1)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5B                         (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE7                          (0)
@@ -285,6 +286,7 @@
 #define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NUM_CHANNELS                         (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_MSTP_OFFSET                          (0U) // Feature not available on this MCU
 
 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS                 (0U)
 #define BSP_FEATURE_ICU_HAS_WUPEN1                           (0U)
@@ -359,7 +361,11 @@
 
 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS                (0x0U)
 
+#define BSP_FEATURE_HAS_RTC                                  (1U)
 #define BSP_FEATURE_RTC_HAS_ROPSEL                           (0U)
+#define BSP_FEATURE_RTC_HAS_TCEN                             (1U)
+#define BSP_FEATURE_RTC_RTCCR_CHANNELS                       (3U)
+#define BSP_FEATURE_SYSC_HAS_VBTICTLR                        (1U)
 
 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS               (BSP_FEATURE_SCI_CHANNELS)
 #define BSP_FEATURE_SCI_CHANNELS                             (0x207U)
@@ -396,7 +402,13 @@
 #define BSP_FEATURE_TFU_SUPPORTED                            (0U) // Trigonometric Function Unit (TFU) not available on this MCU
 
 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP                     (0U)
-
 #define BSP_FEATURE_TZ_HAS_TRUSTZONE                         (0U)
+#define BSP_FEATURE_TZ_HAS_DLM                               (0U)
+
+#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM                     (0)
+#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK                  (0U)
+
+#define BSP_FEATURE_CRC_HAS_SNOOP                            (1U)
+#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR               (0x3U)
 
 #endif
diff --git a/ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h
index 3eb04c0f1..903208e1d 100644
--- a/ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h
+++ b/ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra4m2/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra4m2/bsp_elc.h
index f9a76af5f..2c8090699 100644
--- a/ra/fsp/src/bsp/mcu/ra4m2/bsp_elc.h
+++ b/ra/fsp/src/bsp/mcu/ra4m2/bsp_elc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h
index 2b1ba0e29..53ca1c97b 100644
--- a/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h
+++ b/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -85,8 +85,9 @@
 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS                      (0)
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                      (1U)
 
-#define BSP_FEATURE_AGT_HAS_AGTW                             (0U)
+#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT                   (0)
 #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                      (5)
+#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT                     (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                   (0x3F)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                          (1)
@@ -131,7 +132,6 @@
 #define BSP_FEATURE_BSP_NUM_PMSAR                            (8U)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK                    (0xFFFFF9FFU)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET                  (9U)
-#define BSP_FEATURE_BSP_HAS_OSIS_REG                         (0U)
 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION         (1U)
 #define BSP_FEATURE_BSP_OSIS_PADDING                         (0U)
 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED           (0U)
@@ -208,6 +208,7 @@
 #define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS                     (0) // Feature not available on this MCU TODO_CHECK_FEATURE
 #define BSP_FEATURE_CRYPTO_HAS_RSA                           (1)
 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED                   (1)
+#define BSP_FEATURE_CRYPTO_AES_IP_VERSION                    (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5                          (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5B                         (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE7                          (0)
@@ -287,6 +288,7 @@
 #define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NUM_CHANNELS                         (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_MSTP_OFFSET                          (0U) // Feature not available on this MCU
 
 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS                 (0U)
 #define BSP_FEATURE_ICU_HAS_WUPEN1                           (1U)
@@ -361,7 +363,11 @@
 
 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS                (0x60000000U)
 
+#define BSP_FEATURE_HAS_RTC                                  (1U)
 #define BSP_FEATURE_RTC_HAS_ROPSEL                           (0U)
+#define BSP_FEATURE_RTC_HAS_TCEN                             (0U)
+#define BSP_FEATURE_RTC_RTCCR_CHANNELS                       (0U)
+#define BSP_FEATURE_SYSC_HAS_VBTICTLR                        (1U)
 
 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS               (0x219U)
 #define BSP_FEATURE_SCI_CHANNELS                             (0x21FU)
@@ -374,7 +380,7 @@
 #define BSP_FEATURE_SDHI_CLOCK                               (FSP_PRIV_CLOCK_PCLKB)
 #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION                  (1U)
 #define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT            (0U) // 1 (2^0) is minimum division supported
-#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC                  (1U)
+#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC                  (0U) // ra4m2 does not support 8-bit MMC
 #define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK                  (0x01U)
 
 #define BSP_FEATURE_SDRAM_START_ADDRESS                      (0x0U)
@@ -398,7 +404,13 @@
 #define BSP_FEATURE_TFU_SUPPORTED                            (0U) // Trigonometric Function Unit (TFU) not available on this MCU
 
 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP                     (0U)
-
 #define BSP_FEATURE_TZ_HAS_TRUSTZONE                         (1U)
+#define BSP_FEATURE_TZ_HAS_DLM                               (1U)
+
+#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM                     (0)
+#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK                  (0U)
+
+#define BSP_FEATURE_CRC_HAS_SNOOP                            (0U)
+#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR               (0x0U)
 
 #endif
diff --git a/ra/fsp/src/bsp/mcu/ra4m2/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra4m2/bsp_mcu_info.h
index 2f3f34027..970ff2d0e 100644
--- a/ra/fsp/src/bsp/mcu/ra4m2/bsp_mcu_info.h
+++ b/ra/fsp/src/bsp/mcu/ra4m2/bsp_mcu_info.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra4m3/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra4m3/bsp_elc.h
index 48e326b35..d7b7306e4 100644
--- a/ra/fsp/src/bsp/mcu/ra4m3/bsp_elc.h
+++ b/ra/fsp/src/bsp/mcu/ra4m3/bsp_elc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h
index 8a06f7a97..11a24c53f 100644
--- a/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h
+++ b/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -85,8 +85,9 @@
 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS                      (0x7F0007) // 0 to 2, 16 to 22
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                      (3U)
 
-#define BSP_FEATURE_AGT_HAS_AGTW                             (0U)
+#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT                   (0)
 #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                      (5)
+#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT                     (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                   (0x3F)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                          (1)
@@ -131,7 +132,6 @@
 #define BSP_FEATURE_BSP_NUM_PMSAR                            (9U)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK                    (0xFFFFF9FFU)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET                  (9U)
-#define BSP_FEATURE_BSP_HAS_OSIS_REG                         (0U)
 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION         (1U)
 #define BSP_FEATURE_BSP_OSIS_PADDING                         (0U)
 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED           (0U)
@@ -208,6 +208,7 @@
 #define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS                     (0) // Feature not available on this MCU TODO_CHECK_FEATURE
 #define BSP_FEATURE_CRYPTO_HAS_RSA                           (1)
 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED                   (1)
+#define BSP_FEATURE_CRYPTO_AES_IP_VERSION                    (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5                          (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5B                         (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE7                          (0)
@@ -287,6 +288,7 @@
 #define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NUM_CHANNELS                         (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_MSTP_OFFSET                          (0U) // Feature not available on this MCU
 
 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS                 (0U)
 #define BSP_FEATURE_ICU_HAS_WUPEN1                           (1U)
@@ -361,7 +363,11 @@
 
 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS                (0x60000000U)
 
+#define BSP_FEATURE_HAS_RTC                                  (1U)
 #define BSP_FEATURE_RTC_HAS_ROPSEL                           (0U)
+#define BSP_FEATURE_RTC_HAS_TCEN                             (1U)
+#define BSP_FEATURE_RTC_RTCCR_CHANNELS                       (3U)
+#define BSP_FEATURE_SYSC_HAS_VBTICTLR                        (1U)
 
 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS               (0x219U)
 #define BSP_FEATURE_SCI_CHANNELS                             (0x21FU)
@@ -398,7 +404,13 @@
 #define BSP_FEATURE_TFU_SUPPORTED                            (0U) // Trigonometric Function Unit (TFU) not available on this MCU
 
 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP                     (0U)
-
 #define BSP_FEATURE_TZ_HAS_TRUSTZONE                         (1U)
+#define BSP_FEATURE_TZ_HAS_DLM                               (1U)
+
+#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM                     (0)
+#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK                  (0U)
+
+#define BSP_FEATURE_CRC_HAS_SNOOP                            (0U)
+#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR               (0x0U)
 
 #endif
diff --git a/ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h
index cdf21a8ec..f49c7333c 100644
--- a/ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h
+++ b/ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra4w1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra4w1/bsp_elc.h
index f01423bcd..f9b95de1f 100644
--- a/ra/fsp/src/bsp/mcu/ra4w1/bsp_elc.h
+++ b/ra/fsp/src/bsp/mcu/ra4w1/bsp_elc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h
index 460a5340d..f2c781dd3 100644
--- a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h
+++ b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -81,8 +81,9 @@
 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS                      (0)
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                      (1U)
 
-#define BSP_FEATURE_AGT_HAS_AGTW                             (0U)
+#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT                   (0)
 #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                      (1)
+#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT                     (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                   (0x03)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                          (1U)
@@ -127,7 +128,6 @@
 #define BSP_FEATURE_BSP_NUM_PMSAR                            (0U)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK                    (0xFFFF8FFFU)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET                  (12U)
-#define BSP_FEATURE_BSP_HAS_OSIS_REG                         (1U)
 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION         (0U)
 #define BSP_FEATURE_BSP_OSIS_PADDING                         (1)
 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED           (0U)
@@ -206,6 +206,7 @@
 #define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS                     (0) // Feature not available on this MCU TODO_CHECK_FEATURE
 #define BSP_FEATURE_CRYPTO_HAS_RSA                           (0)
 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED                   (0)
+#define BSP_FEATURE_CRYPTO_AES_IP_VERSION                    (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5                          (1)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5B                         (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE7                          (0)
@@ -285,6 +286,7 @@
 #define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NUM_CHANNELS                         (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_MSTP_OFFSET                          (0U) // Feature not available on this MCU
 
 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS                 (0U)
 #define BSP_FEATURE_ICU_HAS_WUPEN1                           (0U)
@@ -359,7 +361,11 @@
 
 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS                (0x0U)
 
+#define BSP_FEATURE_HAS_RTC                                  (1U)
 #define BSP_FEATURE_RTC_HAS_ROPSEL                           (0U)
+#define BSP_FEATURE_RTC_HAS_TCEN                             (1U)
+#define BSP_FEATURE_RTC_RTCCR_CHANNELS                       (1U)
+#define BSP_FEATURE_SYSC_HAS_VBTICTLR                        (1U)
 
 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS               (BSP_FEATURE_SCI_CHANNELS)
 #define BSP_FEATURE_SCI_CHANNELS                             (0x213U)
@@ -396,7 +402,13 @@
 #define BSP_FEATURE_TFU_SUPPORTED                            (0U) // Trigonometric Function Unit (TFU) not available on this MCU
 
 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP                     (0U)
-
 #define BSP_FEATURE_TZ_HAS_TRUSTZONE                         (0U)
+#define BSP_FEATURE_TZ_HAS_DLM                               (0U)
+
+#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM                     (0)
+#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK                  (0U)
+
+#define BSP_FEATURE_CRC_HAS_SNOOP                            (1U)
+#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR               (0x3U)
 
 #endif
diff --git a/ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h
index be2712bff..d373a186f 100644
--- a/ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h
+++ b/ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra6e1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6e1/bsp_elc.h
index 5194cc8db..0d04c9b47 100644
--- a/ra/fsp/src/bsp/mcu/ra6e1/bsp_elc.h
+++ b/ra/fsp/src/bsp/mcu/ra6e1/bsp_elc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h
index b76b7c29d..b43b23c2a 100644
--- a/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h
+++ b/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -85,8 +85,9 @@
 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS                      (0)      // Feature not available on this MCU
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                      (1U)
 
-#define BSP_FEATURE_AGT_HAS_AGTW                             (0)      // Feature not available on this MCU TODO_CHECK_FEATURE
+#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT                   (0)
 #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                      (5)
+#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT                     (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                   (0x3F)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                          (1)
@@ -131,7 +132,6 @@
 #define BSP_FEATURE_BSP_NUM_PMSAR                            (8U)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK                    (0xFFFFF9FFU)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET                  (9U)
-#define BSP_FEATURE_BSP_HAS_OSIS_REG                         (0U)
 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION         (1U)
 #define BSP_FEATURE_BSP_OSIS_PADDING                         (0U)
 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED           (0U)
@@ -208,6 +208,7 @@
 #define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS                     (0) // Feature not available on this MCU TODO_CHECK_FEATURE
 #define BSP_FEATURE_CRYPTO_HAS_RSA                           (0)
 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED                   (0)
+#define BSP_FEATURE_CRYPTO_AES_IP_VERSION                    (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5                          (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5B                         (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE7                          (0)
@@ -287,6 +288,7 @@
 #define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NUM_CHANNELS                         (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_MSTP_OFFSET                          (0U) // Feature not available on this MCU
 
 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS                 (0U)
 #define BSP_FEATURE_ICU_HAS_WUPEN1                           (1U)
@@ -361,7 +363,11 @@
 
 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS                (0x60000000U)
 
+#define BSP_FEATURE_HAS_RTC                                  (1U)
 #define BSP_FEATURE_RTC_HAS_ROPSEL                           (0U)
+#define BSP_FEATURE_RTC_HAS_TCEN                             (1U)
+#define BSP_FEATURE_RTC_RTCCR_CHANNELS                       (3U)
+#define BSP_FEATURE_SYSC_HAS_VBTICTLR                        (1U)
 
 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS               (0x219U)
 #define BSP_FEATURE_SCI_CHANNELS                             (0x21FU)
@@ -398,7 +404,13 @@
 #define BSP_FEATURE_TFU_SUPPORTED                            (0U) // Trigonometric Function Unit (TFU) not available on this MCU
 
 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP                     (0U)
-
 #define BSP_FEATURE_TZ_HAS_TRUSTZONE                         (1U)
+#define BSP_FEATURE_TZ_HAS_DLM                               (1U)
+
+#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM                     (0)
+#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK                  (0U)
+
+#define BSP_FEATURE_CRC_HAS_SNOOP                            (0U)
+#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR               (0x0U)
 
 #endif
diff --git a/ra/fsp/src/bsp/mcu/ra6e1/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra6e1/bsp_mcu_info.h
index a67f3e705..cd388c396 100644
--- a/ra/fsp/src/bsp/mcu/ra6e1/bsp_mcu_info.h
+++ b/ra/fsp/src/bsp/mcu/ra6e1/bsp_mcu_info.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra6e2/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6e2/bsp_elc.h
new file mode 100644
index 000000000..61bc665cc
--- /dev/null
+++ b/ra/fsp/src/bsp/mcu/ra6e2/bsp_elc.h
@@ -0,0 +1,245 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef BSP_ELC_H
+#define BSP_ELC_H
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************
+ * @addtogroup BSP_MCU_RA6E2
+ * @{
+ **********************************************************************************************************************/
+
+/** Sources of event signals to be linked to other peripherals or the CPU
+ * @note This list may change based on based on the device.
+ * */
+typedef enum e_elc_event_ra6e2
+{
+    ELC_EVENT_NONE                   = (0),     // Link disabled
+    ELC_EVENT_ICU_IRQ0               = (0x001), // External pin interrupt 0
+    ELC_EVENT_ICU_IRQ1               = (0x002), // External pin interrupt 1
+    ELC_EVENT_ICU_IRQ2               = (0x003), // External pin interrupt 2
+    ELC_EVENT_ICU_IRQ3               = (0x004), // External pin interrupt 3
+    ELC_EVENT_ICU_IRQ4               = (0x005), // External pin interrupt 4
+    ELC_EVENT_ICU_IRQ5               = (0x006), // External pin interrupt 5
+    ELC_EVENT_ICU_IRQ6               = (0x007), // External pin interrupt 6
+    ELC_EVENT_ICU_IRQ7               = (0x008), // External pin interrupt 7
+    ELC_EVENT_ICU_IRQ8               = (0x009), // External pin interrupt 8
+    ELC_EVENT_ICU_IRQ9               = (0x00A), // External pin interrupt 9
+    ELC_EVENT_ICU_IRQ10              = (0x00B), // External pin interrupt 10
+    ELC_EVENT_ICU_IRQ11              = (0x00C), // External pin interrupt 11
+    ELC_EVENT_ICU_IRQ12              = (0x00D), // External pin interrupt 12
+    ELC_EVENT_ICU_IRQ13              = (0x00E), // External pin interrupt 13
+    ELC_EVENT_ICU_IRQ14              = (0x00F), // External pin interrupt 14
+    ELC_EVENT_DMAC0_INT              = (0x020), // DMAC transfer end 0
+    ELC_EVENT_DMAC1_INT              = (0x021), // DMAC transfer end 1
+    ELC_EVENT_DMAC2_INT              = (0x022), // DMAC transfer end 2
+    ELC_EVENT_DMAC3_INT              = (0x023), // DMAC transfer end 3
+    ELC_EVENT_DMAC4_INT              = (0x024), // DMAC transfer end 4
+    ELC_EVENT_DMAC5_INT              = (0x025), // DMAC transfer end 5
+    ELC_EVENT_DMAC6_INT              = (0x026), // DMAC transfer end 6
+    ELC_EVENT_DMAC7_INT              = (0x027), // DMAC transfer end 7
+    ELC_EVENT_DTC_COMPLETE           = (0x029), // DTC transfer complete
+    ELC_EVENT_DMA_TRANSERR           = (0x02B), // DMA transfer error
+    ELC_EVENT_ICU_SNOOZE_CANCEL      = (0x02D), // Canceling from Snooze mode
+    ELC_EVENT_FCU_FIFERR             = (0x030), // Flash access error interrupt
+    ELC_EVENT_FCU_FRDYI              = (0x031), // Flash ready interrupt
+    ELC_EVENT_LVD_LVD1               = (0x038), // Voltage monitor 1 interrupt
+    ELC_EVENT_LVD_LVD2               = (0x039), // Voltage monitor 2 interrupt
+    ELC_EVENT_CGC_MOSC_STOP          = (0x03B), // Main Clock oscillation stop
+    ELC_EVENT_LPM_SNOOZE_REQUEST     = (0x03C), // Snooze entry
+    ELC_EVENT_AGT0_INT               = (0x040), // AGT interrupt
+    ELC_EVENT_AGT0_COMPARE_A         = (0x041), // Compare match A
+    ELC_EVENT_AGT0_COMPARE_B         = (0x042), // Compare match B
+    ELC_EVENT_AGT1_INT               = (0x043), // AGT interrupt
+    ELC_EVENT_AGT1_COMPARE_A         = (0x044), // Compare match A
+    ELC_EVENT_AGT1_COMPARE_B         = (0x045), // Compare match B
+    ELC_EVENT_IWDT_UNDERFLOW         = (0x052), // IWDT underflow
+    ELC_EVENT_WDT_UNDERFLOW          = (0x053), // WDT underflow
+    ELC_EVENT_RTC_ALARM              = (0x054), // Alarm interrupt
+    ELC_EVENT_RTC_PERIOD             = (0x055), // Periodic interrupt
+    ELC_EVENT_RTC_CARRY              = (0x056), // Carry interrupt
+    ELC_EVENT_CAN_RXF                = (0x059), // Global recieve FIFO interrupt
+    ELC_EVENT_CAN_GLERR              = (0x05A), // Global error
+    ELC_EVENT_CAN_DMAREQ0            = (0x05B), // DMA 0 request
+    ELC_EVENT_CAN_DMAREQ1            = (0x05C), // DMA 1 request
+    ELC_EVENT_CAN0_TX                = (0x063), // Transmit interrupt
+    ELC_EVENT_CAN0_CHERR             = (0x064), // Channel error
+    ELC_EVENT_CAN0_COMFRX            = (0x065), // Common FIFO recieve interrupt
+    ELC_EVENT_CAN0_CF_DMAREQ         = (0x066), // Channel DMA request
+    ELC_EVENT_CAN0_RXMB              = (0x067), // Receive message buffer interrupt
+    ELC_EVENT_USBFS_INT              = (0x06D), // USBFS interrupt
+    ELC_EVENT_USBFS_RESUME           = (0x06E), // USBFS resume interrupt
+    ELC_EVENT_SSI0_TXI               = (0x08A), // Transmit data empty
+    ELC_EVENT_SSI0_RXI               = (0x08B), // Receive data full
+    ELC_EVENT_SSI0_INT               = (0x08D), // Error interrupt
+    ELC_EVENT_CAC_FREQUENCY_ERROR    = (0x09E), // Frequency error interrupt
+    ELC_EVENT_CAC_MEASUREMENT_END    = (0x09F), // Measurement end interrupt
+    ELC_EVENT_CAC_OVERFLOW           = (0x0A0), // Overflow interrupt
+    ELC_EVENT_CEC_INTDA              = (0x0AB), // Data interrupt
+    ELC_EVENT_CEC_INTCE              = (0x0AC), // Communication complete interrupt
+    ELC_EVENT_CEC_INTERR             = (0x0AD), // Error interrupt
+    ELC_EVENT_IOPORT_EVENT_1         = (0x0B1), // Port 1 event
+    ELC_EVENT_IOPORT_EVENT_2         = (0x0B2), // Port 2 event
+    ELC_EVENT_IOPORT_EVENT_3         = (0x0B3), // Port 3 event
+    ELC_EVENT_IOPORT_EVENT_4         = (0x0B4), // Port 4 event
+    ELC_EVENT_ELC_SOFTWARE_EVENT_0   = (0x0B5), // Software event 0
+    ELC_EVENT_ELC_SOFTWARE_EVENT_1   = (0x0B6), // Software event 1
+    ELC_EVENT_POEG0_EVENT            = (0x0B7), // Port Output disable interrupt A
+    ELC_EVENT_POEG1_EVENT            = (0x0B8), // Port Output disable interrupt B
+    ELC_EVENT_POEG2_EVENT            = (0x0B9), // Port Output disable interrupt C
+    ELC_EVENT_POEG3_EVENT            = (0x0BA), // Port Output disable interrupt D
+    ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0C0), // Compare match A
+    ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0C1), // Compare match B
+    ELC_EVENT_GPT0_COMPARE_C         = (0x0C2), // Compare match C
+    ELC_EVENT_GPT0_COMPARE_D         = (0x0C3), // Compare match D
+    ELC_EVENT_GPT0_COMPARE_E         = (0x0C4), // Compare match E
+    ELC_EVENT_GPT0_COMPARE_F         = (0x0C5), // Compare match F
+    ELC_EVENT_GPT0_COUNTER_OVERFLOW  = (0x0C6), // Overflow
+    ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0C7), // Underflow
+    ELC_EVENT_GPT0_PC                = (0x0C8), // Period count function finish
+    ELC_EVENT_GPT0_AD_TRIG_A         = (0x0C9), // A/D converter start request A
+    ELC_EVENT_GPT0_AD_TRIG_B         = (0x0CA), // A/D converter start request B
+    ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0CB), // Compare match A
+    ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CC), // Compare match B
+    ELC_EVENT_GPT1_COMPARE_C         = (0x0CD), // Compare match C
+    ELC_EVENT_GPT1_COMPARE_D         = (0x0CE), // Compare match D
+    ELC_EVENT_GPT1_COMPARE_E         = (0x0CF), // Compare match E
+    ELC_EVENT_GPT1_COMPARE_F         = (0x0D0), // Compare match F
+    ELC_EVENT_GPT1_COUNTER_OVERFLOW  = (0x0D1), // Overflow
+    ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D2), // Underflow
+    ELC_EVENT_GPT1_PC                = (0x0D3), // Period count function finish
+    ELC_EVENT_GPT1_AD_TRIG_A         = (0x0D4), // A/D converter start request A
+    ELC_EVENT_GPT1_AD_TRIG_B         = (0x0D5), // A/D converter start request B
+    ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0D6), // Compare match A
+    ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0D7), // Compare match B
+    ELC_EVENT_GPT2_COMPARE_C         = (0x0D8), // Compare match C
+    ELC_EVENT_GPT2_COMPARE_D         = (0x0D9), // Compare match D
+    ELC_EVENT_GPT2_COMPARE_E         = (0x0DA), // Compare match E
+    ELC_EVENT_GPT2_COMPARE_F         = (0x0DB), // Compare match F
+    ELC_EVENT_GPT2_COUNTER_OVERFLOW  = (0x0DC), // Overflow
+    ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0DD), // Underflow
+    ELC_EVENT_GPT2_AD_TRIG_A         = (0x0DF), // A/D converter start request A
+    ELC_EVENT_GPT2_AD_TRIG_B         = (0x0E0), // A/D converter start request B
+    ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0E1), // Compare match A
+    ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0E2), // Compare match B
+    ELC_EVENT_GPT3_COMPARE_C         = (0x0E3), // Compare match C
+    ELC_EVENT_GPT3_COMPARE_D         = (0x0E4), // Compare match D
+    ELC_EVENT_GPT3_COMPARE_E         = (0x0E5), // Compare match E
+    ELC_EVENT_GPT3_COMPARE_F         = (0x0E6), // Compare match F
+    ELC_EVENT_GPT3_COUNTER_OVERFLOW  = (0x0E7), // Overflow
+    ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0E8), // Underflow
+    ELC_EVENT_GPT3_AD_TRIG_A         = (0x0EA), // A/D converter start request A
+    ELC_EVENT_GPT3_AD_TRIG_B         = (0x0EB), // A/D converter start request B
+    ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0EC), // Compare match A
+    ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0ED), // Compare match B
+    ELC_EVENT_GPT4_COMPARE_C         = (0x0EE), // Compare match C
+    ELC_EVENT_GPT4_COMPARE_D         = (0x0EF), // Compare match D
+    ELC_EVENT_GPT4_COMPARE_E         = (0x0F0), // Compare match E
+    ELC_EVENT_GPT4_COMPARE_F         = (0x0F1), // Compare match F
+    ELC_EVENT_GPT4_COUNTER_OVERFLOW  = (0x0F2), // Overflow
+    ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0F3), // Underflow
+    ELC_EVENT_GPT4_PC                = (0x0F4), // Period count function finish
+    ELC_EVENT_GPT4_AD_TRIG_A         = (0x0F5), // A/D converter start request A
+    ELC_EVENT_GPT4_AD_TRIG_B         = (0x0F6), // A/D converter start request B
+    ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0F7), // Compare match A
+    ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0F8), // Compare match B
+    ELC_EVENT_GPT5_COMPARE_C         = (0x0F9), // Compare match C
+    ELC_EVENT_GPT5_COMPARE_D         = (0x0FA), // Compare match D
+    ELC_EVENT_GPT5_COMPARE_E         = (0x0FB), // Compare match E
+    ELC_EVENT_GPT5_COMPARE_F         = (0x0FC), // Compare match F
+    ELC_EVENT_GPT5_COUNTER_OVERFLOW  = (0x0FD), // Overflow
+    ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0FE), // Underflow
+    ELC_EVENT_GPT5_PC                = (0x0FF), // Period count function finish
+    ELC_EVENT_GPT5_AD_TRIG_A         = (0x100), // A/D converter start request A
+    ELC_EVENT_GPT5_AD_TRIG_B         = (0x101), // A/D converter start request B
+    ELC_EVENT_OPS_UVW_EDGE           = (0x15C), // UVW edge event
+    ELC_EVENT_ADC0_SCAN_END          = (0x160), // A/D scan end interrupt
+    ELC_EVENT_ADC0_SCAN_END_B        = (0x161), // A/D scan end interrupt for group B
+    ELC_EVENT_ADC0_WINDOW_A          = (0x162), // Window A Compare match
+    ELC_EVENT_ADC0_WINDOW_B          = (0x163), // Window B Compare match
+    ELC_EVENT_ADC0_COMPARE_MATCH     = (0x164), // Compare match
+    ELC_EVENT_ADC0_COMPARE_MISMATCH  = (0x165), // Compare mismatch
+    ELC_EVENT_SCI0_RXI               = (0x180), // Receive data full
+    ELC_EVENT_SCI0_TXI               = (0x181), // Transmit data empty
+    ELC_EVENT_SCI0_TEI               = (0x182), // Transmit end
+    ELC_EVENT_SCI0_ERI               = (0x183), // Receive error
+    ELC_EVENT_SCI0_AM                = (0x184), // Address match event
+    ELC_EVENT_SCI0_RXI_OR_ERI        = (0x185), // Receive data full/Receive
+    ELC_EVENT_SCI9_RXI               = (0x1B6), // Received data full
+    ELC_EVENT_SCI9_TXI               = (0x1B7), // Transmit data empty
+    ELC_EVENT_SCI9_TEI               = (0x1B8), // Transmit end
+    ELC_EVENT_SCI9_ERI               = (0x1B9), // Receive error
+    ELC_EVENT_SCI9_AM                = (0x1BA), // Address match event
+    ELC_EVENT_SPI0_RXI               = (0x1C4), // Receive buffer full
+    ELC_EVENT_SPI0_TXI               = (0x1C5), // Transmit buffer empty
+    ELC_EVENT_SPI0_IDLE              = (0x1C6), // Idle
+    ELC_EVENT_SPI0_ERI               = (0x1C7), // Error
+    ELC_EVENT_SPI0_TEI               = (0x1C8), // Transmission complete event
+    ELC_EVENT_SPI1_RXI               = (0x1C9), // Receive buffer full
+    ELC_EVENT_SPI1_TXI               = (0x1CA), // Transmit buffer empty
+    ELC_EVENT_SPI1_IDLE              = (0x1CB), // Idle
+    ELC_EVENT_SPI1_ERI               = (0x1CC), // Error
+    ELC_EVENT_SPI1_TEI               = (0x1CD), // Transmission complete event
+    ELC_CAN_MRAM_ERI                 = (0x1D0), // ECC error
+    ELC_EVENT_QSPI_INT               = (0x1DA), // QSPI interrupt
+    ELC_EVENT_DOC_INT                = (0x1DB), // Data operation circuit interrupt
+    ELC_EVENT_I3C0_RESPONSE          = (0x1DC), // Response status buffer full
+    ELC_EVENT_I3C0_COMMAND           = (0x1DD), // Command buffer empty
+    ELC_EVENT_I3C0_IBI               = (0x1DE), // IBI status buffer full
+    ELC_EVENT_I3C0_RX                = (0x1DF), // Receive
+    ELC_EVENT_IIC0_RXI               = (0x1DF), // Receive
+    ELC_EVENT_I3C0_TX                = (0x1E0), // Transmit
+    ELC_EVENT_IIC0_TXI               = (0x1E0), // Transmit
+    ELC_EVENT_I3C0_RCV_STATUS        = (0x1E1), // Receive status buffer full
+    ELC_EVENT_I3C0_HRESP             = (0x1E2), // High priority Response status buffer full
+    ELC_EVENT_I3C0_HCMD              = (0x1E3), // High priority Command buffer empty
+    ELC_EVENT_I3C0_HRX               = (0x1E4), // High priority RX buffer full
+    ELC_EVENT_I3C0_HTX               = (0x1E5), // High priority TX buffer empty
+    ELC_EVENT_I3C0_TEND              = (0x1E6), // Transmit end
+    ELC_EVENT_IIC0_TEI               = (0x1E6), // Transmit end
+    ELC_EVENT_I3C0_EEI               = (0x1E7), // Error
+    ELC_EVENT_IIC0_ERI               = (0x1E7), // Error
+    ELC_EVENT_I3C0_STEV              = (0x1E8), // Synchronous timing
+    ELC_EVENT_I3C0_MREFOVF           = (0x1E9), // MREF Counter overflow
+    ELC_EVENT_I3C0_MREFCPT           = (0x1EA), // MREF Capture
+    ELC_EVENT_I3C0_AMEV              = (0x1EB), // Additional Master-initiated bus event
+    ELC_EVENT_I3C0_WU                = (0x1EC), // Wake-up condition detection
+    ELC_EVENT_TRNG_RDREQ             = (0x1F3),
+} elc_event_t;
+
+/** @} (end addtogroup BSP_MCU_RA6E2) */
+
+#endif
diff --git a/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h
new file mode 100644
index 000000000..810f009ef
--- /dev/null
+++ b/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h
@@ -0,0 +1,413 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef BSP_FEATURE_H
+#define BSP_FEATURE_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration */
+#if (BSP_CFG_XTAL_HZ > (19999999))
+ #define CGC_MAINCLOCK_DRIVE    (0x00U)
+#elif (BSP_CFG_XTAL_HZ > (15999999)) && (BSP_CFG_XTAL_HZ < (20000000))
+ #define CGC_MAINCLOCK_DRIVE    (0x01U)
+#elif (BSP_CFG_XTAL_HZ > (7999999)) && (BSP_CFG_XTAL_HZ < (16000000))
+ #define CGC_MAINCLOCK_DRIVE    (0x02U)
+#else
+ #define CGC_MAINCLOCK_DRIVE    (0x03U)
+#endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US                  (0U) // Feature not available on this MCU
+#define BSP_FEATURE_ACMPHS_VREF                              (0U) // Feature not available on this MCU
+
+#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS             (0)  // Feature not available on this MCU
+#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US                  (0)  // Feature not available on this MCU
+
+#define BSP_FEATURE_ADC_ADDITION_SUPPORTED                   (1U)
+#define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK             (0U)
+#define BSP_FEATURE_ADC_B_TSN_SLOPE                          (0U)
+#define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS                    (0U)
+#define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS                    (0U)
+#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE            (0U)
+#define BSP_FEATURE_ADC_CLOCK_SOURCE                         (FSP_PRIV_CLOCK_PCLKC)
+#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED              (1U)
+#define BSP_FEATURE_ADC_HAS_ADBUF                            (1U)
+#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC                      (1U)
+#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT                     (1U)
+#define BSP_FEATURE_ADC_HAS_ADHVREFCNT                       (0U)
+#define BSP_FEATURE_ADC_HAS_PGA                              (1U)
+#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG                  (1U)
+#define BSP_FEATURE_ADC_HAS_VREFAMPCNT                       (0U)
+#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS                  (12U)
+#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE                    (0U)
+#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME             (4150U)
+#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE          (1U)
+#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK               (0x0000FFFFU)
+#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE            (1U)          // TSCDR is a 32-bit register on this MCU
+#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE                (1U)
+#define BSP_FEATURE_ADC_TSN_SLOPE                            (4000)
+#define BSP_FEATURE_ADC_UNIT_0_CHANNELS                      (0x000139F7U) // 0 to 2, 4 to 8, 11 to 13, 16
+#define BSP_FEATURE_ADC_UNIT_1_CHANNELS                      (0)
+#define BSP_FEATURE_ADC_VALID_UNIT_MASK                      (1U)
+
+#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT                   (2)
+#define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                      (1)
+#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT                     (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
+#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                   (0x3U)
+
+#define BSP_FEATURE_BSP_FLASH_CACHE                          (1)
+#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM              (0U)
+#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER                (0)
+#define BSP_FEATURE_BSP_HAS_ADC_CLOCK                        (0)
+#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK                      (1)
+#define BSP_FEATURE_BSP_HAS_CEC_CLOCK                        (1)
+#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB               (0U)
+#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE                (1)
+#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR                   (0U)
+#define BSP_FEATURE_BSP_HAS_DTCM                             (0) // Feature not available on this MCU
+#define BSP_FEATURE_BSP_HAS_GPT_CLOCK                        (0) // Mutually exclusive with USB60 Clock
+#define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN                  (0)
+#define BSP_FEATURE_BSP_HAS_I3C_CLOCK                        (1)
+#define BSP_FEATURE_BSP_HAS_IIC_CLOCK                        (0U)
+#define BSP_FEATURE_BSP_HAS_ITCM                             (0) // Feature not available on this MCU
+#define BSP_FEATURE_BSP_HAS_LCD_CLOCK                        (0)
+#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK                    (0)
+#define BSP_FEATURE_BSP_HAS_OFS2                             (0)
+#define BSP_FEATURE_BSP_HAS_OFS3                             (0)
+#define BSP_FEATURE_BSP_HAS_SCE5                             (0) // Feature not available on this MCU
+#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2                       (0) // Feature not available on this MCU
+#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK                     (0)
+#define BSP_FEATURE_BSP_HAS_SCI_CLOCK                        (0)
+#define BSP_FEATURE_BSP_HAS_SECURITY_MPU                     (0U)
+#define BSP_FEATURE_BSP_HAS_SPI_CLOCK                        (0)
+#define BSP_FEATURE_BSP_HAS_SP_MON                           (0U)
+#define BSP_FEATURE_BSP_HAS_SYRACCR                          (0U)
+#define BSP_FEATURE_BSP_HAS_TZFSAR                           (1)
+#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ                  (0U) // Feature not available on this MCU
+#define BSP_FEATURE_BSP_HAS_USBCKDIVCR                       (1U) // On the RA6E2 there are specific registers for configuring the USB clock.
+#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV                    (1U)
+#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ                    (1U)
+#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL                    (1U)
+#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT                (0U)
+#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION            (0U)
+#define BSP_FEATURE_BSP_MPU_REGION0_MASK                     (0U) // Feature not available on this MCU
+#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH               (0U) // If MSTPRE is present than the setting is not valid.
+#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE                     (1U)
+#define BSP_FEATURE_BSP_NUM_PMSAR                            (9U)
+#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK                    (0xFFFFF9FFU)
+#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET                  (9U)
+#define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION         (0U)
+#define BSP_FEATURE_BSP_OSIS_PADDING                         (0U)
+#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED           (0U)
+#define BSP_FEATURE_BSP_RESET_TRNG                           (0U)
+#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS        (0U)         // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option).
+#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS        (0U)         // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option).
+#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS          (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC.
+#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS         (50000000U)  // The maximum frequency allowed without having one ROM wait cycle.
+#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS       (150000000U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option).
+#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS         (100000000U) // The maximum frequency allowed without having two ROM wait cycles.
+#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET                     (0U)
+#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER                    (0x01008190U)
+#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP            (0U)
+
+#define BSP_FEATURE_CANFD_FD_SUPPORT                         (BSP_MCU_FEATURE_SET == 'B')
+#define BSP_FEATURE_CANFD_LITE                               (1U)
+#define BSP_FEATURE_CANFD_NUM_CHANNELS                       (1U)
+#define BSP_FEATURE_CANFD_NUM_INSTANCES                      (1U)
+
+#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO                    (0U)
+#define BSP_FEATURE_CAN_CLOCK                                (0U)
+#define BSP_FEATURE_CAN_MCLOCK_ONLY                          (0U)
+#define BSP_FEATURE_CAN_NUM_CHANNELS                         (0U) // RA6E2 has CAN-FD
+
+#define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO                    (1)
+#define BSP_FEATURE_CGC_HAS_BCLK                             (0U)
+#define BSP_FEATURE_CGC_HAS_CPUCLK                           (0U)
+#define BSP_FEATURE_CGC_HAS_FCLK                             (1U)
+#define BSP_FEATURE_CGC_HAS_FLDWAITR                         (0U)
+#define BSP_FEATURE_CGC_HAS_FLL                              (1U)
+#define BSP_FEATURE_CGC_HAS_FLWT                             (1U)
+#define BSP_FEATURE_CGC_HAS_HOCOWTCR                         (0U)
+#define BSP_FEATURE_CGC_HAS_MEMWAIT                          (0U)
+#define BSP_FEATURE_CGC_HAS_PCLKA                            (1U)
+#define BSP_FEATURE_CGC_HAS_PCLKB                            (1U)
+#define BSP_FEATURE_CGC_HAS_PCLKC                            (1U)
+#define BSP_FEATURE_CGC_HAS_PCLKD                            (1U)
+#define BSP_FEATURE_CGC_HAS_PCLKE                            (0U)
+#define BSP_FEATURE_CGC_HAS_PLL                              (1U)
+#define BSP_FEATURE_CGC_HAS_PLL2                             (0U)
+#define BSP_FEATURE_CGC_HAS_SOPCCR                           (1U)
+#define BSP_FEATURE_CGC_HAS_SOSC                             (1U)
+#define BSP_FEATURE_CGC_HAS_SRAMPRCR2                        (1U) // On the RA6E2 there is another register to enable write access for SRAMWTSC.
+#define BSP_FEATURE_CGC_HAS_SRAMWTSC                         (1U)
+#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR                  (0U)
+#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY                  (0U)
+#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE            (0)
+#define BSP_FEATURE_CGC_HOCOWTCR_VALUE                       (6U)
+#define BSP_FEATURE_CGC_ICLK_DIV_RESET                       (BSP_CLOCKS_SYS_CLOCK_DIV_4)
+#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US            (61U)
+#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ                (1000000U) // This MCU does have Low Speed Mode, up to 1MHz
+#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ              (0U)       // This MCU does not have Low Voltage Mode
+#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ             (0U)       // This MCU does not have Middle Speed Mode
+#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US            (15U)
+#define BSP_FEATURE_CGC_MODRV_MASK                           (0x30U)
+#define BSP_FEATURE_CGC_MODRV_SHIFT                          (0x4U)
+#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ                        (240000000U)
+#define BSP_FEATURE_CGC_PLLCCR_TYPE                          (1U)
+#define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ                    (240000000U)
+#define BSP_FEATURE_CGC_PLLCCR_WAIT_US                       (0U) // No wait between setting PLLCCR and clearing PLLSTP
+#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB          (0)
+#define BSP_FEATURE_CGC_SODRV_MASK                           (0x02U)
+#define BSP_FEATURE_CGC_SODRV_SHIFT                          (0x01U)
+#define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET                   (1)
+#define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE                    (0x78)
+#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE                   (0)
+
+#define BSP_FEATURE_CRYPTO_HAS_AES                           (0)
+#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED                   (0)
+#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG                      (0)
+#define BSP_FEATURE_CRYPTO_HAS_ECC                           (0)
+#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED                   (0)
+#define BSP_FEATURE_CRYPTO_HAS_HASH                          (0)
+#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS                     (0) // Feature not available on this MCU
+#define BSP_FEATURE_CRYPTO_HAS_RSA                           (0)
+#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED                   (0)
+#define BSP_FEATURE_CRYPTO_AES_IP_VERSION                    (0)
+#define BSP_FEATURE_CRYPTO_HAS_SCE5                          (0)
+#define BSP_FEATURE_CRYPTO_HAS_SCE5B                         (0)
+#define BSP_FEATURE_CRYPTO_HAS_SCE7                          (0)
+#define BSP_FEATURE_CRYPTO_HAS_SCE9                          (0)
+
+#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT             (0U) // Feature not available on this MCU
+#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT            (0U) // Feature not available on this MCU
+#define BSP_FEATURE_CTSU_HAS_TXVSEL                          (0)  // Feature not available on this MCU
+#define BSP_FEATURE_CTSU_VERSION                             (0)  // Feature not available on this MCU
+
+#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP                      (0)  // Feature not available on this MCU
+#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE               (0)  // Feature not available on this MCU
+#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE                   (0)  // Feature not available on this MCU
+#define BSP_FEATURE_DAC8_MAX_CHANNELS                        (0)  // Feature not available on this MCU
+
+#define BSP_FEATURE_DAC_HAS_CHARGEPUMP                       (0U)
+#define BSP_FEATURE_DAC_HAS_DAVREFCR                         (0U)
+#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE                (1U)
+#define BSP_FEATURE_DAC_HAS_INTERNAL_OUTPUT                  (1U)
+#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER                 (1U)
+#define BSP_FEATURE_DAC_MAX_CHANNELS                         (2U)
+
+#define BSP_FEATURE_DMAC_HAS_DELSR                           (0U)
+#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE               (1U)
+#define BSP_FEATURE_DMAC_MAX_CHANNEL                         (8U)
+
+#define BSP_FEATURE_DOC_VERSION                              (1U)
+
+#define BSP_FEATURE_DWT_CYCCNT                               (1U)          // RA6E2 has Data Watchpoint Cycle Count Register
+
+#define BSP_FEATURE_ELC_PERIPHERAL_MASK                      (0x0083F3FFU) // Positions of event link set registers (ELSRs) available on this MCU
+#define BSP_FEATURE_ELC_VERSION                              (1U)
+
+#define BSP_FEATURE_ETHER_FIFO_DEPTH                         (0U)          // Feature not available on this MCU
+#define BSP_FEATURE_ETHER_MAX_CHANNELS                       (0U)          // Feature not available on this MCU
+#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE                 (0)           // Feature not available on this MCU
+
+#define BSP_FEATURE_FLASH_CODE_FLASH_START                   (0x0U)
+#define BSP_FEATURE_FLASH_DATA_FLASH_START                   (0x08000000U)
+#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START              (0x0U)
+#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE           (0x2000U)
+#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE                 (0x10000U)
+#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE           (0x8000U)
+#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE                   (128U)
+#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE                   (64U)
+#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE                   (4U)
+#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT                     (1)
+#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK              (0)
+#define BSP_FEATURE_FLASH_HP_VERSION                         (40U)
+#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK                    (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT                   (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE                   (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE                   (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE                   (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE                   (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC                 (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_VERSION                         (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW             (0) // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE                   (1) // Feature not available on this MCU
+
+#define BSP_FEATURE_GPTEH_CHANNEL_MASK                       (0)
+
+#define BSP_FEATURE_GPTE_CHANNEL_MASK                        (0x3FU)
+
+#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK                   (0x00U)
+#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE              (2U)
+#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID        (0U)
+#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK             (BSP_FEATURE_GPT_VALID_CHANNEL_MASK)
+#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN                  (0U) // Feature not available on this MCU
+#define BSP_FEATURE_GPT_ODC_FREQ_MAX                         (0U) // Feature not available on this MCU
+#define BSP_FEATURE_GPT_ODC_FREQ_MIN                         (0U) // Feature not available on this MCU
+#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK               (0U) // Feature not available on this MCU
+#define BSP_FEATURE_GPT_TPCS_SHIFT                           (0U)
+#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK                   (0x3FU)
+
+#define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (8U)
+#define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (16U)
+#define BSP_FEATURE_I3C_NUM_CHANNELS                         (1U)
+#define BSP_FEATURE_I3C_MSTP_OFFSET                          (4U)
+
+#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS                 (0U)
+#define BSP_FEATURE_ICU_HAS_WUPEN1                           (1U)
+#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK                    (0x7FFFU)
+#define BSP_FEATURE_ICU_WUPEN_MASK                           (0x8007B0D7FFFULL) // Note there is another WUPEN1 register
+#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT                    (0U)
+
+#define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER             (5U)
+#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS                     (0x01)
+#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK                 (0x01)
+#define BSP_FEATURE_IIC_FAST_MODE_PLUS                       (0)
+#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK                   (0)
+#define BSP_FEATURE_IIC_VERSION                              (2)
+
+#define BSP_FEATURE_IOPORT_ELC_PORTS                         (0x001EU)
+#define BSP_FEATURE_IOPORT_HAS_ETHERNET                      (0U)
+#define BSP_FEATURE_IOPORT_VERSION                           (1U)
+
+#define BSP_FEATURE_IWDT_CLOCK_FREQUENCY                     (15000UL)
+#define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE        (0U) // Feature not available on this MCU
+
+#define BSP_FEATURE_KINT_HAS_MSTP                            (0U)
+
+#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY                    (0U)
+#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED                 (0U)
+#define BSP_FEATURE_LPM_DPSIEGR_MASK                         (0x135FF3U)
+#define BSP_FEATURE_LPM_DPSIER_MASK                          (0x051F5FF3U)
+#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP                       (0U)
+#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY                     (1U)
+#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT                  (1U)
+#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY                    (1U)
+#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP                   (0U)
+#define BSP_FEATURE_LPM_HAS_LDO_CONTROL                      (0U)
+#define BSP_FEATURE_LPM_HAS_LPSCR                            (0U)
+#define BSP_FEATURE_LPM_HAS_PDRAMSCR                         (0U)
+#define BSP_FEATURE_LPM_HAS_SBYCR_OPE                        (0U)
+#define BSP_FEATURE_LPM_HAS_SBYCR_SSBY                       (1U)
+#define BSP_FEATURE_LPM_HAS_SNOOZE                           (1U)
+#define BSP_FEATURE_LPM_HAS_SNZEDCR1                         (0U)
+#define BSP_FEATURE_LPM_HAS_SNZREQCR1                        (0U)
+#define BSP_FEATURE_LPM_HAS_STCONR                           (0U)
+#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14                     (1U)
+#define BSP_FEATURE_LPM_SNZEDCR_MASK                         (0x0000009FU)
+#define BSP_FEATURE_LPM_SNZREQCR_MASK                        (0x73007FFFU)
+#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED                (0U)
+
+#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER                   (1U)
+#define BSP_FEATURE_LVD_HAS_LVDLVLR                          (0U)
+#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD               (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V
+#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD              (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V
+#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD               (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V
+#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD              (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V
+#define BSP_FEATURE_LVD_STABILIZATION_TIME_US                (10U)                                 // Time in microseconds required for LVD to stabalize
+
+#define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS                   (0U)
+#define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS                   (0U)
+
+#define BSP_FEATURE_OPAMP_BASE_ADDRESS                       (0U)
+#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED                   (0) // Feature not available on this MCU
+#define BSP_FEATURE_OPAMP_HAS_SWITCHES                       (0U)
+#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL                  (0U)
+#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US                (0) // Feature not available on this MCU
+#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US                (0) // Feature not available on this MCU
+#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US                (0) // Feature not available on this MCU
+#define BSP_FEATURE_OPAMP_TRIM_CAPABLE                       (0U)
+#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK               (0U)
+
+#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS              (0x0U)
+#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS              (0x0U)
+
+#define BSP_FEATURE_POEG_CHANNEL_MASK                        (0xFU)
+
+#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS                (0x60000000U)
+
+#define BSP_FEATURE_HAS_RTC                                  (1U)
+#define BSP_FEATURE_RTC_HAS_ROPSEL                           (0U)
+#define BSP_FEATURE_RTC_HAS_TCEN                             (1U)
+#define BSP_FEATURE_RTC_RTCCR_CHANNELS                       (2U)
+#define BSP_FEATURE_SYSC_HAS_VBTICTLR                        (0U)
+
+#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS               (0x201U)
+#define BSP_FEATURE_SCI_CHANNELS                             (0x201U)
+#define BSP_FEATURE_SCI_CLOCK                                (FSP_PRIV_CLOCK_PCLKA)
+#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS                 (0x201U)
+#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS                   (0x201U)
+#define BSP_FEATURE_SCI_UART_FIFO_DEPTH                      (16U)
+#define BSP_FEATURE_SCI_VERSION                              (1U)
+
+#define BSP_FEATURE_SDHI_CLOCK                               (0)    // Feature not available on this MCU
+#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION                  (0)    // Feature not available on this MCU
+#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT            (0)    // Feature not available on this MCU
+#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC                  (0)    // Feature not available on this MCU
+#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK                  (0)    // Feature not available on this MCU
+
+#define BSP_FEATURE_SDRAM_START_ADDRESS                      (0x0U) // Feature not available on this MCU
+
+#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE                   (0)    // Feature not available on this MCU
+#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN              (0)    // Feature not available on this MCU
+#define BSP_FEATURE_SLCDC_MAX_NUM_SEG                        (0)    // Feature not available on this MCU
+
+#define BSP_FEATURE_SPI_CLK                                  (FSP_PRIV_CLOCK_PCLKA)
+#define BSP_FEATURE_SPI_HAS_SPCR3                            (1U)
+#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP                   (1U)
+#define BSP_FEATURE_SPI_MAX_CHANNEL                          (2U)
+#define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK    (0x3U)
+
+#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE          (0x01U)
+
+#define BSP_FEATURE_SSI_FIFO_NUM_STAGES                      (32U)
+#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK                   (0x01U)
+
+#define BSP_FEATURE_TFU_SUPPORTED                            (0U)
+
+#define BSP_FEATURE_TRNG_HAS_MODULE_STOP                     (1U)
+#define BSP_FEATURE_TZ_HAS_TRUSTZONE                         (1U)
+#define BSP_FEATURE_TZ_HAS_DLM                               (0U)
+
+#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM                     (0)
+#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK                  (0U)
+
+#define BSP_FEATURE_CRC_HAS_SNOOP                            (0U)
+#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR               (0x0U)
+
+#endif
diff --git a/ra/fsp/src/bsp/mcu/ra6e2/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra6e2/bsp_mcu_info.h
new file mode 100644
index 000000000..24b472856
--- /dev/null
+++ b/ra/fsp/src/bsp/mcu/ra6e2/bsp_mcu_info.h
@@ -0,0 +1,58 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup BSP_MCU
+ * @defgroup BSP_MCU_RA6E2 RA6E2
+ * @includedoc config_bsp_ra6e2_fsp.html
+ * @{
+ **********************************************************************************************************************/
+
+/** @} (end defgroup BSP_MCU_RA6E2) */
+
+#ifndef BSP_MCU_INFO_H
+#define BSP_MCU_INFO_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/* BSP MCU Specific Includes. */
+#include "bsp_elc.h"
+#include "bsp_feature.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+typedef elc_event_t bsp_interrupt_event_t;
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+#endif
diff --git a/ra/fsp/src/bsp/mcu/ra6m1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6m1/bsp_elc.h
index 25471748e..1428651c6 100644
--- a/ra/fsp/src/bsp/mcu/ra6m1/bsp_elc.h
+++ b/ra/fsp/src/bsp/mcu/ra6m1/bsp_elc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h
index 956fda295..0572bde2f 100644
--- a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h
+++ b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -85,8 +85,9 @@
 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS                      (0x300E7)
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                      (3U)
 
-#define BSP_FEATURE_AGT_HAS_AGTW                             (0U)
+#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT                   (0)
 #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                      (1)
+#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT                     (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                   (0x03)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                          (1)
@@ -131,7 +132,6 @@
 #define BSP_FEATURE_BSP_NUM_PMSAR                            (0U)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK                    (0xFFFFF9FFU)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET                  (9U)
-#define BSP_FEATURE_BSP_HAS_OSIS_REG                         (1U)
 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION         (0U)
 #define BSP_FEATURE_BSP_OSIS_PADDING                         (0U)
 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED           (1U)
@@ -210,6 +210,7 @@
 #define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS                     (0) // Feature not available on this MCU TODO_CHECK_FEATURE
 #define BSP_FEATURE_CRYPTO_HAS_RSA                           (1)
 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED                   (1)
+#define BSP_FEATURE_CRYPTO_AES_IP_VERSION                    (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5                          (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5B                         (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE7                          (1)
@@ -289,6 +290,7 @@
 #define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NUM_CHANNELS                         (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_MSTP_OFFSET                          (0U) // Feature not available on this MCU
 
 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS                 (0U)
 #define BSP_FEATURE_ICU_HAS_WUPEN1                           (0U)
@@ -363,7 +365,11 @@
 
 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS                (0x60000000U)
 
+#define BSP_FEATURE_HAS_RTC                                  (1U)
 #define BSP_FEATURE_RTC_HAS_ROPSEL                           (0U)
+#define BSP_FEATURE_RTC_HAS_TCEN                             (1U)
+#define BSP_FEATURE_RTC_RTCCR_CHANNELS                       (3U)
+#define BSP_FEATURE_SYSC_HAS_VBTICTLR                        (1U)
 
 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS               (BSP_FEATURE_SCI_CHANNELS)
 #define BSP_FEATURE_SCI_CHANNELS                             (0x31FU)
@@ -400,7 +406,13 @@
 #define BSP_FEATURE_TFU_SUPPORTED                            (0U) // Trigonometric Function Unit (TFU) not available on this MCU
 
 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP                     (0U)
-
 #define BSP_FEATURE_TZ_HAS_TRUSTZONE                         (0U)
+#define BSP_FEATURE_TZ_HAS_DLM                               (0U)
+
+#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM                     (0)
+#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK                  (0U)
+
+#define BSP_FEATURE_CRC_HAS_SNOOP                            (1U)
+#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR               (0x3U)
 
 #endif
diff --git a/ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h
index 938da6fae..d0572dda1 100644
--- a/ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h
+++ b/ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra6m2/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6m2/bsp_elc.h
index d4f86e25d..d548af974 100644
--- a/ra/fsp/src/bsp/mcu/ra6m2/bsp_elc.h
+++ b/ra/fsp/src/bsp/mcu/ra6m2/bsp_elc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h
index 0fc3a5720..7fde93482 100644
--- a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h
+++ b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -85,8 +85,9 @@
 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS                      (0x700E7)
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                      (3U)
 
-#define BSP_FEATURE_AGT_HAS_AGTW                             (0U)
+#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT                   (0)
 #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                      (1)
+#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT                     (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                   (0x03)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                          (1)
@@ -131,7 +132,6 @@
 #define BSP_FEATURE_BSP_NUM_PMSAR                            (0U)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK                    (0xFFFFF9FFU)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET                  (9U)
-#define BSP_FEATURE_BSP_HAS_OSIS_REG                         (1U)
 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION         (0U)
 #define BSP_FEATURE_BSP_OSIS_PADDING                         (0U)
 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED           (1U)
@@ -210,6 +210,7 @@
 #define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS                     (0) // Feature not available on this MCU TODO_CHECK_FEATURE
 #define BSP_FEATURE_CRYPTO_HAS_RSA                           (1)
 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED                   (1)
+#define BSP_FEATURE_CRYPTO_AES_IP_VERSION                    (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5                          (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5B                         (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE7                          (1)
@@ -289,6 +290,7 @@
 #define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NUM_CHANNELS                         (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_MSTP_OFFSET                          (0U) // Feature not available on this MCU
 
 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS                 (0U)
 #define BSP_FEATURE_ICU_HAS_WUPEN1                           (0U)
@@ -363,7 +365,11 @@
 
 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS                (0x60000000U)
 
+#define BSP_FEATURE_HAS_RTC                                  (1U)
 #define BSP_FEATURE_RTC_HAS_ROPSEL                           (0U)
+#define BSP_FEATURE_RTC_HAS_TCEN                             (1U)
+#define BSP_FEATURE_RTC_RTCCR_CHANNELS                       (3U)
+#define BSP_FEATURE_SYSC_HAS_VBTICTLR                        (1U)
 
 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS               (BSP_FEATURE_SCI_CHANNELS)
 #define BSP_FEATURE_SCI_CHANNELS                             (0x3FFU)
@@ -400,7 +406,13 @@
 #define BSP_FEATURE_TFU_SUPPORTED                            (0U) // Trigonometric Function Unit (TFU) not available on this MCU
 
 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP                     (0U)
-
 #define BSP_FEATURE_TZ_HAS_TRUSTZONE                         (0U)
+#define BSP_FEATURE_TZ_HAS_DLM                               (0U)
+
+#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM                     (0)
+#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK                  (0U)
+
+#define BSP_FEATURE_CRC_HAS_SNOOP                            (1U)
+#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR               (0x3U)
 
 #endif
diff --git a/ra/fsp/src/bsp/mcu/ra6m2/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra6m2/bsp_mcu_info.h
index cc76b0673..bce6b2199 100644
--- a/ra/fsp/src/bsp/mcu/ra6m2/bsp_mcu_info.h
+++ b/ra/fsp/src/bsp/mcu/ra6m2/bsp_mcu_info.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h
index 3264ffef3..b483941bb 100644
--- a/ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h
+++ b/ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h
index 793e305da..d675fb6b2 100644
--- a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h
+++ b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -85,8 +85,9 @@
 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS                      (0xF00EF)
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                      (3U)
 
-#define BSP_FEATURE_AGT_HAS_AGTW                             (0U)
+#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT                   (0)
 #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                      (1)
+#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT                     (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                   (0x03)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                          (1)
@@ -131,7 +132,6 @@
 #define BSP_FEATURE_BSP_NUM_PMSAR                            (0U)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK                    (0xFFFFF9FFU)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET                  (9U)
-#define BSP_FEATURE_BSP_HAS_OSIS_REG                         (1U)
 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION         (0U)
 #define BSP_FEATURE_BSP_OSIS_PADDING                         (0U)
 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED           (1U)
@@ -210,6 +210,7 @@
 #define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS                     (0) // Feature not available on this MCU TODO_CHECK_FEATURE
 #define BSP_FEATURE_CRYPTO_HAS_RSA                           (1)
 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED                   (1)
+#define BSP_FEATURE_CRYPTO_AES_IP_VERSION                    (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5                          (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5B                         (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE7                          (1)
@@ -289,6 +290,7 @@
 #define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NUM_CHANNELS                         (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_MSTP_OFFSET                          (0U) // Feature not available on this MCU
 
 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS                 (0U)
 #define BSP_FEATURE_ICU_HAS_WUPEN1                           (0U)
@@ -363,7 +365,11 @@
 
 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS                (0x60000000U)
 
+#define BSP_FEATURE_HAS_RTC                                  (1U)
 #define BSP_FEATURE_RTC_HAS_ROPSEL                           (0U)
+#define BSP_FEATURE_RTC_HAS_TCEN                             (1U)
+#define BSP_FEATURE_RTC_RTCCR_CHANNELS                       (3U)
+#define BSP_FEATURE_SYSC_HAS_VBTICTLR                        (1U)
 
 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS               (BSP_FEATURE_SCI_CHANNELS)
 #define BSP_FEATURE_SCI_CHANNELS                             (0x3FFU)
@@ -400,7 +406,13 @@
 #define BSP_FEATURE_TFU_SUPPORTED                            (0U) // Trigonometric Function Unit (TFU) not available on this MCU
 
 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP                     (0U)
-
 #define BSP_FEATURE_TZ_HAS_TRUSTZONE                         (0U)
+#define BSP_FEATURE_TZ_HAS_DLM                               (0U)
+
+#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM                     (0)
+#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK                  (0U)
+
+#define BSP_FEATURE_CRC_HAS_SNOOP                            (1U)
+#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR               (0x3U)
 
 #endif
diff --git a/ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h
index c64076bc6..7e383ad2f 100644
--- a/ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h
+++ b/ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h
index 60e35c2cb..23798368a 100644
--- a/ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h
+++ b/ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h
index b88c829c7..50d6332f2 100644
--- a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h
+++ b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -85,8 +85,9 @@
 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS                      (0x7F0007) // 0 to 2, 16 to 22
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                      (3U)
 
-#define BSP_FEATURE_AGT_HAS_AGTW                             (0U)
+#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT                   (0)
 #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                      (5)
+#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT                     (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                   (0x3F)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                          (1)
@@ -131,7 +132,6 @@
 #define BSP_FEATURE_BSP_NUM_PMSAR                            (9U)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK                    (0xFFFFF9FFU)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET                  (9U)
-#define BSP_FEATURE_BSP_HAS_OSIS_REG                         (0U)
 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION         (1U)
 #define BSP_FEATURE_BSP_OSIS_PADDING                         (0U)
 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED           (0U)
@@ -208,6 +208,7 @@
 #define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS                     (0) // Feature not available on this MCU TODO_CHECK_FEATURE
 #define BSP_FEATURE_CRYPTO_HAS_RSA                           (1)
 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED                   (1)
+#define BSP_FEATURE_CRYPTO_AES_IP_VERSION                    (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5                          (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5B                         (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE7                          (0)
@@ -287,6 +288,7 @@
 #define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NUM_CHANNELS                         (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_MSTP_OFFSET                          (0U) // Feature not available on this MCU
 
 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS                 (0U)
 #define BSP_FEATURE_ICU_HAS_WUPEN1                           (1U)
@@ -361,7 +363,11 @@
 
 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS                (0x60000000U)
 
+#define BSP_FEATURE_HAS_RTC                                  (1U)
 #define BSP_FEATURE_RTC_HAS_ROPSEL                           (0U)
+#define BSP_FEATURE_RTC_HAS_TCEN                             (0U)
+#define BSP_FEATURE_RTC_RTCCR_CHANNELS                       (0U)
+#define BSP_FEATURE_SYSC_HAS_VBTICTLR                        (1U)
 
 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS               (0x3F9U)
 #define BSP_FEATURE_SCI_CHANNELS                             (0x3FFU)
@@ -398,7 +404,13 @@
 #define BSP_FEATURE_TFU_SUPPORTED                            (0U) // Trigonometric Function Unit (TFU) not available on this MCU
 
 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP                     (0U)
-
 #define BSP_FEATURE_TZ_HAS_TRUSTZONE                         (1U)
+#define BSP_FEATURE_TZ_HAS_DLM                               (1U)
+
+#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM                     (0)
+#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK                  (0U)
+
+#define BSP_FEATURE_CRC_HAS_SNOOP                            (0U)
+#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR               (0x0U)
 
 #endif
diff --git a/ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h
index 6ed17add5..b40145ad8 100644
--- a/ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h
+++ b/ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h
index 1c4f1d542..c475d661d 100644
--- a/ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h
+++ b/ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h
index 3a3d129cc..1bcac8589 100644
--- a/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h
+++ b/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -85,8 +85,9 @@
 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS                      (0x1FFF0007) // 0 to 2, 16 to 28
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                      (3U)
 
-#define BSP_FEATURE_AGT_HAS_AGTW                             (0U)
+#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT                   (0)
 #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                      (5)
+#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT                     (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                   (0x3F)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                          (1)
@@ -131,7 +132,6 @@
 #define BSP_FEATURE_BSP_NUM_PMSAR                            (12U)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK                    (0xFFFFF9FFU)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET                  (9U)
-#define BSP_FEATURE_BSP_HAS_OSIS_REG                         (0U)
 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION         (1U)
 #define BSP_FEATURE_BSP_OSIS_PADDING                         (0U)
 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED           (0U)
@@ -208,6 +208,7 @@
 #define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS                     (0) // Feature not available on this MCU TODO_CHECK_FEATURE
 #define BSP_FEATURE_CRYPTO_HAS_RSA                           (1)
 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED                   (1)
+#define BSP_FEATURE_CRYPTO_AES_IP_VERSION                    (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5                          (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5B                         (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE7                          (0)
@@ -287,6 +288,7 @@
 #define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (0U) // Feature not available on this MCU
 #define BSP_FEATURE_I3C_NUM_CHANNELS                         (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_MSTP_OFFSET                          (0U) // Feature not available on this MCU
 
 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS                 (0U)
 #define BSP_FEATURE_ICU_HAS_WUPEN1                           (1U)
@@ -361,7 +363,11 @@
 
 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS                (0x60000000U)
 
+#define BSP_FEATURE_HAS_RTC                                  (1U)
 #define BSP_FEATURE_RTC_HAS_ROPSEL                           (0U)
+#define BSP_FEATURE_RTC_HAS_TCEN                             (0U)
+#define BSP_FEATURE_RTC_RTCCR_CHANNELS                       (0U)
+#define BSP_FEATURE_SYSC_HAS_VBTICTLR                        (1U)
 
 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS               (0x3F9U)
 #define BSP_FEATURE_SCI_CHANNELS                             (0x3FFU)
@@ -398,7 +404,13 @@
 #define BSP_FEATURE_TFU_SUPPORTED                            (0U) // Trigonometric Function Unit (TFU) not available on this MCU
 
 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP                     (0U)
-
 #define BSP_FEATURE_TZ_HAS_TRUSTZONE                         (1U)
+#define BSP_FEATURE_TZ_HAS_DLM                               (1U)
+
+#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM                     (0)
+#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK                  (0U)
+
+#define BSP_FEATURE_CRC_HAS_SNOOP                            (0U)
+#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR               (0x0U)
 
 #endif
diff --git a/ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h
index b724182bf..3a63bb961 100644
--- a/ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h
+++ b/ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra6t1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6t1/bsp_elc.h
index bb24718e0..16685427f 100644
--- a/ra/fsp/src/bsp/mcu/ra6t1/bsp_elc.h
+++ b/ra/fsp/src/bsp/mcu/ra6t1/bsp_elc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h
index 3d3bbf1ba..530a307dc 100644
--- a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h
+++ b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -85,8 +85,9 @@
 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS                      (0x300E7)
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                      (3U)
 
-#define BSP_FEATURE_AGT_HAS_AGTW                             (0U)
+#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT                   (0)
 #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                      (1)
+#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT                     (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                   (0x03)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                          (1)
@@ -131,7 +132,6 @@
 #define BSP_FEATURE_BSP_NUM_PMSAR                            (0U)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK                    (0xFFFFF9FFU)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET                  (9U)
-#define BSP_FEATURE_BSP_HAS_OSIS_REG                         (1U)
 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION         (0U)
 #define BSP_FEATURE_BSP_OSIS_PADDING                         (0U)
 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED           (1U)
@@ -210,6 +210,7 @@
 #define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS                     (0) // Feature not available on this MCU TODO_CHECK_FEATURE
 #define BSP_FEATURE_CRYPTO_HAS_RSA                           (1)
 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED                   (1)
+#define BSP_FEATURE_CRYPTO_AES_IP_VERSION                    (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5                          (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5B                         (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE7                          (1)
@@ -279,16 +280,17 @@
 #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE              (4U)
 #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID        (0U)
 #define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK             (BSP_FEATURE_GPT_VALID_CHANNEL_MASK)
-#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN                  (0U)    // Feature not available on this MCU
+#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN                  (0U) // Feature not available on this MCU
 #define BSP_FEATURE_GPT_ODC_FREQ_MAX                         (120000000U)
 #define BSP_FEATURE_GPT_ODC_FREQ_MIN                         (80000000U)
-#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK               (0x0FU) // Feature not available on this MCU
+#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK               (0x0FU)
 #define BSP_FEATURE_GPT_TPCS_SHIFT                           (1U)
 #define BSP_FEATURE_GPT_VALID_CHANNEL_MASK                   (0x1FFF)
 
-#define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (0U)    // Feature not available on this MCU
-#define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (0U)    // Feature not available on this MCU
-#define BSP_FEATURE_I3C_NUM_CHANNELS                         (0U)    // Feature not available on this MCU
+#define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_NUM_CHANNELS                         (0U) // Feature not available on this MCU
+#define BSP_FEATURE_I3C_MSTP_OFFSET                          (0U) // Feature not available on this MCU
 
 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS                 (0U)
 #define BSP_FEATURE_ICU_HAS_WUPEN1                           (0U)
@@ -363,7 +365,11 @@
 
 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS                (0x0U)
 
+#define BSP_FEATURE_HAS_RTC                                  (0U)
 #define BSP_FEATURE_RTC_HAS_ROPSEL                           (0U)
+#define BSP_FEATURE_RTC_HAS_TCEN                             (0U)
+#define BSP_FEATURE_RTC_RTCCR_CHANNELS                       (0U)
+#define BSP_FEATURE_SYSC_HAS_VBTICTLR                        (1U)
 
 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS               (BSP_FEATURE_SCI_CHANNELS)
 #define BSP_FEATURE_SCI_CHANNELS                             (0x31FU)
@@ -400,7 +406,13 @@
 #define BSP_FEATURE_TFU_SUPPORTED                            (0U) // Trigonometric Function Unit (TFU) not available on this MCU
 
 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP                     (0U)
-
 #define BSP_FEATURE_TZ_HAS_TRUSTZONE                         (0U)
+#define BSP_FEATURE_TZ_HAS_DLM                               (0U)
+
+#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM                     (0)
+#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK                  (0U)
+
+#define BSP_FEATURE_CRC_HAS_SNOOP                            (1U)
+#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR               (0x3U)
 
 #endif
diff --git a/ra/fsp/src/bsp/mcu/ra6t1/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra6t1/bsp_mcu_info.h
index 3802f361e..10a2e6eec 100644
--- a/ra/fsp/src/bsp/mcu/ra6t1/bsp_mcu_info.h
+++ b/ra/fsp/src/bsp/mcu/ra6t1/bsp_mcu_info.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra6t2/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6t2/bsp_elc.h
index 8280c8f03..6a44daf58 100644
--- a/ra/fsp/src/bsp/mcu/ra6t2/bsp_elc.h
+++ b/ra/fsp/src/bsp/mcu/ra6t2/bsp_elc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h
index c26d8a23a..c7866c96a 100644
--- a/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h
+++ b/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -85,8 +85,9 @@
 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS                      (0U)
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                      (0U)
 
-#define BSP_FEATURE_AGT_HAS_AGTW                             (1U)
+#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT                   (2)
 #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                      (1)
+#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT                     (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                   (0x3U)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                          (1)
@@ -131,7 +132,6 @@
 #define BSP_FEATURE_BSP_NUM_PMSAR                            (16U) // 16 due to offset address change from PMSAR2 to PMSAR3
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK                    (0xFFFFF9FFU)
 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET                  (9U)
-#define BSP_FEATURE_BSP_HAS_OSIS_REG                         (0U)
 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION         (1U)
 #define BSP_FEATURE_BSP_OSIS_PADDING                         (0U)
 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED           (0U)
@@ -208,6 +208,7 @@
 #define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS                     (0) // Feature not available on this MCU TODO_CHECK_FEATURE
 #define BSP_FEATURE_CRYPTO_HAS_RSA                           (0)
 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED                   (0)
+#define BSP_FEATURE_CRYPTO_AES_IP_VERSION                    (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5                          (0)
 #define BSP_FEATURE_CRYPTO_HAS_SCE5B                         (1)
 #define BSP_FEATURE_CRYPTO_HAS_SCE7                          (0)
@@ -284,9 +285,10 @@
 #define BSP_FEATURE_GPT_TPCS_SHIFT                           (0U)
 #define BSP_FEATURE_GPT_VALID_CHANNEL_MASK                   (0x3FFU)
 
-#define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (0) // Feature not available on this MCU TODO_CHECK_FEATURE
-#define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (0) // Feature not available on this MCU TODO_CHECK_FEATURE
-#define BSP_FEATURE_I3C_NUM_CHANNELS                         (0) // Feature not available on this MCU TODO_CHECK_FEATURE
+#define BSP_FEATURE_I3C_MAX_DEV_COUNT                        (0)  // Feature not available on this MCU TODO_CHECK_FEATURE
+#define BSP_FEATURE_I3C_NTDTBP0_DEPTH                        (0)  // Feature not available on this MCU TODO_CHECK_FEATURE
+#define BSP_FEATURE_I3C_NUM_CHANNELS                         (0)  // Feature not available on this MCU TODO_CHECK_FEATURE
+#define BSP_FEATURE_I3C_MSTP_OFFSET                          (0U) // Feature not available on this MCU
 
 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS                 (0U)
 #define BSP_FEATURE_ICU_HAS_WUPEN1                           (0)
@@ -361,7 +363,11 @@
 
 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS                (0x0U)
 
+#define BSP_FEATURE_HAS_RTC                                  (0U)
 #define BSP_FEATURE_RTC_HAS_ROPSEL                           (0U)
+#define BSP_FEATURE_RTC_HAS_TCEN                             (0U)
+#define BSP_FEATURE_RTC_RTCCR_CHANNELS                       (0U)
+#define BSP_FEATURE_SYSC_HAS_VBTICTLR                        (0U)
 
 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS               (0U)
 #define BSP_FEATURE_SCI_CHANNELS                             (0x21FU)
@@ -398,7 +404,13 @@
 #define BSP_FEATURE_TFU_SUPPORTED                            (1U) // Trigonometric Function Unit (TFU) available on this MCU
 
 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP                     (0U)
-
 #define BSP_FEATURE_TZ_HAS_TRUSTZONE                         (1U)
+#define BSP_FEATURE_TZ_HAS_DLM                               (1U)
+
+#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM                     (0)
+#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK                  (0U)
+
+#define BSP_FEATURE_CRC_HAS_SNOOP                            (1U)
+#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR               (0x4U)
 
 #endif
diff --git a/ra/fsp/src/bsp/mcu/ra6t2/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra6t2/bsp_mcu_info.h
index 2b49f3cad..5dae09b59 100644
--- a/ra/fsp/src/bsp/mcu/ra6t2/bsp_mcu_info.h
+++ b/ra/fsp/src/bsp/mcu/ra6t2/bsp_mcu_info.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra6t2/bsp_override.h b/ra/fsp/src/bsp/mcu/ra6t2/bsp_override.h
index 40c6598e2..efc367cc9 100644
--- a/ra/fsp/src/bsp/mcu/ra6t2/bsp_override.h
+++ b/ra/fsp/src/bsp/mcu/ra6t2/bsp_override.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/bsp/mcu/ra6t2/bsp_override_reg.h b/ra/fsp/src/bsp/mcu/ra6t2/bsp_override_reg.h
deleted file mode 100644
index e47750dbc..000000000
--- a/ra/fsp/src/bsp/mcu/ra6t2/bsp_override_reg.h
+++ /dev/null
@@ -1,1179 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
- * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * @addtogroup BSP_MCU_RA6T2
- * @{
- **********************************************************************************************************************/
-
-/** @} (end addtogroup BSP_MCU_RA6T2) */
-
-#ifndef BSP_OVERRIDE_REG_H
-#define BSP_OVERRIDE_REG_H
-
-/***********************************************************************************************************************
- * Includes   <System Includes> , "Project Includes"
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Macro definitions
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Typedef definitions
- **********************************************************************************************************************/
-typedef struct                         /*!< (@ 0x40041000) R_ELC Structure                                            */
-{
-    union
-    {
-        __IOM uint8_t ELCR;            /*!< (@ 0x00000000) Event Link Controller Register                             */
-
-        struct
-        {
-            uint8_t             : 7;
-            __IOM uint8_t ELCON : 1;   /*!< [7..7] All Event Link Enable                                              */
-        } ELCR_b;
-    };
-    __IM uint8_t            RESERVED[3];
-    __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000004) Event Link Software Event Generation Register              */
-    __IM uint16_t           RESERVED1[10];
-    __IOM R_ELC_ELSR_Type   ELSR[30];  /*!< (@ 0x00000020) Event Link Setting Register [0..29]                        */
-    __IM uint32_t           RESERVED2[18];
-
-    union
-    {
-        __IOM uint32_t ELCSARA;         /*!< (@ 0x000000E0) Event Link Controller Security Attribution Register
-                                         *                  A                                                          */
-
-        struct
-        {
-            __IOM uint16_t ELCR    : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution                 */
-            __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security
-                                         *   Attribution                                                               */
-            __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1 Security
-                                         *   Attribution                                                               */
-            uint32_t : 29;
-        } ELCSARA_b;
-    };
-
-    union
-    {
-        __IOM uint32_t ELCSARB;        /*!< (@ 0x000000E4) Event Link Controller Security Attribution Register
-                                        *                  B                                                          */
-
-        struct
-        {
-            __IOM uint32_t ELSR0  : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution                  */
-            __IOM uint32_t ELSR1  : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution                  */
-            __IOM uint32_t ELSR2  : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution                  */
-            __IOM uint32_t ELSR3  : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution                  */
-            __IOM uint32_t ELSR4  : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution                  */
-            __IOM uint32_t ELSR5  : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution                  */
-            __IOM uint32_t ELSR6  : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution                  */
-            __IOM uint32_t ELSR7  : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution                  */
-            uint32_t              : 4;
-            __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution               */
-            __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution               */
-            __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution               */
-            __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution               */
-            __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16Security Attribution               */
-            __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17Security Attribution               */
-            uint32_t              : 1;
-            __IOM uint32_t ELSR19 : 1; /*!< [19..19] Event Link Setting Register 19Security Attribution               */
-            __IOM uint32_t ELSR20 : 1; /*!< [20..20] Event Link Setting Register 20Security Attribution               */
-            __IOM uint32_t ELSR21 : 1; /*!< [21..21] Event Link Setting Register 21Security Attribution               */
-            __IOM uint32_t ELSR22 : 1; /*!< [22..22] Event Link Setting Register 22Security Attribution               */
-            __IOM uint32_t ELSR23 : 1; /*!< [23..23] Event Link Setting Register 23Security Attribution               */
-            __IOM uint32_t ELSR24 : 1; /*!< [24..24] Event Link Setting Register 24Security Attribution               */
-            uint32_t              : 3;
-            __IOM uint32_t ELSR28 : 1; /*!< [28..28] Event Link Setting Register 28Security Attribution               */
-            __IOM uint32_t ELSR29 : 1; /*!< [29..29] Event Link Setting Register 29Security Attribution               */
-            uint32_t              : 2;
-        } ELCSARB_b;
-    };
-} R_ELC_Type;                          /*!< Size = 232 (0xE8)                                                         */
-
-typedef struct                         /*!< (@ 0x4001FD00) R_PMISC Structure                                          */
-{
-    __IOM uint8_t PFENET;              /*!< does not exist but FSP will not build without this                        */
-
-    __IM uint8_t  RESERVED[3];
-    __IM uint32_t RESERVED1[2];
-
-    union
-    {
-        __IOM uint8_t PWPR;            /*!< (@ 0x0000000C) Write-Protect Register                                     */
-
-        struct
-        {
-            uint8_t             : 6;
-            __IOM uint8_t PFSWE : 1;   /*!< [6..6] PmnPFS Register Write                                              */
-            __IOM uint8_t B0WI  : 1;   /*!< [7..7] PFSWE Bit Write Disable                                            */
-        } PWPR_b;
-    };
-    __IM uint8_t  RESERVED2[3];
-    __IM uint32_t RESERVED3;
-
-    union
-    {
-        __IOM uint8_t PWPRS;           /*!< (@ 0x00000014) Write-Protect Register for Secure                          */
-
-        struct
-        {
-            uint8_t             : 6;
-            __IOM uint8_t PFSWE : 1;   /*!< [6..6] PmnPFS Register Write                                              */
-            __IOM uint8_t B0WI  : 1;   /*!< [7..7] PFSWE Bit Write Disable                                            */
-        } PWPRS_b;
-    };
-    __IM uint16_t            RESERVED4;
-    __IM uint32_t            RESERVED5[6];
-    __IOM R_PMISC_PMSAR_Type PMSAR[15]; /*!< (@ 0x00000030) Port Security Attribution Register                        */
-} R_PMISC_Type;                         /*!< Size = 108 (0x6C)                                                        */
-
-typedef struct                          /*!< (@ 0x40084000) R_AGTW0 Structure                                          */
-{
-    union
-    {
-        __IOM uint32_t AGT;             /*!< (@ 0x00000000) AGT Counter Register                                       */
-
-        struct
-        {
-            __IOM uint32_t AGT : 32;    /*!< [31..0] 16bit counter and reload registerNOTE : When 1 is written
-                                         *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
-                                         *   is forcibly stopped and set to FFFFH.                                     */
-        } AGT_b;
-    };
-
-    union
-    {
-        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
-
-        struct
-        {
-            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCRn register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMA_b;
-    };
-
-    union
-    {
-        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
-
-        struct
-        {
-            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
-                                         *   written to the TSTOP bit in the AGTCR register, set to
-                                         *   FFFFH                                                                     */
-        } AGTCMB_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTCR;           /*!< (@ 0x0000000C) AGT Control Register                                       */
-
-        struct
-        {
-            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
-            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
-            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
-            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
-            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
-            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
-        } AGTCR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR1;          /*!< (@ 0x0000000D) AGT Mode Register 1                                        */
-
-        struct
-        {
-            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
-            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
-            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
-            uint8_t              : 1;
-        } AGTMR1_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000E) AGT Mode Register 2                                        */
-
-        struct
-        {
-            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
-                                        *   ratio                                                                     */
-            uint8_t           : 4;
-            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
-        } AGTMR2_b;
-    };
-    __IM uint8_t RESERVED;
-
-    union
-    {
-        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000010) AGT I/O Control Register                                   */
-
-        struct
-        {
-            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
-                                        *   mode.                                                                     */
-            uint8_t             : 1;
-            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
-            uint8_t             : 1;
-            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
-            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
-        } AGTIOC_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTISR;          /*!< (@ 0x00000011) AGT Event Pin Select Register                              */
-
-        struct
-        {
-            uint8_t            : 2;
-            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
-            uint8_t            : 5;
-        } AGTISR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000012) AGT Compare Match Function Select Register                 */
-
-        struct
-        {
-            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
-            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
-            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
-            uint8_t              : 1;
-            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
-            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
-            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
-            uint8_t              : 1;
-        } AGTCMSR_b;
-    };
-
-    union
-    {
-        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x000000013) AGT Pin Select Register                                   */
-
-        struct
-        {
-            uint8_t            : 4;
-            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
-            uint8_t            : 3;
-        } AGTIOSEL_b;
-    };
-} R_AGTW0_Type;                        /*!< Size = 20 (0x14)                                                          */
-
-/* =========================================================================================================================== */
-/* ================                                          R_PORT0                                          ================ */
-/* =========================================================================================================================== */
-
-/**
- * @brief I/O Ports (R_PORT0)
- */
-
-typedef struct                         /*!< (@ 0x40040000) R_PORT0 Structure                                          */
-{
-    union
-    {
-        union
-        {
-            __IOM uint32_t PCNTR1;        /*!< (@ 0x00000000) Port Control Register 1                                    */
-
-            struct
-            {
-                __IOM uint32_t PDR  : 16; /*!< [15..0] Pmn Direction                                                     */
-                __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data                                                  */
-            } PCNTR1_b;
-        };
-
-        struct
-        {
-            union
-            {
-                __IOM uint16_t PDR;           /*!< (@ 0x00000000) Data direction register                                    */
-
-                struct
-                {
-                    __IOM uint16_t PDR0  : 1; /*!< [0..0] Pmn Direction                                                      */
-                    __IOM uint16_t PDR1  : 1; /*!< [1..1] Pmn Direction                                                      */
-                    __IOM uint16_t PDR2  : 1; /*!< [2..2] Pmn Direction                                                      */
-                    __IOM uint16_t PDR3  : 1; /*!< [3..3] Pmn Direction                                                      */
-                    __IOM uint16_t PDR4  : 1; /*!< [4..4] Pmn Direction                                                      */
-                    __IOM uint16_t PDR5  : 1; /*!< [5..5] Pmn Direction                                                      */
-                    __IOM uint16_t PDR6  : 1; /*!< [6..6] Pmn Direction                                                      */
-                    __IOM uint16_t PDR7  : 1; /*!< [7..7] Pmn Direction                                                      */
-                    __IOM uint16_t PDR8  : 1; /*!< [8..8] Pmn Direction                                                      */
-                    __IOM uint16_t PDR9  : 1; /*!< [9..9] Pmn Direction                                                      */
-                    __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction                                                    */
-                    __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction                                                    */
-                    __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction                                                    */
-                    __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction                                                    */
-                    __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction                                                    */
-                    __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction                                                    */
-                } PDR_b;
-            };
-
-            union
-            {
-                __IOM uint16_t PODR;           /*!< (@ 0x00000002) Output data register                                       */
-
-                struct
-                {
-                    __IOM uint16_t PODR0  : 1; /*!< [0..0] Pmn Output Data                                                    */
-                    __IOM uint16_t PODR1  : 1; /*!< [1..1] Pmn Output Data                                                    */
-                    __IOM uint16_t PODR2  : 1; /*!< [2..2] Pmn Output Data                                                    */
-                    __IOM uint16_t PODR3  : 1; /*!< [3..3] Pmn Output Data                                                    */
-                    __IOM uint16_t PODR4  : 1; /*!< [4..4] Pmn Output Data                                                    */
-                    __IOM uint16_t PODR5  : 1; /*!< [5..5] Pmn Output Data                                                    */
-                    __IOM uint16_t PODR6  : 1; /*!< [6..6] Pmn Output Data                                                    */
-                    __IOM uint16_t PODR7  : 1; /*!< [7..7] Pmn Output Data                                                    */
-                    __IOM uint16_t PODR8  : 1; /*!< [8..8] Pmn Output Data                                                    */
-                    __IOM uint16_t PODR9  : 1; /*!< [9..9] Pmn Output Data                                                    */
-                    __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data                                                  */
-                    __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data                                                  */
-                    __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data                                                  */
-                    __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data                                                  */
-                    __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data                                                  */
-                    __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data                                                  */
-                } PODR_b;
-            };
-        };
-    };
-
-    union
-    {
-        union
-        {
-            __IM uint32_t PCNTR2;        /*!< (@ 0x00000004) Port Control Register 2                                    */
-
-            struct
-            {
-                __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data                                                    */
-                __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data                                             */
-            } PCNTR2_b;
-        };
-
-        struct
-        {
-            union
-            {
-                __IM uint16_t PIDR;           /*!< (@ 0x00000004) Input data register                                        */
-
-                struct
-                {
-                    __IM uint16_t PIDR0  : 1; /*!< [0..0] Pmn Input Data                                                     */
-                    __IM uint16_t PIDR1  : 1; /*!< [1..1] Pmn Input Data                                                     */
-                    __IM uint16_t PIDR2  : 1; /*!< [2..2] Pmn Input Data                                                     */
-                    __IM uint16_t PIDR3  : 1; /*!< [3..3] Pmn Input Data                                                     */
-                    __IM uint16_t PIDR4  : 1; /*!< [4..4] Pmn Input Data                                                     */
-                    __IM uint16_t PIDR5  : 1; /*!< [5..5] Pmn Input Data                                                     */
-                    __IM uint16_t PIDR6  : 1; /*!< [6..6] Pmn Input Data                                                     */
-                    __IM uint16_t PIDR7  : 1; /*!< [7..7] Pmn Input Data                                                     */
-                    __IM uint16_t PIDR8  : 1; /*!< [8..8] Pmn Input Data                                                     */
-                    __IM uint16_t PIDR9  : 1; /*!< [9..9] Pmn Input Data                                                     */
-                    __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data                                                   */
-                    __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data                                                   */
-                    __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data                                                   */
-                    __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data                                                   */
-                    __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data                                                   */
-                    __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data                                                   */
-                } PIDR_b;
-            };
-
-            union
-            {
-                __IM uint16_t EIDR;           /*!< (@ 0x00000006) Event input data register                                  */
-
-                struct
-                {
-                    __IM uint16_t EIDR0  : 1; /*!< [0..0] Pmn Event Input Data                                               */
-                    __IM uint16_t EIDR1  : 1; /*!< [1..1] Pmn Event Input Data                                               */
-                    __IM uint16_t EIDR2  : 1; /*!< [2..2] Pmn Event Input Data                                               */
-                    __IM uint16_t EIDR3  : 1; /*!< [3..3] Pmn Event Input Data                                               */
-                    __IM uint16_t EIDR4  : 1; /*!< [4..4] Pmn Event Input Data                                               */
-                    __IM uint16_t EIDR5  : 1; /*!< [5..5] Pmn Event Input Data                                               */
-                    __IM uint16_t EIDR6  : 1; /*!< [6..6] Pmn Event Input Data                                               */
-                    __IM uint16_t EIDR7  : 1; /*!< [7..7] Pmn Event Input Data                                               */
-                    __IM uint16_t EIDR8  : 1; /*!< [8..8] Pmn Event Input Data                                               */
-                    __IM uint16_t EIDR9  : 1; /*!< [9..9] Pmn Event Input Data                                               */
-                    __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data                                             */
-                    __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data                                             */
-                    __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data                                             */
-                    __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data                                             */
-                    __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data                                             */
-                    __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data                                             */
-                } EIDR_b;
-            };
-        };
-    };
-
-    union
-    {
-        union
-        {
-            __OM uint32_t PCNTR3;        /*!< (@ 0x00000008) Port Control Register 3                                    */
-
-            struct
-            {
-                __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set                                                    */
-                __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset                                                 */
-            } PCNTR3_b;
-        };
-
-        struct
-        {
-            union
-            {
-                __OM uint16_t POSR;           /*!< (@ 0x00000008) Output reset register                                      */
-
-                struct
-                {
-                    __OM uint16_t POSR0  : 1; /*!< [0..0] Pmn Output Set                                                     */
-                    __OM uint16_t POSR1  : 1; /*!< [1..1] Pmn Output Set                                                     */
-                    __OM uint16_t POSR2  : 1; /*!< [2..2] Pmn Output Set                                                     */
-                    __OM uint16_t POSR3  : 1; /*!< [3..3] Pmn Output Set                                                     */
-                    __OM uint16_t POSR4  : 1; /*!< [4..4] Pmn Output Set                                                     */
-                    __OM uint16_t POSR5  : 1; /*!< [5..5] Pmn Output Set                                                     */
-                    __OM uint16_t POSR6  : 1; /*!< [6..6] Pmn Output Set                                                     */
-                    __OM uint16_t POSR7  : 1; /*!< [7..7] Pmn Output Set                                                     */
-                    __OM uint16_t POSR8  : 1; /*!< [8..8] Pmn Output Set                                                     */
-                    __OM uint16_t POSR9  : 1; /*!< [9..9] Pmn Output Set                                                     */
-                    __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set                                                   */
-                    __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set                                                   */
-                    __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set                                                   */
-                    __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set                                                   */
-                    __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set                                                   */
-                    __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set                                                   */
-                } POSR_b;
-            };
-
-            union
-            {
-                __OM uint16_t PORR;           /*!< (@ 0x0000000A) Output set register                                        */
-
-                struct
-                {
-                    __OM uint16_t PORR0  : 1; /*!< [0..0] Pmn Output Reset                                                   */
-                    __OM uint16_t PORR1  : 1; /*!< [1..1] Pmn Output Reset                                                   */
-                    __OM uint16_t PORR2  : 1; /*!< [2..2] Pmn Output Reset                                                   */
-                    __OM uint16_t PORR3  : 1; /*!< [3..3] Pmn Output Reset                                                   */
-                    __OM uint16_t PORR4  : 1; /*!< [4..4] Pmn Output Reset                                                   */
-                    __OM uint16_t PORR5  : 1; /*!< [5..5] Pmn Output Reset                                                   */
-                    __OM uint16_t PORR6  : 1; /*!< [6..6] Pmn Output Reset                                                   */
-                    __OM uint16_t PORR7  : 1; /*!< [7..7] Pmn Output Reset                                                   */
-                    __OM uint16_t PORR8  : 1; /*!< [8..8] Pmn Output Reset                                                   */
-                    __OM uint16_t PORR9  : 1; /*!< [9..9] Pmn Output Reset                                                   */
-                    __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset                                                 */
-                    __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset                                                 */
-                    __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset                                                 */
-                    __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset                                                 */
-                    __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset                                                 */
-                    __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset                                                 */
-                } PORR_b;
-            };
-        };
-    };
-
-    union
-    {
-        union
-        {
-            __IOM uint32_t PCNTR4;        /*!< (@ 0x0000000C) Port Control Register 4                                    */
-
-            struct
-            {
-                __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set                                              */
-                __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset                                           */
-            } PCNTR4_b;
-        };
-
-        struct
-        {
-            union
-            {
-                __IOM uint16_t EOSR;           /*!< (@ 0x0000000C) Event output reset register                                */
-
-                struct
-                {
-                    __IOM uint16_t EOSR0  : 1; /*!< [0..0] Pmn Event Output Set                                               */
-                    __IOM uint16_t EOSR1  : 1; /*!< [1..1] Pmn Event Output Set                                               */
-                    __IOM uint16_t EOSR2  : 1; /*!< [2..2] Pmn Event Output Set                                               */
-                    __IOM uint16_t EOSR3  : 1; /*!< [3..3] Pmn Event Output Set                                               */
-                    __IOM uint16_t EOSR4  : 1; /*!< [4..4] Pmn Event Output Set                                               */
-                    __IOM uint16_t EOSR5  : 1; /*!< [5..5] Pmn Event Output Set                                               */
-                    __IOM uint16_t EOSR6  : 1; /*!< [6..6] Pmn Event Output Set                                               */
-                    __IOM uint16_t EOSR7  : 1; /*!< [7..7] Pmn Event Output Set                                               */
-                    __IOM uint16_t EOSR8  : 1; /*!< [8..8] Pmn Event Output Set                                               */
-                    __IOM uint16_t EOSR9  : 1; /*!< [9..9] Pmn Event Output Set                                               */
-                    __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set                                             */
-                    __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set                                             */
-                    __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set                                             */
-                    __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set                                             */
-                    __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set                                             */
-                    __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set                                             */
-                } EOSR_b;
-            };
-
-            union
-            {
-                __IOM uint16_t EORR;           /*!< (@ 0x0000000E) Event output set register                                  */
-
-                struct
-                {
-                    __IOM uint16_t EORR0  : 1; /*!< [0..0] Pmn Event Output Reset                                             */
-                    __IOM uint16_t EORR1  : 1; /*!< [1..1] Pmn Event Output Reset                                             */
-                    __IOM uint16_t EORR2  : 1; /*!< [2..2] Pmn Event Output Reset                                             */
-                    __IOM uint16_t EORR3  : 1; /*!< [3..3] Pmn Event Output Reset                                             */
-                    __IOM uint16_t EORR4  : 1; /*!< [4..4] Pmn Event Output Reset                                             */
-                    __IOM uint16_t EORR5  : 1; /*!< [5..5] Pmn Event Output Reset                                             */
-                    __IOM uint16_t EORR6  : 1; /*!< [6..6] Pmn Event Output Reset                                             */
-                    __IOM uint16_t EORR7  : 1; /*!< [7..7] Pmn Event Output Reset                                             */
-                    __IOM uint16_t EORR8  : 1; /*!< [8..8] Pmn Event Output Reset                                             */
-                    __IOM uint16_t EORR9  : 1; /*!< [9..9] Pmn Event Output Reset                                             */
-                    __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset                                           */
-                    __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset                                           */
-                    __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset                                           */
-                    __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset                                           */
-                    __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset                                           */
-                    __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset                                           */
-                } EORR_b;
-            };
-        };
-    };
-} R_PORT0_Type;                        /*!< Size = 16 (0x10)                                                          */
-
-/* =========================================================================================================================== */
-/* ================                                Pos/Mask Peripheral Section                                ================ */
-/* =========================================================================================================================== */
-
-/* =========================================================================================================================== */
-/* ================                                           R_ELC                                           ================ */
-/* =========================================================================================================================== */
-
-/* =========================================================  ELCR  ========================================================== */
-#define R_ELC_ELCR_ELCON_Pos         (7UL)          /*!< ELCON (Bit 7)                                         */
-#define R_ELC_ELCR_ELCON_Msk         (0x80UL)       /*!< ELCON (Bitfield-Mask: 0x01)                           */
-/* ========================================================  ELCSARA  ======================================================== */
-#define R_ELC_ELCSARA_ELCR_Pos       (0UL)          /*!< ELCR (Bit 0)                                          */
-#define R_ELC_ELCSARA_ELCR_Msk       (0x1UL)        /*!< ELCR (Bitfield-Mask: 0x01)                            */
-#define R_ELC_ELCSARA_ELSEGR0_Pos    (1UL)          /*!< ELSEGR0 (Bit 1)                                       */
-#define R_ELC_ELCSARA_ELSEGR0_Msk    (0x2UL)        /*!< ELSEGR0 (Bitfield-Mask: 0x01)                         */
-#define R_ELC_ELCSARA_ELSEGR1_Pos    (2UL)          /*!< ELSEGR1 (Bit 2)                                       */
-#define R_ELC_ELCSARA_ELSEGR1_Msk    (0x4UL)        /*!< ELSEGR1 (Bitfield-Mask: 0x01)                         */
-/* ========================================================  ELCSARB  ======================================================== */
-#define R_ELC_ELCSARB_ELSR0_Pos      (0UL)          /*!< ELSR0 (Bit 0)                                         */
-#define R_ELC_ELCSARB_ELSR0_Msk      (0x1UL)        /*!< ELSR0 (Bitfield-Mask: 0x01)                           */
-#define R_ELC_ELCSARB_ELSR1_Pos      (1UL)          /*!< ELSR1 (Bit 1)                                         */
-#define R_ELC_ELCSARB_ELSR1_Msk      (0x2UL)        /*!< ELSR1 (Bitfield-Mask: 0x01)                           */
-#define R_ELC_ELCSARB_ELSR2_Pos      (2UL)          /*!< ELSR2 (Bit 2)                                         */
-#define R_ELC_ELCSARB_ELSR2_Msk      (0x4UL)        /*!< ELSR2 (Bitfield-Mask: 0x01)                           */
-#define R_ELC_ELCSARB_ELSR3_Pos      (3UL)          /*!< ELSR3 (Bit 3)                                         */
-#define R_ELC_ELCSARB_ELSR3_Msk      (0x8UL)        /*!< ELSR3 (Bitfield-Mask: 0x01)                           */
-#define R_ELC_ELCSARB_ELSR4_Pos      (4UL)          /*!< ELSR4 (Bit 4)                                         */
-#define R_ELC_ELCSARB_ELSR4_Msk      (0x10UL)       /*!< ELSR4 (Bitfield-Mask: 0x01)                           */
-#define R_ELC_ELCSARB_ELSR5_Pos      (5UL)          /*!< ELSR5 (Bit 5)                                         */
-#define R_ELC_ELCSARB_ELSR5_Msk      (0x20UL)       /*!< ELSR5 (Bitfield-Mask: 0x01)                           */
-#define R_ELC_ELCSARB_ELSR6_Pos      (6UL)          /*!< ELSR6 (Bit 6)                                         */
-#define R_ELC_ELCSARB_ELSR6_Msk      (0x40UL)       /*!< ELSR6 (Bitfield-Mask: 0x01)                           */
-#define R_ELC_ELCSARB_ELSR7_Pos      (7UL)          /*!< ELSR7 (Bit 7)                                         */
-#define R_ELC_ELCSARB_ELSR7_Msk      (0x80UL)       /*!< ELSR7 (Bitfield-Mask: 0x01)                           */
-#define R_ELC_ELCSARB_ELSR12_Pos     (12UL)         /*!< ELSR12 (Bit 12)                                       */
-#define R_ELC_ELCSARB_ELSR12_Msk     (0x1000UL)     /*!< ELSR12 (Bitfield-Mask: 0x01)                          */
-#define R_ELC_ELCSARB_ELSR13_Pos     (13UL)         /*!< ELSR13 (Bit 13)                                       */
-#define R_ELC_ELCSARB_ELSR13_Msk     (0x2000UL)     /*!< ELSR13 (Bitfield-Mask: 0x01)                          */
-#define R_ELC_ELCSARB_ELSR14_Pos     (14UL)         /*!< ELSR14 (Bit 14)                                       */
-#define R_ELC_ELCSARB_ELSR14_Msk     (0x4000UL)     /*!< ELSR14 (Bitfield-Mask: 0x01)                          */
-#define R_ELC_ELCSARB_ELSR15_Pos     (15UL)         /*!< ELSR15 (Bit 15)                                       */
-#define R_ELC_ELCSARB_ELSR15_Msk     (0x8000UL)     /*!< ELSR15 (Bitfield-Mask: 0x01)                          */
-#define R_ELC_ELCSARB_ELSR16_Pos     (16UL)         /*!< ELSR16 (Bit 16)                                       */
-#define R_ELC_ELCSARB_ELSR16_Msk     (0x10000UL)    /*!< ELSR16 (Bitfield-Mask: 0x01)                          */
-#define R_ELC_ELCSARB_ELSR17_Pos     (17UL)         /*!< ELSR17 (Bit 17)                                       */
-#define R_ELC_ELCSARB_ELSR17_Msk     (0x20000UL)    /*!< ELSR17 (Bitfield-Mask: 0x01)                          */
-#define R_ELC_ELCSARB_ELSR19_Pos     (19UL)         /*!< ELSR19 (Bit 19)                                       */
-#define R_ELC_ELCSARB_ELSR19_Msk     (0x80000UL)    /*!< ELSR19 (Bitfield-Mask: 0x01)                          */
-#define R_ELC_ELCSARB_ELSR20_Pos     (20UL)         /*!< ELSR20 (Bit 20)                                       */
-#define R_ELC_ELCSARB_ELSR20_Msk     (0x100000UL)   /*!< ELSR20 (Bitfield-Mask: 0x01)                          */
-#define R_ELC_ELCSARB_ELSR21_Pos     (21UL)         /*!< ELSR21 (Bit 21)                                       */
-#define R_ELC_ELCSARB_ELSR21_Msk     (0x200000UL)   /*!< ELSR21 (Bitfield-Mask: 0x01)                          */
-#define R_ELC_ELCSARB_ELSR22_Pos     (22UL)         /*!< ELSR22 (Bit 22)                                       */
-#define R_ELC_ELCSARB_ELSR22_Msk     (0x400000UL)   /*!< ELSR22 (Bitfield-Mask: 0x01)                          */
-#define R_ELC_ELCSARB_ELSR23_Pos     (23UL)         /*!< ELSR23 (Bit 23)                                       */
-#define R_ELC_ELCSARB_ELSR23_Msk     (0x800000UL)   /*!< ELSR23 (Bitfield-Mask: 0x01)                          */
-#define R_ELC_ELCSARB_ELSR24_Pos     (24UL)         /*!< ELSR24 (Bit 24)                                       */
-#define R_ELC_ELCSARB_ELSR24_Msk     (0x1000000UL)  /*!< ELSR24 (Bitfield-Mask: 0x01)                          */
-#define R_ELC_ELCSARB_ELSR28_Pos     (28UL)         /*!< ELSR28 (Bit 28)                                       */
-#define R_ELC_ELCSARB_ELSR28_Msk     (0x10000000UL) /*!< ELSR28 (Bitfield-Mask: 0x01)                          */
-#define R_ELC_ELCSARB_ELSR29_Pos     (29UL)         /*!< ELSR29 (Bit 29)                                       */
-#define R_ELC_ELCSARB_ELSR29_Msk     (0x20000000UL) /*!< ELSR29 (Bitfield-Mask: 0x01)                          */
-
-/* =========================================================================================================================== */
-/* ================                                           R_SYSTEM                                            ================ */
-/* =========================================================================================================================== */
-
-/* =========================================================  SBYCR  ========================================================= */
-#define R_SYSTEM_SBYCR_SSBY_Pos                   (15UL)         /*!< SSBY (Bit 15)                                         */
-#define R_SYSTEM_SBYCR_SSBY_Msk                   (0x8000UL)     /*!< SSBY (Bitfield-Mask: 0x01)                            */
-/* =======================================================  SCKDIVCR  ======================================================== */
-#define R_SYSTEM_SCKDIVCR_PCKD_Pos                (0UL)          /*!< PCKD (Bit 0)                                          */
-#define R_SYSTEM_SCKDIVCR_PCKD_Msk                (0x7UL)        /*!< PCKD (Bitfield-Mask: 0x07)                            */
-#define R_SYSTEM_SCKDIVCR_PCKC_Pos                (4UL)          /*!< PCKC (Bit 4)                                          */
-#define R_SYSTEM_SCKDIVCR_PCKC_Msk                (0x70UL)       /*!< PCKC (Bitfield-Mask: 0x07)                            */
-#define R_SYSTEM_SCKDIVCR_PCKB_Pos                (8UL)          /*!< PCKB (Bit 8)                                          */
-#define R_SYSTEM_SCKDIVCR_PCKB_Msk                (0x700UL)      /*!< PCKB (Bitfield-Mask: 0x07)                            */
-#define R_SYSTEM_SCKDIVCR_PCKA_Pos                (12UL)         /*!< PCKA (Bit 12)                                         */
-#define R_SYSTEM_SCKDIVCR_PCKA_Msk                (0x7000UL)     /*!< PCKA (Bitfield-Mask: 0x07)                            */
-#define R_SYSTEM_SCKDIVCR_RSV_Pos                 (16UL)         /*!< RSV (Bit 16)                                          */
-#define R_SYSTEM_SCKDIVCR_RSV_Msk                 (0x70000UL)    /*!< RSV (Bitfield-Mask: 0x07)                             */
-#define R_SYSTEM_SCKDIVCR_ICK_Pos                 (24UL)         /*!< ICK (Bit 24)                                          */
-#define R_SYSTEM_SCKDIVCR_ICK_Msk                 (0x7000000UL)  /*!< ICK (Bitfield-Mask: 0x07)                             */
-#define R_SYSTEM_SCKDIVCR_FCK_Pos                 (28UL)         /*!< FCK (Bit 28)                                          */
-#define R_SYSTEM_SCKDIVCR_FCK_Msk                 (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07)                             */
-/* ========================================================  SCKSCR  ========================================================= */
-#define R_SYSTEM_SCKSCR_CKSEL_Pos                 (0UL)          /*!< CKSEL (Bit 0)                                         */
-#define R_SYSTEM_SCKSCR_CKSEL_Msk                 (0x7UL)        /*!< CKSEL (Bitfield-Mask: 0x07)                           */
-/* ========================================================  PLLCCR  ========================================================= */
-#define R_SYSTEM_PLLCCR_PLIDIV_Pos                (0UL)          /*!< PLIDIV (Bit 0)                                        */
-#define R_SYSTEM_PLLCCR_PLIDIV_Msk                (0x3UL)        /*!< PLIDIV (Bitfield-Mask: 0x03)                          */
-#define R_SYSTEM_PLLCCR_PLSRCSEL_Pos              (4UL)          /*!< PLSRCSEL (Bit 4)                                      */
-#define R_SYSTEM_PLLCCR_PLSRCSEL_Msk              (0x10UL)       /*!< PLSRCSEL (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_PLLCCR_PLLMUL_Pos                (8UL)          /*!< PLLMUL (Bit 8)                                        */
-#define R_SYSTEM_PLLCCR_PLLMUL_Msk                (0x3f00UL)     /*!< PLLMUL (Bitfield-Mask: 0x3f)                          */
-/* =========================================================  PLLCR  ========================================================= */
-#define R_SYSTEM_PLLCR_PLLSTP_Pos                 (0UL)          /*!< PLLSTP (Bit 0)                                        */
-#define R_SYSTEM_PLLCR_PLLSTP_Msk                 (0x1UL)        /*!< PLLSTP (Bitfield-Mask: 0x01)                          */
-/* ========================================================  MOSCCR  ========================================================= */
-#define R_SYSTEM_MOSCCR_MOSTP_Pos                 (0UL)          /*!< MOSTP (Bit 0)                                         */
-#define R_SYSTEM_MOSCCR_MOSTP_Msk                 (0x1UL)        /*!< MOSTP (Bitfield-Mask: 0x01)                           */
-/* ========================================================  HOCOCR  ========================================================= */
-#define R_SYSTEM_HOCOCR_HCSTP_Pos                 (0UL)          /*!< HCSTP (Bit 0)                                         */
-#define R_SYSTEM_HOCOCR_HCSTP_Msk                 (0x1UL)        /*!< HCSTP (Bitfield-Mask: 0x01)                           */
-/* ========================================================  MOCOCR  ========================================================= */
-#define R_SYSTEM_MOCOCR_MCSTP_Pos                 (0UL)          /*!< MCSTP (Bit 0)                                         */
-#define R_SYSTEM_MOCOCR_MCSTP_Msk                 (0x1UL)        /*!< MCSTP (Bitfield-Mask: 0x01)                           */
-/* =========================================================  OSCSF  ========================================================= */
-#define R_SYSTEM_OSCSF_HOCOSF_Pos                 (0UL)          /*!< HOCOSF (Bit 0)                                        */
-#define R_SYSTEM_OSCSF_HOCOSF_Msk                 (0x1UL)        /*!< HOCOSF (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_OSCSF_MOSCSF_Pos                 (3UL)          /*!< MOSCSF (Bit 3)                                        */
-#define R_SYSTEM_OSCSF_MOSCSF_Msk                 (0x8UL)        /*!< MOSCSF (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_OSCSF_PLLSF_Pos                  (5UL)          /*!< PLLSF (Bit 5)                                         */
-#define R_SYSTEM_OSCSF_PLLSF_Msk                  (0x20UL)       /*!< PLLSF (Bitfield-Mask: 0x01)                           */
-#define R_SYSTEM_OSCSF_PLL2SF_Pos                 (6UL)          /*!< PLL2SF (Bit 6)                                        */
-#define R_SYSTEM_OSCSF_PLL2SF_Msk                 (0x40UL)       /*!< PLL2SF (Bitfield-Mask: 0x01)                          */
-/* =========================================================  CKOCR  ========================================================= */
-#define R_SYSTEM_CKOCR_CKOSEL_Pos                 (0UL)          /*!< CKOSEL (Bit 0)                                        */
-#define R_SYSTEM_CKOCR_CKOSEL_Msk                 (0x7UL)        /*!< CKOSEL (Bitfield-Mask: 0x07)                          */
-#define R_SYSTEM_CKOCR_CKODIV_Pos                 (4UL)          /*!< CKODIV (Bit 4)                                        */
-#define R_SYSTEM_CKOCR_CKODIV_Msk                 (0x70UL)       /*!< CKODIV (Bitfield-Mask: 0x07)                          */
-#define R_SYSTEM_CKOCR_CKOEN_Pos                  (7UL)          /*!< CKOEN (Bit 7)                                         */
-#define R_SYSTEM_CKOCR_CKOEN_Msk                  (0x80UL)       /*!< CKOEN (Bitfield-Mask: 0x01)                           */
-/* ========================================================  TRCKCR  ========================================================= */
-#define R_SYSTEM_TRCKCR_TRCK_Pos                  (0UL)          /*!< TRCK (Bit 0)                                          */
-#define R_SYSTEM_TRCKCR_TRCK_Msk                  (0xfUL)        /*!< TRCK (Bitfield-Mask: 0x0f)                            */
-#define R_SYSTEM_TRCKCR_TRCKEN_Pos                (7UL)          /*!< TRCKEN (Bit 7)                                        */
-#define R_SYSTEM_TRCKCR_TRCKEN_Msk                (0x80UL)       /*!< TRCKEN (Bitfield-Mask: 0x01)                          */
-/* ========================================================  OSTDCR  ========================================================= */
-#define R_SYSTEM_OSTDCR_OSTDIE_Pos                (0UL)          /*!< OSTDIE (Bit 0)                                        */
-#define R_SYSTEM_OSTDCR_OSTDIE_Msk                (0x1UL)        /*!< OSTDIE (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_OSTDCR_OSTDE_Pos                 (7UL)          /*!< OSTDE (Bit 7)                                         */
-#define R_SYSTEM_OSTDCR_OSTDE_Msk                 (0x80UL)       /*!< OSTDE (Bitfield-Mask: 0x01)                           */
-/* ========================================================  OSTDSR  ========================================================= */
-#define R_SYSTEM_OSTDSR_OSTDF_Pos                 (0UL)          /*!< OSTDF (Bit 0)                                         */
-#define R_SYSTEM_OSTDSR_OSTDF_Msk                 (0x1UL)        /*!< OSTDF (Bitfield-Mask: 0x01)                           */
-/* ========================================================  PLL2CCR  ======================================================== */
-#define R_SYSTEM_PLL2CCR_PL2IDIV_Pos              (0UL)          /*!< PL2IDIV (Bit 0)                                       */
-#define R_SYSTEM_PLL2CCR_PL2IDIV_Msk              (0x3UL)        /*!< PL2IDIV (Bitfield-Mask: 0x03)                         */
-#define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos            (4UL)          /*!< PL2SRCSEL (Bit 4)                                     */
-#define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk            (0x10UL)       /*!< PL2SRCSEL (Bitfield-Mask: 0x01)                       */
-#define R_SYSTEM_PLL2CCR_PLL2MUL_Pos              (8UL)          /*!< PLL2MUL (Bit 8)                                       */
-#define R_SYSTEM_PLL2CCR_PLL2MUL_Msk              (0x3f00UL)     /*!< PLL2MUL (Bitfield-Mask: 0x3f)                         */
-/* ========================================================  PLL2CR  ========================================================= */
-#define R_SYSTEM_PLL2CR_PLL2STP_Pos               (0UL)          /*!< PLL2STP (Bit 0)                                       */
-#define R_SYSTEM_PLL2CR_PLL2STP_Msk               (0x1UL)        /*!< PLL2STP (Bitfield-Mask: 0x01)                         */
-/* =======================================================  MOCOUTCR  ======================================================== */
-#define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos            (0UL)          /*!< MOCOUTRM (Bit 0)                                      */
-#define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk            (0xffUL)       /*!< MOCOUTRM (Bitfield-Mask: 0xff)                        */
-/* =======================================================  HOCOUTCR  ======================================================== */
-#define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos            (0UL)          /*!< HOCOUTRM (Bit 0)                                      */
-#define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk            (0xffUL)       /*!< HOCOUTRM (Bitfield-Mask: 0xff)                        */
-/* =====================================================  SCISPICKDIVCR  ===================================================== */
-#define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos    (0UL)          /*!< SCISPICKDIV (Bit 0)                                   */
-#define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk    (0x7UL)        /*!< SCISPICKDIV (Bitfield-Mask: 0x07)                     */
-/* =====================================================  CANFDCKDIVCR  ====================================================== */
-#define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos      (0UL)          /*!< CANFDCKDIV (Bit 0)                                    */
-#define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk      (0x7UL)        /*!< CANFDCKDIV (Bitfield-Mask: 0x07)                      */
-/* ======================================================  GPTCKDIVCR  ======================================================= */
-#define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos          (0UL)          /*!< GPTCKDIV (Bit 0)                                      */
-#define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk          (0x7UL)        /*!< GPTCKDIV (Bitfield-Mask: 0x07)                        */
-/* ======================================================  IICCKDIVCR  ======================================================= */
-#define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
-#define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
-/* ======================================================  SCISPICKCR  ======================================================= */
-#define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos       (0UL)          /*!< SCISPICKSEL (Bit 0)                                   */
-#define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk       (0x7UL)        /*!< SCISPICKSEL (Bitfield-Mask: 0x07)                     */
-#define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos      (6UL)          /*!< SCISPICKSREQ (Bit 6)                                  */
-#define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk      (0x40UL)       /*!< SCISPICKSREQ (Bitfield-Mask: 0x01)                    */
-#define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos      (7UL)          /*!< SCISPICKSRDY (Bit 7)                                  */
-#define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk      (0x80UL)       /*!< SCISPICKSRDY (Bitfield-Mask: 0x01)                    */
-/* =======================================================  CANFDCKCR  ======================================================= */
-#define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos         (0UL)          /*!< CANFDCKSEL (Bit 0)                                    */
-#define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk         (0x7UL)        /*!< CANFDCKSEL (Bitfield-Mask: 0x07)                      */
-#define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos        (6UL)          /*!< CANFDCKSREQ (Bit 6)                                   */
-#define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk        (0x40UL)       /*!< CANFDCKSREQ (Bitfield-Mask: 0x01)                     */
-#define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos        (7UL)          /*!< CANFDCKSRDY (Bit 7)                                   */
-#define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk        (0x80UL)       /*!< CANFDCKSRDY (Bitfield-Mask: 0x01)                     */
-/* ========================================================  GPTCKCR  ======================================================== */
-#define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos             (0UL)          /*!< GPTCKSEL (Bit 0)                                      */
-#define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk             (0x7UL)        /*!< GPTCKSEL (Bitfield-Mask: 0x07)                        */
-#define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos            (6UL)          /*!< GPTCKSREQ (Bit 6)                                     */
-#define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk            (0x40UL)       /*!< GPTCKSREQ (Bitfield-Mask: 0x01)                       */
-#define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos            (7UL)          /*!< GPTCKSRDY (Bit 7)                                     */
-#define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk            (0x80UL)       /*!< GPTCKSRDY (Bitfield-Mask: 0x01)                       */
-/* ========================================================  IICCKCR  ======================================================== */
-#define R_SYSTEM_IICCKCR_IICCKSEL_Pos             (0UL)          /*!< IICCKSEL (Bit 0)                                      */
-#define R_SYSTEM_IICCKCR_IICCKSEL_Msk             (0x7UL)        /*!< IICCKSEL (Bitfield-Mask: 0x07)                        */
-#define R_SYSTEM_IICCKCR_IICCKSREQ_Pos            (6UL)          /*!< IICCKSREQ (Bit 6)                                     */
-#define R_SYSTEM_IICCKCR_IICCKSREQ_Msk            (0x40UL)       /*!< IICCKSREQ (Bitfield-Mask: 0x01)                       */
-#define R_SYSTEM_IICCKCR_IICCKSRDY_Pos            (7UL)          /*!< IICCKSRDY (Bit 7)                                     */
-#define R_SYSTEM_IICCKCR_IICCKSRDY_Msk            (0x80UL)       /*!< IICCKSRDY (Bitfield-Mask: 0x01)                       */
-/* =========================================================  SNZCR  ========================================================= */
-#define R_SYSTEM_SNZCR_RXDREQEN_Pos               (0UL)          /*!< RXDREQEN (Bit 0)                                      */
-#define R_SYSTEM_SNZCR_RXDREQEN_Msk               (0x1UL)        /*!< RXDREQEN (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_SNZCR_SNZDTCEN_Pos               (1UL)          /*!< SNZDTCEN (Bit 1)                                      */
-#define R_SYSTEM_SNZCR_SNZDTCEN_Msk               (0x2UL)        /*!< SNZDTCEN (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_SNZCR_SNZE_Pos                   (7UL)          /*!< SNZE (Bit 7)                                          */
-#define R_SYSTEM_SNZCR_SNZE_Msk                   (0x80UL)       /*!< SNZE (Bitfield-Mask: 0x01)                            */
-/* =======================================================  SNZEDCR0  ======================================================== */
-#define R_SYSTEM_SNZEDCR0_AGTUNFED_Pos            (0UL)          /*!< AGTUNFED (Bit 0)                                      */
-#define R_SYSTEM_SNZEDCR0_AGTUNFED_Msk            (0x1UL)        /*!< AGTUNFED (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_SNZEDCR0_DTCZRED_Pos             (1UL)          /*!< DTCZRED (Bit 1)                                       */
-#define R_SYSTEM_SNZEDCR0_DTCZRED_Msk             (0x2UL)        /*!< DTCZRED (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_SNZEDCR0_DTCNZRED_Pos            (2UL)          /*!< DTCNZRED (Bit 2)                                      */
-#define R_SYSTEM_SNZEDCR0_DTCNZRED_Msk            (0x4UL)        /*!< DTCNZRED (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_SNZEDCR0_AD0MATED_Pos            (3UL)          /*!< AD0MATED (Bit 3)                                      */
-#define R_SYSTEM_SNZEDCR0_AD0MATED_Msk            (0x8UL)        /*!< AD0MATED (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_SNZEDCR0_AD1MATED_Pos            (5UL)          /*!< AD1MATED (Bit 5)                                      */
-#define R_SYSTEM_SNZEDCR0_AD1MATED_Msk            (0x20UL)       /*!< AD1MATED (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_SNZEDCR0_SCI0UMTED_Pos           (7UL)          /*!< SCI0UMTED (Bit 7)                                     */
-#define R_SYSTEM_SNZEDCR0_SCI0UMTED_Msk           (0x80UL)       /*!< SCI0UMTED (Bitfield-Mask: 0x01)                       */
-/* =======================================================  SNZREQCR0  ======================================================= */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN0_Pos          (0UL)          /*!< SNZREQEN0 (Bit 0)                                     */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN0_Msk          (0x1UL)        /*!< SNZREQEN0 (Bitfield-Mask: 0x01)                       */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN1_Pos          (1UL)          /*!< SNZREQEN1 (Bit 1)                                     */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN1_Msk          (0x2UL)        /*!< SNZREQEN1 (Bitfield-Mask: 0x01)                       */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN2_Pos          (2UL)          /*!< SNZREQEN2 (Bit 2)                                     */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN2_Msk          (0x4UL)        /*!< SNZREQEN2 (Bitfield-Mask: 0x01)                       */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN3_Pos          (3UL)          /*!< SNZREQEN3 (Bit 3)                                     */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN3_Msk          (0x8UL)        /*!< SNZREQEN3 (Bitfield-Mask: 0x01)                       */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN4_Pos          (4UL)          /*!< SNZREQEN4 (Bit 4)                                     */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN4_Msk          (0x10UL)       /*!< SNZREQEN4 (Bitfield-Mask: 0x01)                       */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN5_Pos          (5UL)          /*!< SNZREQEN5 (Bit 5)                                     */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN5_Msk          (0x20UL)       /*!< SNZREQEN5 (Bitfield-Mask: 0x01)                       */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN6_Pos          (6UL)          /*!< SNZREQEN6 (Bit 6)                                     */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN6_Msk          (0x40UL)       /*!< SNZREQEN6 (Bitfield-Mask: 0x01)                       */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN7_Pos          (7UL)          /*!< SNZREQEN7 (Bit 7)                                     */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN7_Msk          (0x80UL)       /*!< SNZREQEN7 (Bitfield-Mask: 0x01)                       */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN8_Pos          (8UL)          /*!< SNZREQEN8 (Bit 8)                                     */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN8_Msk          (0x100UL)      /*!< SNZREQEN8 (Bitfield-Mask: 0x01)                       */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN9_Pos          (9UL)          /*!< SNZREQEN9 (Bit 9)                                     */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN9_Msk          (0x200UL)      /*!< SNZREQEN9 (Bitfield-Mask: 0x01)                       */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN10_Pos         (10UL)         /*!< SNZREQEN10 (Bit 10)                                   */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN10_Msk         (0x400UL)      /*!< SNZREQEN10 (Bitfield-Mask: 0x01)                      */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN11_Pos         (11UL)         /*!< SNZREQEN11 (Bit 11)                                   */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN11_Msk         (0x800UL)      /*!< SNZREQEN11 (Bitfield-Mask: 0x01)                      */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN12_Pos         (12UL)         /*!< SNZREQEN12 (Bit 12)                                   */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN12_Msk         (0x1000UL)     /*!< SNZREQEN12 (Bitfield-Mask: 0x01)                      */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN13_Pos         (13UL)         /*!< SNZREQEN13 (Bit 13)                                   */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN13_Msk         (0x2000UL)     /*!< SNZREQEN13 (Bitfield-Mask: 0x01)                      */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN14_Pos         (14UL)         /*!< SNZREQEN14 (Bit 14)                                   */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN14_Msk         (0x4000UL)     /*!< SNZREQEN14 (Bitfield-Mask: 0x01)                      */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN15_Pos         (15UL)         /*!< SNZREQEN15 (Bit 15)                                   */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN15_Msk         (0x8000UL)     /*!< SNZREQEN15 (Bitfield-Mask: 0x01)                      */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN17_Pos         (17UL)         /*!< SNZREQEN17 (Bit 17)                                   */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN17_Msk         (0x20000UL)    /*!< SNZREQEN17 (Bitfield-Mask: 0x01)                      */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN28_Pos         (28UL)         /*!< SNZREQEN28 (Bit 28)                                   */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN28_Msk         (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01)                      */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN29_Pos         (29UL)         /*!< SNZREQEN29 (Bit 29)                                   */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN29_Msk         (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01)                      */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN30_Pos         (30UL)         /*!< SNZREQEN30 (Bit 30)                                   */
-#define R_SYSTEM_SNZREQCR0_SNZREQEN30_Msk         (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01)                      */
-/* =========================================================  OPCCR  ========================================================= */
-#define R_SYSTEM_OPCCR_OPCM_Pos                   (0UL)          /*!< OPCM (Bit 0)                                          */
-#define R_SYSTEM_OPCCR_OPCM_Msk                   (0x3UL)        /*!< OPCM (Bitfield-Mask: 0x03)                            */
-#define R_SYSTEM_OPCCR_OPCMTSF_Pos                (4UL)          /*!< OPCMTSF (Bit 4)                                       */
-#define R_SYSTEM_OPCCR_OPCMTSF_Msk                (0x10UL)       /*!< OPCMTSF (Bitfield-Mask: 0x01)                         */
-/* =======================================================  MOSCWTCR  ======================================================== */
-#define R_SYSTEM_MOSCWTCR_MSTS_Pos                (0UL)          /*!< MSTS (Bit 0)                                          */
-#define R_SYSTEM_MOSCWTCR_MSTS_Msk                (0xfUL)        /*!< MSTS (Bitfield-Mask: 0x0f)                            */
-/* ========================================================  RSTSR1  ========================================================= */
-#define R_SYSTEM_RSTSR1_IWDTRF_Pos                (0UL)          /*!< IWDTRF (Bit 0)                                        */
-#define R_SYSTEM_RSTSR1_IWDTRF_Msk                (0x1UL)        /*!< IWDTRF (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_RSTSR1_WDTRF_Pos                 (1UL)          /*!< WDTRF (Bit 1)                                         */
-#define R_SYSTEM_RSTSR1_WDTRF_Msk                 (0x2UL)        /*!< WDTRF (Bitfield-Mask: 0x01)                           */
-#define R_SYSTEM_RSTSR1_SWRF_Pos                  (2UL)          /*!< SWRF (Bit 2)                                          */
-#define R_SYSTEM_RSTSR1_SWRF_Msk                  (0x4UL)        /*!< SWRF (Bitfield-Mask: 0x01)                            */
-#define R_SYSTEM_RSTSR1_RPERF_Pos                 (8UL)          /*!< RPERF (Bit 8)                                         */
-#define R_SYSTEM_RSTSR1_RPERF_Msk                 (0x100UL)      /*!< RPERF (Bitfield-Mask: 0x01)                           */
-#define R_SYSTEM_RSTSR1_REERF_Pos                 (9UL)          /*!< REERF (Bit 9)                                         */
-#define R_SYSTEM_RSTSR1_REERF_Msk                 (0x200UL)      /*!< REERF (Bitfield-Mask: 0x01)                           */
-#define R_SYSTEM_RSTSR1_BUSMRF_Pos                (11UL)         /*!< BUSMRF (Bit 11)                                       */
-#define R_SYSTEM_RSTSR1_BUSMRF_Msk                (0x800UL)      /*!< BUSMRF (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_RSTSR1_TZERF_Pos                 (13UL)         /*!< TZERF (Bit 13)                                        */
-#define R_SYSTEM_RSTSR1_TZERF_Msk                 (0x2000UL)     /*!< TZERF (Bitfield-Mask: 0x01)                           */
-#define R_SYSTEM_RSTSR1_CPERF_Pos                 (15UL)         /*!< CPERF (Bit 15)                                        */
-#define R_SYSTEM_RSTSR1_CPERF_Msk                 (0x8000UL)     /*!< CPERF (Bitfield-Mask: 0x01)                           */
-/* ========================================================  LVD1CR1  ======================================================== */
-#define R_SYSTEM_LVD1CR1_IDTSEL_Pos               (0UL)          /*!< IDTSEL (Bit 0)                                        */
-#define R_SYSTEM_LVD1CR1_IDTSEL_Msk               (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
-#define R_SYSTEM_LVD1CR1_IRQSEL_Pos               (2UL)          /*!< IRQSEL (Bit 2)                                        */
-#define R_SYSTEM_LVD1CR1_IRQSEL_Msk               (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
-/* ========================================================  LVD1SR  ========================================================= */
-#define R_SYSTEM_LVD1SR_DET_Pos                   (0UL)          /*!< DET (Bit 0)                                           */
-#define R_SYSTEM_LVD1SR_DET_Msk                   (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
-#define R_SYSTEM_LVD1SR_MON_Pos                   (1UL)          /*!< MON (Bit 1)                                           */
-#define R_SYSTEM_LVD1SR_MON_Msk                   (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
-/* ========================================================  LVD2CR1  ======================================================== */
-#define R_SYSTEM_LVD2CR1_IDTSEL_Pos               (0UL)          /*!< IDTSEL (Bit 0)                                        */
-#define R_SYSTEM_LVD2CR1_IDTSEL_Msk               (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
-#define R_SYSTEM_LVD2CR1_IRQSEL_Pos               (2UL)          /*!< IRQSEL (Bit 2)                                        */
-#define R_SYSTEM_LVD2CR1_IRQSEL_Msk               (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
-/* ========================================================  LVD2SR  ========================================================= */
-#define R_SYSTEM_LVD2SR_DET_Pos                   (0UL)          /*!< DET (Bit 0)                                           */
-#define R_SYSTEM_LVD2SR_DET_Msk                   (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
-#define R_SYSTEM_LVD2SR_MON_Pos                   (1UL)          /*!< MON (Bit 1)                                           */
-#define R_SYSTEM_LVD2SR_MON_Msk                   (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
-/* ========================================================  CGFSAR  ========================================================= */
-#define R_SYSTEM_CGFSAR_NONSEC00_Pos              (0UL)          /*!< NONSEC00 (Bit 0)                                      */
-#define R_SYSTEM_CGFSAR_NONSEC00_Msk              (0x1UL)        /*!< NONSEC00 (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_CGFSAR_NONSEC02_Pos              (2UL)          /*!< NONSEC02 (Bit 2)                                      */
-#define R_SYSTEM_CGFSAR_NONSEC02_Msk              (0x4UL)        /*!< NONSEC02 (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_CGFSAR_NONSEC03_Pos              (3UL)          /*!< NONSEC03 (Bit 3)                                      */
-#define R_SYSTEM_CGFSAR_NONSEC03_Msk              (0x8UL)        /*!< NONSEC03 (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_CGFSAR_NONSEC04_Pos              (4UL)          /*!< NONSEC04 (Bit 4)                                      */
-#define R_SYSTEM_CGFSAR_NONSEC04_Msk              (0x10UL)       /*!< NONSEC04 (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_CGFSAR_NONSEC05_Pos              (5UL)          /*!< NONSEC05 (Bit 5)                                      */
-#define R_SYSTEM_CGFSAR_NONSEC05_Msk              (0x20UL)       /*!< NONSEC05 (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_CGFSAR_NONSEC06_Pos              (6UL)          /*!< NONSEC06 (Bit 6)                                      */
-#define R_SYSTEM_CGFSAR_NONSEC06_Msk              (0x40UL)       /*!< NONSEC06 (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_CGFSAR_NONSEC08_Pos              (8UL)          /*!< NONSEC08 (Bit 8)                                      */
-#define R_SYSTEM_CGFSAR_NONSEC08_Msk              (0x100UL)      /*!< NONSEC08 (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_CGFSAR_NONSEC09_Pos              (9UL)          /*!< NONSEC09 (Bit 9)                                      */
-#define R_SYSTEM_CGFSAR_NONSEC09_Msk              (0x200UL)      /*!< NONSEC09 (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_CGFSAR_NONSEC11_Pos              (11UL)         /*!< NONSEC11 (Bit 11)                                     */
-#define R_SYSTEM_CGFSAR_NONSEC11_Msk              (0x800UL)      /*!< NONSEC11 (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_CGFSAR_NONSEC17_Pos              (17UL)         /*!< NONSEC17 (Bit 17)                                     */
-#define R_SYSTEM_CGFSAR_NONSEC17_Msk              (0x20000UL)    /*!< NONSEC17 (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_CGFSAR_NONSEC18_Pos              (18UL)         /*!< NONSEC18 (Bit 18)                                     */
-#define R_SYSTEM_CGFSAR_NONSEC18_Msk              (0x40000UL)    /*!< NONSEC18 (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_CGFSAR_NONSEC19_Pos              (19UL)         /*!< NONSEC19 (Bit 19)                                     */
-#define R_SYSTEM_CGFSAR_NONSEC19_Msk              (0x80000UL)    /*!< NONSEC19 (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_CGFSAR_NONSEC20_Pos              (20UL)         /*!< NONSEC20 (Bit 20)                                     */
-#define R_SYSTEM_CGFSAR_NONSEC20_Msk              (0x100000UL)   /*!< NONSEC20 (Bitfield-Mask: 0x01)                        */
-/* ========================================================  RSTSAR  ========================================================= */
-#define R_SYSTEM_RSTSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
-#define R_SYSTEM_RSTSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_RSTSAR_NONSEC1_Pos               (1UL)          /*!< NONSEC1 (Bit 1)                                       */
-#define R_SYSTEM_RSTSAR_NONSEC1_Msk               (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_RSTSAR_NONSEC2_Pos               (2UL)          /*!< NONSEC2 (Bit 2)                                       */
-#define R_SYSTEM_RSTSAR_NONSEC2_Msk               (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
-/* ========================================================  LPMSAR  ========================================================= */
-#define R_SYSTEM_LPMSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
-#define R_SYSTEM_LPMSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_LPMSAR_NONSEC2_Pos               (2UL)          /*!< NONSEC2 (Bit 2)                                       */
-#define R_SYSTEM_LPMSAR_NONSEC2_Msk               (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_LPMSAR_NONSEC4_Pos               (4UL)          /*!< NONSEC4 (Bit 4)                                       */
-#define R_SYSTEM_LPMSAR_NONSEC4_Msk               (0x10UL)       /*!< NONSEC4 (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_LPMSAR_NONSEC8_Pos               (8UL)          /*!< NONSEC8 (Bit 8)                                       */
-#define R_SYSTEM_LPMSAR_NONSEC8_Msk               (0x100UL)      /*!< NONSEC8 (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_LPMSAR_NONSEC9_Pos               (9UL)          /*!< NONSEC9 (Bit 9)                                       */
-#define R_SYSTEM_LPMSAR_NONSEC9_Msk               (0x200UL)      /*!< NONSEC9 (Bitfield-Mask: 0x01)                         */
-/* ========================================================  LVDSAR  ========================================================= */
-#define R_SYSTEM_LVDSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
-#define R_SYSTEM_LVDSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_LVDSAR_NONSEC1_Pos               (1UL)          /*!< NONSEC1 (Bit 1)                                       */
-#define R_SYSTEM_LVDSAR_NONSEC1_Msk               (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
-/* ========================================================  DPFSAR  ========================================================= */
-#define R_SYSTEM_DPFSAR_DPFSA0_Pos                (0UL)          /*!< DPFSA0 (Bit 0)                                        */
-#define R_SYSTEM_DPFSAR_DPFSA0_Msk                (0x1UL)        /*!< DPFSA0 (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPFSAR_DPFSA1_Pos                (1UL)          /*!< DPFSA1 (Bit 1)                                        */
-#define R_SYSTEM_DPFSAR_DPFSA1_Msk                (0x2UL)        /*!< DPFSA1 (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPFSAR_DPFSA2_Pos                (2UL)          /*!< DPFSA2 (Bit 2)                                        */
-#define R_SYSTEM_DPFSAR_DPFSA2_Msk                (0x4UL)        /*!< DPFSA2 (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPFSAR_DPFSA3_Pos                (3UL)          /*!< DPFSA3 (Bit 3)                                        */
-#define R_SYSTEM_DPFSAR_DPFSA3_Msk                (0x8UL)        /*!< DPFSA3 (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPFSAR_DPFSA4_Pos                (4UL)          /*!< DPFSA4 (Bit 4)                                        */
-#define R_SYSTEM_DPFSAR_DPFSA4_Msk                (0x10UL)       /*!< DPFSA4 (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPFSAR_DPFSA5_Pos                (5UL)          /*!< DPFSA5 (Bit 5)                                        */
-#define R_SYSTEM_DPFSAR_DPFSA5_Msk                (0x20UL)       /*!< DPFSA5 (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPFSAR_DPFSA6_Pos                (6UL)          /*!< DPFSA6 (Bit 6)                                        */
-#define R_SYSTEM_DPFSAR_DPFSA6_Msk                (0x40UL)       /*!< DPFSA6 (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPFSAR_DPFSA7_Pos                (7UL)          /*!< DPFSA7 (Bit 7)                                        */
-#define R_SYSTEM_DPFSAR_DPFSA7_Msk                (0x80UL)       /*!< DPFSA7 (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPFSAR_DPFSA8_Pos                (8UL)          /*!< DPFSA8 (Bit 8)                                        */
-#define R_SYSTEM_DPFSAR_DPFSA8_Msk                (0x100UL)      /*!< DPFSA8 (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPFSAR_DPFSA9_Pos                (9UL)          /*!< DPFSA9 (Bit 9)                                        */
-#define R_SYSTEM_DPFSAR_DPFSA9_Msk                (0x200UL)      /*!< DPFSA9 (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPFSAR_DPFSA10_Pos               (10UL)         /*!< DPFSA10 (Bit 10)                                      */
-#define R_SYSTEM_DPFSAR_DPFSA10_Msk               (0x400UL)      /*!< DPFSA10 (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPFSAR_DPFSA11_Pos               (11UL)         /*!< DPFSA11 (Bit 11)                                      */
-#define R_SYSTEM_DPFSAR_DPFSA11_Msk               (0x800UL)      /*!< DPFSA11 (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPFSAR_DPFSA12_Pos               (12UL)         /*!< DPFSA12 (Bit 12)                                      */
-#define R_SYSTEM_DPFSAR_DPFSA12_Msk               (0x1000UL)     /*!< DPFSA12 (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPFSAR_DPFSA13_Pos               (13UL)         /*!< DPFSA13 (Bit 13)                                      */
-#define R_SYSTEM_DPFSAR_DPFSA13_Msk               (0x2000UL)     /*!< DPFSA13 (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPFSAR_DPFSA14_Pos               (14UL)         /*!< DPFSA14 (Bit 14)                                      */
-#define R_SYSTEM_DPFSAR_DPFSA14_Msk               (0x4000UL)     /*!< DPFSA14 (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPFSAR_DPFSA15_Pos               (15UL)         /*!< DPFSA15 (Bit 15)                                      */
-#define R_SYSTEM_DPFSAR_DPFSA15_Msk               (0x8000UL)     /*!< DPFSA15 (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPFSAR_DPFSA16_Pos               (16UL)         /*!< DPFSA16 (Bit 16)                                      */
-#define R_SYSTEM_DPFSAR_DPFSA16_Msk               (0x10000UL)    /*!< DPFSA16 (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPFSAR_DPFSA17_Pos               (17UL)         /*!< DPFSA17 (Bit 17)                                      */
-#define R_SYSTEM_DPFSAR_DPFSA17_Msk               (0x20000UL)    /*!< DPFSA17 (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPFSAR_DPFSA20_Pos               (20UL)         /*!< DPFSA20 (Bit 20)                                      */
-#define R_SYSTEM_DPFSAR_DPFSA20_Msk               (0x100000UL)   /*!< DPFSA20 (Bitfield-Mask: 0x01)                         */
-/* =========================================================  PRCR  ========================================================== */
-#define R_SYSTEM_PRCR_PRC0_Pos                    (0UL)          /*!< PRC0 (Bit 0)                                          */
-#define R_SYSTEM_PRCR_PRC0_Msk                    (0x1UL)        /*!< PRC0 (Bitfield-Mask: 0x01)                            */
-#define R_SYSTEM_PRCR_PRC1_Pos                    (1UL)          /*!< PRC1 (Bit 1)                                          */
-#define R_SYSTEM_PRCR_PRC1_Msk                    (0x2UL)        /*!< PRC1 (Bitfield-Mask: 0x01)                            */
-#define R_SYSTEM_PRCR_PRC3_Pos                    (3UL)          /*!< PRC3 (Bit 3)                                          */
-#define R_SYSTEM_PRCR_PRC3_Msk                    (0x8UL)        /*!< PRC3 (Bitfield-Mask: 0x01)                            */
-#define R_SYSTEM_PRCR_PRC4_Pos                    (4UL)          /*!< PRC4 (Bit 4)                                          */
-#define R_SYSTEM_PRCR_PRC4_Msk                    (0x10UL)       /*!< PRC4 (Bitfield-Mask: 0x01)                            */
-#define R_SYSTEM_PRCR_PRKEY_Pos                   (8UL)          /*!< PRKEY (Bit 8)                                         */
-#define R_SYSTEM_PRCR_PRKEY_Msk                   (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
-/* ========================================================  DPSBYCR  ======================================================== */
-#define R_SYSTEM_DPSBYCR_DEEPCUT_Pos              (0UL)          /*!< DEEPCUT (Bit 0)                                       */
-#define R_SYSTEM_DPSBYCR_DEEPCUT_Msk              (0x3UL)        /*!< DEEPCUT (Bitfield-Mask: 0x03)                         */
-#define R_SYSTEM_DPSBYCR_IOKEEP_Pos               (6UL)          /*!< IOKEEP (Bit 6)                                        */
-#define R_SYSTEM_DPSBYCR_IOKEEP_Msk               (0x40UL)       /*!< IOKEEP (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPSBYCR_DPSBY_Pos                (7UL)          /*!< DPSBY (Bit 7)                                         */
-#define R_SYSTEM_DPSBYCR_DPSBY_Msk                (0x80UL)       /*!< DPSBY (Bitfield-Mask: 0x01)                           */
-/* ========================================================  DPSWCR  ========================================================= */
-#define R_SYSTEM_DPSWCR_WTSTS_Pos                 (0UL)          /*!< WTSTS (Bit 0)                                         */
-#define R_SYSTEM_DPSWCR_WTSTS_Msk                 (0x3fUL)       /*!< WTSTS (Bitfield-Mask: 0x3f)                           */
-/* ========================================================  DPSIER0  ======================================================== */
-#define R_SYSTEM_DPSIER0_DIRQ0E_Pos               (0UL)          /*!< DIRQ0E (Bit 0)                                        */
-#define R_SYSTEM_DPSIER0_DIRQ0E_Msk               (0x1UL)        /*!< DIRQ0E (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPSIER0_DIRQ1E_Pos               (1UL)          /*!< DIRQ1E (Bit 1)                                        */
-#define R_SYSTEM_DPSIER0_DIRQ1E_Msk               (0x2UL)        /*!< DIRQ1E (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPSIER0_DIRQ2E_Pos               (2UL)          /*!< DIRQ2E (Bit 2)                                        */
-#define R_SYSTEM_DPSIER0_DIRQ2E_Msk               (0x4UL)        /*!< DIRQ2E (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPSIER0_DIRQ3E_Pos               (3UL)          /*!< DIRQ3E (Bit 3)                                        */
-#define R_SYSTEM_DPSIER0_DIRQ3E_Msk               (0x8UL)        /*!< DIRQ3E (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPSIER0_DIRQ4E_Pos               (4UL)          /*!< DIRQ4E (Bit 4)                                        */
-#define R_SYSTEM_DPSIER0_DIRQ4E_Msk               (0x10UL)       /*!< DIRQ4E (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPSIER0_DIRQ5E_Pos               (5UL)          /*!< DIRQ5E (Bit 5)                                        */
-#define R_SYSTEM_DPSIER0_DIRQ5E_Msk               (0x20UL)       /*!< DIRQ5E (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPSIER0_DIRQ6E_Pos               (6UL)          /*!< DIRQ6E (Bit 6)                                        */
-#define R_SYSTEM_DPSIER0_DIRQ6E_Msk               (0x40UL)       /*!< DIRQ6E (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPSIER0_DIRQ7E_Pos               (7UL)          /*!< DIRQ7E (Bit 7)                                        */
-#define R_SYSTEM_DPSIER0_DIRQ7E_Msk               (0x80UL)       /*!< DIRQ7E (Bitfield-Mask: 0x01)                          */
-/* ========================================================  DPSIER1  ======================================================== */
-#define R_SYSTEM_DPSIER1_DIRQ8E_Pos               (0UL)          /*!< DIRQ8E (Bit 0)                                        */
-#define R_SYSTEM_DPSIER1_DIRQ8E_Msk               (0x1UL)        /*!< DIRQ8E (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPSIER1_DIRQ9E_Pos               (1UL)          /*!< DIRQ9E (Bit 1)                                        */
-#define R_SYSTEM_DPSIER1_DIRQ9E_Msk               (0x2UL)        /*!< DIRQ9E (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPSIER1_DIRQ10E_Pos              (2UL)          /*!< DIRQ10E (Bit 2)                                       */
-#define R_SYSTEM_DPSIER1_DIRQ10E_Msk              (0x4UL)        /*!< DIRQ10E (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIER1_DIRQ11E_Pos              (3UL)          /*!< DIRQ11E (Bit 3)                                       */
-#define R_SYSTEM_DPSIER1_DIRQ11E_Msk              (0x8UL)        /*!< DIRQ11E (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIER1_DIRQ12E_Pos              (4UL)          /*!< DIRQ12E (Bit 4)                                       */
-#define R_SYSTEM_DPSIER1_DIRQ12E_Msk              (0x10UL)       /*!< DIRQ12E (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIER1_DIRQ13E_Pos              (5UL)          /*!< DIRQ13E (Bit 5)                                       */
-#define R_SYSTEM_DPSIER1_DIRQ13E_Msk              (0x20UL)       /*!< DIRQ13E (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIER1_DIRQ14E_Pos              (6UL)          /*!< DIRQ14E (Bit 6)                                       */
-#define R_SYSTEM_DPSIER1_DIRQ14E_Msk              (0x40UL)       /*!< DIRQ14E (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIER1_DIRQ15E_Pos              (7UL)          /*!< DIRQ15E (Bit 7)                                       */
-#define R_SYSTEM_DPSIER1_DIRQ15E_Msk              (0x80UL)       /*!< DIRQ15E (Bitfield-Mask: 0x01)                         */
-/* ========================================================  DPSIER2  ======================================================== */
-#define R_SYSTEM_DPSIER2_DLVD1IE_Pos              (0UL)          /*!< DLVD1IE (Bit 0)                                       */
-#define R_SYSTEM_DPSIER2_DLVD1IE_Msk              (0x1UL)        /*!< DLVD1IE (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIER2_DLVD2IE_Pos              (1UL)          /*!< DLVD2IE (Bit 1)                                       */
-#define R_SYSTEM_DPSIER2_DLVD2IE_Msk              (0x2UL)        /*!< DLVD2IE (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIER2_DNMIE_Pos                (4UL)          /*!< DNMIE (Bit 4)                                         */
-#define R_SYSTEM_DPSIER2_DNMIE_Msk                (0x10UL)       /*!< DNMIE (Bitfield-Mask: 0x01)                           */
-/* ========================================================  DPSIFR0  ======================================================== */
-#define R_SYSTEM_DPSIFR0_DIRQ0F_Pos               (0UL)          /*!< DIRQ0F (Bit 0)                                        */
-#define R_SYSTEM_DPSIFR0_DIRQ0F_Msk               (0x1UL)        /*!< DIRQ0F (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPSIFR0_DIRQ1F_Pos               (1UL)          /*!< DIRQ1F (Bit 1)                                        */
-#define R_SYSTEM_DPSIFR0_DIRQ1F_Msk               (0x2UL)        /*!< DIRQ1F (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPSIFR0_DIRQ2F_Pos               (2UL)          /*!< DIRQ2F (Bit 2)                                        */
-#define R_SYSTEM_DPSIFR0_DIRQ2F_Msk               (0x4UL)        /*!< DIRQ2F (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPSIFR0_DIRQ3F_Pos               (3UL)          /*!< DIRQ3F (Bit 3)                                        */
-#define R_SYSTEM_DPSIFR0_DIRQ3F_Msk               (0x8UL)        /*!< DIRQ3F (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPSIFR0_DIRQ4F_Pos               (4UL)          /*!< DIRQ4F (Bit 4)                                        */
-#define R_SYSTEM_DPSIFR0_DIRQ4F_Msk               (0x10UL)       /*!< DIRQ4F (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPSIFR0_DIRQ5F_Pos               (5UL)          /*!< DIRQ5F (Bit 5)                                        */
-#define R_SYSTEM_DPSIFR0_DIRQ5F_Msk               (0x20UL)       /*!< DIRQ5F (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPSIFR0_DIRQ6F_Pos               (6UL)          /*!< DIRQ6F (Bit 6)                                        */
-#define R_SYSTEM_DPSIFR0_DIRQ6F_Msk               (0x40UL)       /*!< DIRQ6F (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPSIFR0_DIRQ7F_Pos               (7UL)          /*!< DIRQ7F (Bit 7)                                        */
-#define R_SYSTEM_DPSIFR0_DIRQ7F_Msk               (0x80UL)       /*!< DIRQ7F (Bitfield-Mask: 0x01)                          */
-/* ========================================================  DPSIFR1  ======================================================== */
-#define R_SYSTEM_DPSIFR1_DIRQ8F_Pos               (0UL)          /*!< DIRQ8F (Bit 0)                                        */
-#define R_SYSTEM_DPSIFR1_DIRQ8F_Msk               (0x1UL)        /*!< DIRQ8F (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPSIFR1_DIRQ9F_Pos               (1UL)          /*!< DIRQ9F (Bit 1)                                        */
-#define R_SYSTEM_DPSIFR1_DIRQ9F_Msk               (0x2UL)        /*!< DIRQ9F (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_DPSIFR1_DIRQ10F_Pos              (2UL)          /*!< DIRQ10F (Bit 2)                                       */
-#define R_SYSTEM_DPSIFR1_DIRQ10F_Msk              (0x4UL)        /*!< DIRQ10F (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIFR1_DIRQ11F_Pos              (3UL)          /*!< DIRQ11F (Bit 3)                                       */
-#define R_SYSTEM_DPSIFR1_DIRQ11F_Msk              (0x8UL)        /*!< DIRQ11F (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIFR1_DIRQ12F_Pos              (4UL)          /*!< DIRQ12F (Bit 4)                                       */
-#define R_SYSTEM_DPSIFR1_DIRQ12F_Msk              (0x10UL)       /*!< DIRQ12F (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIFR1_DIRQ13F_Pos              (5UL)          /*!< DIRQ13F (Bit 5)                                       */
-#define R_SYSTEM_DPSIFR1_DIRQ13F_Msk              (0x20UL)       /*!< DIRQ13F (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIFR1_DIRQ14F_Pos              (6UL)          /*!< DIRQ14F (Bit 6)                                       */
-#define R_SYSTEM_DPSIFR1_DIRQ14F_Msk              (0x40UL)       /*!< DIRQ14F (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIFR1_DIRQ15F_Pos              (7UL)          /*!< DIRQ15F (Bit 7)                                       */
-#define R_SYSTEM_DPSIFR1_DIRQ15F_Msk              (0x80UL)       /*!< DIRQ15F (Bitfield-Mask: 0x01)                         */
-/* ========================================================  DPSIFR2  ======================================================== */
-#define R_SYSTEM_DPSIFR2_DLVD1IF_Pos              (0UL)          /*!< DLVD1IF (Bit 0)                                       */
-#define R_SYSTEM_DPSIFR2_DLVD1IF_Msk              (0x1UL)        /*!< DLVD1IF (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIFR2_DLVD2IF_Pos              (1UL)          /*!< DLVD2IF (Bit 1)                                       */
-#define R_SYSTEM_DPSIFR2_DLVD2IF_Msk              (0x2UL)        /*!< DLVD2IF (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIFR2_DNMIF_Pos                (4UL)          /*!< DNMIF (Bit 4)                                         */
-#define R_SYSTEM_DPSIFR2_DNMIF_Msk                (0x10UL)       /*!< DNMIF (Bitfield-Mask: 0x01)                           */
-/* =======================================================  DPSIEGR0  ======================================================== */
-#define R_SYSTEM_DPSIEGR0_DIRQ0EG_Pos             (0UL)          /*!< DIRQ0EG (Bit 0)                                       */
-#define R_SYSTEM_DPSIEGR0_DIRQ0EG_Msk             (0x1UL)        /*!< DIRQ0EG (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIEGR0_DIRQ1EG_Pos             (1UL)          /*!< DIRQ1EG (Bit 1)                                       */
-#define R_SYSTEM_DPSIEGR0_DIRQ1EG_Msk             (0x2UL)        /*!< DIRQ1EG (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIEGR0_DIRQ2EG_Pos             (2UL)          /*!< DIRQ2EG (Bit 2)                                       */
-#define R_SYSTEM_DPSIEGR0_DIRQ2EG_Msk             (0x4UL)        /*!< DIRQ2EG (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIEGR0_DIRQ3EG_Pos             (3UL)          /*!< DIRQ3EG (Bit 3)                                       */
-#define R_SYSTEM_DPSIEGR0_DIRQ3EG_Msk             (0x8UL)        /*!< DIRQ3EG (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIEGR0_DIRQ4EG_Pos             (4UL)          /*!< DIRQ4EG (Bit 4)                                       */
-#define R_SYSTEM_DPSIEGR0_DIRQ4EG_Msk             (0x10UL)       /*!< DIRQ4EG (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIEGR0_DIRQ5EG_Pos             (5UL)          /*!< DIRQ5EG (Bit 5)                                       */
-#define R_SYSTEM_DPSIEGR0_DIRQ5EG_Msk             (0x20UL)       /*!< DIRQ5EG (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIEGR0_DIRQ6EG_Pos             (6UL)          /*!< DIRQ6EG (Bit 6)                                       */
-#define R_SYSTEM_DPSIEGR0_DIRQ6EG_Msk             (0x40UL)       /*!< DIRQ6EG (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIEGR0_DIRQ7EG_Pos             (7UL)          /*!< DIRQ7EG (Bit 7)                                       */
-#define R_SYSTEM_DPSIEGR0_DIRQ7EG_Msk             (0x80UL)       /*!< DIRQ7EG (Bitfield-Mask: 0x01)                         */
-/* =======================================================  DPSIEGR1  ======================================================== */
-#define R_SYSTEM_DPSIEGR1_DIRQ8EG_Pos             (0UL)          /*!< DIRQ8EG (Bit 0)                                       */
-#define R_SYSTEM_DPSIEGR1_DIRQ8EG_Msk             (0x1UL)        /*!< DIRQ8EG (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIEGR1_DIRQ9EG_Pos             (1UL)          /*!< DIRQ9EG (Bit 1)                                       */
-#define R_SYSTEM_DPSIEGR1_DIRQ9EG_Msk             (0x2UL)        /*!< DIRQ9EG (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIEGR1_DIRQ10EG_Pos            (2UL)          /*!< DIRQ10EG (Bit 2)                                      */
-#define R_SYSTEM_DPSIEGR1_DIRQ10EG_Msk            (0x4UL)        /*!< DIRQ10EG (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_DPSIEGR1_DIRQ11EG_Pos            (3UL)          /*!< DIRQ11EG (Bit 3)                                      */
-#define R_SYSTEM_DPSIEGR1_DIRQ11EG_Msk            (0x8UL)        /*!< DIRQ11EG (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_DPSIEGR1_DIRQ12EG_Pos            (4UL)          /*!< DIRQ12EG (Bit 4)                                      */
-#define R_SYSTEM_DPSIEGR1_DIRQ12EG_Msk            (0x10UL)       /*!< DIRQ12EG (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_DPSIEGR1_DIRQ13EG_Pos            (5UL)          /*!< DIRQ13EG (Bit 5)                                      */
-#define R_SYSTEM_DPSIEGR1_DIRQ13EG_Msk            (0x20UL)       /*!< DIRQ13EG (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_DPSIEGR1_DIRQ14EG_Pos            (6UL)          /*!< DIRQ14EG (Bit 6)                                      */
-#define R_SYSTEM_DPSIEGR1_DIRQ14EG_Msk            (0x40UL)       /*!< DIRQ14EG (Bitfield-Mask: 0x01)                        */
-#define R_SYSTEM_DPSIEGR1_DIRQ15EG_Pos            (7UL)          /*!< DIRQ15EG (Bit 7)                                      */
-#define R_SYSTEM_DPSIEGR1_DIRQ15EG_Msk            (0x80UL)       /*!< DIRQ15EG (Bitfield-Mask: 0x01)                        */
-/* =======================================================  DPSIEGR2  ======================================================== */
-#define R_SYSTEM_DPSIEGR2_DLVD1EG_Pos             (0UL)          /*!< DLVD1EG (Bit 0)                                       */
-#define R_SYSTEM_DPSIEGR2_DLVD1EG_Msk             (0x1UL)        /*!< DLVD1EG (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIEGR2_DLVD2EG_Pos             (1UL)          /*!< DLVD2EG (Bit 1)                                       */
-#define R_SYSTEM_DPSIEGR2_DLVD2EG_Msk             (0x2UL)        /*!< DLVD2EG (Bitfield-Mask: 0x01)                         */
-#define R_SYSTEM_DPSIEGR2_DNMIEG_Pos              (4UL)          /*!< DNMIEG (Bit 4)                                        */
-#define R_SYSTEM_DPSIEGR2_DNMIEG_Msk              (0x10UL)       /*!< DNMIEG (Bitfield-Mask: 0x01)                          */
-/* ========================================================  SYOCDCR  ======================================================== */
-#define R_SYSTEM_SYOCDCR_DOCDF_Pos                (0UL)          /*!< DOCDF (Bit 0)                                         */
-#define R_SYSTEM_SYOCDCR_DOCDF_Msk                (0x1UL)        /*!< DOCDF (Bitfield-Mask: 0x01)                           */
-#define R_SYSTEM_SYOCDCR_DBGEN_Pos                (7UL)          /*!< DBGEN (Bit 7)                                         */
-#define R_SYSTEM_SYOCDCR_DBGEN_Msk                (0x80UL)       /*!< DBGEN (Bitfield-Mask: 0x01)                           */
-/* ========================================================  RSTSR0  ========================================================= */
-#define R_SYSTEM_RSTSR0_PORF_Pos                  (0UL)          /*!< PORF (Bit 0)                                          */
-#define R_SYSTEM_RSTSR0_PORF_Msk                  (0x1UL)        /*!< PORF (Bitfield-Mask: 0x01)                            */
-#define R_SYSTEM_RSTSR0_LVD0RF_Pos                (1UL)          /*!< LVD0RF (Bit 1)                                        */
-#define R_SYSTEM_RSTSR0_LVD0RF_Msk                (0x2UL)        /*!< LVD0RF (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_RSTSR0_LVD1RF_Pos                (2UL)          /*!< LVD1RF (Bit 2)                                        */
-#define R_SYSTEM_RSTSR0_LVD1RF_Msk                (0x4UL)        /*!< LVD1RF (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_RSTSR0_LVD2RF_Pos                (3UL)          /*!< LVD2RF (Bit 3)                                        */
-#define R_SYSTEM_RSTSR0_LVD2RF_Msk                (0x8UL)        /*!< LVD2RF (Bitfield-Mask: 0x01)                          */
-#define R_SYSTEM_RSTSR0_DPSRSTF_Pos               (7UL)          /*!< DPSRSTF (Bit 7)                                       */
-#define R_SYSTEM_RSTSR0_DPSRSTF_Msk               (0x80UL)       /*!< DPSRSTF (Bitfield-Mask: 0x01)                         */
-/* ========================================================  RSTSR2  ========================================================= */
-#define R_SYSTEM_RSTSR2_CWSF_Pos                  (0UL)          /*!< CWSF (Bit 0)                                          */
-#define R_SYSTEM_RSTSR2_CWSF_Msk                  (0x1UL)        /*!< CWSF (Bitfield-Mask: 0x01)                            */
-/* =========================================================  MOMCR  ========================================================= */
-#define R_SYSTEM_MOMCR_MODRV_Pos                  (4UL)          /*!< MODRV (Bit 4)                                         */
-#define R_SYSTEM_MOMCR_MODRV_Msk                  (0x30UL)       /*!< MODRV (Bitfield-Mask: 0x03)                           */
-#define R_SYSTEM_MOMCR_MOSEL_Pos                  (6UL)          /*!< MOSEL (Bit 6)                                         */
-#define R_SYSTEM_MOMCR_MOSEL_Msk                  (0x40UL)       /*!< MOSEL (Bitfield-Mask: 0x01)                           */
-/* ========================================================  FWEPROR  ======================================================== */
-#define R_SYSTEM_FWEPROR_FLWE_Pos                 (0UL)          /*!< FLWE (Bit 0)                                          */
-#define R_SYSTEM_FWEPROR_FLWE_Msk                 (0x3UL)        /*!< FLWE (Bitfield-Mask: 0x03)                            */
-/* =======================================================  LVD1CMPCR  ======================================================= */
-#define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos            (0UL)          /*!< LVD1LVL (Bit 0)                                       */
-#define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk            (0x1fUL)       /*!< LVD1LVL (Bitfield-Mask: 0x1f)                         */
-#define R_SYSTEM_LVD1CMPCR_LVD1E_Pos              (7UL)          /*!< LVD1E (Bit 7)                                         */
-#define R_SYSTEM_LVD1CMPCR_LVD1E_Msk              (0x80UL)       /*!< LVD1E (Bitfield-Mask: 0x01)                           */
-/* =======================================================  LVD2CMPCR  ======================================================= */
-#define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos            (0UL)          /*!< LVD2LVL (Bit 0)                                       */
-#define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk            (0x7UL)        /*!< LVD2LVL (Bitfield-Mask: 0x07)                         */
-#define R_SYSTEM_LVD2CMPCR_LVD2E_Pos              (7UL)          /*!< LVD2E (Bit 7)                                         */
-#define R_SYSTEM_LVD2CMPCR_LVD2E_Msk              (0x80UL)       /*!< LVD2E (Bitfield-Mask: 0x01)                           */
-/* ========================================================  LVD1CR0  ======================================================== */
-#define R_SYSTEM_LVD1CR0_RIE_Pos                  (0UL)          /*!< RIE (Bit 0)                                           */
-#define R_SYSTEM_LVD1CR0_RIE_Msk                  (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
-#define R_SYSTEM_LVD1CR0_DFDIS_Pos                (1UL)          /*!< DFDIS (Bit 1)                                         */
-#define R_SYSTEM_LVD1CR0_DFDIS_Msk                (0x2UL)        /*!< DFDIS (Bitfield-Mask: 0x01)                           */
-#define R_SYSTEM_LVD1CR0_CMPE_Pos                 (2UL)          /*!< CMPE (Bit 2)                                          */
-#define R_SYSTEM_LVD1CR0_CMPE_Msk                 (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
-#define R_SYSTEM_LVD1CR0_FSAMP_Pos                (4UL)          /*!< FSAMP (Bit 4)                                         */
-#define R_SYSTEM_LVD1CR0_FSAMP_Msk                (0x30UL)       /*!< FSAMP (Bitfield-Mask: 0x03)                           */
-#define R_SYSTEM_LVD1CR0_RI_Pos                   (6UL)          /*!< RI (Bit 6)                                            */
-#define R_SYSTEM_LVD1CR0_RI_Msk                   (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
-#define R_SYSTEM_LVD1CR0_RN_Pos                   (7UL)          /*!< RN (Bit 7)                                            */
-#define R_SYSTEM_LVD1CR0_RN_Msk                   (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
-/* ========================================================  LVD2CR0  ======================================================== */
-#define R_SYSTEM_LVD2CR0_RIE_Pos                  (0UL)          /*!< RIE (Bit 0)                                           */
-#define R_SYSTEM_LVD2CR0_RIE_Msk                  (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
-#define R_SYSTEM_LVD2CR0_DFDIS_Pos                (1UL)          /*!< DFDIS (Bit 1)                                         */
-#define R_SYSTEM_LVD2CR0_DFDIS_Msk                (0x2UL)        /*!< DFDIS (Bitfield-Mask: 0x01)                           */
-#define R_SYSTEM_LVD2CR0_CMPE_Pos                 (2UL)          /*!< CMPE (Bit 2)                                          */
-#define R_SYSTEM_LVD2CR0_CMPE_Msk                 (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
-#define R_SYSTEM_LVD2CR0_FSAMP_Pos                (4UL)          /*!< FSAMP (Bit 4)                                         */
-#define R_SYSTEM_LVD2CR0_FSAMP_Msk                (0x30UL)       /*!< FSAMP (Bitfield-Mask: 0x03)                           */
-#define R_SYSTEM_LVD2CR0_RI_Pos                   (6UL)          /*!< RI (Bit 6)                                            */
-#define R_SYSTEM_LVD2CR0_RI_Msk                   (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
-#define R_SYSTEM_LVD2CR0_RN_Pos                   (7UL)          /*!< RN (Bit 7)                                            */
-#define R_SYSTEM_LVD2CR0_RN_Msk                   (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
-/* ========================================================  LOCOCR  ========================================================= */
-#define R_SYSTEM_LOCOCR_LCSTP_Pos                 (0UL)          /*!< LCSTP (Bit 0)                                         */
-#define R_SYSTEM_LOCOCR_LCSTP_Msk                 (0x1UL)        /*!< LCSTP (Bitfield-Mask: 0x01)                           */
-/* =======================================================  LOCOUTCR  ======================================================== */
-#define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos            (0UL)          /*!< LOCOUTRM (Bit 0)                                      */
-#define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk            (0xffUL)       /*!< LOCOUTRM (Bitfield-Mask: 0xff)                        */
-
-/***********************************************************************************************************************
- * Exported global variables
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Exported global functions (to be accessed by other files)
- **********************************************************************************************************************/
-
-#endif
diff --git a/ra/fsp/src/r_acmphs/r_acmphs.c b/ra/fsp/src/r_acmphs/r_acmphs.c
index 2a6ce2b83..cdee2c0f5 100644
--- a/ra/fsp/src/r_acmphs/r_acmphs.c
+++ b/ra/fsp/src/r_acmphs/r_acmphs.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_acmplp/r_acmplp.c b/ra/fsp/src/r_acmplp/r_acmplp.c
index 2457b287f..639202812 100644
--- a/ra/fsp/src/r_acmplp/r_acmplp.c
+++ b/ra/fsp/src/r_acmplp/r_acmplp.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_adc/r_adc.c b/ra/fsp/src/r_adc/r_adc.c
index 23d41b1d5..2ced6d8a2 100644
--- a/ra/fsp/src/r_adc/r_adc.c
+++ b/ra/fsp/src/r_adc/r_adc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_adc_b/r_adc_b.c b/ra/fsp/src/r_adc_b/r_adc_b.c
index e9c456423..d9e351135 100644
--- a/ra/fsp/src/r_adc_b/r_adc_b.c
+++ b/ra/fsp/src/r_adc_b/r_adc_b.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_agt/r_agt.c b/ra/fsp/src/r_agt/r_agt.c
index 43674a6b6..131735da9 100644
--- a/ra/fsp/src/r_agt/r_agt.c
+++ b/ra/fsp/src/r_agt/r_agt.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -54,12 +54,20 @@
 
 #define AGT_PRV_MIN_CLOCK_FREQ                  (0U)
 
-#if 1U == BSP_FEATURE_AGT_HAS_AGTW
- #define AGT_IODEFINE(reg)    R_AGTW0_ ## reg
+#if (BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT > 0)
+ #if (BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT < (BSP_FEATURE_AGT_MAX_CHANNEL_NUM + 1))
+  #define AGT_PRV_IS_AGTW(p_instance_ctrl)    ((p_instance_ctrl)->p_cfg->channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT)
+ #else
+  #define AGT_PRV_IS_AGTW(p_instance_ctrl)    (true)
+ #endif
 #else
- #define AGT_IODEFINE(reg)    R_AGT0_ ## reg
+ #define AGT_PRV_IS_AGTW(p_instance_ctrl)     (false)
 #endif
 
+#define AGT_PRV_CTRL_PTR(p_instance_ctrl)     ((agt_prv_reg_ctrl_ptr_t) (AGT_PRV_IS_AGTW((p_instance_ctrl))      \
+                                                                         ? &(p_instance_ctrl)->p_reg->AGT32.CTRL \
+                                                                         : &(p_instance_ctrl)->p_reg->AGT16.CTRL))
+
 /**********************************************************************************************************************
  * Typedef definitions
  **********************************************************************************************************************/
@@ -69,6 +77,8 @@ typedef void (BSP_CMSE_NONSECURE_CALL * agt_prv_ns_callback)(timer_callback_args
 typedef BSP_CMSE_NONSECURE_CALL void (*volatile agt_prv_ns_callback)(timer_callback_args_t * p_args);
 #endif
 
+typedef volatile R_AGTX0_AGT16_CTRL_Type * const agt_prv_reg_ctrl_ptr_t;
+
 /***********************************************************************************************************************
  * Private function prototypes
  **********************************************************************************************************************/
@@ -76,13 +86,7 @@ static void r_agt_period_register_set(agt_instance_ctrl_t * p_instance_ctrl, uin
 
 static void r_agt_hardware_cfg(agt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg);
 
-#if BSP_FEATURE_AGT_HAS_AGTW
-static uint32_t r_agt_clock_frequency_get(R_AGTW0_Type * p_agt_regs);
-
-#else
-static uint32_t r_agt_clock_frequency_get(R_AGT0_Type * p_agt_regs);
-
-#endif
+static uint32_t r_agt_clock_frequency_get(R_AGTX0_Type * p_agt_regs, bool is_agtw);
 
 static fsp_err_t r_agt_common_preamble(agt_instance_ctrl_t * p_instance_ctrl);
 
@@ -161,28 +165,25 @@ fsp_err_t R_AGT_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_c
     FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
 #endif
 
-#if BSP_FEATURE_AGT_HAS_AGTW
-    uint32_t base_address = (uint32_t) R_AGTW0 + (p_cfg->channel * ((uint32_t) R_AGTW1 - (uint32_t) R_AGTW0));
-    p_instance_ctrl->p_reg = (R_AGTW0_Type *) base_address;
-#else
-    uint32_t base_address = (uint32_t) R_AGT0 + (p_cfg->channel * ((uint32_t) R_AGT1 - (uint32_t) R_AGT0));
-    p_instance_ctrl->p_reg = (R_AGT0_Type *) base_address;
-#endif
+    uint32_t base_address = (uint32_t) R_AGTX0 + (p_cfg->channel * ((uint32_t) R_AGTX1 - (uint32_t) R_AGTX0));
+    p_instance_ctrl->p_reg = (R_AGTX0_Type *) base_address;
 
     p_instance_ctrl->p_cfg = p_cfg;
 
+    agt_prv_reg_ctrl_ptr_t p_reg_ctrl = AGT_PRV_CTRL_PTR(p_instance_ctrl);
+
     /* Power on the AGT channel. */
     R_BSP_MODULE_START(FSP_IP_AGT, p_cfg->channel);
 
     /* Clear AGTCR. This stops the timer if it is running and clears the flags. */
-    p_instance_ctrl->p_reg->AGTCR = 0U;
+    p_reg_ctrl->AGTCR = 0U;
 
     /* The timer is stopped in sync with the count clock, or in sync with PCLK in event and external count modes. */
-    FSP_HARDWARE_REGISTER_WAIT(0U, p_instance_ctrl->p_reg->AGTCR_b.TCSTF);
+    FSP_HARDWARE_REGISTER_WAIT(0U, p_reg_ctrl->AGTCR_b.TCSTF);
 
     /* Clear AGTMR2 before AGTMR1 is set. Reference Note 3 in section 25.2.6 "AGT Mode Register 2 (AGTMR2)"
      * of the RA6M3 manual R01UH0886EJ0100. */
-    p_instance_ctrl->p_reg->AGTMR2 = 0U;
+    p_reg_ctrl->AGTMR2 = 0U;
 
     /* Set count source and divider and configure pins. */
     r_agt_hardware_cfg(p_instance_ctrl, p_cfg);
@@ -223,6 +224,8 @@ fsp_err_t R_AGT_Start (timer_ctrl_t * const p_ctrl)
     fsp_err_t err = r_agt_common_preamble(p_instance_ctrl);
     FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
 
+    agt_prv_reg_ctrl_ptr_t p_reg_ctrl = AGT_PRV_CTRL_PTR(p_instance_ctrl);
+
     /* Reload period register for one-shot timers. This must be done here instead of in the underflow interrupt because
      * setting AGTCR.TSTOP causes AGT to be reset after 3 cycles of the count source. When the AGT count source is much
      * slower than the core clock, 3 cycles of the count source is too long to wait in an interrupt. */
@@ -233,7 +236,7 @@ fsp_err_t R_AGT_Start (timer_ctrl_t * const p_ctrl)
     }
 
     /* Start timer */
-    p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_START_TIMER;
+    p_reg_ctrl->AGTCR = AGT_PRV_AGTCR_START_TIMER;
 
 #if AGT_CFG_OUTPUT_SUPPORT_ENABLE
 
@@ -243,15 +246,18 @@ fsp_err_t R_AGT_Start (timer_ctrl_t * const p_ctrl)
     {
         /* Verify the timer is started before modifying any other AGT registers. Reference section 25.4.1 "Count
          * Operation Start and Stop Control" in the RA6M3 manual R01UH0886EJ0100. */
-        FSP_HARDWARE_REGISTER_WAIT(1U, p_instance_ctrl->p_reg->AGTCR_b.TCSTF);
+        FSP_HARDWARE_REGISTER_WAIT(1U, p_reg_ctrl->AGTCR_b.TCSTF);
 
- #if BSP_FEATURE_AGT_HAS_AGTW
-        p_instance_ctrl->p_reg->AGTCMA = UINT32_MAX;
-        p_instance_ctrl->p_reg->AGTCMB = UINT32_MAX;
- #else
-        p_instance_ctrl->p_reg->AGTCMA = UINT16_MAX;
-        p_instance_ctrl->p_reg->AGTCMB = UINT16_MAX;
- #endif
+        if (AGT_PRV_IS_AGTW(p_instance_ctrl))
+        {
+            p_instance_ctrl->p_reg->AGT32.AGTCMA = UINT32_MAX;
+            p_instance_ctrl->p_reg->AGT32.AGTCMB = UINT32_MAX;
+        }
+        else
+        {
+            p_instance_ctrl->p_reg->AGT16.AGTCMA = UINT16_MAX;
+            p_instance_ctrl->p_reg->AGT16.AGTCMB = UINT16_MAX;
+        }
     }
 #endif
 
@@ -275,8 +281,10 @@ fsp_err_t R_AGT_Stop (timer_ctrl_t * const p_ctrl)
     fsp_err_t err = r_agt_common_preamble(p_instance_ctrl);
     FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
 
+    agt_prv_reg_ctrl_ptr_t p_reg_ctrl = AGT_PRV_CTRL_PTR(p_instance_ctrl);
+
     /* Stop timer */
-    p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_STOP_TIMER;
+    p_reg_ctrl->AGTCR = AGT_PRV_AGTCR_STOP_TIMER;
 
     return FSP_SUCCESS;
 }
@@ -296,11 +304,14 @@ fsp_err_t R_AGT_Reset (timer_ctrl_t * const p_ctrl)
     FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
 
     /* Reset counter to period minus one. */
-#if BSP_FEATURE_AGT_HAS_AGTW
-    p_instance_ctrl->p_reg->AGT = (uint32_t) (p_instance_ctrl->period - 1U);
-#else
-    p_instance_ctrl->p_reg->AGT = (uint16_t) (p_instance_ctrl->period - 1U);
-#endif
+    if (AGT_PRV_IS_AGTW(p_instance_ctrl))
+    {
+        p_instance_ctrl->p_reg->AGT32.AGT = (uint32_t) (p_instance_ctrl->period - 1U);
+    }
+    else
+    {
+        p_instance_ctrl->p_reg->AGT16.AGT = (uint16_t) (p_instance_ctrl->period - 1U);
+    }
 
     return FSP_SUCCESS;
 }
@@ -323,15 +334,20 @@ fsp_err_t R_AGT_Enable (timer_ctrl_t * const p_ctrl)
     FSP_ERROR_RETURN(AGT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
 #endif
 
+    agt_prv_reg_ctrl_ptr_t p_reg_ctrl = AGT_PRV_CTRL_PTR(p_instance_ctrl);
+
     /* Reset counter to period minus one. */
-#if BSP_FEATURE_AGT_HAS_AGTW
-    p_instance_ctrl->p_reg->AGT = (uint32_t) (p_instance_ctrl->period - 1U);
-#else
-    p_instance_ctrl->p_reg->AGT = (uint16_t) (p_instance_ctrl->period - 1U);
-#endif
+    if (AGT_PRV_IS_AGTW(p_instance_ctrl))
+    {
+        p_instance_ctrl->p_reg->AGT32.AGT = (uint32_t) (p_instance_ctrl->period - 1U);
+    }
+    else
+    {
+        p_instance_ctrl->p_reg->AGT16.AGT = (uint16_t) (p_instance_ctrl->period - 1U);
+    }
 
     /* Enable captures. */
-    p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_START_TIMER;
+    p_reg_ctrl->AGTCR = AGT_PRV_AGTCR_START_TIMER;
 
     return FSP_SUCCESS;
 }
@@ -354,8 +370,10 @@ fsp_err_t R_AGT_Disable (timer_ctrl_t * const p_ctrl)
     FSP_ERROR_RETURN(AGT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
 #endif
 
+    agt_prv_reg_ctrl_ptr_t p_reg_ctrl = AGT_PRV_CTRL_PTR(p_instance_ctrl);
+
     /* Disable captures. */
-    p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_STOP_TIMER;
+    p_reg_ctrl->AGTCR = AGT_PRV_AGTCR_STOP_TIMER;
 
     return FSP_SUCCESS;
 }
@@ -381,18 +399,19 @@ fsp_err_t R_AGT_Disable (timer_ctrl_t * const p_ctrl)
 fsp_err_t R_AGT_PeriodSet (timer_ctrl_t * const p_ctrl, uint32_t const period_counts)
 {
     agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl;
-#if AGT_CFG_PARAM_CHECKING_ENABLE
- #if !BSP_FEATURE_AGT_HAS_AGTW
-
-    /* Validate period parameter. */
-    FSP_ASSERT(0U != period_counts);
-    FSP_ASSERT(period_counts <= AGT_MAX_PERIOD);
- #endif
-#endif
 
     fsp_err_t err = r_agt_common_preamble(p_instance_ctrl);
     FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
 
+#if AGT_CFG_PARAM_CHECKING_ENABLE
+    if (!AGT_PRV_IS_AGTW(p_instance_ctrl))
+    {
+        /* Validate period parameter. */
+        FSP_ASSERT(0U != period_counts);
+        FSP_ASSERT(period_counts <= AGT_MAX_PERIOD_16BIT);
+    }
+#endif
+
     /* Set period. */
     r_agt_period_register_set(p_instance_ctrl, period_counts);
 
@@ -431,13 +450,16 @@ fsp_err_t R_AGT_DutyCycleSet (timer_ctrl_t * const p_ctrl, uint32_t const duty_c
  #endif
 
     /* Set duty cycle. */
- #if BSP_FEATURE_AGT_HAS_AGTW
-    volatile uint32_t * const p_agtcm = &p_instance_ctrl->p_reg->AGTCMA;
-    p_agtcm[pin] = duty_cycle_counts;
- #else
-    volatile uint16_t * const p_agtcm = &p_instance_ctrl->p_reg->AGTCMA;
-    p_agtcm[pin] = (uint16_t) duty_cycle_counts;
- #endif
+    if (AGT_PRV_IS_AGTW(p_instance_ctrl))
+    {
+        volatile uint32_t * const p_agtcm = &p_instance_ctrl->p_reg->AGT32.AGTCMA;
+        p_agtcm[pin] = duty_cycle_counts;
+    }
+    else
+    {
+        volatile uint16_t * const p_agtcm = &p_instance_ctrl->p_reg->AGT16.AGTCMA;
+        p_agtcm[pin] = (uint16_t) duty_cycle_counts;
+    }
 
     return FSP_SUCCESS;
 #else
@@ -478,26 +500,23 @@ fsp_err_t R_AGT_InfoGet (timer_ctrl_t * const p_ctrl, timer_info_t * const p_inf
     {
         /* Clock frequency of this channel is the clock frequency divided by the timer period of the source channel. */
 
-#if BSP_FEATURE_AGT_HAS_AGTW
-        uint32_t source_channel_reg = (uint32_t) (p_instance_ctrl->p_reg) -
-                                      ((uint32_t) R_AGTW1 - (uint32_t) R_AGTW0);
-        R_AGTW0_Type * p_source_channel_reg = (R_AGTW0_Type *) source_channel_reg;
-#else
-        R_AGT0_Type * p_source_channel_reg = p_instance_ctrl->p_reg - (R_AGT1 - R_AGT0);
-#endif
+        /* Source instance is the channel immediately preceding this one. */
         if (0U == gp_prv_agt_periods[p_instance_ctrl->p_cfg->channel - 1])
         {
             p_info->clock_frequency = AGT_PRV_MIN_CLOCK_FREQ;
         }
         else
         {
-            p_info->clock_frequency = r_agt_clock_frequency_get(p_source_channel_reg) /
-                                      gp_prv_agt_periods[p_instance_ctrl->p_cfg->channel - 1];
+            R_AGTX0_Type * p_source_channel_reg = (R_AGTX0_Type *) ((uint32_t) p_instance_ctrl->p_reg -
+                                                                    ((uint32_t) R_AGTX1 - (uint32_t) R_AGTX0));
+            p_info->clock_frequency =
+                r_agt_clock_frequency_get(p_source_channel_reg, AGT_PRV_IS_AGTW(p_instance_ctrl)) /
+                gp_prv_agt_periods[p_instance_ctrl->p_cfg->channel - 1];
         }
     }
     else
     {
-        p_info->clock_frequency = r_agt_clock_frequency_get(p_instance_ctrl->p_reg);
+        p_info->clock_frequency = r_agt_clock_frequency_get(p_instance_ctrl->p_reg, AGT_PRV_IS_AGTW(p_instance_ctrl));
     }
 
     /* AGT supports only counting down direction */
@@ -527,11 +546,14 @@ fsp_err_t R_AGT_StatusGet (timer_ctrl_t * const p_ctrl, timer_status_t * const p
     fsp_err_t err = r_agt_common_preamble(p_instance_ctrl);
     FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
 
+    agt_prv_reg_ctrl_ptr_t p_reg_ctrl = AGT_PRV_CTRL_PTR(p_instance_ctrl);
+
     /* Read the state. */
-    p_status->state = (timer_state_t) p_instance_ctrl->p_reg->AGTCR_b.TCSTF;
+    p_status->state = (timer_state_t) p_reg_ctrl->AGTCR_b.TCSTF;
 
     /* Read counter value */
-    p_status->counter = p_instance_ctrl->p_reg->AGT;
+    p_status->counter =
+        AGT_PRV_IS_AGTW(p_instance_ctrl) ? p_instance_ctrl->p_reg->AGT32.AGT : p_instance_ctrl->p_reg->AGT16.AGT;
 
     return FSP_SUCCESS;
 }
@@ -603,13 +625,15 @@ fsp_err_t R_AGT_Close (timer_ctrl_t * const p_ctrl)
     fsp_err_t err = r_agt_common_preamble(p_instance_ctrl);
     FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
 
+    agt_prv_reg_ctrl_ptr_t p_reg_ctrl = AGT_PRV_CTRL_PTR(p_instance_ctrl);
+
     /* Cleanup the device: Stop counter, disable interrupts, and power down if no other channels are in use. */
 
     /* Stop timer */
-    p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_FORCE_STOP;
+    p_reg_ctrl->AGTCR = AGT_PRV_AGTCR_FORCE_STOP;
 
     /* Clear AGT output. */
-    p_instance_ctrl->p_reg->AGTIOC = 0U;
+    p_reg_ctrl->AGTIOC = 0U;
 
     if (FSP_INVALID_VECTOR != p_instance_ctrl->p_cfg->cycle_end_irq)
     {
@@ -634,7 +658,7 @@ fsp_err_t R_AGT_Close (timer_ctrl_t * const p_ctrl)
  * Parameter checking for R_AGT_Open.
  *
  * @param[in] p_instance_ctrl          Pointer to instance control structure.
- * @param[in]  p_cfg              Configuration structure for this instance
+ * @param[in] p_cfg                    Configuration structure for this instance
  *
  * @retval FSP_SUCCESS                 Initialization was successful and timer has started.
  * @retval FSP_ERR_ASSERTION           A required input pointer is NULL or the period is not in the valid range of
@@ -659,12 +683,13 @@ static fsp_err_t r_agt_open_param_checking (agt_instance_ctrl_t * p_instance_ctr
         FSP_ERROR_RETURN(p_cfg->cycle_end_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED);
     }
 
- #if !BSP_FEATURE_AGT_HAS_AGTW
-    FSP_ASSERT(0U != p_cfg->period_counts);
+    if (!AGT_PRV_IS_AGTW(p_instance_ctrl))
+    {
+        FSP_ASSERT(0U != p_cfg->period_counts);
 
-    /* Validate period parameter. */
-    FSP_ASSERT(p_cfg->period_counts <= AGT_MAX_PERIOD);
- #endif
+        /* Validate period parameter. */
+        FSP_ASSERT(p_cfg->period_counts <= AGT_MAX_PERIOD_16BIT);
+    }
 
     /* Validate channel number. */
     FSP_ERROR_RETURN(((1U << p_cfg->channel) & BSP_FEATURE_AGT_VALID_CHANNEL_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT);
@@ -673,11 +698,14 @@ static fsp_err_t r_agt_open_param_checking (agt_instance_ctrl_t * p_instance_ctr
     agt_extended_cfg_t const * p_extend = (agt_extended_cfg_t const *) p_cfg->p_extend;
     FSP_ASSERT((AGT_CLOCK_AGT_UNDERFLOW != p_extend->count_source) || (p_cfg->channel & 1U));
 
- #if BSP_FEATURE_AGT_HAS_AGTW
-
-    /* Return error for MCUs that do not support P402 and P403 as count sources*/
-    FSP_ASSERT(AGT_CLOCK_P402 != p_extend->count_source);
-    FSP_ASSERT(AGT_CLOCK_P403 != p_extend->count_source);
+    /* Devices with RTCCR.TCEN support P402/P403 as count sources. */
+ #if !BSP_FEATURE_RTC_HAS_TCEN
+    if (AGT_PRV_IS_AGTW(p_instance_ctrl))
+    {
+        /* Return error for MCUs that do not support P402 and P403 as count sources*/
+        FSP_ASSERT(AGT_CLOCK_P402 != p_extend->count_source);
+        FSP_ASSERT(AGT_CLOCK_P403 != p_extend->count_source);
+    }
  #endif
 
     /* Validate divider. */
@@ -719,10 +747,12 @@ static fsp_err_t r_agt_common_preamble (agt_instance_ctrl_t * p_instance_ctrl)
     FSP_ERROR_RETURN(AGT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
 #endif
 
+    agt_prv_reg_ctrl_ptr_t p_reg_ctrl = AGT_PRV_CTRL_PTR(p_instance_ctrl);
+
     /* Ensure timer state reflects expected status. Reference section 25.4.1 "Count Operation Start and Stop Control"
      * in the RA6M3 manual R01UH0886EJ0100. */
-    uint32_t agtcr_tstart = p_instance_ctrl->p_reg->AGTCR_b.TSTART;
-    FSP_HARDWARE_REGISTER_WAIT(agtcr_tstart, p_instance_ctrl->p_reg->AGTCR_b.TCSTF);
+    uint32_t agtcr_tstart = p_reg_ctrl->AGTCR_b.TSTART;
+    FSP_HARDWARE_REGISTER_WAIT(agtcr_tstart, p_reg_ctrl->AGTCR_b.TCSTF);
 
     return FSP_SUCCESS;
 }
@@ -738,14 +768,15 @@ static fsp_err_t r_agt_common_preamble (agt_instance_ctrl_t * p_instance_ctrl)
 static void r_agt_hardware_cfg (agt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg)
 {
     /* Update the divider for PCLKB. */
-    agt_extended_cfg_t const * p_extend = (agt_extended_cfg_t const *) p_cfg->p_extend;
-    uint32_t count_source_int           = (uint32_t) p_extend->count_source;
+    agt_prv_reg_ctrl_ptr_t     p_reg_ctrl = AGT_PRV_CTRL_PTR(p_instance_ctrl);
+    agt_extended_cfg_t const * p_extend   = (agt_extended_cfg_t const *) p_cfg->p_extend;
+    uint32_t count_source_int             = (uint32_t) p_extend->count_source;
     uint32_t agtmr2  = 0U;
     uint32_t agtcmsr = 0U;
     uint32_t tedgsel = 0U;
     uint32_t agtioc  = p_extend->agtio_filter;
 
-    uint32_t mode = p_extend->measurement_mode & AGT_IODEFINE(AGTMR1_TMOD_Msk);
+    uint32_t mode = p_extend->measurement_mode & R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk;
 
     uint32_t edge = 0U;
     if (AGT_CLOCK_PCLKB == p_extend->count_source)
@@ -754,7 +785,7 @@ static void r_agt_hardware_cfg (agt_instance_ctrl_t * const p_instance_ctrl, tim
         {
             /* Toggle the second bit if the count_source_int is not 0 to map PCLKB / 8 to 1 and PCLKB / 2 to 3. */
             count_source_int   = p_cfg->source_div ^ 2U;
-            count_source_int <<= AGT_IODEFINE(AGTMR1_TCK_Pos);
+            count_source_int <<= R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos;
         }
     }
 
@@ -765,10 +796,17 @@ static void r_agt_hardware_cfg (agt_instance_ctrl_t * const p_instance_ctrl, tim
         mode             = AGT_PRV_AGTMR1_TMOD_EVENT_COUNTER;
         count_source_int = 0U;
 
-        edge   |= (p_extend->trigger_edge & AGT_IODEFINE(AGTMR1_TEDGPL_Msk));
-        agtioc |= (p_extend->enable_pin & AGT_IODEFINE(AGTIOC_TIOGT_Msk));
-        p_instance_ctrl->p_reg->AGTISR   = (p_extend->enable_pin & AGT_IODEFINE(AGTISR_EEPS_Msk));
-        p_instance_ctrl->p_reg->AGTIOSEL = (uint8_t) (p_extend->count_source & (uint8_t) ~AGT_CLOCK_AGTIO);
+        edge              |= (p_extend->trigger_edge & R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk);
+        agtioc            |= (p_extend->enable_pin & R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk);
+        p_reg_ctrl->AGTISR = (p_extend->enable_pin & R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk);
+        if (BSP_FEATURE_AGT_USE_AGTIOSEL_ALT)
+        {
+            p_reg_ctrl->AGTIOSEL_ALT = (uint8_t) (p_extend->count_source & (uint8_t) ~AGT_CLOCK_AGTIO);
+        }
+        else
+        {
+            p_reg_ctrl->AGTIOSEL = (uint8_t) (p_extend->count_source & (uint8_t) ~AGT_CLOCK_AGTIO);
+        }
     }
 #endif
     else if (AGT_CLOCK_AGT_UNDERFLOW != p_extend->count_source)
@@ -783,16 +821,6 @@ static void r_agt_hardware_cfg (agt_instance_ctrl_t * const p_instance_ctrl, tim
 
     uint32_t agtmr1 = (count_source_int | edge) | mode;
 
-#if BSP_FEATURE_RTC_HAS_ROPSEL
-    if (AGT_CLOCK_SUBCLOCK == p_extend->count_source)
-    {
-        /* Clear the RCR4_b.ROPSEL bit if AGT uses Sub-clock. This is necessary as ROPSEL bit is undefined after
-         * MCU Reset and if it is set to 1, the Sub-clock output to AGT stops in Software Standby mode. */
-        R_RTC->RCR4_b.ROPSEL = 0U;
-        FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR4_b.ROPSEL, 0U);
-    }
-#endif
-
     /* Configure output settings. */
 
 #if AGT_CFG_OUTPUT_SUPPORT_ENABLE
@@ -817,25 +845,28 @@ static void r_agt_hardware_cfg (agt_instance_ctrl_t * const p_instance_ctrl, tim
             agtcmb = inverted_duty_cycle;
         }
 
- #if BSP_FEATURE_AGT_HAS_AGTW
-        p_instance_ctrl->p_reg->AGTCMA = agtcma;
-        p_instance_ctrl->p_reg->AGTCMB = agtcmb;
- #else
-        p_instance_ctrl->p_reg->AGTCMA = (uint16_t) agtcma;
-        p_instance_ctrl->p_reg->AGTCMB = (uint16_t) agtcmb;
- #endif
+        if (AGT_PRV_IS_AGTW(p_instance_ctrl))
+        {
+            p_instance_ctrl->p_reg->AGT32.AGTCMA = agtcma;
+            p_instance_ctrl->p_reg->AGT32.AGTCMB = agtcmb;
+        }
+        else
+        {
+            p_instance_ctrl->p_reg->AGT16.AGTCMA = (uint16_t) agtcma;
+            p_instance_ctrl->p_reg->AGT16.AGTCMB = (uint16_t) agtcmb;
+        }
     }
 
     /* Configure TEDGSEL bit based on user input. */
     if (AGT_PIN_CFG_DISABLED != p_extend->agto)
     {
         /* Set the TOE bit if AGTO is enabled.  AGTO can be enabled in any mode. */
-        agtioc |= (1U << AGT_IODEFINE(AGTIOC_TOE_Pos));
+        agtioc |= (1U << R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos);
 
         if (AGT_PIN_CFG_START_LEVEL_LOW == p_extend->agto)
         {
             /* Configure the start level of AGTO. */
-            tedgsel |= (1U << AGT_IODEFINE(AGTIOC_TEDGSEL_Pos));
+            tedgsel |= (1U << R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos);
         }
     }
 #endif
@@ -854,17 +885,17 @@ static void r_agt_hardware_cfg (agt_instance_ctrl_t * const p_instance_ctrl, tim
         else
         {
             /* Use the trigger edge for pulse period or event counting modes. */
-            tedgsel = (p_extend->trigger_edge & AGT_IODEFINE(AGTIOC_TEDGSEL_Msk));
+            tedgsel = (p_extend->trigger_edge & R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk);
         }
     }
 #endif
 
     agtioc |= tedgsel;
 
-    p_instance_ctrl->p_reg->AGTIOC  = (uint8_t) agtioc;
-    p_instance_ctrl->p_reg->AGTCMSR = (uint8_t) agtcmsr;
-    p_instance_ctrl->p_reg->AGTMR1  = (uint8_t) agtmr1;
-    p_instance_ctrl->p_reg->AGTMR2  = (uint8_t) agtmr2;
+    p_reg_ctrl->AGTIOC  = (uint8_t) agtioc;
+    p_reg_ctrl->AGTCMSR = (uint8_t) agtcmsr;
+    p_reg_ctrl->AGTMR1  = (uint8_t) agtmr1;
+    p_reg_ctrl->AGTMR2  = (uint8_t) agtmr2;
 }
 
 /*******************************************************************************************************************//**
@@ -878,25 +909,14 @@ static void r_agt_period_register_set (agt_instance_ctrl_t * p_instance_ctrl, ui
     /* Store the period value so it can be retrieved later. */
     p_instance_ctrl->period = period_counts;
     gp_prv_agt_periods[p_instance_ctrl->p_cfg->channel] = period_counts;
-#if BSP_FEATURE_AGT_HAS_AGTW
+
     uint32_t period_reg = (period_counts - 1U);
-#else
-    uint16_t period_reg = (uint16_t) (period_counts - 1U);
-#endif
 
 #if AGT_CFG_OUTPUT_SUPPORT_ENABLE
- #if BSP_FEATURE_AGT_HAS_AGTW
     uint32_t duty_cycle_counts = 0U;
- #else
-    uint16_t duty_cycle_counts = 0U;
- #endif
     if (TIMER_MODE_PERIODIC == p_instance_ctrl->p_cfg->mode)
     {
- #if BSP_FEATURE_AGT_HAS_AGTW
         duty_cycle_counts = (period_counts >> 1);
- #else
-        duty_cycle_counts = (uint16_t) (period_counts >> 1);
- #endif
     }
     else if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode)
     {
@@ -909,30 +929,44 @@ static void r_agt_period_register_set (agt_instance_ctrl_t * p_instance_ctrl, ui
 
     if (TIMER_MODE_PWM != p_instance_ctrl->p_cfg->mode)
     {
-        p_instance_ctrl->p_reg->AGTCMA = duty_cycle_counts;
-        p_instance_ctrl->p_reg->AGTCMB = duty_cycle_counts;
+        if (AGT_PRV_IS_AGTW(p_instance_ctrl))
+        {
+            p_instance_ctrl->p_reg->AGT32.AGTCMA = duty_cycle_counts;
+            p_instance_ctrl->p_reg->AGT32.AGTCMB = duty_cycle_counts;
+        }
+        else
+        {
+            p_instance_ctrl->p_reg->AGT16.AGTCMA = (uint16_t) duty_cycle_counts;
+            p_instance_ctrl->p_reg->AGT16.AGTCMB = (uint16_t) duty_cycle_counts;
+        }
     }
 #endif
 
     /* Set counter to period minus one. */
-    p_instance_ctrl->p_reg->AGT = period_reg;
+    if (AGT_PRV_IS_AGTW(p_instance_ctrl))
+    {
+        p_instance_ctrl->p_reg->AGT32.AGT = period_reg;
+    }
+    else
+    {
+        p_instance_ctrl->p_reg->AGT16.AGT = (uint16_t) period_reg;
+    }
 }
 
 /*******************************************************************************************************************//**
  * Obtains the clock frequency of AGT for all clock sources except AGT0 underflow, with divisor applied.
  *
  * @param[in]  p_agt_regs         Registers of AGT channel used
+ * @param[in]  is_agtw            Specifies this AGT channel is using the AGTW peripheral.
  *
  * @return Source clock frequency of AGT in Hz, divider applied.
  **********************************************************************************************************************/
-#if BSP_FEATURE_AGT_HAS_AGTW
-static uint32_t r_agt_clock_frequency_get (R_AGTW0_Type * p_agt_regs)
-#else
-static uint32_t r_agt_clock_frequency_get (R_AGT0_Type * p_agt_regs)
-#endif
+static uint32_t r_agt_clock_frequency_get (R_AGTX0_Type * p_agt_regs, bool is_agtw)
 {
+    agt_prv_reg_ctrl_ptr_t p_agt_regs_ctrl = is_agtw ? &p_agt_regs->AGT32.CTRL : &p_agt_regs->AGT16.CTRL;
+
     uint32_t           clock_freq_hz    = 0U;
-    uint8_t            count_source_int = p_agt_regs->AGTMR1_b.TCK;
+    uint8_t            count_source_int = p_agt_regs_ctrl->AGTMR1_b.TCK;
     timer_source_div_t divider          = TIMER_SOURCE_DIV_1;
     if (0U == (count_source_int & (~AGT_SOURCE_CLOCK_PCLKB_BITS)))
     {
@@ -954,7 +988,7 @@ static uint32_t r_agt_clock_frequency_get (R_AGT0_Type * p_agt_regs)
          * support AGT0 underflow as count source.  */
         clock_freq_hz = FSUB_FREQUENCY_HZ;
 
-        divider = (timer_source_div_t) p_agt_regs->AGTMR2_b.CKS;
+        divider = (timer_source_div_t) p_agt_regs_ctrl->AGTMR2_b.CKS;
     }
 
     clock_freq_hz >>= divider;
@@ -976,10 +1010,11 @@ void agt_int_isr (void)
     R_BSP_IrqStatusClear(irq);
 
     /* Recover ISR context saved in open. */
-    agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+    agt_instance_ctrl_t  * p_instance_ctrl = (agt_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+    agt_prv_reg_ctrl_ptr_t p_reg_ctrl      = AGT_PRV_CTRL_PTR(p_instance_ctrl);
 
     /* Save AGTCR to determine the source of the interrupt. */
-    uint32_t agtcr = p_instance_ctrl->p_reg->AGTCR;
+    uint32_t agtcr = p_reg_ctrl->AGTCR;
 
     /* If the channel is configured to be one-shot mode, stop the timer. */
     if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode)
@@ -988,18 +1023,18 @@ void agt_int_isr (void)
 
         /* Forcibly stopping the timer resets AGTCMSR, AGTCMA, and AGTCMB. AGTCMA and AGTCMB are based on the
          * timer period, but AGTCMSR must be saved so it can be restored. */
-        uint8_t agtcmsr = p_instance_ctrl->p_reg->AGTCMSR;
+        uint8_t agtcmsr = p_reg_ctrl->AGTCMSR;
 #endif
 
         /* Stop timer. This resets the timer period (AGT register). The AGT register is reconfigured in R_AGT_Start(). */
-        p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_FORCE_STOP;
-        agtcr &= AGT_PRV_AGTCR_STATUS_FLAGS;
-        p_instance_ctrl->p_reg->AGTCR = (uint8_t) agtcr;
+        p_reg_ctrl->AGTCR = AGT_PRV_AGTCR_FORCE_STOP;
+        agtcr            &= AGT_PRV_AGTCR_STATUS_FLAGS;
+        p_reg_ctrl->AGTCR = (uint8_t) agtcr;
 
 #if AGT_CFG_OUTPUT_SUPPORT_ENABLE
 
         /* Restore AGTCMSR. */
-        p_instance_ctrl->p_reg->AGTCMSR = agtcmsr;
+        p_reg_ctrl->AGTCMSR = agtcmsr;
 #endif
     }
 
@@ -1023,7 +1058,7 @@ void agt_int_isr (void)
             callback_args = *p_args;
         }
 
-        if (agtcr & AGT_IODEFINE(AGTCR_TUNDF_Msk))
+        if (agtcr & R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk)
         {
             p_args->event = TIMER_EVENT_CYCLE_END;
         }
@@ -1033,18 +1068,28 @@ void agt_int_isr (void)
         {
             p_args->event = TIMER_EVENT_CAPTURE_A;
             uint32_t reload_value = p_instance_ctrl->period - 1U;
-            p_args->capture = reload_value - p_instance_ctrl->p_reg->AGT;
+            if (AGT_PRV_IS_AGTW(p_instance_ctrl))
+            {
+                p_args->capture = reload_value - p_instance_ctrl->p_reg->AGT32.AGT;
+            }
+            else
+            {
+                p_args->capture = reload_value - p_instance_ctrl->p_reg->AGT16.AGT;
+            }
 
             /* The AGT counter is not reset in pulse width measurement mode. Reset it by software. Note that this
              * will restart the counter if a new capture has already started. Application writers must ensure that
              * this interrupt processing completes before the next capture begins. */
-            if (AGT_PRV_AGTMR1_TMOD_PULSE_WIDTH == p_instance_ctrl->p_reg->AGTMR1_b.TMOD)
+            if (AGT_PRV_AGTMR1_TMOD_PULSE_WIDTH == p_reg_ctrl->AGTMR1_b.TMOD)
             {
- #if BSP_FEATURE_AGT_HAS_AGTW
-                p_instance_ctrl->p_reg->AGT = reload_value;
- #else
-                p_instance_ctrl->p_reg->AGT = (uint16_t) reload_value;
- #endif
+                if (AGT_PRV_IS_AGTW(p_instance_ctrl))
+                {
+                    p_instance_ctrl->p_reg->AGT32.AGT = reload_value;
+                }
+                else
+                {
+                    p_instance_ctrl->p_reg->AGT16.AGT = (uint16_t) reload_value;
+                }
             }
             else
             {
@@ -1085,11 +1130,11 @@ void agt_int_isr (void)
         }
 
         /* Retreive AGTCR in case it was modified in the callback. */
-        agtcr = p_instance_ctrl->p_reg->AGTCR;
+        agtcr = p_reg_ctrl->AGTCR;
     }
 
     /* Clear flags in AGTCR. */
-    p_instance_ctrl->p_reg->AGTCR = (uint8_t) (agtcr & ~AGT_PRV_AGTCR_STATUS_FLAGS);
+    p_reg_ctrl->AGTCR = (uint8_t) (agtcr & ~AGT_PRV_AGTCR_STATUS_FLAGS);
 
     /* Restore context if RTOS is used */
     FSP_CONTEXT_RESTORE
diff --git a/ra/fsp/src/r_ble/r_ble.c b/ra/fsp/src/r_ble/r_ble.c
index d57f725b6..2072c6915 100644
--- a/ra/fsp/src/r_ble/r_ble.c
+++ b/ra/fsp/src/r_ble/r_ble.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_cac/r_cac.c b/ra/fsp/src/r_cac/r_cac.c
index b305df2c2..ae0044bf5 100644
--- a/ra/fsp/src/r_cac/r_cac.c
+++ b/ra/fsp/src/r_cac/r_cac.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_can/r_can.c b/ra/fsp/src/r_can/r_can.c
index afdd28350..395d8d809 100644
--- a/ra/fsp/src/r_can/r_can.c
+++ b/ra/fsp/src/r_can/r_can.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_canfd/.util/Renesas##HAL Drivers##all##r_canfd####4.2.0.xml.j2 b/ra/fsp/src/r_canfd/.util/Renesas##HAL Drivers##all##r_canfd####4.3.0.xml.j2
similarity index 100%
rename from ra/fsp/src/r_canfd/.util/Renesas##HAL Drivers##all##r_canfd####4.2.0.xml.j2
rename to ra/fsp/src/r_canfd/.util/Renesas##HAL Drivers##all##r_canfd####4.3.0.xml.j2
diff --git a/ra/fsp/src/r_canfd/r_canfd.c b/ra/fsp/src/r_canfd/r_canfd.c
index 7ae155e27..a64f20356 100644
--- a/ra/fsp/src/r_canfd/r_canfd.c
+++ b/ra/fsp/src/r_canfd/r_canfd.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_cec/r_cec.c b/ra/fsp/src/r_cec/r_cec.c
index d62cbc0f6..51892b50d 100644
--- a/ra/fsp/src/r_cec/r_cec.c
+++ b/ra/fsp/src/r_cec/r_cec.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_cgc/r_cgc.c b/ra/fsp/src/r_cgc/r_cgc.c
index 8850e0528..1e41713d2 100644
--- a/ra/fsp/src/r_cgc/r_cgc.c
+++ b/ra/fsp/src/r_cgc/r_cgc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_crc/r_crc.c b/ra/fsp/src/r_crc/r_crc.c
index 579be7597..cff89038d 100644
--- a/ra/fsp/src/r_crc/r_crc.c
+++ b/ra/fsp/src/r_crc/r_crc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -29,9 +29,16 @@
  **********************************************************************************************************************/
 
 /* "CRC" in ASCII, used to determine if channel is open. */
-#define CRC_OPEN                   (0x00435243ULL)
+#define CRC_OPEN                        (0x00435243ULL)
 
-#define CRC_CRCCR1_CRCSWR_SHIFT    (5)
+#define CRC_CRCCR1_CRCSWR_SHIFT         (5)
+
+/* Snoop address
+ * TDR and RDR depends on MCU.
+ * FTDRL is always 0x**F while FRDRL is always 0x**1.
+ */
+#define CRC_SNOOP_ADDRESS_TYPE_MASK     (0x0FU)
+#define CRC_SNOOP_ADDRESS_TYPE_FTDRL    (0x0FU)
 
 /***********************************************************************************************************************
  * Typedef definitions
@@ -117,8 +124,11 @@ fsp_err_t R_CRC_Open (crc_ctrl_t * const p_ctrl, crc_cfg_t const * const p_cfg)
 
     R_CRC->CRCCR0 = crccr0;
 
+#if BSP_FEATURE_CRC_HAS_SNOOP
+
     /* Disable snooping */
     R_CRC->CRCCR1 = 0;
+#endif
 
     return FSP_SUCCESS;
 }
@@ -217,37 +227,53 @@ fsp_err_t R_CRC_CalculatedValueGet (crc_ctrl_t * const p_ctrl, uint32_t * calcul
  * For example, if set to channel 0, transmit, every byte written out SCI channel 0 is also
  * sent to the CRC calculator as if the value was explicitly written directly to the CRC calculator.
  *
- * @retval FSP_SUCCESS             Snoop configured successfully.
- * @retval FSP_ERR_ASSERTION       Pointer to control stucture is NULL
- * @retval FSP_ERR_NOT_OPEN        The driver is not opened.
+ * @retval FSP_SUCCESS                  Snoop configured successfully.
+ * @retval FSP_ERR_ASSERTION            Pointer to control stucture is NULL
+ * @retval FSP_ERR_NOT_OPEN             The driver is not opened.
+ * @retval FSP_ERR_UNSUPPORTED          SNOOP operation is not supported.
+ * @retval FSP_ERR_INVALID_ARGUMENT     SNOOP address is invalid.
  *
  **********************************************************************************************************************/
 fsp_err_t R_CRC_SnoopEnable (crc_ctrl_t * const p_ctrl, uint32_t crc_seed)
 {
+#if BSP_FEATURE_CRC_HAS_SNOOP
     crc_instance_ctrl_t * p_instance_ctrl = (crc_instance_ctrl_t *) p_ctrl;
 
-#if CRC_CFG_PARAM_CHECKING_ENABLE
+ #if CRC_CFG_PARAM_CHECKING_ENABLE
     FSP_ASSERT(p_ctrl);
     FSP_ERROR_RETURN(CRC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
-    uint8_t crccr1 = 0;
-    uint8_t crcsar = 0;
+    FSP_ERROR_RETURN(p_instance_ctrl->p_cfg->snoop_address >= 0, FSP_ERR_INVALID_ARGUMENT);
+ #endif
 
-    /* Set CRC snoop direction */
-    crccr1 = (uint8_t) ((p_instance_ctrl->p_cfg->snoop_address & 2) << CRC_CRCCR1_CRCSWR_SHIFT);
+    crc_seed_value_update(p_instance_ctrl, crc_seed);
 
     /* Set CRC snoop address */
-    crcsar = (uint8_t) (p_instance_ctrl->p_cfg->snoop_address & R_CRC_CRCSAR_CRCSA_Msk);
-
-    R_CRC->CRCSAR = crcsar;
-
-    crc_seed_value_update(p_instance_ctrl, crc_seed);
+    R_CRC->CRCSAR =
+        (uint16_t) (((uint32_t) p_instance_ctrl->p_cfg->snoop_address & R_CRC_CRCSAR_CRCSA_Msk) <<
+                    R_CRC_CRCSAR_CRCSA_Pos);
+
+    /*
+     * Enable snoop operation and set direction:
+     */
+    uint8_t addr = (uint8_t) p_instance_ctrl->p_cfg->snoop_address & CRC_SNOOP_ADDRESS_TYPE_MASK;
+    if ((BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR == addr) || (CRC_SNOOP_ADDRESS_TYPE_FTDRL == addr))
+    {
+        R_CRC->CRCCR1 = (uint8_t) ((1UL << R_CRC_CRCCR1_CRCSEN_Pos) | (1UL << R_CRC_CRCCR1_CRCSWR_Pos));
+    }
+    else
+    {
+        R_CRC->CRCCR1 = (uint8_t) (1 << R_CRC_CRCCR1_CRCSEN_Pos);
+    }
 
-    /* Enable the snoop operation */
-    crccr1       |= (1 << R_CRC_CRCCR1_CRCSEN_Pos);
-    R_CRC->CRCCR1 = crccr1;
+    FSP_REGISTER_READ(R_CRC->CRCCR1_b.CRCSWR);
 
     return FSP_SUCCESS;
+#else
+    FSP_PARAMETER_NOT_USED(crc_seed);
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+
+    return FSP_ERR_UNSUPPORTED;
+#endif
 }
 
 /*******************************************************************************************************************//**
@@ -258,21 +284,28 @@ fsp_err_t R_CRC_SnoopEnable (crc_ctrl_t * const p_ctrl, uint32_t crc_seed)
  * @retval FSP_SUCCESS             Snoop disabled.
  * @retval FSP_ERR_ASSERTION       p_ctrl is NULL.
  * @retval FSP_ERR_NOT_OPEN        The driver is not opened.
+ * @retval FSP_ERR_UNSUPPORTED     SNOOP operation is not supported.
  *
  **********************************************************************************************************************/
 fsp_err_t R_CRC_SnoopDisable (crc_ctrl_t * const p_ctrl)
 {
-#if CRC_CFG_PARAM_CHECKING_ENABLE
+#if BSP_FEATURE_CRC_HAS_SNOOP
+ #if CRC_CFG_PARAM_CHECKING_ENABLE
     crc_instance_ctrl_t * p_instance_ctrl = (crc_instance_ctrl_t *) p_ctrl;
     FSP_ASSERT(p_ctrl);
     FSP_ERROR_RETURN(CRC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
+ #endif
     FSP_PARAMETER_NOT_USED(p_ctrl);
 
     /* Clear CRCSEN to disable snoop operation */
     R_CRC->CRCCR1 = 0;
 
     return FSP_SUCCESS;
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+
+    return FSP_ERR_UNSUPPORTED;
+#endif
 }
 
 /** @} (end addtogroup CRC) */
diff --git a/ra/fsp/src/r_ctsu/r_ctsu.c b/ra/fsp/src/r_ctsu/r_ctsu.c
index c3fe74bbc..fc1c90c4d 100644
--- a/ra/fsp/src/r_ctsu/r_ctsu.c
+++ b/ra/fsp/src/r_ctsu/r_ctsu.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -57,6 +57,9 @@
 #define CTSU_TUNING_VALUE_SELF               (15360)
 #define CTSU_TUNING_VALUE_MUTUAL             (10240)
 
+#define CTSU_CFG_DECIMAL_POINT               (16)
+#define CTSU_CFG_DECIMAL_POINT_MASK          (0x0000FFFF)
+
 #if (BSP_FEATURE_CTSU_VERSION == 2)
  #define CTSU_SST_RECOMMEND                  (0x1F) // The recommend value of SST
  #define CTSU_SST_RECOMMEND_CURRENT          (0x3F) // The recommend value of SST with current
@@ -291,7 +294,7 @@ static void ctsu_transer_count_element(uint32_t element_mask, uint16_t * num_ele
  #endif
 #endif
 static void ctsu_initial_offset_tuning(ctsu_instance_ctrl_t * const p_instance_ctrl);
-static void ctsu_moving_average(uint16_t * p_average, uint16_t new_data, uint16_t average_num);
+static void ctsu_moving_average(ctsu_data_t * p_average, uint16_t new_data, uint16_t average_num);
 void        ctsu_write_isr(void);
 void        ctsu_read_isr(void);
 void        ctsu_end_isr(void);
@@ -408,15 +411,15 @@ static ctsu_ctsuwr_t g_ctsu_ctsuwr[(CTSU_CFG_NUM_SELF_ELEMENTS + CTSU_CFG_NUM_MU
 static uint16_t        g_ctsu_self_element_index = 0;
 static ctsu_self_buf_t g_ctsu_self_raw[CTSU_CFG_NUM_SELF_ELEMENTS * CTSU_CFG_NUM_SUMULTI];
 static uint16_t        g_ctsu_self_corr[CTSU_CFG_NUM_SELF_ELEMENTS * CTSU_CFG_NUM_SUMULTI];
-static uint16_t        g_ctsu_self_data[CTSU_CFG_NUM_SELF_ELEMENTS];
+static ctsu_data_t     g_ctsu_self_data[CTSU_CFG_NUM_SELF_ELEMENTS];
 #endif
 #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0)
 static uint16_t          g_ctsu_mutual_element_index = 0;
 static ctsu_mutual_buf_t g_ctsu_mutual_raw[CTSU_CFG_NUM_MUTUAL_ELEMENTS * CTSU_MUTUAL_BUF_SIZE];
 static uint16_t          g_ctsu_mutual_pri_corr[CTSU_CFG_NUM_MUTUAL_ELEMENTS * CTSU_CFG_NUM_SUMULTI];
 static uint16_t          g_ctsu_mutual_snd_corr[CTSU_CFG_NUM_MUTUAL_ELEMENTS * CTSU_CFG_NUM_SUMULTI];
-static uint16_t          g_ctsu_mutual_pri_data[CTSU_CFG_NUM_MUTUAL_ELEMENTS];
-static uint16_t          g_ctsu_mutual_snd_data[CTSU_CFG_NUM_MUTUAL_ELEMENTS];
+static ctsu_data_t       g_ctsu_mutual_pri_data[CTSU_CFG_NUM_MUTUAL_ELEMENTS];
+static ctsu_data_t       g_ctsu_mutual_snd_data[CTSU_CFG_NUM_MUTUAL_ELEMENTS];
 #endif
 static ctsu_correction_info_t g_ctsu_correction_info;
 
@@ -1343,7 +1346,7 @@ fsp_err_t R_CTSU_DataGet (ctsu_ctrl_t * const p_ctrl, uint16_t * p_data)
     {
         for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++)
         {
-            *p_data = *(p_instance_ctrl->p_self_data + element_id);
+            *p_data = (p_instance_ctrl->p_self_data + element_id)->int_data;
             p_data++;
         }
     }
@@ -1353,9 +1356,9 @@ fsp_err_t R_CTSU_DataGet (ctsu_ctrl_t * const p_ctrl, uint16_t * p_data)
     {
         for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++)
         {
-            *p_data = *(p_instance_ctrl->p_mutual_pri_data + element_id);
+            *p_data = (p_instance_ctrl->p_mutual_pri_data + element_id)->int_data;
             p_data++;
-            *p_data = *(p_instance_ctrl->p_mutual_snd_data + element_id);
+            *p_data = (p_instance_ctrl->p_mutual_snd_data + element_id)->int_data;
             p_data++;
         }
     }
@@ -1795,7 +1798,7 @@ fsp_err_t R_CTSU_DataInsert (ctsu_ctrl_t * const p_ctrl, uint16_t * p_insert_dat
         /* Data output */
         for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++)
         {
-            *(p_instance_ctrl->p_self_data + element_id) = *p_insert_data;
+            (p_instance_ctrl->p_self_data + element_id)->int_data = *p_insert_data;
             p_insert_data++;
         }
     }
@@ -1805,9 +1808,9 @@ fsp_err_t R_CTSU_DataInsert (ctsu_ctrl_t * const p_ctrl, uint16_t * p_insert_dat
     {
         for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++)
         {
-            *(p_instance_ctrl->p_mutual_pri_data + element_id) = *p_insert_data;
+            (p_instance_ctrl->p_mutual_pri_data + element_id)->int_data = *p_insert_data;
             p_insert_data++;
-            *(p_instance_ctrl->p_mutual_snd_data + element_id) = *p_insert_data;
+            (p_instance_ctrl->p_mutual_snd_data + element_id)->int_data = *p_insert_data;
             p_insert_data++;
         }
     }
@@ -2263,13 +2266,13 @@ void ctsu_initial_offset_tuning (ctsu_instance_ctrl_t * const p_instance_ctrl)
  #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0)
             if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->md)
             {
-                diff = *(p_instance_ctrl->p_self_data + element_id) - target_val;
+                diff = (p_instance_ctrl->p_self_data + element_id)->int_data - target_val;
             }
  #endif
  #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0)
             if (CTSU_MODE_MUTUAL_FULL_SCAN == p_instance_ctrl->md)
             {
-                diff = *(p_instance_ctrl->p_mutual_pri_data + element_id) - target_val;
+                diff = (p_instance_ctrl->p_mutual_pri_data + element_id)->int_data - target_val;
             }
  #endif
             ctsuso = (p_instance_ctrl->p_ctsuwr[element_id].ctsuso0 & CTSU_TUNING_MAX);
@@ -2419,13 +2422,16 @@ void ctsu_initial_offset_tuning (ctsu_instance_ctrl_t * const p_instance_ctrl)
 /***********************************************************************************************************************
  * ctsu_moving_average
  ***********************************************************************************************************************/
-void ctsu_moving_average (uint16_t * p_average, uint16_t new_data, uint16_t average_num)
+void ctsu_moving_average (ctsu_data_t * p_average, uint16_t new_data, uint16_t average_num)
 {
     uint32_t work;
 
-    work       = (uint32_t) ((uint32_t) *p_average * (uint32_t) (average_num - 1)); /* Average * (num - 1) */
-    work      += new_data;                                                          /* Add Now data        */
-    *p_average = (uint16_t) (work / average_num);                                   /* Average calculation */
+    work  = (uint32_t) (((uint32_t) p_average->int_data << CTSU_CFG_DECIMAL_POINT) + p_average->decimal_point_data);
+    work -= (uint32_t) (work / average_num);
+    work += (uint32_t) (((uint32_t) new_data << CTSU_CFG_DECIMAL_POINT) / average_num);
+
+    p_average->int_data           = (uint16_t) (work >> CTSU_CFG_DECIMAL_POINT);
+    p_average->decimal_point_data = (uint16_t) (work & CTSU_CFG_DECIMAL_POINT_MASK);
 }
 
 /***********************************************************************************************************************
@@ -3276,20 +3282,21 @@ fsp_err_t ctsu_correction_data_get (ctsu_instance_ctrl_t * const p_instance_ctrl
   #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1)
     adc_instance_t const * p_adc = p_instance_ctrl->p_ctsu_cfg->p_adc_instance;
   #endif
-    uint32_t  i;
-    uint32_t  j;
-    uint16_t  base_value;
-    uint16_t  base_conv_dac;
-    int32_t   x0;
-    int32_t   x1;
-    int32_t   y0;
-    fsp_err_t err = FSP_SUCCESS;
+    uint32_t    i;
+    uint32_t    j;
+    uint16_t    base_value;
+    uint16_t    base_conv_dac;
+    int32_t     x0;
+    int32_t     x1;
+    int32_t     y0;
+    ctsu_data_t temp_avg_data = {0, 0};
+    fsp_err_t   err           = FSP_SUCCESS;
 
     if (g_ctsu_correction_info.scan_index < CTSU_CORRECTION_POINT_NUM)
     {
-        ctsu_moving_average(&g_ctsu_correction_info.dac_value[g_ctsu_correction_info.scan_index],
-                            *p_instance_ctrl->p_self_raw,
-                            4);
+        temp_avg_data.int_data = g_ctsu_correction_info.dac_value[g_ctsu_correction_info.scan_index];
+        ctsu_moving_average(&temp_avg_data, *p_instance_ctrl->p_self_raw, 4);
+        g_ctsu_correction_info.dac_value[g_ctsu_correction_info.scan_index] = temp_avg_data.int_data;
         g_ctsu_correction_info.scan_index++;
     }
     else
@@ -3301,7 +3308,9 @@ fsp_err_t ctsu_correction_data_get (ctsu_instance_ctrl_t * const p_instance_ctrl
         }
         else
         {
-            ctsu_moving_average(&g_ctsu_correction_info.ex_base_value, *p_instance_ctrl->p_self_raw, 4);
+            temp_avg_data.int_data = g_ctsu_correction_info.ex_base_value;
+            ctsu_moving_average(&temp_avg_data, *p_instance_ctrl->p_self_raw, 4);
+            g_ctsu_correction_info.ex_base_value = temp_avg_data.int_data;
         }
 
         g_ctsu_correction_info.scan_index = 0;
@@ -3513,10 +3522,10 @@ void ctsu_correction_calc (uint16_t * correction_data, uint16_t raw_data, ctsu_c
     uint16_t coefficient;
 #endif
 #if (BSP_FEATURE_CTSU_VERSION == 2)
-    int32_t  y0 = 0;
-    int32_t  y1 = 0;
-    int32_t  x0 = 0;
-    int32_t  x1 = 0;
+    int64_t  y0 = 0;
+    int64_t  y1 = 0;
+    int64_t  x0 = 0;
+    int64_t  x1 = 0;
     uint16_t i;
 #endif
 
@@ -3643,13 +3652,14 @@ void ctsu_correction_calc (uint16_t * correction_data, uint16_t raw_data, ctsu_c
             }
         }
  #endif
-
-        answer = (uint32_t) (y0 - (((y0 - y1) * (x0 - cmp_data)) / (x0 - x1)));
-
         if (CTSU_SNUM_RECOMMEND != p_calc->snum)
         {
-            answer = (uint32_t) ((answer * (uint32_t) (p_calc->snum + 1)) / (CTSU_SNUM_RECOMMEND + 1));
+            x0 = (int64_t) ((x0 * (p_calc->snum + 1)) / (CTSU_SNUM_RECOMMEND + 1));
+            y0 = (int64_t) ((y0 * (p_calc->snum + 1)) / (CTSU_SNUM_RECOMMEND + 1));
+            x1 = (int64_t) ((x1 * (p_calc->snum + 1)) / (CTSU_SNUM_RECOMMEND + 1));
+            y1 = (int64_t) ((y1 * (p_calc->snum + 1)) / (CTSU_SNUM_RECOMMEND + 1));
         }
+        answer = (uint32_t) (y0 - (((y0 - y1) * (x0 - raw_data)) / (x0 - x1)));
 #endif
 
         /* Value Overflow Check */
@@ -3678,14 +3688,14 @@ void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl)
     ctsu_correction_calc_t calc;
 #if (BSP_FEATURE_CTSU_VERSION == 1)
  #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0)
-    uint16_t * p_self_data;
-    uint16_t   average_self;
+    ctsu_data_t * p_self_data;
+    ctsu_data_t   average_self = {0, 0};
  #endif
  #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0)
-    uint16_t * p_pri_data;
-    uint16_t * p_snd_data;
-    uint16_t   average_pri;
-    uint16_t   average_snd;
+    ctsu_data_t * p_pri_data;
+    ctsu_data_t * p_snd_data;
+    ctsu_data_t   average_pri = {0, 0};
+    ctsu_data_t   average_snd = {0, 0};
  #endif
 
     for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++)
@@ -3700,10 +3710,10 @@ void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl)
             ctsu_correction_calc((p_instance_ctrl->p_self_corr + element_id),
                                  (p_instance_ctrl->p_self_raw + element_id)->sen,
                                  &calc);
-            *p_self_data = *(p_instance_ctrl->p_self_corr + element_id);
+            p_self_data->int_data = *(p_instance_ctrl->p_self_corr + element_id);
             if (1 < p_instance_ctrl->average)
             {
-                ctsu_moving_average(&average_self, *p_self_data, p_instance_ctrl->average);
+                ctsu_moving_average(&average_self, p_self_data->int_data, p_instance_ctrl->average);
                 *p_self_data = average_self;
             }
         }
@@ -3719,13 +3729,13 @@ void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl)
                                  (p_instance_ctrl->p_mutual_raw + element_id)->pri_sen, &calc);
             ctsu_correction_calc((p_instance_ctrl->p_mutual_snd_corr + element_id),
                                  (p_instance_ctrl->p_mutual_raw + element_id)->snd_sen, &calc);
-            *p_pri_data = *(p_instance_ctrl->p_mutual_pri_corr + element_id);
-            *p_snd_data = *(p_instance_ctrl->p_mutual_snd_corr + element_id);
+            p_pri_data->int_data = *(p_instance_ctrl->p_mutual_pri_corr + element_id);
+            p_snd_data->int_data = *(p_instance_ctrl->p_mutual_snd_corr + element_id);
 
             if (1 < p_instance_ctrl->average)
             {
-                ctsu_moving_average(&average_pri, *p_pri_data, p_instance_ctrl->average);
-                ctsu_moving_average(&average_snd, *p_snd_data, p_instance_ctrl->average);
+                ctsu_moving_average(&average_pri, p_pri_data->int_data, p_instance_ctrl->average);
+                ctsu_moving_average(&average_snd, p_snd_data->int_data, p_instance_ctrl->average);
                 *p_pri_data = average_pri;
                 *p_snd_data = average_snd;
             }
@@ -3741,14 +3751,14 @@ void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl)
     int32_t                 offset_unit;
     ctsu_correction_multi_t multi;
  #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0)
-    uint16_t * p_self_data;
-    uint16_t   average_self;
+    ctsu_data_t * p_self_data;
+    ctsu_data_t   average_self = {0, 0};
  #endif
  #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0)
-    uint16_t * p_pri_data;
-    uint16_t * p_snd_data;
-    uint16_t   average_pri;
-    uint16_t   average_snd;
+    ctsu_data_t * p_pri_data;
+    ctsu_data_t * p_snd_data;
+    ctsu_data_t   average_pri = {0, 0};
+    ctsu_data_t   average_snd = {0, 0};
 
   #if (CTSU_CFG_NUM_CFC != 0)
     uint8_t  ts_id;
@@ -3820,16 +3830,17 @@ void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl)
             else
             {
                 /* Store last moving averaged data */
-                average_self = *p_self_data;
+                average_self.int_data           = p_self_data->int_data;
+                average_self.decimal_point_data = p_self_data->decimal_point_data;
 
                 /* Matching values */
                 ctsu_correction_fleq(&multi, multi.pri, NULL);
-                ctsu_correction_multi(&multi, p_self_data, NULL);
+                ctsu_correction_multi(&multi, &(p_self_data->int_data), NULL);
 
                 *(p_instance_ctrl->p_selected_freq_self + element_id) = multi.selected_freq;
 
                 /* Update moving averaged data */
-                ctsu_moving_average(&average_self, *p_self_data, p_instance_ctrl->average);
+                ctsu_moving_average(&average_self, p_self_data->int_data, p_instance_ctrl->average);
                 *p_self_data = average_self;
             }
         }
@@ -3841,12 +3852,12 @@ void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl)
             average_self = *p_self_data;
 
             /* Correction */
-            ctsu_correction_calc(p_self_data, p_instance_ctrl->p_self_raw[element_id], &calc);
+            ctsu_correction_calc(&(p_self_data->int_data), p_instance_ctrl->p_self_raw[element_id], &calc);
 
             /* Update moving averaged data */
             if (1 < p_instance_ctrl->average)
             {
-                ctsu_moving_average(&average_self, *p_self_data, p_instance_ctrl->average);
+                ctsu_moving_average(&average_self, p_self_data->int_data, p_instance_ctrl->average);
                 *p_self_data = average_self;
             }
  #endif
@@ -3884,13 +3895,13 @@ void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl)
 
                 /* Matching values */
                 ctsu_correction_fleq(&multi, multi.pri, multi.snd);
-                ctsu_correction_multi(&multi, p_pri_data, p_snd_data);
+                ctsu_correction_multi(&multi, &(p_pri_data->int_data), &(p_snd_data->int_data));
                 *(p_instance_ctrl->p_selected_freq_mutual + element_id) = multi.selected_freq;
 
                 /* Update moving averaged data */
-                ctsu_moving_average(&average_pri, *p_pri_data, p_instance_ctrl->average);
+                ctsu_moving_average(&average_pri, p_pri_data->int_data, p_instance_ctrl->average);
                 *p_pri_data = average_pri;
-                ctsu_moving_average(&average_snd, *p_snd_data, p_instance_ctrl->average);
+                ctsu_moving_average(&average_snd, p_snd_data->int_data, p_instance_ctrl->average);
                 *p_snd_data = average_snd;
             }
  #endif
@@ -3941,7 +3952,7 @@ void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl)
                 /* Store corrected data in p_pri_data[i] for initial offset tuning */
                 for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++)
                 {
-                    p_pri_data[i] = multi.pri[i];
+                    p_pri_data[i].int_data = multi.pri[i];
                 }
             }
             else
@@ -3952,13 +3963,13 @@ void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl)
 
                 /* Matching values */
                 ctsu_correction_fleq(&multi, multi.pri, multi.snd);
-                ctsu_correction_multi(&multi, p_pri_data, p_snd_data);
+                ctsu_correction_multi(&multi, &(p_pri_data->int_data), &(p_snd_data->int_data));
                 *(p_instance_ctrl->p_selected_freq_mutual + element_id) = multi.selected_freq;
 
                 /* Update moving averaged data */
-                ctsu_moving_average(&average_pri, *p_pri_data, p_instance_ctrl->average);
+                ctsu_moving_average(&average_pri, p_pri_data->int_data, p_instance_ctrl->average);
                 *p_pri_data = average_pri;
-                ctsu_moving_average(&average_snd, *p_snd_data, p_instance_ctrl->average);
+                ctsu_moving_average(&average_snd, p_snd_data->int_data, p_instance_ctrl->average);
                 *p_snd_data = average_snd;
             }
   #endif
diff --git a/ra/fsp/src/r_dac/r_dac.c b/ra/fsp/src/r_dac/r_dac.c
index 7545779a2..a9cecc88b 100644
--- a/ra/fsp/src/r_dac/r_dac.c
+++ b/ra/fsp/src/r_dac/r_dac.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_dac8/r_dac8.c b/ra/fsp/src/r_dac8/r_dac8.c
index 0d020a5e8..20fa49ca2 100644
--- a/ra/fsp/src/r_dac8/r_dac8.c
+++ b/ra/fsp/src/r_dac8/r_dac8.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_dmac/r_dmac.c b/ra/fsp/src/r_dmac/r_dmac.c
index 4eef3ca8d..acc20777b 100644
--- a/ra/fsp/src/r_dmac/r_dmac.c
+++ b/ra/fsp/src/r_dmac/r_dmac.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_doc/r_doc.c b/ra/fsp/src/r_doc/r_doc.c
index bf52a2aaf..0ebae5c81 100644
--- a/ra/fsp/src/r_doc/r_doc.c
+++ b/ra/fsp/src/r_doc/r_doc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_drw/r_drw_base.c b/ra/fsp/src/r_drw/r_drw_base.c
index a65d67b14..41a3a1fef 100644
--- a/ra/fsp/src/r_drw/r_drw_base.c
+++ b/ra/fsp/src/r_drw/r_drw_base.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_drw/r_drw_base.h b/ra/fsp/src/r_drw/r_drw_base.h
index 5e87b356a..961eef482 100644
--- a/ra/fsp/src/r_drw/r_drw_base.h
+++ b/ra/fsp/src/r_drw/r_drw_base.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_drw/r_drw_irq.c b/ra/fsp/src/r_drw/r_drw_irq.c
index d20df3c7a..4176bddf4 100644
--- a/ra/fsp/src/r_drw/r_drw_irq.c
+++ b/ra/fsp/src/r_drw/r_drw_irq.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_drw/r_drw_memory.c b/ra/fsp/src/r_drw/r_drw_memory.c
index c0dc5eac7..d51b372dc 100644
--- a/ra/fsp/src/r_drw/r_drw_memory.c
+++ b/ra/fsp/src/r_drw/r_drw_memory.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_dtc/r_dtc.c b/ra/fsp/src/r_dtc/r_dtc.c
index 8aa67632a..128fd0298 100644
--- a/ra/fsp/src/r_dtc/r_dtc.c
+++ b/ra/fsp/src/r_dtc/r_dtc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_elc/r_elc.c b/ra/fsp/src/r_elc/r_elc.c
index e4a24fd72..66ab61012 100644
--- a/ra/fsp/src/r_elc/r_elc.c
+++ b/ra/fsp/src/r_elc/r_elc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_ether/r_ether.c b/ra/fsp/src/r_ether/r_ether.c
index 7ec909f0a..9bc25af5b 100644
--- a/ra/fsp/src/r_ether/r_ether.c
+++ b/ra/fsp/src/r_ether/r_ether.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_ether_phy/r_ether_phy.c b/ra/fsp/src/r_ether_phy/r_ether_phy.c
index 42db1e5d4..bc0faae44 100644
--- a/ra/fsp/src/r_ether_phy/r_ether_phy.c
+++ b/ra/fsp/src/r_ether_phy/r_ether_phy.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_ether_phy/targets/DP83620/r_ether_phy_target_dp83620.c b/ra/fsp/src/r_ether_phy/targets/DP83620/r_ether_phy_target_dp83620.c
index 7a45d9b8d..f33eb1e98 100644
--- a/ra/fsp/src/r_ether_phy/targets/DP83620/r_ether_phy_target_dp83620.c
+++ b/ra/fsp/src/r_ether_phy/targets/DP83620/r_ether_phy_target_dp83620.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_ether_phy/targets/ICS1894/r_ether_phy_target_ics1894.c b/ra/fsp/src/r_ether_phy/targets/ICS1894/r_ether_phy_target_ics1894.c
index 8b581a47b..61526f20c 100644
--- a/ra/fsp/src/r_ether_phy/targets/ICS1894/r_ether_phy_target_ics1894.c
+++ b/ra/fsp/src/r_ether_phy/targets/ICS1894/r_ether_phy_target_ics1894.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_ether_phy/targets/KSZ8041/r_ether_phy_target_ksz8041.c b/ra/fsp/src/r_ether_phy/targets/KSZ8041/r_ether_phy_target_ksz8041.c
index 4f0b5bbcf..00cec5572 100644
--- a/ra/fsp/src/r_ether_phy/targets/KSZ8041/r_ether_phy_target_ksz8041.c
+++ b/ra/fsp/src/r_ether_phy/targets/KSZ8041/r_ether_phy_target_ksz8041.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_ether_phy/targets/KSZ8091RNB/r_ether_phy_target_ksz8091rnb.c b/ra/fsp/src/r_ether_phy/targets/KSZ8091RNB/r_ether_phy_target_ksz8091rnb.c
index 3c0afd5e6..d387a2fc1 100644
--- a/ra/fsp/src/r_ether_phy/targets/KSZ8091RNB/r_ether_phy_target_ksz8091rnb.c
+++ b/ra/fsp/src/r_ether_phy/targets/KSZ8091RNB/r_ether_phy_target_ksz8091rnb.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_flash_hp/r_flash_hp.c b/ra/fsp/src/r_flash_hp/r_flash_hp.c
index 27cab2bf5..b3c96ea37 100644
--- a/ra/fsp/src/r_flash_hp/r_flash_hp.c
+++ b/ra/fsp/src/r_flash_hp/r_flash_hp.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -99,19 +99,19 @@ typedef BSP_CMSE_NONSECURE_CALL void (*volatile flash_hp_prv_ns_callback)(flash_
 #define FLASH_HP_FACI_CMD_LOCK_BIT_READ               (0x71U)
 #define FLASH_HP_FACI_CMD_FINAL                       (0xD0U)
 
-/**  Configuration set Command offset*/
-#define FLASH_HP_FCU_CONFIG_SET_ID_BYTE               (0x0000A150U)
 #if (BSP_CFG_MCU_PART_SERIES == 8)
  #define FLASH_HP_FCU_CONFIG_SET_DUAL_MODE            (0x0300A110U)
  #define FLASH_HP_FCU_CONFIG_SET_ACCESS_STARTUP       (0x0300A130U)
  #define FLASH_HP_FCU_CONFIG_SET_BANK_MODE            (0x1300A190U)
-#elif !(defined(BSP_MCU_GROUP_RA6M4) || defined(BSP_MCU_GROUP_RA4M3) || defined(BSP_MCU_GROUP_RA4M2) || \
-    defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA4E1) || defined(BSP_MCU_GROUP_RA6E1) ||     \
-    defined(BSP_MCU_GROUP_RA6T2))
- #define FLASH_HP_FCU_CONFIG_SET_ACCESS_STARTUP       (0x0000A160U)
 #else
+ #if BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW
+  #define FLASH_HP_FCU_CONFIG_SET_ACCESS_STARTUP      (0x0000A160U)
+  #define FLASH_HP_FCU_CONFIG_SET_ID_BYTE             (0x0000A150U)
+ #else
+  #define FLASH_HP_FCU_CONFIG_SET_ACCESS_STARTUP      (0x0100A130U)
+  #define FLASH_HP_FCU_CONFIG_SET_ID_BYTE             (0x0000A120U)
+ #endif
  #define FLASH_HP_FCU_CONFIG_SET_DUAL_MODE            (0x0100A110U)
- #define FLASH_HP_FCU_CONFIG_SET_ACCESS_STARTUP       (0x0100A130U)
  #define FLASH_HP_FCU_CONFIG_SET_BANK_MODE            (0x0100A190U)
 #endif
 
@@ -320,10 +320,13 @@ static fsp_err_t flash_hp_set_startup_area_boot(flash_hp_instance_ctrl_t * p_ctr
                                                 flash_startup_area_swap_t  swap_type,
                                                 bool                       is_temporary) PLACE_IN_RAM_SECTION;
 
+ #if (BSP_FEATURE_FLASH_SUPPORTS_ID_CODE == 1)
 static fsp_err_t flash_hp_set_id_code(flash_hp_instance_ctrl_t * p_ctrl,
                                       uint8_t const * const      p_id_code,
                                       flash_id_code_mode_t       mode) PLACE_IN_RAM_SECTION;
 
+ #endif
+
 #endif
 
 #if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE == 1)
@@ -2284,7 +2287,7 @@ static fsp_err_t flash_hp_set_startup_area_boot (flash_hp_instance_ctrl_t * p_ct
 
 #endif
 
-#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_SUPPORTS_ID_CODE == 1)
 
 /*******************************************************************************************************************//**
  * Set the ID code.
diff --git a/ra/fsp/src/r_flash_lp/r_flash_lp.c b/ra/fsp/src/r_flash_lp/r_flash_lp.c
index 78be83d88..62da8c8bc 100644
--- a/ra/fsp/src/r_flash_lp/r_flash_lp.c
+++ b/ra/fsp/src/r_flash_lp/r_flash_lp.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_glcdc/r_glcdc.c b/ra/fsp/src/r_glcdc/r_glcdc.c
index 69050f712..570ee662b 100644
--- a/ra/fsp/src/r_glcdc/r_glcdc.c
+++ b/ra/fsp/src/r_glcdc/r_glcdc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_gpt/r_gpt.c b/ra/fsp/src/r_gpt/r_gpt.c
index 825441a7e..f22ebe03a 100644
--- a/ra/fsp/src/r_gpt/r_gpt.c
+++ b/ra/fsp/src/r_gpt/r_gpt.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_gpt_three_phase/r_gpt_three_phase.c b/ra/fsp/src/r_gpt_three_phase/r_gpt_three_phase.c
index e92c86781..4786ddeed 100644
--- a/ra/fsp/src/r_gpt_three_phase/r_gpt_three_phase.c
+++ b/ra/fsp/src/r_gpt_three_phase/r_gpt_three_phase.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_i3c/r_i3c.c b/ra/fsp/src/r_i3c/r_i3c.c
index ea62ff0da..67d6af7d0 100644
--- a/ra/fsp/src/r_i3c/r_i3c.c
+++ b/ra/fsp/src/r_i3c/r_i3c.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -55,91 +55,95 @@ typedef enum e_i3c_slave_error_recovery_type
 /***********************************************************************************************************************
  * Macro definitions
  **********************************************************************************************************************/
-#define I3C_OPEN                                   (('I' << 16U) | ('3' << 8U) | ('C' << 0U))
+#define I3C_OPEN                                     (('I' << 16U) | ('3' << 8U) | ('C' << 0U))
 
 /* Bitfield definitions for Command Descriptor fields. */
-#define I3C_CMD_DESC_CMD_ATTR_Pos                  (0U)
-#define I3C_CMD_DESC_CMD_ATTR_Msk                  (7U << I3C_CMD_DESC_CMD_ATTR_Pos)
-#define I3C_CMD_DESC_CND_ATTR_XFER                 (0U)
-#define I3C_CMD_DESC_CMD_ATTR_ADDR_ASSGN_CMD       (2U)
-#define I3C_CMD_DESC_TID_Pos                       (3U)
-#define I3C_CMD_DESC_TID_Msk                       (0x0FU << I3C_CMD_DESC_TID_Pos)
-#define I3C_CMD_DESC_CMD_Pos                       (7U)
-#define I3C_CMD_DESC_CMD_Msk                       (0xFFU << I3C_CMD_DESC_CMD_Pos)
-#define I3C_CMD_DESC_DEV_INDEX_Pos                 (16U)
-#define I3C_CMD_DESC_DEV_INDEX_Msk                 (0x01FFU << I3C_CMD_DESC_DEV_INDEX_Pos)
-#define I3C_CMD_DESC_ROC_Pos                       (30U)
-#define I3C_CMD_DESC_ROC_Msk                       (1U << I3C_CMD_DESC_ROC_Pos)
-#define I3C_CMD_DESC_TOC_Pos                       (31U)
-#define I3C_CMD_DESC_TOC_Msk                       (1U << I3C_CMD_DESC_TOC_Pos)
+#define I3C_CMD_DESC_CMD_ATTR_Pos                    (0U)
+#define I3C_CMD_DESC_CMD_ATTR_Msk                    (7U << I3C_CMD_DESC_CMD_ATTR_Pos)
+#define I3C_CMD_DESC_CND_ATTR_XFER                   (0U)
+#define I3C_CMD_DESC_CND_ATTR_IMMED_DATA_XFER        (1U)
+#define I3C_CMD_DESC_CMD_ATTR_ADDR_ASSGN_CMD         (2U)
+#define I3C_CMD_DESC_TID_Pos                         (3U)
+#define I3C_CMD_DESC_TID_Msk                         (0x0FU << I3C_CMD_DESC_TID_Pos)
+#define I3C_CMD_DESC_CMD_Pos                         (7U)
+#define I3C_CMD_DESC_CMD_Msk                         (0xFFU << I3C_CMD_DESC_CMD_Pos)
+#define I3C_CMD_DESC_DEV_INDEX_Pos                   (16U)
+#define I3C_CMD_DESC_DEV_INDEX_Msk                   (0x01FFU << I3C_CMD_DESC_DEV_INDEX_Pos)
+#define I3C_CMD_DESC_ROC_Pos                         (30U)
+#define I3C_CMD_DESC_ROC_Msk                         (1U << I3C_CMD_DESC_ROC_Pos)
+#define I3C_CMD_DESC_TOC_Pos                         (31U)
+#define I3C_CMD_DESC_TOC_Msk                         (1U << I3C_CMD_DESC_TOC_Pos)
 
 /* Command Descriptor definitions for Address Assign Commands. */
-#define I3C_CMD_DESC_ADDR_ASSGN_DEV_COUNT_Pos      (26U)
-#define I3C_CMD_DESC_ADDR_ASSGN_DEV_COUNT_Msk      (0x0FU << I3C_CMD_DESC_ADDR_ASSGN_DEV_COUNT_Pos)
-
-/* Command Descriptor definitions for Regular transfer Commands. */
-#define I3C_CMD_DESC_XFER_CP_Pos                   (15U)
-#define I3C_CMD_DESC_XFER_CP_Msk                   (1U << I3C_CMD_DESC_XFER_CP_Pos)
-#define I3C_CMD_DESC_XFER_HJ_Pos                   (15U)
-#define I3C_CMD_DESC_XFER_HJ_Msk                   (1U << I3C_CMD_DESC_XFER_HJ_Pos)
-#define I3C_CMD_DESC_XFER_LENGTH_Pos               (16U)
-#define I3C_CMD_DESC_XFER_LENGTH_Msk               (0xFFFFU << I3C_CMD_DESC_XFER_LENGTH_Pos)
-#define I3C_CMD_DESC_XFER_MODE_Pos                 (26U)
-#define I3C_CMD_DESC_XFER_MODE_Msk                 (0x07U << I3C_CMD_DESC_XFER_MODE_Pos)
-#define I3C_CMD_DESC_XFER_RNW_Pos                  (29U)
-#define I3C_CMD_DESC_XFER_RNW_Msk                  (1U << I3C_CMD_DESC_XFER_RNW_Pos)
-#define I3C_CMD_DESC_XFER_MODE_I2C_STDBR           (0U)
-#define I3C_CMD_DESC_XFER_MODE_I2C_EXDBR           (1U)
-#define I3C_CMD_DESC_XFER_MODE_I3C_SDR_EXTBR_X2    (3U)
-#define I3C_CMD_DESC_XFER_MODE_I3C_SDR_EXTBR_X4    (4U)
+#define I3C_CMD_DESC_ADDR_ASSGN_DEV_COUNT_Pos        (26U)
+#define I3C_CMD_DESC_ADDR_ASSGN_DEV_COUNT_Msk        (0x0FU << I3C_CMD_DESC_ADDR_ASSGN_DEV_COUNT_Pos)
+
+/* Command Descriptor definitions for Regular Transfer Commands. */
+#define I3C_CMD_DESC_XFER_CP_Pos                     (15U)
+#define I3C_CMD_DESC_XFER_CP_Msk                     (1U << I3C_CMD_DESC_XFER_CP_Pos)
+#define I3C_CMD_DESC_XFER_HJ_Pos                     (15U)
+#define I3C_CMD_DESC_XFER_HJ_Msk                     (1U << I3C_CMD_DESC_XFER_HJ_Pos)
+#define I3C_CMD_DESC_XFER_LENGTH_Pos                 (16U)
+#define I3C_CMD_DESC_XFER_LENGTH_Msk                 (0xFFFFU << I3C_CMD_DESC_XFER_LENGTH_Pos)
+#define I3C_CMD_DESC_XFER_MODE_Pos                   (26U)
+#define I3C_CMD_DESC_XFER_MODE_Msk                   (0x07U << I3C_CMD_DESC_XFER_MODE_Pos)
+#define I3C_CMD_DESC_XFER_RNW_Pos                    (29U)
+#define I3C_CMD_DESC_XFER_RNW_Msk                    (1U << I3C_CMD_DESC_XFER_RNW_Pos)
+#define I3C_CMD_DESC_XFER_MODE_I2C_STDBR             (0U)
+#define I3C_CMD_DESC_XFER_MODE_I2C_EXDBR             (1U)
+#define I3C_CMD_DESC_XFER_MODE_I3C_SDR_EXTBR_X2      (3U)
+#define I3C_CMD_DESC_XFER_MODE_I3C_SDR_EXTBR_X4      (4U)
+
+/* Command Descriptor definitions for Immediate Data Transfer Commands. */
+#define I3C_CMD_DESC_IMMED_DATA_XFER_BYTE_CNT_Pos    (23U)
 
 /* Bitfield definitions for the Response Status Descriptor fields. */
-#define I3C_RESP_STATUS_DESC_DATA_LENGTH_Pos       (0U)
-#define I3C_RESP_STATUS_DESC_DATA_LENGTH_Msk       (0xFFFFU << I3C_RESP_STATUS_DESC_DATA_LENGTH_Pos)
-#define I3C_RESP_STATUS_DESC_TID_Pos               (24U)
-#define I3C_RESP_STATUS_DESC_TID_Msk               (0x0FU << I3C_RESP_STATUS_DESC_TID_Pos)
-#define I3C_RESP_STATUS_DESC_ERR_STATUS_Pos        (28U)
-#define I3C_RESP_STATUS_DESC_ERR_STATUS_Msk        (0x0FU << I3C_RESP_STATUS_DESC_ERR_STATUS_Pos)
+#define I3C_RESP_STATUS_DESC_DATA_LENGTH_Pos         (0U)
+#define I3C_RESP_STATUS_DESC_DATA_LENGTH_Msk         (0xFFFFU << I3C_RESP_STATUS_DESC_DATA_LENGTH_Pos)
+#define I3C_RESP_STATUS_DESC_TID_Pos                 (24U)
+#define I3C_RESP_STATUS_DESC_TID_Msk                 (0x0FU << I3C_RESP_STATUS_DESC_TID_Pos)
+#define I3C_RESP_STATUS_DESC_ERR_STATUS_Pos          (28U)
+#define I3C_RESP_STATUS_DESC_ERR_STATUS_Msk          (0x0FU << I3C_RESP_STATUS_DESC_ERR_STATUS_Pos)
 
 /* Bitfield definitions for Receive Status Descriptor fields. */
-#define I3C_RECV_STATUS_DESC_DATA_LENGTH_Pos       (0U)
-#define I3C_RECV_STATUS_DESC_DATA_LENGTH_Msk       (0xFFFFU << I3C_RECV_STATUS_DESC_DATA_LENGTH_Pos)
-#define I3C_RECV_STATUS_DESC_CMD_Pos               (16U)
-#define I3C_RECV_STATUS_DESC_CMD_Msk               (0xFFU << I3C_RECV_STATUS_DESC_CMD_Pos)
-#define I3C_RECV_STATUS_DESC_SDR_R_W_TYPE_Pos      (23U)
-#define I3C_RECV_STATUS_DESC_SDR_R_W_TYPE_Msk      (0x01U << I3C_RECV_STATUS_DESC_SDR_R_W_TYPE_Pos)
-#define I3C_RECV_STATUS_DESC_ERR_STATUS_Pos        (24U)
-#define I3C_RECV_STATUS_DESC_ERR_STATUS_Msk        (0x07U << I3C_RECV_STATUS_DESC_ERR_STATUS_Pos)
-#define I3C_RECV_STATUS_DESC_TRANSFER_TYPE_Pos     (27U)
-#define I3C_RECV_STATUS_DESC_TRANSFER_TYPE_Msk     (0x03U << I3C_RECV_STATUS_DESC_TRANSFER_TYPE_Pos)
-#define I3C_RECV_STATUS_DESC_DEV_INDEX_Pos         (29U)
-#define I3C_RECV_STATUS_DESC_DEV_INDEX_Msk         (0x07U << I3C_RECV_STATUS_DESC_DEV_INDEX_Pos)
+#define I3C_RECV_STATUS_DESC_DATA_LENGTH_Pos         (0U)
+#define I3C_RECV_STATUS_DESC_DATA_LENGTH_Msk         (0xFFFFU << I3C_RECV_STATUS_DESC_DATA_LENGTH_Pos)
+#define I3C_RECV_STATUS_DESC_CMD_Pos                 (16U)
+#define I3C_RECV_STATUS_DESC_CMD_Msk                 (0xFFU << I3C_RECV_STATUS_DESC_CMD_Pos)
+#define I3C_RECV_STATUS_DESC_SDR_R_W_TYPE_Pos        (23U)
+#define I3C_RECV_STATUS_DESC_SDR_R_W_TYPE_Msk        (0x01U << I3C_RECV_STATUS_DESC_SDR_R_W_TYPE_Pos)
+#define I3C_RECV_STATUS_DESC_ERR_STATUS_Pos          (24U)
+#define I3C_RECV_STATUS_DESC_ERR_STATUS_Msk          (0x07U << I3C_RECV_STATUS_DESC_ERR_STATUS_Pos)
+#define I3C_RECV_STATUS_DESC_TRANSFER_TYPE_Pos       (27U)
+#define I3C_RECV_STATUS_DESC_TRANSFER_TYPE_Msk       (0x03U << I3C_RECV_STATUS_DESC_TRANSFER_TYPE_Pos)
+#define I3C_RECV_STATUS_DESC_DEV_INDEX_Pos           (29U)
+#define I3C_RECV_STATUS_DESC_DEV_INDEX_Msk           (0x07U << I3C_RECV_STATUS_DESC_DEV_INDEX_Pos)
 
 /* Bitfield definitions for IBI Status Descriptor fields. */
-#define I3C_IBI_STATUS_DESC_LENGTH_Pos             (0U)
-#define I3C_IBI_STATUS_DESC_LENGTH_Msk             (0xFFU << I3C_IBI_STATUS_DESC_LENGTH_Pos)
-#define I3C_IBI_STATUS_DESC_IBI_ID_Pos             (8U)
-#define I3C_IBI_STATUS_DESC_IBI_ID_Msk             (0xFFU << I3C_IBI_STATUS_DESC_IBI_ID_Pos)
-#define I3C_IBI_STATUS_DESC_LAST_STATUS_Pos        (24U)
-#define I3C_IBI_STATUS_DESC_LAST_STATUS_Msk        (1U << I3C_IBI_STATUS_DESC_LAST_STATUS_Pos)
-#define I3C_IBI_STATUS_DESC_TS_Pos                 (25U)
-#define I3C_IBI_STATUS_DESC_TS_Msk                 (1U << I3C_IBI_STATUS_DESC_TS_Pos)
-#define I3C_IBI_STATUS_DESC_ERR_STATUS_Pos         (26U)
-#define I3C_IBI_STATUS_DESC_ERR_STATUS_Msk         (0x7U << I3C_IBI_STATUS_DESC_ERR_STATUS_Pos)
-#define I3C_IBI_STATUS_DESC_IBI_ST_Pos             (31U)
-#define I3C_IBI_STATUS_DESC_IBI_ST_Msk             (1U << I3C_IBI_STATUS_DESC_IBI_ST_Pos)
+#define I3C_IBI_STATUS_DESC_LENGTH_Pos               (0U)
+#define I3C_IBI_STATUS_DESC_LENGTH_Msk               (0xFFU << I3C_IBI_STATUS_DESC_LENGTH_Pos)
+#define I3C_IBI_STATUS_DESC_IBI_ID_Pos               (8U)
+#define I3C_IBI_STATUS_DESC_IBI_ID_Msk               (0xFFU << I3C_IBI_STATUS_DESC_IBI_ID_Pos)
+#define I3C_IBI_STATUS_DESC_LAST_STATUS_Pos          (24U)
+#define I3C_IBI_STATUS_DESC_LAST_STATUS_Msk          (1U << I3C_IBI_STATUS_DESC_LAST_STATUS_Pos)
+#define I3C_IBI_STATUS_DESC_TS_Pos                   (25U)
+#define I3C_IBI_STATUS_DESC_TS_Msk                   (1U << I3C_IBI_STATUS_DESC_TS_Pos)
+#define I3C_IBI_STATUS_DESC_ERR_STATUS_Pos           (26U)
+#define I3C_IBI_STATUS_DESC_ERR_STATUS_Msk           (0x7U << I3C_IBI_STATUS_DESC_ERR_STATUS_Pos)
+#define I3C_IBI_STATUS_DESC_IBI_ST_Pos               (31U)
+#define I3C_IBI_STATUS_DESC_IBI_ST_Msk               (1U << I3C_IBI_STATUS_DESC_IBI_ST_Pos)
 
 /* Address that is written by the slave during a Hot Join request. */
-#define I3C_HOT_JOIN_ADDRESS                       (2U)
+#define I3C_HOT_JOIN_ADDRESS                         (2U)
 
 /* Mask for flushing the Read, Write, and Command FIFO. */
-#define I3C_RSTCTRL_FIFO_FLUSH_Msk                 (R_I3C0_RSTCTL_CMDQRST_Msk | R_I3C0_RSTCTL_TDBRST_Msk | \
-                                                    R_I3C0_RSTCTL_RDBRST_Msk)
+#define I3C_RSTCTRL_FIFO_FLUSH_Msk                   (R_I3C0_RSTCTL_CMDQRST_Msk | R_I3C0_RSTCTL_TDBRST_Msk | \
+                                                      R_I3C0_RSTCTL_RDBRST_Msk)
 
-#define I3C_MAX_PUSH_PULL_PERIOD                   (0x3FU)
+#define I3C_MAX_PUSH_PULL_PERIOD                     (0x3FU)
 
 /* Mask for converting the internal state into an I3C event. */
-#define I3C_INTERNAL_EVENT_MASK                    (0x7FU)
+#define I3C_INTERNAL_EVENT_MASK                      (0x7FU)
 
 /***********************************************************************************************************************
  * Function Prototypes
@@ -250,7 +254,7 @@ fsp_err_t R_I3C_Open (i3c_ctrl_t * const p_api_ctrl, i3c_cfg_t const * const p_c
     p_ctrl->p_cfg = p_cfg;
 
     /* Clear the I3C Module Stop bit. */
-    R_BSP_MODULE_START(FSP_IP_IIC, p_cfg->channel);
+    R_BSP_MODULE_START(FSP_IP_I3C, p_cfg->channel);
 
     /* Get a pointer to the I3C registers for this channel. */
 #if BSP_FEATURE_I3C_NUM_CHANNELS > 1
@@ -259,6 +263,10 @@ fsp_err_t R_I3C_Open (i3c_ctrl_t * const p_api_ctrl, i3c_cfg_t const * const p_c
     p_ctrl->p_reg = R_I3C0;
 #endif
 
+#if BSP_FEATURE_BSP_HAS_I3C_CLOCK
+    p_ctrl->p_reg->CECTL = 1;
+#endif
+
     /*
      * Reset the I3C Peripheral so that it is in a known state during initialization (See Figure 25.102 I3C Communication Flow
      * in the RA2E2 manual R01UH0919EJ0100).
@@ -295,13 +303,6 @@ fsp_err_t R_I3C_Enable (i3c_ctrl_t * const p_api_ctrl)
 
     i3c_extended_cfg_t const * p_extend = (i3c_extended_cfg_t const *) p_ctrl->p_cfg->p_extend;
 
-#if I3C_CFG_MASTER_SUPPORT
-
-    /* Write the standard and extended bitrate settings. */
-    p_ctrl->p_reg->STDBR = p_extend->bitrate_settings.stdbr;
-    p_ctrl->p_reg->EXTBR = p_extend->bitrate_settings.extbr;
-#endif
-
     /*
      * Write all remaining configuration settings (See Figure 25.102 I3C Communication Flow in the RA2E2
      * manual R01UH0919EJ0100).
@@ -327,6 +328,10 @@ fsp_err_t R_I3C_Enable (i3c_ctrl_t * const p_api_ctrl)
 
         /* Enable the Queue Empty/Full Interrupt. */
         ntie |= R_I3C0_NTIE_IBIQEFIE_Msk;
+
+        /* Write the standard and extended bitrate settings. */
+        p_ctrl->p_reg->STDBR = p_extend->bitrate_settings.stdbr;
+        p_ctrl->p_reg->EXTBR = p_extend->bitrate_settings.extbr;
     }
     else
 #endif
@@ -339,6 +344,10 @@ fsp_err_t R_I3C_Enable (i3c_ctrl_t * const p_api_ctrl)
          * IBI transmit FIFO.
          */
         nqthctl |= 1U << R_I3C0_NQTHCTL_IBIQTH_Pos;
+
+        /* Baudrate registers are not used in slave mode. */
+        p_ctrl->p_reg->STDBR = 0;
+        p_ctrl->p_reg->EXTBR = 0;
 #endif
     }
 
@@ -541,6 +550,9 @@ fsp_err_t R_I3C_DeviceCfgSet (i3c_ctrl_t * const p_api_ctrl, i3c_device_cfg_t co
         sdatbas0 |= (uint32_t) (p_device_cfg->slave_info.bcr_b.ibi_payload << R_I3C0_SDATBAS0_SDIBIPL_Pos) &
                     R_I3C0_SDATBAS0_SDIBIPL_Msk;
 
+        /* Set the slave address to valid. */
+        p_ctrl->p_reg->SVCTL_b.SVAEn = 1;
+
         /* Write settings to the Slave Device Address Table Register. */
         p_ctrl->p_reg->SDATBAS0 = sdatbas0;
 
@@ -556,9 +568,6 @@ fsp_err_t R_I3C_DeviceCfgSet (i3c_ctrl_t * const p_api_ctrl, i3c_device_cfg_t co
                                               (pid[1] << 16U) |
                                               (pid[2] << 8U) |
                                               (pid[3] << 0U));
-
-        /* Set the slave address to valid. */
-        p_ctrl->p_reg->SVCTL_b.SVAEn = 1;
 #endif
     }
 
@@ -889,29 +898,44 @@ fsp_err_t R_I3C_CommandSend (i3c_ctrl_t * const p_api_ctrl, i3c_command_descript
     p_transfer_descriptor->buffer_size = p_command_descriptor->length;
 
     /* Calculate the command descriptor. */
-    uint32_t command_descriptor = 0;
-    command_descriptor |= (p_ctrl->device_index << I3C_CMD_DESC_DEV_INDEX_Pos) & I3C_CMD_DESC_DEV_INDEX_Msk;
-    command_descriptor |= (0 << I3C_CMD_DESC_XFER_MODE_Pos) & I3C_CMD_DESC_XFER_MODE_Msk;
-    command_descriptor |= (uint32_t) (p_command_descriptor->rnw << I3C_CMD_DESC_XFER_RNW_Pos);
-    command_descriptor |= I3C_CMD_DESC_ROC_Msk;
-    command_descriptor |= (uint32_t) (!p_command_descriptor->restart << I3C_CMD_DESC_TOC_Pos) & I3C_CMD_DESC_TOC_Msk;
-    command_descriptor |= (uint32_t) (p_command_descriptor->command_code << I3C_CMD_DESC_CMD_Pos);
-    command_descriptor |= (1U << 15U);
-    command_descriptor |= (uint32_t) (I3C_EVENT_COMMAND_COMPLETE << I3C_CMD_DESC_TID_Pos);
+    uint32_t cmd1 = 0;
+    cmd1 |= (p_ctrl->device_index << I3C_CMD_DESC_DEV_INDEX_Pos) & I3C_CMD_DESC_DEV_INDEX_Msk;
+    cmd1 |= (0 << I3C_CMD_DESC_XFER_MODE_Pos) & I3C_CMD_DESC_XFER_MODE_Msk;
+    cmd1 |= (uint32_t) (p_command_descriptor->rnw << I3C_CMD_DESC_XFER_RNW_Pos);
+    cmd1 |= I3C_CMD_DESC_ROC_Msk;
+    cmd1 |= (uint32_t) (!p_command_descriptor->restart << I3C_CMD_DESC_TOC_Pos) & I3C_CMD_DESC_TOC_Msk;
+    cmd1 |= (uint32_t) (p_command_descriptor->command_code << I3C_CMD_DESC_CMD_Pos);
+    cmd1 |= I3C_CMD_DESC_XFER_CP_Msk;
+    cmd1 |= (uint32_t) (I3C_EVENT_COMMAND_COMPLETE << I3C_CMD_DESC_TID_Pos);
+
+    uint32_t cmd2;
+    if ((4 >= p_command_descriptor->length) && !p_command_descriptor->rnw)
+    {
+        /* If the transfer length is less than or equal to 4 bytes, then use "Immediate Data Transfer".
+         * See section "25.3.1.1.2 Immediate Transfer Command" in the RA2E2 manual R01UH0919EJ0100. */
+        cmd1 |= I3C_CMD_DESC_CND_ATTR_IMMED_DATA_XFER;
+        cmd1 |= (p_command_descriptor->length << I3C_CMD_DESC_IMMED_DATA_XFER_BYTE_CNT_Pos);
+        cmd2  = i3c_next_data_word_calculate(&p_ctrl->write_buffer_descriptor);
+        p_ctrl->write_buffer_descriptor.count = p_command_descriptor->length;
+    }
+    else
+    {
+        cmd2 = (p_command_descriptor->length << I3C_CMD_DESC_XFER_LENGTH_Pos) &
+               I3C_CMD_DESC_XFER_LENGTH_Msk;
+    }
 
     /*
      * Write the descriptor to the command queue.
      * Note that the command descriptor is two words. The least significant word must be written first followed by
      * the most significant word (See Section 25.3.1.1 in the RA2E2 manual R01UH0919EJ0100).
      */
-    p_ctrl->p_reg->NCMDQP = command_descriptor;
-    p_ctrl->p_reg->NCMDQP = (p_command_descriptor->length << I3C_CMD_DESC_XFER_LENGTH_Pos) &
-                            I3C_CMD_DESC_XFER_LENGTH_Msk;
+    p_ctrl->p_reg->NCMDQP = cmd1;
+    p_ctrl->p_reg->NCMDQP = cmd2;
 
     /* Clear the command queue empty flag. */
     p_ctrl->p_reg->NTST_b.CMDQEF = 0;
 
-    if (!p_command_descriptor->rnw && (0 < p_command_descriptor->length))
+    if (!p_command_descriptor->rnw && (4 < p_command_descriptor->length))
     {
         /* Calculate the next data word that will be written to the FIFO. */
         p_ctrl->next_word = i3c_next_data_word_calculate(&p_ctrl->write_buffer_descriptor);
@@ -1011,14 +1035,18 @@ fsp_err_t R_I3C_Write (i3c_ctrl_t * const p_api_ctrl, uint8_t const * const p_da
     }
 #endif
 
-    /* Write data to the FIFO. */
-    i3c_fifo_write(p_ctrl);
-
-    /* If there is still data remaining in the transfer then it will be written in the Write Buffer Empty IRQ. */
-    if ((BSP_FEATURE_I3C_NTDTBP0_DEPTH * sizeof(uint32_t)) < length)
+    if ((length > 4) || (I3C_INTERNAL_STATE_SLAVE_IDLE == p_ctrl->internal_state))
     {
-        /* Enable the Write Buffer Empty IRQ. */
-        p_ctrl->p_reg->NTIE_b.TDBEIE0 = 1;
+        /* Write data to the FIFO. Note that in master mode, if the legnth is less than or equal to 4 bytes,
+         * the "Immediate Data Transfer" command must be used instead of the "Regular Transfer" command. */
+        i3c_fifo_write(p_ctrl);
+
+        /* If there is still data remaining in the transfer then it will be written in the Write Buffer Empty IRQ. */
+        if ((BSP_FEATURE_I3C_NTDTBP0_DEPTH * sizeof(uint32_t)) < length)
+        {
+            /* Enable the Write Buffer Empty IRQ. */
+            p_ctrl->p_reg->NTIE_b.TDBEIE0 = 1;
+        }
     }
 
 #if I3C_CFG_MASTER_SUPPORT
@@ -1031,11 +1059,25 @@ fsp_err_t R_I3C_Write (i3c_ctrl_t * const p_api_ctrl, uint8_t const * const p_da
          * Note that the command descriptor is two words. The least significant word must be written first followed by
          * the most significant word (See Section 25.3.1.1 in the RA2E2 manual R01UH0919EJ0100).
          */
-        p_ctrl->p_reg->NCMDQP = i3c_xfer_command_calculate(p_ctrl->device_index,
-                                                           false,
-                                                           p_ctrl->device_bitrate_mode,
-                                                           restart);
-        p_ctrl->p_reg->NCMDQP = (length << I3C_CMD_DESC_XFER_LENGTH_Pos) & I3C_CMD_DESC_XFER_LENGTH_Msk;
+        uint32_t cmd1 = i3c_xfer_command_calculate(p_ctrl->device_index, false, p_ctrl->device_bitrate_mode, restart);
+
+        uint32_t cmd2;
+        if (length <= 4)
+        {
+            /* If the transfer length is less than or equal to 4 bytes, then use "Immediate Data Transfer".
+             * See section "25.3.1.1.2 Immediate Transfer Command" in the RA2E2 manual R01UH0919EJ0100. */
+            cmd1 |= I3C_CMD_DESC_CND_ATTR_IMMED_DATA_XFER;
+            cmd1 |= (length << I3C_CMD_DESC_IMMED_DATA_XFER_BYTE_CNT_Pos);
+            cmd2  = p_ctrl->next_word;
+            p_ctrl->write_buffer_descriptor.count = length;
+        }
+        else
+        {
+            cmd2 = (length << I3C_CMD_DESC_XFER_LENGTH_Pos) & I3C_CMD_DESC_XFER_LENGTH_Msk;
+        }
+
+        p_ctrl->p_reg->NCMDQP = cmd1;
+        p_ctrl->p_reg->NCMDQP = cmd2;
 
         /* Clear the command queue empty flag. */
         p_ctrl->p_reg->NTST_b.CMDQEF = 0;
@@ -1327,7 +1369,7 @@ fsp_err_t R_I3C_Close (i3c_ctrl_t * const p_api_ctrl)
     FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->RSTCTL, 0U);
 
     /* Set the I3C Module Stop bit. */
-    R_BSP_MODULE_STOP(FSP_IP_IIC, p_ctrl->p_cfg->channel);
+    R_BSP_MODULE_STOP(FSP_IP_I3C, p_ctrl->p_cfg->channel);
 
     p_ctrl->open = 0;
 
diff --git a/ra/fsp/src/r_icu/r_icu.c b/ra/fsp/src/r_icu/r_icu.c
index f842feb0c..c39df8c62 100644
--- a/ra/fsp/src/r_icu/r_icu.c
+++ b/ra/fsp/src/r_icu/r_icu.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_iic_b_master/r_iic_b_master.c b/ra/fsp/src/r_iic_b_master/r_iic_b_master.c
index 7413c3899..ed8057ab3 100644
--- a/ra/fsp/src/r_iic_b_master/r_iic_b_master.c
+++ b/ra/fsp/src/r_iic_b_master/r_iic_b_master.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -126,11 +126,9 @@ static fsp_err_t iic_b_master_read_write(i2c_master_ctrl_t * const   p_api_ctrl,
 static void iic_b_master_notify(iic_b_master_instance_ctrl_t * const p_ctrl, i2c_master_event_t const event);
 
 #if IIC_B_MASTER_CFG_DTC_ENABLE
-static fsp_err_t iic_b_master_transfer_open(iic_b_master_instance_ctrl_t * p_ctrl,
-                                            i2c_master_cfg_t const * const p_cfg);
-static fsp_err_t iic_b_master_transfer_configure(iic_b_master_instance_ctrl_t * p_ctrl,
-                                                 transfer_instance_t const    * p_transfer,
-                                                 iic_b_master_transfer_dir_t    direction);
+static fsp_err_t iic_b_master_transfer_open(i2c_master_cfg_t const * const p_cfg);
+static fsp_err_t iic_b_master_transfer_configure(transfer_instance_t const * p_transfer,
+                                                 iic_b_master_transfer_dir_t direction);
 
 #endif
 
@@ -243,7 +241,7 @@ fsp_err_t R_IIC_B_MASTER_Open (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_
 #if IIC_B_MASTER_CFG_DTC_ENABLE
 
     /* Open the IIC transfer interface if available */
-    err = iic_b_master_transfer_open(p_ctrl, p_cfg);
+    err = iic_b_master_transfer_open(p_cfg);
     if (FSP_SUCCESS != err)
     {
         R_BSP_MODULE_STOP(FSP_IP_IIC, p_cfg->channel);
@@ -690,29 +688,28 @@ static void iic_b_master_notify (iic_b_master_instance_ctrl_t * const p_ctrl, i2
  **********************************************************************************************************************/
 static void iic_b_master_abort_seq_master (iic_b_master_instance_ctrl_t * const p_ctrl, bool iic_reset)
 {
-    /* Check if there is an in-progress transfer associated with the match or an error event occurred */
-    if ((0U != p_ctrl->remain) || (p_ctrl->restarted) || (true == p_ctrl->err))
+    /* Safely stop the hardware from operating. */
+
+    /* Reset the peripheral */
+    if (true == iic_reset)
     {
-        /* Reset the peripheral */
-        if (true == iic_reset)
-        {
-            /* Disable channel interrupts */
-            p_ctrl->p_reg->BIE  = 0x00;
-            p_ctrl->p_reg->NTIE = 0x00;
+        /* Disable channel interrupts */
+        p_ctrl->p_reg->BIE  = 0x00;
+        p_ctrl->p_reg->NTIE = 0x00;
 
-            /* This helper function would do a full IIC reset
-             * followed by re-initializing the required peripheral registers. */
-            iic_b_master_open_hw_master(p_ctrl, p_ctrl->p_cfg);
-        }
+        /* This helper function would do a full IIC reset
+         * followed by re-initializing the required peripheral registers. */
+        iic_b_master_open_hw_master(p_ctrl, p_ctrl->p_cfg);
+    }
 
-        /* Update the transfer descriptor to show no longer in-progress and an error */
-        p_ctrl->remain = 0U;
+    /* Update the transfer descriptor to show no longer in-progress and an error */
+    p_ctrl->remain = 0U;
 
-        /* Update the transfer descriptor to make sure interrupts no longer process */
-        p_ctrl->addr_loaded = p_ctrl->addr_total;
-        p_ctrl->loaded      = p_ctrl->total;
-        p_ctrl->restarted   = false;
-    }
+    /* Update the transfer descriptor to make sure interrupts no longer process */
+    p_ctrl->addr_loaded = p_ctrl->addr_total;
+    p_ctrl->loaded      = p_ctrl->total;
+    p_ctrl->restarted   = false;
+    p_ctrl->restart     = false;
 
     /* Enable Interrupts: TMOIE, ALIE, NAKIE, RIE, TIE.
      * Disable Interrupt: TEIE, STIE, SPIE
@@ -1465,20 +1462,19 @@ static void iic_b_master_txi_send_address (iic_b_master_instance_ctrl_t * const
  * @retval      FSP_SUCCESS                Transfer interface initialized successfully.
  * @retval      FSP_ERR_ASSERTION          Pointer to transfer instance for I2C receive in p_cfg is NULL.
  **********************************************************************************************************************/
-static fsp_err_t iic_b_master_transfer_open (iic_b_master_instance_ctrl_t * p_ctrl,
-                                             i2c_master_cfg_t const * const p_cfg)
+static fsp_err_t iic_b_master_transfer_open (i2c_master_cfg_t const * const p_cfg)
 {
     fsp_err_t err = FSP_SUCCESS;
 
     if (NULL != p_cfg->p_transfer_rx)
     {
-        err = iic_b_master_transfer_configure(p_ctrl, p_cfg->p_transfer_rx, IIC_B_MASTER_TRANSFER_DIR_READ);
+        err = iic_b_master_transfer_configure(p_cfg->p_transfer_rx, IIC_B_MASTER_TRANSFER_DIR_READ);
         FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
     }
 
     if (NULL != p_cfg->p_transfer_tx)
     {
-        err = iic_b_master_transfer_configure(p_ctrl, p_cfg->p_transfer_tx, IIC_B_MASTER_TRANSFER_DIR_WRITE);
+        err = iic_b_master_transfer_configure(p_cfg->p_transfer_tx, IIC_B_MASTER_TRANSFER_DIR_WRITE);
         if (FSP_SUCCESS != err)
         {
             if (NULL != p_cfg->p_transfer_rx)
@@ -1501,37 +1497,28 @@ static fsp_err_t iic_b_master_transfer_open (iic_b_master_instance_ctrl_t * p_ct
  * @retval        FSP_SUCCESS                Transfer interface is configured with valid parameters.
  * @retval        FSP_ERR_ASSERTION          Pointer to transfer instance for I2C receive in p_cfg is NULL.
  **********************************************************************************************************************/
-static fsp_err_t iic_b_master_transfer_configure (iic_b_master_instance_ctrl_t * p_ctrl,
-                                                  transfer_instance_t const    * p_transfer,
-                                                  iic_b_master_transfer_dir_t    direction)
+static fsp_err_t iic_b_master_transfer_configure (transfer_instance_t const * p_transfer,
+                                                  iic_b_master_transfer_dir_t direction)
 {
     fsp_err_t err;
-    IRQn_Type irq;
 
     /* Set default transfer info and open receive transfer module, if enabled. */
  #if (IIC_B_MASTER_CFG_PARAM_CHECKING_ENABLE)
     FSP_ASSERT(NULL != p_transfer->p_api);
-    FSP_ASSERT(NULL != p_transfer->p_ctrl);
     FSP_ASSERT(NULL != p_transfer->p_cfg);
     FSP_ASSERT(NULL != p_transfer->p_cfg->p_info);
  #endif
     transfer_info_t * p_cfg = p_transfer->p_cfg->p_info;
     if (IIC_B_MASTER_TRANSFER_DIR_READ == direction)
     {
-        irq = p_ctrl->p_cfg->rxi_irq;
         p_cfg->transfer_settings_word = IIC_B_MASTER_DTC_RX_TRANSFER_SETTINGS;
     }
     else
     {
-        irq = p_ctrl->p_cfg->txi_irq;
         p_cfg->transfer_settings_word = IIC_B_MASTER_DTC_TX_TRANSFER_SETTINGS;
     }
 
-    transfer_cfg_t       cfg = *(p_transfer->p_cfg);
-    dtc_extended_cfg_t * p_dtc_extended_configuration = (dtc_extended_cfg_t *) (cfg.p_extend);
-    p_dtc_extended_configuration->activation_source = irq;
-
-    err = p_transfer->p_api->open(p_transfer->p_ctrl, &cfg);
+    err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg);
     FSP_ERROR_RETURN((FSP_SUCCESS == err), err);
 
     return FSP_SUCCESS;
diff --git a/ra/fsp/src/r_iic_b_slave/r_iic_b_slave.c b/ra/fsp/src/r_iic_b_slave/r_iic_b_slave.c
index 4406cd5a3..2d2cf3313 100644
--- a/ra/fsp/src/r_iic_b_slave/r_iic_b_slave.c
+++ b/ra/fsp/src/r_iic_b_slave/r_iic_b_slave.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_iic_master/r_iic_master.c b/ra/fsp/src/r_iic_master/r_iic_master.c
index 92d3d22e3..391589cb7 100644
--- a/ra/fsp/src/r_iic_master/r_iic_master.c
+++ b/ra/fsp/src/r_iic_master/r_iic_master.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -157,10 +157,9 @@ static fsp_err_t iic_master_read_write(i2c_master_ctrl_t * const p_api_ctrl,
 static void iic_master_notify(iic_master_instance_ctrl_t * const p_ctrl, i2c_master_event_t const event);
 
 #if IIC_MASTER_CFG_DTC_ENABLE
-static fsp_err_t iic_master_transfer_open(iic_master_instance_ctrl_t * p_ctrl, i2c_master_cfg_t const * const p_cfg);
-static fsp_err_t iic_master_transfer_configure(iic_master_instance_ctrl_t * p_ctrl,
-                                               transfer_instance_t const  * p_transfer,
-                                               iic_master_transfer_dir_t    direction);
+static fsp_err_t iic_master_transfer_open(i2c_master_cfg_t const * const p_cfg);
+static fsp_err_t iic_master_transfer_configure(transfer_instance_t const * p_transfer,
+                                               iic_master_transfer_dir_t   direction);
 
 #endif
 
@@ -264,7 +263,7 @@ fsp_err_t R_IIC_MASTER_Open (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cf
 #if IIC_MASTER_CFG_DTC_ENABLE
 
     /* Open the IIC transfer interface if available */
-    err = iic_master_transfer_open(p_ctrl, p_cfg);
+    err = iic_master_transfer_open(p_cfg);
     if (FSP_SUCCESS != err)
     {
         R_BSP_MODULE_STOP(FSP_IP_IIC, p_cfg->channel);
@@ -699,28 +698,27 @@ static void iic_master_notify (iic_master_instance_ctrl_t * const p_ctrl, i2c_ma
  **********************************************************************************************************************/
 static void iic_master_abort_seq_master (iic_master_instance_ctrl_t * const p_ctrl, bool iic_reset)
 {
-    /* Check if there is an in-progress transfer associated with the match or an error event occurred */
-    if ((0U != p_ctrl->remain) || (p_ctrl->restarted) || (true == p_ctrl->err))
+    /* Safely stop the hardware from operating. */
+
+    /* Reset the peripheral */
+    if (true == iic_reset)
     {
-        /* Reset the peripheral */
-        if (true == iic_reset)
-        {
-            /* Disable channel interrupts */
-            p_ctrl->p_reg->ICIER = 0x00;
+        /* Disable channel interrupts */
+        p_ctrl->p_reg->ICIER = 0x00;
 
-            /* This helper function would do a full IIC reset
-             * followed by re-initializing the required peripheral registers. */
-            iic_master_open_hw_master(p_ctrl, p_ctrl->p_cfg);
-        }
+        /* This helper function would do a full IIC reset
+         * followed by re-initializing the required peripheral registers. */
+        iic_master_open_hw_master(p_ctrl, p_ctrl->p_cfg);
+    }
 
-        /* Update the transfer descriptor to show no longer in-progress and an error */
-        p_ctrl->remain = 0U;
+    /* Update the transfer descriptor to show no longer in-progress and an error */
+    p_ctrl->remain = 0U;
 
-        /* Update the transfer descriptor to make sure interrupts no longer process */
-        p_ctrl->addr_loaded = p_ctrl->addr_total;
-        p_ctrl->loaded      = p_ctrl->total;
-        p_ctrl->restarted   = false;
-    }
+    /* Update the transfer descriptor to make sure interrupts no longer process */
+    p_ctrl->addr_loaded = p_ctrl->addr_total;
+    p_ctrl->loaded      = p_ctrl->total;
+    p_ctrl->restarted   = false;
+    p_ctrl->restart     = false;
 
     /* Enable Interrupts: TMOIE, ALIE, NAKIE, RIE, TIE.
      * Disable Interrupt: TEIE, STIE, SPIE
@@ -1430,19 +1428,19 @@ static void iic_master_txi_send_address (iic_master_instance_ctrl_t * const p_ct
  * @retval      FSP_SUCCESS                Transfer interface initialized successfully.
  * @retval      FSP_ERR_ASSERTION          Pointer to transfer instance for I2C receive in p_cfg is NULL.
  **********************************************************************************************************************/
-static fsp_err_t iic_master_transfer_open (iic_master_instance_ctrl_t * p_ctrl, i2c_master_cfg_t const * const p_cfg)
+static fsp_err_t iic_master_transfer_open (i2c_master_cfg_t const * const p_cfg)
 {
     fsp_err_t err = FSP_SUCCESS;
 
     if (NULL != p_cfg->p_transfer_rx)
     {
-        err = iic_master_transfer_configure(p_ctrl, p_cfg->p_transfer_rx, IIC_MASTER_TRANSFER_DIR_READ);
+        err = iic_master_transfer_configure(p_cfg->p_transfer_rx, IIC_MASTER_TRANSFER_DIR_READ);
         FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
     }
 
     if (NULL != p_cfg->p_transfer_tx)
     {
-        err = iic_master_transfer_configure(p_ctrl, p_cfg->p_transfer_tx, IIC_MASTER_TRANSFER_DIR_WRITE);
+        err = iic_master_transfer_configure(p_cfg->p_transfer_tx, IIC_MASTER_TRANSFER_DIR_WRITE);
         if (FSP_SUCCESS != err)
         {
             if (NULL != p_cfg->p_transfer_rx)
@@ -1465,37 +1463,28 @@ static fsp_err_t iic_master_transfer_open (iic_master_instance_ctrl_t * p_ctrl,
  * @retval        FSP_SUCCESS                Transfer interface is configured with valid parameters.
  * @retval        FSP_ERR_ASSERTION          Pointer to transfer instance for I2C receive in p_cfg is NULL.
  **********************************************************************************************************************/
-static fsp_err_t iic_master_transfer_configure (iic_master_instance_ctrl_t * p_ctrl,
-                                                transfer_instance_t const  * p_transfer,
-                                                iic_master_transfer_dir_t    direction)
+static fsp_err_t iic_master_transfer_configure (transfer_instance_t const * p_transfer,
+                                                iic_master_transfer_dir_t   direction)
 {
     fsp_err_t err;
-    IRQn_Type irq;
 
     /* Set default transfer info and open receive transfer module, if enabled. */
  #if (IIC_MASTER_CFG_PARAM_CHECKING_ENABLE)
     FSP_ASSERT(NULL != p_transfer->p_api);
-    FSP_ASSERT(NULL != p_transfer->p_ctrl);
     FSP_ASSERT(NULL != p_transfer->p_cfg);
     FSP_ASSERT(NULL != p_transfer->p_cfg->p_info);
  #endif
     transfer_info_t * p_cfg = p_transfer->p_cfg->p_info;
     if (IIC_MASTER_TRANSFER_DIR_READ == direction)
     {
-        irq = p_ctrl->p_cfg->rxi_irq;
         p_cfg->transfer_settings_word = IIC_MASTER_DTC_RX_TRANSFER_SETTINGS;
     }
     else
     {
-        irq = p_ctrl->p_cfg->txi_irq;
         p_cfg->transfer_settings_word = IIC_MASTER_DTC_TX_TRANSFER_SETTINGS;
     }
 
-    transfer_cfg_t       cfg = *(p_transfer->p_cfg);
-    dtc_extended_cfg_t * p_dtc_extended_configuration = (dtc_extended_cfg_t *) (cfg.p_extend);
-    p_dtc_extended_configuration->activation_source = irq;
-
-    err = p_transfer->p_api->open(p_transfer->p_ctrl, &cfg);
+    err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg);
     FSP_ERROR_RETURN((FSP_SUCCESS == err), err);
 
     return FSP_SUCCESS;
diff --git a/ra/fsp/src/r_iic_slave/r_iic_slave.c b/ra/fsp/src/r_iic_slave/r_iic_slave.c
index 0af234832..56896f030 100644
--- a/ra/fsp/src/r_iic_slave/r_iic_slave.c
+++ b/ra/fsp/src/r_iic_slave/r_iic_slave.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_iirfa/r_iirfa.c b/ra/fsp/src/r_iirfa/r_iirfa.c
index 8e9b5e998..d65790aca 100644
--- a/ra/fsp/src/r_iirfa/r_iirfa.c
+++ b/ra/fsp/src/r_iirfa/r_iirfa.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_ioport/r_ioport.c b/ra/fsp/src/r_ioport/r_ioport.c
index ed9ab69df..3b9717239 100644
--- a/ra/fsp/src/r_ioport/r_ioport.c
+++ b/ra/fsp/src/r_ioport/r_ioport.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -46,10 +46,6 @@
 /* Shift to get port in bsp_io_port_t and bsp_io_port_pin_t enums. */
 #define IOPORT_PRV_PORT_OFFSET            (8U)
 
-#ifndef BSP_MCU_VBATT_SUPPORT
- #define BSP_MCU_VBATT_SUPPORT            (0U)
-#endif
-
 #define IOPORT_PRV_PORT_BITS              (0xFF00U)
 #define IOPORT_PRV_PIN_BITS               (0x00FFU)
 
@@ -84,7 +80,7 @@ static void r_ioport_hw_pin_event_output_data_write(bsp_io_port_t  port,
 
 static void r_ioport_pfs_write(bsp_io_port_pin_t pin, uint32_t value);
 
-#if BSP_MCU_VBATT_SUPPORT
+#if BSP_FEATURE_SYSC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN
 static void bsp_vbatt_init(ioport_cfg_t const * const p_pin_cfg); // Used internally by BSP
 
 #endif
@@ -115,7 +111,7 @@ const ioport_api_t g_ioport_on_ioport =
     .portWrite            = R_IOPORT_PortWrite,
 };
 
-#if BSP_MCU_VBATT_SUPPORT
+#if BSP_FEATURE_SYSC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN
 static const bsp_io_port_pin_t g_vbatt_pins_input[] =
 {
     BSP_IO_PORT_04_PIN_02,             ///< Associated with VBTICTLR->VCH0INEN
@@ -237,7 +233,7 @@ fsp_err_t R_IOPORT_PinCfg (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin,
     FSP_PARAMETER_NOT_USED(p_ctrl);
 #endif
 
-#if BSP_MCU_VBATT_SUPPORT
+#if BSP_FEATURE_SYSC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN
 
     /* Create temporary structure for handling VBATT pins. */
     ioport_cfg_t     temp_cfg;
@@ -687,7 +683,7 @@ fsp_err_t R_IOPORT_PinEventOutputWrite (ioport_ctrl_t * const p_ctrl, bsp_io_por
  **********************************************************************************************************************/
 void r_ioport_pins_config (const ioport_cfg_t * p_cfg)
 {
-#if BSP_MCU_VBATT_SUPPORT
+#if BSP_FEATURE_SYSC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN
 
     /* Handle any VBATT domain pin configuration. */
     bsp_vbatt_init(p_cfg);
@@ -778,7 +774,7 @@ static void r_ioport_pfs_write (bsp_io_port_pin_t pin, uint32_t value)
     R_PFS->PORT[pin >> IOPORT_PRV_PORT_OFFSET].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = value;
 }
 
-#if BSP_MCU_VBATT_SUPPORT
+#if BSP_FEATURE_SYSC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN
 
 /*******************************************************************************************************************//**
  * @brief Initializes VBTICTLR register based on pin configuration.
@@ -792,12 +788,6 @@ static void bsp_vbatt_init (ioport_cfg_t const * const p_pin_cfg)
 {
     uint32_t pin_index;
     uint32_t vbatt_index;
-    uint8_t  local_vbtictlr_set;       ///< Will hold bits to set in VBTICTLR
-    uint8_t  local_vbtictlr_clear;     ///< Will hold bits to clear in VBTICTLR
-
-    /* Make no changes unless required. */
-    local_vbtictlr_set   = 0U;
-    local_vbtictlr_clear = 0U;
 
     /* Must loop over all pins as pin configuration table is unordered. */
     for (pin_index = 0U; pin_index < p_pin_cfg->number_of_pins; pin_index++)
@@ -816,29 +806,78 @@ static void bsp_vbatt_init (ioport_cfg_t const * const p_pin_cfg)
                 if ((IOPORT_PERIPHERAL_AGT == pfs_psel_value) || (IOPORT_PERIPHERAL_CLKOUT_COMP_RTC == pfs_psel_value))
                 {
                     /* Bit should be set to 1. */
-                    local_vbtictlr_set |= (uint8_t) (1U << vbatt_index);
+ #if BSP_FEATURE_SYSC_HAS_VBTICTLR
+                    if (0 == (R_SYSTEM->VBTICTLR & (uint8_t) (1U << vbatt_index)))
+                    {
+                        R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
+                        R_SYSTEM->VBTICTLR |= (uint8_t) (1U << vbatt_index);
+                        R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
+                    }
+                    else
+                    {
+                        /* Do nothing: it is already enabled. */
+                    }
+ #endif
+ #if BSP_FEATURE_RTC_HAS_TCEN
+  #if BSP_TZ_NONSECURE_BUILD
+                    if (0 == R_PSCU->PSARE_b.PSARE2)
+                    {
+                        /* Do nothing: non secure build can't configure secure RTC registers. */
+                    }
+                    else
+  #endif
+                    {
+                        if (0 == R_RTC->RTCCR[vbatt_index].RTCCR_b.TCEN)
+                        {
+                            R_RTC->RTCCR[vbatt_index].RTCCR_b.TCEN = 1;
+                            R_BSP_SoftwareDelay(BSP_PRV_RTC_RESET_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS);
+                        }
+                        else
+                        {
+                            /* Do nothing: it is already enabled. */
+                        }
+                    }
+ #endif
                 }
                 else
                 {
                     /* Bit should be cleared to 0. */
-                    local_vbtictlr_clear |= (uint8_t) (1U << vbatt_index);
+ #if BSP_FEATURE_SYSC_HAS_VBTICTLR
+                    if ((R_SYSTEM->VBTICTLR & (uint8_t) (1U << vbatt_index)) > 0)
+                    {
+                        R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
+                        R_SYSTEM->VBTICTLR &= (uint8_t) ~(1U << vbatt_index);
+                        R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
+                    }
+                    else
+                    {
+                        /* Do nothing: it is already disabled. */
+                    }
+ #endif
+ #if BSP_FEATURE_RTC_HAS_TCEN
+  #if BSP_TZ_NONSECURE_BUILD
+                    if (0 == R_PSCU->PSARE_b.PSARE2)
+                    {
+                        /* Do nothing: non secure build can't configure secure RTC registers. */
+                    }
+                    else
+  #endif
+                    {
+                        if (R_RTC->RTCCR[vbatt_index].RTCCR_b.TCEN > 0)
+                        {
+                            R_RTC->RTCCR[vbatt_index].RTCCR_b.TCEN = 0;
+                            R_BSP_SoftwareDelay(BSP_PRV_RTC_RESET_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS);
+                        }
+                        else
+                        {
+                            /* Do nothing: it is already disabled. */
+                        }
+                    }
+ #endif
                 }
             }
         }
     }
-
-    /* Disable write protection on VBTICTLR. */
-    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
-
-    /* Read value, set and clear bits as needed and write back. */
-    uint8_t local_vbtictlr = R_SYSTEM->VBTICTLR;
-    local_vbtictlr |= local_vbtictlr_set;              ///< Set appropriate bits
-    local_vbtictlr &= (uint8_t) ~local_vbtictlr_clear; ///< Clear appropriate bits
-
-    R_SYSTEM->VBTICTLR = local_vbtictlr;
-
-    /* Enable write protection on VBTICTLR. */
-    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
 }
 
 #endif
diff --git a/ra/fsp/src/r_iwdt/r_iwdt.c b/ra/fsp/src/r_iwdt/r_iwdt.c
index fd9d55f29..8987cda99 100644
--- a/ra/fsp/src/r_iwdt/r_iwdt.c
+++ b/ra/fsp/src/r_iwdt/r_iwdt.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_jpeg/r_jpeg.c b/ra/fsp/src/r_jpeg/r_jpeg.c
index 12fca5b4d..fdfca69b6 100644
--- a/ra/fsp/src/r_jpeg/r_jpeg.c
+++ b/ra/fsp/src/r_jpeg/r_jpeg.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_kint/r_kint.c b/ra/fsp/src/r_kint/r_kint.c
index b2804cd81..fb0851d01 100644
--- a/ra/fsp/src/r_kint/r_kint.c
+++ b/ra/fsp/src/r_kint/r_kint.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_lpm/r_lpm.c b/ra/fsp/src/r_lpm/r_lpm.c
index 0e7a8522b..f34567e32 100644
--- a/ra/fsp/src/r_lpm/r_lpm.c
+++ b/ra/fsp/src/r_lpm/r_lpm.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_lvd/r_lvd.c b/ra/fsp/src/r_lvd/r_lvd.c
index b0cde3a2d..4754030e1 100644
--- a/ra/fsp/src/r_lvd/r_lvd.c
+++ b/ra/fsp/src/r_lvd/r_lvd.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_opamp/r_opamp.c b/ra/fsp/src/r_opamp/r_opamp.c
index b45348f28..17bc42ea0 100644
--- a/ra/fsp/src/r_opamp/r_opamp.c
+++ b/ra/fsp/src/r_opamp/r_opamp.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_ospi/r_ospi.c b/ra/fsp/src/r_ospi/r_ospi.c
index 79bbed8e2..9a777f43a 100644
--- a/ra/fsp/src/r_ospi/r_ospi.c
+++ b/ra/fsp/src/r_ospi/r_ospi.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_pdc/r_pdc.c b/ra/fsp/src/r_pdc/r_pdc.c
index 3cde089e1..fbbd699c0 100644
--- a/ra/fsp/src/r_pdc/r_pdc.c
+++ b/ra/fsp/src/r_pdc/r_pdc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_poeg/r_poeg.c b/ra/fsp/src/r_poeg/r_poeg.c
index 5105e3e52..c875cf3ca 100644
--- a/ra/fsp/src/r_poeg/r_poeg.c
+++ b/ra/fsp/src/r_poeg/r_poeg.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_ptp/r_edmac/r_edmac.c b/ra/fsp/src/r_ptp/r_edmac/r_edmac.c
index 0e8030ca1..b94967ec3 100644
--- a/ra/fsp/src/r_ptp/r_edmac/r_edmac.c
+++ b/ra/fsp/src/r_ptp/r_edmac/r_edmac.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_ptp/r_edmac/r_edmac.h b/ra/fsp/src/r_ptp/r_edmac/r_edmac.h
index 6de3a0643..dcf330e46 100644
--- a/ra/fsp/src/r_ptp/r_edmac/r_edmac.h
+++ b/ra/fsp/src/r_ptp/r_edmac/r_edmac.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_ptp/r_ptp.c b/ra/fsp/src/r_ptp/r_ptp.c
index d1d74a959..839b72c19 100644
--- a/ra/fsp/src/r_ptp/r_ptp.c
+++ b/ra/fsp/src/r_ptp/r_ptp.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_qspi/r_qspi.c b/ra/fsp/src/r_qspi/r_qspi.c
index 75cf60c45..f32fceac2 100644
--- a/ra/fsp/src/r_qspi/r_qspi.c
+++ b/ra/fsp/src/r_qspi/r_qspi.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_rtc/r_rtc.c b/ra/fsp/src/r_rtc/r_rtc.c
index f05306dcd..a6e4a6e33 100644
--- a/ra/fsp/src/r_rtc/r_rtc.c
+++ b/ra/fsp/src/r_rtc/r_rtc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -26,61 +26,58 @@
 /***********************************************************************************************************************
  * Macro definitions
  **********************************************************************************************************************/
-#define RTC_MASK_MSB                        (0x0F)
-#define RTC_MASK_LSB                        (0xF0)
+#define RTC_MASK_MSB                      (0x0F)
+#define RTC_MASK_LSB                      (0xF0)
 
-#define RTC_FIRST_DAY_OF_A_MONTH            (1)
+#define RTC_FIRST_DAY_OF_A_MONTH          (1)
 
 /* Day of week : valid range between 0 to 6. */
-#define RTC_DAYS_IN_A_WEEK                  (6)
+#define RTC_DAYS_IN_A_WEEK                (6)
 
 /* Month : valid range between 0 to 11.*/
-#define RTC_MONTHS_IN_A_YEAR                (11)
-#define RTC_LAST_DAY_OF_LEAP_FEB_MONTH      (29)
-#define RTC_LAST_DAY_OF_A_MONTH             (31)
-#define RTC_YEAR_VALUE_MIN                  (100)
-#define RTC_YEAR_VALUE_MAX                  (199)
+#define RTC_MONTHS_IN_A_YEAR              (11)
+#define RTC_LAST_DAY_OF_LEAP_FEB_MONTH    (29)
+#define RTC_LAST_DAY_OF_A_MONTH           (31)
+#define RTC_YEAR_VALUE_MIN                (100)
+#define RTC_YEAR_VALUE_MAX                (199)
 
 /* Seconds : valid range between 0 to 59.*/
-#define RTC_SECONDS_IN_A_MINUTE             (59)
+#define RTC_SECONDS_IN_A_MINUTE           (59)
 
 /* Minute : valid range between 0 to 59. */
-#define RTC_MINUTES_IN_A_HOUR               (59)
+#define RTC_MINUTES_IN_A_HOUR             (59)
 
 /* Hours : valid range between 0 to 23. */
-#define RTC_HOURS_IN_A_DAY                  (23)
+#define RTC_HOURS_IN_A_DAY                (23)
 
 /* In Zeller algorithm value of (-[Y/100] + [Y/400]) is 15 for Y = 2000 to Y = 2099) */
-#define RTC_ZELLER_ALGM_CONST_FIFTEEN       (15)
+#define RTC_ZELLER_ALGM_CONST_FIFTEEN     (15)
 
 /* Macro definitions for February and March months */
-#define RTC_FEBRUARY_MONTH                  (2U)
-#define RTC_MARCH_MONTH                     (3U)
+#define RTC_FEBRUARY_MONTH                (2U)
+#define RTC_MARCH_MONTH                   (3U)
 
-#define RTC_TIME_H_MONTH_OFFSET             (1)
+#define RTC_TIME_H_MONTH_OFFSET           (1)
 
 /*The RTC has a 100 year calendar to match the starting year 2000, year offset(1900) is added like 117 + 1900 = 2017 */
-#define RTC_TIME_H_YEAR_OFFSET              (1900)
+#define RTC_TIME_H_YEAR_OFFSET            (1900)
 
 /** "RTC" in ASCII, used to determine if device is open. */
-#define RTC_OPEN                            (0x00525443ULL)
+#define RTC_OPEN                          (0x00525443ULL)
 
-#define RTC_MAX_ERROR_ADJUSTMENT_VALUE      (0x3FU)
+#define RTC_MAX_ERROR_ADJUSTMENT_VALUE    (0x3FU)
 
-#define RTC_RHRCNT_HOUR_MASK                (0x3f)
-#define RTC_COMPARE_ENB_BIT                 (7U)
-#define RTC_MASK_8TH_BIT                    (0x7F)
+#define RTC_RHRCNT_HOUR_MASK              (0x3f)
+#define RTC_COMPARE_ENB_BIT               (7U)
+#define RTC_MASK_8TH_BIT                  (0x7F)
 
 /* As per HW manual, value of Year is between 0 to 99, the RTC has a 100 year calendar from 2000 to 2099.
  * But as per C standards, tm_year is years since 1900.*/
-#define RTC_C_TIME_OFFSET                   (100)
+#define RTC_C_TIME_OFFSET                 (100)
 
 /* See section 26.2.20 Frequency Register (RFRH/RFRL)" of the RA6M3 manual R01UH0886EJ0100) */
-#define RTC_RFRL_MIN_VALUE_LOCO             (0x7U)
-#define RTC_RFRL_MAX_VALUE_LOCO             (0x1FFU)
-
-#define RTC_SUB_CLK_STABLIZATION_TIME_MS    (100)
-#define RTC_LOCO_STABLIZATION_TIME_US       (190)
+#define RTC_RFRL_MIN_VALUE_LOCO           (0x7U)
+#define RTC_RFRL_MAX_VALUE_LOCO           (0x1FFU)
 
 /***********************************************************************************************************************
  * Typedef definitions
@@ -228,14 +225,6 @@ fsp_err_t R_RTC_Open (rtc_ctrl_t * const p_ctrl, rtc_cfg_t const * const p_cfg)
 
     r_rtc_config_rtc_interrupts(p_instance_ctrl, p_cfg);
 
-#if BSP_FEATURE_RTC_HAS_ROPSEL
-
-    /* Clear the RCR4_b.ROPSEL bit as it's value is undefined after MCU Reset and if its set to 1,
-     * the RTC operates in low-consumption clock mode. */
-    R_RTC->RCR4_b.ROPSEL = 0U;
-    FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR4_b.ROPSEL, 0U);
-#endif
-
     /* On a cold-start, force the RTC to be in the stopped state. Some devices power up with the RTC started. */
     /* Checks to see if the PORF bit is set. PORF can be cleared by software if application code handles a POR. */
     if (R_SYSTEM->RSTSR0 == 1)
@@ -823,16 +812,9 @@ static void r_rtc_set_clock_source (rtc_instance_ctrl_t * const p_ctrl, rtc_cfg_
     /* Select the count source (RCKSEL) */
     R_RTC->RCR4 = (uint8_t) p_ctrl->p_cfg->clock_source;
 
-    /* Supply 6 clocks of the count source (LOCO, 183us, 32kHZ).
+    /* Supply 6 clocks of the count source (LOCO/SOSC, 183us, 32kHZ).
      * See 26.3.2 "Clock and Count Mode Setting Procedure" of the RA6M3 manual R01UH0886EJ0100)*/
-    if (RTC_CLOCK_SOURCE_SUBCLK == p_ctrl->p_cfg->clock_source)
-    {
-        R_BSP_SoftwareDelay(RTC_SUB_CLK_STABLIZATION_TIME_MS, BSP_DELAY_UNITS_MILLISECONDS);
-    }
-    else
-    {
-        R_BSP_SoftwareDelay(RTC_LOCO_STABLIZATION_TIME_US, BSP_DELAY_UNITS_MICROSECONDS);
-    }
+    R_BSP_SoftwareDelay(BSP_PRV_RTC_RESET_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS);
 
     /* Set the START bit to 0 */
     r_rtc_start_bit_update(0U);
@@ -865,6 +847,15 @@ static void r_rtc_set_clock_source (rtc_instance_ctrl_t * const p_ctrl, rtc_cfg_
 
     /* Execute RTC software reset */
     r_rtc_software_reset();
+
+#if BSP_FEATURE_RTC_HAS_TCEN
+    for (uint8_t index = 0U; index < BSP_FEATURE_RTC_RTCCR_CHANNELS; index++)
+    {
+        /* RTCCRn.TCEN must be cleared after reset. */
+        R_RTC->RTCCR[index].RTCCR_b.TCEN = 0U;
+        FSP_HARDWARE_REGISTER_WAIT(R_RTC->RTCCR[index].RTCCR_b.TCEN, 0);
+    }
+#endif
 }
 
 /*******************************************************************************************************************//**
diff --git a/ra/fsp/src/r_sce/SCE_ProcCommon.h b/ra/fsp/src/r_sce/SCE_ProcCommon.h
index 7eeb8bf6f..7fa1d674a 100644
--- a/ra/fsp/src/r_sce/SCE_ProcCommon.h
+++ b/ra/fsp/src/r_sce/SCE_ProcCommon.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/aes2/SCE_module.h b/ra/fsp/src/r_sce/aes2/SCE_module.h
new file mode 100644
index 000000000..1237b414c
--- /dev/null
+++ b/ra/fsp/src/r_sce/aes2/SCE_module.h
@@ -0,0 +1,31 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef HW_SCE_MODULE_H
+#define HW_SCE_MODULE_H
+#include "bsp_api.h"
+
+/* ================================================================================ */
+/* ================              Peripheral memory map             ================ */
+/* ================================================================================ */
+#define SCE1_TRNG_BASE    0x400D1000UL
+#define SCE1_AES_BASE     0x400D0000UL
+
+#endif                                 // HW_SCE_MODULE_H
diff --git a/ra/fsp/src/r_sce/aes2/adaptors/hw_sce_ra_private.h b/ra/fsp/src/r_sce/aes2/adaptors/hw_sce_ra_private.h
new file mode 100644
index 000000000..90c7939c8
--- /dev/null
+++ b/ra/fsp/src/r_sce/aes2/adaptors/hw_sce_ra_private.h
@@ -0,0 +1,93 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ *********************************************************************************************************************/
+#ifndef HW_SCE_RA_PRIVATE_HEADER_FILE
+#define HW_SCE_RA_PRIVATE_HEADER_FILE
+
+#include "hw_sce_aes_private.h"
+
+/**********************************************************************************************************************
+ * Macro definitions
+ *********************************************************************************************************************/
+#define SCE_AES_IN_DATA_CMD_ECB_ENCRYPTION               (0x00000000U)
+#define SCE_AES_IN_DATA_CMD_ECB_DECRYPTION               (0x00000001U)
+#define SCE_AES_IN_DATA_CMD_CBC_ENCRYPTION               (0x00000002U)
+#define SCE_AES_IN_DATA_CMD_CBC_DECRYPTION               (0x00000003U)
+#define SCE_AES_IN_DATA_CMD_CTR_ENCRYPTION_DECRYPTION    (0x00000004U)
+
+/* Wrapped keys not supported on RA2; these definitions are added to let the code compile. */
+#define SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED              (1)
+#define SIZE_AES_128BIT_KEYLEN_BYTES_WRAPPED             ((SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED) / 8)
+#define SIZE_AES_128BIT_KEYLEN_WORDS_WRAPPED             ((SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED) / 32)
+
+#define SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED              (2) /* 192 not supported on SCE5 */
+#define SIZE_AES_192BIT_KEYLEN_BYTES_WRAPPED             ((SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED) / 8)
+#define SIZE_AES_192BIT_KEYLEN_WORDS_WRAPPED             ((SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED) / 32)
+
+#define SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED              (3)
+#define SIZE_AES_256BIT_KEYLEN_BYTES_WRAPPED             ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 8)
+#define SIZE_AES_256BIT_KEYLEN_WORDS_WRAPPED             ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 32)
+
+/**********************************************************************************************************************
+ * Global Typedef definitions
+ *********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * External global variables
+ *********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Exported global functions
+ *********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ ***********************************************************************************************************************/
+uint32_t change_endian_long(uint32_t data);
+
+fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub(const uint32_t * InData_KeyType,
+                                             const uint32_t * InData_Cmd,
+                                             const uint32_t * InData_KeyIndex,
+                                             const uint32_t * InData_IV);
+void HW_SCE_Aes128EncryptDecryptUpdateSub(const uint32_t * InData_Text,
+                                          uint32_t       * OutData_Text,
+                                          const uint32_t   MAX_CNT);
+fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub(void);
+
+fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub(const uint32_t * InData_Cmd,
+                                             const uint32_t * InData_KeyIndex,
+                                             const uint32_t * InData_IV);
+void HW_SCE_Aes192EncryptDecryptUpdateSub(const uint32_t * InData_Text,
+                                          uint32_t       * OutData_Text,
+                                          const uint32_t   MAX_CNT);
+fsp_err_t HW_SCE_Aes192EncryptDecryptFinalSub(void);
+fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub(const uint32_t * InData_KeyType,
+                                             const uint32_t * InData_Cmd,
+                                             const uint32_t * InData_KeyIndex,
+                                             const uint32_t * InData_IV);
+void HW_SCE_Aes256EncryptDecryptUpdateSub(const uint32_t * InData_Text,
+                                          uint32_t       * OutData_Text,
+                                          const uint32_t   MAX_CNT);
+fsp_err_t HW_SCE_Aes256EncryptDecryptFinalSub(void);
+
+#endif                                 /* HW_SCE_RA_PRIVATE_HEADER_FILE */
diff --git a/ra/fsp/src/r_sce/aes2/adaptors/r_sce_AES_adapt.c b/ra/fsp/src/r_sce/aes2/adaptors/r_sce_AES_adapt.c
new file mode 100644
index 000000000..b4e11078d
--- /dev/null
+++ b/ra/fsp/src/r_sce/aes2/adaptors/r_sce_AES_adapt.c
@@ -0,0 +1,146 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ ***********************************************************************************************************************/
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Imported global variables and functions
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ ***********************************************************************************************************************/
+
+uint32_t change_endian_long (uint32_t a)
+{
+    return __REV(a);
+}
+
+fsp_err_t HW_SCE_GenerateAes128RandomKeyIndexSub (uint32_t * OutData_KeyIndex)
+{
+    FSP_PARAMETER_NOT_USED(OutData_KeyIndex);
+
+    return FSP_ERR_UNSUPPORTED;
+}
+
+fsp_err_t HW_SCE_GenerateAes192RandomKeyIndexSub (uint32_t * OutData_KeyIndex)
+{
+    FSP_PARAMETER_NOT_USED(OutData_KeyIndex);
+
+    return FSP_ERR_UNSUPPORTED;
+}
+
+fsp_err_t HW_SCE_GenerateAes256RandomKeyIndexSub (uint32_t * OutData_KeyIndex)
+{
+    FSP_PARAMETER_NOT_USED(OutData_KeyIndex);
+
+    return FSP_ERR_UNSUPPORTED;
+}
+
+fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub (const uint32_t * InData_Cmd,
+                                              const uint32_t * InData_KeyIndex,
+                                              const uint32_t * InData_IV)
+{
+    FSP_PARAMETER_NOT_USED(InData_Cmd);
+    FSP_PARAMETER_NOT_USED(InData_KeyIndex);
+    FSP_PARAMETER_NOT_USED(InData_IV);
+
+    return FSP_ERR_UNSUPPORTED;
+}
+
+void HW_SCE_Aes192EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_t * OutData_Text,
+                                           const uint32_t MAX_CNT)
+{
+    FSP_PARAMETER_NOT_USED(InData_Text);
+    FSP_PARAMETER_NOT_USED(OutData_Text);
+    FSP_PARAMETER_NOT_USED(MAX_CNT);
+}
+
+fsp_err_t HW_SCE_Aes192EncryptDecryptFinalSub (void)
+{
+    return FSP_ERR_UNSUPPORTED;
+}
+
+fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub (const uint32_t * InData_KeyType,
+                                              const uint32_t * InData_Cmd,
+                                              const uint32_t * InData_KeyIndex,
+                                              const uint32_t * InData_IV)
+{
+    FSP_PARAMETER_NOT_USED(InData_KeyType);
+    FSP_PARAMETER_NOT_USED(InData_Cmd);
+    FSP_PARAMETER_NOT_USED(InData_KeyIndex);
+    FSP_PARAMETER_NOT_USED(InData_IV);
+
+    return FSP_ERR_UNSUPPORTED;
+}
+
+void HW_SCE_Aes128EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_t * OutData_Text,
+                                           const uint32_t MAX_CNT)
+{
+    FSP_PARAMETER_NOT_USED(InData_Text);
+    FSP_PARAMETER_NOT_USED(OutData_Text);
+    FSP_PARAMETER_NOT_USED(MAX_CNT);
+}
+
+fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub (void)
+{
+    return FSP_ERR_UNSUPPORTED;
+}
+
+fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub (const uint32_t * InData_KeyType,
+                                              const uint32_t * InData_Cmd,
+                                              const uint32_t * InData_KeyIndex,
+                                              const uint32_t * InData_IV)
+{
+    FSP_PARAMETER_NOT_USED(InData_KeyType);
+    FSP_PARAMETER_NOT_USED(InData_Cmd);
+    FSP_PARAMETER_NOT_USED(InData_KeyIndex);
+    FSP_PARAMETER_NOT_USED(InData_IV);
+
+    return FSP_ERR_UNSUPPORTED;
+}
+
+void HW_SCE_Aes256EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_t * OutData_Text,
+                                           const uint32_t MAX_CNT)
+{
+    FSP_PARAMETER_NOT_USED(InData_Text);
+    FSP_PARAMETER_NOT_USED(OutData_Text);
+    FSP_PARAMETER_NOT_USED(MAX_CNT);
+}
+
+fsp_err_t HW_SCE_Aes256EncryptDecryptFinalSub (void)
+{
+    return FSP_ERR_UNSUPPORTED;
+}
diff --git a/ra/fsp/src/r_sce/aes2/adaptors/r_sce_if.h b/ra/fsp/src/r_sce/aes2/adaptors/r_sce_if.h
new file mode 100644
index 000000000..7811137d7
--- /dev/null
+++ b/ra/fsp/src/r_sce/aes2/adaptors/r_sce_if.h
@@ -0,0 +1,80 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ *********************************************************************************************************************/
+
+#include "bsp_api.h"
+
+/**********************************************************************************************************************
+ * Macro definitions
+ *********************************************************************************************************************/
+
+#ifndef R_SCE_IF_HEADER_FILE
+ #define R_SCE_IF_HEADER_FILE
+
+ #define HW_SCE_AES128XTS_KEY_BIT_SIZE    (256U)
+ #define HW_SCE_AES256XTS_KEY_BIT_SIZE    (512U)
+
+/* OEM Command */
+typedef enum e_sce_oem_cmd
+{
+    SCE_OEM_CMD_AES128 = 5,
+    SCE_OEM_CMD_AES192,
+    SCE_OEM_CMD_AES256,
+    SCE_OEM_CMD_AES128_XTS,
+    SCE_OEM_CMD_AES256_XTS,
+    SCE_OEM_CMD_RSA1024_PUBLIC,
+    SCE_OEM_CMD_RSA1024_PRIVATE,
+    SCE_OEM_CMD_RSA2048_PUBLIC,
+    SCE_OEM_CMD_RSA2048_PRIVATE,
+    SCE_OEM_CMD_RSA3072_PUBLIC,
+    SCE_OEM_CMD_RSA3072_PRIVATE,
+    SCE_OEM_CMD_RSA4096_PUBLIC,
+    SCE_OEM_CMD_RSA4096_PRIVATE,
+    SCE_OEM_CMD_ECC_P192_PUBLIC,
+    SCE_OEM_CMD_ECC_P192_PRIVATE,
+    SCE_OEM_CMD_ECC_P224_PUBLIC,
+    SCE_OEM_CMD_ECC_P224_PRIVATE,
+    SCE_OEM_CMD_ECC_P256_PUBLIC,
+    SCE_OEM_CMD_ECC_P256_PRIVATE,
+    SCE_OEM_CMD_ECC_P384_PUBLIC,
+    SCE_OEM_CMD_ECC_P384_PRIVATE,
+    SCE_OEM_CMD_HMAC_SHA224,
+    SCE_OEM_CMD_HMAC_SHA256,
+    SCE_OEM_CMD_ECC_P256R1_PUBLIC,
+    SCE_OEM_CMD_ECC_P256R1_PRIVATE,
+    SCE_OEM_CMD_ECC_P384R1_PUBLIC,
+    SCE_OEM_CMD_ECC_P384R1_PRIVATE,
+    SCE_OEM_CMD_ECC_P512R1_PUBLIC,
+    SCE_OEM_CMD_ECC_P512R1_PRIVATE,
+    SCE_OEM_CMD_ECC_SECP256K1_PUBLIC,
+    SCE_OEM_CMD_ECC_SECP256K1_PRIVATE,
+    SCE_OEM_CMD_NUM
+} sce_oem_cmd_t;
+
+typedef enum e_sce_oem_key_type
+{
+    SCE_OEM_KEY_TYPE_ENCRYPTED = 0,
+    SCE_OEM_KEY_TYPE_PLAIN     = 1
+} sce_oem_key_type_t;
+
+#endif                                 /* R_SCE_IF_HEADER_FILE */
diff --git a/ra/fsp/src/r_sce/aes2/r_sce_iodefine.h b/ra/fsp/src/r_sce/aes2/r_sce_iodefine.h
new file mode 100644
index 000000000..64af5113a
--- /dev/null
+++ b/ra/fsp/src/r_sce/aes2/r_sce_iodefine.h
@@ -0,0 +1,99 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef SCE_IODEFINE_H
+#define SCE_IODEFINE_H
+
+#include <stdint.h>
+#include "SCE_module.h"
+
+typedef struct                              /*!< SCE register structure        */
+{
+    volatile uint8_t REG_00H;               /*!< TRNG seed data register       */
+    volatile uint8_t REG_01H;               /*!< Reserved                      */
+    union
+    {
+        volatile uint8_t REG_02H;           /*!< TRNG seed command register 0  */
+        struct
+        {
+            volatile         uint8_t   : 2;
+            volatile uint8_t rng_start : 1; /// !< seed generation start, this bit is read as 0
+            volatile uint8_t core_en   : 1; /// !< seed generation enable/disable bit
+            volatile         uint8_t   : 3;
+            volatile uint8_t rdrdy     : 1; /// !< indicates if seed generation completed. when core_en bit is 0, this bit is read as 0
+        } TRNGSCR0;
+    };
+    volatile uint8_t REG_03H;               /*!< TRNG seed command register 1  */
+    volatile uint8_t REG_04H;               /*!< Reserved                      */
+    volatile uint8_t REG_05H;               /*!< Reserved                      */
+    volatile uint8_t REG_06H;               /*!< Reserved                      */
+    volatile uint8_t REG_07H;               /*!< Reserved                      */
+} SCE1_TRNG_Type;
+
+#define R_TRNG    ((volatile SCE1_TRNG_Type *) SCE1_TRNG_BASE)
+
+typedef struct
+{
+    union
+    {
+        volatile uint32_t AESMOD;               ///< AES Mode register
+        struct
+        {
+            volatile uint32_t module_en    : 1; /// !< AES Module enable bit
+            volatile          uint32_t     : 6;
+            volatile uint32_t read_req_en  : 1; /// !< Enable or disable processed of data read using DTC
+            volatile uint32_t write_req_en : 1; /// !< Enable or disable processing of data written using DTC
+        } AESMOD_b;
+    };
+
+    union
+    {
+        volatile uint32_t AESCMD;                    ///< AES Command register
+        struct
+        {
+            volatile uint32_t inverse_cipher    : 1; /// !< Select data encryption or decryption
+            volatile uint32_t key_length        : 1; /// !< Select the key length
+            volatile          uint32_t          : 2;
+            volatile uint32_t chaining          : 2; /// !< Select the chaining mode
+            volatile          uint32_t          : 2;
+            volatile          uint32_t          : 2; /// !< Select output destination of an operation result
+            volatile          uint32_t          : 2;
+            volatile uint32_t key_select        : 1; /// !< Select the key-register
+            volatile          uint32_t          : 11;
+            volatile uint32_t write_ready       : 1; /// !< Select the key-register
+            volatile uint32_t read_ready        : 1; /// !< Select the key-register
+            volatile uint32_t com_write_ready   : 1; /// !< Select the key-register
+            volatile uint32_t iv_write_ready    : 1; /// !< Select the key-register
+            volatile uint32_t iv_read_ready     : 1; /// !< Select the key-register
+            volatile uint32_t key_write_ready0  : 1; /// !< Select the key-register
+            volatile uint32_t key_write_ready1  : 1; /// !< Select the key-register
+            volatile uint32_t illegal_operation : 1; /// !< Select the key-register
+        } AESCMD_b;
+    };
+
+    volatile uint32_t AESDW;                         ///< AES Data Windows register
+    volatile uint32_t AESIVW;                        ///< AES IV Window register
+    volatile uint32_t AESKW0;                        ///< AES Key Window 0 register
+    volatile uint32_t AESKW1;                        ///< AES Key Window 1 register
+} SCE1_AES_Type;
+
+#define SCE1_AES    ((volatile SCE1_AES_Type *) SCE1_AES_BASE)
+
+#endif                                 /* SCE_IODEFINE_H */
diff --git a/ra/fsp/src/r_sce/aes2/r_sce_trng.c b/ra/fsp/src/r_sce/aes2/r_sce_trng.c
new file mode 100644
index 000000000..790646705
--- /dev/null
+++ b/ra/fsp/src/r_sce/aes2/r_sce_trng.c
@@ -0,0 +1,57 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+#include "r_sce_iodefine.h"
+#include "bsp_api.h"
+#include "hw_sce_trng_private.h"
+
+/*******************************************************************************************************************//**
+ * 128bit Random Number Generation
+ * @param      OutData_Text    The out data text
+ * @retval FSP_SUCCESS      The operation completed successfully.
+ **********************************************************************************************************************/
+fsp_err_t HW_SCE_RNG_Read (uint32_t * OutData_Text) {
+    uint8_t * ptmp = (uint8_t *) OutData_Text;
+    uint32_t  k;
+
+    for (k = 0; k < 4; k++)            // read 4 words of random data similar (to make this API consistent with S7 and S3 implementation)
+    {
+        /* Set core_en bit and rng_start bit */
+        R_TRNG->TRNGSCR0.core_en   = 1;
+        R_TRNG->TRNGSCR0.rng_start = 1;
+
+        /* Wait for RDRDY bit to be set */
+        while (0 == R_TRNG->TRNGSCR0.rdrdy)
+        {
+        }
+
+        /* Read generated random data */
+        *ptmp++ = R_TRNG->REG_00H;
+        *ptmp++ = R_TRNG->REG_00H;
+        *ptmp++ = R_TRNG->REG_00H;
+        *ptmp++ = R_TRNG->REG_00H;
+    }
+
+    return FSP_SUCCESS;
+}
diff --git a/ra/fsp/src/r_sce/aes2/r_sce_utils.c b/ra/fsp/src/r_sce/aes2/r_sce_utils.c
new file mode 100644
index 000000000..12334af66
--- /dev/null
+++ b/ra/fsp/src/r_sce/aes2/r_sce_utils.c
@@ -0,0 +1,34 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#include "hw_sce_private.h"
+
+/*******************************************************************************************************************//**
+ * Initialize the crypto engine
+ * @retval FSP_SUCCESS      The operation completed successfully.
+ **********************************************************************************************************************/
+
+fsp_err_t HW_SCE_McuSpecificInit (void)
+{
+    // power on the SCE module
+    HW_SCE_PowerOn();
+
+    return FSP_SUCCESS;
+}
diff --git a/ra/fsp/src/r_sce/common/hw_sce_common.h b/ra/fsp/src/r_sce/common/hw_sce_common.h
index 77d37f016..b19bf3db3 100644
--- a/ra/fsp/src/r_sce/common/hw_sce_common.h
+++ b/ra/fsp/src/r_sce/common/hw_sce_common.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/adaptors/r_sce_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/adaptors/r_sce_adapt.c
index 02db59a6f..2ceffe243 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/adaptors/r_sce_adapt.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/adaptors/r_sce_adapt.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/change_endian_long.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/change_endian_long.c
index aee2c0738..47c7496c6 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/change_endian_long.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/change_endian_long.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func008.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func008.c
index a0f03133a..5f55fc733 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func008.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func008.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func027.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func027.c
index 1a6c644f3..3e1efc8b0 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func027.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func027.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func028.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func028.c
index 707b4c951..c16f452fc 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func028.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func028.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func031.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func031.c
index 9d44fd04f..084cbd7d1 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func031.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func031.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func043.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func043.c
index 9058aeb08..ba2540767 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func043.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func043.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func044.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func044.c
index a1c51f454..cdbae1168 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func044.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func044.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func048.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func048.c
index abc6106f3..82fadee78 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func048.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func048.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func049.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func049.c
index ceedd13b6..d118b2790 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func049.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func049.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func057.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func057.c
index 5e3537000..0f21d3959 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func057.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func057.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func058.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func058.c
index 1e1c7a38f..c3b647084 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func058.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func058.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func059.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func059.c
index da6b30707..2c54fce1c 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func059.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func059.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func060.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func060.c
index 8a10065c7..2560b4cae 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func060.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func060.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func061.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func061.c
index 69572bb44..b722439dc 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func061.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func061.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func062.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func062.c
index 346884111..02d00c642 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func062.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func062.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func063.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func063.c
index d7d910cff..0ef75ef4d 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func063.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func063.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func065.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func065.c
index e23d3c220..99e0f66e1 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func065.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func065.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func066.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func066.c
index 2d42d94ea..5f628c7ee 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func066.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func066.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func068.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func068.c
index 591dcccb2..3ecb8ca59 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func068.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func068.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func070.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func070.c
index b5fda8442..70abf967a 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func070.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func070.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func071.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func071.c
index ecb68db36..962701e31 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func071.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func071.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func073.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func073.c
index 2c15550e5..c8e986264 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func073.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func073.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func074.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func074.c
index c399577ec..47eb817e1 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func074.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func074.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func075.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func075.c
index fa5c5d8a3..598d5fe22 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func075.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func075.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func076.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func076.c
index 0602b8c3a..33479906a 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func076.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func076.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func077.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func077.c
index 10a064a72..980c04681 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func077.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func077.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func078.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func078.c
index 7c4e9e489..39c477d99 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func078.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func078.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func079.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func079.c
index c734b584f..e02657e13 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func079.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func079.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func081.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func081.c
index 9027064c0..55e8ebe5c 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func081.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func081.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func082.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func082.c
index 69eb289df..a5ef3b961 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func082.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func082.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func086.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func086.c
index 1127deff6..804a3141c 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func086.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func086.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func087.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func087.c
index 68b484010..131d8b57d 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func087.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func087.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func088.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func088.c
index a1359801b..5704a1200 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func088.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func088.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func089.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func089.c
index 8326416f3..6d6603124 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func089.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func089.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func090.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func090.c
index 41d8132a2..538557868 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func090.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func090.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func091.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func091.c
index 454f1b35e..e845102ba 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func091.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func091.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func092.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func092.c
index 0326bae83..ec1e6eef1 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func092.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func092.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func093.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func093.c
index cd5b6a67e..c9e78ab6c 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func093.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func093.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func094.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func094.c
index ab37a8d15..3aae0ff93 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func094.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func094.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func095.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func095.c
index adb4b2a5e..2ed508682 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func095.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func095.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func100.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func100.c
index 963f8a5d2..1af66761e 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func100.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func100.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func101.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func101.c
index 375808b14..d8aa15c00 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func101.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func101.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func102.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func102.c
index a88d7e888..b371b90b0 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func102.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func102.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func103.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func103.c
index 182865d86..1601b66cb 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func103.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func103.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func202.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func202.c
index 8579b1b88..ac7d4f9db 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func202.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func202.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func209.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func209.c
index b3092e538..86a2de1a1 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func209.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func209.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func214.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func214.c
index eb6417b45..4011031cc 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func214.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func214.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func215.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func215.c
index 2d3e20fa2..7991baebd 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func215.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func215.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func216.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func216.c
index d762cffc9..94972fae6 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func216.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func216.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p00.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p00.c
index 1f2acb9b3..111da8ffc 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p00.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p00.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p07.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p07.c
index c435167e0..bd268042f 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p07.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p07.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p08.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p08.c
index 885a4c1fa..bd1a06b5c 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p08.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p08.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p11.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p11.c
index bfe3639a7..d4d8ae24e 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p11.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p11.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p12.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p12.c
index 28b2499be..4cb57234a 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p12.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p12.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p13.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p13.c
index 41eba872b..aaed530f9 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p13.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p13.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p14.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p14.c
index 86d4f7a89..99dc52baf 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p14.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p14.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p15.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p15.c
index 728bcbb68..66379507d 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p15.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p15.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p16.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p16.c
index e6ad98259..a2a2166c7 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p16.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p16.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p17.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p17.c
index e5868fde3..f83fc3cab 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p17.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p17.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p20.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p20.c
index a88b80f81..c8ac0be6e 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p20.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p20.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p21.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p21.c
index b9d762340..7479a0d52 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p21.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p21.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p26.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p26.c
index 94480c711..5ea4691a0 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p26.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p26.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29a.c
index 82d0b8956..7ff0a4372 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29a.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29a.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29f.c
index 036d6f1ba..05ee8784b 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29i.c
index 10ae6c844..019bafa0f 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29t.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29t.c
index b1dc43e89..beca36f77 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29t.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29t.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29u.c
index 9c20bd9a0..9796b912c 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32a.c
index 3523456d9..3855fcf11 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32a.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32a.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32f.c
index 7d33ac357..dc35a95c5 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32i.c
index 949ea0dfe..3cb643312 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32t.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32t.c
index 33afe3d23..fd8df0fa3 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32t.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32t.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32u.c
index 774fea513..edf132288 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34a.c
index 3b4b483f5..f51debef4 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34a.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34a.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34f.c
index 7535271f4..5ebfea399 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34i.c
index 043dda92e..42f70f2e9 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34t.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34t.c
index 1c253f5d3..a4bc281c4 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34t.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34t.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34u.c
index a7e0cf436..bf434cd25 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36a.c
index feaa2b6e2..c80404703 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36a.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36a.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36f.c
index 5691d4988..6c122d7be 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36i.c
index e7b6a41d3..fe63fdc20 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36t.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36t.c
index 3b87120f1..f95973dd9 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36t.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36t.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36u.c
index 406dc5cb4..53325e213 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p40.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p40.c
index e4212203f..594e3cb34 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p40.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p40.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41f.c
index 035d99c9c..a9f259c75 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41i.c
index eff29c2ef..4d1702b58 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41u.c
index 5b145e2f5..4526300c1 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44f.c
index f7741e08e..da914e170 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44i.c
index c211128a5..2133a9573 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44u.c
index ae5fbb6ee..14a2736e5 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47f.c
index 1ff070773..5b3944b17 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47i.c
index ad70b70b6..7e4c9597e 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47u.c
index 3b49e3e47..c72872fd5 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50f.c
index ed6890b9a..bda53f9dd 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50i.c
index 587ffe48c..b14647cd1 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50u.c
index bb89ac2f6..f22874454 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p53.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p53.c
index ea8117c2d..c7deaf297 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p53.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p53.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p54.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p54.c
index c980b96b6..cdb46df0d 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p54.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p54.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p56.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p56.c
index 6f49540fc..553fd97a7 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p56.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p56.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p57.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p57.c
index bcee0457e..5c13d6a62 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p57.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p57.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p6e.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p6e.c
index 912ec10e4..59900e2cb 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p6e.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p6e.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p70.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p70.c
index a0c09a48f..fb8df4fbc 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p70.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p70.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p72.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p72.c
index f4f617594..b25dcb789 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p72.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p72.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76f.c
index ade87b175..f68a52154 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76i.c
index cd581332d..31396ddcb 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76u.c
index c2f0f8941..6cdb8557f 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p79.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p79.c
index 6dbd2be54..2fffdf4d6 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p79.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p79.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7a.c
index 010a7d3e5..0b023a068 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7a.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7a.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7b.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7b.c
index dac1b6020..7d7a0a314 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7b.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7b.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7c.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7c.c
index b59c36145..31f045824 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7c.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7c.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7d.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7d.c
index 529be383e..115a71146 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7d.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7d.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7e.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7e.c
index 141498ac4..fa964754d 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7e.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7e.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7f.c
index 385e273df..92a4198e8 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p81.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p81.c
index 21badd8d7..ea7a5a5d6 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p81.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p81.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p82.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p82.c
index 7572ea67d..7ca0345ea 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p82.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p82.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83a.c
index 74d9a4a8e..6f6209d69 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83a.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83a.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83f.c
index 603d6aba8..68f559e60 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83i.c
index ab36c0940..2594dcb1e 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83t.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83t.c
index dc242cdc6..c060ebde2 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83t.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83t.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83u.c
index 10fbcd4d6..d46f2284b 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85a.c
index eb1766e30..7c88c641a 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85a.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85a.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85f.c
index cd6787d85..4d24e3699 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85i.c
index 2112ed9dd..66a125203 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85t.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85t.c
index 800d03089..9e06aa2e6 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85t.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85t.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85u.c
index d78592104..eb5f01fe4 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87f.c
index 28cee107b..f20be2dbc 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87i.c
index 47a96df08..e52ae0ed7 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87u.c
index aa8700e6d..26b15318e 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89f.c
index ab4a6a149..b3cc0885f 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89i.c
index ad4120890..ae6b7749d 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89u.c
index 81441efec..abbfadd96 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95f.c
index 9324ee105..4179ce402 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95i.c
index 074b51f4f..05961626d 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95u.c
index 732ed0cd7..4b6bdef57 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98f.c
index 212505b2d..badbc3ad6 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98i.c
index 0dcaf683d..bac916e2e 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98u.c
index c9f6e85af..d98b21bef 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9a.c
index 93ec6b0b3..4eef7102c 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9a.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9a.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9b.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9b.c
index 4a33231a6..097186dbc 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9b.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9b.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9c.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9c.c
index 5dbfd71ef..4d6642fc4 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9c.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9c.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1f.c
index ba451dcbb..6109eed0e 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1i.c
index ed671fd76..3a9619712 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1u.c
index b92265d1e..1378a04ef 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4f.c
index 1eb91a972..2d29f4fb5 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4i.c
index 8e42dc809..5e0feeda5 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4u.c
index 0c8a8bff8..da3badaa2 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7f.c
index bdb0e063e..44d47d204 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7i.c
index 2b95117de..187cdc679 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7u.c
index 1878e91ea..fc72d7009 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0f.c
index 66b68dbca..6e1c6aa87 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0i.c
index fa54d0a4c..d5529d378 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0u.c
index 84d4bb514..6a0b35e98 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3f.c
index 6e56ec599..a1a679075 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3i.c
index f379339e9..39e3ad080 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3u.c
index 51713d4b4..d0f05551d 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6f.c
index 379fdd8a1..74dc6c5d2 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6i.c
index 801cf7c37..1a0bae8ec 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6u.c
index 64500b9e8..27ba501e3 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9f.c
index f29fc40af..7781b9bc2 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9i.c
index 792a7712a..e261afd8f 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9u.c
index 411435a66..4e34ffa33 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2f.c
index e55158c4c..6f2b1a864 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2i.c
index db8fc19b6..1a7a28603 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2u.c
index ff27f635f..7e4ca40a3 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5f.c
index abbd803c7..49f329d16 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5i.c
index fb3596de3..3ae329960 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5u.c
index e26b3eb12..b27e285fb 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8f.c
index aa7532027..fd98f8bfd 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8i.c
index 85ec163b9..ea15ae387 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8u.c
index a87ef73b4..44fbcaf8f 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1f.c
index c156ca9f0..bf0cf06f2 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1f.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1f.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1i.c
index 4945e4285..1d37bb4ae 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1i.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1i.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1u.c
index 1d54db018..d3ba5ca63 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1u.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1u.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdcf.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdcf.c
index 6bf6905d1..0b68f2e52 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdcf.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdcf.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdci.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdci.c
index f43c5b675..29db6e798 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdci.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdci.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdcu.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdcu.c
index 5e96fe562..8b8012792 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdcu.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdcu.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf0.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf0.c
index 3b85dea27..508a170b6 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf0.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf0.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf1.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf1.c
index 32beca63e..1703a0b6e 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf1.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf1.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf4.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf4.c
index 1984eeddd..1aa788af7 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf4.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf4.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf5.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf5.c
index 22992055f..55e8214cb 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf5.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf5.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf6.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf6.c
index 67885f9d3..f93153039 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf6.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf6.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf9.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf9.c
index 01732afaf..c6e78db08 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf9.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf9.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/s_flash2.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/s_flash2.c
index 28efb5059..5489076f9 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/s_flash2.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/s_flash2.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/adaptors/r_sce_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/adaptors/r_sce_adapt.c
index 3f835f79f..b457d8eb9 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/adaptors/r_sce_adapt.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/adaptors/r_sce_adapt.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -167,6 +167,10 @@ fsp_err_t HW_SCE_GenerateOemKeyIndexPrivate (const sce_oem_key_type_t key_type,
         {
             ret = HW_SCE_GenerateAes256PlainKeyIndexSub(indata_key_type, install_key_ring_index, (uint32_t *) encrypted_provisioning_key, (uint32_t *) iv, (uint32_t *) encrypted_oem_key, key_index);
         }
+        else if (cmd == SCE_OEM_CMD_AES128_XTS)
+        {
+            ret = HW_SCE_GenerateAes128XtsKeyIndexSub(indata_key_type, install_key_ring_index, (uint32_t *) encrypted_provisioning_key, (uint32_t *) iv, (uint32_t *) encrypted_oem_key, key_index);
+        }
         else
         {
             ret = FSP_ERR_ASSERTION;
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p16.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p16.c
new file mode 100644
index 000000000..f0fe5a72a
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p16.c
@@ -0,0 +1,378 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_GenerateAes128XtsRandomKeyIndexSub(uint32_t *OutData_KeyIndex)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x00001601U;
+    SCE->REG_108H = 0x00000000U;
+    HW_SCE_func001(0xb29e5969U, 0x5e4703caU, 0x38fdb8abU, 0x00771ea8U);
+    SCE->REG_104H = 0x00000251U;
+    SCE->REG_A4H = 0x0020363cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x002036bcU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x002036bcU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x00060805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_104H = 0x00000151U;
+    SCE->REG_A4H = 0x0021340cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x000b0805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_A4H = 0x01000684U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    HW_SCE_func001(0x3afab9bfU, 0xa6aee36aU, 0x4d04eaf6U, 0x0d38f2f7U);
+    SCE->REG_E0H = 0x80040000U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_00H = 0x00008113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_E0H = 0x81040000U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_04H = 0x00000612U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[0] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[1] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[2] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[3] = SCE->REG_100H;
+    SCE->REG_A4H = 0x600c3a0dU;
+    SCE->REG_E0H = 0x81040000U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_00H = 0x00001813U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_A4H = 0x400c0a0cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x2d8daf39U);
+    HW_SCE_func001(0xfc1fc44aU, 0x4a43489fU, 0x458962c4U, 0x4173cbebU);
+    SCE->REG_104H = 0x00000251U;
+    SCE->REG_A4H = 0x0020363cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x002036bcU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x002036bcU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x00060805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_104H = 0x00000151U;
+    SCE->REG_A4H = 0x0021340cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x000b0805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_A4H = 0x01000684U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    HW_SCE_func001(0x864fd5aeU, 0x1d202218U, 0x82b56d96U, 0x6d09dc7dU);
+    SCE->REG_E0H = 0x80080000U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_00H = 0x00008113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_104H = 0x00000251U;
+    SCE->REG_A4H = 0x0020363cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x002036bcU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x002036bcU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x00060805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_104H = 0x00000151U;
+    SCE->REG_A4H = 0x0021340cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x000b0805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_A4H = 0x01000684U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_00H = 0x00008113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_func001(0x82750538U, 0x1c0ec684U, 0x1912ae7dU, 0xd870558cU);
+    SCE->REG_B0H = 0x00000100U;
+    SCE->REG_A4H = 0x42e486bfU;
+    SCE->REG_E0H = 0x81080000U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_00H = 0x00001823U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_104H = 0x00000351U;
+    SCE->REG_A4H = 0x400009cdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_100H = change_endian_long(0x00000002U);
+    SCE->REG_04H = 0x00000132U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[4] = SCE->REG_100H;
+    OutData_KeyIndex[5] = SCE->REG_100H;
+    OutData_KeyIndex[6] = SCE->REG_100H;
+    OutData_KeyIndex[7] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[8] = SCE->REG_100H;
+    OutData_KeyIndex[9] = SCE->REG_100H;
+    OutData_KeyIndex[10] = SCE->REG_100H;
+    OutData_KeyIndex[11] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[12] = SCE->REG_100H;
+    OutData_KeyIndex[13] = SCE->REG_100H;
+    OutData_KeyIndex[14] = SCE->REG_100H;
+    OutData_KeyIndex[15] = SCE->REG_100H;
+    HW_SCE_func003(0x775fa887U, 0xdf6828d9U, 0xcf49352aU, 0xaed42e2bU);
+    SCE->REG_1BCH = 0x00000040U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_18H_b.B12)
+    {
+        /* waiting */
+    }
+    return FSP_SUCCESS;
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p16.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p17.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p17.c
new file mode 100644
index 000000000..ab9f901ca
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p17.c
@@ -0,0 +1,533 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_GenerateAes256XtsRandomKeyIndexSub(uint32_t *OutData_KeyIndex)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x00001701U;
+    SCE->REG_108H = 0x00000000U;
+    HW_SCE_func001(0x069c2e54U, 0x6c7be636U, 0xea7c104dU, 0x7f271a3dU);
+    SCE->REG_104H = 0x00000251U;
+    SCE->REG_A4H = 0x0020363cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x002036bcU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x002036bcU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x00060805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_104H = 0x00000151U;
+    SCE->REG_A4H = 0x0021340cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x000b0805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_A4H = 0x01000684U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    HW_SCE_func001(0x9d17e379U, 0x19ae942dU, 0xe43e2d82U, 0x056f7c89U);
+    SCE->REG_E0H = 0x80040000U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_00H = 0x00008113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_E0H = 0x81040000U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_04H = 0x00000612U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[0] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[1] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[2] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[3] = SCE->REG_100H;
+    SCE->REG_A4H = 0x600c3a0dU;
+    SCE->REG_E0H = 0x81040000U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_00H = 0x00001813U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_A4H = 0x400c0a0cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x5737b943U);
+    HW_SCE_func001(0x790f4d3dU, 0x51b61d27U, 0xc27aa958U, 0x6085a7deU);
+    SCE->REG_104H = 0x00000251U;
+    SCE->REG_A4H = 0x0020363cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x002036bcU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x002036bcU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x00060805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_104H = 0x00000151U;
+    SCE->REG_A4H = 0x0021340cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x000b0805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_A4H = 0x01000684U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    HW_SCE_func001(0x6388f234U, 0xf210cb6bU, 0x92d58b26U, 0x602f9c57U);
+    SCE->REG_E0H = 0x80080000U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_00H = 0x00008113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_104H = 0x00000251U;
+    SCE->REG_A4H = 0x0020363cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x002036bcU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x002036bcU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x00060805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_104H = 0x00000151U;
+    SCE->REG_A4H = 0x0021340cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x000b0805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_A4H = 0x01000684U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_00H = 0x00008113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_func001(0xbf80940cU, 0x5ef1969fU, 0x36f3cc6eU, 0x2e50a692U);
+    SCE->REG_B0H = 0x00000100U;
+    SCE->REG_A4H = 0x42e486bfU;
+    SCE->REG_E0H = 0x81080000U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_00H = 0x00001823U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_04H = 0x00000122U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[4] = SCE->REG_100H;
+    OutData_KeyIndex[5] = SCE->REG_100H;
+    OutData_KeyIndex[6] = SCE->REG_100H;
+    OutData_KeyIndex[7] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[8] = SCE->REG_100H;
+    OutData_KeyIndex[9] = SCE->REG_100H;
+    OutData_KeyIndex[10] = SCE->REG_100H;
+    OutData_KeyIndex[11] = SCE->REG_100H;
+    HW_SCE_func001(0x189d504aU, 0x4e514a8fU, 0x38d652e2U, 0xab6638ceU);
+    SCE->REG_104H = 0x00000251U;
+    SCE->REG_A4H = 0x0020363cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x002036bcU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x002036bcU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x00060805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_104H = 0x00000151U;
+    SCE->REG_A4H = 0x0021340cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x000b0805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_A4H = 0x01000684U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    HW_SCE_func001(0xdd0ef7b5U, 0x1363967dU, 0x535a94e7U, 0x652489e7U);
+    SCE->REG_E0H = 0x80080000U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_00H = 0x00008113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_104H = 0x00000251U;
+    SCE->REG_A4H = 0x0020363cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x002036bcU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x002036bcU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x00060805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_104H = 0x00000151U;
+    SCE->REG_A4H = 0x0021340cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x000b0805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_A4H = 0x01000684U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_00H = 0x00008113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_func001(0x45765ba0U, 0xc0e4fef7U, 0x04ecae5aU, 0x30d8776bU);
+    SCE->REG_B0H = 0x00000100U;
+    SCE->REG_A4H = 0x40e486bfU;
+    SCE->REG_E0H = 0x81080000U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_00H = 0x00001823U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_104H = 0x00000351U;
+    SCE->REG_A4H = 0x400009cdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_100H = change_endian_long(0x00000004U);
+    SCE->REG_04H = 0x00000132U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[12] = SCE->REG_100H;
+    OutData_KeyIndex[13] = SCE->REG_100H;
+    OutData_KeyIndex[14] = SCE->REG_100H;
+    OutData_KeyIndex[15] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[16] = SCE->REG_100H;
+    OutData_KeyIndex[17] = SCE->REG_100H;
+    OutData_KeyIndex[18] = SCE->REG_100H;
+    OutData_KeyIndex[19] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[20] = SCE->REG_100H;
+    OutData_KeyIndex[21] = SCE->REG_100H;
+    OutData_KeyIndex[22] = SCE->REG_100H;
+    OutData_KeyIndex[23] = SCE->REG_100H;
+    HW_SCE_func003(0x2903686bU, 0xf771fbe0U, 0x4121546dU, 0xe67f54ceU);
+    SCE->REG_1BCH = 0x00000040U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_18H_b.B12)
+    {
+        /* waiting */
+    }
+    return FSP_SUCCESS;
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p17.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p87.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p87.c
new file mode 100644
index 000000000..413a7e265
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p87.c
@@ -0,0 +1,655 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_GenerateAes128XtsKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x00008701U;
+    SCE->REG_108H = 0x00000000U;
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x800100e0U;
+    SCE->REG_1D0H = 0x00000000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyType[0];
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x38000ce7U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00260000U;
+    HW_SCE_func001(0xd7f83c6aU, 0x40157d24U, 0x75b98bfcU, 0xd4e29e1dU);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        SCE->REG_104H = 0x00000068U;
+        SCE->REG_E0H = 0x80010000U;
+        SCE->REG_1D0H = 0x00000000U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(InData_SharedKeyIndex[0]);
+        SCE->REG_1D0H = 0x00000000U;
+        SCE->REG_ECH = 0x38008c00U;
+        SCE->REG_1D0H = 0x00000000U;
+        SCE->REG_ECH = 0xfffffff0U;
+        SCE->REG_1D0H = 0x00000000U;
+        SCE->REG_E0H = 0x00000080U;
+        SCE->REG_1CH = 0x00A60000U;
+        HW_SCE_func001(0x8f4899b2U, 0x42ce94beU, 0x1c929b57U, 0x65a9f00aU);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_func003(0x136515a8U, 0xcbfe3c1eU, 0xb5c04a26U, 0xed3d0d06U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            HW_SCE_func001(0xd31bc27eU, 0xfa51eb81U, 0x3afc1603U, 0x9dba13b3U);
+            OFS_ADR = InData_SharedKeyIndex[0]*8;
+            SCE->REG_A4H = 0x400c3a0cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x129e32e8U);
+            SCE->REG_A4H = 0x400c0a0cU;
+            SCE->REG_E0H = 0x81010000U;
+            SCE->REG_1D0H = 0x00000000U;
+            SCE->REG_00H = 0x00001807U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_A4H = 0x42fa063dU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = S_FLASH[OFS_ADR + 0];
+            SCE->REG_100H = S_FLASH[OFS_ADR + 1];
+            SCE->REG_100H = S_FLASH[OFS_ADR + 2];
+            SCE->REG_100H = S_FLASH[OFS_ADR + 3];
+            HW_SCE_func001(0xbb07333bU, 0x1ced036fU, 0x738c8fdbU, 0xd93c2a27U);
+            SCE->REG_A4H = 0x400006bdU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = S_FLASH[OFS_ADR+4 + 0];
+            SCE->REG_100H = S_FLASH[OFS_ADR+4 + 1];
+            SCE->REG_100H = S_FLASH[OFS_ADR+4 + 2];
+            SCE->REG_100H = S_FLASH[OFS_ADR+4 + 3];
+            SCE->REG_A4H = 0x00800c45U;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x0008680dU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_SessionKey[0];
+            SCE->REG_100H = InData_SessionKey[1];
+            SCE->REG_100H = InData_SessionKey[2];
+            SCE->REG_100H = InData_SessionKey[3];
+            HW_SCE_func001(0x6ca1d45dU, 0x8d854a62U, 0x4eab7c9bU, 0xea1f2c86U);
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x0009680dU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_SessionKey[4];
+            SCE->REG_100H = InData_SessionKey[5];
+            SCE->REG_100H = InData_SessionKey[6];
+            SCE->REG_100H = InData_SessionKey[7];
+            HW_SCE_func001(0xa357dd65U, 0x247297dfU, 0x314188b7U, 0x27b9b7ebU);
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x00040805U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_IV[0];
+            SCE->REG_100H = InData_IV[1];
+            SCE->REG_100H = InData_IV[2];
+            SCE->REG_100H = InData_IV[3];
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00050804U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_104H = 0x00000251U;
+            SCE->REG_A4H = 0x0020363cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_A4H = 0x002036bcU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_A4H = 0x002036bcU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_A4H = 0x00060805U;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_104H = 0x00000151U;
+            SCE->REG_A4H = 0x0021340cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_A4H = 0x000b0805U;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_A4H = 0x01000684U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            HW_SCE_func001(0xb8ae23cfU, 0xb652a9c5U, 0xfa69a92bU, 0xbfb7c58eU);
+            SCE->REG_E0H = 0x80040000U;
+            SCE->REG_1D0H = 0x00000000U;
+            SCE->REG_00H = 0x00008113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_A4H = 0x600c3a0dU;
+            SCE->REG_E0H = 0x81040000U;
+            SCE->REG_1D0H = 0x00000000U;
+            SCE->REG_00H = 0x00001813U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_A4H = 0x400c0a0cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x2d8daf39U);
+            SCE->REG_104H = 0x00000761U;
+            SCE->REG_B0H = 0x00000100U;
+            SCE->REG_A4H = 0x00d0c9afU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_InstData[0];
+            SCE->REG_100H = InData_InstData[1];
+            SCE->REG_100H = InData_InstData[2];
+            SCE->REG_100H = InData_InstData[3];
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_InstData[4];
+            SCE->REG_100H = InData_InstData[5];
+            SCE->REG_100H = InData_InstData[6];
+            SCE->REG_100H = InData_InstData[7];
+            SCE->REG_B0H = 0x00000100U;
+            SCE->REG_A4H = 0x43e086bfU;
+            SCE->REG_00H = 0x00001123U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_04H = 0x00000122U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_KeyIndex[4] = SCE->REG_100H;
+            OutData_KeyIndex[5] = SCE->REG_100H;
+            OutData_KeyIndex[6] = SCE->REG_100H;
+            OutData_KeyIndex[7] = SCE->REG_100H;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_KeyIndex[8] = SCE->REG_100H;
+            OutData_KeyIndex[9] = SCE->REG_100H;
+            OutData_KeyIndex[10] = SCE->REG_100H;
+            OutData_KeyIndex[11] = SCE->REG_100H;
+            HW_SCE_func001(0xdef8d302U, 0x0d5ca74bU, 0x5e4af557U, 0x89cf4091U);
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x01000684U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_A4H = 0x410009cdU;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_04H = 0x00000112U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_KeyIndex[12] = SCE->REG_100H;
+            OutData_KeyIndex[13] = SCE->REG_100H;
+            OutData_KeyIndex[14] = SCE->REG_100H;
+            OutData_KeyIndex[15] = SCE->REG_100H;
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x000049adU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_InstData[8];
+            SCE->REG_100H = InData_InstData[9];
+            SCE->REG_100H = InData_InstData[10];
+            SCE->REG_100H = InData_InstData[11];
+            SCE->REG_A4H = 0x00900c45U;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            HW_SCE_func001(0x1731adbfU, 0x54677ba1U, 0xc451786fU, 0xed119a73U);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_func003(0xc2e82a26U, 0x85101fbdU, 0x82b146b7U, 0x9a652619U);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_ERR_CRYPTO_SCE_FAIL;
+            }
+            else
+            {
+                HW_SCE_func001(0x3e70dfccU, 0x1d388ed8U, 0xc76f09b8U, 0x6740985fU);
+                SCE->REG_E0H = 0x81040000U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_04H = 0x00000612U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_KeyIndex[0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_KeyIndex[1] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_KeyIndex[2] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_KeyIndex[3] = SCE->REG_100H;
+                HW_SCE_func003(0x818b9bafU, 0x29f54d40U, 0x843998f7U, 0x382339d2U);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_SUCCESS;
+            }
+        }
+    }
+    else
+    {
+        HW_SCE_func001(0x74745802U, 0x94b5da2eU, 0xd156499bU, 0x7687a57fU);
+        SCE->REG_104H = 0x00000251U;
+        SCE->REG_A4H = 0x0020363cU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        SCE->REG_A4H = 0x002036bcU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        SCE->REG_A4H = 0x002036bcU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        SCE->REG_A4H = 0x00060805U;
+        SCE->REG_00H = 0x00001113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_104H = 0x00000151U;
+        SCE->REG_A4H = 0x0021340cU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        SCE->REG_A4H = 0x000b0805U;
+        SCE->REG_00H = 0x00001113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_A4H = 0x01000684U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        HW_SCE_func001(0xc23cde81U, 0x790a2f24U, 0xcc15c1eeU, 0xc9d475c2U);
+        SCE->REG_E0H = 0x80040000U;
+        SCE->REG_1D0H = 0x00000000U;
+        SCE->REG_00H = 0x00008113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_A4H = 0x600c3a0dU;
+        SCE->REG_E0H = 0x81040000U;
+        SCE->REG_1D0H = 0x00000000U;
+        SCE->REG_00H = 0x00001813U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_A4H = 0x400c0a0cU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x2d8daf39U);
+        SCE->REG_104H = 0x00000761U;
+        SCE->REG_B0H = 0x00000100U;
+        SCE->REG_A4H = 0x00008887U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_InstData[0];
+        SCE->REG_100H = InData_InstData[1];
+        SCE->REG_100H = InData_InstData[2];
+        SCE->REG_100H = InData_InstData[3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_InstData[4];
+        SCE->REG_100H = InData_InstData[5];
+        SCE->REG_100H = InData_InstData[6];
+        SCE->REG_100H = InData_InstData[7];
+        SCE->REG_B0H = 0x00000100U;
+        SCE->REG_A4H = 0x43e086bfU;
+        SCE->REG_00H = 0x00001123U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_04H = 0x00000122U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[4] = SCE->REG_100H;
+        OutData_KeyIndex[5] = SCE->REG_100H;
+        OutData_KeyIndex[6] = SCE->REG_100H;
+        OutData_KeyIndex[7] = SCE->REG_100H;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[8] = SCE->REG_100H;
+        OutData_KeyIndex[9] = SCE->REG_100H;
+        OutData_KeyIndex[10] = SCE->REG_100H;
+        OutData_KeyIndex[11] = SCE->REG_100H;
+        HW_SCE_func001(0x492cbe9eU, 0x43bd6eeaU, 0xc223afe4U, 0x4404e219U);
+        SCE->REG_104H = 0x00000051U;
+        SCE->REG_A4H = 0x01000684U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        SCE->REG_A4H = 0x410009cdU;
+        SCE->REG_00H = 0x00001113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_04H = 0x00000112U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[12] = SCE->REG_100H;
+        OutData_KeyIndex[13] = SCE->REG_100H;
+        OutData_KeyIndex[14] = SCE->REG_100H;
+        OutData_KeyIndex[15] = SCE->REG_100H;
+        HW_SCE_func001(0xb8808aa8U, 0x5ff991a3U, 0xab71689cU, 0x5af1efd0U);
+        SCE->REG_E0H = 0x81040000U;
+        SCE->REG_1D0H = 0x00000000U;
+        SCE->REG_04H = 0x00000612U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[0] = SCE->REG_100H;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[1] = SCE->REG_100H;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[2] = SCE->REG_100H;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[3] = SCE->REG_100H;
+        HW_SCE_func003(0x4a88f02eU, 0x3ba00792U, 0x7b0a0c43U, 0xebbadd2fU);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_SUCCESS;
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic_PlainKey/HW_SCEp_p87.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p88.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p88.c
new file mode 100644
index 000000000..363d8a080
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p88.c
@@ -0,0 +1,756 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_GenerateAes256XtsKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x00008801U;
+    SCE->REG_108H = 0x00000000U;
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x800100e0U;
+    SCE->REG_1D0H = 0x00000000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyType[0];
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x38000ce7U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00260000U;
+    HW_SCE_func001(0x7812c91cU, 0x79980cf1U, 0x1b960d51U, 0xcb864decU);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        SCE->REG_104H = 0x00000068U;
+        SCE->REG_E0H = 0x80010000U;
+        SCE->REG_1D0H = 0x00000000U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(InData_SharedKeyIndex[0]);
+        SCE->REG_1D0H = 0x00000000U;
+        SCE->REG_ECH = 0x38008c00U;
+        SCE->REG_1D0H = 0x00000000U;
+        SCE->REG_ECH = 0xfffffff0U;
+        SCE->REG_1D0H = 0x00000000U;
+        SCE->REG_E0H = 0x00000080U;
+        SCE->REG_1CH = 0x00A60000U;
+        HW_SCE_func001(0x669f2861U, 0x75c7ec15U, 0x001dc3ddU, 0xc7a034e6U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_func003(0x6f3ae3deU, 0xf5389f99U, 0xcbee3cecU, 0xa0ccfcb6U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            HW_SCE_func001(0x9f3e45b6U, 0xb4f7f68eU, 0xfd571442U, 0x07c6ffe0U);
+            OFS_ADR = InData_SharedKeyIndex[0]*8;
+            SCE->REG_A4H = 0x400c3a0cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x129e32e8U);
+            SCE->REG_A4H = 0x400c0a0cU;
+            SCE->REG_E0H = 0x81010000U;
+            SCE->REG_1D0H = 0x00000000U;
+            SCE->REG_00H = 0x00001807U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_A4H = 0x42fa063dU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = S_FLASH[OFS_ADR + 0];
+            SCE->REG_100H = S_FLASH[OFS_ADR + 1];
+            SCE->REG_100H = S_FLASH[OFS_ADR + 2];
+            SCE->REG_100H = S_FLASH[OFS_ADR + 3];
+            HW_SCE_func001(0x197d7aa2U, 0xfa44c456U, 0xbb96601aU, 0x851c6f4bU);
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x400006bdU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = S_FLASH[OFS_ADR+4 + 0];
+            SCE->REG_100H = S_FLASH[OFS_ADR+4 + 1];
+            SCE->REG_100H = S_FLASH[OFS_ADR+4 + 2];
+            SCE->REG_100H = S_FLASH[OFS_ADR+4 + 3];
+            SCE->REG_A4H = 0x00800c45U;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x0008680dU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_SessionKey[0];
+            SCE->REG_100H = InData_SessionKey[1];
+            SCE->REG_100H = InData_SessionKey[2];
+            SCE->REG_100H = InData_SessionKey[3];
+            HW_SCE_func001(0xea310249U, 0xf5388ac3U, 0xdfe8c8f7U, 0x077f20efU);
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x0009680dU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_SessionKey[4];
+            SCE->REG_100H = InData_SessionKey[5];
+            SCE->REG_100H = InData_SessionKey[6];
+            SCE->REG_100H = InData_SessionKey[7];
+            HW_SCE_func001(0x034d7d56U, 0x4a71eb34U, 0x87d1b778U, 0x4b764a8cU);
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x00040805U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_IV[0];
+            SCE->REG_100H = InData_IV[1];
+            SCE->REG_100H = InData_IV[2];
+            SCE->REG_100H = InData_IV[3];
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00050804U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_104H = 0x00000251U;
+            SCE->REG_A4H = 0x0020363cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_A4H = 0x002036bcU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_A4H = 0x002036bcU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_A4H = 0x00060805U;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_104H = 0x00000151U;
+            SCE->REG_A4H = 0x0021340cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_A4H = 0x000b0805U;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_A4H = 0x01000684U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            HW_SCE_func001(0xd3d49b98U, 0x4cd9e5bcU, 0x69760e3cU, 0x8b08fe4dU);
+            SCE->REG_E0H = 0x80040000U;
+            SCE->REG_1D0H = 0x00000000U;
+            SCE->REG_00H = 0x00008113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_A4H = 0x600c3a0dU;
+            SCE->REG_E0H = 0x81040000U;
+            SCE->REG_1D0H = 0x00000000U;
+            SCE->REG_00H = 0x00001813U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_A4H = 0x400c0a0cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x5737b943U);
+            SCE->REG_104H = 0x00000761U;
+            SCE->REG_B0H = 0x00000100U;
+            SCE->REG_A4H = 0x00d0c9afU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_InstData[0];
+            SCE->REG_100H = InData_InstData[1];
+            SCE->REG_100H = InData_InstData[2];
+            SCE->REG_100H = InData_InstData[3];
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_InstData[4];
+            SCE->REG_100H = InData_InstData[5];
+            SCE->REG_100H = InData_InstData[6];
+            SCE->REG_100H = InData_InstData[7];
+            SCE->REG_B0H = 0x00000100U;
+            SCE->REG_A4H = 0x43e086bfU;
+            SCE->REG_00H = 0x00001123U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_04H = 0x00000122U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_KeyIndex[4] = SCE->REG_100H;
+            OutData_KeyIndex[5] = SCE->REG_100H;
+            OutData_KeyIndex[6] = SCE->REG_100H;
+            OutData_KeyIndex[7] = SCE->REG_100H;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_KeyIndex[8] = SCE->REG_100H;
+            OutData_KeyIndex[9] = SCE->REG_100H;
+            OutData_KeyIndex[10] = SCE->REG_100H;
+            OutData_KeyIndex[11] = SCE->REG_100H;
+            HW_SCE_func001(0xc95d93f1U, 0x81640901U, 0x13797acfU, 0x1f506509U);
+            SCE->REG_104H = 0x00000761U;
+            SCE->REG_B0H = 0x00000100U;
+            SCE->REG_A4H = 0x00d0c9afU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_InstData[8];
+            SCE->REG_100H = InData_InstData[9];
+            SCE->REG_100H = InData_InstData[10];
+            SCE->REG_100H = InData_InstData[11];
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_InstData[12];
+            SCE->REG_100H = InData_InstData[13];
+            SCE->REG_100H = InData_InstData[14];
+            SCE->REG_100H = InData_InstData[15];
+            SCE->REG_B0H = 0x00000100U;
+            SCE->REG_A4H = 0x41e086bfU;
+            SCE->REG_00H = 0x00001123U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_04H = 0x00000122U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_KeyIndex[12] = SCE->REG_100H;
+            OutData_KeyIndex[13] = SCE->REG_100H;
+            OutData_KeyIndex[14] = SCE->REG_100H;
+            OutData_KeyIndex[15] = SCE->REG_100H;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_KeyIndex[16] = SCE->REG_100H;
+            OutData_KeyIndex[17] = SCE->REG_100H;
+            OutData_KeyIndex[18] = SCE->REG_100H;
+            OutData_KeyIndex[19] = SCE->REG_100H;
+            HW_SCE_func001(0x5a9e3914U, 0xe93b7da0U, 0x9e7f4192U, 0xbf5820e7U);
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x01000684U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_A4H = 0x410009cdU;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_04H = 0x00000112U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_KeyIndex[20] = SCE->REG_100H;
+            OutData_KeyIndex[21] = SCE->REG_100H;
+            OutData_KeyIndex[22] = SCE->REG_100H;
+            OutData_KeyIndex[23] = SCE->REG_100H;
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x000049adU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_InstData[16];
+            SCE->REG_100H = InData_InstData[17];
+            SCE->REG_100H = InData_InstData[18];
+            SCE->REG_100H = InData_InstData[19];
+            SCE->REG_A4H = 0x00900c45U;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            HW_SCE_func001(0xaa14be48U, 0x26570375U, 0xc1463945U, 0xdc306117U);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_func003(0xa897d2d1U, 0x09ec6213U, 0x3046618fU, 0xbdee25b8U);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_ERR_CRYPTO_SCE_FAIL;
+            }
+            else
+            {
+                HW_SCE_func001(0xc43071e6U, 0xe6cbab98U, 0xfca8a99fU, 0xa446a3efU);
+                SCE->REG_E0H = 0x81040000U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_04H = 0x00000612U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_KeyIndex[0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_KeyIndex[1] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_KeyIndex[2] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_KeyIndex[3] = SCE->REG_100H;
+                HW_SCE_func003(0x9fb367eeU, 0x4afaaffeU, 0xb17a0d06U, 0xa5063a19U);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_SUCCESS;
+            }
+        }
+    }
+    else
+    {
+        HW_SCE_func001(0xd3e961caU, 0xa9de9718U, 0xc91035e0U, 0x204ce292U);
+        SCE->REG_104H = 0x00000251U;
+        SCE->REG_A4H = 0x0020363cU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        SCE->REG_A4H = 0x002036bcU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        SCE->REG_A4H = 0x002036bcU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        SCE->REG_A4H = 0x00060805U;
+        SCE->REG_00H = 0x00001113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_104H = 0x00000151U;
+        SCE->REG_A4H = 0x0021340cU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        SCE->REG_A4H = 0x000b0805U;
+        SCE->REG_00H = 0x00001113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_A4H = 0x01000684U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        HW_SCE_func001(0xfd79cc47U, 0x06880f36U, 0xecc79dcaU, 0x85413a7cU);
+        SCE->REG_E0H = 0x80040000U;
+        SCE->REG_1D0H = 0x00000000U;
+        SCE->REG_00H = 0x00008113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_A4H = 0x600c3a0dU;
+        SCE->REG_E0H = 0x81040000U;
+        SCE->REG_1D0H = 0x00000000U;
+        SCE->REG_00H = 0x00001813U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_A4H = 0x400c0a0cU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x5737b943U);
+        SCE->REG_104H = 0x00000761U;
+        SCE->REG_B0H = 0x00000100U;
+        SCE->REG_A4H = 0x00008887U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_InstData[0];
+        SCE->REG_100H = InData_InstData[1];
+        SCE->REG_100H = InData_InstData[2];
+        SCE->REG_100H = InData_InstData[3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_InstData[4];
+        SCE->REG_100H = InData_InstData[5];
+        SCE->REG_100H = InData_InstData[6];
+        SCE->REG_100H = InData_InstData[7];
+        SCE->REG_B0H = 0x00000100U;
+        SCE->REG_A4H = 0x43e086bfU;
+        SCE->REG_00H = 0x00001123U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_04H = 0x00000122U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[4] = SCE->REG_100H;
+        OutData_KeyIndex[5] = SCE->REG_100H;
+        OutData_KeyIndex[6] = SCE->REG_100H;
+        OutData_KeyIndex[7] = SCE->REG_100H;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[8] = SCE->REG_100H;
+        OutData_KeyIndex[9] = SCE->REG_100H;
+        OutData_KeyIndex[10] = SCE->REG_100H;
+        OutData_KeyIndex[11] = SCE->REG_100H;
+        HW_SCE_func001(0xdf816f93U, 0x47525829U, 0x807f9f17U, 0x4c4d33f3U);
+        SCE->REG_104H = 0x00000761U;
+        SCE->REG_B0H = 0x00000100U;
+        SCE->REG_A4H = 0x00008887U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_InstData[8];
+        SCE->REG_100H = InData_InstData[9];
+        SCE->REG_100H = InData_InstData[10];
+        SCE->REG_100H = InData_InstData[11];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_InstData[12];
+        SCE->REG_100H = InData_InstData[13];
+        SCE->REG_100H = InData_InstData[14];
+        SCE->REG_100H = InData_InstData[15];
+        SCE->REG_B0H = 0x00000100U;
+        SCE->REG_A4H = 0x41e086bfU;
+        SCE->REG_00H = 0x00001123U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_04H = 0x00000122U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[12] = SCE->REG_100H;
+        OutData_KeyIndex[13] = SCE->REG_100H;
+        OutData_KeyIndex[14] = SCE->REG_100H;
+        OutData_KeyIndex[15] = SCE->REG_100H;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[16] = SCE->REG_100H;
+        OutData_KeyIndex[17] = SCE->REG_100H;
+        OutData_KeyIndex[18] = SCE->REG_100H;
+        OutData_KeyIndex[19] = SCE->REG_100H;
+        HW_SCE_func001(0x8ba9f501U, 0x099be69dU, 0xf35ba183U, 0x9d0c67a3U);
+        SCE->REG_104H = 0x00000051U;
+        SCE->REG_A4H = 0x01000684U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        SCE->REG_A4H = 0x410009cdU;
+        SCE->REG_00H = 0x00001113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_04H = 0x00000112U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[20] = SCE->REG_100H;
+        OutData_KeyIndex[21] = SCE->REG_100H;
+        OutData_KeyIndex[22] = SCE->REG_100H;
+        OutData_KeyIndex[23] = SCE->REG_100H;
+        HW_SCE_func001(0xa5dc0026U, 0xc1de13a4U, 0x4b1ac6a0U, 0xdc937aa6U);
+        SCE->REG_E0H = 0x81040000U;
+        SCE->REG_1D0H = 0x00000000U;
+        SCE->REG_04H = 0x00000612U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[0] = SCE->REG_100H;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[1] = SCE->REG_100H;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[2] = SCE->REG_100H;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[3] = SCE->REG_100H;
+        HW_SCE_func003(0x37122ea1U, 0x54c0dea5U, 0x9aea8f74U, 0x8c4af148U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_SUCCESS;
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic_PlainKey/HW_SCEp_p88.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb3f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb3f.c
new file mode 100644
index 000000000..5d2ec5abd
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb3f.c
@@ -0,0 +1,515 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes128XtsEncryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x80010000U;
+    SCE->REG_1D0H = 0x00000000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_TextBitLen[0];
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00003420U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00076821U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00026c21U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x000008c6U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x38008c00U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x0000007fU;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00020020U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x3420a800U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x1000d0c0U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x2000a820U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00000004U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x38000cc6U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00A60000U;
+    HW_SCE_func001(0xada7a2a7U, 0x3c06c766U, 0xcee96d8cU, 0xbb06f9afU);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        SCE->REG_1CH = 0x002d0000U;
+        HW_SCE_func001(0x20c968f6U, 0x7ca4814cU, 0x7273f13aU, 0x569a4247U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            SCE->REG_00H = 0x00000113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            HW_SCE_func002(0xef49cf67U, 0x79b08e3fU, 0x0f25d451U, 0x920ba087U);
+        }
+        else
+        {
+            HW_SCE_func002(0x16103be5U, 0x18f5fa4cU, 0xd1e03853U, 0xaea3c1f5U);
+        }
+        HW_SCE_func003(0x4ddf8916U, 0x048eb860U, 0xc424455bU, 0xaabb9316U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        HW_SCE_func001(0x79fc81b5U, 0x059e6c78U, 0xf0460d58U, 0x5a190490U);
+        SCE->REG_E0H = 0x81010020U;
+        SCE->REG_1D0H = 0x00000000U;
+        SCE->REG_04H = 0x00000606U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        S_RAM[0] = change_endian_long(SCE->REG_100H);
+        HW_SCE_func001(0xc195e91dU, 0x6f1bf5e5U, 0x09713592U, 0xce791577U);
+        SCE->REG_104H = 0x000000b1U;
+        SCE->REG_B0H = 0x00000020U;
+        SCE->REG_A4H = 0x00008daeU;
+        SCE->REG_04H = 0x0000c100U;
+        iLoop = 0;
+            if(S_RAM[0] >= 4) 
+        {
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_Text[0];
+            SCE->REG_100H = InData_Text[1];
+            SCE->REG_100H = InData_Text[2];
+            SCE->REG_100H = InData_Text[3];
+            for (iLoop = 4; iLoop < S_RAM[0]; iLoop = iLoop + 4)
+            {
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+            }
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+        }
+        HW_SCE_func206();
+        HW_SCE_func001(0x6ccff8f0U, 0x6a9b3933U, 0x4a1440c8U, 0x4c71a2e3U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            SCE->REG_1CH = 0x002d0000U;
+            HW_SCE_func001(0xd0bae410U, 0x4d1061c6U, 0xf751cda8U, 0x94c38a99U);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                SCE->REG_00H = 0x00000113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                HW_SCE_func002(0xa4668cddU, 0xe7c37c21U, 0x705c7557U, 0xa8f88eb4U);
+            }
+            else
+            {
+                HW_SCE_func002(0x4f1c669eU, 0x21ea31d5U, 0x1e96f4c1U, 0x3ab4e6b8U);
+            }
+            HW_SCE_func003(0x38f4dbbaU, 0x93ad1091U, 0x47cf57e0U, 0x7f78ca80U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            SCE->REG_ECH = 0x38008c00U;
+            SCE->REG_1D0H = 0x00000000U;
+            SCE->REG_ECH = 0x0000007fU;
+            SCE->REG_1D0H = 0x00000000U;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00A60000U;
+            HW_SCE_func001(0x211f4540U, 0xf8091d27U, 0xc3bb854cU, 0x0b847558U);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_func001(0xd9e0ddd6U, 0x4e7f16a9U, 0xa5de5dacU, 0xc5d2ef87U);
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_B0H = 0x00000020U;
+                SCE->REG_A4H = 0x00008dadU;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_E0H = 0x80840006U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_00H = 0x00008113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_ECH = 0x0000b460U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_104H = 0x00000368U;
+                SCE->REG_E0H = 0x80840003U;
+                SCE->REG_1D0H = 0x00000000U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+4 + 0];
+                SCE->REG_1D0H = 0x00000000U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+5 + 0];
+                SCE->REG_1D0H = 0x00000000U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+6 + 0];
+                SCE->REG_1D0H = 0x00000000U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+7 + 0];
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003440U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00008c40U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000b480U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0xffffffffU;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00004402U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00007484U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x000034a0U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x000368a5U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00008ca0U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000000cU;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x000024c5U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00002465U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003843U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00001484U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000c44U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00001041U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003c43U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003440U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00008c40U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000007fU;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x38008c40U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x1000a440U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000020U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000b420U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00002822U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00056821U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003401U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_E0H = 0x81010020U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_04H = 0x00000606U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                S_RAM[0] = change_endian_long(SCE->REG_100H);
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x0000a4c0U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x0000a460U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00003846U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00003c43U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00003020U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    HW_SCE_func002(0x3dee1511U, 0xde3b88feU, 0x2e4c5e9aU, 0x2105aeb3U);
+                }
+                HW_SCE_func001(0x16223a72U, 0x70c9e73eU, 0x621cf19dU, 0xe6a1dabfU);
+                SCE->REG_ECH = 0x38000c21U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000b460U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_B0H = 0x00000020U;
+                SCE->REG_A4H = 0x00008dadU;
+                SCE->REG_E0H = 0x81840003U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_00H = 0x00001813U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_04H = 0x00000112U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop + 0] = SCE->REG_100H;
+                OutData_Text[iLoop + 1] = SCE->REG_100H;
+                OutData_Text[iLoop + 2] = SCE->REG_100H;
+                OutData_Text[iLoop + 3] = SCE->REG_100H;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x000024c5U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003c26U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000842U;
+                SCE->REG_1D0H = 0x00000000U;
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x0000a4c0U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00003c46U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00003000U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    HW_SCE_func002(0x5fd415a4U, 0x053385b5U, 0x1d6211daU, 0xb850974aU);
+                }
+                HW_SCE_func001(0x309fc174U, 0x83ac880bU, 0xf4b95fc3U, 0x5bb8b140U);
+                SCE->REG_ECH = 0x38000c00U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_E0H = 0x81840006U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_04H = 0x00000612U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+4 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+5 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+6 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+7 + 0] = SCE->REG_100H;
+                HW_SCE_func002(0x35e1960dU, 0xd45960b2U, 0xe6dadf8cU, 0x914fbfa7U);
+            }
+            HW_SCE_func003(0xc5d51ffbU, 0xa4de3279U, 0x9411dddbU, 0xf093895eU);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_SUCCESS;
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pb3f.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb3i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb3i.c
new file mode 100644
index 000000000..2beb4de85
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb3i.c
@@ -0,0 +1,174 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes128XtsEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x0000b301U;
+    SCE->REG_108H = 0x00000000U;
+    HW_SCE_func001(0x7a76264dU, 0x29f884a3U, 0x2bdcd3a2U, 0xf9e03db0U);
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x600c3a0dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[0];
+    SCE->REG_100H = InData_KeyIndex[1];
+    SCE->REG_100H = InData_KeyIndex[2];
+    SCE->REG_100H = InData_KeyIndex[3];
+    SCE->REG_A4H = 0x400c0a0cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x2d8daf39U);
+    SCE->REG_A4H = 0x42f8063dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[4];
+    SCE->REG_100H = InData_KeyIndex[5];
+    SCE->REG_100H = InData_KeyIndex[6];
+    SCE->REG_100H = InData_KeyIndex[7];
+    HW_SCE_func001(0x77640d25U, 0x14318a53U, 0x0668c7ebU, 0x022e5cbdU);
+    SCE->REG_A4H = 0x40f9063dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[8];
+    SCE->REG_100H = InData_KeyIndex[9];
+    SCE->REG_100H = InData_KeyIndex[10];
+    SCE->REG_100H = InData_KeyIndex[11];
+    SCE->REG_A4H = 0x400006bdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[12];
+    SCE->REG_100H = InData_KeyIndex[13];
+    SCE->REG_100H = InData_KeyIndex[14];
+    SCE->REG_100H = InData_KeyIndex[15];
+    SCE->REG_A4H = 0x00900c45U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_func001(0x1e0b1d16U, 0xd9250389U, 0x73afb6aeU, 0xaf08cd95U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_func003(0x9bbda832U, 0x404b9385U, 0x2c45350fU, 0xb3ec64b1U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+    }
+    else
+    {
+        SCE->REG_104H = 0x00000361U;
+        SCE->REG_A4H = 0x0004180dU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_IV[0];
+        SCE->REG_100H = InData_IV[1];
+        SCE->REG_100H = InData_IV[2];
+        SCE->REG_100H = InData_IV[3];
+        return FSP_SUCCESS;
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pb3i.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb3u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb3u.c
new file mode 100644
index 000000000..d812216c9
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb3u.c
@@ -0,0 +1,127 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes128XtsEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_func001(0x9a9fd229U, 0xb2b401a8U, 0x0717ce6bU, 0xe6b432aeU);
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_B0H = 0x00000020U;
+    SCE->REG_A4H = 0x00008daeU;
+    SCE->REG_04H = 0x0000c100U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_Text[0];
+    SCE->REG_100H = InData_Text[1];
+    SCE->REG_100H = InData_Text[2];
+    SCE->REG_100H = InData_Text[3];
+    for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    }
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    HW_SCE_func206();
+    HW_SCE_func002(0xd9167d5bU, 0x078a27eeU, 0xcfa43850U, 0x244fa44aU);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pb3u.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb6f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb6f.c
new file mode 100644
index 000000000..79c040198
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb6f.c
@@ -0,0 +1,540 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes128XtsDecryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x80010000U;
+    SCE->REG_1D0H = 0x00000000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_TextBitLen[0];
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00003420U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00076821U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00026c21U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x000008c6U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x38008c00U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x0000007fU;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00020020U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x3420a800U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x1000d0c0U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x2000a820U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00000004U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x38000cc6U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00A60000U;
+    HW_SCE_func001(0x04a1a3adU, 0xb7ae1bb2U, 0x96919b7aU, 0xae7bca18U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        SCE->REG_1CH = 0x002d0000U;
+        HW_SCE_func001(0xd8e7b9ceU, 0x8e48f4d4U, 0x0cf65781U, 0xcbc06fdfU);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            SCE->REG_00H = 0x00000113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            HW_SCE_func002(0x494c4865U, 0x975f1863U, 0x1dee465bU, 0x2fe166ecU);
+        }
+        else
+        {
+            HW_SCE_func002(0xd2c2702fU, 0xa95166c0U, 0xb41110eeU, 0x06c2a737U);
+        }
+        HW_SCE_func003(0x64e39d0eU, 0xbaaacb50U, 0x5002b105U, 0x99165728U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        HW_SCE_func001(0x78f0a60aU, 0x5719b14bU, 0xa4385167U, 0x9195283fU);
+        SCE->REG_E0H = 0x81010020U;
+        SCE->REG_1D0H = 0x00000000U;
+        SCE->REG_04H = 0x00000606U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        S_RAM[0] = change_endian_long(SCE->REG_100H);
+        HW_SCE_func001(0x621d84bbU, 0xe8c8553fU, 0x8ec52b15U, 0xa850847eU);
+        SCE->REG_104H = 0x000000b1U;
+        SCE->REG_B0H = 0x00000020U;
+        SCE->REG_A4H = 0x0000cdaeU;
+        SCE->REG_04H = 0x0000c100U;
+        iLoop = 0;
+            if(S_RAM[0] >= 4) 
+        {
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_Text[0];
+            SCE->REG_100H = InData_Text[1];
+            SCE->REG_100H = InData_Text[2];
+            SCE->REG_100H = InData_Text[3];
+            for (iLoop = 4; iLoop < S_RAM[0]; iLoop = iLoop + 4)
+            {
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+            }
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+        }
+        HW_SCE_func206();
+        HW_SCE_func001(0x6af85827U, 0x986f2951U, 0xcd494103U, 0x4f332451U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            SCE->REG_1CH = 0x002d0000U;
+            HW_SCE_func001(0x1a02ab9eU, 0xa489ea6dU, 0x2e2cd1d5U, 0xbcb840cdU);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                SCE->REG_00H = 0x00000113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                HW_SCE_func002(0x1abad95eU, 0x2a5721e1U, 0x209eafb9U, 0x182c4fa7U);
+            }
+            else
+            {
+                HW_SCE_func002(0x7dc66de0U, 0x53ae55dbU, 0x2160bba0U, 0x7d5c0f1eU);
+            }
+            HW_SCE_func003(0x9a611b88U, 0x9eb9266eU, 0xbadf9271U, 0x5c17d597U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            SCE->REG_ECH = 0x38008c00U;
+            SCE->REG_1D0H = 0x00000000U;
+            SCE->REG_ECH = 0x0000007fU;
+            SCE->REG_1D0H = 0x00000000U;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00A60000U;
+            HW_SCE_func001(0x1369afc1U, 0xe520ca03U, 0x9c86ba8aU, 0x58d9062bU);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_func001(0x56512253U, 0x591af8aaU, 0x317d00e3U, 0x9b083202U);
+                SCE->REG_104H = 0x00000051U;
+                SCE->REG_A4H = 0x00050604U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = change_endian_long(0x00000000U);
+                SCE->REG_104H = 0x00000051U;
+                SCE->REG_B0H = 0x00000020U;
+                SCE->REG_A4H = 0x0000cd2cU;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = change_endian_long(0x00000000U);
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_B0H = 0x00000020U;
+                SCE->REG_A4H = 0x0000cdadU;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_E0H = 0x80840006U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_00H = 0x00008113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_ECH = 0x0000b460U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_104H = 0x00000368U;
+                SCE->REG_E0H = 0x80840003U;
+                SCE->REG_1D0H = 0x00000000U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+4 + 0];
+                SCE->REG_1D0H = 0x00000000U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+5 + 0];
+                SCE->REG_1D0H = 0x00000000U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+6 + 0];
+                SCE->REG_1D0H = 0x00000000U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+7 + 0];
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003440U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00008c40U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000b480U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0xffffffffU;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00004402U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00007484U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x000034a0U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x000368a5U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00008ca0U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000000cU;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x000024c5U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00002465U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003843U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00001484U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000c44U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00001041U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003c43U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003440U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00008c40U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000007fU;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x38008c40U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x1000a440U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000020U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000b420U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00002822U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00056821U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003401U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_E0H = 0x81010020U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_04H = 0x00000606U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                S_RAM[0] = change_endian_long(SCE->REG_100H);
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x0000a4c0U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x0000a460U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00003846U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00003c43U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00003020U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    HW_SCE_func002(0xd677f598U, 0xd2e09b40U, 0x039486f9U, 0xb04463deU);
+                }
+                HW_SCE_func001(0xea307e71U, 0x053d7261U, 0x15a2c000U, 0xd5f6b634U);
+                SCE->REG_ECH = 0x38000c21U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_104H = 0x00000051U;
+                SCE->REG_A4H = 0x00040644U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = change_endian_long(0x00000000U);
+                SCE->REG_ECH = 0x0000b460U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_B0H = 0x00000020U;
+                SCE->REG_A4H = 0x0000cdadU;
+                SCE->REG_E0H = 0x81840003U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_00H = 0x00001813U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_04H = 0x00000112U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop + 0] = SCE->REG_100H;
+                OutData_Text[iLoop + 1] = SCE->REG_100H;
+                OutData_Text[iLoop + 2] = SCE->REG_100H;
+                OutData_Text[iLoop + 3] = SCE->REG_100H;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x000024c5U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003c26U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000842U;
+                SCE->REG_1D0H = 0x00000000U;
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x0000a4c0U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00003c46U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00003000U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    HW_SCE_func002(0x790cf255U, 0xd2a06165U, 0xc0da2c52U, 0x9db4aba4U);
+                }
+                HW_SCE_func001(0xdcf8b5a3U, 0xc198b5caU, 0x4bc15577U, 0xb0cd47f1U);
+                SCE->REG_ECH = 0x38000c00U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_E0H = 0x81840006U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_04H = 0x00000612U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+4 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+5 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+6 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+7 + 0] = SCE->REG_100H;
+                HW_SCE_func002(0xf55d04efU, 0x65c1ba06U, 0x46edae79U, 0x5919b454U);
+            }
+            HW_SCE_func003(0x28a11de3U, 0x4dc4fddaU, 0xfdada47dU, 0x3f895a0eU);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_SUCCESS;
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pb6f.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb6i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb6i.c
new file mode 100644
index 000000000..9d035aa94
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb6i.c
@@ -0,0 +1,175 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes128XtsDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x0000b601U;
+    SCE->REG_108H = 0x00000000U;
+    HW_SCE_func001(0xc360df21U, 0x85ca3bf7U, 0x776419f7U, 0x1483725dU);
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x600c3a0dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[0];
+    SCE->REG_100H = InData_KeyIndex[1];
+    SCE->REG_100H = InData_KeyIndex[2];
+    SCE->REG_100H = InData_KeyIndex[3];
+    SCE->REG_A4H = 0x400c0a0cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x2d8daf39U);
+    SCE->REG_A4H = 0x42f8063dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[4];
+    SCE->REG_100H = InData_KeyIndex[5];
+    SCE->REG_100H = InData_KeyIndex[6];
+    SCE->REG_100H = InData_KeyIndex[7];
+    HW_SCE_func001(0xce05b262U, 0xd9c2e222U, 0x3ea8f17fU, 0xde299ffcU);
+    SCE->REG_A4H = 0x40f9063dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[8];
+    SCE->REG_100H = InData_KeyIndex[9];
+    SCE->REG_100H = InData_KeyIndex[10];
+    SCE->REG_100H = InData_KeyIndex[11];
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x400006bdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[12];
+    SCE->REG_100H = InData_KeyIndex[13];
+    SCE->REG_100H = InData_KeyIndex[14];
+    SCE->REG_100H = InData_KeyIndex[15];
+    SCE->REG_A4H = 0x00900c45U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_func001(0x9f6891d5U, 0x73922d45U, 0xa03c6f7cU, 0xc62f3bbfU);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_func003(0xf04c8dd7U, 0x6b239c27U, 0x570de152U, 0x2380be58U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+    }
+    else
+    {
+        SCE->REG_104H = 0x00000361U;
+        SCE->REG_A4H = 0x0004180dU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_IV[0];
+        SCE->REG_100H = InData_IV[1];
+        SCE->REG_100H = InData_IV[2];
+        SCE->REG_100H = InData_IV[3];
+        return FSP_SUCCESS;
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pb6i.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb6u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb6u.c
new file mode 100644
index 000000000..ce118730c
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb6u.c
@@ -0,0 +1,127 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes128XtsDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_func001(0x4c778cd9U, 0xd8ba587aU, 0x9db74827U, 0xcf1851c6U);
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_B0H = 0x00000020U;
+    SCE->REG_A4H = 0x0000cdaeU;
+    SCE->REG_04H = 0x0000c100U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_Text[0];
+    SCE->REG_100H = InData_Text[1];
+    SCE->REG_100H = InData_Text[2];
+    SCE->REG_100H = InData_Text[3];
+    for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    }
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    HW_SCE_func206();
+    HW_SCE_func002(0xb10ae393U, 0x0f9f09cfU, 0xe84ecfa1U, 0x0b7c1be7U);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pb6u.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb9f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb9f.c
new file mode 100644
index 000000000..ddbd8f0c4
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb9f.c
@@ -0,0 +1,542 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes256XtsEncryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x80010000U;
+    SCE->REG_1D0H = 0x00000000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_TextBitLen[0];
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00003420U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00076821U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00026c21U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x000008c6U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x38008c00U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x0000007fU;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00020020U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x3420a800U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x1000d0c0U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x2000a820U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00000004U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x38000cc6U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00A60000U;
+    HW_SCE_func001(0xe3d7cd5fU, 0xfe4d305bU, 0x10ca5e65U, 0xf453caccU);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        SCE->REG_1CH = 0x002d0000U;
+        HW_SCE_func001(0x99091361U, 0x1488f34aU, 0x30a16f63U, 0xcec8b940U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            SCE->REG_00H = 0x00000113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            HW_SCE_func002(0x3566a77fU, 0x3f7e8a14U, 0x94e39633U, 0x192b2e5dU);
+        }
+        else
+        {
+            HW_SCE_func002(0x531b7461U, 0xdac9105fU, 0x50a1d923U, 0xb0c66d32U);
+        }
+        HW_SCE_func001(0x20f0967fU, 0x5bccc8dbU, 0x9828ed15U, 0x5260c813U);
+        SCE->REG_104H = 0x00000051U;
+        SCE->REG_A4H = 0x010b0644U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        HW_SCE_func003(0x825432f1U, 0x95184069U, 0x2388bdf5U, 0xd5ed4928U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        HW_SCE_func001(0x79902488U, 0x90ac2eafU, 0x55780219U, 0x37904342U);
+        SCE->REG_E0H = 0x81010020U;
+        SCE->REG_1D0H = 0x00000000U;
+        SCE->REG_04H = 0x00000606U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        S_RAM[0] = change_endian_long(SCE->REG_100H);
+        HW_SCE_func001(0x4975b4acU, 0x8226d9ddU, 0x491df082U, 0x853efa8bU);
+        SCE->REG_104H = 0x000000b1U;
+        SCE->REG_B0H = 0x40000020U;
+        SCE->REG_A4H = 0x00008daeU;
+        SCE->REG_04H = 0x0000c100U;
+        iLoop = 0;
+            if(S_RAM[0] >= 4) 
+        {
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_Text[0];
+            SCE->REG_100H = InData_Text[1];
+            SCE->REG_100H = InData_Text[2];
+            SCE->REG_100H = InData_Text[3];
+            for (iLoop = 4; iLoop < S_RAM[0]; iLoop = iLoop + 4)
+            {
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+            }
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+        }
+        HW_SCE_func206();
+        HW_SCE_func001(0x26d5c2bcU, 0xffda44beU, 0x1ca188bcU, 0xd045c96fU);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            SCE->REG_1CH = 0x002d0000U;
+            HW_SCE_func001(0x573c4303U, 0x29ee731eU, 0xfa9f417dU, 0xeec5611aU);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                SCE->REG_00H = 0x00000113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                HW_SCE_func002(0x5c93420eU, 0x625fa6d5U, 0xd92b5d00U, 0x5488c446U);
+            }
+            else
+            {
+                HW_SCE_func002(0x7f90ca60U, 0x4da9a2ebU, 0x9d1f39bbU, 0x95cdb4b2U);
+            }
+            HW_SCE_func001(0xe59e2853U, 0x9d9e56f0U, 0xfbafdeeaU, 0x35934401U);
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x010b0644U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            HW_SCE_func003(0xbe820c8fU, 0x2c8b1dc6U, 0xec1af11dU, 0xda87d583U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            SCE->REG_ECH = 0x38008c00U;
+            SCE->REG_1D0H = 0x00000000U;
+            SCE->REG_ECH = 0x0000007fU;
+            SCE->REG_1D0H = 0x00000000U;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00A60000U;
+            HW_SCE_func001(0x7915accdU, 0x7ab62473U, 0x775f9db6U, 0x45dc8e36U);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_func001(0x4de076b9U, 0xb10ac7b9U, 0x4e697c78U, 0x4a57cbe5U);
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_B0H = 0x40000020U;
+                SCE->REG_A4H = 0x00008dadU;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_E0H = 0x80840006U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_00H = 0x00008113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_ECH = 0x0000b460U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_104H = 0x00000368U;
+                SCE->REG_E0H = 0x80840003U;
+                SCE->REG_1D0H = 0x00000000U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+4 + 0];
+                SCE->REG_1D0H = 0x00000000U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+5 + 0];
+                SCE->REG_1D0H = 0x00000000U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+6 + 0];
+                SCE->REG_1D0H = 0x00000000U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+7 + 0];
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003440U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00008c40U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000b480U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0xffffffffU;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00004402U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00007484U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x000034a0U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x000368a5U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00008ca0U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000000cU;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x000024c5U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00002465U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003843U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00001484U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000c44U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00001041U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003c43U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003440U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00008c40U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000007fU;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x38008c40U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x1000a440U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000020U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000b420U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00002822U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00056821U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003401U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_E0H = 0x81010020U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_04H = 0x00000606U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                S_RAM[0] = change_endian_long(SCE->REG_100H);
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x0000a4c0U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x0000a460U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00003846U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00003c43U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00003020U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    HW_SCE_func002(0xa62c1099U, 0x3d72cd2bU, 0xc31de1feU, 0x4bee9f13U);
+                }
+                HW_SCE_func001(0xb02d577bU, 0x9fd9e562U, 0xb281ff0cU, 0x997d8400U);
+                SCE->REG_ECH = 0x38000c21U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000b460U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_B0H = 0x40000020U;
+                SCE->REG_A4H = 0x00008dadU;
+                SCE->REG_E0H = 0x81840003U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_00H = 0x00001813U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_04H = 0x00000112U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop + 0] = SCE->REG_100H;
+                OutData_Text[iLoop + 1] = SCE->REG_100H;
+                OutData_Text[iLoop + 2] = SCE->REG_100H;
+                OutData_Text[iLoop + 3] = SCE->REG_100H;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x000024c5U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003c26U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000842U;
+                SCE->REG_1D0H = 0x00000000U;
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x0000a4c0U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00003c46U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00003000U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    HW_SCE_func002(0xac8ef2b1U, 0xc2fe571cU, 0x1a5adf4eU, 0xf27a67b2U);
+                }
+                HW_SCE_func001(0xe8576321U, 0x972e49f3U, 0x05af01efU, 0x19f4699bU);
+                SCE->REG_ECH = 0x38000c00U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_E0H = 0x81840006U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_04H = 0x00000612U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+4 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+5 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+6 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+7 + 0] = SCE->REG_100H;
+                HW_SCE_func002(0x8a7b089fU, 0xd21e6af5U, 0x28dce7b2U, 0xb264a678U);
+            }
+            HW_SCE_func001(0xfb595513U, 0x993b1bfbU, 0xb229e17fU, 0x7f506d0bU);
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x010b0644U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            HW_SCE_func003(0xdea4c319U, 0x1870122dU, 0x567cba9dU, 0x24e3e4d0U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_SUCCESS;
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pb9f.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb9i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb9i.c
new file mode 100644
index 000000000..03e97f3ef
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb9i.c
@@ -0,0 +1,244 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes256XtsEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x0000b901U;
+    SCE->REG_108H = 0x00000000U;
+    SCE->REG_104H = 0x00000251U;
+    SCE->REG_A4H = 0x0020363cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x0020363cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x002036bcU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_104H = 0x00000051U;
+    SCE->REG_A4H = 0x0021340cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x00070805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_func001(0xe2c6c619U, 0xe6583873U, 0x8bec795cU, 0x8b3ed753U);
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x600c3a0dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[0];
+    SCE->REG_100H = InData_KeyIndex[1];
+    SCE->REG_100H = InData_KeyIndex[2];
+    SCE->REG_100H = InData_KeyIndex[3];
+    SCE->REG_A4H = 0x400c0a0cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x5737b943U);
+    SCE->REG_A4H = 0x42f8063dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[4];
+    SCE->REG_100H = InData_KeyIndex[5];
+    SCE->REG_100H = InData_KeyIndex[6];
+    SCE->REG_100H = InData_KeyIndex[7];
+    HW_SCE_func001(0x0b6f6163U, 0x6a372131U, 0x9cc9fb41U, 0x03f0f273U);
+    SCE->REG_A4H = 0x40f9063dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[8];
+    SCE->REG_100H = InData_KeyIndex[9];
+    SCE->REG_100H = InData_KeyIndex[10];
+    SCE->REG_100H = InData_KeyIndex[11];
+    HW_SCE_func001(0xb3a9613eU, 0xf5926368U, 0x46ef4880U, 0xe69b245aU);
+    SCE->REG_A4H = 0x40fa063dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[12];
+    SCE->REG_100H = InData_KeyIndex[13];
+    SCE->REG_100H = InData_KeyIndex[14];
+    SCE->REG_100H = InData_KeyIndex[15];
+    HW_SCE_func001(0x0981c6feU, 0xfd6734dfU, 0xa303e9b9U, 0x8da82124U);
+    SCE->REG_A4H = 0x40fb063dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[16];
+    SCE->REG_100H = InData_KeyIndex[17];
+    SCE->REG_100H = InData_KeyIndex[18];
+    SCE->REG_100H = InData_KeyIndex[19];
+    SCE->REG_A4H = 0x400006bdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[20];
+    SCE->REG_100H = InData_KeyIndex[21];
+    SCE->REG_100H = InData_KeyIndex[22];
+    SCE->REG_100H = InData_KeyIndex[23];
+    SCE->REG_A4H = 0x00900c45U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_func001(0x445ad96dU, 0xb3cff680U, 0xfff2d822U, 0xb76b3a88U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_func001(0xac230876U, 0x4d9f7fdfU, 0x7d2718bfU, 0xe8ecca0aU);
+        SCE->REG_104H = 0x00000051U;
+        SCE->REG_A4H = 0x010b0644U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        HW_SCE_func003(0x05522c3cU, 0x4834f34aU, 0x2b23b2dfU, 0x66fc1ca9U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+    }
+    else
+    {
+        SCE->REG_104H = 0x00000361U;
+        SCE->REG_B0H = 0x40000000U;
+        SCE->REG_A4H = 0x0004a80dU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_IV[0];
+        SCE->REG_100H = InData_IV[1];
+        SCE->REG_100H = InData_IV[2];
+        SCE->REG_100H = InData_IV[3];
+        return FSP_SUCCESS;
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pb9i.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb9u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb9u.c
new file mode 100644
index 000000000..26f21d6b6
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb9u.c
@@ -0,0 +1,127 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes256XtsEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_func001(0x651deaa6U, 0xb808f13aU, 0xf28b2e1bU, 0x90941ffcU);
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_B0H = 0x40000020U;
+    SCE->REG_A4H = 0x00008daeU;
+    SCE->REG_04H = 0x0000c100U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_Text[0];
+    SCE->REG_100H = InData_Text[1];
+    SCE->REG_100H = InData_Text[2];
+    SCE->REG_100H = InData_Text[3];
+    for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    }
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    HW_SCE_func206();
+    HW_SCE_func002(0x73f0fcbeU, 0x69bf1ccfU, 0xad57d2e1U, 0x66e4e4b5U);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pb9u.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pc2f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pc2f.c
new file mode 100644
index 000000000..a4aa19372
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pc2f.c
@@ -0,0 +1,567 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes256XtsDecryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x80010000U;
+    SCE->REG_1D0H = 0x00000000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_TextBitLen[0];
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00003420U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00076821U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00026c21U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x000008c6U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x38008c00U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x0000007fU;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00020020U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x3420a800U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x1000d0c0U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x2000a820U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00000004U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_ECH = 0x38000cc6U;
+    SCE->REG_1D0H = 0x00000000U;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00A60000U;
+    HW_SCE_func001(0xce9accb2U, 0xcdcc26e2U, 0xd91fa9edU, 0xab15a636U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        SCE->REG_1CH = 0x002d0000U;
+        HW_SCE_func001(0x22df0fb7U, 0xc2a78deaU, 0xc78df098U, 0x2fd15e14U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            SCE->REG_00H = 0x00000113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            HW_SCE_func002(0x1fd615f9U, 0xf33df947U, 0xb9b40855U, 0x36adf76fU);
+        }
+        else
+        {
+            HW_SCE_func002(0x4dccb1e1U, 0xbd1f45faU, 0xc5c33d20U, 0x400b0df4U);
+        }
+        HW_SCE_func001(0xec71656cU, 0xa352f213U, 0xd2c9122aU, 0x46093feaU);
+        SCE->REG_104H = 0x00000051U;
+        SCE->REG_A4H = 0x010b0644U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        HW_SCE_func003(0xaaf565b6U, 0xa14023eeU, 0x0a9561e1U, 0x10c72774U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        HW_SCE_func001(0x5ae5c7a0U, 0xd1c87403U, 0xf1bb78f0U, 0x4ae3820fU);
+        SCE->REG_E0H = 0x81010020U;
+        SCE->REG_1D0H = 0x00000000U;
+        SCE->REG_04H = 0x00000606U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        S_RAM[0] = change_endian_long(SCE->REG_100H);
+        HW_SCE_func001(0xa6de294cU, 0x6e2d19e0U, 0xf8f5bd40U, 0x1918fceeU);
+        SCE->REG_104H = 0x000000b1U;
+        SCE->REG_B0H = 0x40000020U;
+        SCE->REG_A4H = 0x0000cdaeU;
+        SCE->REG_04H = 0x0000c100U;
+        iLoop = 0;
+            if(S_RAM[0] >= 4) 
+        {
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_Text[0];
+            SCE->REG_100H = InData_Text[1];
+            SCE->REG_100H = InData_Text[2];
+            SCE->REG_100H = InData_Text[3];
+            for (iLoop = 4; iLoop < S_RAM[0]; iLoop = iLoop + 4)
+            {
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+            }
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+        }
+        HW_SCE_func206();
+        HW_SCE_func001(0x59ac3e9fU, 0x34ae6ff2U, 0x5ce7e8cdU, 0xb3cd0f1dU);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            SCE->REG_1CH = 0x002d0000U;
+            HW_SCE_func001(0x95e388c1U, 0x8c85dcebU, 0xe27a815dU, 0x5a60e683U);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                SCE->REG_00H = 0x00000113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                HW_SCE_func002(0xf277f06dU, 0x03318561U, 0x1900dfeeU, 0xf2f91da3U);
+            }
+            else
+            {
+                HW_SCE_func002(0x3e25783cU, 0x8d1906f6U, 0xae010de0U, 0xde84e80dU);
+            }
+            HW_SCE_func001(0x2c7d9a60U, 0x1f750dd1U, 0xd01a6b39U, 0x26c7bceaU);
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x010b0644U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            HW_SCE_func003(0x5007b925U, 0xb5010564U, 0x130075acU, 0x5dd666ffU);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            SCE->REG_ECH = 0x38008c00U;
+            SCE->REG_1D0H = 0x00000000U;
+            SCE->REG_ECH = 0x0000007fU;
+            SCE->REG_1D0H = 0x00000000U;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00A60000U;
+            HW_SCE_func001(0x3a5ffb0eU, 0x7107479aU, 0x75504e7cU, 0x351e41bbU);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_func001(0xb7b3056eU, 0xe3c02d5bU, 0x7d96a9ecU, 0xe1f61ea8U);
+                SCE->REG_104H = 0x00000051U;
+                SCE->REG_A4H = 0x00050604U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = change_endian_long(0x00000000U);
+                SCE->REG_104H = 0x00000051U;
+                SCE->REG_B0H = 0x40000020U;
+                SCE->REG_A4H = 0x0000cd2cU;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = change_endian_long(0x00000000U);
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_B0H = 0x40000020U;
+                SCE->REG_A4H = 0x0000cdadU;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_E0H = 0x80840006U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_00H = 0x00008113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_ECH = 0x0000b460U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_104H = 0x00000368U;
+                SCE->REG_E0H = 0x80840003U;
+                SCE->REG_1D0H = 0x00000000U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+4 + 0];
+                SCE->REG_1D0H = 0x00000000U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+5 + 0];
+                SCE->REG_1D0H = 0x00000000U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+6 + 0];
+                SCE->REG_1D0H = 0x00000000U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+7 + 0];
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003440U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00008c40U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000b480U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0xffffffffU;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00004402U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00007484U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x000034a0U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x000368a5U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00008ca0U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000000cU;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x000024c5U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00002465U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003843U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00001484U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000c44U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00001041U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003c43U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003440U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00008c40U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000007fU;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x38008c40U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x1000a440U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000020U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x0000b420U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00002822U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00056821U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003401U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_E0H = 0x81010020U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_04H = 0x00000606U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                S_RAM[0] = change_endian_long(SCE->REG_100H);
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x0000a4c0U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x0000a460U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00003846U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00003c43U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00003020U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    HW_SCE_func002(0xcb48c703U, 0xee2dc584U, 0xe2638516U, 0xb9d2ef96U);
+                }
+                HW_SCE_func001(0x721b4e10U, 0xf5d4dc8eU, 0x2083fee8U, 0xc4f55818U);
+                SCE->REG_ECH = 0x38000c21U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_104H = 0x00000051U;
+                SCE->REG_A4H = 0x00040644U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = change_endian_long(0x00000000U);
+                SCE->REG_ECH = 0x0000b460U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_B0H = 0x40000020U;
+                SCE->REG_A4H = 0x0000cdadU;
+                SCE->REG_E0H = 0x81840003U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_00H = 0x00001813U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_04H = 0x00000112U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop + 0] = SCE->REG_100H;
+                OutData_Text[iLoop + 1] = SCE->REG_100H;
+                OutData_Text[iLoop + 2] = SCE->REG_100H;
+                OutData_Text[iLoop + 3] = SCE->REG_100H;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x000024c5U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00003c26U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x00000842U;
+                SCE->REG_1D0H = 0x00000000U;
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x0000a4c0U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00003c46U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    SCE->REG_ECH = 0x00003000U;
+                    SCE->REG_1D0H = 0x00000000U;
+                    HW_SCE_func002(0x470dbb5eU, 0x77fcf121U, 0x82a42003U, 0xf494beccU);
+                }
+                HW_SCE_func001(0x0b847bfdU, 0xc4c48c6eU, 0xad20a312U, 0x6e3e81c5U);
+                SCE->REG_ECH = 0x38000c00U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_E0H = 0x81840006U;
+                SCE->REG_1D0H = 0x00000000U;
+                SCE->REG_04H = 0x00000612U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+4 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+5 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+6 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+7 + 0] = SCE->REG_100H;
+                HW_SCE_func002(0x8da3c818U, 0x56364771U, 0xee0081e9U, 0x3815eb4cU);
+            }
+            HW_SCE_func001(0x40750ce0U, 0x171fd58bU, 0x60aac93eU, 0xdabce961U);
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x010b0644U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            HW_SCE_func003(0x98cfbfeeU, 0x4c6ffa00U, 0x97f1a35fU, 0x24761a97U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_SUCCESS;
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pc2f.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pc2i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pc2i.c
new file mode 100644
index 000000000..508d03762
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pc2i.c
@@ -0,0 +1,244 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes256XtsDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x0000c201U;
+    SCE->REG_108H = 0x00000000U;
+    SCE->REG_104H = 0x00000251U;
+    SCE->REG_A4H = 0x0020363cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x0020363cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x002036bcU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_104H = 0x00000051U;
+    SCE->REG_A4H = 0x0021340cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x00070805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_func001(0x1da03fa7U, 0xee7b2471U, 0x35d6996bU, 0x88d327f2U);
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x600c3a0dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[0];
+    SCE->REG_100H = InData_KeyIndex[1];
+    SCE->REG_100H = InData_KeyIndex[2];
+    SCE->REG_100H = InData_KeyIndex[3];
+    SCE->REG_A4H = 0x400c0a0cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x5737b943U);
+    SCE->REG_A4H = 0x42f8063dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[4];
+    SCE->REG_100H = InData_KeyIndex[5];
+    SCE->REG_100H = InData_KeyIndex[6];
+    SCE->REG_100H = InData_KeyIndex[7];
+    HW_SCE_func001(0x570167b9U, 0x56ee8455U, 0x769701b3U, 0xef7bfda2U);
+    SCE->REG_A4H = 0x40f9063dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[8];
+    SCE->REG_100H = InData_KeyIndex[9];
+    SCE->REG_100H = InData_KeyIndex[10];
+    SCE->REG_100H = InData_KeyIndex[11];
+    HW_SCE_func001(0x8f2e5af0U, 0x883a208aU, 0x4236c1cbU, 0xe1dc5831U);
+    SCE->REG_A4H = 0x40fa063dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[12];
+    SCE->REG_100H = InData_KeyIndex[13];
+    SCE->REG_100H = InData_KeyIndex[14];
+    SCE->REG_100H = InData_KeyIndex[15];
+    HW_SCE_func001(0x28420221U, 0xcb9471dbU, 0x52476198U, 0x43584bd9U);
+    SCE->REG_A4H = 0x40fb063dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[16];
+    SCE->REG_100H = InData_KeyIndex[17];
+    SCE->REG_100H = InData_KeyIndex[18];
+    SCE->REG_100H = InData_KeyIndex[19];
+    SCE->REG_A4H = 0x400006bdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[20];
+    SCE->REG_100H = InData_KeyIndex[21];
+    SCE->REG_100H = InData_KeyIndex[22];
+    SCE->REG_100H = InData_KeyIndex[23];
+    SCE->REG_A4H = 0x00900c45U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_func001(0x8547eb4eU, 0xd0b2ccc4U, 0x0ce3d227U, 0xf3e5d8d6U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_func001(0x014c27a6U, 0xf19098cbU, 0x92029b0fU, 0xd5d99b1eU);
+        SCE->REG_104H = 0x00000051U;
+        SCE->REG_A4H = 0x010b0644U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        HW_SCE_func003(0xf1ca0383U, 0xd6c2c942U, 0x41b4415fU, 0x3f9246b2U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+    }
+    else
+    {
+        SCE->REG_104H = 0x00000361U;
+        SCE->REG_B0H = 0x40000000U;
+        SCE->REG_A4H = 0x0004a80dU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_IV[0];
+        SCE->REG_100H = InData_IV[1];
+        SCE->REG_100H = InData_IV[2];
+        SCE->REG_100H = InData_IV[3];
+        return FSP_SUCCESS;
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pc2i.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pc2u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pc2u.c
new file mode 100644
index 000000000..0f9d32bef
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pc2u.c
@@ -0,0 +1,127 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes256XtsDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_func001(0xa0abc7cbU, 0xf959aa62U, 0x6e4bfd28U, 0xf5f70337U);
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_B0H = 0x40000020U;
+    SCE->REG_A4H = 0x0000cdaeU;
+    SCE->REG_04H = 0x0000c100U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_Text[0];
+    SCE->REG_100H = InData_Text[1];
+    SCE->REG_100H = InData_Text[2];
+    SCE->REG_100H = InData_Text[3];
+    for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    }
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    HW_SCE_func206();
+    HW_SCE_func002(0xa0cca9a3U, 0x7c4fc59fU, 0x7303fb1dU, 0xf8a2e023U);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pc2u.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/SCE_module.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/SCE_module.h
index 783f493af..e3ab6278d 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/SCE_module.h
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/SCE_module.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/hw_sce_ra_private.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/hw_sce_ra_private.h
index e28c00976..bfae0e79b 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/hw_sce_ra_private.h
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/hw_sce_ra_private.h
@@ -62,11 +62,11 @@
  #define SIZE_AES_256BIT_KEYLEN_BYTES_WRAPPED    ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 8)
  #define SIZE_AES_256BIT_KEYLEN_WORDS_WRAPPED    ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 32)
 
- #define SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED     (416)
+ #define SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED     (512)
  #define SIZE_AES_XTS_128BIT_KEYLEN_BYTES_WRAPPED    ((SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED) / 8)
  #define SIZE_AES_XTS_128BIT_KEYLEN_WORDS_WRAPPED    ((SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED) / 32)
 
- #define SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED     (672)
+ #define SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED     (768)
  #define SIZE_AES_XTS_256BIT_KEYLEN_BYTES_WRAPPED    ((SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED) / 8)
  #define SIZE_AES_XTS_256BIT_KEYLEN_WORDS_WRAPPED    ((SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED) / 32)
 
@@ -196,6 +196,10 @@ fsp_err_t HW_SCE_GenerateAes128PlainKeyIndexSub(uint32_t *InData_KeyType, uint32
         uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex);
 fsp_err_t HW_SCE_GenerateAes256PlainKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey,
         uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex);
+fsp_err_t HW_SCE_GenerateAes128XtsKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex,
+         uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex);
+fsp_err_t HW_SCE_GenerateAes256XtsKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, 
+        uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex);
 fsp_err_t HW_SCE_GenerateAes128RandomKeyIndexSub(uint32_t *OutData_KeyIndex);
 fsp_err_t HW_SCE_GenerateAes256RandomKeyIndexSub(uint32_t *OutData_KeyIndex);
 fsp_err_t HW_SCE_GenerateRandomNumberSub(uint32_t *OutData_Text);
@@ -220,6 +224,21 @@ fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub(const uint32_t *InData_KeyType, con
 void         HW_SCE_Aes256EncryptDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT);
 fsp_err_t HW_SCE_Aes256EncryptDecryptFinalSub(void);
 
+fsp_err_t HW_SCE_GenerateAes128XtsRandomKeyIndexSub(uint32_t *OutData_KeyIndex);
+fsp_err_t HW_SCE_GenerateAes256XtsRandomKeyIndexSub(uint32_t *OutData_KeyIndex);
+fsp_err_t HW_SCE_Aes128XtsEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV);
+void HW_SCE_Aes128XtsEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT);
+fsp_err_t HW_SCE_Aes128XtsEncryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text);
+fsp_err_t HW_SCE_Aes128XtsDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV);
+void HW_SCE_Aes128XtsDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT);
+fsp_err_t HW_SCE_Aes128XtsDecryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text);
+fsp_err_t HW_SCE_Aes256XtsEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV);
+void HW_SCE_Aes256XtsEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT);
+fsp_err_t HW_SCE_Aes256XtsEncryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text);
+fsp_err_t HW_SCE_Aes256XtsDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV);
+void HW_SCE_Aes256XtsDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT);
+fsp_err_t HW_SCE_Aes256XtsDecryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text);
+
 fsp_err_t HW_SCE_Ghash(uint32_t *InData_HV, uint32_t *InData_IV, uint32_t *InData_Text, uint32_t *OutData_DataT,
         uint32_t MAX_CNT);
 
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/adaptors/r_sce_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/adaptors/r_sce_adapt.c
index 10f887515..3cb60133e 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/adaptors/r_sce_adapt.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/adaptors/r_sce_adapt.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_p16.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_p16.c
new file mode 100644
index 000000000..c96235da2
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_p16.c
@@ -0,0 +1,238 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_GenerateAes128XtsRandomKeyIndexSub(uint32_t *OutData_KeyIndex)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x00001601U;
+    SCE->REG_108H = 0x00000000U;
+    HW_SCE_func100(0x952bf9a2U, 0x7d944591U, 0x4540c78aU, 0x3f943db2U);
+    HW_SCE_func103();
+    SCE->REG_104H = 0x00000051U;
+    SCE->REG_A4H = 0x01000e84U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_E0H = 0x80010000U;
+    SCE->REG_00H = 0x00008107U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_00H = 0x0000010fU;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_ECH = 0x000008c6U;
+    SCE->REG_ECH = 0x00003c06U;
+    SCE->REG_ECH = 0x000034a0U;
+    SCE->REG_104H = 0x00000058U;
+    SCE->REG_E0H = 0x800100c0U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000016U);
+    HW_SCE_func101(0x90881eafU, 0xdf5a5296U, 0x5b9581e7U, 0x1717d1bbU);
+    HW_SCE_func043();
+    HW_SCE_func100(0xd8e36327U, 0x36bc2c7aU, 0x91c4b9ceU, 0x2d1f6197U);
+    SCE->REG_ECH = 0x0000b4a0U;
+    SCE->REG_ECH = 0x00000008U;
+    HW_SCE_func044();
+    HW_SCE_func100(0x206f5183U, 0x114cf563U, 0xbf025f07U, 0x4bd2e6ebU);
+    SCE->REG_ECH = 0x0000b4c0U;
+    SCE->REG_ECH = 0x00000004U;
+    SCE->REG_ECH = 0x00003ce6U;
+    HW_SCE_func103();
+    HW_SCE_func100(0x1d9ee0b4U, 0x4ef10f7cU, 0xb14e599dU, 0x7a03bb6dU);
+    SCE->REG_104H = 0x00000051U;
+    SCE->REG_A4H = 0x01000e84U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_E0H = 0x80080000U;
+    SCE->REG_00H = 0x00008113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_func103();
+    HW_SCE_func100(0x6b425726U, 0x2720e12fU, 0x38905d5eU, 0x713e38cdU);
+    SCE->REG_104H = 0x00000051U;
+    SCE->REG_A4H = 0x01000e84U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_00H = 0x00008113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_B0H = 0x00000100U;
+    SCE->REG_A4H = 0x02e4a6bfU;
+    SCE->REG_E0H = 0x81080000U;
+    SCE->REG_00H = 0x00001823U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_104H = 0x00000351U;
+    SCE->REG_A4H = 0x000029cdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_100H = change_endian_long(0x00000002U);
+    SCE->REG_04H = 0x00000132U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[1] = SCE->REG_100H;
+    OutData_KeyIndex[2] = SCE->REG_100H;
+    OutData_KeyIndex[3] = SCE->REG_100H;
+    OutData_KeyIndex[4] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[5] = SCE->REG_100H;
+    OutData_KeyIndex[6] = SCE->REG_100H;
+    OutData_KeyIndex[7] = SCE->REG_100H;
+    OutData_KeyIndex[8] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[9] = SCE->REG_100H;
+    OutData_KeyIndex[10] = SCE->REG_100H;
+    OutData_KeyIndex[11] = SCE->REG_100H;
+    OutData_KeyIndex[12] = SCE->REG_100H;
+    HW_SCE_func100(0xbd467f76U, 0x3f35e107U, 0x20bf8581U, 0x99a919e3U);
+    SCE->REG_ECH = 0x0000b4c0U;
+    SCE->REG_ECH = 0x00000004U;
+    SCE->REG_ECH = 0x000038e6U;
+    SCE->REG_ECH = 0x000008c6U;
+    SCE->REG_E0H = 0x81810006U;
+    SCE->REG_04H = 0x00000606U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[0] = SCE->REG_100H;
+    HW_SCE_func102(0x266283fdU, 0x5bccc515U, 0x136c0c19U, 0x73faaa19U);
+    SCE->REG_1BCH = 0x00000040U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_18H_b.B12)
+    {
+        /* waiting */
+    }
+    return FSP_SUCCESS;
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/RA6T_Boot/200821/HW_SCE/Cryptographic/HW_SCE_p16.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_p17.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_p17.c
new file mode 100644
index 000000000..0ab893795
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_p17.c
@@ -0,0 +1,303 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_GenerateAes256XtsRandomKeyIndexSub(uint32_t *OutData_KeyIndex)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x00001701U;
+    SCE->REG_108H = 0x00000000U;
+    HW_SCE_func100(0x053cc9e9U, 0xe296f52bU, 0xe360339aU, 0x5fdbec82U);
+    HW_SCE_func103();
+    SCE->REG_104H = 0x00000051U;
+    SCE->REG_A4H = 0x01000e84U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_E0H = 0x80010000U;
+    SCE->REG_00H = 0x00008107U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_00H = 0x0000010fU;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_ECH = 0x000008c6U;
+    SCE->REG_ECH = 0x00003c06U;
+    SCE->REG_ECH = 0x000034a0U;
+    SCE->REG_104H = 0x00000058U;
+    SCE->REG_E0H = 0x800100c0U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000017U);
+    HW_SCE_func101(0x29cf48c0U, 0x1280ed7dU, 0xcade3e9dU, 0xa222d261U);
+    HW_SCE_func043();
+    HW_SCE_func100(0x13ab8662U, 0x484f5d4fU, 0xe1e89fb9U, 0x8c972bf9U);
+    SCE->REG_ECH = 0x0000b4a0U;
+    SCE->REG_ECH = 0x00000009U;
+    HW_SCE_func044();
+    HW_SCE_func100(0x36979b23U, 0xc87584e4U, 0x3f2c0feeU, 0xbe55ea78U);
+    SCE->REG_ECH = 0x0000b4c0U;
+    SCE->REG_ECH = 0x00000004U;
+    SCE->REG_ECH = 0x00003ce6U;
+    HW_SCE_func103();
+    HW_SCE_func100(0xc3a1e3f8U, 0x9a5ca673U, 0x0694c594U, 0x0710b0dbU);
+    SCE->REG_104H = 0x00000051U;
+    SCE->REG_A4H = 0x01000e84U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_E0H = 0x80080000U;
+    SCE->REG_00H = 0x00008113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_func103();
+    HW_SCE_func100(0x0566aee6U, 0x173280ecU, 0xb272b4f0U, 0x0e949171U);
+    SCE->REG_104H = 0x00000051U;
+    SCE->REG_A4H = 0x01000e84U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_00H = 0x00008113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_B0H = 0x00000100U;
+    SCE->REG_A4H = 0x02e4a6bfU;
+    SCE->REG_E0H = 0x81080000U;
+    SCE->REG_00H = 0x00001823U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_04H = 0x00000122U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[1] = SCE->REG_100H;
+    OutData_KeyIndex[2] = SCE->REG_100H;
+    OutData_KeyIndex[3] = SCE->REG_100H;
+    OutData_KeyIndex[4] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[5] = SCE->REG_100H;
+    OutData_KeyIndex[6] = SCE->REG_100H;
+    OutData_KeyIndex[7] = SCE->REG_100H;
+    OutData_KeyIndex[8] = SCE->REG_100H;
+    HW_SCE_func100(0x06d34346U, 0x0a9bc90fU, 0x85d8199dU, 0x4ea6bf1eU);
+    HW_SCE_func103();
+    HW_SCE_func100(0x577fb671U, 0x27b6e79dU, 0x0eb99917U, 0x0121ca69U);
+    SCE->REG_104H = 0x00000051U;
+    SCE->REG_A4H = 0x01000e84U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_E0H = 0x80080000U;
+    SCE->REG_00H = 0x00008113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_func103();
+    HW_SCE_func100(0xf267ad32U, 0xb288cb13U, 0x30200584U, 0xfb4a7929U);
+    SCE->REG_104H = 0x00000051U;
+    SCE->REG_A4H = 0x01000e84U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_00H = 0x00008113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_B0H = 0x00000100U;
+    SCE->REG_A4H = 0x00e4a6bfU;
+    SCE->REG_E0H = 0x81080000U;
+    SCE->REG_00H = 0x00001823U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_104H = 0x00000351U;
+    SCE->REG_A4H = 0x000029cdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_100H = change_endian_long(0x00000004U);
+    SCE->REG_04H = 0x00000132U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[9] = SCE->REG_100H;
+    OutData_KeyIndex[10] = SCE->REG_100H;
+    OutData_KeyIndex[11] = SCE->REG_100H;
+    OutData_KeyIndex[12] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[13] = SCE->REG_100H;
+    OutData_KeyIndex[14] = SCE->REG_100H;
+    OutData_KeyIndex[15] = SCE->REG_100H;
+    OutData_KeyIndex[16] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[17] = SCE->REG_100H;
+    OutData_KeyIndex[18] = SCE->REG_100H;
+    OutData_KeyIndex[19] = SCE->REG_100H;
+    OutData_KeyIndex[20] = SCE->REG_100H;
+    HW_SCE_func100(0x5288b937U, 0x93531447U, 0x318e445bU, 0xeb8adcf9U);
+    SCE->REG_ECH = 0x0000b4c0U;
+    SCE->REG_ECH = 0x00000004U;
+    SCE->REG_ECH = 0x000038e6U;
+    SCE->REG_ECH = 0x000008c6U;
+    SCE->REG_E0H = 0x81810006U;
+    SCE->REG_04H = 0x00000606U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[0] = SCE->REG_100H;
+    HW_SCE_func102(0xc9b7f81eU, 0x93979747U, 0xcc20f4e7U, 0x249c0b53U);
+    SCE->REG_1BCH = 0x00000040U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_18H_b.B12)
+    {
+        /* waiting */
+    }
+    return FSP_SUCCESS;
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/RA6T_Boot/200821/HW_SCE/Cryptographic/HW_SCE_p17.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb3f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb3f.c
new file mode 100644
index 000000000..ee2cd53d1
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb3f.c
@@ -0,0 +1,408 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes128XtsEncryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x80010000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_TextBitLen[0];
+    SCE->REG_ECH = 0x00003420U;
+    SCE->REG_ECH = 0x00076821U;
+    SCE->REG_ECH = 0x00026c21U;
+    SCE->REG_ECH = 0x000008c6U;
+    SCE->REG_ECH = 0x38008c00U;
+    SCE->REG_ECH = 0x0000007fU;
+    SCE->REG_ECH = 0x00020020U;
+    SCE->REG_ECH = 0x3420a800U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_ECH = 0x1000d0c0U;
+    SCE->REG_ECH = 0x2000a820U;
+    SCE->REG_ECH = 0x00000004U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_ECH = 0x38000cc6U;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00A60000U;
+    HW_SCE_func100(0x160b8f35U, 0x710be7f0U, 0x52211b5bU, 0x6fd6b3fbU);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_func102(0x107868a6U, 0x2f5ca5ddU, 0xec2ff32eU, 0x2186eeb9U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        HW_SCE_func100(0x566ae4fdU, 0x752b3084U, 0x4542839cU, 0x90a2db50U);
+        SCE->REG_E0H = 0x81010020U;
+        SCE->REG_04H = 0x00000606U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        S_RAM[0] = change_endian_long(SCE->REG_100H);
+        HW_SCE_func100(0x9fb5482cU, 0xebd141bbU, 0xc2c7970eU, 0x3a318ed6U);
+        SCE->REG_104H = 0x000000b1U;
+        SCE->REG_B0H = 0x00000020U;
+        SCE->REG_A4H = 0x00008daeU;
+        SCE->REG_04H = 0x0000c100U;
+        iLoop = 0;
+            if(S_RAM[0] >= 4) 
+        {
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_Text[0];
+            SCE->REG_100H = InData_Text[1];
+            SCE->REG_100H = InData_Text[2];
+            SCE->REG_100H = InData_Text[3];
+            for (iLoop = 4; iLoop < S_RAM[0]; iLoop = iLoop + 4)
+            {
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+            }
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+        }
+        HW_SCE_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+        HW_SCE_func100(0x5c25ce0dU, 0x3a771266U, 0x28f2cd5dU, 0xd989d883U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_func102(0x401f80deU, 0x4b1ffee3U, 0x0ca4153dU, 0x9b9c36cbU);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            SCE->REG_ECH = 0x38008c00U;
+            SCE->REG_ECH = 0x0000007fU;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00A60000U;
+            HW_SCE_func100(0x46969484U, 0xae43ef35U, 0x8cae67daU, 0xc9f62e7fU);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_func100(0x594d6a02U, 0x78e1481aU, 0xf8c3ef2aU, 0x3267eac9U);
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_B0H = 0x00000020U;
+                SCE->REG_A4H = 0x00008dadU;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_E0H = 0x80840006U;
+                SCE->REG_00H = 0x00008113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_ECH = 0x0000b460U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_104H = 0x00000368U;
+                SCE->REG_E0H = 0x80840003U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+4 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+5 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+6 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+7 + 0];
+                SCE->REG_ECH = 0x00003440U;
+                SCE->REG_ECH = 0x00008c40U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x0000b480U;
+                SCE->REG_ECH = 0xffffffffU;
+                SCE->REG_ECH = 0x00004402U;
+                SCE->REG_ECH = 0x00007484U;
+                SCE->REG_ECH = 0x000034a0U;
+                SCE->REG_ECH = 0x000368a5U;
+                SCE->REG_ECH = 0x00008ca0U;
+                SCE->REG_ECH = 0x0000000cU;
+                SCE->REG_ECH = 0x000024c5U;
+                SCE->REG_ECH = 0x00002465U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_ECH = 0x00003843U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_ECH = 0x00001484U;
+                SCE->REG_ECH = 0x00000c44U;
+                SCE->REG_ECH = 0x00001041U;
+                SCE->REG_ECH = 0x00003c43U;
+                SCE->REG_ECH = 0x00003440U;
+                SCE->REG_ECH = 0x00008c40U;
+                SCE->REG_ECH = 0x0000007fU;
+                SCE->REG_ECH = 0x38008c40U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x1000a440U;
+                SCE->REG_ECH = 0x00000020U;
+                SCE->REG_ECH = 0x0000b420U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_ECH = 0x00002822U;
+                SCE->REG_ECH = 0x00056821U;
+                SCE->REG_ECH = 0x00003401U;
+                SCE->REG_E0H = 0x81010020U;
+                SCE->REG_04H = 0x00000606U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                S_RAM[0] = change_endian_long(SCE->REG_100H);
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x0000a4c0U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_ECH = 0x0000a460U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_ECH = 0x00003846U;
+                    SCE->REG_ECH = 0x00003c43U;
+                    SCE->REG_ECH = 0x00003020U;
+                    HW_SCE_func101(0x65759091U, 0x3f0aacb9U, 0xcce9b35bU, 0xb5845086U);
+                }
+                HW_SCE_func100(0x1b59867eU, 0x32965fa9U, 0xa3ab172dU, 0x8b308c8fU);
+                SCE->REG_ECH = 0x38000c21U;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_ECH = 0x0000b460U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_B0H = 0x00000020U;
+                SCE->REG_A4H = 0x00008dadU;
+                SCE->REG_E0H = 0x81840003U;
+                SCE->REG_00H = 0x00001813U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_04H = 0x00000112U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop + 0] = SCE->REG_100H;
+                OutData_Text[iLoop + 1] = SCE->REG_100H;
+                OutData_Text[iLoop + 2] = SCE->REG_100H;
+                OutData_Text[iLoop + 3] = SCE->REG_100H;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_ECH = 0x000024c5U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_ECH = 0x00003c26U;
+                SCE->REG_ECH = 0x00000842U;
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x0000a4c0U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_ECH = 0x00003c46U;
+                    SCE->REG_ECH = 0x00003000U;
+                    HW_SCE_func101(0x0c6ab5abU, 0xa8a59fcfU, 0x4e25d07aU, 0xa47479a5U);
+                }
+                HW_SCE_func100(0x425ab71fU, 0xc82744e4U, 0x78917484U, 0x519e438bU);
+                SCE->REG_ECH = 0x38000c00U;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_E0H = 0x81840006U;
+                SCE->REG_04H = 0x00000612U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+4 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+5 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+6 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+7 + 0] = SCE->REG_100H;
+                HW_SCE_func101(0x9b12682dU, 0x9f680f9fU, 0xc40d5caaU, 0xcea34015U);
+            }
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x01000684U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_ECH = 0x0000b4c0U;
+            SCE->REG_ECH = 0x00000010U;
+            SCE->REG_E0H = 0x80840006U;
+            SCE->REG_00H = 0x00008113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            HW_SCE_func102(0x0c497a06U, 0xc4b1bad8U, 0x36605d00U, 0x12e3c09dU);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_SUCCESS;
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/RA6T_Boot/200821/HW_SCE/Cryptographic/HW_SCE_pb3f.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb3i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb3i.c
new file mode 100644
index 000000000..ad4f053d1
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb3i.c
@@ -0,0 +1,191 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes128XtsEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x0000b301U;
+    SCE->REG_108H = 0x00000000U;
+    SCE->REG_A4H = 0x00060805U;
+    SCE->REG_ECH = 0x0000b4c0U;
+    SCE->REG_ECH = 0x00000010U;
+    SCE->REG_E0H = 0x81840006U;
+    SCE->REG_00H = 0x00001813U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x800100a0U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[0];
+    SCE->REG_104H = 0x00000058U;
+    SCE->REG_E0H = 0x800100c0U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x000000b3U);
+    HW_SCE_func101(0x5025a1c6U, 0x66167039U, 0xdf5a20b0U, 0xdeb47c9dU);
+    HW_SCE_func043();
+    HW_SCE_func100(0x7c4cc7cfU, 0xf94cfb37U, 0x93e9584aU, 0x2163084aU);
+    SCE->REG_ECH = 0x0000b4a0U;
+    SCE->REG_ECH = 0x00000008U;
+    HW_SCE_func044();
+    HW_SCE_func100(0xd505746aU, 0xa7a20794U, 0xd8a48731U, 0xd37841a5U);
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x02f8263dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[1];
+    SCE->REG_100H = InData_KeyIndex[2];
+    SCE->REG_100H = InData_KeyIndex[3];
+    SCE->REG_100H = InData_KeyIndex[4];
+    HW_SCE_func100(0xea20a04cU, 0x31a2bfb8U, 0x8174c241U, 0xaa62b7b0U);
+    SCE->REG_104H = 0x00000761U;
+    SCE->REG_A4H = 0x00f9263dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[5];
+    SCE->REG_100H = InData_KeyIndex[6];
+    SCE->REG_100H = InData_KeyIndex[7];
+    SCE->REG_100H = InData_KeyIndex[8];
+    SCE->REG_A4H = 0x000026bdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[9];
+    SCE->REG_100H = InData_KeyIndex[10];
+    SCE->REG_100H = InData_KeyIndex[11];
+    SCE->REG_100H = InData_KeyIndex[12];
+    SCE->REG_A4H = 0x00900c45U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_func100(0x0dbd2e5eU, 0xc844cdd1U, 0x7ac256c8U, 0xea65ffb8U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_func102(0xfaed3c01U, 0xcb016beaU, 0x3a79f631U, 0x5ecfa5c7U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+    }
+    else
+    {
+        SCE->REG_104H = 0x00000361U;
+        SCE->REG_A4H = 0x0004180dU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_IV[0];
+        SCE->REG_100H = InData_IV[1];
+        SCE->REG_100H = InData_IV[2];
+        SCE->REG_100H = InData_IV[3];
+        return FSP_SUCCESS;
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/RA6T_Boot/200821/HW_SCE/Cryptographic/HW_SCE_pb3i.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb3u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb3u.c
new file mode 100644
index 000000000..539044e91
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb3u.c
@@ -0,0 +1,127 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes128XtsEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_func100(0x297a87b8U, 0xf2ccb622U, 0xefeceeedU, 0x257b8fddU);
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_B0H = 0x00000020U;
+    SCE->REG_A4H = 0x00008daeU;
+    SCE->REG_04H = 0x0000c100U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_Text[0];
+    SCE->REG_100H = InData_Text[1];
+    SCE->REG_100H = InData_Text[2];
+    SCE->REG_100H = InData_Text[3];
+    for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    }
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    HW_SCE_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+    HW_SCE_func101(0xfa934af1U, 0x6d9a0835U, 0x83571ed2U, 0xd112a3f2U);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/RA6T_Boot/200821/HW_SCE/Cryptographic/HW_SCE_pb3u.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb6f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb6f.c
new file mode 100644
index 000000000..560b5c4b3
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb6f.c
@@ -0,0 +1,433 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes128XtsDecryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x80010000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_TextBitLen[0];
+    SCE->REG_ECH = 0x00003420U;
+    SCE->REG_ECH = 0x00076821U;
+    SCE->REG_ECH = 0x00026c21U;
+    SCE->REG_ECH = 0x000008c6U;
+    SCE->REG_ECH = 0x38008c00U;
+    SCE->REG_ECH = 0x0000007fU;
+    SCE->REG_ECH = 0x00020020U;
+    SCE->REG_ECH = 0x3420a800U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_ECH = 0x1000d0c0U;
+    SCE->REG_ECH = 0x2000a820U;
+    SCE->REG_ECH = 0x00000004U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_ECH = 0x38000cc6U;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00A60000U;
+    HW_SCE_func100(0xd5607bc5U, 0x8abd5a61U, 0x481443d3U, 0xf21c4cd7U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_func102(0xb3ffd26fU, 0xe72bf127U, 0x63e94c67U, 0x286e3832U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        HW_SCE_func100(0x2dfbd4f9U, 0xfbfa6c1aU, 0xc0f18a51U, 0xa8aa4bacU);
+        SCE->REG_E0H = 0x81010020U;
+        SCE->REG_04H = 0x00000606U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        S_RAM[0] = change_endian_long(SCE->REG_100H);
+        HW_SCE_func100(0xe1583c80U, 0x035bd2d0U, 0xbea324c9U, 0x7cfe63a8U);
+        SCE->REG_104H = 0x000000b1U;
+        SCE->REG_B0H = 0x00000020U;
+        SCE->REG_A4H = 0x0000cdaeU;
+        SCE->REG_04H = 0x0000c100U;
+        iLoop = 0;
+            if(S_RAM[0] >= 4) 
+        {
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_Text[0];
+            SCE->REG_100H = InData_Text[1];
+            SCE->REG_100H = InData_Text[2];
+            SCE->REG_100H = InData_Text[3];
+            for (iLoop = 4; iLoop < S_RAM[0]; iLoop = iLoop + 4)
+            {
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+            }
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+        }
+        HW_SCE_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+        HW_SCE_func100(0x68f58131U, 0x5f61ad2dU, 0x5eded0faU, 0xd58f61b7U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_func102(0x87095c78U, 0xb43f5ceaU, 0xc5c296c1U, 0x396f4f72U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            SCE->REG_ECH = 0x38008c00U;
+            SCE->REG_ECH = 0x0000007fU;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00A60000U;
+            HW_SCE_func100(0x77403975U, 0x451015e6U, 0x17567b8bU, 0xfb498237U);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_func100(0x5d66f55cU, 0x927babcaU, 0x10486486U, 0x3e3492a4U);
+                SCE->REG_104H = 0x00000051U;
+                SCE->REG_A4H = 0x00050604U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = change_endian_long(0x00000000U);
+                SCE->REG_104H = 0x00000051U;
+                SCE->REG_B0H = 0x00000020U;
+                SCE->REG_A4H = 0x0000cd2cU;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = change_endian_long(0x00000000U);
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_B0H = 0x00000020U;
+                SCE->REG_A4H = 0x0000cdadU;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_E0H = 0x80840006U;
+                SCE->REG_00H = 0x00008113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_ECH = 0x0000b460U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_104H = 0x00000368U;
+                SCE->REG_E0H = 0x80840003U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+4 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+5 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+6 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+7 + 0];
+                SCE->REG_ECH = 0x00003440U;
+                SCE->REG_ECH = 0x00008c40U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x0000b480U;
+                SCE->REG_ECH = 0xffffffffU;
+                SCE->REG_ECH = 0x00004402U;
+                SCE->REG_ECH = 0x00007484U;
+                SCE->REG_ECH = 0x000034a0U;
+                SCE->REG_ECH = 0x000368a5U;
+                SCE->REG_ECH = 0x00008ca0U;
+                SCE->REG_ECH = 0x0000000cU;
+                SCE->REG_ECH = 0x000024c5U;
+                SCE->REG_ECH = 0x00002465U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_ECH = 0x00003843U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_ECH = 0x00001484U;
+                SCE->REG_ECH = 0x00000c44U;
+                SCE->REG_ECH = 0x00001041U;
+                SCE->REG_ECH = 0x00003c43U;
+                SCE->REG_ECH = 0x00003440U;
+                SCE->REG_ECH = 0x00008c40U;
+                SCE->REG_ECH = 0x0000007fU;
+                SCE->REG_ECH = 0x38008c40U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x1000a440U;
+                SCE->REG_ECH = 0x00000020U;
+                SCE->REG_ECH = 0x0000b420U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_ECH = 0x00002822U;
+                SCE->REG_ECH = 0x00056821U;
+                SCE->REG_ECH = 0x00003401U;
+                SCE->REG_E0H = 0x81010020U;
+                SCE->REG_04H = 0x00000606U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                S_RAM[0] = change_endian_long(SCE->REG_100H);
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x0000a4c0U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_ECH = 0x0000a460U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_ECH = 0x00003846U;
+                    SCE->REG_ECH = 0x00003c43U;
+                    SCE->REG_ECH = 0x00003020U;
+                    HW_SCE_func101(0xea7ad227U, 0x3550d88fU, 0x859a5bd7U, 0x00be02a3U);
+                }
+                HW_SCE_func100(0x3320125fU, 0xf3a9f650U, 0x2199bafdU, 0x98b899cdU);
+                SCE->REG_ECH = 0x38000c21U;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_104H = 0x00000051U;
+                SCE->REG_A4H = 0x00040644U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = change_endian_long(0x00000000U);
+                SCE->REG_ECH = 0x0000b460U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_B0H = 0x00000020U;
+                SCE->REG_A4H = 0x0000cdadU;
+                SCE->REG_E0H = 0x81840003U;
+                SCE->REG_00H = 0x00001813U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_04H = 0x00000112U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop + 0] = SCE->REG_100H;
+                OutData_Text[iLoop + 1] = SCE->REG_100H;
+                OutData_Text[iLoop + 2] = SCE->REG_100H;
+                OutData_Text[iLoop + 3] = SCE->REG_100H;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_ECH = 0x000024c5U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_ECH = 0x00003c26U;
+                SCE->REG_ECH = 0x00000842U;
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x0000a4c0U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_ECH = 0x00003c46U;
+                    SCE->REG_ECH = 0x00003000U;
+                    HW_SCE_func101(0x49f567bbU, 0x1e5a92f8U, 0x41b8b1feU, 0x6febddf3U);
+                }
+                HW_SCE_func100(0x272903afU, 0x87f1b22eU, 0xae507c75U, 0xf577797aU);
+                SCE->REG_ECH = 0x38000c00U;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_E0H = 0x81840006U;
+                SCE->REG_04H = 0x00000612U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+4 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+5 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+6 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+7 + 0] = SCE->REG_100H;
+                HW_SCE_func101(0x9cce1c4dU, 0xd2fe58c7U, 0x01777838U, 0xda4dfbfeU);
+            }
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x01000684U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_ECH = 0x0000b4c0U;
+            SCE->REG_ECH = 0x00000010U;
+            SCE->REG_E0H = 0x80840006U;
+            SCE->REG_00H = 0x00008113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            HW_SCE_func102(0xe82858d2U, 0xac54c053U, 0xce8756daU, 0xd7c8a8f2U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_SUCCESS;
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/RA6T_Boot/200821/HW_SCE/Cryptographic/HW_SCE_pb6f.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb6i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb6i.c
new file mode 100644
index 000000000..3526a8976
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb6i.c
@@ -0,0 +1,191 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes128XtsDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x0000b601U;
+    SCE->REG_108H = 0x00000000U;
+    SCE->REG_A4H = 0x00060805U;
+    SCE->REG_ECH = 0x0000b4c0U;
+    SCE->REG_ECH = 0x00000010U;
+    SCE->REG_E0H = 0x81840006U;
+    SCE->REG_00H = 0x00001813U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x800100a0U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[0];
+    SCE->REG_104H = 0x00000058U;
+    SCE->REG_E0H = 0x800100c0U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x000000b6U);
+    HW_SCE_func101(0xc84e7a33U, 0xf52d778aU, 0x86c3749cU, 0x002a07a2U);
+    HW_SCE_func043();
+    HW_SCE_func100(0xd1e71bdeU, 0x7698a16bU, 0x734e2ce0U, 0x4df7c07cU);
+    SCE->REG_ECH = 0x0000b4a0U;
+    SCE->REG_ECH = 0x00000008U;
+    HW_SCE_func044();
+    HW_SCE_func100(0xec6ea47dU, 0xac393824U, 0x0f9a748eU, 0x8d184bf3U);
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x02f8263dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[1];
+    SCE->REG_100H = InData_KeyIndex[2];
+    SCE->REG_100H = InData_KeyIndex[3];
+    SCE->REG_100H = InData_KeyIndex[4];
+    HW_SCE_func100(0x2f34b67fU, 0x92d6da5eU, 0xed55a092U, 0xf571bba4U);
+    SCE->REG_104H = 0x00000761U;
+    SCE->REG_A4H = 0x00f9263dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[5];
+    SCE->REG_100H = InData_KeyIndex[6];
+    SCE->REG_100H = InData_KeyIndex[7];
+    SCE->REG_100H = InData_KeyIndex[8];
+    SCE->REG_A4H = 0x000026bdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[9];
+    SCE->REG_100H = InData_KeyIndex[10];
+    SCE->REG_100H = InData_KeyIndex[11];
+    SCE->REG_100H = InData_KeyIndex[12];
+    SCE->REG_A4H = 0x00900c45U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_func100(0xf3d06202U, 0x84d19065U, 0x265b20a7U, 0x227e3d97U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_func102(0xfeb88923U, 0x8ef08db9U, 0x9385394aU, 0x35525a82U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+    }
+    else
+    {
+        SCE->REG_104H = 0x00000361U;
+        SCE->REG_A4H = 0x0004180dU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_IV[0];
+        SCE->REG_100H = InData_IV[1];
+        SCE->REG_100H = InData_IV[2];
+        SCE->REG_100H = InData_IV[3];
+        return FSP_SUCCESS;
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/RA6T_Boot/200821/HW_SCE/Cryptographic/HW_SCE_pb6i.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb6u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb6u.c
new file mode 100644
index 000000000..5c1880975
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb6u.c
@@ -0,0 +1,127 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes128XtsDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_func100(0xc581c488U, 0xb3096681U, 0x97d9b838U, 0x3b855161U);
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_B0H = 0x00000020U;
+    SCE->REG_A4H = 0x0000cdaeU;
+    SCE->REG_04H = 0x0000c100U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_Text[0];
+    SCE->REG_100H = InData_Text[1];
+    SCE->REG_100H = InData_Text[2];
+    SCE->REG_100H = InData_Text[3];
+    for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    }
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    HW_SCE_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+    HW_SCE_func101(0x138641e1U, 0x502be79fU, 0xf6f517f3U, 0xcba99654U);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/RA6T_Boot/200821/HW_SCE/Cryptographic/HW_SCE_pb6u.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb9f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb9f.c
new file mode 100644
index 000000000..0576d1e08
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb9f.c
@@ -0,0 +1,435 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes256XtsEncryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x80010000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_TextBitLen[0];
+    SCE->REG_ECH = 0x00003420U;
+    SCE->REG_ECH = 0x00076821U;
+    SCE->REG_ECH = 0x00026c21U;
+    SCE->REG_ECH = 0x000008c6U;
+    SCE->REG_ECH = 0x38008c00U;
+    SCE->REG_ECH = 0x0000007fU;
+    SCE->REG_ECH = 0x00020020U;
+    SCE->REG_ECH = 0x3420a800U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_ECH = 0x1000d0c0U;
+    SCE->REG_ECH = 0x2000a820U;
+    SCE->REG_ECH = 0x00000004U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_ECH = 0x38000cc6U;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00A60000U;
+    HW_SCE_func100(0xb26613e3U, 0x8fcbf316U, 0x77363984U, 0x56c5a9a9U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_func100(0x58528061U, 0x069ad4cdU, 0x3413d0cfU, 0xa462be32U);
+        SCE->REG_104H = 0x00000051U;
+        SCE->REG_A4H = 0x010b0644U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        HW_SCE_func102(0xaac42da6U, 0xfff5fbaeU, 0x54f57420U, 0xe2e264c4U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        HW_SCE_func100(0x12005f98U, 0x65512057U, 0x3a1d9a32U, 0xdad161e1U);
+        SCE->REG_E0H = 0x81010020U;
+        SCE->REG_04H = 0x00000606U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        S_RAM[0] = change_endian_long(SCE->REG_100H);
+        HW_SCE_func100(0x5224af5bU, 0x1b14dad7U, 0x00f2d690U, 0x7a0d043eU);
+        SCE->REG_104H = 0x000000b1U;
+        SCE->REG_B0H = 0x40000020U;
+        SCE->REG_A4H = 0x00008daeU;
+        SCE->REG_04H = 0x0000c100U;
+        iLoop = 0;
+            if(S_RAM[0] >= 4) 
+        {
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_Text[0];
+            SCE->REG_100H = InData_Text[1];
+            SCE->REG_100H = InData_Text[2];
+            SCE->REG_100H = InData_Text[3];
+            for (iLoop = 4; iLoop < S_RAM[0]; iLoop = iLoop + 4)
+            {
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+            }
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+        }
+        HW_SCE_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+        HW_SCE_func100(0x7eeacb57U, 0x4b4bb00bU, 0xc651f695U, 0x9fd4dec1U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_func100(0xa1035361U, 0xb13364a8U, 0xd6f804cfU, 0x3eb28444U);
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x010b0644U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            HW_SCE_func102(0x44d76337U, 0xc77e285dU, 0x6fffbb3eU, 0x1e0cb65fU);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            SCE->REG_ECH = 0x38008c00U;
+            SCE->REG_ECH = 0x0000007fU;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00A60000U;
+            HW_SCE_func100(0x1386ddfbU, 0x123bd081U, 0x931aeb93U, 0x5206684aU);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_func100(0x5757bce6U, 0x59a8da16U, 0x4e019726U, 0x4022d1f6U);
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_B0H = 0x40000020U;
+                SCE->REG_A4H = 0x00008dadU;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_E0H = 0x80840006U;
+                SCE->REG_00H = 0x00008113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_ECH = 0x0000b460U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_104H = 0x00000368U;
+                SCE->REG_E0H = 0x80840003U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+4 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+5 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+6 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+7 + 0];
+                SCE->REG_ECH = 0x00003440U;
+                SCE->REG_ECH = 0x00008c40U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x0000b480U;
+                SCE->REG_ECH = 0xffffffffU;
+                SCE->REG_ECH = 0x00004402U;
+                SCE->REG_ECH = 0x00007484U;
+                SCE->REG_ECH = 0x000034a0U;
+                SCE->REG_ECH = 0x000368a5U;
+                SCE->REG_ECH = 0x00008ca0U;
+                SCE->REG_ECH = 0x0000000cU;
+                SCE->REG_ECH = 0x000024c5U;
+                SCE->REG_ECH = 0x00002465U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_ECH = 0x00003843U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_ECH = 0x00001484U;
+                SCE->REG_ECH = 0x00000c44U;
+                SCE->REG_ECH = 0x00001041U;
+                SCE->REG_ECH = 0x00003c43U;
+                SCE->REG_ECH = 0x00003440U;
+                SCE->REG_ECH = 0x00008c40U;
+                SCE->REG_ECH = 0x0000007fU;
+                SCE->REG_ECH = 0x38008c40U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x1000a440U;
+                SCE->REG_ECH = 0x00000020U;
+                SCE->REG_ECH = 0x0000b420U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_ECH = 0x00002822U;
+                SCE->REG_ECH = 0x00056821U;
+                SCE->REG_ECH = 0x00003401U;
+                SCE->REG_E0H = 0x81010020U;
+                SCE->REG_04H = 0x00000606U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                S_RAM[0] = change_endian_long(SCE->REG_100H);
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x0000a4c0U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_ECH = 0x0000a460U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_ECH = 0x00003846U;
+                    SCE->REG_ECH = 0x00003c43U;
+                    SCE->REG_ECH = 0x00003020U;
+                    HW_SCE_func101(0xb6c83ae7U, 0x71dc42c1U, 0x2cff6c41U, 0x16aae51fU);
+                }
+                HW_SCE_func100(0x707a62acU, 0x47ecf41eU, 0x03a32ab1U, 0x9729dde2U);
+                SCE->REG_ECH = 0x38000c21U;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_ECH = 0x0000b460U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_B0H = 0x40000020U;
+                SCE->REG_A4H = 0x00008dadU;
+                SCE->REG_E0H = 0x81840003U;
+                SCE->REG_00H = 0x00001813U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_04H = 0x00000112U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop + 0] = SCE->REG_100H;
+                OutData_Text[iLoop + 1] = SCE->REG_100H;
+                OutData_Text[iLoop + 2] = SCE->REG_100H;
+                OutData_Text[iLoop + 3] = SCE->REG_100H;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_ECH = 0x000024c5U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_ECH = 0x00003c26U;
+                SCE->REG_ECH = 0x00000842U;
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x0000a4c0U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_ECH = 0x00003c46U;
+                    SCE->REG_ECH = 0x00003000U;
+                    HW_SCE_func101(0x3dcfcf30U, 0x2e3e0d8fU, 0x60e1a46eU, 0x796b6d4fU);
+                }
+                HW_SCE_func100(0x909ca31dU, 0x4c8887f2U, 0xaec02d78U, 0x5808b6f6U);
+                SCE->REG_ECH = 0x38000c00U;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_E0H = 0x81840006U;
+                SCE->REG_04H = 0x00000612U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+4 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+5 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+6 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+7 + 0] = SCE->REG_100H;
+                HW_SCE_func101(0x1bb31f58U, 0x669c8fc1U, 0x6d2fb3a6U, 0xd31f3068U);
+            }
+            HW_SCE_func100(0xcd32ed6fU, 0x49615749U, 0xac7abc6eU, 0x236ae5a7U);
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x010b0644U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x01000684U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_ECH = 0x0000b4c0U;
+            SCE->REG_ECH = 0x00000010U;
+            SCE->REG_E0H = 0x80840006U;
+            SCE->REG_00H = 0x00008113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            HW_SCE_func102(0xaa76e2e9U, 0x563d2ddcU, 0x2c95b082U, 0x6998f616U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_SUCCESS;
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/RA6T_Boot/200821/HW_SCE/Cryptographic/HW_SCE_pb9f.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb9i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb9i.c
new file mode 100644
index 000000000..2287eca73
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb9i.c
@@ -0,0 +1,272 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes256XtsEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x0000b901U;
+    SCE->REG_108H = 0x00000000U;
+    SCE->REG_104H = 0x00000251U;
+    SCE->REG_A4H = 0x0020363cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x0020363cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x002036bcU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_104H = 0x00000051U;
+    SCE->REG_A4H = 0x0021340cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x00070805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_A4H = 0x00060805U;
+    SCE->REG_ECH = 0x0000b4c0U;
+    SCE->REG_ECH = 0x00000010U;
+    SCE->REG_E0H = 0x81840006U;
+    SCE->REG_00H = 0x00001813U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x800100a0U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[0];
+    SCE->REG_104H = 0x00000058U;
+    SCE->REG_E0H = 0x800100c0U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x000000b9U);
+    HW_SCE_func101(0x390956a2U, 0x3d359a1dU, 0x5384796fU, 0x60563c30U);
+    HW_SCE_func043();
+    HW_SCE_func100(0x75899a02U, 0x91370c2eU, 0x7396ed2cU, 0xd1e14700U);
+    SCE->REG_ECH = 0x0000b4a0U;
+    SCE->REG_ECH = 0x00000009U;
+    HW_SCE_func044();
+    HW_SCE_func100(0x2ea8b1bdU, 0x0675464aU, 0xf20ced8fU, 0x7f190ee0U);
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x02f8263dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[1];
+    SCE->REG_100H = InData_KeyIndex[2];
+    SCE->REG_100H = InData_KeyIndex[3];
+    SCE->REG_100H = InData_KeyIndex[4];
+    HW_SCE_func100(0x5b41c2a1U, 0xb1905345U, 0x7320b263U, 0x96496fd2U);
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x00f9263dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[5];
+    SCE->REG_100H = InData_KeyIndex[6];
+    SCE->REG_100H = InData_KeyIndex[7];
+    SCE->REG_100H = InData_KeyIndex[8];
+    HW_SCE_func100(0xfb83c366U, 0x485abee4U, 0x7525100fU, 0xd25302e6U);
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x00f026bdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[9];
+    SCE->REG_100H = InData_KeyIndex[10];
+    SCE->REG_100H = InData_KeyIndex[11];
+    SCE->REG_100H = InData_KeyIndex[12];
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x00fb263dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[13];
+    SCE->REG_100H = InData_KeyIndex[14];
+    SCE->REG_100H = InData_KeyIndex[15];
+    SCE->REG_100H = InData_KeyIndex[16];
+    HW_SCE_func100(0x4d3b0cf9U, 0x34365472U, 0x28d09b1eU, 0xf72bf92aU);
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x000026bdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[17];
+    SCE->REG_100H = InData_KeyIndex[18];
+    SCE->REG_100H = InData_KeyIndex[19];
+    SCE->REG_100H = InData_KeyIndex[20];
+    SCE->REG_A4H = 0x000a0805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_A4H = 0x00900c45U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_func100(0x6d071d0dU, 0x3ca1faf7U, 0xebb0fd4cU, 0x18c20f48U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_func100(0xff0bf5e2U, 0xf1d62821U, 0x71a44456U, 0x6d002d26U);
+        SCE->REG_104H = 0x00000051U;
+        SCE->REG_A4H = 0x010b0644U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        HW_SCE_func102(0x1362595dU, 0x5e5f0a76U, 0x8558994bU, 0xfdee6b1cU);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+    }
+    else
+    {
+        SCE->REG_104H = 0x00000361U;
+        SCE->REG_B0H = 0x40000000U;
+        SCE->REG_A4H = 0x0004a80dU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_IV[0];
+        SCE->REG_100H = InData_IV[1];
+        SCE->REG_100H = InData_IV[2];
+        SCE->REG_100H = InData_IV[3];
+        return FSP_SUCCESS;
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/RA6T_Boot/200821/HW_SCE/Cryptographic/HW_SCE_pb9i.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb9u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb9u.c
new file mode 100644
index 000000000..82177fdc8
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pb9u.c
@@ -0,0 +1,127 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes256XtsEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_func100(0xc3e8da0fU, 0xde351af2U, 0x5308aafdU, 0x390f2b09U);
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_B0H = 0x40000020U;
+    SCE->REG_A4H = 0x00008daeU;
+    SCE->REG_04H = 0x0000c100U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_Text[0];
+    SCE->REG_100H = InData_Text[1];
+    SCE->REG_100H = InData_Text[2];
+    SCE->REG_100H = InData_Text[3];
+    for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    }
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    HW_SCE_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+    HW_SCE_func101(0x3a312c5eU, 0x7f7a7c17U, 0xab999074U, 0xa2af8f2eU);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/RA6T_Boot/200821/HW_SCE/Cryptographic/HW_SCE_pb9u.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pc2f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pc2f.c
new file mode 100644
index 000000000..c3f31617d
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pc2f.c
@@ -0,0 +1,460 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes256XtsDecryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x80010000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_TextBitLen[0];
+    SCE->REG_ECH = 0x00003420U;
+    SCE->REG_ECH = 0x00076821U;
+    SCE->REG_ECH = 0x00026c21U;
+    SCE->REG_ECH = 0x000008c6U;
+    SCE->REG_ECH = 0x38008c00U;
+    SCE->REG_ECH = 0x0000007fU;
+    SCE->REG_ECH = 0x00020020U;
+    SCE->REG_ECH = 0x3420a800U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_ECH = 0x1000d0c0U;
+    SCE->REG_ECH = 0x2000a820U;
+    SCE->REG_ECH = 0x00000004U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_ECH = 0x38000cc6U;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00A60000U;
+    HW_SCE_func100(0x9f1ad3c7U, 0xa3fa4a6aU, 0x3396b804U, 0xa60bac7cU);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_func100(0x2c5cb97cU, 0x52b86309U, 0xa3772fd0U, 0x9fa59d56U);
+        SCE->REG_104H = 0x00000051U;
+        SCE->REG_A4H = 0x010b0644U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        HW_SCE_func102(0x999953abU, 0x3d46bd2cU, 0xc31bc82aU, 0x351b3e6bU);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        HW_SCE_func100(0x13b7fe30U, 0x99470ecbU, 0x73fb0091U, 0xcc1422dcU);
+        SCE->REG_E0H = 0x81010020U;
+        SCE->REG_04H = 0x00000606U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        S_RAM[0] = change_endian_long(SCE->REG_100H);
+        HW_SCE_func100(0x0c139818U, 0xb1c60822U, 0xd9896ec5U, 0x584bc4adU);
+        SCE->REG_104H = 0x000000b1U;
+        SCE->REG_B0H = 0x40000020U;
+        SCE->REG_A4H = 0x0000cdaeU;
+        SCE->REG_04H = 0x0000c100U;
+        iLoop = 0;
+            if(S_RAM[0] >= 4) 
+        {
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_Text[0];
+            SCE->REG_100H = InData_Text[1];
+            SCE->REG_100H = InData_Text[2];
+            SCE->REG_100H = InData_Text[3];
+            for (iLoop = 4; iLoop < S_RAM[0]; iLoop = iLoop + 4)
+            {
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+            }
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+        }
+        HW_SCE_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+        HW_SCE_func100(0x119c2ec4U, 0x628ea9ceU, 0xe50ebefcU, 0x40952bd4U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_func100(0x752f6284U, 0x2165f522U, 0x05dbf687U, 0xbc616416U);
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x010b0644U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            HW_SCE_func102(0x930c35a5U, 0x851d1f53U, 0x2669c14dU, 0xd087b9c6U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            SCE->REG_ECH = 0x38008c00U;
+            SCE->REG_ECH = 0x0000007fU;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00A60000U;
+            HW_SCE_func100(0x64ca3a97U, 0x78133f41U, 0x06f8a6f2U, 0x1f2ceea0U);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_func100(0xbc213d26U, 0xea83d482U, 0x605fceb4U, 0xe586e915U);
+                SCE->REG_104H = 0x00000051U;
+                SCE->REG_A4H = 0x00050604U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = change_endian_long(0x00000000U);
+                SCE->REG_104H = 0x00000051U;
+                SCE->REG_B0H = 0x40000020U;
+                SCE->REG_A4H = 0x0000cd2cU;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = change_endian_long(0x00000000U);
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_B0H = 0x40000020U;
+                SCE->REG_A4H = 0x0000cdadU;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_E0H = 0x80840006U;
+                SCE->REG_00H = 0x00008113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_ECH = 0x0000b460U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_104H = 0x00000368U;
+                SCE->REG_E0H = 0x80840003U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+4 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+5 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+6 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+7 + 0];
+                SCE->REG_ECH = 0x00003440U;
+                SCE->REG_ECH = 0x00008c40U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x0000b480U;
+                SCE->REG_ECH = 0xffffffffU;
+                SCE->REG_ECH = 0x00004402U;
+                SCE->REG_ECH = 0x00007484U;
+                SCE->REG_ECH = 0x000034a0U;
+                SCE->REG_ECH = 0x000368a5U;
+                SCE->REG_ECH = 0x00008ca0U;
+                SCE->REG_ECH = 0x0000000cU;
+                SCE->REG_ECH = 0x000024c5U;
+                SCE->REG_ECH = 0x00002465U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_ECH = 0x00003843U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_ECH = 0x00001484U;
+                SCE->REG_ECH = 0x00000c44U;
+                SCE->REG_ECH = 0x00001041U;
+                SCE->REG_ECH = 0x00003c43U;
+                SCE->REG_ECH = 0x00003440U;
+                SCE->REG_ECH = 0x00008c40U;
+                SCE->REG_ECH = 0x0000007fU;
+                SCE->REG_ECH = 0x38008c40U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x1000a440U;
+                SCE->REG_ECH = 0x00000020U;
+                SCE->REG_ECH = 0x0000b420U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_ECH = 0x00002822U;
+                SCE->REG_ECH = 0x00056821U;
+                SCE->REG_ECH = 0x00003401U;
+                SCE->REG_E0H = 0x81010020U;
+                SCE->REG_04H = 0x00000606U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                S_RAM[0] = change_endian_long(SCE->REG_100H);
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x0000a4c0U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_ECH = 0x0000a460U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_ECH = 0x00003846U;
+                    SCE->REG_ECH = 0x00003c43U;
+                    SCE->REG_ECH = 0x00003020U;
+                    HW_SCE_func101(0xfbedd59eU, 0xa57d25f5U, 0x85c40796U, 0x9ef260d9U);
+                }
+                HW_SCE_func100(0x58650db8U, 0x80ad8165U, 0x57e76724U, 0x05e2c34fU);
+                SCE->REG_ECH = 0x38000c21U;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_104H = 0x00000051U;
+                SCE->REG_A4H = 0x00040644U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = change_endian_long(0x00000000U);
+                SCE->REG_ECH = 0x0000b460U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_B0H = 0x40000020U;
+                SCE->REG_A4H = 0x0000cdadU;
+                SCE->REG_E0H = 0x81840003U;
+                SCE->REG_00H = 0x00001813U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_04H = 0x00000112U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop + 0] = SCE->REG_100H;
+                OutData_Text[iLoop + 1] = SCE->REG_100H;
+                OutData_Text[iLoop + 2] = SCE->REG_100H;
+                OutData_Text[iLoop + 3] = SCE->REG_100H;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_ECH = 0x000024c5U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_ECH = 0x00003c26U;
+                SCE->REG_ECH = 0x00000842U;
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x0000a4c0U;
+                    SCE->REG_ECH = 0x00000004U;
+                    SCE->REG_ECH = 0x00003c46U;
+                    SCE->REG_ECH = 0x00003000U;
+                    HW_SCE_func101(0x39a7b534U, 0x872e0cd2U, 0x9512ea80U, 0xd7d75551U);
+                }
+                HW_SCE_func100(0xf1ed533dU, 0xeaafc24aU, 0x9eb39fbfU, 0xf32ecf93U);
+                SCE->REG_ECH = 0x38000c00U;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_E0H = 0x81840006U;
+                SCE->REG_04H = 0x00000612U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+4 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+5 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+6 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+7 + 0] = SCE->REG_100H;
+                HW_SCE_func101(0x1ad30d99U, 0xb444de05U, 0xc1906ac8U, 0x8bb61113U);
+            }
+            HW_SCE_func100(0x041d0122U, 0xd678cd0dU, 0xaa89c2beU, 0x6629aa7cU);
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x010b0644U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x01000684U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_ECH = 0x0000b4c0U;
+            SCE->REG_ECH = 0x00000010U;
+            SCE->REG_E0H = 0x80840006U;
+            SCE->REG_00H = 0x00008113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            HW_SCE_func102(0x710fa672U, 0x02c006c9U, 0x23245875U, 0xcd131682U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_SUCCESS;
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/RA6T_Boot/200821/HW_SCE/Cryptographic/HW_SCE_pc2f.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pc2i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pc2i.c
new file mode 100644
index 000000000..61bfbbbfc
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pc2i.c
@@ -0,0 +1,272 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes256XtsDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x0000c201U;
+    SCE->REG_108H = 0x00000000U;
+    SCE->REG_104H = 0x00000251U;
+    SCE->REG_A4H = 0x0020363cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x0020363cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x002036bcU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_104H = 0x00000051U;
+    SCE->REG_A4H = 0x0021340cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_A4H = 0x00070805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_A4H = 0x00060805U;
+    SCE->REG_ECH = 0x0000b4c0U;
+    SCE->REG_ECH = 0x00000010U;
+    SCE->REG_E0H = 0x81840006U;
+    SCE->REG_00H = 0x00001813U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x800100a0U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[0];
+    SCE->REG_104H = 0x00000058U;
+    SCE->REG_E0H = 0x800100c0U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x000000c2U);
+    HW_SCE_func101(0x66a40182U, 0xe09596f9U, 0x8b3225d5U, 0x48df15a2U);
+    HW_SCE_func043();
+    HW_SCE_func100(0x7b933b57U, 0xa1d2f912U, 0x1cdf970dU, 0x653a7c28U);
+    SCE->REG_ECH = 0x0000b4a0U;
+    SCE->REG_ECH = 0x00000009U;
+    HW_SCE_func044();
+    HW_SCE_func100(0x99c482f3U, 0x7be84bf2U, 0xeb05482bU, 0xf97b0656U);
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x02f8263dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[1];
+    SCE->REG_100H = InData_KeyIndex[2];
+    SCE->REG_100H = InData_KeyIndex[3];
+    SCE->REG_100H = InData_KeyIndex[4];
+    HW_SCE_func100(0x88aa6fa7U, 0x2ce1f09aU, 0x5113c601U, 0xa77b5c66U);
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x00f9263dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[5];
+    SCE->REG_100H = InData_KeyIndex[6];
+    SCE->REG_100H = InData_KeyIndex[7];
+    SCE->REG_100H = InData_KeyIndex[8];
+    HW_SCE_func100(0xff0f56c2U, 0x7918045dU, 0xcc025017U, 0xbc5b9b6eU);
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x00f026bdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[9];
+    SCE->REG_100H = InData_KeyIndex[10];
+    SCE->REG_100H = InData_KeyIndex[11];
+    SCE->REG_100H = InData_KeyIndex[12];
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x00fb263dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[13];
+    SCE->REG_100H = InData_KeyIndex[14];
+    SCE->REG_100H = InData_KeyIndex[15];
+    SCE->REG_100H = InData_KeyIndex[16];
+    HW_SCE_func100(0x73ee2cb7U, 0xcd3354bdU, 0x231df94dU, 0x2436397dU);
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x000026bdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[17];
+    SCE->REG_100H = InData_KeyIndex[18];
+    SCE->REG_100H = InData_KeyIndex[19];
+    SCE->REG_100H = InData_KeyIndex[20];
+    SCE->REG_A4H = 0x000a0805U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_A4H = 0x00900c45U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_func100(0x120fa0d6U, 0x0dd6277eU, 0xc18ba544U, 0xc0067778U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_func100(0x15a01140U, 0x284081f2U, 0x91723104U, 0x82a49cb0U);
+        SCE->REG_104H = 0x00000051U;
+        SCE->REG_A4H = 0x010b0644U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        HW_SCE_func102(0xf671ccc1U, 0xc634f098U, 0x2c503a86U, 0x5dd96648U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+    }
+    else
+    {
+        SCE->REG_104H = 0x00000361U;
+        SCE->REG_B0H = 0x40000000U;
+        SCE->REG_A4H = 0x0004a80dU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_IV[0];
+        SCE->REG_100H = InData_IV[1];
+        SCE->REG_100H = InData_IV[2];
+        SCE->REG_100H = InData_IV[3];
+        return FSP_SUCCESS;
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/RA6T_Boot/200821/HW_SCE/Cryptographic/HW_SCE_pc2i.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pc2u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pc2u.c
new file mode 100644
index 000000000..5c27dc7d2
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/primitive/hw_sce_pc2u.c
@@ -0,0 +1,127 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes256XtsDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_func100(0x55894bdcU, 0x3ae9abc1U, 0xece5e11dU, 0xaaf9187dU);
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_B0H = 0x40000020U;
+    SCE->REG_A4H = 0x0000cdaeU;
+    SCE->REG_04H = 0x0000c100U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_Text[0];
+    SCE->REG_100H = InData_Text[1];
+    SCE->REG_100H = InData_Text[2];
+    SCE->REG_100H = InData_Text[3];
+    for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    }
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    HW_SCE_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+    HW_SCE_func101(0x57c741d2U, 0x001664b4U, 0x06f4eed4U, 0x431953c9U);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/RA6T_Boot/200821/HW_SCE/Cryptographic/HW_SCE_pc2u.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/private/inc/SCE_module.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/private/inc/SCE_module.h
index 26bb94bec..64e75a67d 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/private/inc/SCE_module.h
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/private/inc/SCE_module.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/adaptors/r_sce_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/adaptors/r_sce_adapt.c
index df8976d13..3ca4e7f30 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/adaptors/r_sce_adapt.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/adaptors/r_sce_adapt.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -148,6 +148,10 @@ fsp_err_t HW_SCE_GenerateOemKeyIndexPrivate (const sce_oem_key_type_t key_type,
         {
             ret = HW_SCE_GenerateAes256KeyIndexSub(indata_key_type, install_key_ring_index, (uint32_t *) encrypted_provisioning_key, (uint32_t *) iv, (uint32_t *) encrypted_oem_key, key_index);
         }
+        else if (cmd == SCE_OEM_CMD_AES128_XTS)
+        {
+            ret = HW_SCE_GenerateAes128XtsKeyIndexSub(indata_key_type, install_key_ring_index, (uint32_t *) encrypted_provisioning_key, (uint32_t *) iv, (uint32_t *) encrypted_oem_key, key_index);
+        }
         else if (cmd == SCE_OEM_CMD_RSA2048_PUBLIC)
         {
             ret = HW_SCE_GenerateRsa2048PublicKeyIndexSub(indata_key_type, install_key_ring_index, (uint32_t *) encrypted_provisioning_key, (uint32_t *) iv, (uint32_t *) encrypted_oem_key, key_index);
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_func205.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_func205.c
new file mode 100644
index 000000000..abd6ae0b8
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_func205.c
@@ -0,0 +1,91 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_p_func205(void)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    SCE->REG_104H = 0x00000000U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_A8H_b.B6)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x002c0000U;
+    SCE->REG_1CH = 0x002d0000U;
+    SCE->REG_B0H = 0x00000001U;
+    SCE->REG_A4H = 0x00000000U;
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_func205.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_func207.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_func207.c
new file mode 100644
index 000000000..a7e7a6739
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_func207.c
@@ -0,0 +1,92 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_p_func207(void)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    SCE->REG_04H = 0x00000000U;
+    SCE->REG_104H = 0x00000000U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_A8H_b.B6)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x002c0000U;
+    SCE->REG_1CH = 0x002d0000U;
+    SCE->REG_B0H = 0x00000001U;
+    SCE->REG_A4H = 0x00000000U;
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_func207.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p12.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p12.c
new file mode 100644
index 000000000..a23f0c0af
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p12.c
@@ -0,0 +1,543 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_GenerateAes128XtsKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x00001201U;
+    SCE->REG_108H = 0x00000000U;
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x800103e0U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyType[0];
+    SCE->REG_ECH = 0x38000fffU;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00260000U;
+    HW_SCE_p_func100(0x43e9b133U, 0xac6be8c3U, 0x9f9a899eU, 0x3a7a97a4U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        SCE->REG_104H = 0x00000068U;
+        SCE->REG_E0H = 0x80010000U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(InData_SharedKeyIndex[0]);
+        SCE->REG_ECH = 0x38008c00U;
+        SCE->REG_ECH = 0xfffffff0U;
+        SCE->REG_E0H = 0x00000080U;
+        SCE->REG_1CH = 0x00A60000U;
+        HW_SCE_p_func100(0x8ad5d3e5U, 0x666841faU, 0x9d6ea2bdU, 0x58862544U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_p_func102(0x78d22ee0U, 0x8b724f03U, 0x89116727U, 0xfb4fe866U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            HW_SCE_p_func100(0x76cf34b3U, 0x7804ea15U, 0x8fcd2a2dU, 0x89b93ce1U);
+            OFS_ADR = InData_SharedKeyIndex[0]*8;
+            SCE->REG_C4H = 0x000c3b0cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x3b74d08aU);
+            SCE->REG_C4H = 0x000c0b0cU;
+            SCE->REG_E0H = 0x81010000U;
+            SCE->REG_00H = 0x00002807U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x02fb073dU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = S_FLASH[OFS_ADR + 0];
+            SCE->REG_100H = S_FLASH[OFS_ADR + 1];
+            SCE->REG_100H = S_FLASH[OFS_ADR + 2];
+            SCE->REG_100H = S_FLASH[OFS_ADR + 3];
+            HW_SCE_p_func100(0x95a55768U, 0x8441a4e9U, 0xe6242002U, 0x8a7d128bU);
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x000007bdU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = S_FLASH[OFS_ADR+4 + 0];
+            SCE->REG_100H = S_FLASH[OFS_ADR+4 + 1];
+            SCE->REG_100H = S_FLASH[OFS_ADR+4 + 2];
+            SCE->REG_100H = S_FLASH[OFS_ADR+4 + 3];
+            SCE->REG_A4H = 0x00800c45U;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x00087a05U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_SessionKey[0];
+            SCE->REG_100H = InData_SessionKey[1];
+            SCE->REG_100H = InData_SessionKey[2];
+            SCE->REG_100H = InData_SessionKey[3];
+            HW_SCE_p_func100(0x303a46c8U, 0x02204e4fU, 0x8a975920U, 0xb3e2c017U);
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x00097a05U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_SessionKey[4];
+            SCE->REG_100H = InData_SessionKey[5];
+            SCE->REG_100H = InData_SessionKey[6];
+            SCE->REG_100H = InData_SessionKey[7];
+            HW_SCE_p_func100(0x883b8d7eU, 0xb24ec166U, 0x352f4724U, 0x946ee7c8U);
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x00040805U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_IV[0];
+            SCE->REG_100H = InData_IV[1];
+            SCE->REG_100H = InData_IV[2];
+            SCE->REG_100H = InData_IV[3];
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00050804U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            HW_SCE_p_func103();
+            HW_SCE_p_func100(0x71784993U, 0x7e5de785U, 0xf7864e9aU, 0x0606704fU);
+            SCE->REG_104H = 0x00000052U;
+            SCE->REG_C4H = 0x01000c84U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_E0H = 0x80040000U;
+            SCE->REG_00H = 0x00008213U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_A4H = 0x200c3b0dU;
+            SCE->REG_E0H = 0x81040000U;
+            SCE->REG_00H = 0x00001813U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_A4H = 0x000c0b0cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x2d8daf39U);
+            SCE->REG_00H = 0x00002123U;
+            SCE->REG_104H = 0x00000761U;
+            SCE->REG_B0H = 0x00000100U;
+            SCE->REG_A4H = 0x00d0c9a7U;
+            SCE->REG_D0H = 0x00000100U;
+            SCE->REG_C4H = 0x02e087bfU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_InstData[0];
+            SCE->REG_100H = InData_InstData[1];
+            SCE->REG_100H = InData_InstData[2];
+            SCE->REG_100H = InData_InstData[3];
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_InstData[4];
+            SCE->REG_100H = InData_InstData[5];
+            SCE->REG_100H = InData_InstData[6];
+            SCE->REG_100H = InData_InstData[7];
+            SCE->REG_04H = 0x00000222U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_KeyIndex[4] = SCE->REG_100H;
+            OutData_KeyIndex[5] = SCE->REG_100H;
+            OutData_KeyIndex[6] = SCE->REG_100H;
+            OutData_KeyIndex[7] = SCE->REG_100H;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_KeyIndex[8] = SCE->REG_100H;
+            OutData_KeyIndex[9] = SCE->REG_100H;
+            OutData_KeyIndex[10] = SCE->REG_100H;
+            OutData_KeyIndex[11] = SCE->REG_100H;
+            HW_SCE_p_func100(0xb25a5d47U, 0x96778d9eU, 0x933c78f8U, 0x0d4f83dbU);
+            SCE->REG_104H = 0x00000052U;
+            SCE->REG_C4H = 0x00000c84U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_C4H = 0x000009cdU;
+            SCE->REG_00H = 0x00002213U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_04H = 0x00000212U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_KeyIndex[12] = SCE->REG_100H;
+            OutData_KeyIndex[13] = SCE->REG_100H;
+            OutData_KeyIndex[14] = SCE->REG_100H;
+            OutData_KeyIndex[15] = SCE->REG_100H;
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x000049a5U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_InstData[8];
+            SCE->REG_100H = InData_InstData[9];
+            SCE->REG_100H = InData_InstData[10];
+            SCE->REG_100H = InData_InstData[11];
+            SCE->REG_A4H = 0x00900c45U;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            HW_SCE_p_func100(0x683fd211U, 0x5f9209bbU, 0x49114b38U, 0x8edeba37U);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_p_func102(0xd1050b68U, 0xfb1b14c6U, 0xb4fdd03cU, 0xceb01eb9U);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_ERR_CRYPTO_SCE_FAIL;
+            }
+            else
+            {
+                HW_SCE_p_func100(0x2683d509U, 0x40d35d99U, 0x203c9248U, 0x683d3cdfU);
+                SCE->REG_E0H = 0x81040000U;
+                SCE->REG_04H = 0x00000612U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_KeyIndex[0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_KeyIndex[1] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_KeyIndex[2] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_KeyIndex[3] = SCE->REG_100H;
+                HW_SCE_p_func102(0x1c8b8306U, 0x17fa5d27U, 0xef7aed28U, 0x23f2a6ebU);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_SUCCESS;
+            }
+        }
+    }
+    else
+    {
+        HW_SCE_p_func100(0x9c093942U, 0xa56c48ddU, 0xe0c1cac8U, 0xa0e22de5U);
+        HW_SCE_p_func103();
+        HW_SCE_p_func100(0xb2f0753cU, 0xd9fc69b9U, 0x61ec3094U, 0x9385a672U);
+        SCE->REG_104H = 0x00000052U;
+        SCE->REG_C4H = 0x01000c84U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        SCE->REG_E0H = 0x80040000U;
+        SCE->REG_00H = 0x00008213U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_A4H = 0x200c3b0dU;
+        SCE->REG_E0H = 0x81040000U;
+        SCE->REG_00H = 0x00001813U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_A4H = 0x000c0b0cU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x2d8daf39U);
+        SCE->REG_00H = 0x00002123U;
+        SCE->REG_104H = 0x00000761U;
+        SCE->REG_B0H = 0x00000100U;
+        SCE->REG_A4H = 0x00008887U;
+        SCE->REG_D0H = 0x00000100U;
+        SCE->REG_C4H = 0x02e087bfU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_InstData[0];
+        SCE->REG_100H = InData_InstData[1];
+        SCE->REG_100H = InData_InstData[2];
+        SCE->REG_100H = InData_InstData[3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_InstData[4];
+        SCE->REG_100H = InData_InstData[5];
+        SCE->REG_100H = InData_InstData[6];
+        SCE->REG_100H = InData_InstData[7];
+        SCE->REG_04H = 0x00000222U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[4] = SCE->REG_100H;
+        OutData_KeyIndex[5] = SCE->REG_100H;
+        OutData_KeyIndex[6] = SCE->REG_100H;
+        OutData_KeyIndex[7] = SCE->REG_100H;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[8] = SCE->REG_100H;
+        OutData_KeyIndex[9] = SCE->REG_100H;
+        OutData_KeyIndex[10] = SCE->REG_100H;
+        OutData_KeyIndex[11] = SCE->REG_100H;
+        HW_SCE_p_func100(0x733cb6f7U, 0x7ee74516U, 0x633a84f8U, 0xf07d3f53U);
+        SCE->REG_104H = 0x00000052U;
+        SCE->REG_C4H = 0x00000c84U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        SCE->REG_C4H = 0x000009cdU;
+        SCE->REG_00H = 0x00002213U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_04H = 0x00000212U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[12] = SCE->REG_100H;
+        OutData_KeyIndex[13] = SCE->REG_100H;
+        OutData_KeyIndex[14] = SCE->REG_100H;
+        OutData_KeyIndex[15] = SCE->REG_100H;
+        HW_SCE_p_func100(0x72aed4a5U, 0x54681fc1U, 0x58e16676U, 0xc1a01a37U);
+        SCE->REG_E0H = 0x81040000U;
+        SCE->REG_04H = 0x00000612U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[0] = SCE->REG_100H;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[1] = SCE->REG_100H;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[2] = SCE->REG_100H;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[3] = SCE->REG_100H;
+        HW_SCE_p_func102(0x31bfdbccU, 0x074b4607U, 0x1c97047aU, 0x95c0fd51U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_SUCCESS;
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_p12.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p13.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p13.c
new file mode 100644
index 000000000..a4a41be53
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p13.c
@@ -0,0 +1,573 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_GenerateAes256XtsKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x00001301U;
+    SCE->REG_108H = 0x00000000U;
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x800103e0U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyType[0];
+    SCE->REG_ECH = 0x38000fffU;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00260000U;
+    HW_SCE_p_func100(0xa952ee98U, 0xa1776572U, 0xd4223d10U, 0x5577daecU);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        SCE->REG_104H = 0x00000068U;
+        SCE->REG_E0H = 0x80010000U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(InData_SharedKeyIndex[0]);
+        SCE->REG_ECH = 0x38008c00U;
+        SCE->REG_ECH = 0xfffffff0U;
+        SCE->REG_E0H = 0x00000080U;
+        SCE->REG_1CH = 0x00A60000U;
+        HW_SCE_p_func100(0xf05d0f69U, 0x2f2fa83fU, 0x62406fe0U, 0x56fb434bU);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_p_func102(0x66940e2dU, 0x707e0eb3U, 0x399dd477U, 0xc15acdcdU);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            HW_SCE_p_func100(0x1f4b74f4U, 0x2f738c0eU, 0xa9cac0cdU, 0xf2415863U);
+            OFS_ADR = InData_SharedKeyIndex[0]*8;
+            SCE->REG_C4H = 0x000c3b0cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x3b74d08aU);
+            SCE->REG_C4H = 0x000c0b0cU;
+            SCE->REG_E0H = 0x81010000U;
+            SCE->REG_00H = 0x00002807U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x02fb073dU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = S_FLASH[OFS_ADR + 0];
+            SCE->REG_100H = S_FLASH[OFS_ADR + 1];
+            SCE->REG_100H = S_FLASH[OFS_ADR + 2];
+            SCE->REG_100H = S_FLASH[OFS_ADR + 3];
+            HW_SCE_p_func100(0x2135f6c2U, 0x5fd571b6U, 0xb6445bf8U, 0xd7253f6bU);
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x000007bdU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = S_FLASH[OFS_ADR+4 + 0];
+            SCE->REG_100H = S_FLASH[OFS_ADR+4 + 1];
+            SCE->REG_100H = S_FLASH[OFS_ADR+4 + 2];
+            SCE->REG_100H = S_FLASH[OFS_ADR+4 + 3];
+            SCE->REG_A4H = 0x00800c45U;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x00087a05U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_SessionKey[0];
+            SCE->REG_100H = InData_SessionKey[1];
+            SCE->REG_100H = InData_SessionKey[2];
+            SCE->REG_100H = InData_SessionKey[3];
+            HW_SCE_p_func100(0x5a0ab60fU, 0xab191df5U, 0xc72cd3ceU, 0x4ea17eeaU);
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x00097a05U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_SessionKey[4];
+            SCE->REG_100H = InData_SessionKey[5];
+            SCE->REG_100H = InData_SessionKey[6];
+            SCE->REG_100H = InData_SessionKey[7];
+            HW_SCE_p_func100(0x0f3dbb98U, 0x604012bbU, 0x20e2a669U, 0x71c32341U);
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x00040805U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_IV[0];
+            SCE->REG_100H = InData_IV[1];
+            SCE->REG_100H = InData_IV[2];
+            SCE->REG_100H = InData_IV[3];
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00050804U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            HW_SCE_p_func103();
+            HW_SCE_p_func100(0xb4e587eeU, 0x59a90220U, 0xc98e4342U, 0x665ab67fU);
+            SCE->REG_104H = 0x00000052U;
+            SCE->REG_C4H = 0x01000c84U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_E0H = 0x80040000U;
+            SCE->REG_00H = 0x00008213U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_A4H = 0x200c3b0dU;
+            SCE->REG_E0H = 0x81040000U;
+            SCE->REG_00H = 0x00001813U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_A4H = 0x000c0b0cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x5737b943U);
+            SCE->REG_00H = 0x00002143U;
+            SCE->REG_104H = 0x00000031U;
+            SCE->REG_B0H = 0x00000300U;
+            SCE->REG_A4H = 0x00d0c9a7U;
+            SCE->REG_D0H = 0x00000300U;
+            SCE->REG_C4H = 0x02e087bfU;
+            SCE->REG_04H = 0x00000242U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_InstData[0];
+            SCE->REG_100H = InData_InstData[1];
+            SCE->REG_100H = InData_InstData[2];
+            SCE->REG_100H = InData_InstData[3];
+            for (iLoop = 4; iLoop < 16 ; iLoop = iLoop + 4)
+            {
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_InstData[iLoop + 0];
+                SCE->REG_100H = InData_InstData[iLoop + 1];
+                SCE->REG_100H = InData_InstData[iLoop + 2];
+                SCE->REG_100H = InData_InstData[iLoop + 3];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_KeyIndex[iLoop + 0] = SCE->REG_100H;
+                OutData_KeyIndex[iLoop + 1] = SCE->REG_100H;
+                OutData_KeyIndex[iLoop + 2] = SCE->REG_100H;
+                OutData_KeyIndex[iLoop + 3] = SCE->REG_100H;
+            }
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_KeyIndex[iLoop + 0] = SCE->REG_100H;
+            OutData_KeyIndex[iLoop + 1] = SCE->REG_100H;
+            OutData_KeyIndex[iLoop + 2] = SCE->REG_100H;
+            OutData_KeyIndex[iLoop + 3] = SCE->REG_100H;
+            SCE->REG_104H = 0x00000000U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_C8H_b.B6)
+            {
+                /* waiting */
+            }
+            HW_SCE_p_func100(0x926155a1U, 0xa355d695U, 0x4b8f1f4dU, 0x6b9c7ba8U);
+            SCE->REG_104H = 0x00000052U;
+            SCE->REG_C4H = 0x00000c84U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_C4H = 0x000009cdU;
+            SCE->REG_00H = 0x00002213U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_04H = 0x00000212U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_KeyIndex[20] = SCE->REG_100H;
+            OutData_KeyIndex[21] = SCE->REG_100H;
+            OutData_KeyIndex[22] = SCE->REG_100H;
+            OutData_KeyIndex[23] = SCE->REG_100H;
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x000049a5U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_InstData[16];
+            SCE->REG_100H = InData_InstData[17];
+            SCE->REG_100H = InData_InstData[18];
+            SCE->REG_100H = InData_InstData[19];
+            SCE->REG_A4H = 0x00900c45U;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            HW_SCE_p_func100(0x5b5f9552U, 0x48fe2027U, 0x517b9d15U, 0xc1add95eU);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_p_func102(0x3285519cU, 0x7371d58eU, 0x8f17dcf1U, 0x15f9edcaU);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_ERR_CRYPTO_SCE_FAIL;
+            }
+            else
+            {
+                HW_SCE_p_func100(0x9dfb80fbU, 0x01459e2eU, 0x48e00493U, 0xcb8a84e5U);
+                SCE->REG_E0H = 0x81040000U;
+                SCE->REG_04H = 0x00000612U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_KeyIndex[0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_KeyIndex[1] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_KeyIndex[2] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_KeyIndex[3] = SCE->REG_100H;
+                HW_SCE_p_func102(0x945202cbU, 0xd916e9bfU, 0x95ad1636U, 0x5698eec4U);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_SUCCESS;
+            }
+        }
+    }
+    else
+    {
+        HW_SCE_p_func100(0x5d5b9144U, 0x8248c9c4U, 0x5a046e01U, 0x37c2f216U);
+        HW_SCE_p_func103();
+        HW_SCE_p_func100(0x5e114686U, 0xcb3cf0efU, 0xb34886fcU, 0xfd5f7b22U);
+        SCE->REG_104H = 0x00000052U;
+        SCE->REG_C4H = 0x01000c84U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        SCE->REG_E0H = 0x80040000U;
+        SCE->REG_00H = 0x00008213U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_A4H = 0x200c3b0dU;
+        SCE->REG_E0H = 0x81040000U;
+        SCE->REG_00H = 0x00001813U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_A4H = 0x000c0b0cU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x5737b943U);
+        SCE->REG_00H = 0x00002143U;
+        SCE->REG_104H = 0x00000031U;
+        SCE->REG_B0H = 0x00000300U;
+        SCE->REG_A4H = 0x00008887U;
+        SCE->REG_D0H = 0x00000300U;
+        SCE->REG_C4H = 0x02e087bfU;
+        SCE->REG_04H = 0x00000242U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_InstData[0];
+        SCE->REG_100H = InData_InstData[1];
+        SCE->REG_100H = InData_InstData[2];
+        SCE->REG_100H = InData_InstData[3];
+        for (iLoop = 4; iLoop < 16 ; iLoop = iLoop + 4)
+        {
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_InstData[iLoop + 0];
+            SCE->REG_100H = InData_InstData[iLoop + 1];
+            SCE->REG_100H = InData_InstData[iLoop + 2];
+            SCE->REG_100H = InData_InstData[iLoop + 3];
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_KeyIndex[iLoop + 0] = SCE->REG_100H;
+            OutData_KeyIndex[iLoop + 1] = SCE->REG_100H;
+            OutData_KeyIndex[iLoop + 2] = SCE->REG_100H;
+            OutData_KeyIndex[iLoop + 3] = SCE->REG_100H;
+        }
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[iLoop + 0] = SCE->REG_100H;
+        OutData_KeyIndex[iLoop + 1] = SCE->REG_100H;
+        OutData_KeyIndex[iLoop + 2] = SCE->REG_100H;
+        OutData_KeyIndex[iLoop + 3] = SCE->REG_100H;
+        SCE->REG_104H = 0x00000000U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_C8H_b.B6)
+        {
+            /* waiting */
+        }
+        HW_SCE_p_func100(0xa6c6b3cfU, 0x48c176b9U, 0x456a2ae0U, 0x9db84d24U);
+        SCE->REG_104H = 0x00000052U;
+        SCE->REG_C4H = 0x00000c84U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        SCE->REG_C4H = 0x000009cdU;
+        SCE->REG_00H = 0x00002213U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_04H = 0x00000212U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[20] = SCE->REG_100H;
+        OutData_KeyIndex[21] = SCE->REG_100H;
+        OutData_KeyIndex[22] = SCE->REG_100H;
+        OutData_KeyIndex[23] = SCE->REG_100H;
+        HW_SCE_p_func100(0xfb567de4U, 0xe8b0d2b7U, 0x4aca17e9U, 0xadcb4311U);
+        SCE->REG_E0H = 0x81040000U;
+        SCE->REG_04H = 0x00000612U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[0] = SCE->REG_100H;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[1] = SCE->REG_100H;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[2] = SCE->REG_100H;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[3] = SCE->REG_100H;
+        HW_SCE_p_func102(0xb433daa8U, 0xe2224abeU, 0xb40677d6U, 0x1a133fa1U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_SUCCESS;
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_p13.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p16.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p16.c
new file mode 100644
index 000000000..e1764757f
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p16.c
@@ -0,0 +1,241 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_GenerateAes128XtsRandomKeyIndexSub(uint32_t *OutData_KeyIndex)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x00001601U;
+    SCE->REG_108H = 0x00000000U;
+    HW_SCE_p_func100(0x87c8e2d8U, 0xd595dcefU, 0xe5db4674U, 0x011a9c9aU);
+    HW_SCE_p_func103();
+    SCE->REG_104H = 0x00000052U;
+    SCE->REG_C4H = 0x01000c84U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    HW_SCE_p_func100(0x12a33193U, 0xcd137e9dU, 0x7b186a35U, 0xfaaedbc4U);
+    SCE->REG_E0H = 0x80040000U;
+    SCE->REG_00H = 0x00008213U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_E0H = 0x81040000U;
+    SCE->REG_04H = 0x00000612U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[0] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[1] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[2] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[3] = SCE->REG_100H;
+    HW_SCE_p_func100(0xb48d056cU, 0x9250466dU, 0xd8aafc56U, 0xf219be44U);
+    SCE->REG_A4H = 0x200c3b0dU;
+    SCE->REG_E0H = 0x81040000U;
+    SCE->REG_00H = 0x00001813U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_A4H = 0x000c0b0cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x2d8daf39U);
+    HW_SCE_p_func103();
+    SCE->REG_104H = 0x00000052U;
+    SCE->REG_C4H = 0x01000c84U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_E0H = 0x80080000U;
+    SCE->REG_00H = 0x00008213U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_p_func100(0xfc881108U, 0x9f07dfc9U, 0xaa491a59U, 0xdc5cecd4U);
+    HW_SCE_p_func103();
+    SCE->REG_104H = 0x00000052U;
+    SCE->REG_C4H = 0x01000c84U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_00H = 0x00008213U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_p_func100(0x987e23feU, 0xeef104caU, 0xf1bb4746U, 0xfc987d2eU);
+    SCE->REG_B0H = 0x00000100U;
+    SCE->REG_A4H = 0x02e487bfU;
+    SCE->REG_E0H = 0x81080000U;
+    SCE->REG_00H = 0x00001823U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_104H = 0x00000351U;
+    SCE->REG_A4H = 0x000009cdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_100H = change_endian_long(0x00000002U);
+    SCE->REG_04H = 0x00000132U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[4] = SCE->REG_100H;
+    OutData_KeyIndex[5] = SCE->REG_100H;
+    OutData_KeyIndex[6] = SCE->REG_100H;
+    OutData_KeyIndex[7] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[8] = SCE->REG_100H;
+    OutData_KeyIndex[9] = SCE->REG_100H;
+    OutData_KeyIndex[10] = SCE->REG_100H;
+    OutData_KeyIndex[11] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[12] = SCE->REG_100H;
+    OutData_KeyIndex[13] = SCE->REG_100H;
+    OutData_KeyIndex[14] = SCE->REG_100H;
+    OutData_KeyIndex[15] = SCE->REG_100H;
+    HW_SCE_p_func102(0xd34d136aU, 0xaf832c61U, 0x4490eb64U, 0x10e47924U);
+    SCE->REG_1BCH = 0x00000040U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_18H_b.B12)
+    {
+        /* waiting */
+    }
+    return FSP_SUCCESS;
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_p16.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p17.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p17.c
new file mode 100644
index 000000000..be00ab609
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p17.c
@@ -0,0 +1,265 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_GenerateAes256XtsRandomKeyIndexSub(uint32_t *OutData_KeyIndex)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x00001701U;
+    SCE->REG_108H = 0x00000000U;
+    HW_SCE_p_func100(0xd8cc5954U, 0x83ae2a3aU, 0xf89036a8U, 0xaf96e5a7U);
+    HW_SCE_p_func103();
+    SCE->REG_104H = 0x00000052U;
+    SCE->REG_C4H = 0x01000c84U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    HW_SCE_p_func100(0xbd4fbe31U, 0x81679db9U, 0x8b01ddb6U, 0x53263891U);
+    SCE->REG_E0H = 0x80040000U;
+    SCE->REG_00H = 0x00008213U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_E0H = 0x81040000U;
+    SCE->REG_04H = 0x00000612U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[0] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[1] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[2] = SCE->REG_100H;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[3] = SCE->REG_100H;
+    HW_SCE_p_func100(0xb3b6f2a6U, 0xb0586158U, 0x9256ccf1U, 0xd63ae2a2U);
+    SCE->REG_A4H = 0x200c3b0dU;
+    SCE->REG_E0H = 0x81040000U;
+    SCE->REG_00H = 0x00001813U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    SCE->REG_A4H = 0x000c0b0cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x5737b943U);
+    HW_SCE_p_func103();
+    SCE->REG_104H = 0x00000052U;
+    SCE->REG_C4H = 0x01000c84U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_E0H = 0x80100000U;
+    SCE->REG_00H = 0x00008213U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_p_func100(0xc6069870U, 0x39159b6fU, 0x6bf8409fU, 0xa6340cb1U);
+    HW_SCE_p_func103();
+    SCE->REG_104H = 0x00000052U;
+    SCE->REG_C4H = 0x01000c84U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_00H = 0x00008213U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_p_func100(0x6377b1c4U, 0x4eb7aa8eU, 0x8dcaee68U, 0xda1ea520U);
+    HW_SCE_p_func103();
+    SCE->REG_104H = 0x00000052U;
+    SCE->REG_C4H = 0x01000c84U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_00H = 0x00008213U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_p_func100(0xfdd12cb4U, 0xe2c15388U, 0x86153aacU, 0x7cbb04dfU);
+    HW_SCE_p_func103();
+    SCE->REG_104H = 0x00000052U;
+    SCE->REG_C4H = 0x01000c84U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_00H = 0x00008213U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_p_func100(0xd6080230U, 0x5224cabcU, 0x95a86d89U, 0x62ecc03bU);
+    SCE->REG_B0H = 0x00000300U;
+    SCE->REG_A4H = 0x02e487bfU;
+    SCE->REG_E0H = 0x81100000U;
+    SCE->REG_00H = 0x00001843U;
+    SCE->REG_04H = 0x00000142U;
+    for(iLoop=4; iLoop<20; iLoop=iLoop+4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_KeyIndex[iLoop + 0] = SCE->REG_100H;
+        OutData_KeyIndex[iLoop + 1] = SCE->REG_100H;
+        OutData_KeyIndex[iLoop + 2] = SCE->REG_100H;
+        OutData_KeyIndex[iLoop + 3] = SCE->REG_100H;
+    }
+    HW_SCE_p_func100(0xc18b94b6U, 0x37ac8db8U, 0x8bd120aaU, 0x8d761229U);
+    SCE->REG_104H = 0x00000351U;
+    SCE->REG_A4H = 0x000009cdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_100H = change_endian_long(0x00000000U);
+    SCE->REG_100H = change_endian_long(0x00000004U);
+    SCE->REG_04H = 0x00000112U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_KeyIndex[20] = SCE->REG_100H;
+    OutData_KeyIndex[21] = SCE->REG_100H;
+    OutData_KeyIndex[22] = SCE->REG_100H;
+    OutData_KeyIndex[23] = SCE->REG_100H;
+    HW_SCE_p_func102(0x0091c2a0U, 0x8422f666U, 0x4c18775bU, 0x6d4da3f1U);
+    SCE->REG_1BCH = 0x00000040U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_18H_b.B12)
+    {
+        /* waiting */
+    }
+    return FSP_SUCCESS;
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_p17.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p41f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p41f.c
new file mode 100644
index 000000000..f24a71c93
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p41f.c
@@ -0,0 +1,296 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes128CmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataTLen, uint32_t *OutData_DataT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_p_func100(0xc5088878U, 0xd1dec1b4U, 0x55d5ce23U, 0x4e2fd2c8U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0x604c1827U, 0x7d1c29c0U, 0x087e5414U, 0xb61b49daU);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000002U))
+        {
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00400a84U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            HW_SCE_p_func101(0x1f5670b0U, 0x5a29b28bU, 0x9e079501U, 0xcf4fd055U);
+        }
+        else
+        {
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00500a84U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            HW_SCE_p_func101(0x9d3e98d0U, 0x303cb037U, 0x8cfbaeb2U, 0x1e5a5fc3U);
+        }
+        SCE->REG_A4H = 0x00040c05U;
+        SCE->REG_00H = 0x00001113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000001U))
+        {
+            HW_SCE_p_func100(0x522fdcccU, 0xd5217facU, 0x768fef5cU, 0x5d257f66U);
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x00000e95U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_Text[0];
+            SCE->REG_100H = InData_Text[1];
+            SCE->REG_100H = InData_Text[2];
+            SCE->REG_100H = InData_Text[3];
+            SCE->REG_04H = 0x00000112U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_DataT[0] = SCE->REG_100H;
+            OutData_DataT[1] = SCE->REG_100H;
+            OutData_DataT[2] = SCE->REG_100H;
+            OutData_DataT[3] = SCE->REG_100H;
+            HW_SCE_p_func102(0x8d120335U, 0xa8b323f8U, 0x23f1a63aU, 0x82b60252U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_SUCCESS;
+        }
+        else
+        {
+            SCE->REG_104H = 0x00000068U;
+            SCE->REG_E0H = 0x80010040U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_DataTLen[0];
+            SCE->REG_ECH = 0x3420a840U;
+            SCE->REG_ECH = 0x00000010U;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00260000U;
+            SCE->REG_ECH = 0x0000b460U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_ECH = 0x34202862U;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00260000U;
+            HW_SCE_p_func100(0xa34170f3U, 0x2ffafb72U, 0x6bd00efeU, 0x312ba181U);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_p_func102(0x594cfb93U, 0x8784511cU, 0xd6dc51f6U, 0x4d7b6d9cU);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_ERR_CRYPTO_SCE_FAIL;
+            }
+            else
+            {
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_A4H = 0x00000e95U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[0];
+                SCE->REG_100H = InData_Text[1];
+                SCE->REG_100H = InData_Text[2];
+                SCE->REG_100H = InData_Text[3];
+                SCE->REG_ECH = 0x00000821U;
+                SCE->REG_E0H = 0x80840001U;
+                SCE->REG_00H = 0x00008113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_ECH = 0x000034e2U;
+                SCE->REG_ECH = 0x000568e7U;
+                SCE->REG_ECH = 0x00026ce7U;
+                SCE->REG_ECH = 0x00003827U;
+                SCE->REG_ECH = 0x0000b4c0U;
+                SCE->REG_ECH = 0x00000020U;
+                SCE->REG_ECH = 0x00003402U;
+                SCE->REG_ECH = 0x00008c00U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x000028c0U;
+                SCE->REG_ECH = 0x00008cc0U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x00004406U;
+                SCE->REG_ECH = 0x00007421U;
+                SCE->REG_ECH = 0x00007821U;
+                SCE->REG_ECH = 0x00003c27U;
+                SCE->REG_ECH = 0x000034c2U;
+                SCE->REG_ECH = 0x0000a4c0U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x000568c6U;
+                SCE->REG_ECH = 0x000034e6U;
+                SCE->REG_ECH = 0x00026ce7U;
+                SCE->REG_ECH = 0x00000821U;
+                for (iLoop = 0; iLoop < 4; iLoop = iLoop+1)
+                {
+                    SCE->REG_ECH = 0x3420a8e0U;
+                    SCE->REG_ECH = 0x0000000dU;
+                    SCE->REG_ECH = 0x10003c27U;
+                    SCE->REG_ECH = 0x1000a4e0U;
+                    SCE->REG_ECH = 0x00000004U;
+                }
+                SCE->REG_A4H = 0x00040805U;
+                SCE->REG_E0H = 0x81840001U;
+                SCE->REG_00H = 0x00001813U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_A4H = 0x00900c05U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_DataT[0];
+                SCE->REG_100H = InData_DataT[1];
+                SCE->REG_100H = InData_DataT[2];
+                SCE->REG_100H = InData_DataT[3];
+                HW_SCE_p_func100(0x4da42f56U, 0x353cb5ffU, 0xf9d3580bU, 0xbb884079U);
+                SCE->REG_1CH = 0x00400000U;
+                SCE->REG_1D0H = 0x00000000U;
+                if (1U == (SCE->REG_1CH_b.B22))
+                {
+                    HW_SCE_p_func102(0x7ac07674U, 0xa2f236faU, 0xecf4dd04U, 0xe11bf76cU);
+                    SCE->REG_1BCH = 0x00000040U;
+                    /* WAIT_LOOP */
+                    while (0U != SCE->REG_18H_b.B12)
+                    {
+                        /* waiting */
+                    }
+                    return FSP_ERR_CRYPTO_SCE_AUTHENTICATION;
+                }
+                else
+                {
+                    HW_SCE_p_func102(0x3f36b8c5U, 0x7738b9a0U, 0x1ac6ed97U, 0xb9631f3aU);
+                    SCE->REG_1BCH = 0x00000040U;
+                    /* WAIT_LOOP */
+                    while (0U != SCE->REG_18H_b.B12)
+                    {
+                        /* waiting */
+                    }
+                    return FSP_SUCCESS;
+                }
+            }
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_p41f.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p41i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p41i.c
new file mode 100644
index 000000000..c7745e80d
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p41i.c
@@ -0,0 +1,230 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes128CmacInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x00004101U;
+    SCE->REG_108H = 0x00000000U;
+    SCE->REG_C4H = 0x200e1a0dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = S_RAM[16+0 + 0];
+    SCE->REG_100H = S_RAM[16+0 + 1];
+    SCE->REG_100H = S_RAM[16+0 + 2];
+    SCE->REG_100H = S_RAM[16+0 + 3];
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x80010000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyType[0];
+    SCE->REG_ECH = 0x38008800U;
+    SCE->REG_ECH = 0x00000001U;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00260000U;
+    HW_SCE_p_func100(0x4c8c17f9U, 0x4f145e2dU, 0x3e449da9U, 0xe68a4efaU);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0xc8b42b01U, 0x86ff1e56U, 0xcc4bdde5U, 0x44325d18U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        SCE->REG_ECH = 0x38000c00U;
+        SCE->REG_E0H = 0x00000080U;
+        SCE->REG_1CH = 0x00260000U;
+        HW_SCE_p_func100(0xaef123e5U, 0x99f132bdU, 0x499cb74fU, 0x5724ad28U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            SCE->REG_A4H = 0x200c3b0dU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_KeyIndex[0];
+            SCE->REG_100H = InData_KeyIndex[1];
+            SCE->REG_100H = InData_KeyIndex[2];
+            SCE->REG_100H = InData_KeyIndex[3];
+            SCE->REG_A4H = 0x000c0b0cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x4e2279dbU);
+            HW_SCE_p_func101(0xcdac5657U, 0x868badd8U, 0x268896c3U, 0x3ff0ec85U);
+        }
+        else
+        {
+            SCE->REG_A4H = 0x000c2b0dU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_KeyIndex[0];
+            SCE->REG_100H = InData_KeyIndex[1];
+            SCE->REG_100H = InData_KeyIndex[2];
+            SCE->REG_100H = InData_KeyIndex[3];
+            SCE->REG_A4H = 0x000c0b0cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x2a46c04bU);
+            HW_SCE_p_func101(0xdbb3fa6dU, 0xb4dcf810U, 0x6da52cfcU, 0xa0ebe44dU);
+        }
+        HW_SCE_p_func100(0x26d22a69U, 0x5814bebdU, 0x3798d7bfU, 0x009dda54U);
+        SCE->REG_A4H = 0x02f8073dU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_KeyIndex[4];
+        SCE->REG_100H = InData_KeyIndex[5];
+        SCE->REG_100H = InData_KeyIndex[6];
+        SCE->REG_100H = InData_KeyIndex[7];
+        SCE->REG_A4H = 0x000007bdU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_KeyIndex[8];
+        SCE->REG_100H = InData_KeyIndex[9];
+        SCE->REG_100H = InData_KeyIndex[10];
+        SCE->REG_100H = InData_KeyIndex[11];
+        SCE->REG_A4H = 0x00900c45U;
+        SCE->REG_00H = 0x00001113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        HW_SCE_p_func100(0x08e6cbadU, 0xa2a897f3U, 0xb1581051U, 0x4935d511U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_p_func102(0x1b0a1ce6U, 0x85f76c02U, 0xa92b23f5U, 0xe8065914U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+        }
+        else
+        {
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00040804U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            HW_SCE_p_func101(0x2f685bcdU, 0xae2171d8U, 0x1ae99d17U, 0x6d946e27U);
+            return FSP_SUCCESS;
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_p41i_r1.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p41u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p41u.c
new file mode 100644
index 000000000..ca3789342
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p41u.c
@@ -0,0 +1,97 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes128CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_A4H = 0x00000e16U;
+    for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+    }
+    HW_SCE_p_func205();//DisableINTEGRATE_WRRDYBinthisfunction.
+    HW_SCE_p_func101(0xb07c33a7U, 0x1722f796U, 0x49369365U, 0xeb81b013U);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_p41u.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p44f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p44f.c
new file mode 100644
index 000000000..80355b663
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p44f.c
@@ -0,0 +1,300 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes256CmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataTLen, uint32_t *OutData_DataT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_p_func100(0xb060c2f8U, 0xdbcb01b0U, 0x42d1ed81U, 0x1ec8fcdfU);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0xde4fd58aU, 0x1d440d06U, 0x9dfbd34aU, 0x3205bb06U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000002U))
+        {
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_B0H = 0x40000000U;
+            SCE->REG_A4H = 0x00408a84U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            HW_SCE_p_func101(0x53e25420U, 0x62bb6a2aU, 0xcaef5387U, 0x59eca0b3U);
+        }
+        else
+        {
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_B0H = 0x40000000U;
+            SCE->REG_A4H = 0x00508a84U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            HW_SCE_p_func101(0x4c8fb73cU, 0x95614b30U, 0x206dd170U, 0xd0c1f9b3U);
+        }
+        SCE->REG_A4H = 0x00040c05U;
+        SCE->REG_00H = 0x00001113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000001U))
+        {
+            HW_SCE_p_func100(0xe83564adU, 0xe80f1523U, 0xf4646700U, 0xa9a0af1cU);
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_B0H = 0x40000000U;
+            SCE->REG_A4H = 0x00008e95U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_Text[0];
+            SCE->REG_100H = InData_Text[1];
+            SCE->REG_100H = InData_Text[2];
+            SCE->REG_100H = InData_Text[3];
+            SCE->REG_04H = 0x00000112U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_DataT[0] = SCE->REG_100H;
+            OutData_DataT[1] = SCE->REG_100H;
+            OutData_DataT[2] = SCE->REG_100H;
+            OutData_DataT[3] = SCE->REG_100H;
+            HW_SCE_p_func102(0x3ba2c38aU, 0x1a0d8a8aU, 0x719eeaf4U, 0x3b9e14f4U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_SUCCESS;
+        }
+        else
+        {
+            SCE->REG_104H = 0x00000068U;
+            SCE->REG_E0H = 0x80010040U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_DataTLen[0];
+            SCE->REG_ECH = 0x3420a840U;
+            SCE->REG_ECH = 0x00000010U;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00260000U;
+            SCE->REG_ECH = 0x0000b460U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_ECH = 0x34202862U;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00260000U;
+            HW_SCE_p_func100(0x90a35862U, 0x922f2c16U, 0x13e5b621U, 0x5baf11faU);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_p_func102(0x42256946U, 0xb9eb52f1U, 0x7c111d83U, 0x248d2f49U);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_ERR_CRYPTO_SCE_FAIL;
+            }
+            else
+            {
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_B0H = 0x40000000U;
+                SCE->REG_A4H = 0x00008e95U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[0];
+                SCE->REG_100H = InData_Text[1];
+                SCE->REG_100H = InData_Text[2];
+                SCE->REG_100H = InData_Text[3];
+                SCE->REG_ECH = 0x00000821U;
+                SCE->REG_E0H = 0x80840001U;
+                SCE->REG_00H = 0x00008113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_ECH = 0x000034e2U;
+                SCE->REG_ECH = 0x000568e7U;
+                SCE->REG_ECH = 0x00026ce7U;
+                SCE->REG_ECH = 0x00003827U;
+                SCE->REG_ECH = 0x0000b4c0U;
+                SCE->REG_ECH = 0x00000020U;
+                SCE->REG_ECH = 0x00003402U;
+                SCE->REG_ECH = 0x00008c00U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x000028c0U;
+                SCE->REG_ECH = 0x00008cc0U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x00004406U;
+                SCE->REG_ECH = 0x00007421U;
+                SCE->REG_ECH = 0x00007821U;
+                SCE->REG_ECH = 0x00003c27U;
+                SCE->REG_ECH = 0x000034c2U;
+                SCE->REG_ECH = 0x0000a4c0U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x000568c6U;
+                SCE->REG_ECH = 0x000034e6U;
+                SCE->REG_ECH = 0x00026ce7U;
+                SCE->REG_ECH = 0x00000821U;
+                for (iLoop = 0; iLoop < 4; iLoop = iLoop+1)
+                {
+                    SCE->REG_ECH = 0x3420a8e0U;
+                    SCE->REG_ECH = 0x0000000dU;
+                    SCE->REG_ECH = 0x10003c27U;
+                    SCE->REG_ECH = 0x1000a4e0U;
+                    SCE->REG_ECH = 0x00000004U;
+                }
+                SCE->REG_A4H = 0x00040805U;
+                SCE->REG_E0H = 0x81840001U;
+                SCE->REG_00H = 0x00001813U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_A4H = 0x00900c05U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_DataT[0];
+                SCE->REG_100H = InData_DataT[1];
+                SCE->REG_100H = InData_DataT[2];
+                SCE->REG_100H = InData_DataT[3];
+                HW_SCE_p_func100(0xb4fbfc90U, 0x792ea3fdU, 0x15bf2b4bU, 0xabd75113U);
+                SCE->REG_1CH = 0x00400000U;
+                SCE->REG_1D0H = 0x00000000U;
+                if (1U == (SCE->REG_1CH_b.B22))
+                {
+                    HW_SCE_p_func102(0x3a920974U, 0x464a37ffU, 0x1c0f3aefU, 0x15a1f102U);
+                    SCE->REG_1BCH = 0x00000040U;
+                    /* WAIT_LOOP */
+                    while (0U != SCE->REG_18H_b.B12)
+                    {
+                        /* waiting */
+                    }
+                    return FSP_ERR_CRYPTO_SCE_AUTHENTICATION;
+                }
+                else
+                {
+                    HW_SCE_p_func102(0x4d5245f4U, 0x60f91572U, 0x0233abf5U, 0xcc1654b2U);
+                    SCE->REG_1BCH = 0x00000040U;
+                    /* WAIT_LOOP */
+                    while (0U != SCE->REG_18H_b.B12)
+                    {
+                        /* waiting */
+                    }
+                    return FSP_SUCCESS;
+                }
+            }
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_p44f.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p44i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p44i.c
new file mode 100644
index 000000000..dc4de95ca
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p44i.c
@@ -0,0 +1,241 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes256CmacInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x00004401U;
+    SCE->REG_108H = 0x00000000U;
+    SCE->REG_C4H = 0x200e1a0dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = S_RAM[16+0 + 0];
+    SCE->REG_100H = S_RAM[16+0 + 1];
+    SCE->REG_100H = S_RAM[16+0 + 2];
+    SCE->REG_100H = S_RAM[16+0 + 3];
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x80010000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyType[0];
+    SCE->REG_ECH = 0x38008800U;
+    SCE->REG_ECH = 0x00000001U;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00260000U;
+    HW_SCE_p_func100(0x9704e567U, 0xca230276U, 0x71d046c7U, 0x81185820U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0xee522da9U, 0xaa8ab544U, 0xfcec3384U, 0xe0bd90fcU);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        SCE->REG_ECH = 0x38000c00U;
+        SCE->REG_E0H = 0x00000080U;
+        SCE->REG_1CH = 0x00260000U;
+        HW_SCE_p_func100(0xe10b720cU, 0xe032f2c7U, 0x45a49807U, 0xd4ef83e7U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            SCE->REG_A4H = 0x200c3b0dU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_KeyIndex[0];
+            SCE->REG_100H = InData_KeyIndex[1];
+            SCE->REG_100H = InData_KeyIndex[2];
+            SCE->REG_100H = InData_KeyIndex[3];
+            SCE->REG_A4H = 0x000c0b0cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x6e78d475U);
+            HW_SCE_p_func101(0xa1ddd48dU, 0xf117b9c4U, 0xebd3e1cbU, 0xc20887afU);
+        }
+        else
+        {
+            SCE->REG_A4H = 0x000c2b0dU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_KeyIndex[0];
+            SCE->REG_100H = InData_KeyIndex[1];
+            SCE->REG_100H = InData_KeyIndex[2];
+            SCE->REG_100H = InData_KeyIndex[3];
+            SCE->REG_A4H = 0x000c0b0cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x85d04999U);
+            HW_SCE_p_func101(0x1b93fd9eU, 0x451b51c6U, 0x6f665bc3U, 0x5d1216ffU);
+        }
+        HW_SCE_p_func100(0x25ea0ad0U, 0x18bd965bU, 0x14d547e9U, 0x8acb3728U);
+        SCE->REG_A4H = 0x02f8073dU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_KeyIndex[4];
+        SCE->REG_100H = InData_KeyIndex[5];
+        SCE->REG_100H = InData_KeyIndex[6];
+        SCE->REG_100H = InData_KeyIndex[7];
+        HW_SCE_p_func100(0x05a03ed4U, 0x1d8b5895U, 0x331784e3U, 0x37f27fefU);
+        SCE->REG_A4H = 0x00f9073dU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_KeyIndex[8];
+        SCE->REG_100H = InData_KeyIndex[9];
+        SCE->REG_100H = InData_KeyIndex[10];
+        SCE->REG_100H = InData_KeyIndex[11];
+        SCE->REG_A4H = 0x000007bdU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_KeyIndex[12];
+        SCE->REG_100H = InData_KeyIndex[13];
+        SCE->REG_100H = InData_KeyIndex[14];
+        SCE->REG_100H = InData_KeyIndex[15];
+        SCE->REG_A4H = 0x00900c45U;
+        SCE->REG_00H = 0x00001113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        HW_SCE_p_func100(0x267503feU, 0xb8823ab5U, 0xbd416f15U, 0x57676869U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_p_func102(0x113e0f24U, 0x03097a01U, 0x8a9b246dU, 0x1dce7c1fU);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+        }
+        else
+        {
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00040804U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            HW_SCE_p_func101(0x1c627e73U, 0x41ec6829U, 0x2f91440bU, 0xb5650faeU);
+            return FSP_SUCCESS;
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_p44i_r1.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p44u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p44u.c
new file mode 100644
index 000000000..e2bd51c9c
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p44u.c
@@ -0,0 +1,98 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes256CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_B0H = 0x40000000U;
+    SCE->REG_A4H = 0x00008e16U;
+    for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+    }
+    HW_SCE_p_func205();//DisableINTEGRATE_WRRDYBinthisfunction.
+    HW_SCE_p_func101(0xdeb5244bU, 0x781fdc27U, 0xa396d1f5U, 0x8df233b2U);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_p44u.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p95f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p95f.c
new file mode 100644
index 000000000..c8e345b82
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p95f.c
@@ -0,0 +1,219 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes128CcmEncryptFinalSub(uint32_t *InData_TextLen, uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t *OutData_MAC)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_p_func100(0xffe18b6dU, 0xf01a8cd5U, 0x178773d5U, 0x707f81acU);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0x0838f761U, 0x482169ddU, 0x56189c24U, 0x48c876c5U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        SCE->REG_104H = 0x00000068U;
+        SCE->REG_E0H = 0x80010000U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_TextLen[0];
+        SCE->REG_ECH = 0x00008c00U;
+        SCE->REG_ECH = 0x0000000fU;
+        SCE->REG_ECH = 0x38008800U;
+        SCE->REG_ECH = 0x00000000U;
+        SCE->REG_E0H = 0x00000080U;
+        SCE->REG_1CH = 0x00A60000U;
+        HW_SCE_p_func100(0xecefaa76U, 0x1a6588d8U, 0x1a740031U, 0xff914c3aU);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x00e007b5U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_Text[0];
+            SCE->REG_100H = InData_Text[1];
+            SCE->REG_100H = InData_Text[2];
+            SCE->REG_100H = InData_Text[3];
+            SCE->REG_ECH = 0x0000b420U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_E0H = 0x80840001U;
+            SCE->REG_00H = 0x00008113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_ECH = 0x00000821U;
+            SCE->REG_ECH = 0x0000a400U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_ECH = 0x0000b7e0U;
+            SCE->REG_ECH = 0x00000080U;
+            for (iLoop = 0; iLoop < 16; iLoop = iLoop+1)
+            {
+                SCE->REG_ECH = 0x3c002be0U;
+                SCE->REG_ECH = 0x12003c3fU;
+                SCE->REG_ECH = 0x00002fe0U;
+            }
+            HW_SCE_p_func100(0xf1d0cda1U, 0x8977e121U, 0x097d31ebU, 0x8db58aabU);
+            SCE->REG_ECH = 0x0000b420U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_E0H = 0x81840001U;
+            SCE->REG_04H = 0x00000612U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[0] = SCE->REG_100H;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[1] = SCE->REG_100H;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[2] = SCE->REG_100H;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[3] = SCE->REG_100H;
+            HW_SCE_p_func101(0x0c1f9cecU, 0xb5aa7f31U, 0x9de4949dU, 0xf8cc5ae0U);
+        }
+        else
+        {
+            HW_SCE_p_func101(0x6e381eb1U, 0x513ee58eU, 0x5b0ba0f1U, 0x422259bdU);
+        }
+        SCE->REG_104H = 0x00000051U;
+        SCE->REG_A4H = 0x01000c84U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        HW_SCE_p_func100(0x747e423dU, 0xd5ef4bdeU, 0x35942bffU, 0x82648969U);
+        SCE->REG_A4H = 0x000009c5U;
+        SCE->REG_00H = 0x00001113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_04H = 0x00000112U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_MAC[0] = SCE->REG_100H;
+        OutData_MAC[1] = SCE->REG_100H;
+        OutData_MAC[2] = SCE->REG_100H;
+        OutData_MAC[3] = SCE->REG_100H;
+        HW_SCE_p_func102(0xabdc57b2U, 0xc3a63efbU, 0x7f2d53bbU, 0xf62f60f7U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_SUCCESS;
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_p95f.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p95i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p95i.c
new file mode 100644
index 000000000..abf261c58
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p95i.c
@@ -0,0 +1,289 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes128CcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x00009501U;
+    SCE->REG_108H = 0x00000000U;
+    SCE->REG_C4H = 0x200e1a0dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = S_RAM[16+0 + 0];
+    SCE->REG_100H = S_RAM[16+0 + 1];
+    SCE->REG_100H = S_RAM[16+0 + 2];
+    SCE->REG_100H = S_RAM[16+0 + 3];
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x80010000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyType[0];
+    SCE->REG_ECH = 0x38008800U;
+    SCE->REG_ECH = 0x00000001U;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00260000U;
+    HW_SCE_p_func100(0x9d20f0e9U, 0xe2341535U, 0x69244f2bU, 0xf22f1e66U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0x36392c43U, 0x43e699deU, 0x9504e1a4U, 0x92b678e3U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        SCE->REG_ECH = 0x38000c00U;
+        SCE->REG_E0H = 0x00000080U;
+        SCE->REG_1CH = 0x00260000U;
+        HW_SCE_p_func100(0x5b156992U, 0xd4913199U, 0xf2bc3346U, 0x852a3499U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            SCE->REG_A4H = 0x200c3b0dU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_KeyIndex[0];
+            SCE->REG_100H = InData_KeyIndex[1];
+            SCE->REG_100H = InData_KeyIndex[2];
+            SCE->REG_100H = InData_KeyIndex[3];
+            SCE->REG_A4H = 0x000c0b0cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x4e2279dbU);
+            HW_SCE_p_func101(0xbbf5ca5cU, 0x1cce52fbU, 0xbd50a186U, 0xc2f6f7a0U);
+        }
+        else
+        {
+            SCE->REG_A4H = 0x000c2b0dU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_KeyIndex[0];
+            SCE->REG_100H = InData_KeyIndex[1];
+            SCE->REG_100H = InData_KeyIndex[2];
+            SCE->REG_100H = InData_KeyIndex[3];
+            SCE->REG_A4H = 0x000c0b0cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x2a46c04bU);
+            HW_SCE_p_func101(0xd64721c9U, 0x0e7978abU, 0x287808b4U, 0xce3632ddU);
+        }
+        HW_SCE_p_func100(0x6448a962U, 0xe0ec0bfcU, 0x7e28faadU, 0x6b7949fdU);
+        SCE->REG_A4H = 0x02f8073dU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_KeyIndex[4];
+        SCE->REG_100H = InData_KeyIndex[5];
+        SCE->REG_100H = InData_KeyIndex[6];
+        SCE->REG_100H = InData_KeyIndex[7];
+        SCE->REG_A4H = 0x000007bdU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_KeyIndex[8];
+        SCE->REG_100H = InData_KeyIndex[9];
+        SCE->REG_100H = InData_KeyIndex[10];
+        SCE->REG_100H = InData_KeyIndex[11];
+        SCE->REG_A4H = 0x00900c45U;
+        SCE->REG_00H = 0x00001113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        HW_SCE_p_func100(0x83183375U, 0xe3a8195bU, 0xb345c9f8U, 0xa44a7a4aU);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_p_func102(0xbf233080U, 0x46c66151U, 0xd5f2a9a0U, 0x7fbf63daU);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+        }
+        else
+        {
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x00040885U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_IV[0];
+            SCE->REG_100H = InData_IV[1];
+            SCE->REG_100H = InData_IV[2];
+            SCE->REG_100H = InData_IV[3];
+            SCE->REG_A4H = 0x00060805U;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00000734U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00050804U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_104H = 0x000000b1U;
+            SCE->REG_A4H = 0x00e00806U;
+            for (iLoop = 0; iLoop < Header_Len; iLoop = iLoop + 4)
+            {
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Header[iLoop + 0];
+                SCE->REG_100H = InData_Header[iLoop + 1];
+                SCE->REG_100H = InData_Header[iLoop + 2];
+                SCE->REG_100H = InData_Header[iLoop + 3];
+            }
+            HW_SCE_p_func205();//DisableINTEGRATE_WRRDYBinthisfunction.
+            HW_SCE_p_func100(0xc447366dU, 0x700b60cdU, 0xe90eab86U, 0x716a5accU);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_p_func102(0x8cdfc28aU, 0xbb40f7f7U, 0x0d20d3dfU, 0xedee2be1U);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_ERR_CRYPTO_SCE_FAIL;
+            }
+            else
+            {
+                HW_SCE_p_func101(0x5e7a4476U, 0x86a9df5bU, 0xc4c7f252U, 0x27912b47U);
+                return FSP_SUCCESS;
+            }
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_p95i_r1.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p95u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p95u.c
new file mode 100644
index 000000000..32ec47dca
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p95u.c
@@ -0,0 +1,126 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes128CcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_p_func100(0x03046333U, 0x630db336U, 0xaa1d854bU, 0x2136c4b8U);
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_A4H = 0x00e007b6U;
+    SCE->REG_04H = 0x0000c100U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_Text[0];
+    SCE->REG_100H = InData_Text[1];
+    SCE->REG_100H = InData_Text[2];
+    SCE->REG_100H = InData_Text[3];
+    for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    }
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H;
+    OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H;
+    OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H;
+    OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H;
+    HW_SCE_p_func207();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+    HW_SCE_p_func101(0x39f1226bU, 0x0745e712U, 0x822d3c68U, 0x48c98a4aU);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_p95u.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p98f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p98f.c
new file mode 100644
index 000000000..5ac3cf324
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p98f.c
@@ -0,0 +1,312 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes128CcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_TextLen, uint32_t *InData_MAC, uint32_t *InData_MACLength, uint32_t *OutData_Text)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_p_func100(0x426011c9U, 0xbe9d6415U, 0xb3191a57U, 0x727c195fU);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0xbe3ad49fU, 0x02fb43eaU, 0x077ed144U, 0x09d56126U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        SCE->REG_104H = 0x00000068U;
+        SCE->REG_E0H = 0x80010140U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_MACLength[0];
+        SCE->REG_ECH = 0x38008940U;
+        SCE->REG_ECH = 0x00000000U;
+        SCE->REG_E0H = 0x00000080U;
+        SCE->REG_1CH = 0x00260000U;
+        SCE->REG_ECH = 0x0000b7e0U;
+        SCE->REG_ECH = 0x00000010U;
+        SCE->REG_ECH = 0x34202beaU;
+        SCE->REG_E0H = 0x00000080U;
+        SCE->REG_1CH = 0x00260000U;
+        HW_SCE_p_func100(0x015dc501U, 0xe503799eU, 0xe740a209U, 0x1ca184a1U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_p_func102(0xad04eb0fU, 0x04543909U, 0x331be2cfU, 0x74fe7e77U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            SCE->REG_104H = 0x00000068U;
+            SCE->REG_E0H = 0x80010000U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_TextLen[0];
+            SCE->REG_ECH = 0x00008c00U;
+            SCE->REG_ECH = 0x0000000fU;
+            SCE->REG_ECH = 0x38008800U;
+            SCE->REG_ECH = 0x00000000U;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00A60000U;
+            HW_SCE_p_func100(0xa3ba947aU, 0xae0d6f09U, 0x7546b011U, 0x9ec176f9U);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_A4H = 0x000007b5U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[0];
+                SCE->REG_100H = InData_Text[1];
+                SCE->REG_100H = InData_Text[2];
+                SCE->REG_100H = InData_Text[3];
+                SCE->REG_ECH = 0x0000b420U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_E0H = 0x80840001U;
+                SCE->REG_00H = 0x00008113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_ECH = 0x00000821U;
+                SCE->REG_ECH = 0x0000a400U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_ECH = 0x0000b7e0U;
+                SCE->REG_ECH = 0x00000080U;
+                for (iLoop = 0; iLoop < 16; iLoop = iLoop+1)
+                {
+                    SCE->REG_ECH = 0x3c002be0U;
+                    SCE->REG_ECH = 0x12003c3fU;
+                    SCE->REG_ECH = 0x00002fe0U;
+                }
+                HW_SCE_p_func100(0x06177f6fU, 0xc65172ebU, 0xd699c48eU, 0xeff05c3cU);
+                SCE->REG_ECH = 0x0000b420U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_E0H = 0x81840001U;
+                SCE->REG_04H = 0x00000612U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[1] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[2] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[3] = SCE->REG_100H;
+                SCE->REG_A4H = 0x00000e55U;
+                SCE->REG_E0H = 0x81840001U;
+                SCE->REG_00H = 0x00001813U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                HW_SCE_p_func101(0xaf7abe4cU, 0x44e05732U, 0xe4c8b5caU, 0x05aef66dU);
+            }
+            else
+            {
+                HW_SCE_p_func101(0x2db599e4U, 0x94ada8adU, 0xcfe52db5U, 0xd2c089bcU);
+            }
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00000cc4U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_A4H = 0x010007b5U;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_ECH = 0x0000b420U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_E0H = 0x80840001U;
+            SCE->REG_00H = 0x00008113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_ECH = 0x0000a540U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_ECH = 0x0000b7e0U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_ECH = 0x00000821U;
+            for (iLoop = 0; iLoop < 16; iLoop = iLoop+1)
+            {
+                SCE->REG_ECH = 0x3c002beaU;
+                SCE->REG_ECH = 0x12003c3fU;
+                SCE->REG_ECH = 0x00002fe0U;
+            }
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x00050805U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_MAC[0];
+            SCE->REG_100H = InData_MAC[1];
+            SCE->REG_100H = InData_MAC[2];
+            SCE->REG_100H = InData_MAC[3];
+            SCE->REG_A4H = 0x00900c45U;
+            SCE->REG_ECH = 0x0000b420U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_E0H = 0x81840001U;
+            SCE->REG_00H = 0x00001813U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_A4H = 0x00000000U;
+            HW_SCE_p_func100(0xc5f0b0e0U, 0x7e7d46c4U, 0x8b37380bU, 0x03edabfaU);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_p_func102(0x99c68240U, 0xb50e9c49U, 0xf671303bU, 0x097cb1ddU);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_ERR_CRYPTO_SCE_FAIL;
+            }
+            else
+            {
+                HW_SCE_p_func102(0x4c835987U, 0x4ca4df76U, 0x9fe04444U, 0xb19781d2U);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_SUCCESS;
+            }
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_p98f.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p98i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p98i.c
new file mode 100644
index 000000000..246f76ab1
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p98i.c
@@ -0,0 +1,289 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes128CcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x00009801U;
+    SCE->REG_108H = 0x00000000U;
+    SCE->REG_C4H = 0x200e1a0dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = S_RAM[16+0 + 0];
+    SCE->REG_100H = S_RAM[16+0 + 1];
+    SCE->REG_100H = S_RAM[16+0 + 2];
+    SCE->REG_100H = S_RAM[16+0 + 3];
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x80010000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyType[0];
+    SCE->REG_ECH = 0x38008800U;
+    SCE->REG_ECH = 0x00000001U;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00260000U;
+    HW_SCE_p_func100(0x182e6b78U, 0xf7291d77U, 0xcccf58efU, 0x6df98771U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0xbe994366U, 0x31b402a9U, 0x33744887U, 0xdafbdbe4U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        SCE->REG_ECH = 0x38000c00U;
+        SCE->REG_E0H = 0x00000080U;
+        SCE->REG_1CH = 0x00260000U;
+        HW_SCE_p_func100(0xc9c66796U, 0xf904b8a8U, 0x23403b46U, 0xeb519bdfU);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            SCE->REG_A4H = 0x200c3b0dU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_KeyIndex[0];
+            SCE->REG_100H = InData_KeyIndex[1];
+            SCE->REG_100H = InData_KeyIndex[2];
+            SCE->REG_100H = InData_KeyIndex[3];
+            SCE->REG_A4H = 0x000c0b0cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x4e2279dbU);
+            HW_SCE_p_func101(0xb1e5d663U, 0xd54a72d9U, 0xc0818699U, 0x7c0a56cbU);
+        }
+        else
+        {
+            SCE->REG_A4H = 0x000c2b0dU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_KeyIndex[0];
+            SCE->REG_100H = InData_KeyIndex[1];
+            SCE->REG_100H = InData_KeyIndex[2];
+            SCE->REG_100H = InData_KeyIndex[3];
+            SCE->REG_A4H = 0x000c0b0cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x2a46c04bU);
+            HW_SCE_p_func101(0x0de918cfU, 0xec809b22U, 0xade5c4c3U, 0x8fe4e850U);
+        }
+        HW_SCE_p_func100(0xd6c5d532U, 0xd4c3259bU, 0x6ab17090U, 0x84645174U);
+        SCE->REG_A4H = 0x02f8073dU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_KeyIndex[4];
+        SCE->REG_100H = InData_KeyIndex[5];
+        SCE->REG_100H = InData_KeyIndex[6];
+        SCE->REG_100H = InData_KeyIndex[7];
+        SCE->REG_A4H = 0x000007bdU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_KeyIndex[8];
+        SCE->REG_100H = InData_KeyIndex[9];
+        SCE->REG_100H = InData_KeyIndex[10];
+        SCE->REG_100H = InData_KeyIndex[11];
+        SCE->REG_A4H = 0x00900c45U;
+        SCE->REG_00H = 0x00001113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        HW_SCE_p_func100(0x6682a37dU, 0x201922aeU, 0xc1632d7bU, 0x4c3a900eU);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_p_func102(0x69ca8b59U, 0x252cc969U, 0x9e8a6d63U, 0x769b49a8U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+        }
+        else
+        {
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x00040885U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_IV[0];
+            SCE->REG_100H = InData_IV[1];
+            SCE->REG_100H = InData_IV[2];
+            SCE->REG_100H = InData_IV[3];
+            SCE->REG_A4H = 0x00060805U;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00000734U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00050804U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_104H = 0x000000b1U;
+            SCE->REG_A4H = 0x00f00806U;
+            for (iLoop = 0; iLoop < Header_Len; iLoop = iLoop + 4)
+            {
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Header[iLoop + 0];
+                SCE->REG_100H = InData_Header[iLoop + 1];
+                SCE->REG_100H = InData_Header[iLoop + 2];
+                SCE->REG_100H = InData_Header[iLoop + 3];
+            }
+            HW_SCE_p_func205();//DisableINTEGRATE_WRRDYBinthisfunction.
+            HW_SCE_p_func100(0xa46b2c64U, 0x5f447fbfU, 0xfc2899e1U, 0xbc0ac9a8U);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_p_func102(0x8f66ceacU, 0x56f6c3efU, 0x4b0e031cU, 0xbc58860dU);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_ERR_CRYPTO_SCE_FAIL;
+            }
+            else
+            {
+                HW_SCE_p_func101(0x90d32cddU, 0x6b8bf9e9U, 0x1b1b23fcU, 0xc9964b0fU);
+                return FSP_SUCCESS;
+            }
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_p98i_r1.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p98u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p98u.c
new file mode 100644
index 000000000..fcbe9cdff
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p98u.c
@@ -0,0 +1,126 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes128CcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_p_func100(0x99cd889dU, 0x10823a7aU, 0xb2aa16b7U, 0x978714b6U);
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_A4H = 0x00f007b6U;
+    SCE->REG_04H = 0x0000c100U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_Text[0];
+    SCE->REG_100H = InData_Text[1];
+    SCE->REG_100H = InData_Text[2];
+    SCE->REG_100H = InData_Text[3];
+    for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    }
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H;
+    OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H;
+    OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H;
+    OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H;
+    HW_SCE_p_func207();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+    HW_SCE_p_func101(0xf22d9480U, 0x36579c2dU, 0x8ca47c8aU, 0x155c87d3U);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_p98u.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa1f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa1f.c
new file mode 100644
index 000000000..146b1e558
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa1f.c
@@ -0,0 +1,221 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes256CcmEncryptFinalSub(uint32_t *InData_TextLen, uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t *OutData_MAC)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_p_func100(0xb33a4fc9U, 0x4e3c89a6U, 0x3a15ce49U, 0x29492865U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0x8564e2e9U, 0x6d0dccd4U, 0x6c2e0597U, 0x3110c7ebU);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        SCE->REG_104H = 0x00000068U;
+        SCE->REG_E0H = 0x80010000U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_TextLen[0];
+        SCE->REG_ECH = 0x00008c00U;
+        SCE->REG_ECH = 0x0000000fU;
+        SCE->REG_ECH = 0x38008800U;
+        SCE->REG_ECH = 0x00000000U;
+        SCE->REG_E0H = 0x00000080U;
+        SCE->REG_1CH = 0x00A60000U;
+        HW_SCE_p_func100(0xd1a6e034U, 0xdb9d1d41U, 0x4fb70c49U, 0xaaadf399U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_B0H = 0x40000000U;
+            SCE->REG_A4H = 0x00e087b5U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_Text[0];
+            SCE->REG_100H = InData_Text[1];
+            SCE->REG_100H = InData_Text[2];
+            SCE->REG_100H = InData_Text[3];
+            SCE->REG_ECH = 0x0000b420U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_E0H = 0x80840001U;
+            SCE->REG_00H = 0x00008113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_ECH = 0x00000821U;
+            SCE->REG_ECH = 0x0000a400U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_ECH = 0x0000b7e0U;
+            SCE->REG_ECH = 0x00000080U;
+            for (iLoop = 0; iLoop < 16; iLoop = iLoop+1)
+            {
+                SCE->REG_ECH = 0x3c002be0U;
+                SCE->REG_ECH = 0x12003c3fU;
+                SCE->REG_ECH = 0x00002fe0U;
+            }
+            HW_SCE_p_func100(0x5348d785U, 0x5160a826U, 0xdaf71142U, 0x5c7152f0U);
+            SCE->REG_ECH = 0x0000b420U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_E0H = 0x81840001U;
+            SCE->REG_04H = 0x00000612U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[0] = SCE->REG_100H;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[1] = SCE->REG_100H;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[2] = SCE->REG_100H;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[3] = SCE->REG_100H;
+            HW_SCE_p_func101(0x7e13f5cdU, 0xa0044347U, 0xa12428c0U, 0xc30ecc67U);
+        }
+        else
+        {
+            HW_SCE_p_func101(0x12b51c08U, 0x092ff296U, 0xe0657e0cU, 0xd3693a67U);
+        }
+        SCE->REG_104H = 0x00000051U;
+        SCE->REG_A4H = 0x01000c84U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        HW_SCE_p_func100(0x915d0a1cU, 0xa7ba5a5dU, 0xad777b3cU, 0x20869eb6U);
+        SCE->REG_B0H = 0x40000000U;
+        SCE->REG_A4H = 0x000089c5U;
+        SCE->REG_00H = 0x00001113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_04H = 0x00000112U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_MAC[0] = SCE->REG_100H;
+        OutData_MAC[1] = SCE->REG_100H;
+        OutData_MAC[2] = SCE->REG_100H;
+        OutData_MAC[3] = SCE->REG_100H;
+        HW_SCE_p_func102(0x5120d867U, 0xdb89ce50U, 0xf4c0e0e8U, 0x1a49e472U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_SUCCESS;
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pa1f.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa1i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa1i.c
new file mode 100644
index 000000000..41a994c93
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa1i.c
@@ -0,0 +1,301 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes256CcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x0000a101U;
+    SCE->REG_108H = 0x00000000U;
+    SCE->REG_C4H = 0x200e1a0dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = S_RAM[16+0 + 0];
+    SCE->REG_100H = S_RAM[16+0 + 1];
+    SCE->REG_100H = S_RAM[16+0 + 2];
+    SCE->REG_100H = S_RAM[16+0 + 3];
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x80010000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyType[0];
+    SCE->REG_ECH = 0x38008800U;
+    SCE->REG_ECH = 0x00000001U;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00260000U;
+    HW_SCE_p_func100(0x9a9c43feU, 0x5e0e6538U, 0x38238a7aU, 0x9030f158U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0xc89c5bcdU, 0x31125123U, 0xe1963149U, 0x63dc28e6U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        SCE->REG_ECH = 0x38000c00U;
+        SCE->REG_E0H = 0x00000080U;
+        SCE->REG_1CH = 0x00260000U;
+        HW_SCE_p_func100(0x1f12a749U, 0x9055b744U, 0x697f74abU, 0x9013242bU);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            SCE->REG_A4H = 0x200c3b0dU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_KeyIndex[0];
+            SCE->REG_100H = InData_KeyIndex[1];
+            SCE->REG_100H = InData_KeyIndex[2];
+            SCE->REG_100H = InData_KeyIndex[3];
+            SCE->REG_A4H = 0x000c0b0cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x6e78d475U);
+            HW_SCE_p_func101(0x5c9e4642U, 0x2ccc5f5aU, 0xae8712b9U, 0x7bdccbd6U);
+        }
+        else
+        {
+            SCE->REG_A4H = 0x000c2b0dU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_KeyIndex[0];
+            SCE->REG_100H = InData_KeyIndex[1];
+            SCE->REG_100H = InData_KeyIndex[2];
+            SCE->REG_100H = InData_KeyIndex[3];
+            SCE->REG_A4H = 0x000c0b0cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x85d04999U);
+            HW_SCE_p_func101(0xa0ae06d4U, 0xce4892daU, 0x434f3b6eU, 0x4bd1030cU);
+        }
+        HW_SCE_p_func100(0xfc9efc29U, 0x7017dc91U, 0xfcafb02aU, 0x968222fbU);
+        SCE->REG_A4H = 0x02f8073dU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_KeyIndex[4];
+        SCE->REG_100H = InData_KeyIndex[5];
+        SCE->REG_100H = InData_KeyIndex[6];
+        SCE->REG_100H = InData_KeyIndex[7];
+        HW_SCE_p_func100(0x2aff4404U, 0x98a3a205U, 0x3abed0caU, 0x22414c70U);
+        SCE->REG_A4H = 0x00f9073dU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_KeyIndex[8];
+        SCE->REG_100H = InData_KeyIndex[9];
+        SCE->REG_100H = InData_KeyIndex[10];
+        SCE->REG_100H = InData_KeyIndex[11];
+        SCE->REG_A4H = 0x000007bdU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_KeyIndex[12];
+        SCE->REG_100H = InData_KeyIndex[13];
+        SCE->REG_100H = InData_KeyIndex[14];
+        SCE->REG_100H = InData_KeyIndex[15];
+        SCE->REG_A4H = 0x00900c45U;
+        SCE->REG_00H = 0x00001113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        HW_SCE_p_func100(0x890a82f1U, 0x59e16f61U, 0xfe96941dU, 0x16f99d15U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_p_func102(0x577f762bU, 0x315b65a6U, 0xc09a2e66U, 0xf6417053U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+        }
+        else
+        {
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x00040885U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_IV[0];
+            SCE->REG_100H = InData_IV[1];
+            SCE->REG_100H = InData_IV[2];
+            SCE->REG_100H = InData_IV[3];
+            SCE->REG_A4H = 0x00060805U;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00000734U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00050804U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_104H = 0x000000b1U;
+            SCE->REG_B0H = 0x40000000U;
+            SCE->REG_A4H = 0x00058e56U;
+            for (iLoop = 0; iLoop < Header_Len; iLoop = iLoop + 4)
+            {
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Header[iLoop + 0];
+                SCE->REG_100H = InData_Header[iLoop + 1];
+                SCE->REG_100H = InData_Header[iLoop + 2];
+                SCE->REG_100H = InData_Header[iLoop + 3];
+            }
+            HW_SCE_p_func205();//DisableINTEGRATE_WRRDYBinthisfunction.
+            HW_SCE_p_func100(0xe88b4351U, 0x3c3372c6U, 0xc9ad9969U, 0xd2a50734U);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_p_func102(0x8f195136U, 0x57780f0cU, 0xaff7751cU, 0xa0925788U);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_ERR_CRYPTO_SCE_FAIL;
+            }
+            else
+            {
+                HW_SCE_p_func101(0xb6d1093aU, 0x7d69a0eaU, 0x501abbb3U, 0xa5000b2dU);
+                return FSP_SUCCESS;
+            }
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pa1i_r1.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa1u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa1u.c
new file mode 100644
index 000000000..1c3230ab8
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa1u.c
@@ -0,0 +1,127 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes256CcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_p_func100(0xc1ac76aeU, 0x77bb0649U, 0x387127ceU, 0x775e0543U);
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_B0H = 0x40000000U;
+    SCE->REG_A4H = 0x00e087b6U;
+    SCE->REG_04H = 0x0000c100U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_Text[0];
+    SCE->REG_100H = InData_Text[1];
+    SCE->REG_100H = InData_Text[2];
+    SCE->REG_100H = InData_Text[3];
+    for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    }
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H;
+    OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H;
+    OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H;
+    OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H;
+    HW_SCE_p_func207();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+    HW_SCE_p_func101(0xb3a2a8ecU, 0x3085da6aU, 0xc4e7fe61U, 0x2c0bf07dU);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pa1u.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa4f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa4f.c
new file mode 100644
index 000000000..af8512fea
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa4f.c
@@ -0,0 +1,315 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes256CcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_TextLen, uint32_t *InData_MAC, uint32_t *InData_MACLength, uint32_t *OutData_Text)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_p_func100(0xb48ffb6eU, 0x54a1f1ddU, 0x3a90117fU, 0xdb6d35a4U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0x81b92821U, 0x86b71c7cU, 0xa84bb045U, 0x73a86808U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        SCE->REG_104H = 0x00000068U;
+        SCE->REG_E0H = 0x80010140U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_MACLength[0];
+        SCE->REG_ECH = 0x38008940U;
+        SCE->REG_ECH = 0x00000000U;
+        SCE->REG_E0H = 0x00000080U;
+        SCE->REG_1CH = 0x00260000U;
+        SCE->REG_ECH = 0x0000b7e0U;
+        SCE->REG_ECH = 0x00000010U;
+        SCE->REG_ECH = 0x34202beaU;
+        SCE->REG_E0H = 0x00000080U;
+        SCE->REG_1CH = 0x00260000U;
+        HW_SCE_p_func100(0xfb9c1041U, 0x4036e7e6U, 0x3f42eaf0U, 0xbb3895e6U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_p_func102(0xfd7a2e07U, 0x50b10703U, 0xac8761d4U, 0x815e56ffU);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            SCE->REG_104H = 0x00000068U;
+            SCE->REG_E0H = 0x80010000U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_TextLen[0];
+            SCE->REG_ECH = 0x00008c00U;
+            SCE->REG_ECH = 0x0000000fU;
+            SCE->REG_ECH = 0x38008800U;
+            SCE->REG_ECH = 0x00000000U;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00A60000U;
+            HW_SCE_p_func100(0xed1573c8U, 0xece58b76U, 0xd3996d06U, 0x1caf7ecdU);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_B0H = 0x40000000U;
+                SCE->REG_A4H = 0x000087b5U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[0];
+                SCE->REG_100H = InData_Text[1];
+                SCE->REG_100H = InData_Text[2];
+                SCE->REG_100H = InData_Text[3];
+                SCE->REG_ECH = 0x0000b420U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_E0H = 0x80840001U;
+                SCE->REG_00H = 0x00008113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_ECH = 0x00000821U;
+                SCE->REG_ECH = 0x0000a400U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_ECH = 0x0000b7e0U;
+                SCE->REG_ECH = 0x00000080U;
+                for (iLoop = 0; iLoop < 16; iLoop = iLoop+1)
+                {
+                    SCE->REG_ECH = 0x3c002be0U;
+                    SCE->REG_ECH = 0x12003c3fU;
+                    SCE->REG_ECH = 0x00002fe0U;
+                }
+                HW_SCE_p_func100(0x3d81fda8U, 0x84486d0eU, 0x1ae4ceecU, 0x55c3b41aU);
+                SCE->REG_ECH = 0x0000b420U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_E0H = 0x81840001U;
+                SCE->REG_04H = 0x00000612U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[1] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[2] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[3] = SCE->REG_100H;
+                SCE->REG_B0H = 0x40000000U;
+                SCE->REG_A4H = 0x00008e55U;
+                SCE->REG_E0H = 0x81840001U;
+                SCE->REG_00H = 0x00001813U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                HW_SCE_p_func101(0x3753e09cU, 0xeb5d08e9U, 0x172cabccU, 0x820c6a84U);
+            }
+            else
+            {
+                HW_SCE_p_func101(0xc146649cU, 0xc9f93406U, 0xb4151e68U, 0x350bea3dU);
+            }
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00000cc4U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_B0H = 0x40000000U;
+            SCE->REG_A4H = 0x010087b5U;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_ECH = 0x0000b420U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_E0H = 0x80840001U;
+            SCE->REG_00H = 0x00008113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_ECH = 0x0000a540U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_ECH = 0x0000b7e0U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_ECH = 0x00000821U;
+            for (iLoop = 0; iLoop < 16; iLoop = iLoop+1)
+            {
+                SCE->REG_ECH = 0x3c002beaU;
+                SCE->REG_ECH = 0x12003c3fU;
+                SCE->REG_ECH = 0x00002fe0U;
+            }
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x00050805U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_MAC[0];
+            SCE->REG_100H = InData_MAC[1];
+            SCE->REG_100H = InData_MAC[2];
+            SCE->REG_100H = InData_MAC[3];
+            SCE->REG_A4H = 0x00900c45U;
+            SCE->REG_ECH = 0x0000b420U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_E0H = 0x81840001U;
+            SCE->REG_00H = 0x00001813U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_A4H = 0x00000000U;
+            HW_SCE_p_func100(0xcb5b64dfU, 0x657f9494U, 0x03814613U, 0xe7430083U);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_p_func102(0x6aa38abaU, 0xcd17e265U, 0xf6d55500U, 0xb66d00aeU);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_ERR_CRYPTO_SCE_FAIL;
+            }
+            else
+            {
+                HW_SCE_p_func102(0xfd9169abU, 0x5a2a8a2bU, 0x4d130f75U, 0xffa02c71U);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_SUCCESS;
+            }
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pa4f.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa4i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa4i.c
new file mode 100644
index 000000000..386665dc6
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa4i.c
@@ -0,0 +1,301 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes256CcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x0000a401U;
+    SCE->REG_108H = 0x00000000U;
+    SCE->REG_C4H = 0x200e1a0dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = S_RAM[16+0 + 0];
+    SCE->REG_100H = S_RAM[16+0 + 1];
+    SCE->REG_100H = S_RAM[16+0 + 2];
+    SCE->REG_100H = S_RAM[16+0 + 3];
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x80010000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyType[0];
+    SCE->REG_ECH = 0x38008800U;
+    SCE->REG_ECH = 0x00000001U;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00260000U;
+    HW_SCE_p_func100(0x4ae22d4fU, 0x21322d90U, 0x3286355dU, 0x3fa6ebecU);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0x620cbcafU, 0xdade38b9U, 0xeedc57d4U, 0xfdedae42U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        SCE->REG_ECH = 0x38000c00U;
+        SCE->REG_E0H = 0x00000080U;
+        SCE->REG_1CH = 0x00260000U;
+        HW_SCE_p_func100(0x55809dd9U, 0x1af7639eU, 0x946b61f5U, 0xda96e5baU);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            SCE->REG_A4H = 0x200c3b0dU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_KeyIndex[0];
+            SCE->REG_100H = InData_KeyIndex[1];
+            SCE->REG_100H = InData_KeyIndex[2];
+            SCE->REG_100H = InData_KeyIndex[3];
+            SCE->REG_A4H = 0x000c0b0cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x6e78d475U);
+            HW_SCE_p_func101(0x4e594381U, 0xf7034f4eU, 0x528ba33bU, 0x28d58b28U);
+        }
+        else
+        {
+            SCE->REG_A4H = 0x000c2b0dU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_KeyIndex[0];
+            SCE->REG_100H = InData_KeyIndex[1];
+            SCE->REG_100H = InData_KeyIndex[2];
+            SCE->REG_100H = InData_KeyIndex[3];
+            SCE->REG_A4H = 0x000c0b0cU;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x85d04999U);
+            HW_SCE_p_func101(0x0bade84dU, 0xb2fe7312U, 0x287d727aU, 0xb9645ca3U);
+        }
+        HW_SCE_p_func100(0xf5e9ad35U, 0x6e41a747U, 0x4257190dU, 0xedf1470bU);
+        SCE->REG_A4H = 0x02f8073dU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_KeyIndex[4];
+        SCE->REG_100H = InData_KeyIndex[5];
+        SCE->REG_100H = InData_KeyIndex[6];
+        SCE->REG_100H = InData_KeyIndex[7];
+        HW_SCE_p_func100(0x559bb14aU, 0xa71a63b7U, 0x0932190cU, 0x0af6b1a4U);
+        SCE->REG_A4H = 0x00f9073dU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_KeyIndex[8];
+        SCE->REG_100H = InData_KeyIndex[9];
+        SCE->REG_100H = InData_KeyIndex[10];
+        SCE->REG_100H = InData_KeyIndex[11];
+        SCE->REG_A4H = 0x000007bdU;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_KeyIndex[12];
+        SCE->REG_100H = InData_KeyIndex[13];
+        SCE->REG_100H = InData_KeyIndex[14];
+        SCE->REG_100H = InData_KeyIndex[15];
+        SCE->REG_A4H = 0x00900c45U;
+        SCE->REG_00H = 0x00001113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        HW_SCE_p_func100(0x6e8fe000U, 0x7b61e020U, 0xb97bfc23U, 0xf020fa35U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_p_func102(0xde470b37U, 0x1122069aU, 0xe666aac7U, 0xc779b694U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+        }
+        else
+        {
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x00040885U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_IV[0];
+            SCE->REG_100H = InData_IV[1];
+            SCE->REG_100H = InData_IV[2];
+            SCE->REG_100H = InData_IV[3];
+            SCE->REG_A4H = 0x00060805U;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00000734U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00050804U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_104H = 0x000000b1U;
+            SCE->REG_B0H = 0x40000000U;
+            SCE->REG_A4H = 0x00008e56U;
+            for (iLoop = 0; iLoop < Header_Len; iLoop = iLoop + 4)
+            {
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Header[iLoop + 0];
+                SCE->REG_100H = InData_Header[iLoop + 1];
+                SCE->REG_100H = InData_Header[iLoop + 2];
+                SCE->REG_100H = InData_Header[iLoop + 3];
+            }
+            HW_SCE_p_func205();//DisableINTEGRATE_WRRDYBinthisfunction.
+            HW_SCE_p_func100(0xe3c71749U, 0x39337772U, 0x2a7e1215U, 0xba3ca979U);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_p_func102(0x1e9244d4U, 0x44282cf6U, 0x3ae45c8eU, 0x328e4d68U);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_ERR_CRYPTO_SCE_FAIL;
+            }
+            else
+            {
+                HW_SCE_p_func101(0xec2b1ac8U, 0x5d656049U, 0x3552c558U, 0xb63c59b3U);
+                return FSP_SUCCESS;
+            }
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pa4i_r1.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa4u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa4u.c
new file mode 100644
index 000000000..cac87aa90
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa4u.c
@@ -0,0 +1,127 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes256CcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_p_func100(0xd7a64a68U, 0x15dcf5feU, 0xd0a71911U, 0xf319d57cU);
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_B0H = 0x40000000U;
+    SCE->REG_A4H = 0x00f087b6U;
+    SCE->REG_04H = 0x0000c100U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_Text[0];
+    SCE->REG_100H = InData_Text[1];
+    SCE->REG_100H = InData_Text[2];
+    SCE->REG_100H = InData_Text[3];
+    for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    }
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H;
+    OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H;
+    OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H;
+    OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H;
+    HW_SCE_p_func207();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+    HW_SCE_p_func101(0x7a295021U, 0x8c4d2a69U, 0xe39b4d8eU, 0x9b5afd2cU);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pa4u.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa7f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa7f.c
new file mode 100644
index 000000000..6bc68d7c8
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa7f.c
@@ -0,0 +1,221 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes192CcmEncryptFinalSub(uint32_t *InData_TextLen, uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t *OutData_MAC)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_p_func100(0x470d2cb1U, 0x16b738d9U, 0x8fddf5afU, 0x81545ec7U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0xb29c5e20U, 0x805deec2U, 0xaa036e1bU, 0x222235c7U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        SCE->REG_104H = 0x00000068U;
+        SCE->REG_E0H = 0x80010000U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_TextLen[0];
+        SCE->REG_ECH = 0x00008c00U;
+        SCE->REG_ECH = 0x0000000fU;
+        SCE->REG_ECH = 0x38008800U;
+        SCE->REG_ECH = 0x00000000U;
+        SCE->REG_E0H = 0x00000080U;
+        SCE->REG_1CH = 0x00A60000U;
+        HW_SCE_p_func100(0x29f34e19U, 0x52a2e9f9U, 0xc8e8929cU, 0xde66f217U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_B0H = 0x40000010U;
+            SCE->REG_A4H = 0x00e087b5U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_Text[0];
+            SCE->REG_100H = InData_Text[1];
+            SCE->REG_100H = InData_Text[2];
+            SCE->REG_100H = InData_Text[3];
+            SCE->REG_ECH = 0x0000b420U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_E0H = 0x80840001U;
+            SCE->REG_00H = 0x00008113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_ECH = 0x00000821U;
+            SCE->REG_ECH = 0x0000a400U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_ECH = 0x0000b7e0U;
+            SCE->REG_ECH = 0x00000080U;
+            for (iLoop = 0; iLoop < 16; iLoop = iLoop+1)
+            {
+                SCE->REG_ECH = 0x3c002be0U;
+                SCE->REG_ECH = 0x12003c3fU;
+                SCE->REG_ECH = 0x00002fe0U;
+            }
+            HW_SCE_p_func100(0x81d76dc5U, 0x88b8965cU, 0xcedb7e8aU, 0xd95b0f41U);
+            SCE->REG_ECH = 0x0000b420U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_E0H = 0x81840001U;
+            SCE->REG_04H = 0x00000612U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[0] = SCE->REG_100H;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[1] = SCE->REG_100H;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[2] = SCE->REG_100H;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[3] = SCE->REG_100H;
+            HW_SCE_p_func101(0xb79f433bU, 0xd3fe8f2aU, 0x6a5195eeU, 0xd44ecb00U);
+        }
+        else
+        {
+            HW_SCE_p_func101(0x57d61337U, 0xbcbb1dc0U, 0xb500f5f3U, 0x3799a289U);
+        }
+        SCE->REG_104H = 0x00000051U;
+        SCE->REG_A4H = 0x01000c84U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        HW_SCE_p_func100(0x6b5ef7f2U, 0xc1a631acU, 0xf9820bd4U, 0xd44f8d7dU);
+        SCE->REG_B0H = 0x40000010U;
+        SCE->REG_A4H = 0x000089c5U;
+        SCE->REG_00H = 0x00001113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_04H = 0x00000112U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_MAC[0] = SCE->REG_100H;
+        OutData_MAC[1] = SCE->REG_100H;
+        OutData_MAC[2] = SCE->REG_100H;
+        OutData_MAC[3] = SCE->REG_100H;
+        HW_SCE_p_func102(0x6a61afe6U, 0x05e3bd11U, 0x75b9b3e5U, 0x2326bcd9U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_SUCCESS;
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pa7f.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa7i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa7i.c
new file mode 100644
index 000000000..e5b4c573b
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa7i.c
@@ -0,0 +1,231 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes192CcmEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x0000a701U;
+    SCE->REG_108H = 0x00000000U;
+    HW_SCE_p_func100(0x2592366dU, 0x1c5ed460U, 0x7b9c8e90U, 0xcf4c9915U);
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x200c3b0dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[0];
+    SCE->REG_100H = InData_KeyIndex[1];
+    SCE->REG_100H = InData_KeyIndex[2];
+    SCE->REG_100H = InData_KeyIndex[3];
+    SCE->REG_A4H = 0x000c0b0cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0xc79c2843U);
+    SCE->REG_A4H = 0x02f8073dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[4];
+    SCE->REG_100H = InData_KeyIndex[5];
+    SCE->REG_100H = InData_KeyIndex[6];
+    SCE->REG_100H = InData_KeyIndex[7];
+    HW_SCE_p_func100(0x549566ecU, 0xb70501faU, 0x925046c1U, 0xd1d90571U);
+    SCE->REG_A4H = 0x00f9073dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[8];
+    SCE->REG_100H = InData_KeyIndex[9];
+    SCE->REG_100H = InData_KeyIndex[10];
+    SCE->REG_100H = InData_KeyIndex[11];
+    SCE->REG_A4H = 0x000007bdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[12];
+    SCE->REG_100H = InData_KeyIndex[13];
+    SCE->REG_100H = InData_KeyIndex[14];
+    SCE->REG_100H = InData_KeyIndex[15];
+    SCE->REG_A4H = 0x00900c45U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_p_func100(0x4f369d6bU, 0x118e8276U, 0xd2717b7cU, 0x7001b03dU);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0xb3965759U, 0xf559ad5bU, 0xfdf197dfU, 0xd258b75bU);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+    }
+    else
+    {
+        SCE->REG_104H = 0x00000361U;
+        SCE->REG_A4H = 0x00040885U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_IV[0];
+        SCE->REG_100H = InData_IV[1];
+        SCE->REG_100H = InData_IV[2];
+        SCE->REG_100H = InData_IV[3];
+        SCE->REG_A4H = 0x00060805U;
+        SCE->REG_00H = 0x00001113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_104H = 0x00000051U;
+        SCE->REG_A4H = 0x00000734U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        SCE->REG_104H = 0x00000051U;
+        SCE->REG_A4H = 0x00050804U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        SCE->REG_104H = 0x000000b1U;
+        SCE->REG_B0H = 0x40000010U;
+        SCE->REG_A4H = 0x00058e56U;
+        for (iLoop = 0; iLoop < Header_Len; iLoop = iLoop + 4)
+        {
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_Header[iLoop + 0];
+            SCE->REG_100H = InData_Header[iLoop + 1];
+            SCE->REG_100H = InData_Header[iLoop + 2];
+            SCE->REG_100H = InData_Header[iLoop + 3];
+        }
+        HW_SCE_p_func205();//DisableINTEGRATE_WRRDYBinthisfunction.
+        HW_SCE_p_func100(0xa241e2e5U, 0xffc2d529U, 0xf2196de7U, 0x9b87d04fU);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_p_func102(0x149c4dbfU, 0xbbacd443U, 0x9e4c93d1U, 0xce24e7d8U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            return FSP_SUCCESS;
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pa7i.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa7u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa7u.c
new file mode 100644
index 000000000..14678fd92
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pa7u.c
@@ -0,0 +1,127 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes192CcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_p_func100(0x3693ef9eU, 0x47c2a672U, 0x7aa78f43U, 0x67e698b4U);
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_B0H = 0x40000010U;
+    SCE->REG_A4H = 0x00e087b6U;
+    SCE->REG_04H = 0x0000c100U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_Text[0];
+    SCE->REG_100H = InData_Text[1];
+    SCE->REG_100H = InData_Text[2];
+    SCE->REG_100H = InData_Text[3];
+    for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    }
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H;
+    OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H;
+    OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H;
+    OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H;
+    HW_SCE_p_func207();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+    HW_SCE_p_func101(0xf5bab6a3U, 0xf38a0d02U, 0xd2738d3fU, 0xc35b6f51U);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pa7u.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb0f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb0f.c
new file mode 100644
index 000000000..3789ecd9b
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb0f.c
@@ -0,0 +1,315 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes192CcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_TextLen, uint32_t *InData_MAC, uint32_t *InData_MACLength, uint32_t *OutData_Text)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_p_func100(0x8a9c0c9dU, 0x7a793140U, 0x72684e99U, 0xd2621d59U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0x61d5c53cU, 0xa9cec669U, 0x81475113U, 0xdddea4edU);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        SCE->REG_104H = 0x00000068U;
+        SCE->REG_E0H = 0x80010140U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_MACLength[0];
+        SCE->REG_ECH = 0x38008940U;
+        SCE->REG_ECH = 0x00000000U;
+        SCE->REG_E0H = 0x00000080U;
+        SCE->REG_1CH = 0x00260000U;
+        SCE->REG_ECH = 0x0000b7e0U;
+        SCE->REG_ECH = 0x00000010U;
+        SCE->REG_ECH = 0x34202beaU;
+        SCE->REG_E0H = 0x00000080U;
+        SCE->REG_1CH = 0x00260000U;
+        HW_SCE_p_func100(0x3b2c4b7eU, 0xa3292db8U, 0x414ef0fdU, 0xc7ba9a1dU);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_p_func102(0x893e5396U, 0xdd93c3a3U, 0x6a1e2a3cU, 0x7dc48d95U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            SCE->REG_104H = 0x00000068U;
+            SCE->REG_E0H = 0x80010000U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_TextLen[0];
+            SCE->REG_ECH = 0x00008c00U;
+            SCE->REG_ECH = 0x0000000fU;
+            SCE->REG_ECH = 0x38008800U;
+            SCE->REG_ECH = 0x00000000U;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00A60000U;
+            HW_SCE_p_func100(0xbe4fcf29U, 0xababc195U, 0x40cc1c11U, 0x34bce73cU);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_B0H = 0x40000010U;
+                SCE->REG_A4H = 0x000087b5U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[0];
+                SCE->REG_100H = InData_Text[1];
+                SCE->REG_100H = InData_Text[2];
+                SCE->REG_100H = InData_Text[3];
+                SCE->REG_ECH = 0x0000b420U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_E0H = 0x80840001U;
+                SCE->REG_00H = 0x00008113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_ECH = 0x00000821U;
+                SCE->REG_ECH = 0x0000a400U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_ECH = 0x0000b7e0U;
+                SCE->REG_ECH = 0x00000080U;
+                for (iLoop = 0; iLoop < 16; iLoop = iLoop+1)
+                {
+                    SCE->REG_ECH = 0x3c002be0U;
+                    SCE->REG_ECH = 0x12003c3fU;
+                    SCE->REG_ECH = 0x00002fe0U;
+                }
+                HW_SCE_p_func100(0x7b556cbfU, 0xf12b7b6aU, 0x50b85b38U, 0x49ef665fU);
+                SCE->REG_ECH = 0x0000b420U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_E0H = 0x81840001U;
+                SCE->REG_04H = 0x00000612U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[1] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[2] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[3] = SCE->REG_100H;
+                SCE->REG_B0H = 0x40000010U;
+                SCE->REG_A4H = 0x00008e55U;
+                SCE->REG_E0H = 0x81840001U;
+                SCE->REG_00H = 0x00001813U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                HW_SCE_p_func101(0x58b140d8U, 0x7e6bef6cU, 0x3aaf3845U, 0x0565b716U);
+            }
+            else
+            {
+                HW_SCE_p_func101(0x9f4a0dbfU, 0x84687f76U, 0x1920e6f2U, 0xe965133aU);
+            }
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00000cc4U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            SCE->REG_B0H = 0x40000010U;
+            SCE->REG_A4H = 0x010087b5U;
+            SCE->REG_00H = 0x00001113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_ECH = 0x0000b420U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_E0H = 0x80840001U;
+            SCE->REG_00H = 0x00008113U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_ECH = 0x0000a540U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_ECH = 0x0000b7e0U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_ECH = 0x00000821U;
+            for (iLoop = 0; iLoop < 16; iLoop = iLoop+1)
+            {
+                SCE->REG_ECH = 0x3c002beaU;
+                SCE->REG_ECH = 0x12003c3fU;
+                SCE->REG_ECH = 0x00002fe0U;
+            }
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x00050805U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_MAC[0];
+            SCE->REG_100H = InData_MAC[1];
+            SCE->REG_100H = InData_MAC[2];
+            SCE->REG_100H = InData_MAC[3];
+            SCE->REG_A4H = 0x00900c45U;
+            SCE->REG_ECH = 0x0000b420U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_E0H = 0x81840001U;
+            SCE->REG_00H = 0x00001813U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_00H_b.B25)
+            {
+                /* waiting */
+            }
+            SCE->REG_1CH = 0x00001800U;
+            SCE->REG_A4H = 0x00000000U;
+            HW_SCE_p_func100(0x3ad05585U, 0x0d7db2fcU, 0x042f75f9U, 0x999daf07U);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_p_func102(0x22fd028bU, 0x82b658caU, 0x67fb820aU, 0x39750567U);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_ERR_CRYPTO_SCE_FAIL;
+            }
+            else
+            {
+                HW_SCE_p_func102(0x22df2322U, 0x344546a2U, 0xc9b5d8e5U, 0x2fea3bb0U);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_SUCCESS;
+            }
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pb0f.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb0i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb0i.c
new file mode 100644
index 000000000..6124a9bcd
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb0i.c
@@ -0,0 +1,231 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes192CcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x0000b001U;
+    SCE->REG_108H = 0x00000000U;
+    HW_SCE_p_func100(0xee7e9f00U, 0xd295b4e9U, 0x0067dd0fU, 0x94f3d79dU);
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x200c3b0dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[0];
+    SCE->REG_100H = InData_KeyIndex[1];
+    SCE->REG_100H = InData_KeyIndex[2];
+    SCE->REG_100H = InData_KeyIndex[3];
+    SCE->REG_A4H = 0x000c0b0cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0xc79c2843U);
+    SCE->REG_A4H = 0x02f8073dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[4];
+    SCE->REG_100H = InData_KeyIndex[5];
+    SCE->REG_100H = InData_KeyIndex[6];
+    SCE->REG_100H = InData_KeyIndex[7];
+    HW_SCE_p_func100(0xe41ebae4U, 0xd2ccd41fU, 0xa96e7972U, 0x0d7a1446U);
+    SCE->REG_A4H = 0x00f9073dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[8];
+    SCE->REG_100H = InData_KeyIndex[9];
+    SCE->REG_100H = InData_KeyIndex[10];
+    SCE->REG_100H = InData_KeyIndex[11];
+    SCE->REG_A4H = 0x000007bdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[12];
+    SCE->REG_100H = InData_KeyIndex[13];
+    SCE->REG_100H = InData_KeyIndex[14];
+    SCE->REG_100H = InData_KeyIndex[15];
+    SCE->REG_A4H = 0x00900c45U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_p_func100(0xdd860239U, 0xbafb3cb6U, 0x3a50c2d3U, 0x7e07f7c1U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0xd50a6e06U, 0x0258424aU, 0x03420028U, 0xd6795849U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+    }
+    else
+    {
+        SCE->REG_104H = 0x00000361U;
+        SCE->REG_A4H = 0x00040885U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_IV[0];
+        SCE->REG_100H = InData_IV[1];
+        SCE->REG_100H = InData_IV[2];
+        SCE->REG_100H = InData_IV[3];
+        SCE->REG_A4H = 0x00060805U;
+        SCE->REG_00H = 0x00001113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_104H = 0x00000051U;
+        SCE->REG_A4H = 0x00000734U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        SCE->REG_104H = 0x00000051U;
+        SCE->REG_A4H = 0x00050804U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000000U);
+        SCE->REG_104H = 0x000000b1U;
+        SCE->REG_B0H = 0x40000010U;
+        SCE->REG_A4H = 0x00008e56U;
+        for (iLoop = 0; iLoop < Header_Len; iLoop = iLoop + 4)
+        {
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_Header[iLoop + 0];
+            SCE->REG_100H = InData_Header[iLoop + 1];
+            SCE->REG_100H = InData_Header[iLoop + 2];
+            SCE->REG_100H = InData_Header[iLoop + 3];
+        }
+        HW_SCE_p_func205();//DisableINTEGRATE_WRRDYBinthisfunction.
+        HW_SCE_p_func100(0xead4e73aU, 0x7b6d20f3U, 0xe6bd500cU, 0x6d2f02bdU);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_p_func102(0xd95d7241U, 0x19b843b9U, 0xf13a4218U, 0x8360ef66U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            return FSP_SUCCESS;
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pb0i.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb0u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb0u.c
new file mode 100644
index 000000000..1ae645a45
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb0u.c
@@ -0,0 +1,127 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes192CcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_p_func100(0x6abda488U, 0x13202f14U, 0x1f9503d4U, 0x10fc4234U);
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_B0H = 0x40000010U;
+    SCE->REG_A4H = 0x00f087b6U;
+    SCE->REG_04H = 0x0000c100U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_Text[0];
+    SCE->REG_100H = InData_Text[1];
+    SCE->REG_100H = InData_Text[2];
+    SCE->REG_100H = InData_Text[3];
+    for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    }
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H;
+    OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H;
+    OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H;
+    OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H;
+    HW_SCE_p_func207();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+    HW_SCE_p_func101(0x8dce9380U, 0x330231feU, 0xc9c04420U, 0x1375e5eeU);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pb0u.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb3f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb3f.c
new file mode 100644
index 000000000..8d5bc94f4
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb3f.c
@@ -0,0 +1,389 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes128XtsEncryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x80010000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_TextBitLen[0];
+    SCE->REG_ECH = 0x000037c0U;
+    SCE->REG_ECH = 0x00076bdeU;
+    SCE->REG_ECH = 0x00026fdeU;
+    SCE->REG_ECH = 0x00000bffU;
+    SCE->REG_ECH = 0x38008c00U;
+    SCE->REG_ECH = 0x0000007fU;
+    SCE->REG_ECH = 0x00020020U;
+    SCE->REG_ECH = 0x3420a800U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_ECH = 0x1000d3e0U;
+    SCE->REG_ECH = 0x2000abc0U;
+    SCE->REG_ECH = 0x00000004U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_ECH = 0x38000fffU;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00A60000U;
+    HW_SCE_p_func100(0x9a72b2b6U, 0x6a6c3491U, 0xbf56b55aU, 0x2d05cd9eU);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0x86d1fd1fU, 0x5e5fe136U, 0x17f29831U, 0x13d78d71U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        HW_SCE_p_func100(0xd00d8778U, 0x4ac4d3fcU, 0xc5dca3e4U, 0xc0fa694aU);
+        SCE->REG_E0H = 0x810103c0U;
+        SCE->REG_04H = 0x00000606U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        S_RAM[0] = change_endian_long(SCE->REG_100H);
+        HW_SCE_p_func100(0x9ea6b296U, 0x9a027953U, 0x411c82dbU, 0x06cdecbbU);
+        SCE->REG_104H = 0x000000b1U;
+        SCE->REG_B0H = 0x00000020U;
+        SCE->REG_A4H = 0x00008da6U;
+        SCE->REG_04H = 0x0000c100U;
+        iLoop = 0;
+            if(S_RAM[0] >= 4) 
+        {
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_Text[0];
+            SCE->REG_100H = InData_Text[1];
+            SCE->REG_100H = InData_Text[2];
+            SCE->REG_100H = InData_Text[3];
+            for (iLoop = 4; iLoop < S_RAM[0]; iLoop = iLoop + 4)
+            {
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+            }
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+        }
+        HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+        HW_SCE_p_func100(0xf8d1ff89U, 0x0b00457aU, 0xc501f476U, 0xcf801dfbU);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_p_func102(0x31623a36U, 0x3e3ffe22U, 0x829fe5c2U, 0x53f5ec07U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            SCE->REG_ECH = 0x38008c00U;
+            SCE->REG_ECH = 0x0000007fU;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00A60000U;
+            HW_SCE_p_func100(0x35e1038aU, 0xf37817e3U, 0x77c65939U, 0x8b975881U);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_B0H = 0x00000020U;
+                SCE->REG_A4H = 0x00008da5U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_E0H = 0x80840006U;
+                SCE->REG_00H = 0x00008113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_ECH = 0x0000b4e0U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_104H = 0x00000368U;
+                SCE->REG_E0H = 0x80840007U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+4 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+5 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+6 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+7 + 0];
+                SCE->REG_ECH = 0x0000b4a0U;
+                SCE->REG_ECH = 0x00000004U;
+                SCE->REG_ECH = 0x00003500U;
+                SCE->REG_ECH = 0x00036908U;
+                SCE->REG_ECH = 0x00008d00U;
+                SCE->REG_ECH = 0x0000000cU;
+                SCE->REG_ECH = 0x000024c8U;
+                SCE->REG_ECH = 0x000024e8U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_ECH = 0x00003847U;
+                SCE->REG_ECH = 0x00003460U;
+                SCE->REG_ECH = 0x00008c60U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x0000b480U;
+                SCE->REG_ECH = 0xffffffffU;
+                SCE->REG_ECH = 0x00004403U;
+                SCE->REG_ECH = 0x00007484U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_ECH = 0x00001484U;
+                SCE->REG_ECH = 0x00000c44U;
+                SCE->REG_ECH = 0x00001041U;
+                SCE->REG_ECH = 0x00003c47U;
+                SCE->REG_ECH = 0x000037e0U;
+                SCE->REG_ECH = 0x00008fe0U;
+                SCE->REG_ECH = 0x0000007fU;
+                SCE->REG_ECH = 0x38008fe0U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x1000a7e0U;
+                SCE->REG_ECH = 0x00000020U;
+                SCE->REG_ECH = 0x0000b7c0U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_ECH = 0x00002bdfU;
+                SCE->REG_ECH = 0x00056bdeU;
+                SCE->REG_ECH = 0x0000353eU;
+                HW_SCE_p_func100(0xac4f35abU, 0x618a9fbeU, 0x7bda9d62U, 0x75d3969dU);
+                SCE->REG_E0H = 0x810103c0U;
+                SCE->REG_04H = 0x00000606U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                S_RAM[0] = change_endian_long(SCE->REG_100H);
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x000024c5U;
+                    SCE->REG_ECH = 0x000024e5U;
+                    SCE->REG_ECH = 0x00003ba6U;
+                    SCE->REG_ECH = 0x00003fa7U;
+                    SCE->REG_ECH = 0x000033c0U;
+                    HW_SCE_p_func101(0x7289abdaU, 0x17d781e4U, 0x7f6a8aa3U, 0xf1ebaa1bU);
+                }
+                SCE->REG_ECH = 0x38000fdeU;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                HW_SCE_p_func100(0x3e3f80b3U, 0x4c48265aU, 0x54dd92cbU, 0x8c749fd3U);
+                SCE->REG_ECH = 0x0000b4e0U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_B0H = 0x00000020U;
+                SCE->REG_A4H = 0x00008da5U;
+                SCE->REG_E0H = 0x81840007U;
+                SCE->REG_00H = 0x00001813U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_04H = 0x00000112U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop + 0] = SCE->REG_100H;
+                OutData_Text[iLoop + 1] = SCE->REG_100H;
+                OutData_Text[iLoop + 2] = SCE->REG_100H;
+                OutData_Text[iLoop + 3] = SCE->REG_100H;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_ECH = 0x000024c8U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_ECH = 0x00003c26U;
+                SCE->REG_ECH = 0x00000bffU;
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x000024c5U;
+                    SCE->REG_ECH = 0x00003fe6U;
+                    SCE->REG_ECH = 0x00003120U;
+                    HW_SCE_p_func101(0x43363b85U, 0x9b7c1a67U, 0xe36f2e28U, 0xa5786444U);
+                }
+                HW_SCE_p_func100(0x9a595467U, 0xe12fbe7aU, 0x065ec1a8U, 0xda6533a0U);
+                SCE->REG_ECH = 0x38000d29U;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_E0H = 0x81840006U;
+                SCE->REG_04H = 0x00000612U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+4 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+5 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+6 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+7 + 0] = SCE->REG_100H;
+                HW_SCE_p_func101(0xb9ff3e1eU, 0x83bb50aaU, 0xac5650c1U, 0x1bb649c0U);
+            }
+            HW_SCE_p_func102(0x0f2ea017U, 0x4d647b6fU, 0xb08b41dbU, 0x6f311a7aU);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_SUCCESS;
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pb3f.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb3i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb3i.c
new file mode 100644
index 000000000..9483306ba
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb3i.c
@@ -0,0 +1,174 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes128XtsEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x0000b301U;
+    SCE->REG_108H = 0x00000000U;
+    HW_SCE_p_func100(0x4fb65f5cU, 0x656ff6b0U, 0x1f44ad0bU, 0x1828d2daU);
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x200c3b0dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[0];
+    SCE->REG_100H = InData_KeyIndex[1];
+    SCE->REG_100H = InData_KeyIndex[2];
+    SCE->REG_100H = InData_KeyIndex[3];
+    SCE->REG_A4H = 0x000c0b0cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x2d8daf39U);
+    SCE->REG_A4H = 0x02f8073dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[4];
+    SCE->REG_100H = InData_KeyIndex[5];
+    SCE->REG_100H = InData_KeyIndex[6];
+    SCE->REG_100H = InData_KeyIndex[7];
+    HW_SCE_p_func100(0x5610b322U, 0xc6aaf4f6U, 0x75a0f4c5U, 0x82dfdb4eU);
+    SCE->REG_A4H = 0x00f9073dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[8];
+    SCE->REG_100H = InData_KeyIndex[9];
+    SCE->REG_100H = InData_KeyIndex[10];
+    SCE->REG_100H = InData_KeyIndex[11];
+    SCE->REG_A4H = 0x000007bdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[12];
+    SCE->REG_100H = InData_KeyIndex[13];
+    SCE->REG_100H = InData_KeyIndex[14];
+    SCE->REG_100H = InData_KeyIndex[15];
+    SCE->REG_A4H = 0x00900c45U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_p_func100(0x4b56b266U, 0x3a9c2db9U, 0x0991185aU, 0xf6cb7ea7U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0xdd6b0c9fU, 0x3145866dU, 0x9973e60cU, 0x696c4442U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+    }
+    else
+    {
+        SCE->REG_104H = 0x00000361U;
+        SCE->REG_A4H = 0x00041a05U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_IV[0];
+        SCE->REG_100H = InData_IV[1];
+        SCE->REG_100H = InData_IV[2];
+        SCE->REG_100H = InData_IV[3];
+        return FSP_SUCCESS;
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pb3i.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb3u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb3u.c
new file mode 100644
index 000000000..d01766ee7
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb3u.c
@@ -0,0 +1,127 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes128XtsEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_p_func100(0xde73180eU, 0x28746107U, 0x8dc19ee5U, 0x8a6d2f9cU);
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_B0H = 0x00000020U;
+    SCE->REG_A4H = 0x00008da6U;
+    SCE->REG_04H = 0x0000c100U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_Text[0];
+    SCE->REG_100H = InData_Text[1];
+    SCE->REG_100H = InData_Text[2];
+    SCE->REG_100H = InData_Text[3];
+    for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    }
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+    HW_SCE_p_func101(0xaacdf9a0U, 0x04e2b68aU, 0xec389e1fU, 0x1e8f7026U);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pb3u.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb6f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb6f.c
new file mode 100644
index 000000000..8d156cf9b
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb6f.c
@@ -0,0 +1,423 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes128XtsDecryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x80010000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_TextBitLen[0];
+    SCE->REG_ECH = 0x000037c0U;
+    SCE->REG_ECH = 0x00076bdeU;
+    SCE->REG_ECH = 0x00026fdeU;
+    SCE->REG_ECH = 0x00000bffU;
+    SCE->REG_ECH = 0x38008c00U;
+    SCE->REG_ECH = 0x0000007fU;
+    SCE->REG_ECH = 0x00020020U;
+    SCE->REG_ECH = 0x3420a800U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_ECH = 0x1000d3e0U;
+    SCE->REG_ECH = 0x2000abc0U;
+    SCE->REG_ECH = 0x00000004U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_ECH = 0x38000fffU;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00A60000U;
+    HW_SCE_p_func100(0x8d9edd55U, 0xcd7dab22U, 0xb87340e0U, 0x583f4075U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0xead71f29U, 0x17da8dbdU, 0x937a940aU, 0xfc88bd55U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        HW_SCE_p_func100(0x75a7b920U, 0xe3c11d3bU, 0x37a56ed2U, 0x12de765aU);
+        SCE->REG_E0H = 0x810103c0U;
+        SCE->REG_04H = 0x00000606U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        S_RAM[0] = change_endian_long(SCE->REG_100H);
+        HW_SCE_p_func100(0x12bf93f0U, 0x5bf14bedU, 0x6940ecfdU, 0x2ef66ceaU);
+        SCE->REG_104H = 0x000000b1U;
+        SCE->REG_B0H = 0x00000020U;
+        SCE->REG_A4H = 0x0000cda6U;
+        SCE->REG_04H = 0x0000c100U;
+        iLoop = 0;
+            if(S_RAM[0] >= 4) 
+        {
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_Text[0];
+            SCE->REG_100H = InData_Text[1];
+            SCE->REG_100H = InData_Text[2];
+            SCE->REG_100H = InData_Text[3];
+            for (iLoop = 4; iLoop < S_RAM[0]; iLoop = iLoop + 4)
+            {
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+            }
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+        }
+        HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+        HW_SCE_p_func100(0x4292a0beU, 0xa0f8d5e2U, 0x8fe354bfU, 0x53c147ffU);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_p_func102(0x467890bdU, 0xe5e15402U, 0xe12f7618U, 0xd7fa84bfU);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            SCE->REG_ECH = 0x38008c00U;
+            SCE->REG_ECH = 0x0000007fU;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00A60000U;
+            HW_SCE_p_func100(0xf34b7ebbU, 0x4c069156U, 0xafc186d9U, 0xb191a2f5U);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_p_func100(0x82b35c94U, 0xfbdd2787U, 0xdf48566dU, 0x0db0c24bU);
+                SCE->REG_104H = 0x00000051U;
+                SCE->REG_A4H = 0x00000c84U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = change_endian_long(0x00000000U);
+                SCE->REG_E0H = 0x80040140U;
+                SCE->REG_00H = 0x00008113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_104H = 0x00000051U;
+                SCE->REG_B0H = 0x00000020U;
+                SCE->REG_A4H = 0x0000cd24U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = change_endian_long(0x00000000U);
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_B0H = 0x00000020U;
+                SCE->REG_A4H = 0x0000cda5U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_E0H = 0x80840006U;
+                SCE->REG_00H = 0x00008113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_ECH = 0x0000b4e0U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_104H = 0x00000368U;
+                SCE->REG_E0H = 0x80840007U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+4 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+5 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+6 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+7 + 0];
+                SCE->REG_ECH = 0x0000b4a0U;
+                SCE->REG_ECH = 0x00000004U;
+                SCE->REG_ECH = 0x00003500U;
+                SCE->REG_ECH = 0x00036908U;
+                SCE->REG_ECH = 0x00008d00U;
+                SCE->REG_ECH = 0x0000000cU;
+                SCE->REG_ECH = 0x000024c8U;
+                SCE->REG_ECH = 0x000024e8U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_ECH = 0x00003847U;
+                SCE->REG_ECH = 0x00003460U;
+                SCE->REG_ECH = 0x00008c60U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x0000b480U;
+                SCE->REG_ECH = 0xffffffffU;
+                SCE->REG_ECH = 0x00004403U;
+                SCE->REG_ECH = 0x00007484U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_ECH = 0x00001484U;
+                SCE->REG_ECH = 0x00000c44U;
+                SCE->REG_ECH = 0x00001041U;
+                SCE->REG_ECH = 0x00003c47U;
+                SCE->REG_ECH = 0x000037e0U;
+                SCE->REG_ECH = 0x00008fe0U;
+                SCE->REG_ECH = 0x0000007fU;
+                SCE->REG_ECH = 0x38008fe0U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x1000a7e0U;
+                SCE->REG_ECH = 0x00000020U;
+                SCE->REG_ECH = 0x0000b7c0U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_ECH = 0x00002bdfU;
+                SCE->REG_ECH = 0x00056bdeU;
+                SCE->REG_ECH = 0x0000353eU;
+                SCE->REG_E0H = 0x810103c0U;
+                SCE->REG_04H = 0x00000606U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                S_RAM[0] = change_endian_long(SCE->REG_100H);
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x000024c5U;
+                    SCE->REG_ECH = 0x000024e5U;
+                    SCE->REG_ECH = 0x00003ba6U;
+                    SCE->REG_ECH = 0x00003fa7U;
+                    SCE->REG_ECH = 0x000033c0U;
+                    HW_SCE_p_func101(0x62395e74U, 0xf1f967c5U, 0xc71e7432U, 0xad80dab6U);
+                }
+                HW_SCE_p_func100(0x60efb16cU, 0xf3ac1400U, 0x2f40a35bU, 0x19974a77U);
+                SCE->REG_ECH = 0x38000fdeU;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_A4H = 0x00040805U;
+                SCE->REG_E0H = 0x81040140U;
+                SCE->REG_00H = 0x00001813U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_ECH = 0x0000b4e0U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_B0H = 0x00000020U;
+                SCE->REG_A4H = 0x0000cda5U;
+                SCE->REG_E0H = 0x81840007U;
+                SCE->REG_00H = 0x00001813U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_04H = 0x00000112U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop + 0] = SCE->REG_100H;
+                OutData_Text[iLoop + 1] = SCE->REG_100H;
+                OutData_Text[iLoop + 2] = SCE->REG_100H;
+                OutData_Text[iLoop + 3] = SCE->REG_100H;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_ECH = 0x000024c8U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_ECH = 0x00003c26U;
+                SCE->REG_ECH = 0x00000bffU;
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x000024c5U;
+                    SCE->REG_ECH = 0x00003fe6U;
+                    SCE->REG_ECH = 0x00003120U;
+                    HW_SCE_p_func101(0x2ecd3be3U, 0x1da6e741U, 0x606b628eU, 0x76898e01U);
+                }
+                HW_SCE_p_func100(0x617d0560U, 0x9706c4afU, 0x17b07cc6U, 0x85f644e5U);
+                SCE->REG_ECH = 0x38000d29U;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_E0H = 0x81840006U;
+                SCE->REG_04H = 0x00000612U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+4 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+5 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+6 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+7 + 0] = SCE->REG_100H;
+                HW_SCE_p_func101(0x68660d77U, 0xfed17014U, 0x34401600U, 0x8dc1218aU);
+            }
+            HW_SCE_p_func102(0xa666fa63U, 0x4ff0b0a2U, 0x93160b43U, 0xaa914a03U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_SUCCESS;
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pb6f.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb6i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb6i.c
new file mode 100644
index 000000000..cb5320180
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb6i.c
@@ -0,0 +1,175 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes128XtsDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x0000b601U;
+    SCE->REG_108H = 0x00000000U;
+    HW_SCE_p_func100(0xd9d51d2fU, 0xb5652154U, 0x03119b6aU, 0xd5e91813U);
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x200c3b0dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[0];
+    SCE->REG_100H = InData_KeyIndex[1];
+    SCE->REG_100H = InData_KeyIndex[2];
+    SCE->REG_100H = InData_KeyIndex[3];
+    SCE->REG_A4H = 0x000c0b0cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x2d8daf39U);
+    SCE->REG_A4H = 0x02f8073dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[4];
+    SCE->REG_100H = InData_KeyIndex[5];
+    SCE->REG_100H = InData_KeyIndex[6];
+    SCE->REG_100H = InData_KeyIndex[7];
+    HW_SCE_p_func100(0xc305d637U, 0x7e47743eU, 0x417ced2fU, 0x3a5dc13eU);
+    SCE->REG_A4H = 0x00f9073dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[8];
+    SCE->REG_100H = InData_KeyIndex[9];
+    SCE->REG_100H = InData_KeyIndex[10];
+    SCE->REG_100H = InData_KeyIndex[11];
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x000007bdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[12];
+    SCE->REG_100H = InData_KeyIndex[13];
+    SCE->REG_100H = InData_KeyIndex[14];
+    SCE->REG_100H = InData_KeyIndex[15];
+    SCE->REG_A4H = 0x00900c45U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_p_func100(0x55e4a8e5U, 0x86875ebbU, 0xfd9c6583U, 0xac8c08f5U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0xff078204U, 0x478beff9U, 0x8f11b149U, 0x52c6858fU);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+    }
+    else
+    {
+        SCE->REG_104H = 0x00000361U;
+        SCE->REG_A4H = 0x00041a05U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_IV[0];
+        SCE->REG_100H = InData_IV[1];
+        SCE->REG_100H = InData_IV[2];
+        SCE->REG_100H = InData_IV[3];
+        return FSP_SUCCESS;
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pb6i.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb6u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb6u.c
new file mode 100644
index 000000000..866544764
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb6u.c
@@ -0,0 +1,127 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes128XtsDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_p_func100(0xa68d22efU, 0x4f2550e5U, 0x9328f3d8U, 0x821724c9U);
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_B0H = 0x00000020U;
+    SCE->REG_A4H = 0x0000cda6U;
+    SCE->REG_04H = 0x0000c100U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_Text[0];
+    SCE->REG_100H = InData_Text[1];
+    SCE->REG_100H = InData_Text[2];
+    SCE->REG_100H = InData_Text[3];
+    for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    }
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+    HW_SCE_p_func101(0xe063f521U, 0x29eba585U, 0x4dc32f2aU, 0xa7b3cbbbU);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pb6u.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb9f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb9f.c
new file mode 100644
index 000000000..7d6185d3d
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb9f.c
@@ -0,0 +1,389 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes256XtsEncryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x80010000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_TextBitLen[0];
+    SCE->REG_ECH = 0x000037c0U;
+    SCE->REG_ECH = 0x00076bdeU;
+    SCE->REG_ECH = 0x00026fdeU;
+    SCE->REG_ECH = 0x00000bffU;
+    SCE->REG_ECH = 0x38008c00U;
+    SCE->REG_ECH = 0x0000007fU;
+    SCE->REG_ECH = 0x00020020U;
+    SCE->REG_ECH = 0x3420a800U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_ECH = 0x1000d3e0U;
+    SCE->REG_ECH = 0x2000abc0U;
+    SCE->REG_ECH = 0x00000004U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_ECH = 0x38000fffU;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00A60000U;
+    HW_SCE_p_func100(0x6a31b316U, 0x42f68ef5U, 0xa1ae40dbU, 0x61688390U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0x025f62c7U, 0xef26962dU, 0xf07fe67dU, 0xef873f2bU);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        HW_SCE_p_func100(0xd66d0381U, 0x9f7eda8dU, 0xbff80dedU, 0x0afc73f4U);
+        SCE->REG_E0H = 0x810103c0U;
+        SCE->REG_04H = 0x00000606U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        S_RAM[0] = change_endian_long(SCE->REG_100H);
+        HW_SCE_p_func100(0x42f6b391U, 0x327a6023U, 0xfb694c21U, 0x446bd730U);
+        SCE->REG_104H = 0x000000b1U;
+        SCE->REG_B0H = 0x40000020U;
+        SCE->REG_A4H = 0x00008da6U;
+        SCE->REG_04H = 0x0000c100U;
+        iLoop = 0;
+            if(S_RAM[0] >= 4) 
+        {
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_Text[0];
+            SCE->REG_100H = InData_Text[1];
+            SCE->REG_100H = InData_Text[2];
+            SCE->REG_100H = InData_Text[3];
+            for (iLoop = 4; iLoop < S_RAM[0]; iLoop = iLoop + 4)
+            {
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+            }
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+        }
+        HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+        HW_SCE_p_func100(0xad8d9eaeU, 0x706f5f14U, 0x7bef6bc4U, 0xabf8742fU);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_p_func102(0xf873ac20U, 0xd6e03ba4U, 0x46939fbbU, 0xbde20dceU);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            SCE->REG_ECH = 0x38008c00U;
+            SCE->REG_ECH = 0x0000007fU;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00A60000U;
+            HW_SCE_p_func100(0x73f68803U, 0xf98e911dU, 0xe6edc7d1U, 0xefa122a3U);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_B0H = 0x40000020U;
+                SCE->REG_A4H = 0x00008da5U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_E0H = 0x80840006U;
+                SCE->REG_00H = 0x00008113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_ECH = 0x0000b4e0U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_104H = 0x00000368U;
+                SCE->REG_E0H = 0x80840007U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+4 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+5 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+6 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+7 + 0];
+                SCE->REG_ECH = 0x0000b4a0U;
+                SCE->REG_ECH = 0x00000004U;
+                SCE->REG_ECH = 0x00003500U;
+                SCE->REG_ECH = 0x00036908U;
+                SCE->REG_ECH = 0x00008d00U;
+                SCE->REG_ECH = 0x0000000cU;
+                SCE->REG_ECH = 0x000024c8U;
+                SCE->REG_ECH = 0x000024e8U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_ECH = 0x00003847U;
+                SCE->REG_ECH = 0x00003460U;
+                SCE->REG_ECH = 0x00008c60U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x0000b480U;
+                SCE->REG_ECH = 0xffffffffU;
+                SCE->REG_ECH = 0x00004403U;
+                SCE->REG_ECH = 0x00007484U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_ECH = 0x00001484U;
+                SCE->REG_ECH = 0x00000c44U;
+                SCE->REG_ECH = 0x00001041U;
+                SCE->REG_ECH = 0x00003c47U;
+                SCE->REG_ECH = 0x000037e0U;
+                SCE->REG_ECH = 0x00008fe0U;
+                SCE->REG_ECH = 0x0000007fU;
+                SCE->REG_ECH = 0x38008fe0U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x1000a7e0U;
+                SCE->REG_ECH = 0x00000020U;
+                SCE->REG_ECH = 0x0000b7c0U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_ECH = 0x00002bdfU;
+                SCE->REG_ECH = 0x00056bdeU;
+                SCE->REG_ECH = 0x0000353eU;
+                HW_SCE_p_func100(0x598bc922U, 0xa30c1bc1U, 0x145e6f3bU, 0x79f23b31U);
+                SCE->REG_E0H = 0x810103c0U;
+                SCE->REG_04H = 0x00000606U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                S_RAM[0] = change_endian_long(SCE->REG_100H);
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x000024c5U;
+                    SCE->REG_ECH = 0x000024e5U;
+                    SCE->REG_ECH = 0x00003ba6U;
+                    SCE->REG_ECH = 0x00003fa7U;
+                    SCE->REG_ECH = 0x000033c0U;
+                    HW_SCE_p_func101(0xe18457e3U, 0x59405a68U, 0x02cca054U, 0x6014c0e7U);
+                }
+                SCE->REG_ECH = 0x38000fdeU;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_ECH = 0x0000b4e0U;
+                SCE->REG_ECH = 0x00000010U;
+                HW_SCE_p_func100(0x1062e713U, 0xbcca75b5U, 0x75965907U, 0x18ed182bU);
+                SCE->REG_B0H = 0x40000020U;
+                SCE->REG_A4H = 0x00008da5U;
+                SCE->REG_E0H = 0x81840007U;
+                SCE->REG_00H = 0x00001813U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_04H = 0x00000112U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop + 0] = SCE->REG_100H;
+                OutData_Text[iLoop + 1] = SCE->REG_100H;
+                OutData_Text[iLoop + 2] = SCE->REG_100H;
+                OutData_Text[iLoop + 3] = SCE->REG_100H;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_ECH = 0x000024c8U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_ECH = 0x00003c26U;
+                SCE->REG_ECH = 0x00000bffU;
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x000024c5U;
+                    SCE->REG_ECH = 0x00003fe6U;
+                    SCE->REG_ECH = 0x00003120U;
+                    HW_SCE_p_func101(0x2f712768U, 0x3e99d3f0U, 0x5cb8453dU, 0xf777f65bU);
+                }
+                SCE->REG_ECH = 0x38000d29U;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                HW_SCE_p_func100(0xdd48f516U, 0x54f2d236U, 0xaa8b6a98U, 0x46b073a7U);
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_E0H = 0x81840006U;
+                SCE->REG_04H = 0x00000612U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+4 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+5 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+6 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+7 + 0] = SCE->REG_100H;
+                HW_SCE_p_func101(0x65dea63bU, 0x27bfd024U, 0x576cbffeU, 0x2895cfbdU);
+            }
+            HW_SCE_p_func102(0xfbc356b3U, 0x8cd24c21U, 0xd18d8ddeU, 0x915b4ae8U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_SUCCESS;
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pb9f.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb9i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb9i.c
new file mode 100644
index 000000000..0ce0cc446
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb9i.c
@@ -0,0 +1,197 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes256XtsEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x0000b901U;
+    SCE->REG_108H = 0x00000000U;
+    HW_SCE_p_func100(0xcf0df0d7U, 0xc94ad4ffU, 0xdde903b0U, 0xae2d501cU);
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x200c3b0dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[0];
+    SCE->REG_100H = InData_KeyIndex[1];
+    SCE->REG_100H = InData_KeyIndex[2];
+    SCE->REG_100H = InData_KeyIndex[3];
+    SCE->REG_A4H = 0x000c0b0cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x5737b943U);
+    SCE->REG_A4H = 0x02f8073dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[4];
+    SCE->REG_100H = InData_KeyIndex[5];
+    SCE->REG_100H = InData_KeyIndex[6];
+    SCE->REG_100H = InData_KeyIndex[7];
+    HW_SCE_p_func100(0xdedfdf9dU, 0x11b3163eU, 0x2cff7867U, 0x4d621404U);
+    SCE->REG_A4H = 0x00f9073dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[8];
+    SCE->REG_100H = InData_KeyIndex[9];
+    SCE->REG_100H = InData_KeyIndex[10];
+    SCE->REG_100H = InData_KeyIndex[11];
+    HW_SCE_p_func100(0x7f0472e2U, 0x9bf24d24U, 0x051dd28fU, 0x70afe8c6U);
+    SCE->REG_A4H = 0x00fa073dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[12];
+    SCE->REG_100H = InData_KeyIndex[13];
+    SCE->REG_100H = InData_KeyIndex[14];
+    SCE->REG_100H = InData_KeyIndex[15];
+    HW_SCE_p_func100(0xb88882f7U, 0x37874313U, 0x55ebbe4aU, 0xafc87fe3U);
+    SCE->REG_A4H = 0x00fb073dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[16];
+    SCE->REG_100H = InData_KeyIndex[17];
+    SCE->REG_100H = InData_KeyIndex[18];
+    SCE->REG_100H = InData_KeyIndex[19];
+    SCE->REG_A4H = 0x000007bdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[20];
+    SCE->REG_100H = InData_KeyIndex[21];
+    SCE->REG_100H = InData_KeyIndex[22];
+    SCE->REG_100H = InData_KeyIndex[23];
+    SCE->REG_A4H = 0x00900c45U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_p_func100(0x452c5099U, 0x8aac17a6U, 0x17dca341U, 0x7a516e07U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0x71adfa08U, 0x14fc3404U, 0x8dbca5abU, 0x9fa60f4fU);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+    }
+    else
+    {
+        SCE->REG_104H = 0x00000361U;
+        SCE->REG_B0H = 0x40000000U;
+        SCE->REG_A4H = 0x0004aa05U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_IV[0];
+        SCE->REG_100H = InData_IV[1];
+        SCE->REG_100H = InData_IV[2];
+        SCE->REG_100H = InData_IV[3];
+        return FSP_SUCCESS;
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pb9i.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb9u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb9u.c
new file mode 100644
index 000000000..b59896d72
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pb9u.c
@@ -0,0 +1,127 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes256XtsEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_p_func100(0x02a4f808U, 0xab90621fU, 0xeee875afU, 0x0a4db5abU);
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_B0H = 0x40000020U;
+    SCE->REG_A4H = 0x00008da6U;
+    SCE->REG_04H = 0x0000c100U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_Text[0];
+    SCE->REG_100H = InData_Text[1];
+    SCE->REG_100H = InData_Text[2];
+    SCE->REG_100H = InData_Text[3];
+    for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    }
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+    HW_SCE_p_func101(0xcd8c9861U, 0xe9018d64U, 0x47c58717U, 0x6fb3a773U);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pb9u.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pc2f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pc2f.c
new file mode 100644
index 000000000..bb3e2fccf
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pc2f.c
@@ -0,0 +1,423 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes256XtsDecryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x80010000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_TextBitLen[0];
+    SCE->REG_ECH = 0x000037c0U;
+    SCE->REG_ECH = 0x00076bdeU;
+    SCE->REG_ECH = 0x00026fdeU;
+    SCE->REG_ECH = 0x00000bffU;
+    SCE->REG_ECH = 0x38008c00U;
+    SCE->REG_ECH = 0x0000007fU;
+    SCE->REG_ECH = 0x00020020U;
+    SCE->REG_ECH = 0x3420a800U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_ECH = 0x1000d3e0U;
+    SCE->REG_ECH = 0x2000abc0U;
+    SCE->REG_ECH = 0x00000004U;
+    SCE->REG_ECH = 0x00000080U;
+    SCE->REG_ECH = 0x38000fffU;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00A60000U;
+    HW_SCE_p_func100(0x229da61dU, 0x9513d0a8U, 0xab03ae9bU, 0x826405b0U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0x5ec78887U, 0x8d8b599fU, 0x2a039cccU, 0x65fb6735U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        HW_SCE_p_func100(0x685f9d9aU, 0xc2284c09U, 0x3a04d08eU, 0xa07f92d0U);
+        SCE->REG_E0H = 0x810103c0U;
+        SCE->REG_04H = 0x00000606U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        S_RAM[0] = change_endian_long(SCE->REG_100H);
+        HW_SCE_p_func100(0x77e1c5d3U, 0xa90d6811U, 0xeaf23c40U, 0x6c1cda72U);
+        SCE->REG_104H = 0x000000b1U;
+        SCE->REG_B0H = 0x40000020U;
+        SCE->REG_A4H = 0x0000cda6U;
+        SCE->REG_04H = 0x0000c100U;
+        iLoop = 0;
+            if(S_RAM[0] >= 4) 
+        {
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_Text[0];
+            SCE->REG_100H = InData_Text[1];
+            SCE->REG_100H = InData_Text[2];
+            SCE->REG_100H = InData_Text[3];
+            for (iLoop = 4; iLoop < S_RAM[0]; iLoop = iLoop + 4)
+            {
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+                OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+            }
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+            OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+        }
+        HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+        HW_SCE_p_func100(0x1b196f1fU, 0x354fea9eU, 0xc64b0d0fU, 0x71b1f2cdU);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_p_func102(0xefb12f73U, 0x1e840e86U, 0xa06be3c7U, 0xd6004449U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_FAIL;
+        }
+        else
+        {
+            SCE->REG_ECH = 0x38008c00U;
+            SCE->REG_ECH = 0x0000007fU;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00A60000U;
+            HW_SCE_p_func100(0x327d16efU, 0x7d621ba0U, 0xda470300U, 0x300a14b9U);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_p_func100(0xf06fa039U, 0x7363f258U, 0x9772d3ebU, 0x2adab3feU);
+                SCE->REG_104H = 0x00000051U;
+                SCE->REG_A4H = 0x00000c84U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = change_endian_long(0x00000000U);
+                SCE->REG_E0H = 0x80040140U;
+                SCE->REG_00H = 0x00008113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_104H = 0x00000051U;
+                SCE->REG_B0H = 0x40000020U;
+                SCE->REG_A4H = 0x0000cd24U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = change_endian_long(0x00000000U);
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_B0H = 0x40000020U;
+                SCE->REG_A4H = 0x0000cda5U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop + 0];
+                SCE->REG_100H = InData_Text[iLoop + 1];
+                SCE->REG_100H = InData_Text[iLoop + 2];
+                SCE->REG_100H = InData_Text[iLoop + 3];
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_E0H = 0x80840006U;
+                SCE->REG_00H = 0x00008113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_ECH = 0x0000b4e0U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_104H = 0x00000368U;
+                SCE->REG_E0H = 0x80840007U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+4 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+5 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+6 + 0];
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[iLoop+7 + 0];
+                SCE->REG_ECH = 0x0000b4a0U;
+                SCE->REG_ECH = 0x00000004U;
+                SCE->REG_ECH = 0x00003500U;
+                SCE->REG_ECH = 0x00036908U;
+                SCE->REG_ECH = 0x00008d00U;
+                SCE->REG_ECH = 0x0000000cU;
+                SCE->REG_ECH = 0x000024c8U;
+                SCE->REG_ECH = 0x000024e8U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_ECH = 0x00003847U;
+                SCE->REG_ECH = 0x00003460U;
+                SCE->REG_ECH = 0x00008c60U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x0000b480U;
+                SCE->REG_ECH = 0xffffffffU;
+                SCE->REG_ECH = 0x00004403U;
+                SCE->REG_ECH = 0x00007484U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_ECH = 0x00001484U;
+                SCE->REG_ECH = 0x00000c44U;
+                SCE->REG_ECH = 0x00001041U;
+                SCE->REG_ECH = 0x00003c47U;
+                SCE->REG_ECH = 0x000037e0U;
+                SCE->REG_ECH = 0x00008fe0U;
+                SCE->REG_ECH = 0x0000007fU;
+                SCE->REG_ECH = 0x38008fe0U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x1000a7e0U;
+                SCE->REG_ECH = 0x00000020U;
+                SCE->REG_ECH = 0x0000b7c0U;
+                SCE->REG_ECH = 0x00000080U;
+                SCE->REG_ECH = 0x00002bdfU;
+                SCE->REG_ECH = 0x00056bdeU;
+                SCE->REG_ECH = 0x0000353eU;
+                SCE->REG_E0H = 0x810103c0U;
+                SCE->REG_04H = 0x00000606U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                S_RAM[0] = change_endian_long(SCE->REG_100H);
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x000024c5U;
+                    SCE->REG_ECH = 0x000024e5U;
+                    SCE->REG_ECH = 0x00003ba6U;
+                    SCE->REG_ECH = 0x00003fa7U;
+                    SCE->REG_ECH = 0x000033c0U;
+                    HW_SCE_p_func101(0xae4bd0b9U, 0x1578f531U, 0x46a266aaU, 0x82a08f99U);
+                }
+                HW_SCE_p_func100(0x547bb80fU, 0xf4755c29U, 0x62d86e03U, 0xa85e7b9dU);
+                SCE->REG_ECH = 0x38000fdeU;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_A4H = 0x00040805U;
+                SCE->REG_E0H = 0x81040140U;
+                SCE->REG_00H = 0x00001813U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_ECH = 0x0000b4e0U;
+                SCE->REG_ECH = 0x00000010U;
+                SCE->REG_B0H = 0x40000020U;
+                SCE->REG_A4H = 0x0000cda5U;
+                SCE->REG_E0H = 0x81840007U;
+                SCE->REG_00H = 0x00001813U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_04H = 0x00000112U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop + 0] = SCE->REG_100H;
+                OutData_Text[iLoop + 1] = SCE->REG_100H;
+                OutData_Text[iLoop + 2] = SCE->REG_100H;
+                OutData_Text[iLoop + 3] = SCE->REG_100H;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_ECH = 0x000024c8U;
+                SCE->REG_ECH = 0x00003826U;
+                SCE->REG_ECH = 0x00000c24U;
+                SCE->REG_ECH = 0x00003c26U;
+                SCE->REG_ECH = 0x00000bffU;
+                for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1)
+                {
+                    SCE->REG_ECH = 0x000024c5U;
+                    SCE->REG_ECH = 0x00003fe6U;
+                    SCE->REG_ECH = 0x00003120U;
+                    HW_SCE_p_func101(0x2ec87fc2U, 0x68d6b223U, 0xc906cb5aU, 0xed26e21bU);
+                }
+                HW_SCE_p_func100(0xa25cad7dU, 0x937ac89aU, 0xed02a819U, 0x9762f0efU);
+                SCE->REG_ECH = 0x38000d29U;
+                SCE->REG_E0H = 0x00000080U;
+                SCE->REG_1CH = 0x00260000U;
+                SCE->REG_1CH = 0x00402000U;
+                SCE->REG_ECH = 0x000008c6U;
+                SCE->REG_E0H = 0x81840006U;
+                SCE->REG_04H = 0x00000612U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+4 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+5 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+6 + 0] = SCE->REG_100H;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_04H_b.B30)
+                {
+                    /* waiting */
+                }
+                OutData_Text[iLoop+7 + 0] = SCE->REG_100H;
+                HW_SCE_p_func101(0x0dcb7782U, 0x15b4a5c3U, 0x30442b72U, 0x0c459048U);
+            }
+            HW_SCE_p_func102(0x672acfe5U, 0x96b45d68U, 0x613664eaU, 0x90dcb54dU);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_SUCCESS;
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pc2f.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pc2i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pc2i.c
new file mode 100644
index 000000000..70167509b
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pc2i.c
@@ -0,0 +1,197 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes256XtsDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x0000c201U;
+    SCE->REG_108H = 0x00000000U;
+    HW_SCE_p_func100(0x9aea7b2bU, 0x4eaa40d7U, 0x979c124aU, 0x689b5539U);
+    SCE->REG_104H = 0x00000361U;
+    SCE->REG_A4H = 0x200c3b0dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[0];
+    SCE->REG_100H = InData_KeyIndex[1];
+    SCE->REG_100H = InData_KeyIndex[2];
+    SCE->REG_100H = InData_KeyIndex[3];
+    SCE->REG_A4H = 0x000c0b0cU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = change_endian_long(0x5737b943U);
+    SCE->REG_A4H = 0x02f8073dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[4];
+    SCE->REG_100H = InData_KeyIndex[5];
+    SCE->REG_100H = InData_KeyIndex[6];
+    SCE->REG_100H = InData_KeyIndex[7];
+    HW_SCE_p_func100(0xc58b4be7U, 0x78280051U, 0x5efaa65eU, 0xfcb515c8U);
+    SCE->REG_A4H = 0x00f9073dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[8];
+    SCE->REG_100H = InData_KeyIndex[9];
+    SCE->REG_100H = InData_KeyIndex[10];
+    SCE->REG_100H = InData_KeyIndex[11];
+    HW_SCE_p_func100(0xda7354e5U, 0xcd02e475U, 0xc3846981U, 0x1f27921aU);
+    SCE->REG_A4H = 0x00fa073dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[12];
+    SCE->REG_100H = InData_KeyIndex[13];
+    SCE->REG_100H = InData_KeyIndex[14];
+    SCE->REG_100H = InData_KeyIndex[15];
+    HW_SCE_p_func100(0xbe8a2f6aU, 0x8b3a3b45U, 0x8fb61526U, 0xda8d78ccU);
+    SCE->REG_A4H = 0x00fb073dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[16];
+    SCE->REG_100H = InData_KeyIndex[17];
+    SCE->REG_100H = InData_KeyIndex[18];
+    SCE->REG_100H = InData_KeyIndex[19];
+    SCE->REG_A4H = 0x000007bdU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyIndex[20];
+    SCE->REG_100H = InData_KeyIndex[21];
+    SCE->REG_100H = InData_KeyIndex[22];
+    SCE->REG_100H = InData_KeyIndex[23];
+    SCE->REG_A4H = 0x00900c45U;
+    SCE->REG_00H = 0x00001113U;
+    /* WAIT_LOOP */
+    while (0U != SCE->REG_00H_b.B25)
+    {
+        /* waiting */
+    }
+    SCE->REG_1CH = 0x00001800U;
+    HW_SCE_p_func100(0x82166c98U, 0xa3bb6e42U, 0xdb93e04dU, 0xbc4c67daU);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0xe7c5f44fU, 0x8b6b9980U, 0x6aec75e6U, 0x7581737eU);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+    }
+    else
+    {
+        SCE->REG_104H = 0x00000361U;
+        SCE->REG_B0H = 0x40000000U;
+        SCE->REG_A4H = 0x0004aa05U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_IV[0];
+        SCE->REG_100H = InData_IV[1];
+        SCE->REG_100H = InData_IV[2];
+        SCE->REG_100H = InData_IV[3];
+        return FSP_SUCCESS;
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pc2i.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pc2u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pc2u.c
new file mode 100644
index 000000000..55cb2c9c8
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pc2u.c
@@ -0,0 +1,127 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes256XtsDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_p_func100(0x34b697a3U, 0xc83df7b8U, 0x66a86f9aU, 0x696b4cf4U);
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_B0H = 0x40000020U;
+    SCE->REG_A4H = 0x0000cda6U;
+    SCE->REG_04H = 0x0000c100U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_Text[0];
+    SCE->REG_100H = InData_Text[1];
+    SCE->REG_100H = InData_Text[2];
+    SCE->REG_100H = InData_Text[3];
+    for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_04H_b.B30)
+        {
+            /* waiting */
+        }
+        OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+        OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    }
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_04H_b.B30)
+    {
+        /* waiting */
+    }
+    OutData_Text[iLoop-4 + 0] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 1] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 2] = SCE->REG_100H;
+    OutData_Text[iLoop-4 + 3] = SCE->REG_100H;
+    HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction.
+    HW_SCE_p_func101(0x6d03655dU, 0x3ae405a7U, 0x9ff9740eU, 0xc716aad6U);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pc2u.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/SCE_module.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/SCE_module.h
index 676eb12bc..322f4cbb1 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/SCE_module.h
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/SCE_module.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/hw_sce_ra_private.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/hw_sce_ra_private.h
index c3233d55d..b5aeb7171 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/hw_sce_ra_private.h
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/hw_sce_ra_private.h
@@ -63,11 +63,11 @@
  #define SIZE_AES_256BIT_KEYLEN_BYTES_WRAPPED    ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 8)
  #define SIZE_AES_256BIT_KEYLEN_WORDS_WRAPPED    ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 32)
 
- #define SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED     (416)
+ #define SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED     (512)
  #define SIZE_AES_XTS_128BIT_KEYLEN_BYTES_WRAPPED    ((SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED) / 8)
  #define SIZE_AES_XTS_128BIT_KEYLEN_WORDS_WRAPPED    ((SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED) / 32)
 
- #define SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED     (672)
+ #define SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED     (768)
  #define SIZE_AES_XTS_256BIT_KEYLEN_BYTES_WRAPPED    ((SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED) / 8)
  #define SIZE_AES_XTS_256BIT_KEYLEN_WORDS_WRAPPED    ((SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED) / 32)
  
@@ -412,7 +412,10 @@ fsp_err_t HW_SCE_GenerateAes192KeyIndexSub(uint32_t *InData_KeyType, uint32_t *I
         uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex);
 fsp_err_t HW_SCE_GenerateAes256KeyIndexSub(const uint32_t * const InData_KeyType, const uint32_t * const InData_SharedKeyIndex,
         const uint32_t * const InData_SessionKey, const uint32_t * const InData_IV, const uint32_t * const InData_InstData, uint32_t * const OutData_KeyIndex);
-
+fsp_err_t HW_SCE_GenerateAes128XtsKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex,
+         uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex);
+fsp_err_t HW_SCE_GenerateAes256XtsKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, 
+        uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex);         
 fsp_err_t HW_SCE_GenerateAes128RandomKeyIndexSub(uint32_t *OutData_KeyIndex);
 fsp_err_t HW_SCE_GenerateAes192RandomKeyIndexSub(uint32_t *OutData_KeyIndex);
 fsp_err_t HW_SCE_GenerateAes256RandomKeyIndexSub(uint32_t *OutData_KeyIndex);
@@ -568,13 +571,13 @@ void         HW_SCE_Aes192GcmDecryptUpdateAADSub(uint32_t *InData_DataA, uint32_
 void         HW_SCE_Aes256GcmEncryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT);
 void         HW_SCE_Aes256GcmDecryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT);
 
-fsp_err_t HW_SCE_Aes128CcmEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header,
-        uint32_t Header_Len);
+fsp_err_t HW_SCE_Aes128CcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV, 
+        uint32_t *InData_Header, uint32_t Header_Len);
 void HW_SCE_Aes128CcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT);
 fsp_err_t HW_SCE_Aes128CcmEncryptFinalSub(uint32_t *InData_TextLen, uint32_t *InData_Text, uint32_t *OutData_Text,
         uint32_t *OutData_MAC);
-fsp_err_t HW_SCE_Aes128CcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header,
-        uint32_t Header_Len);
+fsp_err_t HW_SCE_Aes128CcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV, 
+        uint32_t *InData_Header, uint32_t Header_Len);
 void HW_SCE_Aes128CcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT);
 fsp_err_t HW_SCE_Aes128CcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_TextLen, uint32_t *InData_MAC,
         uint32_t *InData_MACLength, uint32_t *OutData_Text);
@@ -590,18 +593,18 @@ void HW_SCE_Aes192CcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_T
 fsp_err_t HW_SCE_Aes192CcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_TextLen, uint32_t *InData_MAC,
         uint32_t *InData_MACLength, uint32_t *OutData_Text);
 
-fsp_err_t HW_SCE_Aes256CcmEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header,
-        uint32_t Header_Len);
+fsp_err_t HW_SCE_Aes256CcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV, 
+        uint32_t *InData_Header, uint32_t Header_Len);
 void HW_SCE_Aes256CcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT);
 fsp_err_t HW_SCE_Aes256CcmEncryptFinalSub(uint32_t *InData_TextLen, uint32_t *InData_Text, uint32_t *OutData_Text,
         uint32_t *OutData_MAC);
-fsp_err_t HW_SCE_Aes256CcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header,
-        uint32_t Header_Len);
+fsp_err_t HW_SCE_Aes256CcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV, 
+        uint32_t *InData_Header, uint32_t Header_Len);
 void HW_SCE_Aes256CcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT);
 fsp_err_t HW_SCE_Aes256CcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_TextLen, uint32_t *InData_MAC,
         uint32_t *InData_MACLength, uint32_t *OutData_Text);
 
-fsp_err_t HW_SCE_Aes128CmacInitSub(uint32_t *InData_KeyIndex);
+fsp_err_t HW_SCE_Aes128CmacInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex);
 void         HW_SCE_Aes128CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT);
 fsp_err_t HW_SCE_Aes128CmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_Text, uint32_t *InData_DataT,
         uint32_t *InData_DataTLen, uint32_t *OutData_DataT);
@@ -609,7 +612,7 @@ fsp_err_t HW_SCE_Aes192CmacInitSub(uint32_t *InData_KeyIndex);
 void         HW_SCE_Aes192CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT);
 fsp_err_t HW_SCE_Aes192CmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_Text, uint32_t *InData_DataT,
         uint32_t *InData_DataTLen, uint32_t *OutData_DataT);
-fsp_err_t HW_SCE_Aes256CmacInitSub(uint32_t *InData_KeyIndex);
+fsp_err_t HW_SCE_Aes256CmacInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex);
 void         HW_SCE_Aes256CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT);
 fsp_err_t HW_SCE_Aes256CmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_Text, uint32_t *InData_DataT,
         uint32_t *InData_DataTLen, uint32_t *OutData_DataT);
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/public/inc/r_sce_if.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/public/inc/r_sce_if.h
index 478daf15f..f0ce912fa 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/public/inc/r_sce_if.h
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/public/inc/r_sce_if.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_adapt.c
index c36c8d69e..77d960f94 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_adapt.c
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_adapt.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p41f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p41f.c
new file mode 100644
index 000000000..b9b8b165f
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p41f.c
@@ -0,0 +1,296 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes128CmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataTLen, uint32_t *OutData_DataT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    HW_SCE_p_func100(0x4a99ebceU, 0x994c779bU, 0xf070c5f0U, 0xd8443037U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0x17eb14a1U, 0xb77756aeU, 0xa6e65c9fU, 0xfba60a99U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000002U))
+        {
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00400a84U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            HW_SCE_p_func101(0xcc1c0947U, 0x99cbbd69U, 0xcbae7594U, 0x176a22c1U);
+        }
+        else
+        {
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00500a84U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            HW_SCE_p_func101(0xfd8f573dU, 0x0b0980a6U, 0x7cbf9d4dU, 0x60bc39c5U);
+        }
+        SCE->REG_A4H = 0x00040c05U;
+        SCE->REG_00H = 0x00001113U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000001U))
+        {
+            HW_SCE_p_func100(0xaecaecc1U, 0x365ceb89U, 0x853113fbU, 0xe4a9d73eU);
+            SCE->REG_104H = 0x00000361U;
+            SCE->REG_A4H = 0x00000e95U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_Text[0];
+            SCE->REG_100H = InData_Text[1];
+            SCE->REG_100H = InData_Text[2];
+            SCE->REG_100H = InData_Text[3];
+            SCE->REG_04H = 0x00000113U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_04H_b.B30)
+            {
+                /* waiting */
+            }
+            OutData_DataT[0] = SCE->REG_100H;
+            OutData_DataT[1] = SCE->REG_100H;
+            OutData_DataT[2] = SCE->REG_100H;
+            OutData_DataT[3] = SCE->REG_100H;
+            HW_SCE_p_func102(0x46910254U, 0xfe754650U, 0x87941303U, 0xbbb02417U);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_SUCCESS;
+        }
+        else
+        {
+            SCE->REG_104H = 0x00000068U;
+            SCE->REG_E0H = 0x80010040U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_DataTLen[0];
+            SCE->REG_ECH = 0x3420a840U;
+            SCE->REG_ECH = 0x00000010U;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00260000U;
+            SCE->REG_ECH = 0x0000b460U;
+            SCE->REG_ECH = 0x00000080U;
+            SCE->REG_ECH = 0x34202862U;
+            SCE->REG_E0H = 0x00000080U;
+            SCE->REG_1CH = 0x00260000U;
+            HW_SCE_p_func100(0x868c3fa6U, 0xcbebe6a2U, 0xa5e8d99fU, 0x4e7f2acbU);
+            SCE->REG_1CH = 0x00400000U;
+            SCE->REG_1D0H = 0x00000000U;
+            if (1U == (SCE->REG_1CH_b.B22))
+            {
+                HW_SCE_p_func102(0xc84095e3U, 0xfe73f3faU, 0x5d208506U, 0x4f06dd4dU);
+                SCE->REG_1BCH = 0x00000040U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_18H_b.B12)
+                {
+                    /* waiting */
+                }
+                return FSP_ERR_CRYPTO_SCE_FAIL;
+            }
+            else
+            {
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_A4H = 0x00000e95U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_Text[0];
+                SCE->REG_100H = InData_Text[1];
+                SCE->REG_100H = InData_Text[2];
+                SCE->REG_100H = InData_Text[3];
+                SCE->REG_ECH = 0x00000821U;
+                SCE->REG_E0H = 0x80840001U;
+                SCE->REG_00H = 0x00008113U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_ECH = 0x000034e2U;
+                SCE->REG_ECH = 0x000568e7U;
+                SCE->REG_ECH = 0x00026ce7U;
+                SCE->REG_ECH = 0x00003827U;
+                SCE->REG_ECH = 0x0000b4c0U;
+                SCE->REG_ECH = 0x00000020U;
+                SCE->REG_ECH = 0x00003402U;
+                SCE->REG_ECH = 0x00008c00U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x000028c0U;
+                SCE->REG_ECH = 0x00008cc0U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x00004406U;
+                SCE->REG_ECH = 0x00007421U;
+                SCE->REG_ECH = 0x00007821U;
+                SCE->REG_ECH = 0x00003c27U;
+                SCE->REG_ECH = 0x000034c2U;
+                SCE->REG_ECH = 0x0000a4c0U;
+                SCE->REG_ECH = 0x0000001fU;
+                SCE->REG_ECH = 0x000568c6U;
+                SCE->REG_ECH = 0x000034e6U;
+                SCE->REG_ECH = 0x00026ce7U;
+                SCE->REG_ECH = 0x00000821U;
+                for (iLoop = 0; iLoop < 4; iLoop = iLoop+1)
+                {
+                    SCE->REG_ECH = 0x3420a8e0U;
+                    SCE->REG_ECH = 0x0000000dU;
+                    SCE->REG_ECH = 0x10003c27U;
+                    SCE->REG_ECH = 0x1000a4e0U;
+                    SCE->REG_ECH = 0x00000004U;
+                }
+                SCE->REG_A4H = 0x00040805U;
+                SCE->REG_E0H = 0x81840001U;
+                SCE->REG_00H = 0x00001813U;
+                /* WAIT_LOOP */
+                while (0U != SCE->REG_00H_b.B25)
+                {
+                    /* waiting */
+                }
+                SCE->REG_1CH = 0x00001800U;
+                SCE->REG_104H = 0x00000361U;
+                SCE->REG_A4H = 0x00900c05U;
+                /* WAIT_LOOP */
+                while (1U != SCE->REG_104H_b.B31)
+                {
+                    /* waiting */
+                }
+                SCE->REG_100H = InData_DataT[0];
+                SCE->REG_100H = InData_DataT[1];
+                SCE->REG_100H = InData_DataT[2];
+                SCE->REG_100H = InData_DataT[3];
+                HW_SCE_p_func100(0x209fb07dU, 0x45c52359U, 0x8bd1ffb8U, 0x63570637U);
+                SCE->REG_1CH = 0x00400000U;
+                SCE->REG_1D0H = 0x00000000U;
+                if (1U == (SCE->REG_1CH_b.B22))
+                {
+                    HW_SCE_p_func102(0xc546b264U, 0xb50aa63aU, 0x59d29b24U, 0x618a6db3U);
+                    SCE->REG_1BCH = 0x00000040U;
+                    /* WAIT_LOOP */
+                    while (0U != SCE->REG_18H_b.B12)
+                    {
+                        /* waiting */
+                    }
+                    return FSP_ERR_CRYPTO_SCE_AUTHENTICATION;
+                }
+                else
+                {
+                    HW_SCE_p_func102(0x927f099dU, 0xa622d40dU, 0x3fd396adU, 0x3552f048U);
+                    SCE->REG_1BCH = 0x00000040U;
+                    /* WAIT_LOOP */
+                    while (0U != SCE->REG_18H_b.B12)
+                    {
+                        /* waiting */
+                    }
+                    return FSP_SUCCESS;
+                }
+            }
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p41f_r1.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p41i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p41i.c
new file mode 100644
index 000000000..dd40204c3
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p41i.c
@@ -0,0 +1,258 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+fsp_err_t HW_SCE_Aes128CmacInitSub(uint32_t *InData_KeyIndex)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    uint32_t InData_KeyType[1] = {0};
+    if (0x0U != (SCE->REG_1BCH & 0x1fU))
+    {
+        return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT;
+    }
+    SCE->REG_84H = 0x00004102U;
+    SCE->REG_108H = 0x00000000U;
+    SCE->REG_C4H = 0x200e1a0dU;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = S_RAM[20+0 + 0];
+    SCE->REG_100H = S_RAM[20+0 + 1];
+    SCE->REG_100H = S_RAM[20+0 + 2];
+    SCE->REG_100H = S_RAM[20+0 + 3];
+    SCE->REG_104H = 0x00000068U;
+    SCE->REG_E0H = 0x80010000U;
+    /* WAIT_LOOP */
+    while (1U != SCE->REG_104H_b.B31)
+    {
+        /* waiting */
+    }
+    SCE->REG_100H = InData_KeyType[0];
+    SCE->REG_ECH = 0x38008800U;
+    SCE->REG_ECH = 0x00000001U;
+    SCE->REG_E0H = 0x00000080U;
+    SCE->REG_1CH = 0x00260000U;
+    HW_SCE_p_func100(0xabd38050U, 0x5ba81f06U, 0x71f86840U, 0xab20a600U);
+    SCE->REG_1CH = 0x00400000U;
+    SCE->REG_1D0H = 0x00000000U;
+    if (1U == (SCE->REG_1CH_b.B22))
+    {
+        HW_SCE_p_func102(0x40c3155fU, 0xfade58a2U, 0x81b2308cU, 0xbec9a415U);
+        SCE->REG_1BCH = 0x00000040U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_18H_b.B12)
+        {
+            /* waiting */
+        }
+        return FSP_ERR_CRYPTO_SCE_FAIL;
+    }
+    else
+    {
+        SCE->REG_ECH = 0x38000c00U;
+        SCE->REG_E0H = 0x00000080U;
+        SCE->REG_1CH = 0x00260000U;
+        HW_SCE_p_func100(0xfa043140U, 0x2c6b0e94U, 0x20a68d42U, 0x37f054e3U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            SCE->REG_104H = 0x00000068U;
+            SCE->REG_E0H = 0x800100e0U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_KeyIndex[0];
+            SCE->REG_104H = 0x00000058U;
+            SCE->REG_E0H = 0x800103a0U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000041U);
+            HW_SCE_p_func101(0x98a04074U, 0x66bafebeU, 0xd412c527U, 0xf52309f8U);
+            HW_SCE_p_func043();
+            SCE->REG_ECH = 0x0000b4e0U;
+            SCE->REG_ECH = 0x00000005U;
+            HW_SCE_p_func101(0x26d01534U, 0x98e8e4ebU, 0xdc58bfdaU, 0xc07e7d51U);
+        }
+        else
+        {
+            SCE->REG_104H = 0x00000068U;
+            SCE->REG_E0H = 0x80010140U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = InData_KeyIndex[0];
+            SCE->REG_104H = 0x00000058U;
+            SCE->REG_E0H = 0x800103a0U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000041U);
+            HW_SCE_p_func101(0x4e3ea3a0U, 0xfdb662dcU, 0x180a7f7cU, 0x63cbe076U);
+            HW_SCE_p_func068();
+            SCE->REG_ECH = 0x0000b4e0U;
+            SCE->REG_ECH = 0x0146c04bU;
+            HW_SCE_p_func101(0xdf744ad9U, 0x6c17598fU, 0x12d94ec0U, 0xd9ea16a9U);
+        }
+        SCE->REG_104H = 0x00000058U;
+        SCE->REG_E0H = 0x800103a0U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = change_endian_long(0x00000041U);
+        HW_SCE_p_func101(0xac6c999cU, 0xf27778f2U, 0x330f1addU, 0x0d60716eU);
+        HW_SCE_p_func044();
+        HW_SCE_p_func100(0x4942a239U, 0x977f047cU, 0xb0220abfU, 0xc4aa2689U);
+        SCE->REG_104H = 0x00000362U;
+        SCE->REG_D0H = 0x40000000U;
+        SCE->REG_C4H = 0x02f087b5U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_KeyIndex[1];
+        SCE->REG_100H = InData_KeyIndex[2];
+        SCE->REG_100H = InData_KeyIndex[3];
+        SCE->REG_100H = InData_KeyIndex[4];
+        SCE->REG_A4H = 0x00080805U;
+        SCE->REG_00H = 0x00001213U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        SCE->REG_104H = 0x00000362U;
+        SCE->REG_D0H = 0x40000000U;
+        SCE->REG_C4H = 0x000087b5U;
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_KeyIndex[5];
+        SCE->REG_100H = InData_KeyIndex[6];
+        SCE->REG_100H = InData_KeyIndex[7];
+        SCE->REG_100H = InData_KeyIndex[8];
+        SCE->REG_C4H = 0x00900c45U;
+        SCE->REG_00H = 0x00002213U;
+        /* WAIT_LOOP */
+        while (0U != SCE->REG_00H_b.B25)
+        {
+            /* waiting */
+        }
+        SCE->REG_1CH = 0x00001800U;
+        HW_SCE_p_func100(0x99397a13U, 0x7c7f0177U, 0xc3d94e5cU, 0x78b7f2f6U);
+        SCE->REG_1CH = 0x00400000U;
+        SCE->REG_1D0H = 0x00000000U;
+        if (1U == (SCE->REG_1CH_b.B22))
+        {
+            HW_SCE_p_func102(0x93d24779U, 0xc0c06183U, 0x80c823c6U, 0x99b0bf1bU);
+            SCE->REG_1BCH = 0x00000040U;
+            /* WAIT_LOOP */
+            while (0U != SCE->REG_18H_b.B12)
+            {
+                /* waiting */
+            }
+            return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL;
+        }
+        else
+        {
+            SCE->REG_104H = 0x00000051U;
+            SCE->REG_A4H = 0x00040804U;
+            /* WAIT_LOOP */
+            while (1U != SCE->REG_104H_b.B31)
+            {
+                /* waiting */
+            }
+            SCE->REG_100H = change_endian_long(0x00000000U);
+            return FSP_SUCCESS;
+        }
+    }
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p41i_r1.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p41u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p41u.c
new file mode 100644
index 000000000..310824b14
--- /dev/null
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p41u.c
@@ -0,0 +1,97 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED  AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *         : 05.10.2020 1.00        First Release.
+ *         : 02.12.2020 1.01        Added new functions such as the Brainpool curve.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes   <System Includes> , "Project Includes"
+***********************************************************************************************************************/
+#include "r_sce_if.h"
+#include "hw_sce_ra_private.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Imported global variables and functions (from other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+void HW_SCE_Aes128CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT)
+{
+    uint32_t iLoop    = 0U;
+    uint32_t iLoop1   = 0U;
+    uint32_t iLoop2   = 0U;
+    int32_t  jLoop    = 0U;
+    uint32_t kLoop    = 0U;
+    uint32_t oLoop    = 0U;
+    uint32_t oLoop1   = 0U;
+    uint32_t oLoop2   = 0U;
+    uint32_t dummy    = 0U;
+    uint32_t KEY_ADR  = 0U;
+    uint32_t OFS_ADR  = 0U;
+    uint32_t MAX_CNT2 = 0U;
+    (void)iLoop;
+    (void)iLoop1;
+    (void)iLoop2;
+    (void)jLoop;
+    (void)kLoop;
+    (void)oLoop;
+    (void)oLoop1;
+    (void)oLoop2;
+    (void)dummy;
+    (void)KEY_ADR;
+    (void)OFS_ADR;
+    (void)MAX_CNT2;
+    SCE->REG_104H = 0x000000b1U;
+    SCE->REG_A4H = 0x00000e16U;
+    for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4)
+    {
+        /* WAIT_LOOP */
+        while (1U != SCE->REG_104H_b.B31)
+        {
+            /* waiting */
+        }
+        SCE->REG_100H = InData_Text[iLoop + 0];
+        SCE->REG_100H = InData_Text[iLoop + 1];
+        SCE->REG_100H = InData_Text[iLoop + 2];
+        SCE->REG_100H = InData_Text[iLoop + 3];
+    }
+    HW_SCE_p_func205();//DisableINTEGRATE_WRRDYBinthisfunction.
+    HW_SCE_p_func101(0x3076c9f4U, 0x318697edU, 0x87ee80b1U, 0x3ac079e1U);
+}
+
+/***********************************************************************************************************************
+End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p41u_r1.prc
+***********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/SCE_module.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/SCE_module.h
index 26bb94bec..64e75a67d 100644
--- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/SCE_module.h
+++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/SCE_module.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/hw_sce_aes_private.h b/ra/fsp/src/r_sce/hw_sce_aes_private.h
index 01df7bdd4..282ce8058 100644
--- a/ra/fsp/src/r_sce/hw_sce_aes_private.h
+++ b/ra/fsp/src/r_sce/hw_sce_aes_private.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/hw_sce_ecc_private.h b/ra/fsp/src/r_sce/hw_sce_ecc_private.h
index c342a4b7b..7abb4b233 100644
--- a/ra/fsp/src/r_sce/hw_sce_ecc_private.h
+++ b/ra/fsp/src/r_sce/hw_sce_ecc_private.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/hw_sce_hash_private.h b/ra/fsp/src/r_sce/hw_sce_hash_private.h
index f2a099274..aae167ac0 100644
--- a/ra/fsp/src/r_sce/hw_sce_hash_private.h
+++ b/ra/fsp/src/r_sce/hw_sce_hash_private.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/hw_sce_private.h b/ra/fsp/src/r_sce/hw_sce_private.h
index 802016dfc..f96b9f2d9 100644
--- a/ra/fsp/src/r_sce/hw_sce_private.h
+++ b/ra/fsp/src/r_sce/hw_sce_private.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/hw_sce_rsa_private.h b/ra/fsp/src/r_sce/hw_sce_rsa_private.h
index a791c900a..d7ac44e64 100644
--- a/ra/fsp/src/r_sce/hw_sce_rsa_private.h
+++ b/ra/fsp/src/r_sce/hw_sce_rsa_private.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/hw_sce_trng_private.h b/ra/fsp/src/r_sce/hw_sce_trng_private.h
index 082903223..49a160229 100644
--- a/ra/fsp/src/r_sce/hw_sce_trng_private.h
+++ b/ra/fsp/src/r_sce/hw_sce_trng_private.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/ra2/SC324_endian.c b/ra/fsp/src/r_sce/ra2/SC324_endian.c
index 602fd4774..22cdbbd82 100644
--- a/ra/fsp/src/r_sce/ra2/SC324_endian.c
+++ b/ra/fsp/src/r_sce/ra2/SC324_endian.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/ra2/SC324_p03.prc.c b/ra/fsp/src/r_sce/ra2/SC324_p03.prc.c
index 5d8cbca84..54572b171 100644
--- a/ra/fsp/src/r_sce/ra2/SC324_p03.prc.c
+++ b/ra/fsp/src/r_sce/ra2/SC324_p03.prc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/ra2/SC324_p04.prc.c b/ra/fsp/src/r_sce/ra2/SC324_p04.prc.c
index 6e5ee7e25..44dcd9371 100644
--- a/ra/fsp/src/r_sce/ra2/SC324_p04.prc.c
+++ b/ra/fsp/src/r_sce/ra2/SC324_p04.prc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/ra2/SC324_p05.prc.c b/ra/fsp/src/r_sce/ra2/SC324_p05.prc.c
index 3966814fb..134e277cb 100644
--- a/ra/fsp/src/r_sce/ra2/SC324_p05.prc.c
+++ b/ra/fsp/src/r_sce/ra2/SC324_p05.prc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/ra2/SC324_p06.prc.c b/ra/fsp/src/r_sce/ra2/SC324_p06.prc.c
index 3856bc856..0776ddc33 100644
--- a/ra/fsp/src/r_sce/ra2/SC324_p06.prc.c
+++ b/ra/fsp/src/r_sce/ra2/SC324_p06.prc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/ra2/SC324_p07.prc.c b/ra/fsp/src/r_sce/ra2/SC324_p07.prc.c
index 6910b15fe..71109be78 100644
--- a/ra/fsp/src/r_sce/ra2/SC324_p07.prc.c
+++ b/ra/fsp/src/r_sce/ra2/SC324_p07.prc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/ra2/SC324_p08.prc.c b/ra/fsp/src/r_sce/ra2/SC324_p08.prc.c
index 288da394d..cb85d9a58 100644
--- a/ra/fsp/src/r_sce/ra2/SC324_p08.prc.c
+++ b/ra/fsp/src/r_sce/ra2/SC324_p08.prc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/ra2/SC324_p20.prc.c b/ra/fsp/src/r_sce/ra2/SC324_p20.prc.c
index dea00d8d4..fe8837e1c 100644
--- a/ra/fsp/src/r_sce/ra2/SC324_p20.prc.c
+++ b/ra/fsp/src/r_sce/ra2/SC324_p20.prc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/ra2/SC324_p21.prc.c b/ra/fsp/src/r_sce/ra2/SC324_p21.prc.c
index 13a67a09c..293e140dc 100644
--- a/ra/fsp/src/r_sce/ra2/SC324_p21.prc.c
+++ b/ra/fsp/src/r_sce/ra2/SC324_p21.prc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/ra2/SC324_p22.prc.c b/ra/fsp/src/r_sce/ra2/SC324_p22.prc.c
index 3c2131f22..d729ca50a 100644
--- a/ra/fsp/src/r_sce/ra2/SC324_p22.prc.c
+++ b/ra/fsp/src/r_sce/ra2/SC324_p22.prc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/ra2/SC324_p23.prc.c b/ra/fsp/src/r_sce/ra2/SC324_p23.prc.c
index e847d6d79..b99642c80 100644
--- a/ra/fsp/src/r_sce/ra2/SC324_p23.prc.c
+++ b/ra/fsp/src/r_sce/ra2/SC324_p23.prc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/ra2/SC324_p24.prc.c b/ra/fsp/src/r_sce/ra2/SC324_p24.prc.c
index 7adaa5b13..8728f5a5b 100644
--- a/ra/fsp/src/r_sce/ra2/SC324_p24.prc.c
+++ b/ra/fsp/src/r_sce/ra2/SC324_p24.prc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/ra2/SC324_private.h b/ra/fsp/src/r_sce/ra2/SC324_private.h
index e8c6c9fd7..bdf19e178 100644
--- a/ra/fsp/src/r_sce/ra2/SC324_private.h
+++ b/ra/fsp/src/r_sce/ra2/SC324_private.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/ra2/SC324_utils.c b/ra/fsp/src/r_sce/ra2/SC324_utils.c
index d8a666152..852a69097 100644
--- a/ra/fsp/src/r_sce/ra2/SC324_utils.c
+++ b/ra/fsp/src/r_sce/ra2/SC324_utils.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -21,7 +21,7 @@
 #include "hw_sce_private.h"
 
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/ra2/SCE_module.h b/ra/fsp/src/r_sce/ra2/SCE_module.h
index 7deb9c2b0..1237b414c 100644
--- a/ra/fsp/src/r_sce/ra2/SCE_module.h
+++ b/ra/fsp/src/r_sce/ra2/SCE_module.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -20,6 +20,7 @@
 
 #ifndef HW_SCE_MODULE_H
 #define HW_SCE_MODULE_H
+#include "bsp_api.h"
 
 /* ================================================================================ */
 /* ================              Peripheral memory map             ================ */
diff --git a/ra/fsp/src/r_sce/ra2/sc324_aes_private.c b/ra/fsp/src/r_sce/ra2/sc324_aes_private.c
index 282efb31e..fc4005859 100644
--- a/ra/fsp/src/r_sce/ra2/sc324_aes_private.c
+++ b/ra/fsp/src/r_sce/ra2/sc324_aes_private.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce/ra2/sc324_aes_private.h b/ra/fsp/src/r_sce/ra2/sc324_aes_private.h
index e837530ae..fb4b9f382 100644
--- a/ra/fsp/src/r_sce/ra2/sc324_aes_private.h
+++ b/ra/fsp/src/r_sce/ra2/sc324_aes_private.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce_key_injection/r_sce_key_injection.c b/ra/fsp/src/r_sce_key_injection/r_sce_key_injection.c
index 742ead9e6..1eac2a727 100644
--- a/ra/fsp/src/r_sce_key_injection/r_sce_key_injection.c
+++ b/ra/fsp/src/r_sce_key_injection/r_sce_key_injection.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -77,8 +77,11 @@
 
 const sce_key_injection_api_t g_sce_key_injection_on_sce =
 {
-    .AES128_InitialKeyWrap = R_SCE_AES128_InitialKeyWrap,
-    .AES256_InitialKeyWrap = R_SCE_AES256_InitialKeyWrap,
+    .AES128_InitialKeyWrap                         = R_SCE_AES128_InitialKeyWrap,
+#if (SCE9)
+    .AES192_InitialKeyWrap                         = R_SCE_AES192_InitialKeyWrap,
+#endif
+    .AES256_InitialKeyWrap                         = R_SCE_AES256_InitialKeyWrap,
 #if ((SCE5) || (SCE7))
     .KeyUpdateKeyWrap        = R_SCE_KeyUpdateKeyWrap,
     .AES128_EncryptedKeyWrap = R_SCE_AES128_EncryptedKeyWrap,
@@ -110,7 +113,13 @@ const sce_key_injection_api_t g_sce_key_injection_on_sce =
     .ECC_secp384r1_EncryptedPublicKeyWrap  = R_SCE_ECC_secp384r1_EncryptedPublicKeyWrap,
     .ECC_secp384r1_EncryptedPrivateKeyWrap = R_SCE_ECC_secp384r1_EncryptedPrivateKeyWrap,
     .ECC_secp256k1_EncryptedPublicKeyWrap  = R_SCE_ECC_secp256k1_EncryptedPublicKeyWrap,
-    .ECC_secp256k1_EncryptedPrivateKeyWrap = R_SCE_ECC_secp256k1_EncryptedPrivateKeyWrap
+    .ECC_secp256k1_EncryptedPrivateKeyWrap = R_SCE_ECC_secp256k1_EncryptedPrivateKeyWrap,
+#endif
+#if (SCE9)
+    .ECC_brainpoolP256r1_InitialPublicKeyWrap  = R_SCE_ECC_brainpoolP256r1_InitialPublicKeyWrap,
+    .ECC_brainpoolP256r1_InitialPrivateKeyWrap = R_SCE_ECC_brainpoolP256r1_InitialPrivateKeyWrap,
+    .ECC_brainpoolP384r1_InitialPublicKeyWrap  = R_SCE_ECC_brainpoolP384r1_InitialPublicKeyWrap,
+    .ECC_brainpoolP384r1_InitialPrivateKeyWrap = R_SCE_ECC_brainpoolP384r1_InitialPrivateKeyWrap,
 #endif
 };
 
@@ -222,6 +231,82 @@ fsp_err_t R_SCE_AES128_InitialKeyWrap (const uint8_t * const         key_type,
     return error_code;
 }
 
+/*******************************************************************************************************************//**
+ * This API generates 192-bit AES key within the user routine.
+ *
+ * @param[in]     key_type                              Selection key type when generating wrapped key
+ *                                                      (0: for encrypted key, 1: for plain key)
+ * @param[in]     wrapped_user_factory_programming_key  Wrapped user factory programming key by the Renesas Key Wrap Service.
+ *                                                      When key_type is 1 as plain key, this is not required and
+ *                                                      any value can be specified.
+ * @param[in]     initial_vector                        Initialization vector when generating encrypted_key.
+ *                                                      When key_type is 1 as plain key, this is not required and
+ *                                                      any value can be specified.
+ * @param[in]     encrypted_key                         Encrypted user key and MAC appended
+ * @param[in,out] wrapped_key                           192-bit AES wrapped key
+ *
+ * @retval FSP_SUCCESS                          Normal termination.
+ * @retval FSP_ERR_UNSUPPORTED                  API not supported.
+ * @return If an error occurs, the return value will be as follows.
+ *         * FSP_ERR_CRYPTO_SCE_FAIL Internal I/O buffer is not empty.
+ *         * FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed.
+ *
+ * @note The pre-run state is SCE Enabled State.
+ *       After the function runs the state transitions to SCE Enabled State.
+ **********************************************************************************************************************/
+fsp_err_t R_SCE_AES192_InitialKeyWrap (const uint8_t * const         key_type,
+                                       const uint8_t * const         wrapped_user_factory_programming_key,
+                                       const uint8_t * const         initial_vector,
+                                       const uint8_t * const         encrypted_key,
+                                       sce_aes_wrapped_key_t * const wrapped_key)
+{
+    fsp_err_t error_code = FSP_SUCCESS;
+
+#if (SCE9)
+    uint32_t indata_keytype         = 0;
+    uint32_t install_key_ring_index = R_SCE_INSTALL_KEY_RING_INDEX;
+
+    uint32_t indata_cmd = SCE_OEM_CMD_AES192;
+    indata_keytype = change_endian_long((uint32_t) (*key_type));
+
+    if (0 == *key_type)
+    {
+        INST_DATA_SIZE = sce_oem_key_size[indata_cmd];
+    }
+    else
+    {
+        INST_DATA_SIZE = sce_oem_key_size[indata_cmd] - 4;
+    }
+
+    error_code = HW_SCE_GenerateOemKeyIndexSub(&indata_keytype,
+                                               &indata_cmd,
+                                               &install_key_ring_index,
+                                               (uint32_t *) wrapped_user_factory_programming_key,
+                                               (uint32_t *) initial_vector,
+                                               (uint32_t *) encrypted_key,
+                                               wrapped_key->value);
+    if (FSP_SUCCESS == error_code)
+    {
+        wrapped_key->type = SCE_KEY_INDEX_TYPE_AES192;
+    }
+    else
+    {
+        wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID;
+    }
+#else
+    error_code = FSP_ERR_UNSUPPORTED;
+
+    FSP_PARAMETER_NOT_USED(key_type);
+    FSP_PARAMETER_NOT_USED(wrapped_user_factory_programming_key);
+    FSP_PARAMETER_NOT_USED(initial_vector);
+    FSP_PARAMETER_NOT_USED(encrypted_key);
+    FSP_PARAMETER_NOT_USED(wrapped_key);
+    wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID;
+#endif
+
+    return error_code;
+}
+
 /*******************************************************************************************************************//**
  * This API generates 256-bit AES key within the user routine.
  *
@@ -1843,6 +1928,316 @@ fsp_err_t R_SCE_ECC_secp384r1_EncryptedPrivateKeyWrap (const uint8_t * const
     return error_code;
 }
 
+/*******************************************************************************************************************//**
+ * This API generates 256-bit Brainpool ECC key within the user routine.
+ *
+ * @param[in]     key_type                              Selection key type when generating wrapped key
+ *                                                      (0: for encrypted key, 1: for plain key)
+ * @param[in]     wrapped_user_factory_programming_key  Wrapped user factory programming key by the Renesas Key Wrap Service.
+ *                                                      When key_type is 1 as plain key, this is not required and
+ *                                                      any value can be specified.
+ * @param[in]     initial_vector                        Initialization vector when generating encrypted_key.
+ *                                                      When key_type is 1 as plain key, this is not required and
+ *                                                      any value can be specified.
+ * @param[in]     encrypted_key                         Encrypted user key and MAC appended
+ * @param[in,out] wrapped_key                           256-bit ECC wrapped key
+ *
+ * @retval FSP_SUCCESS                          Normal termination.
+ * @retval FSP_ERR_UNSUPPORTED                  API not supported.
+ * @return If an error occurs, the return value will be as follows.
+ *         * FSP_ERR_CRYPTO_SCE_FAIL Internal I/O buffer is not empty.
+ *         * FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed.
+ *
+ * @note The pre-run state is SCE Enabled State.
+ *       After the function runs the state transitions to SCE Enabled State.
+ **********************************************************************************************************************/
+fsp_err_t R_SCE_ECC_brainpoolP256r1_InitialPublicKeyWrap (const uint8_t * const                key_type,
+                                                          const uint8_t * const                wrapped_user_factory_programming_key,
+                                                          const uint8_t * const                initial_vector,
+                                                          const uint8_t * const                encrypted_key,
+                                                          sce_ecc_public_wrapped_key_t * const wrapped_key)
+{
+    fsp_err_t error_code = FSP_SUCCESS;
+
+#if (SCE9)
+    uint32_t indata_keytype         = 0;
+    uint32_t indata_cmd             = 0;
+    uint32_t install_key_ring_index = R_SCE_INSTALL_KEY_RING_INDEX;
+
+    indata_cmd = SCE_OEM_CMD_ECC_P256R1_PUBLIC;
+
+    indata_keytype = change_endian_long((uint32_t) (*key_type));
+
+    if (0 == *key_type)
+    {
+        INST_DATA_SIZE = sce_oem_key_size[indata_cmd];
+    }
+    else
+    {
+        INST_DATA_SIZE = sce_oem_key_size[indata_cmd] - 4;
+    }
+
+    error_code = HW_SCE_GenerateOemKeyIndexSub(&indata_keytype,
+                                               &indata_cmd,
+                                               &install_key_ring_index,
+                                               (uint32_t *) wrapped_user_factory_programming_key,
+                                               (uint32_t *) initial_vector,
+                                               (uint32_t *) encrypted_key,
+                                               (uint32_t *) &wrapped_key->value);
+#else
+    error_code = FSP_ERR_UNSUPPORTED;
+
+    FSP_PARAMETER_NOT_USED(key_type);
+    FSP_PARAMETER_NOT_USED(wrapped_user_factory_programming_key);
+    FSP_PARAMETER_NOT_USED(initial_vector);
+    FSP_PARAMETER_NOT_USED(encrypted_key);
+    FSP_PARAMETER_NOT_USED(wrapped_key);
+#endif
+
+    if (FSP_SUCCESS == error_code)
+    {
+        wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P256_PUBLIC;
+    }
+    else
+    {
+        wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID;
+    }
+
+    return error_code;
+}
+
+/*******************************************************************************************************************//**
+ * This API generates 256-bit Brainpool ECC key within the user routine.
+ *
+ * @param[in]     key_type                              Selection key type when generating wrapped key
+ *                                                      (0: for encrypted key, 1: for plain key)
+ * @param[in]     wrapped_user_factory_programming_key  Wrapped user factory programming key by the Renesas Key Wrap Service.
+ *                                                      When key_type is 1 as plain key, this is not required and
+ *                                                      any value can be specified.
+ * @param[in]     initial_vector                        Initialization vector when generating encrypted_key.
+ *                                                      When key_type is 1 as plain key, this is not required and
+ *                                                      any value can be specified.
+ * @param[in]     encrypted_key                         Encrypted user key and MAC appended
+ * @param[in,out] wrapped_key                           256-bit ECC wrapped key
+ *
+ * @retval FSP_SUCCESS                          Normal termination.
+ * @retval FSP_ERR_UNSUPPORTED                  API not supported.
+ * @return If an error occurs, the return value will be as follows.
+ *         * FSP_ERR_CRYPTO_SCE_FAIL Internal I/O buffer is not empty.
+ *         * FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed.
+ *
+ * @note The pre-run state is SCE Enabled State.
+ *       After the function runs the state transitions to SCE Enabled State.
+ **********************************************************************************************************************/
+fsp_err_t R_SCE_ECC_brainpoolP256r1_InitialPrivateKeyWrap (const uint8_t * const                 key_type,
+                                                           const uint8_t * const                 wrapped_user_factory_programming_key,
+                                                           const uint8_t * const                 initial_vector,
+                                                           const uint8_t * const                 encrypted_key,
+                                                           sce_ecc_private_wrapped_key_t * const wrapped_key)
+{
+    fsp_err_t error_code = FSP_SUCCESS;
+
+#if (SCE9)
+    uint32_t indata_keytype         = 0;
+    uint32_t indata_cmd             = 0;
+    uint32_t install_key_ring_index = R_SCE_INSTALL_KEY_RING_INDEX;
+
+    indata_cmd     = SCE_OEM_CMD_ECC_P256R1_PRIVATE;
+    indata_keytype = change_endian_long((uint32_t) (*key_type));
+
+    if (0 == *key_type)
+    {
+        INST_DATA_SIZE = sce_oem_key_size[indata_cmd];
+    }
+    else
+    {
+        INST_DATA_SIZE = sce_oem_key_size[indata_cmd] - 4;
+    }
+
+    error_code = HW_SCE_GenerateOemKeyIndexSub(&indata_keytype,
+                                               &indata_cmd,
+                                               &install_key_ring_index,
+                                               (uint32_t *) wrapped_user_factory_programming_key,
+                                               (uint32_t *) initial_vector,
+                                               (uint32_t *) encrypted_key,
+                                               (uint32_t *) &wrapped_key->value);
+#else
+    error_code = FSP_ERR_UNSUPPORTED;
+
+    FSP_PARAMETER_NOT_USED(key_type);
+    FSP_PARAMETER_NOT_USED(wrapped_user_factory_programming_key);
+    FSP_PARAMETER_NOT_USED(initial_vector);
+    FSP_PARAMETER_NOT_USED(encrypted_key);
+    FSP_PARAMETER_NOT_USED(wrapped_key);
+#endif
+
+    if (FSP_SUCCESS == error_code)
+    {
+        wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P256_PRIVATE;
+    }
+    else
+    {
+        wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID;
+    }
+
+    return error_code;
+}
+
+/*******************************************************************************************************************//**
+ * This API generates 384-bit Brainpool ECC key within the user routine.
+ *
+ * @param[in]     key_type                              Selection key type when generating wrapped key
+ *                                                      (0: for encrypted key, 1: for plain key)
+ * @param[in]     wrapped_user_factory_programming_key  Wrapped user factory programming key by the Renesas Key Wrap Service.
+ *                                                      When key_type is 1 as plain key, this is not required and
+ *                                                      any value can be specified.
+ * @param[in]     initial_vector                        Initialization vector when generating encrypted_key.
+ *                                                      When key_type is 1 as plain key, this is not required and
+ *                                                      any value can be specified.
+ * @param[in]     encrypted_key                         Encrypted user key and MAC appended
+ * @param[in,out] wrapped_key                           364-bit ECC wrapped key
+ *
+ * @retval FSP_SUCCESS                          Normal termination.
+ * @retval FSP_ERR_UNSUPPORTED                  API not supported.
+ * @return If an error occurs, the return value will be as follows.
+ *         * FSP_ERR_CRYPTO_SCE_FAIL Internal I/O buffer is not empty.
+ *         * FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed.
+ *
+ * @note The pre-run state is SCE Enabled State.
+ *       After the function runs the state transitions to SCE Enabled State.
+ **********************************************************************************************************************/
+fsp_err_t R_SCE_ECC_brainpoolP384r1_InitialPublicKeyWrap (const uint8_t * const                key_type,
+                                                          const uint8_t * const                wrapped_user_factory_programming_key,
+                                                          const uint8_t * const                initial_vector,
+                                                          const uint8_t * const                encrypted_key,
+                                                          sce_ecc_public_wrapped_key_t * const wrapped_key)
+{
+    fsp_err_t error_code = FSP_SUCCESS;
+
+#if (SCE9)
+    uint32_t indata_keytype         = 0;
+    uint32_t indata_cmd             = 0;
+    uint32_t install_key_ring_index = R_SCE_INSTALL_KEY_RING_INDEX;
+
+    indata_cmd = SCE_OEM_CMD_ECC_P384R1_PUBLIC;
+
+    indata_keytype = change_endian_long((uint32_t) (*key_type));
+
+    if (0 == *key_type)
+    {
+        INST_DATA_SIZE = sce_oem_key_size[indata_cmd];
+    }
+    else
+    {
+        INST_DATA_SIZE = sce_oem_key_size[indata_cmd] - 4;
+    }
+
+    error_code = HW_SCE_GenerateOemKeyIndexSub(&indata_keytype,
+                                               &indata_cmd,
+                                               &install_key_ring_index,
+                                               (uint32_t *) wrapped_user_factory_programming_key,
+                                               (uint32_t *) initial_vector,
+                                               (uint32_t *) encrypted_key,
+                                               (uint32_t *) &wrapped_key->value);
+#else
+    error_code = FSP_ERR_UNSUPPORTED;
+
+    FSP_PARAMETER_NOT_USED(key_type);
+    FSP_PARAMETER_NOT_USED(wrapped_user_factory_programming_key);
+    FSP_PARAMETER_NOT_USED(initial_vector);
+    FSP_PARAMETER_NOT_USED(encrypted_key);
+    FSP_PARAMETER_NOT_USED(wrapped_key);
+#endif
+
+    if (FSP_SUCCESS == error_code)
+    {
+        wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P384_PUBLIC;
+    }
+    else
+    {
+        wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID;
+    }
+
+    return error_code;
+}
+
+/*******************************************************************************************************************//**
+ * This API generates 384-bit Brainpool ECC key within the user routine.
+ *
+ * @param[in]     key_type                              Selection key type when generating wrapped key
+ *                                                      (0: for encrypted key, 1: for plain key)
+ * @param[in]     wrapped_user_factory_programming_key  Wrapped user factory programming key by the Renesas Key Wrap Service.
+ *                                                      When key_type is 1 as plain key, this is not required and
+ *                                                      any value can be specified.
+ * @param[in]     initial_vector                        Initialization vector when generating encrypted_key.
+ *                                                      When key_type is 1 as plain key, this is not required and
+ *                                                      any value can be specified.
+ * @param[in]     encrypted_key                         Encrypted user key and MAC appended
+ * @param[in,out] wrapped_key                           384-bit ECC wrapped key
+ *
+ * @retval FSP_SUCCESS                          Normal termination.
+ * @retval FSP_ERR_UNSUPPORTED                  API not supported.
+ * @return If an error occurs, the return value will be as follows.
+ *         * FSP_ERR_CRYPTO_SCE_FAIL Internal I/O buffer is not empty.
+ *         * FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed.
+ *
+ * @note The pre-run state is SCE Enabled State.
+ *       After the function runs the state transitions to SCE Enabled State.
+ **********************************************************************************************************************/
+fsp_err_t R_SCE_ECC_brainpoolP384r1_InitialPrivateKeyWrap (const uint8_t * const                 key_type,
+                                                           const uint8_t * const                 wrapped_user_factory_programming_key,
+                                                           const uint8_t * const                 initial_vector,
+                                                           const uint8_t * const                 encrypted_key,
+                                                           sce_ecc_private_wrapped_key_t * const wrapped_key)
+{
+    fsp_err_t error_code = FSP_SUCCESS;
+
+#if (SCE9)
+    uint32_t indata_keytype         = 0;
+    uint32_t indata_cmd             = 0;
+    uint32_t install_key_ring_index = R_SCE_INSTALL_KEY_RING_INDEX;
+
+    indata_cmd     = SCE_OEM_CMD_ECC_P384R1_PRIVATE;
+    indata_keytype = change_endian_long((uint32_t) (*key_type));
+
+    if (0 == *key_type)
+    {
+        INST_DATA_SIZE = sce_oem_key_size[indata_cmd];
+    }
+    else
+    {
+        INST_DATA_SIZE = sce_oem_key_size[indata_cmd] - 4;
+    }
+
+    error_code = HW_SCE_GenerateOemKeyIndexSub(&indata_keytype,
+                                               &indata_cmd,
+                                               &install_key_ring_index,
+                                               (uint32_t *) wrapped_user_factory_programming_key,
+                                               (uint32_t *) initial_vector,
+                                               (uint32_t *) encrypted_key,
+                                               (uint32_t *) &wrapped_key->value);
+#else
+    error_code = FSP_ERR_UNSUPPORTED;
+
+    FSP_PARAMETER_NOT_USED(key_type);
+    FSP_PARAMETER_NOT_USED(wrapped_user_factory_programming_key);
+    FSP_PARAMETER_NOT_USED(initial_vector);
+    FSP_PARAMETER_NOT_USED(encrypted_key);
+    FSP_PARAMETER_NOT_USED(wrapped_key);
+#endif
+
+    if (FSP_SUCCESS == error_code)
+    {
+        wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P384_PRIVATE;
+    }
+    else
+    {
+        wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID;
+    }
+
+    return error_code;
+}
+
 /*******************************************************************************************************************//**
  * @} (end addtogroup SCE_KEY_INJECTION)
  **********************************************************************************************************************/
diff --git a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/api/r_sce_api.h b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/api/r_sce_api.h
index 1dcc4ed1f..36429bda7 100644
--- a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/api/r_sce_api.h
+++ b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/api/r_sce_api.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/instances/r_sce.h b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/instances/r_sce.h
index 2573996dc..41c3b410b 100644
--- a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/instances/r_sce.h
+++ b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/instances/r_sce.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/SCE_module.h b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/SCE_module.h
index 26bb94bec..64e75a67d 100644
--- a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/SCE_module.h
+++ b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/SCE_module.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/r_sce_private.h b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/r_sce_private.h
index ba254bc09..0752bffde 100644
--- a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/r_sce_private.h
+++ b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/r_sce_private.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/r_sce_private.c b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/r_sce_private.c
index 209524558..6e0a0533b 100644
--- a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/r_sce_private.c
+++ b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/r_sce_private.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce.c b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce.c
index 973b5ff8f..c655f1626 100644
--- a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce.c
+++ b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_aes.c b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_aes.c
index c30c0c811..1009c15ff 100644
--- a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_aes.c
+++ b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_aes.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_ecc.c b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_ecc.c
index 9a58159d5..9ac4c0255 100644
--- a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_ecc.c
+++ b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_ecc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_rsa.c b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_rsa.c
index 91596204b..0f011eb73 100644
--- a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_rsa.c
+++ b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_rsa.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_sha.c b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_sha.c
index a0ee739ef..0dd39c3ba 100644
--- a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_sha.c
+++ b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_sha.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_tls.c b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_tls.c
index b9fa06223..cb8e62adb 100644
--- a/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_tls.c
+++ b/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_tls.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sci_b_i2c/r_sci_b_i2c.c b/ra/fsp/src/r_sci_b_i2c/r_sci_b_i2c.c
index 404db210b..5ac3f74fa 100644
--- a/ra/fsp/src/r_sci_b_i2c/r_sci_b_i2c.c
+++ b/ra/fsp/src/r_sci_b_i2c/r_sci_b_i2c.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -668,6 +668,7 @@ static void sci_b_i2c_abort_seq_master (sci_b_i2c_instance_ctrl_t * const p_ctrl
     /* Update the transfer descriptor to show no longer in-progress and an error */
     p_ctrl->remain    = 0U;
     p_ctrl->restarted = false;
+    p_ctrl->restart   = false;
 
     /* Update the transfer descriptor to make sure interrupts no longer process */
     p_ctrl->addr_loaded = p_ctrl->addr_total;
@@ -1080,7 +1081,6 @@ static fsp_err_t sci_b_i2c_transfer_configure (sci_b_i2c_instance_ctrl_t       *
                                                sci_b_i2c_dtc_interrupt_trigger_t trigger)
 {
     fsp_err_t err;
-    IRQn_Type irq;
 
     /* Set default transfer info and open receive transfer module, if enabled. */
  #if (SCI_B_I2C_CFG_PARAM_CHECKING_ENABLE)
@@ -1092,25 +1092,18 @@ static fsp_err_t sci_b_i2c_transfer_configure (sci_b_i2c_instance_ctrl_t       *
     transfer_info_t * p_cfg = p_transfer->p_cfg->p_info;
     if (SCI_B_I2C_DTC_INTERRUPT_TRIGGER_RXI == trigger)
     {
-        irq = p_ctrl->p_cfg->rxi_irq;
         p_cfg->transfer_settings_word = SCI_B_I2C_PRV_DTC_RX_FOR_READ_TRANSFER_SETTINGS;
         p_cfg->p_src = (void *) (&(p_ctrl->p_reg->RDR));
     }
     else
     {
         /* In case of read operation using DTC, the TXI interrupt will trigger the DTC to write 0xFF into TDR (See Figure 26.94 in the RA6T2 manual R01UH0951EJ0100). */
-        irq = p_ctrl->p_cfg->txi_irq;
-
         /* In case of Write operation this will be reconfigured */
         p_cfg->transfer_settings_word = SCI_B_I2C_PRV_DTC_TX_FOR_READ_TRANSFER_SETTINGS;
         p_cfg->p_dest                 = (void *) (&(p_ctrl->p_reg->TDR));
     }
 
-    transfer_cfg_t       cfg = *(p_transfer->p_cfg);
-    dtc_extended_cfg_t * p_dtc_extended_configuration = (dtc_extended_cfg_t *) (cfg.p_extend);
-    p_dtc_extended_configuration->activation_source = irq;
-
-    err = p_transfer->p_api->open(p_transfer->p_ctrl, &cfg);
+    err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg);
     FSP_ERROR_RETURN((FSP_SUCCESS == err), err);
 
     return FSP_SUCCESS;
diff --git a/ra/fsp/src/r_sci_b_spi/r_sci_b_spi.c b/ra/fsp/src/r_sci_b_spi/r_sci_b_spi.c
index ba7a48a8c..b5c101000 100644
--- a/ra/fsp/src/r_sci_b_spi/r_sci_b_spi.c
+++ b/ra/fsp/src/r_sci_b_spi/r_sci_b_spi.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c b/ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c
index 4db5bdfd9..9e646d96f 100644
--- a/ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c
+++ b/ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -72,7 +72,6 @@
 #define SCI_B_UART_CCR3_CKE_MASK               (0x03000000U)
 
 /* SCI Data register bit masks */
-#define SCI_B_UART_RDR_RDAT_MASK_8BITS         (0x000000FFU)
 #define SCI_B_UART_TDR_TDAT_MASK_9BITS         (0x000091FFU)
 
 /* SCI CSR register receiver error (overflow, framing, parity) bits masks */
@@ -1522,8 +1521,8 @@ void sci_b_uart_txi_isr (void)
                 }
                 else
                 {
-                    /* Write 1byte (uint8_t) data to (uint8_t) data register */
-                    p_ctrl->p_reg->TDR = (uint32_t) (*(p_ctrl->p_tx_src));
+                    /* Write 1byte data to TDR_BY register */
+                    p_ctrl->p_reg->TDR_BY = (*(p_ctrl->p_tx_src));
                 }
 
                 p_ctrl->tx_src_bytes -= p_ctrl->data_bytes;
@@ -1543,8 +1542,8 @@ void sci_b_uart_txi_isr (void)
             }
             else
             {
-                /* Write 1byte (uint8_t) data to (uint8_t) data register */
-                p_ctrl->p_reg->TDR = (uint32_t) (*(p_ctrl->p_tx_src));
+                /* Write 1byte data to TDR_BY register */
+                p_ctrl->p_reg->TDR_BY = (*(p_ctrl->p_tx_src));
             }
 
             p_ctrl->tx_src_bytes -= p_ctrl->data_bytes;
@@ -1625,7 +1624,14 @@ void sci_b_uart_rxi_isr (void)
             {
                 if (p_ctrl->p_reg->FRSR_b.R > 0U)
                 {
-                    data = p_ctrl->p_reg->RDR & R_SCI_B0_RDR_RDAT_Msk;
+                    if (2U == p_ctrl->data_bytes)
+                    {
+                        data = p_ctrl->p_reg->RDR & R_SCI_B0_RDR_RDAT_Msk;
+                    }
+                    else
+                    {
+                        data = p_ctrl->p_reg->RDR_BY;
+                    }
                 }
                 else
                 {
@@ -1642,7 +1648,7 @@ void sci_b_uart_rxi_isr (void)
             }
             else
             {
-                data = p_ctrl->p_reg->RDR & SCI_B_UART_RDR_RDAT_MASK_8BITS;
+                data = p_ctrl->p_reg->RDR_BY;
             }
 
             if (0 == p_ctrl->rx_dest_bytes)
@@ -1773,7 +1779,7 @@ void sci_b_uart_eri_isr (void)
     }
     else
     {
-        data = p_ctrl->p_reg->RDR & SCI_B_UART_RDR_RDAT_MASK_8BITS;
+        data = p_ctrl->p_reg->RDR_BY;
     }
 
     /* Determine cause of error. */
diff --git a/ra/fsp/src/r_sci_i2c/r_sci_i2c.c b/ra/fsp/src/r_sci_i2c/r_sci_i2c.c
index 28fbfec40..977bf3e6d 100644
--- a/ra/fsp/src/r_sci_i2c/r_sci_i2c.c
+++ b/ra/fsp/src/r_sci_i2c/r_sci_i2c.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -684,6 +684,7 @@ static void sci_i2c_abort_seq_master (sci_i2c_instance_ctrl_t * const p_ctrl)
     /* Update the transfer descriptor to show no longer in-progress and an error */
     p_ctrl->remain    = 0U;
     p_ctrl->restarted = false;
+    p_ctrl->restart   = false;
 
     /* Update the transfer descriptor to make sure interrupts no longer process */
     p_ctrl->addr_loaded = p_ctrl->addr_total;
@@ -1060,7 +1061,6 @@ static fsp_err_t sci_i2c_transfer_configure (sci_i2c_instance_ctrl_t       * p_c
                                              sci_i2c_dtc_interrupt_trigger_t trigger)
 {
     fsp_err_t err;
-    IRQn_Type irq;
 
     /* Set default transfer info and open receive transfer module, if enabled. */
  #if (SCI_I2C_CFG_PARAM_CHECKING_ENABLE)
@@ -1072,7 +1072,6 @@ static fsp_err_t sci_i2c_transfer_configure (sci_i2c_instance_ctrl_t       * p_c
     transfer_info_t * p_cfg = p_transfer->p_cfg->p_info;
     if (SCI_I2C_DTC_INTERRUPT_TRIGGER_RXI == trigger)
     {
-        irq = p_ctrl->p_cfg->rxi_irq;
         p_cfg->transfer_settings_word = SCI_I2C_PRV_DTC_RX_FOR_READ_TRANSFER_SETTINGS;
         p_cfg->p_src = (void *) (&(p_ctrl->p_reg->RDR));
     }
@@ -1083,18 +1082,13 @@ static fsp_err_t sci_i2c_transfer_configure (sci_i2c_instance_ctrl_t       * p_c
         /* Refer flow diagram of master reception as described in hardware manual (see Figure 34.68
          * 'Example flow of master reception in simple IIC mode with transmission interrupts and reception interrupts'
          *  of the RA6M3 manual R01UH0886EJ0100). */
-        irq = p_ctrl->p_cfg->txi_irq;
 
         /* In case of Write operation this will be reconfigured */
         p_cfg->transfer_settings_word = SCI_I2C_PRV_DTC_TX_FOR_READ_TRANSFER_SETTINGS;
         p_cfg->p_dest                 = (void *) (&(p_ctrl->p_reg->TDR));
     }
 
-    transfer_cfg_t       cfg = *(p_transfer->p_cfg);
-    dtc_extended_cfg_t * p_dtc_extended_configuration = (dtc_extended_cfg_t *) (cfg.p_extend);
-    p_dtc_extended_configuration->activation_source = irq;
-
-    err = p_transfer->p_api->open(p_transfer->p_ctrl, &cfg);
+    err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg);
     FSP_ERROR_RETURN((FSP_SUCCESS == err), err);
 
     return FSP_SUCCESS;
diff --git a/ra/fsp/src/r_sci_spi/r_sci_spi.c b/ra/fsp/src/r_sci_spi/r_sci_spi.c
index 9421070f1..8f6332c49 100644
--- a/ra/fsp/src/r_sci_spi/r_sci_spi.c
+++ b/ra/fsp/src/r_sci_spi/r_sci_spi.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sci_uart/r_sci_uart.c b/ra/fsp/src/r_sci_uart/r_sci_uart.c
index 5aeab7b90..5c8e55154 100644
--- a/ra/fsp/src/r_sci_uart/r_sci_uart.c
+++ b/ra/fsp/src/r_sci_uart/r_sci_uart.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sdadc/r_sdadc.c b/ra/fsp/src/r_sdadc/r_sdadc.c
index 9c5058b69..9a617ea95 100644
--- a/ra/fsp/src/r_sdadc/r_sdadc.c
+++ b/ra/fsp/src/r_sdadc/r_sdadc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_sdhi/r_sdhi.c b/ra/fsp/src/r_sdhi/r_sdhi.c
index 509734c8d..a27c16115 100644
--- a/ra/fsp/src/r_sdhi/r_sdhi.c
+++ b/ra/fsp/src/r_sdhi/r_sdhi.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -435,7 +435,8 @@ fsp_err_t R_SDHI_Open (sdmmc_ctrl_t * const p_api_ctrl, sdmmc_cfg_t const * cons
  *                                       be 512 bytes for SD cards and eMMC devices.  It is configurable for SDIO only.
  * @retval     FSP_ERR_NOT_OPEN          Driver has not been initialized.
  * @retval     FSP_ERR_CARD_INIT_FAILED  Device was not identified as an SD card, eMMC device, or SDIO card.
- * @retval     FSP_ERR_RESPONSE          Device did not respond or responded with an error.
+ * @retval     FSP_ERR_RESPONSE          Device responded with an error.
+ * @retval     FSP_ERR_TIMEOUT           Device did not respond.
  * @retval     FSP_ERR_DEVICE_BUSY       Device is holding DAT0 low (device is busy) or another operation is ongoing.
  **********************************************************************************************************************/
 fsp_err_t R_SDHI_MediaInit (sdmmc_ctrl_t * const p_api_ctrl, sdmmc_device_t * const p_device)
@@ -612,7 +613,8 @@ fsp_err_t R_SDHI_Write (sdmmc_ctrl_t * const  p_api_ctrl,
  * @retval     FSP_ERR_NOT_OPEN              Driver has not been initialized.
  * @retval     FSP_ERR_CARD_NOT_INITIALIZED  Card was unplugged.
  * @retval     FSP_ERR_UNSUPPORTED           SDIO support disabled in SDHI_CFG_SDIO_SUPPORT_ENABLE.
- * @retval     FSP_ERR_RESPONSE              Device did not respond or responded with an error.
+ * @retval     FSP_ERR_RESPONSE              Device responded with an error.
+ * @retval     FSP_ERR_TIMEOUT               Device did not respond.
  * @retval     FSP_ERR_DEVICE_BUSY           Device is holding DAT0 low (device is busy) or another operation is
  *                                           ongoing.
  **********************************************************************************************************************/
@@ -661,7 +663,8 @@ fsp_err_t R_SDHI_ReadIo (sdmmc_ctrl_t * const p_api_ctrl,
  * @retval     FSP_ERR_CARD_NOT_INITIALIZED  Card was unplugged.
  * @retval     FSP_ERR_WRITE_FAILED          Write operation failed.
  * @retval     FSP_ERR_UNSUPPORTED           SDIO support disabled in SDHI_CFG_SDIO_SUPPORT_ENABLE.
- * @retval     FSP_ERR_RESPONSE              Device did not respond or responded with an error.
+ * @retval     FSP_ERR_RESPONSE              Device responded with an error.
+ * @retval     FSP_ERR_TIMEOUT               Device did not respond.
  * @retval     FSP_ERR_DEVICE_BUSY           Device is holding DAT0 low (device is busy) or another operation is
  *                                           ongoing.
  **********************************************************************************************************************/
@@ -971,7 +974,8 @@ fsp_err_t R_SDHI_StatusGet (sdmmc_ctrl_t * const p_api_ctrl, sdmmc_status_t * co
  * @retval     FSP_ERR_NOT_OPEN              Driver has not been initialized.
  * @retval     FSP_ERR_CARD_NOT_INITIALIZED  Card was unplugged.
  * @retval     FSP_ERR_CARD_WRITE_PROTECTED  SD card is Write Protected.
- * @retval     FSP_ERR_RESPONSE              Device did not respond or responded with an error.
+ * @retval     FSP_ERR_RESPONSE              Device responded with an error.
+ * @retval     FSP_ERR_TIMEOUT               Device did not respond.
  * @retval     FSP_ERR_DEVICE_BUSY           Device is holding DAT0 low (device is busy) or another operation is
  *                                           ongoing.
  **********************************************************************************************************************/
@@ -1198,6 +1202,9 @@ static fsp_err_t r_sdhi_erase_error_check (sdhi_instance_ctrl_t * const p_ctrl,
                                            uint32_t const               start_sector,
                                            uint32_t const               sector_count)
 {
+    fsp_err_t err = r_sdhi_common_error_check(p_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
 #if SDHI_CFG_PARAM_CHECKING_ENABLE
 
     /* Check for valid sector count.  Must be a non-zero multiple of erase_sector_count. */
@@ -1212,9 +1219,6 @@ static fsp_err_t r_sdhi_erase_error_check (sdhi_instance_ctrl_t * const p_ctrl,
     FSP_PARAMETER_NOT_USED(sector_count);
 #endif
 
-    fsp_err_t err = r_sdhi_common_error_check(p_ctrl);
-    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
-
     /* Check for write protection */
     FSP_ERROR_RETURN(!p_ctrl->device.write_protected, FSP_ERR_CARD_WRITE_PROTECTED);
 
@@ -1423,7 +1427,8 @@ static void r_sdhi_command_send_no_wait (sdhi_instance_ctrl_t * p_ctrl, uint32_t
  * @param[in]  argument             Argument to send with the command.
  *
  * @retval     FSP_SUCCESS          Command sent and response received, no errors in response.
- * @retval     FSP_ERR_RESPONSE     Device did not respond or responded with an error.
+ * @retval     FSP_ERR_RESPONSE     Device responded with an error.
+ * @retval     FSP_ERR_TIMEOUT      Device did not respond.
  * @retval     FSP_ERR_DEVICE_BUSY  Device is holding DAT0 low (device is busy) or another operation is ongoing.
  **********************************************************************************************************************/
 static fsp_err_t r_sdhi_command_send (sdhi_instance_ctrl_t * p_ctrl, uint32_t command, uint32_t argument)
@@ -1546,7 +1551,8 @@ static fsp_err_t r_sdhi_hw_cfg (sdhi_instance_ctrl_t * const p_ctrl)
  * @retval     FSP_SUCCESS               Operation completed successfully.
  * @retval     FSP_ERR_CARD_INIT_FAILED  Device could not be identified.
  * @retval     FSP_ERR_ASSERTION         Card detection configured but not supported.
- * @retval     FSP_ERR_RESPONSE          Device did not respond or responded with an error.
+ * @retval     FSP_ERR_RESPONSE          Device responded with an error.
+ * @retval     FSP_ERR_TIMEOUT           Device did not respond.
  * @retval     FSP_ERR_DEVICE_BUSY       Device is holding DAT0 low (device is busy) or another operation is ongoing.
  **********************************************************************************************************************/
 static fsp_err_t r_sdhi_card_identify (sdhi_instance_ctrl_t * const p_ctrl)
@@ -1629,7 +1635,8 @@ static fsp_err_t r_sdhi_card_identify (sdhi_instance_ctrl_t * const p_ctrl)
  *
  * @retval     FSP_SUCCESS               Operation completed successfully.
  * @retval     FSP_ERR_CARD_INIT_FAILED  Operation failed.
- * @retval     FSP_ERR_RESPONSE          Device did not respond or responded with an error.
+ * @retval     FSP_ERR_RESPONSE     Device responded with an error.
+ * @retval     FSP_ERR_TIMEOUT      Device did not respond.
  * @retval     FSP_ERR_DEVICE_BUSY       Device is holding DAT0 low (device is busy) or another operation is ongoing.
  **********************************************************************************************************************/
 static fsp_err_t r_sdhi_bus_cfg (sdhi_instance_ctrl_t * const p_ctrl)
@@ -1754,7 +1761,8 @@ static void r_sdhi_read_write_common (sdhi_instance_ctrl_t * const p_ctrl,
  * @param[in]  command              Command (read or write)
  *
  * @retval     FSP_SUCCESS          CMD52 sent and response received with no error.
- * @retval     FSP_ERR_RESPONSE     Device did not respond or responded with an error.
+ * @retval     FSP_ERR_RESPONSE     Device responded with an error.
+ * @retval     FSP_ERR_TIMEOUT      Device did not respond.
  * @retval     FSP_ERR_DEVICE_BUSY  Device is holding DAT0 low (device is busy) or another operation is ongoing.
  **********************************************************************************************************************/
 static fsp_err_t r_sdhi_cmd52 (sdhi_instance_ctrl_t * const p_ctrl,
@@ -1794,7 +1802,8 @@ static fsp_err_t r_sdhi_cmd52 (sdhi_instance_ctrl_t * const p_ctrl,
  * @param[in]  p_ctrl               Pointer to the instance control block.
  *
  * @retval     FSP_SUCCESS          Card type is set if the device is an SDIO card.
- * @retval     FSP_ERR_RESPONSE     Device did not respond or responded with an error.
+ * @retval     FSP_ERR_RESPONSE     Device responded with an error.
+ * @retval     FSP_ERR_TIMEOUT      Device did not respond.
  * @retval     FSP_ERR_DEVICE_BUSY  Device is holding DAT0 low (device is busy) or another operation is ongoing.
  **********************************************************************************************************************/
 static fsp_err_t r_sdhi_sdio_check (sdhi_instance_ctrl_t * const p_ctrl)
@@ -1851,7 +1860,8 @@ static fsp_err_t r_sdhi_sdio_check (sdhi_instance_ctrl_t * const p_ctrl)
  * @param[in]  p_ctrl               Pointer to the instance control block.
  *
  * @retval     FSP_SUCCESS          Card type is set if the device is an SD card.
- * @retval     FSP_ERR_RESPONSE     Device did not respond or responded with an error.
+ * @retval     FSP_ERR_RESPONSE     Device responded with an error.
+ * @retval     FSP_ERR_TIMEOUT      Device did not respond.
  * @retval     FSP_ERR_DEVICE_BUSY  Device is holding DAT0 low (device is busy) or another operation is ongoing.
  **********************************************************************************************************************/
 static fsp_err_t r_sdhi_sd_card_check (sdhi_instance_ctrl_t * const p_ctrl)
@@ -1860,13 +1870,18 @@ static fsp_err_t r_sdhi_sd_card_check (sdhi_instance_ctrl_t * const p_ctrl)
      * in the SD Physical Layer Specification Version 6.00. */
     uint32_t  argument = ((SDHI_PRV_IF_COND_VOLTAGE << 8) | SDHI_PRV_IF_COND_CHECK_PATTERN);
     fsp_err_t err      = r_sdhi_command_send(p_ctrl, SDHI_PRV_CMD_IF_COND, argument);
-    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+    if (FSP_ERR_TIMEOUT == err)
+    {
+        FSP_RETURN(err);
+    }
 
     /* An SD card responds to CMD8 by echoing the argument in the R7 response. An eMMC device responds to CMD8 with the
      * extended CSD. If the response does not match the argument, return to check if this is an eMMC device. */
     sdmmc_response_t response;
     response.status = p_ctrl->p_reg->SD_RSP10;
-    if (response.status == argument)
+
+    /* CMD8 is not supported by spec V1.X so we have to try CMD41. */
+    if ((FSP_ERR_RESPONSE == err) || (response.status == argument))
     {
         /* Try to send ACMD41 for up to 1 second as long as the card is responding and initialization is not complete.
          * Returns immediately if the card fails to respond to ACMD41. */
@@ -1916,7 +1931,8 @@ static fsp_err_t r_sdhi_sd_card_check (sdhi_instance_ctrl_t * const p_ctrl)
  * @param[in]  p_ctrl               Pointer to the instance control block.
  *
  * @retval     FSP_SUCCESS          Card type is set if the device is an eMMC card.
- * @retval     FSP_ERR_RESPONSE     Device did not respond or responded with an error.
+ * @retval     FSP_ERR_RESPONSE     Device responded with an error.
+ * @retval     FSP_ERR_TIMEOUT      Device did not respond.
  * @retval     FSP_ERR_DEVICE_BUSY  Device is holding DAT0 low (device is busy) or another operation is ongoing.
  **********************************************************************************************************************/
 static fsp_err_t r_sdhi_emmc_check (sdhi_instance_ctrl_t * const p_ctrl)
@@ -2012,7 +2028,8 @@ static fsp_err_t r_sdhi_wait_for_device (sdhi_instance_ctrl_t * const p_ctrl)
  * @param[in]  p_csd_reg                 Pointer to card specific data.
  *
  * @retval     FSP_SUCCESS               Clock rate adjusted to the maximum speed allowed by both device and MCU.
- * @retval     FSP_ERR_RESPONSE          Device did not respond or responded with an error.
+ * @retval     FSP_ERR_RESPONSE          Device responded with an error.
+ * @retval     FSP_ERR_TIMEOUT           Device did not respond.
  * @retval     FSP_ERR_CARD_INIT_FAILED  Timeout setting divider or operation is still too fast at maximum divider
  *                                       (unlikely).
  * @retval     FSP_ERR_DEVICE_BUSY       Device is holding DAT0 low (device is busy) or another operation is ongoing.
@@ -2082,7 +2099,8 @@ static fsp_err_t r_sdhi_clock_optimize (sdhi_instance_ctrl_t * const p_ctrl,
  * @param[in]  p_ctrl                    Pointer to the instance control block.
  *
  * @retval     FSP_SUCCESS               Clock settings applied for SDIO.
- * @retval     FSP_ERR_RESPONSE          Device did not respond or responded with an error.
+ * @retval     FSP_ERR_RESPONSE          Device responded with an error.
+ * @retval     FSP_ERR_TIMEOUT           Device did not respond.
  * @retval     FSP_ERR_DEVICE_BUSY       Device is holding DAT0 low (device is busy) or another operation is ongoing.
  * @retval     FSP_ERR_CARD_INIT_FAILED  Timeout setting divider or operation is still too fast at maximum divider
  *                                       (unlikely).
@@ -2127,7 +2145,8 @@ static fsp_err_t r_sdhi_sdio_clock_optimize (sdhi_instance_ctrl_t * const p_ctrl
  * @param[in]  timeout_us        Number of loops to check bit (at least 1 us per loop).
  *
  * @retval     FSP_SUCCESS       Requested bit (access end or response end) is set.
- * @retval     FSP_ERR_RESPONSE  Device did not respond or responded with an error.
+ * @retval     FSP_ERR_RESPONSE     Device responded with an error.
+ * @retval     FSP_ERR_TIMEOUT      Device did not respond.
  **********************************************************************************************************************/
 static fsp_err_t r_sdhi_wait_for_event (sdhi_instance_ctrl_t * const p_ctrl, uint32_t bit, uint32_t timeout_us)
 {
@@ -2155,7 +2174,7 @@ static fsp_err_t r_sdhi_wait_for_event (sdhi_instance_ctrl_t * const p_ctrl, uin
         timeout_us--;
         if (0U == timeout_us)
         {
-            FSP_RETURN(FSP_ERR_RESPONSE);
+            FSP_RETURN(FSP_ERR_TIMEOUT);
         }
 
         /* Wait 1 us for consistent loop timing. */
@@ -2171,7 +2190,8 @@ static fsp_err_t r_sdhi_wait_for_event (sdhi_instance_ctrl_t * const p_ctrl, uin
  * @param[in]  p_ctrl               Pointer to the instance control block.
  *
  * @retval     FSP_SUCCESS          SD clock set to the maximum supported by both host and device.
- * @retval     FSP_ERR_RESPONSE     Device did not respond or responded with an error.
+ * @retval     FSP_ERR_RESPONSE     Device responded with an error.
+ * @retval     FSP_ERR_TIMEOUT      Device did not respond.
  * @retval     FSP_ERR_INTERNAL     Error in response from card during switch to high speed mode.
  **********************************************************************************************************************/
 static fsp_err_t r_sdhi_sd_high_speed (sdhi_instance_ctrl_t * const p_ctrl)
@@ -2218,7 +2238,8 @@ static fsp_err_t r_sdhi_sd_high_speed (sdhi_instance_ctrl_t * const p_ctrl)
  * @param[out] p_csd_reg            Pointer to card specific data.
  *
  * @retval     FSP_SUCCESS          Card specific data stored in provided pointer.
- * @retval     FSP_ERR_RESPONSE     Device did not respond or responded with an error.
+ * @retval     FSP_ERR_RESPONSE     Device responded with an error.
+ * @retval     FSP_ERR_TIMEOUT      Device did not respond.
  * @retval     FSP_ERR_DEVICE_BUSY  Device is holding DAT0 low (device is busy) or another operation is ongoing.
  **********************************************************************************************************************/
 static fsp_err_t r_sdhi_csd_save (sdhi_instance_ctrl_t * const p_ctrl,
@@ -2301,7 +2322,8 @@ static fsp_err_t r_sdhi_csd_save (sdhi_instance_ctrl_t * const p_ctrl,
  *
  * @retval     FSP_SUCCESS          Device type obtained from eMMC extended CSD.  Sector count is also calculated here
  *                                  if it was not determined previously.
- * @retval     FSP_ERR_RESPONSE     Device did not respond or responded with an error.
+ * @retval     FSP_ERR_RESPONSE     Device responded with an error.
+ * @retval     FSP_ERR_TIMEOUT      Device did not respond.
  **********************************************************************************************************************/
 static fsp_err_t r_sdhi_csd_extended_get (sdhi_instance_ctrl_t * const p_ctrl, uint32_t rca, uint8_t * p_device_type)
 {
@@ -2335,7 +2357,8 @@ static fsp_err_t r_sdhi_csd_extended_get (sdhi_instance_ctrl_t * const p_ctrl, u
  * @param[in]  byte_count           Expected number of bytes to read.
  *
  * @retval     FSP_SUCCESS          Requested data read into internal buffer.
- * @retval     FSP_ERR_RESPONSE     Device did not respond or responded with an error.
+ * @retval     FSP_ERR_RESPONSE     Device responded with an error.
+ * @retval     FSP_ERR_TIMEOUT      Device did not respond.
  **********************************************************************************************************************/
 static fsp_err_t r_sdhi_read_and_block (sdhi_instance_ctrl_t * const p_ctrl,
                                         uint32_t                     command,
@@ -2362,7 +2385,8 @@ static fsp_err_t r_sdhi_read_and_block (sdhi_instance_ctrl_t * const p_ctrl,
  * @param[out] p_rca                Pointer to store relative card address.
  *
  * @retval     FSP_SUCCESS          Relative card address is assigned and device is in standby state.
- * @retval     FSP_ERR_RESPONSE     Device did not respond or responded with an error.
+ * @retval     FSP_ERR_RESPONSE     Device responded with an error.
+ * @retval     FSP_ERR_TIMEOUT      Device did not respond.
  * @retval     FSP_ERR_DEVICE_BUSY  Device is holding DAT0 low (device is busy) or another operation is ongoing.
  **********************************************************************************************************************/
 static fsp_err_t r_sdhi_rca_get (sdhi_instance_ctrl_t * const p_ctrl, uint32_t * p_rca)
@@ -2397,7 +2421,8 @@ static fsp_err_t r_sdhi_rca_get (sdhi_instance_ctrl_t * const p_ctrl, uint32_t *
  * @param[in]  rca                  Relative card address
  *
  * @retval     FSP_SUCCESS          Bus width updated on device.
- * @retval     FSP_ERR_RESPONSE     Device did not respond or responded with an error.
+ * @retval     FSP_ERR_RESPONSE     Device responded with an error.
+ * @retval     FSP_ERR_TIMEOUT      Device did not respond.
  * @retval     FSP_ERR_DEVICE_BUSY  Device is holding DAT0 low (device is busy) or another operation is ongoing.
  **********************************************************************************************************************/
 static fsp_err_t r_sdhi_bus_width_set (sdhi_instance_ctrl_t * const p_ctrl, uint32_t rca)
diff --git a/ra/fsp/src/r_sdhi/r_sdhi_private.h b/ra/fsp/src/r_sdhi/r_sdhi_private.h
index 61740cd16..4e7019c71 100644
--- a/ra/fsp/src/r_sdhi/r_sdhi_private.h
+++ b/ra/fsp/src/r_sdhi/r_sdhi_private.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_slcdc/r_slcdc.c b/ra/fsp/src/r_slcdc/r_slcdc.c
index 31c7c4d65..a58d1c1f3 100644
--- a/ra/fsp/src/r_slcdc/r_slcdc.c
+++ b/ra/fsp/src/r_slcdc/r_slcdc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_spi/r_spi.c b/ra/fsp/src/r_spi/r_spi.c
index 77503f99f..0a9e4997f 100644
--- a/ra/fsp/src/r_spi/r_spi.c
+++ b/ra/fsp/src/r_spi/r_spi.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_spi_b/r_spi_b.c b/ra/fsp/src/r_spi_b/r_spi_b.c
index 2e4dfd0b0..1b58e6e94 100644
--- a/ra/fsp/src/r_spi_b/r_spi_b.c
+++ b/ra/fsp/src/r_spi_b/r_spi_b.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_ssi/r_ssi.c b/ra/fsp/src/r_ssi/r_ssi.c
index 113b0c19e..70deb074b 100644
--- a/ra/fsp/src/r_ssi/r_ssi.c
+++ b/ra/fsp/src/r_ssi/r_ssi.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_ulpt/r_ulpt.c b/ra/fsp/src/r_ulpt/r_ulpt.c
new file mode 100644
index 000000000..4bb0daff4
--- /dev/null
+++ b/ra/fsp/src/r_ulpt/r_ulpt.c
@@ -0,0 +1,896 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "r_ulpt.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/** "ULPT" in ASCII, used to determine if channel is open. */
+#define ULPT_OPEN                           (0x554C5054ULL)
+
+#define ULPT_PRV_ULPTCR_STATUS_FLAGS        (0xE0U)
+#define ULPT_PRV_ULPTCMSR_VALID_BITS        (0x77U)
+
+#define ULPT_PRV_ULPTCR_START_TIMER         (0xE1U)
+#define ULPT_PRV_ULPTCR_STOP_TIMER          (0xE0U)
+#define ULPT_PRV_ULPTCR_FORCE_STOP_TIMER    (0xE4U)
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+typedef void (BSP_CMSE_NONSECURE_CALL * ulpt_prv_ns_callback)(timer_callback_args_t * p_args);
+#elif defined(__GNUC__)
+typedef BSP_CMSE_NONSECURE_CALL void (*volatile ulpt_prv_ns_callback)(timer_callback_args_t * p_args);
+#endif
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+static fsp_err_t r_ulpt_common_preamble(ulpt_instance_ctrl_t * p_instance_ctrl);
+
+static void r_ulpt_hardware_cfg(ulpt_instance_ctrl_t * p_instance_ctrl, timer_cfg_t const * const p_cfg);
+
+static void r_ulpt_period_register_set(ulpt_instance_ctrl_t * p_instance_ctrl, uint32_t period_counts);
+static uint32_t r_ulpt_clock_frequency_get (R_ULPT0_Type * p_ulpt_regs);
+
+#if ULPT_CFG_PARAM_CHECKING_ENABLE
+static fsp_err_t r_ulpt_open_param_checking(ulpt_instance_ctrl_t * p_instance_ctrl, timer_cfg_t const * const p_cfg);
+
+#endif
+
+/* ISRs. */
+void ulpt_int_isr(void);
+
+/***********************************************************************************************************************
+ * Private global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Global Variables
+ **********************************************************************************************************************/
+
+/** ULPT implementation of General Timer Driver. */
+const timer_api_t g_timer_on_ulpt =
+{
+    .open         = R_ULPT_Open,
+    .stop         = R_ULPT_Stop,
+    .start        = R_ULPT_Start,
+    .reset        = R_ULPT_Reset,
+    .enable       = R_ULPT_Enable,
+    .disable      = R_ULPT_Disable,
+    .periodSet    = R_ULPT_PeriodSet,
+    .dutyCycleSet = R_ULPT_DutyCycleSet,
+    .infoGet      = R_ULPT_InfoGet,
+    .statusGet    = R_ULPT_StatusGet,
+    .callbackSet  = R_ULPT_CallbackSet,
+    .close        = R_ULPT_Close,
+};
+
+/*******************************************************************************************************************//**
+ * @addtogroup ULPT
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Initializes the ULPT module instance. Implements @ref timer_api_t::open.
+ *
+ * The ULPT implementation of the general timer can accept an optional ulpt_extended_cfg_t extension parameter.  For
+ * ULPT, the extension specifies the clock to be used as timer source and the output pin configurations.  If the
+ * extension parameter is not specified (NULL), the default clock LOCO is used and the output pins are disabled.
+ *
+ * Example:
+ * @snippet r_ulpt_example.c R_ULPT_Open
+ *
+ * @retval FSP_SUCCESS                 Initialization was successful and timer has started.
+ * @retval FSP_ERR_ASSERTION           A required input pointer is NULL or the period is not in the valid range of
+ *                                     1 to 0xFFFF.
+ * @retval FSP_ERR_ALREADY_OPEN        R_ULPT_Open has already been called for this p_ctrl.
+ * @retval FSP_ERR_IRQ_BSP_DISABLED    A required interrupt has not been enabled in the vector table.
+ * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT  Requested channel number is not available on ULPT.
+ **********************************************************************************************************************/
+fsp_err_t R_ULPT_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg)
+{
+    ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl;
+
+#if ULPT_CFG_PARAM_CHECKING_ENABLE
+    fsp_err_t err = r_ulpt_open_param_checking(p_instance_ctrl, p_cfg);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+#endif
+
+    uint32_t base_address =  (uint32_t) R_ULPT0_BASE + (p_cfg->channel * ((uint32_t)R_ULPT1_BASE - (uint32_t)R_ULPT0_BASE));
+    p_instance_ctrl->p_reg = (R_ULPT0_Type *) base_address;
+
+    p_instance_ctrl->p_cfg = p_cfg;
+
+    /* Power on the ULPT channel. */
+    R_BSP_MODULE_START(FSP_IP_ULPT, p_cfg->channel);
+
+    /* Clear ULPTCR. This stops the timer if it is running and clears the flags. */
+    p_instance_ctrl->p_reg->ULPTCR = 0U;
+
+    /* The timer is stopped in sync with the count source. */
+    FSP_HARDWARE_REGISTER_WAIT(0U, p_instance_ctrl->p_reg->ULPTCR_b.TCSTF);
+
+    /* Clear ULPTMR2 before ULPTMR1 to prevent clock destablization if the mode is changed. */
+    p_instance_ctrl->p_reg->ULPTMR2 = 0U;
+
+    /* Set count source and divider and configure pins. */
+    r_ulpt_hardware_cfg(p_instance_ctrl, p_cfg);
+
+    /* Set period register and update duty cycle if output mode is used. */
+    r_ulpt_period_register_set(p_instance_ctrl, p_cfg->period_counts);
+
+    if (p_cfg->cycle_end_irq >= 0)
+    {
+        R_BSP_IrqCfgEnable(p_cfg->cycle_end_irq, p_cfg->cycle_end_ipl, p_instance_ctrl);
+    }
+
+    /* Set callback and context pointers */
+    p_instance_ctrl->p_callback        = p_cfg->p_callback;
+    p_instance_ctrl->p_context         = p_cfg->p_context;
+    p_instance_ctrl->p_callback_memory = NULL;
+
+    p_instance_ctrl->open = ULPT_OPEN;
+
+    /* All done.  */
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Starts timer. Implements @ref timer_api_t::start.
+ *
+ * Example:
+ * @snippet r_ulpt_example.c R_ULPT_Start
+ *
+ * @retval FSP_SUCCESS                 Timer started.
+ * @retval FSP_ERR_ASSERTION           p_ctrl is null.
+ * @retval FSP_ERR_NOT_OPEN            The instance control structure is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_ULPT_Start (timer_ctrl_t * const p_ctrl)
+{
+    ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl;
+
+    fsp_err_t err = r_ulpt_common_preamble(p_instance_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    /* Start timer */
+    p_instance_ctrl->p_reg->ULPTCR = ULPT_PRV_ULPTCR_START_TIMER;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Stops the timer.  Implements @ref timer_api_t::stop.
+ *
+ * Example:
+ * @snippet r_ulpt_example.c R_ULPT_Stop
+ *
+ * @retval FSP_SUCCESS                 Timer stopped.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance control structure is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_ULPT_Stop (timer_ctrl_t * const p_ctrl)
+{
+    ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl;
+
+    fsp_err_t err = r_ulpt_common_preamble(p_instance_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    /* Stop timer */
+    p_instance_ctrl->p_reg->ULPTCR = ULPT_PRV_ULPTCR_STOP_TIMER;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Resets the counter value to the period minus one. Implements @ref timer_api_t::reset.
+ *
+ * @retval FSP_SUCCESS                 Counter reset.
+ * @retval FSP_ERR_ASSERTION           p_ctrl is NULL
+ * @retval FSP_ERR_NOT_OPEN            The instance control structure is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_ULPT_Reset (timer_ctrl_t * const p_ctrl)
+{
+    ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl;
+
+    fsp_err_t err = r_ulpt_common_preamble(p_instance_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    /* Reset counter to period minus one. */
+    p_instance_ctrl->p_reg->ULPTCNT = p_instance_ctrl->period - 1U;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Enables external event triggers that start, stop, clear, or capture the counter. Implements @ref timer_api_t::enable.
+ *
+ * Example:
+ * @snippet r_ulpt_example.c R_ULPT_Enable
+ *
+ * @retval FSP_SUCCESS                 External events successfully enabled.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_ULPT_Enable (timer_ctrl_t * const p_ctrl)
+{
+    ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl;
+#if ULPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(ULPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Reset counter to period minus one. */
+    p_instance_ctrl->p_reg->ULPTCNT = p_instance_ctrl->period - 1U;
+
+    /* Enable captures. */
+    p_instance_ctrl->p_reg->ULPTCR = ULPT_PRV_ULPTCR_START_TIMER;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Disables external event triggers that start, stop, clear, or capture the counter. Implements @ref timer_api_t::disable.
+ *
+ * Example:
+ * @snippet r_ulpt_example.c R_ULPT_Disable
+ *
+ * @retval FSP_SUCCESS                 External events successfully disabled.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_ULPT_Disable (timer_ctrl_t * const p_ctrl)
+{
+    ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl;
+#if ULPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(ULPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Disable captures. */
+    p_instance_ctrl->p_reg->ULPTCR = ULPT_PRV_ULPTCR_STOP_TIMER;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Updates period. The new period is updated immediately and the counter is reset to the maximum value. Implements
+ * @ref timer_api_t::periodSet.
+ *
+ * @warning If periodic output is used, the duty cycle buffer registers are updated after the period buffer register.
+ * If this function is called while the timer is running and an AGT underflow occurs during processing, the duty cycle
+ * will not be the desired 50% duty cycle until the counter underflow after processing completes.
+ *
+ * @warning Stop the timer before calling this function if one-shot output is used.
+ *
+ * Example:
+ * @snippet r_ulpt_example.c R_ULPT_PeriodSet
+ *
+ * @retval FSP_SUCCESS                 Period value updated.
+ * @retval FSP_ERR_ASSERTION           A required pointer was NULL, or the period was not in the valid range of
+ *                                     1 to 0xFFFF.
+ * @retval FSP_ERR_NOT_OPEN            The instance control structure is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_ULPT_PeriodSet (timer_ctrl_t * const p_ctrl, uint32_t const period_counts)
+{
+    ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl;
+#if ULPT_CFG_PARAM_CHECKING_ENABLE
+
+    /* Validate period parameter. */
+    FSP_ASSERT(0U != period_counts);
+#endif
+
+    fsp_err_t err = r_ulpt_common_preamble(p_instance_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    /* Set period. */
+    r_ulpt_period_register_set(p_instance_ctrl, period_counts);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Updates duty cycle. If the timer is counting, the new duty cycle is reflected after the next counter underflow.
+ * Implements @ref timer_api_t::dutyCycleSet.
+ *
+ * Example:
+ * @snippet r_ulpt_example.c R_ULPT_DutyCycleSet
+ *
+ * @retval FSP_SUCCESS                 Duty cycle updated.
+ * @retval FSP_ERR_ASSERTION           A required pointer was NULL, or the pin was not ULPT_ULPTO_ULPTOA or ULPT_ULPTO_ULPTOB.
+ * @retval FSP_ERR_INVALID_ARGUMENT    Duty cycle was not in the valid range of 0 to period (counts) - 1
+ * @retval FSP_ERR_NOT_OPEN            The instance control structure is not opened.
+ * @retval FSP_ERR_UNSUPPORTED         ULPT_CFG_OUTPUT_SUPPORT_ENABLE is 0.
+ **********************************************************************************************************************/
+fsp_err_t R_ULPT_DutyCycleSet (timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin)
+{
+#if ULPT_CFG_OUTPUT_SUPPORT_ENABLE
+    ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl;
+ #if ULPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT((pin == ULPT_OUTPUT_PIN_ULPTOA) || (pin == ULPT_OUTPUT_PIN_ULPTOB));
+ #endif
+
+    fsp_err_t err = r_ulpt_common_preamble(p_instance_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+ #if ULPT_CFG_PARAM_CHECKING_ENABLE
+    if (0U != p_instance_ctrl->period)
+    {
+        FSP_ERROR_RETURN(duty_cycle_counts < (p_instance_ctrl->period), FSP_ERR_INVALID_ARGUMENT);
+    }
+ #endif
+
+    uint32_t temp_duty_cycle_counts           = duty_cycle_counts;
+    uint32_t ulptcmsr_ulptoab_start_level_bit = 1U << 2 << (4 * pin); /* polarity set*/
+    ulpt_extended_cfg_t const * p_extend      = (ulpt_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend;
+    if (p_extend->ulptoab_settings & ulptcmsr_ulptoab_start_level_bit)
+    {
+        /* Invert duty cycle if this pin starts high since the high portion is at the beginning of the cycle. */
+        temp_duty_cycle_counts = p_instance_ctrl->period - temp_duty_cycle_counts - 1;
+    }
+
+    /* Set duty cycle. */
+    volatile uint32_t * const p_ulptcm = &p_instance_ctrl->p_reg->ULPTCMA;
+    p_ulptcm[pin] = temp_duty_cycle_counts;
+
+    return FSP_SUCCESS;
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+    FSP_PARAMETER_NOT_USED(duty_cycle_counts);
+    FSP_PARAMETER_NOT_USED(pin);
+
+    FSP_RETURN(FSP_ERR_UNSUPPORTED);
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Gets timer information and store it in provided pointer p_info. Implements @ref timer_api_t::infoGet.
+ *
+ * Example:
+ * @snippet r_ulpt_example.c R_ULPT_InfoGet
+ *
+ * @retval FSP_SUCCESS                 Period, count direction, and frequency stored in p_info.
+ * @retval FSP_ERR_ASSERTION           A required pointer is NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance control structure is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_ULPT_InfoGet (timer_ctrl_t * const p_ctrl, timer_info_t * const p_info)
+{
+    ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl;
+#if ULPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_info);
+#endif
+
+    fsp_err_t err = r_ulpt_common_preamble(p_instance_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    /* Get and store period */
+    p_info->period_counts = p_instance_ctrl->period;
+
+    /* Get and store clock frequency */
+    /* ulpt_extended_cfg_t const * p_extend = (ulpt_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend;*/
+    p_info->clock_frequency = r_ulpt_clock_frequency_get(p_instance_ctrl->p_reg);
+
+    /* ULPT supports only counting down direction */
+    p_info->count_direction = TIMER_DIRECTION_DOWN;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Retrieves the current state and counter value stores them in p_status. Implements @ref timer_api_t::statusGet.
+ *
+ * Example:
+ * @snippet r_ulpt_example.c R_ULPT_StatusGet
+ *
+ * @retval FSP_SUCCESS                 Current status and counter value provided in p_status.
+ * @retval FSP_ERR_ASSERTION           A required pointer is NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance control structure is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_ULPT_StatusGet (timer_ctrl_t * const p_ctrl, timer_status_t * const p_status)
+{
+    ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl;
+
+#if ULPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_status);
+#endif
+
+    fsp_err_t err = r_ulpt_common_preamble(p_instance_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    /* Read the state. */
+    p_status->state = (timer_state_t) p_instance_ctrl->p_reg->ULPTCR_b.TCSTF;
+
+    /* Read counter value */
+    p_status->counter = p_instance_ctrl->p_reg->ULPTCNT;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Updates the user callback with the option to provide memory for the callback argument structure.
+ * Implements @ref timer_api_t::callbackSet.
+ *
+ * @retval  FSP_SUCCESS                  Callback updated successfully.
+ * @retval  FSP_ERR_ASSERTION            A required pointer is NULL.
+ * @retval  FSP_ERR_NOT_OPEN             The control block has not been opened.
+ * @retval  FSP_ERR_NO_CALLBACK_MEMORY   p_callback is non-secure and p_callback_memory is either secure or NULL.
+ **********************************************************************************************************************/
+fsp_err_t R_ULPT_CallbackSet (timer_ctrl_t * const          p_api_ctrl,
+                              void (                      * p_callback)(timer_callback_args_t *),
+                              void const * const            p_context,
+                              timer_callback_args_t * const p_callback_memory)
+{
+    ulpt_instance_ctrl_t * p_ctrl = (ulpt_instance_ctrl_t *) p_api_ctrl;
+
+#if ULPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_ctrl);
+    FSP_ASSERT(p_callback);
+    FSP_ERROR_RETURN(ULPT_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+#if BSP_TZ_SECURE_BUILD
+
+    /* Get security state of p_callback */
+    bool callback_is_secure =
+        (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE));
+
+ #if ULPT_CFG_PARAM_CHECKING_ENABLE
+
+    /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */
+    timer_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory,
+                                                                                        CMSE_AU_NONSECURE);
+    FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY);
+ #endif
+#endif
+
+    /* Store callback and context */
+#if BSP_TZ_SECURE_BUILD
+    p_ctrl->p_callback = callback_is_secure ? p_callback :
+                         (void (*)(timer_callback_args_t *))cmse_nsfptr_create(p_callback);
+#else
+    p_ctrl->p_callback = p_callback;
+#endif
+    p_ctrl->p_context         = p_context;
+    p_ctrl->p_callback_memory = p_callback_memory;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Stops counter, disables interrupts, disables output pins, and clears internal driver data.  Implements
+ * @ref timer_api_t::close.
+ *
+ *
+ *
+ * @retval FSP_SUCCESS                 Timer closed.
+ * @retval FSP_ERR_ASSERTION           p_ctrl is NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance control structure is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_ULPT_Close (timer_ctrl_t * const p_ctrl)
+{
+    ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl;
+
+    fsp_err_t err = r_ulpt_common_preamble(p_instance_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    /* Cleanup the device: Stop counter, disable interrupts, and power down if no other channels are in use. */
+
+    /* Stop timer */
+    p_instance_ctrl->p_reg->ULPTCR = ULPT_PRV_ULPTCR_FORCE_STOP_TIMER;
+
+    /* Clear ULPT output. */
+    p_instance_ctrl->p_reg->ULPTIOC = 0U;
+
+    if (FSP_INVALID_VECTOR != p_instance_ctrl->p_cfg->cycle_end_irq)
+    {
+        NVIC_DisableIRQ(p_instance_ctrl->p_cfg->cycle_end_irq);
+        R_FSP_IsrContextSet(p_instance_ctrl->p_cfg->cycle_end_irq, p_instance_ctrl);
+    }
+
+    p_instance_ctrl->open = 0U;
+
+    return FSP_SUCCESS;
+}
+
+/** @} (end addtogroup ULPT) */
+
+/***********************************************************************************************************************
+ * Private Functions
+ **********************************************************************************************************************/
+
+#if ULPT_CFG_PARAM_CHECKING_ENABLE
+
+/*******************************************************************************************************************//**
+ * Parameter checking for R_ULPT_Open.
+ *
+ * @param[in] p_instance_ctrl              Pointer to instance control structure.
+ * @param[in] p_cfg                        Configuration structure for this instance
+ *
+ * @retval FSP_SUCCESS                     Initialization was successful and timer has started.
+ * @retval FSP_ERR_ASSERTION               A required input pointer is NULL or an invalid parameter exists.
+ * @retval FSP_ERR_ALREADY_OPEN            R_ULPT_Open has already been called for this p_ctrl.
+ * @retval FSP_ERR_IRQ_BSP_DISABLED        A required interrupt has not been enabled in the vector table.
+ * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT  Requested channel number is not available on ULPT.
+ **********************************************************************************************************************/
+static fsp_err_t r_ulpt_open_param_checking (ulpt_instance_ctrl_t * p_instance_ctrl, timer_cfg_t const * const p_cfg)
+{
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT(NULL != p_cfg);
+    FSP_ASSERT(NULL != p_cfg->p_extend);
+    FSP_ERROR_RETURN(ULPT_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
+
+    /* Validate channel number. */
+    FSP_ERROR_RETURN(((1U << p_cfg->channel) & BSP_FEATURE_ULPT_VALID_CHANNEL_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT);
+
+    /* Enable IRQ if user supplied a callback function,
+     *  or if the timer is a one-shot timer (so the driver is able to
+     *  turn off the timer after one period. */
+    if ((NULL != p_cfg->p_callback) || (TIMER_MODE_ONE_SHOT == p_cfg->mode))
+    {
+        /* Return error if IRQ is required and not in the vector table. */
+        FSP_ERROR_RETURN(p_cfg->cycle_end_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED);
+    }
+
+     ulpt_extended_cfg_t const * p_extend = (ulpt_extended_cfg_t const *) p_cfg->p_extend;
+    /* Validate mode specific settings. */
+    if ((ULPT_CLOCK_LOCO == p_extend->count_source) || (ULPT_CLOCK_SUBCLOCK == p_extend->count_source))
+    {
+        /* Timer mode */
+
+        /* Validate the divider. */
+        FSP_ASSERT(p_cfg->source_div <= TIMER_SOURCE_DIV_128);
+
+        /* Count enable,start,amd restart functions are not allowed in timer mode. */
+        FSP_ASSERT(p_extend->enable_function != ULPT_ENABLE_FUNCTION_ENABLE_LOW);
+        FSP_ASSERT(p_extend->enable_function != ULPT_ENABLE_FUNCTION_ENABLE_HIGH);
+        FSP_ASSERT(p_extend->enable_function != ULPT_ENABLE_FUNCTION_START);
+        FSP_ASSERT(p_extend->enable_function != ULPT_ENABLE_FUNCTION_RESTART);
+    }
+    else
+    {
+        /* Event counter mode */
+        /* No Divider allowed. */
+        FSP_ASSERT(p_cfg->source_div <= TIMER_SOURCE_DIV_1);
+    }
+    return (FSP_SUCCESS);
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Common code at the beginning of all ULPT functions except open.
+ *
+ * @param[in] p_instance_ctrl          Pointer to instance control structure.
+ *
+ * @retval FSP_SUCCESS                 No invalid conditions detected, timer state matches expected state.
+ * @retval FSP_ERR_ASSERTION           p_ctrl is null.
+ * @retval FSP_ERR_NOT_OPEN            The instance control structure is not opened.
+ **********************************************************************************************************************/
+static fsp_err_t r_ulpt_common_preamble (ulpt_instance_ctrl_t * p_instance_ctrl)
+{
+#if ULPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(ULPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Ensure timer state reflects expected status. */
+    uint32_t ulptcr_tstart = p_instance_ctrl->p_reg->ULPTCR_b.TSTART;
+    FSP_HARDWARE_REGISTER_WAIT(ulptcr_tstart, p_instance_ctrl->p_reg->ULPTCR_b.TCSTF);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Sets count source, divider, and other hardware registers.
+ *
+ * @note Counter must be stopped before entering this function.
+ *
+ * @param[in]  p_instance_ctrl    Control block for this instance
+ * @param[in]  p_cfg              Configuration structure for this instance
+ **********************************************************************************************************************/
+
+static void r_ulpt_hardware_cfg (ulpt_instance_ctrl_t * p_instance_ctrl, timer_cfg_t const * const p_cfg)
+{
+    ulpt_extended_cfg_t const * p_extend = (ulpt_extended_cfg_t const *) p_cfg->p_extend;
+
+    /* ULPT register locals */
+    uint32_t ulptmr1  = 0U;
+    uint32_t ulptmr2  = 0U;
+    uint32_t ulptmr3  = 0U;
+    uint32_t ulptioc  = 0U;
+    uint32_t ulptisr  = 0U;
+    uint32_t ulptcmsr = 0U;
+
+    /* Configure the count source(LOCO or SCK) and mode(event or Timer). */
+    ulptmr1 |= p_extend->count_source & (R_ULPT0_ULPTMR1_TMOD1_Msk | R_ULPT0_ULPTMR1_TCK1_Msk);
+    
+    if (TIMER_MODE_ONE_SHOT == p_cfg->mode)
+    {
+        ulptmr3 |= R_ULPT0_ULPTMR3_TCNTCTL_Msk;
+    }
+    if (p_extend->count_source != ULPT_CLOCK_ULPTEVI)
+    {
+        /* Timer mode */
+        ulptmr1 &= ~R_ULPT0_ULPTMR1_TMOD1_Msk;
+
+        /* The divider is only used for normal timer operation. */
+        ulptmr2 |= p_cfg->source_div & R_ULPT0_ULPTMR2_CKS_Msk;
+    }
+#if ULPT_CFG_INPUT_SUPPORT_ENABLE
+    else // (p_extend->count_source == ULPT_CLOCK_ULPTEVI)
+    {
+        /* Event counter mode */
+        ulptmr1 |= R_ULPT0_ULPTMR1_TMOD1_Msk;
+
+        /* Set the edge selection for for event pin. */
+        /*  For Falling we set it for rising edge and flip the polarity */
+        ulptmr1 |= p_extend->event_pin & R_ULPT0_ULPTMR1_TEDGPL_Msk;
+        ulptmr3 |= p_extend->event_pin & R_ULPT0_ULPTMR3_TEVPOL_Msk;
+        /* Configure input filtering */
+        ulptioc |= p_extend->ulptevi_filter & R_ULPT0_ULPTIOC_TIPF_Msk;
+
+        /* Select if the ULPTEE pin should be ignored. */
+        ulptioc |= p_extend->enable_function & R_ULPT0_ULPTIOC_TIOGT0_Msk;
+
+        /* Set the active polarity for ULPTEE. This is only set for count enable function. */
+        ulptisr |= p_extend->enable_function & R_ULPT0_ULPTISR_RCCPSEL2_Msk;
+    }
+#endif    
+
+
+
+    /* ULPTEE can be used in either timer or event mode. */
+    /* Configure ULPTEE pin function and edge polarity for start or restart functions. */
+    ulptmr3 |= p_extend->enable_function & R_ULPT0_ULPTMR3_TEECTL_Msk;
+    ulptmr3 |= p_extend->trigger_edge & R_ULPT0_ULPTMR3_TEEPOL_Msk;
+
+    
+#if ULPT_CFG_OUTPUT_SUPPORT_ENABLE
+
+    /* Set output if requested. */
+    if ( p_extend->ulpto != ULPT_PULSE_PIN_CFG_DISABLED)
+    {
+        ulptioc |= R_ULPT0_ULPTIOC_TOE_Msk;
+        /* Now set the polarity*/ 
+        if (p_extend->ulpto == ULPT_PULSE_PIN_CFG_ENABLED_START_LEVEL_HIGH)
+        {
+            ulptmr3 |=  R_ULPT0_ULPTMR3_TOPOL_Msk;
+        }
+        else
+        {
+            ulptmr3 &=  ~R_ULPT0_ULPTMR3_TOPOL_Msk;
+        }
+    }
+    /* set enable match, output, and polarity of both match outputs*/
+    ulptcmsr = p_extend->ulptoab_settings & ULPT_PRV_ULPTCMSR_VALID_BITS;
+
+    /* Set initial duty cycle for PWM mode in open.  Duty cycle is set for other modes in r_agt_period_register_set. */
+    if (TIMER_MODE_PWM == p_instance_ctrl->p_cfg->mode)
+    {
+        uint32_t inverted_duty_cycle = p_instance_ctrl->p_cfg->period_counts -
+                                       p_instance_ctrl->p_cfg->duty_cycle_counts - 1;
+        /*In this driver match A and match b have the same duty cycle*/
+        uint32_t ulptcma = p_instance_ctrl->p_cfg->duty_cycle_counts;
+        uint32_t ulptcmb = p_instance_ctrl->p_cfg->duty_cycle_counts;
+        if (ULPT_MATCH_PIN_CFG_DISABLED != p_extend->ulptoab_settings_b.ulptoa)
+        {
+            if (ULPT_MATCH_PIN_CFG_START_LEVEL_HIGH == p_extend->ulptoab_settings_b.ulptoa)
+            {
+                ulptcma = inverted_duty_cycle;
+            }
+            p_instance_ctrl->p_reg->ULPTCMA = ulptcma;
+        }
+        if (ULPT_MATCH_PIN_CFG_DISABLED != p_extend->ulptoab_settings_b.ulptob)
+        {
+            if (ULPT_MATCH_PIN_CFG_START_LEVEL_HIGH == p_extend->ulptoab_settings_b.ulptob)
+            {
+                ulptcmb = inverted_duty_cycle;
+            }
+            p_instance_ctrl->p_reg->ULPTCMB = ulptcmb;
+
+        }
+    }
+#endif
+
+    p_instance_ctrl->p_reg->ULPTMR1  = (uint8_t)ulptmr1;
+    p_instance_ctrl->p_reg->ULPTMR2  = (uint8_t)ulptmr2;
+    p_instance_ctrl->p_reg->ULPTMR3  = (uint8_t)ulptmr3;
+    p_instance_ctrl->p_reg->ULPTIOC  = (uint8_t)ulptioc;
+    p_instance_ctrl->p_reg->ULPTISR  = (uint8_t)ulptisr;
+    p_instance_ctrl->p_reg->ULPTCMSR = (uint8_t)ulptcmsr;
+}
+
+/*******************************************************************************************************************//**
+ * Sets period register and updates compare match registers in one-shot and periodic mode.
+ *
+ * @param[in]  p_instance_ctrl    Control block for this instance
+ * @param[in]  period_counts      ULPT period in counts
+ **********************************************************************************************************************/
+static void r_ulpt_period_register_set (ulpt_instance_ctrl_t * p_instance_ctrl, uint32_t period_counts)
+{
+    /* Store the period value so it can be retrieved later. */
+    p_instance_ctrl->period = period_counts;
+
+    uint32_t period_reg = period_counts - 1U;
+
+#if ULPT_CFG_OUTPUT_SUPPORT_ENABLE
+    uint32_t duty_cycle_counts = 0U;
+    if (TIMER_MODE_PERIODIC == p_instance_ctrl->p_cfg->mode)
+    {
+        duty_cycle_counts = (period_counts >> 1);
+    }
+    else if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode)
+    {
+        duty_cycle_counts = period_reg;
+    }
+    else
+    {
+        /* Do nothing, duty cycle should not be updated in R_ULPT_PeriodSet. */
+    }
+
+    if (TIMER_MODE_PWM != p_instance_ctrl->p_cfg->mode)
+    {
+        p_instance_ctrl->p_reg->ULPTCMA = duty_cycle_counts;
+        p_instance_ctrl->p_reg->ULPTCMB = duty_cycle_counts;
+    }
+#endif
+
+    /* Set counter to period minus one. */
+    p_instance_ctrl->p_reg->ULPTCNT = period_reg;
+}
+
+/*******************************************************************************************************************//**
+ * Obtains the clock frequency of ULPT for all clock sources 
+ *
+ * @param[in]  p_ulpt_regs         Registers of ULPT channel used
+ *
+ * @return Source clock frequency of ULPT in Hz with prescaler divider applied
+ **********************************************************************************************************************/
+static uint32_t r_ulpt_clock_frequency_get (R_ULPT0_Type * p_ulpt_regs)
+{
+    uint32_t clock_freq_hz    = 0U;
+    uint8_t  count_source_int = p_ulpt_regs->ULPTMR1_b.TCK1;
+    uint8_t  divider          = p_ulpt_regs->ULPTMR2_b.CKS;
+
+    if (ULPT_CLOCK_SUBCLOCK == (count_source_int & R_ULPT0_ULPTMR1_TCK1_Msk))
+    {
+        clock_freq_hz = BSP_SUBCLOCK_FREQ_HZ;
+    }
+    else
+    {
+        clock_freq_hz = BSP_LOCO_FREQ_HZ;
+    }
+
+    clock_freq_hz >>= divider;
+
+    return clock_freq_hz;
+}
+
+/*********************************************************************************************************************
+ * AGT counter underflow interrupt.
+ **********************************************************************************************************************/
+void ulpt_int_isr (void)
+{
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE
+    uint32_t statusMask;
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    /* Clear pending IRQ to make sure it doesn't fire again after exiting */
+    R_BSP_IrqStatusClear(irq);
+
+    /* Recover ISR context saved in open. */
+    ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    /* Save ULPTCR to determine the source of the interrupt. */
+    uint32_t ulptcr = p_instance_ctrl->p_reg->ULPTCR;
+
+    /* Invoke the callback function if it is set. */
+    if (NULL != p_instance_ctrl->p_callback)
+    {
+        /* Setup parameters for the user-supplied callback function. */
+        timer_callback_args_t callback_args;
+
+        /* Store callback arguments in memory provided by user if available.  This allows callback arguments to be
+         * stored in non-secure memory so they can be accessed by a non-secure callback function. */
+        timer_callback_args_t * p_args = p_instance_ctrl->p_callback_memory;
+        if (NULL == p_args)
+        {
+            /* Store on stack */
+            p_args = &callback_args;
+        }
+        else
+        {
+            /* Save current arguments on the stack in case this is a nested interrupt. */
+            callback_args = *p_args;
+        }
+
+        if (ulptcr & R_ULPT0_ULPTCR_TUNDF_Msk)
+        {
+            p_args->event = TIMER_EVENT_CYCLE_END;
+        }
+        else if (ulptcr & R_ULPT0_ULPTCR_TCMAF_Msk)
+        {
+            p_args->event = TIMER_EVENT_CAPTURE_A;
+        }
+        else if (ulptcr & R_ULPT0_ULPTCR_TCMBF_Msk)
+        {
+            p_args->event = TIMER_EVENT_CAPTURE_B;
+        }
+        else 
+        {
+
+        }
+
+        p_args->p_context = p_instance_ctrl->p_context;
+
+#if BSP_TZ_SECURE_BUILD
+
+        /* p_callback can point to a secure function or a non-secure function. */
+        if (!cmse_is_nsfptr(p_instance_ctrl->p_callback))
+        {
+            /* If p_callback is secure, then the project does not need to change security state. */
+            p_instance_ctrl->p_callback(p_args);
+        }
+        else
+        {
+            /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */
+            ulpt_prv_ns_callback p_callback = (ulpt_prv_ns_callback) (p_instance_ctrl->p_callback);
+            p_callback(p_args);
+        }
+
+#else
+
+        /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */
+        p_instance_ctrl->p_callback(p_args);
+#endif
+
+        if (NULL != p_instance_ctrl->p_callback_memory)
+        {
+            /* Restore callback memory in case this is a nested interrupt. */
+            *p_instance_ctrl->p_callback_memory = callback_args;
+        }
+
+        /* Retreive AGTCR in case it was modified in the callback. */
+        ulptcr = p_instance_ctrl->p_reg->ULPTCR;
+    }
+
+    /* Clear flags in AGTCR. */
+    /* In one shot mode we need to stop the timer*/
+    statusMask = ULPT_PRV_ULPTCR_STATUS_FLAGS;
+    if (p_instance_ctrl->p_reg->ULPTMR3 &  R_ULPT0_ULPTMR3_TCNTCTL_Msk)
+    {
+        statusMask |= R_ULPT0_ULPTCR_TSTART_Msk;
+    }
+
+    p_instance_ctrl->p_reg->ULPTCR = (uint8_t) (ulptcr & ~statusMask);
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE
+}
diff --git a/ra/fsp/src/r_usb_basic/r_usb_basic.c b/ra/fsp/src/r_usb_basic/r_usb_basic.c
index 4ceafeb7f..e93cb673a 100644
--- a/ra/fsp/src/r_usb_basic/r_usb_basic.c
+++ b/ra/fsp/src/r_usb_basic/r_usb_basic.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -449,6 +449,7 @@ fsp_err_t R_USB_Open (usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_c
         case USB_CLASS_INTERNAL_PMSC:
         case USB_CLASS_INTERNAL_PAUD:
         case USB_CLASS_INTERNAL_PPRN:
+        case USB_CLASS_INTERNAL_DFU:
         {
             FSP_ERROR_RETURN(USB_MODE_PERI == p_cfg->usb_mode, FSP_ERR_USB_PARAMETER)
 
@@ -899,6 +900,10 @@ fsp_err_t R_USB_Open (usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_c
             g_usb_open_class[p_ctrl->module_number] |= (uint16_t) (1 << USB_CLASS_INTERNAL_PPRN);
 #endif                                 /* defined(USB_CFG_PPRN_USE) */
 
+#if defined(USB_CFG_DFU_USE)
+            g_usb_open_class[p_ctrl->module_number] |= (uint16_t) (1 << USB_CLASS_INTERNAL_DFU);
+#endif                                 /* defined(USB_CFG_PPRN_USE) */
+
 #if defined(USB_CFG_OTG_USE)
             _ux_system_otg->ux_system_otg_device_type = UX_OTG_DEVICE_B;
             (*g_p_otg_callback[p_ctrl->module_number])(UX_OTG_MODE_SLAVE);
@@ -919,10 +924,13 @@ fsp_err_t R_USB_Open (usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_c
         {
             usb_otg_irq_callback(0);
         }
+
+  #if USB_NUM_USBIP == 2
         else
         {
             usb2_otg_irq_callback(0);
         }
+  #endif                               /* USB_NUM_USBIP == 2 */
     }
  #endif                                /* defined(USB_CFG_OTG_USB) */
 #endif                                 /* (BSP_CFG_RTOS == 1) */
diff --git a/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h b/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h
index 2bc709eed..3cdc5a00f 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h
+++ b/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -22,10 +22,14 @@
 
  #include "r_usb_basic_cfg.h"
 
- #define USB_CFG_LITTLE    (0U)
- #define USB_CFG_BIG       (1U)
+ #define USB_CFG_LITTLE     (0U)
+ #define USB_CFG_BIG        (1U)
 
- #define USB_CFG_ENDIAN    (USB_CFG_LITTLE)
+ #define USB_NOT_SUPPORT    (0U)
+ #define USB_FS_MODULE      (1U)
+ #define USB_HS_MODULE      (2U)
+
+ #define USB_CFG_ENDIAN     (USB_CFG_LITTLE)
 
  #if defined(USB_DEBUG_ON)
   #include    <stdlib.h>               /* @@@MISRA del */
@@ -42,12 +46,107 @@ extern "C" {
  * Macro definitions
  **********************************************************************************************************************/
  #if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8)
+
   #define USB_HIGH_SPEED_MODULE
+  #define USB_IP0_MODULE    USB_FS_MODULE
+  #define USB_IP1_MODULE    USB_HS_MODULE
+
+  #define USB_NUM_USBIP     (2U)
+
  #endif                                /* defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) */
 
+ #if defined(BSP_MCU_GROUP_RA2A1) || defined(BSP_MCU_GROUP_RA6E2) || defined(BSP_MCU_GROUP_RA4E2)   \
+    || defined(BSP_MCU_GROUP_RA4M1) || defined(BSP_MCU_GROUP_RA4M2) || defined(BSP_MCU_GROUP_RA4M3) \
+    || defined(BSP_MCU_GROUP_RA4W1) || defined(BSP_MCU_GROUP_RA6M1) || defined(BSP_MCU_GROUP_RA6M2) \
+    || defined(BSP_MCU_GROUP_RA6M4)
+
+  #define USB_IP0_MODULE    USB_FS_MODULE
+  #define USB_IP1_MODULE    USB_NOT_SUPPORT
+
+  #define USB_NUM_USBIP     (1U)
+ #endif                                /* defined(BSP_MCU_GROUP_RA2A1 || defined(BSP_MCU_GROUP_RA6E2) || defined(BSP_MCU_GROUP_RA4E2) */
+
+ #if defined(BSP_MCU_GROUP_RA2A1) || defined(BSP_MCU_GROUP_RA6E2) || defined(BSP_MCU_GROUP_RA4E2)
+
+  #define USB_SUPPORT_MINI_MODULE
+  #define USB_NOT_SUPPORT_HOST
+  #define USB_NOT_SUPPORT_DMAC
+
+ #endif                                      /* defined(BSP_MCU_GROUP_RA2A1) || defined(BSP_MCU_GROUP_RA6E2) || defined(BSP_MCU_GROUP_RA4E2) */
+
+ #if defined(BSP_MCU_GROUP_RA2A1) || defined(BSP_MCU_GROUP_RA4W1)
+
+  #define USB_SUPPORT_PERI_LS                /* USB Peripheral Low-speed Support Module */
+
+ #endif                                      /* defined(BSP_MCU_GROUP_RA2A1) */
+
  #if defined(BSP_MCU_GROUP_RA2A1)
-  #define USB_SUPPORT_HOCO_MODULE
- #endif                                /* defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) */
+
+  #define USB_UNALIGNED_MEMORY_ACCESS_NG_MCU /* Coretex M23 etc */
+
+ #endif                                      /* defined(BSP_MCU_GROUP_RA2A1) */
+
+ #if defined(BSP_MCU_GROUP_RA2A1)
+
+  #define USB_SUPPORT_HOCO_MODULE            /* UCKSELC bit */
+
+ #endif                                      /* defined(BSP_MCU_GROUP_RA2A1) */
+
+ #if defined(BSP_MCU_GROUP_RA2A1) || defined(BSP_MCU_GROUP_RA4M1)
+
+  #define USB_LDO_REGULATOR_MODULE           /* VDCEN bit */
+
+ #endif                                      /* (BSP_MCU_GROUP_RA2A1) || defined(BSP_MCU_GROUP_RA4M1) */
+
+ #if defined(BSP_MCU_GROUP_RA4M1) || defined(BSP_MCU_GROUP_RA4W1) || defined(BSP_MCU_GROUP_RA2A1)
+
+  #define USB_SUPPORT_VDDUSBE                /* VDDUSBE bit */
+
+ #endif                                      /* defined(BSP_MCU_GROUP_RA4M1) || defined(BSP_MCU_GROUP_RA4W1) || defined(BSP_MCU_GROUP_RA2A1) */
+
+ #if defined(BSP_MCU_GROUP_RA6M3) || defined(BSP_MCU_GROUP_RA6M2) || defined(BSP_MCU_GROUP_RA6M1)
+
+  #define USB_SUPPORT_PHYSLEW                /* PHYSLEW bit */
+
+ #endif                                      /* defined(BSP_MCU_GROUP_RA6M3) || defined(BSP_MCU_GROUP_RA6M2) || defined(BSP_MCU_GROUP_RA6M1) */
+
+ #if defined(BSP_MCU_GROUP_RA6M3) || defined(BSP_MCU_GROUP_RA6M2) || defined(BSP_MCU_GROUP_RA6M1)
+
+  #define USB_PHYSLEW_VALUE    (0xEU)
+
+ #endif                                /* defined(BSP_MCU_GROUP_RA6M3) || defined(BSP_MCU_GROUP_RA6M2) || defined(BSP_MCU_GROUP_RA6M1) */
+
+ #if defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8)
+
+  #define USB_CNEN_SYSCFG_USB_IP1      /* CNEN bit */
+  #define USB_SUPPORT_BC_HS            /* Battery Charging in High-speed module */
+
+ #endif                                /* defined(BSP_MCU_GROUP_RA2A1 || defined(BSP_MCU_GROUP_RA6E2) || defined(BSP_MCU_GROUP_RA4E2) */
+
+ #if defined(BSP_MCU_GROUP_RA2A1)
+
+  #define USB_CNEN_SYSCFG_USB_IP0      /* CNEN bit */
+  #define USB_SUPPORT_BC_FS            /* Battery Charging in Full-speed module*/
+
+ #endif                                /* defined(USB_SUPPORT_MINI_MODULE) */                            /* defined(BSP_MCU_GROUP_RA2A1 */
+
+ #if defined(BSP_MCU_GROUP_RA6E2) || defined(BSP_MCU_GROUP_RA4E2)                                   \
+    || defined(BSP_MCU_GROUP_RA4M1) || defined(BSP_MCU_GROUP_RA4M2) || defined(BSP_MCU_GROUP_RA4M3) \
+    || defined(BSP_MCU_GROUP_RA4W1) || defined(BSP_MCU_GROUP_RA6M5)                                 \
+    || defined(BSP_MCU_GROUP_RA6M4)
+
+  #define USB_CNEN_PHYSECTRL_USB_IP0   /* CNEN bit */
+
+  #if defined(BSP_MCU_GROUP_RA6M5)
+   #define USB_SUPPORT_BC_HS           /* Battery Charging in High-speed module */
+   #define USB_SUPPORT_BC_FS           /* Battery Charging in Full-speed module */
+  #endif                               /* defined(BSP_MCU_GROUP_RA6M5) */
+
+  #if defined(BSP_MCU_GROUP_RA4M1) || defined(BSP_MCU_GROUP_RA4M2) || defined(BSP_MCU_GROUP_RA4M3) \
+    || defined(BSP_MCU_GROUP_RA4W1) || defined(BSP_MCU_GROUP_RA6M4)
+   #define USB_SUPPORT_BC_FS
+  #endif                               /* defined(BSP_MCU_GROUP_RA4M1) || defined(BSP_MCU_GROUP_RA4M2) || defined(BSP_MCU_GROUP_RA4M3) */
+ #endif                                /* defined(BSP_MCU_GROUP_RA6E2) || defined(BSP_MCU_GROUP_RA4E2) */
 
 /* Version Number of API. */
  #define USB_VERSION_MAJOR        (1)
@@ -219,9 +318,6 @@ extern "C" {
  * Macro definitions
  ******************************************************************************/
 
-/* The number of USBIP */
- #define USB_NUM_USBIP                          (2U)
-
 /* USB module definition */
  #define USB_M0                                 (R_USB_FS0)
 
@@ -249,19 +345,19 @@ extern "C" {
  #define USB1_D1FIFO_MBW                        (USB_MBW_32)
 
 /* Start Pipe No */
- #if defined(BSP_MCU_GROUP_RA2A1)
+ #if defined(USB_SUPPORT_MINI_MODULE)
   #define USB_MIN_PIPE_NO                       (4U)
   #define USB_MAXPIPE_BULK                      (5U)
   #define USB_BULK_PIPE_START                   (4U)
   #define USB_INT_PIPE_END                      (7U)
   #define USB_MAX_PIPE_NO                       (7U) /* PIPE4 ... PIPE7 */
- #else
+ #else  /* defined(USB_MINI_MODULE_DMAC) || defined(USB_MINI_MODULE_NO_DMAC) */
   #define USB_MIN_PIPE_NO                       (1U)
   #define USB_MAXPIPE_BULK                      (5U)
   #define USB_BULK_PIPE_START                   (1U)
   #define USB_INT_PIPE_END                      (9U)
   #define USB_MAX_PIPE_NO                       (9U) /* PIPE0 ... PIPE9 */
- #endif
+ #endif /* defined(USB_MINI_MODULE_DMAC) || defined(USB_MINI_MODULE_NO_DMAC) */
 
  #define USB_MAXPIPE_NUM                        (9U)
  #define USB_INT_PIPE_START                     (6U)
diff --git a/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_cstd_rtos.h b/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_cstd_rtos.h
index 4f1d2ddfb..cf737b173 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_cstd_rtos.h
+++ b/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_cstd_rtos.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_extern.h b/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_extern.h
index bb23f3c63..6092a7082 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_extern.h
+++ b/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_extern.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_typedef.h b/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_typedef.h
index 77451f629..c57f4dc14 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_typedef.h
+++ b/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_typedef.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -245,17 +245,18 @@ typedef enum e_usb_class_internal
     USB_CLASS_INTERNAL_PHID2,          ///< PHID2 Class     5
     USB_CLASS_INTERNAL_PAUD,           ///< PAUD Class      6
     USB_CLASS_INTERNAL_PPRN,           ///< PPRN Class      7
-    USB_CLASS_INTERNAL_PVND,           ///< PVND Class      8
-    USB_CLASS_INTERNAL_HCDC,           ///< HCDC Class      9
-    USB_CLASS_INTERNAL_HCDCC,          ///< HCDCC Class     10
-    USB_CLASS_INTERNAL_HHID,           ///< HHID Class      11
-    USB_CLASS_INTERNAL_HVND,           ///< HVND Class      12
-    USB_CLASS_INTERNAL_HMSC,           ///< HMSC Class      13
-    USB_CLASS_INTERNAL_PMSC,           ///< PMSC Class      14
-    USB_CLASS_INTERNAL_HPRN,           ///< HPRN Class      15
-    USB_CLASS_INTERNAL_HUVC,           ///< HUVC Class      16
-    USB_CLASS_INTERNAL_REQUEST,        ///< USB Class Request      17
-    USB_CLASS_INTERNAL_END             ///< USB Class       18
+    USB_CLASS_INTERNAL_DFU,            ///< DFU Class       8
+    USB_CLASS_INTERNAL_PVND,           ///< PVND Class      9
+    USB_CLASS_INTERNAL_HCDC,           ///< HCDC Class      10
+    USB_CLASS_INTERNAL_HCDCC,          ///< HCDCC Class     11
+    USB_CLASS_INTERNAL_HHID,           ///< HHID Class      12
+    USB_CLASS_INTERNAL_HVND,           ///< HVND Class      13
+    USB_CLASS_INTERNAL_HMSC,           ///< HMSC Class      14
+    USB_CLASS_INTERNAL_PMSC,           ///< PMSC Class      15
+    USB_CLASS_INTERNAL_HPRN,           ///< HPRN Class      16
+    USB_CLASS_INTERNAL_HUVC,           ///< HUVC Class      17
+    USB_CLASS_INTERNAL_REQUEST,        ///< USB Class Request      18
+    USB_CLASS_INTERNAL_END,            ///< USB Class       19
 } usb_class_internal_t;
 
 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_cdataio.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_cdataio.c
index e49a54ec9..6d80a1c3e 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_cdataio.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_cdataio.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -202,6 +202,8 @@ static const uint8_t g_usb_pipe_peri[] =
  #else                                            /* defined(USB_CFG_PPRN_USE) */
     USB_NULL,               USB_NULL,
  #endif                                           /* defined(USB_CFG_PPRN_USE) */
+
+    USB_NULL,               USB_NULL,             /* USB_DFU (8) */
 };
 #endif  /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */
 
@@ -273,61 +275,64 @@ void (* g_usb_callback[])(usb_utr_t *, uint16_t, uint16_t) =
     USB_NULL, USB_NULL,                              /* USB_PPRN (7) */
 #endif /* defined(USB_CFG_PPRN_USE) */
 
+    /* DFU */
+    USB_NULL, USB_NULL,                              /* USB_DFU (8) */
+
     /* PVND */
-    USB_NULL, USB_NULL,                              /* USB_PVND (8) */
+    USB_NULL, USB_NULL,                              /* USB_PVND (9) */
 
     /* HCDC, HCDCC */
 #if defined(USB_CFG_HCDC_USE)
  #if (BSP_CFG_RTOS == 1)
-    USB_NULL, USB_NULL,                              /* USB_HCDC  (9) */
-    USB_NULL, USB_NULL,                              /* USB_HCDCC (10) */
+    USB_NULL, USB_NULL,                              /* USB_HCDC  (10) */
+    USB_NULL, USB_NULL,                              /* USB_HCDCC (11) */
  #else  /* #if (BSP_CFG_RTOS == 1) */
-    usb_hcdc_read_complete, usb_hcdc_write_complete, /* USB_HCDC  (9) */
-    usb_hcdc_read_complete, USB_NULL,                /* USB_HCDCC (10) */
+    usb_hcdc_read_complete, usb_hcdc_write_complete, /* USB_HCDC  (10) */
+    usb_hcdc_read_complete, USB_NULL,                /* USB_HCDCC (11) */
  #endif /* #if (BSP_CFG_RTOS == 1) */
 #else
-    USB_NULL, USB_NULL,                              /* USB_HCDC  (9) */
-    USB_NULL, USB_NULL,                              /* USB_HCDCC (10) */
+    USB_NULL, USB_NULL,                              /* USB_HCDC  (10) */
+    USB_NULL, USB_NULL,                              /* USB_HCDCC (11) */
 #endif
 
     /* HHID */
 #if defined(USB_CFG_HHID_USE)
  #if (BSP_CFG_RTOS == 1)
-    USB_NULL, USB_NULL,                              /* USB_HHID (11) */
+    USB_NULL, USB_NULL,                              /* USB_HHID (12) */
  #else                                               /* #if (BSP_CFG_RTOS == 1) */
-    usb_hhid_read_complete, usb_hhid_write_complete, /* USB_HHID  (11) */
+    usb_hhid_read_complete, usb_hhid_write_complete, /* USB_HHID  (12) */
  #endif /* #if (BSP_CFG_RTOS == 1) */
 #else
-    USB_NULL, USB_NULL,                              /* USB_HHID  (11) */
+    USB_NULL, USB_NULL,                              /* USB_HHID  (12) */
 #endif
 
     /* HVND */
 #if defined(USB_CFG_HVND_USE)
-    usb_hvnd_read_complete, usb_hvnd_write_complete, /* USB_HVND  (12) */
+    usb_hvnd_read_complete, usb_hvnd_write_complete, /* USB_HVND  (13) */
 #else
-    USB_NULL, USB_NULL,                              /* USB_HVND  (12) */
+    USB_NULL, USB_NULL,                              /* USB_HVND  (13) */
 #endif
 
     /* HMSC */
-    USB_NULL, USB_NULL,                              /* USB_HMSC  (13) */
+    USB_NULL, USB_NULL,                              /* USB_HMSC  (14) */
 
     /* PMSC */
-    USB_NULL, USB_NULL,                              /* USB_PMSC  (14) */
+    USB_NULL, USB_NULL,                              /* USB_PMSC  (15) */
 
     /* HPRN */
 #if defined(USB_CFG_HPRN_USE)
  #if (BSP_CFG_RTOS == 1)
-    USB_NULL, USB_NULL,                              /* USB_HPRN (15) */
+    USB_NULL, USB_NULL,                              /* USB_HPRN (16) */
  #else                                               /* #if (BSP_CFG_RTOS == 1) */
-    usb_hprn_read_complete, usb_hprn_write_complete, /* USB_HPRN (15) */
+    usb_hprn_read_complete, usb_hprn_write_complete, /* USB_HPRN (16) */
  #endif /* #if (BSP_CFG_RTOS == 1) */
 #else
-    USB_NULL, USB_NULL,                              /* USB_HPRN (15) */
+    USB_NULL, USB_NULL,                              /* USB_HPRN (16) */
 #endif
 
     /* HUVC */
 
-    USB_NULL, USB_NULL,                /* USB_HUVC (16) */
+    USB_NULL, USB_NULL,                /* USB_HUVC (17) */
 };                                     /* const void (g_usb_callback[])(usb_utr_t *, uint16_t, uint16_t) */
 
 #if defined(USB_CFG_PCDC_USE)
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_clibusbip.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_clibusbip.c
index 9701c2320..09c9e995b 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_clibusbip.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_clibusbip.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_cstd_rtos.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_cstd_rtos.c
index 30b01d282..e751e0ca5 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_cstd_rtos.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_cstd_rtos.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -730,8 +730,10 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode)
             }
         }
     }
-}
 
+  #if (USB_NUM_USBIP == 2)
+}
+  #endif                               /* (USB_NUM_USBIP == 2) */
  #elif (BSP_CFG_RTOS == 1)             /* Azure RTOS */
     uint32_t ret;
 
@@ -1049,10 +1051,9 @@ usb_rtos_err_t usb_rtos_configuration (usb_mode_t usb_mode)
     }
    #endif                              /* USB_NUM_USBIP == 2 */
   #endif                               /* defined (USB_CFG_OTG_USE) */
-
  #endif                                /* BSP_CFG_RTOS */
 
-return err;
+    return err;
 }                                      /* End of function usb_rtos_configuration() */
 
 /******************************************************************************
@@ -1241,8 +1242,10 @@ usb_rtos_err_t usb_rtos_delete (uint8_t module_number)
             vQueueDelete(g_pipe_hdl[ip_loop][pipe_loop]);
         }
     }
-}
 
+  #if (USB_NUM_USBIP == 2)
+}
+  #endif                               /* (USB_NUM_USBIP == 2) */
  #elif (BSP_CFG_RTOS == 1)             /* Azure RTOS */
     uint32_t ret;
 
@@ -1497,10 +1500,9 @@ usb_rtos_err_t usb_rtos_delete (uint8_t module_number)
         return err;
     }
   #endif                               /* defined (USB_CFG_OTG_USE) */
-
  #endif                                /* BSP_CFG_RTOS */
 
-return err;
+    return err;
 }                                      /* End of function usb_rtos_delete() */
 
 /******************************************************************************
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hbc.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hbc.c
index c4e156b86..ddb5055c0 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hbc.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hbc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hcontrolrw.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hcontrolrw.c
index cc557fbc1..c0ab6b8c3 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hcontrolrw.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hcontrolrw.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hdriver.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hdriver.c
index bed87114f..3d24dfc7b 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hdriver.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hdriver.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -1064,10 +1064,13 @@ static void usb_hstd_interrupt (usb_utr_t * ptr)
                     {
                         tx_timer_activate(&g_usb_otg_detach_timer);
                     }
+
+  #if USB_NUM_USBIP == 2
                     else
                     {
                         tx_timer_activate(&g_usb2_otg_detach_timer);
                     }
+  #endif                               /* USB_NUM_USBIP == 2 */
                 }
 
                 g_usb_otg_hnp_process[ptr->ip] = USB_OFF;
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hhubsys.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hhubsys.c
index 68b14c7f7..991b6fb99 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hhubsys.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hhubsys.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hintfifo.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hintfifo.c
index 7842732e2..6a69112d5 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hintfifo.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hintfifo.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hinthandler_usbip0.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hinthandler_usbip0.c
index 8db30a163..9336230bf 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hinthandler_usbip0.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hinthandler_usbip0.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hinthandler_usbip1.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hinthandler_usbip1.c
index 9e4747147..a03ae25b9 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hinthandler_usbip1.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hinthandler_usbip1.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hlibusbip.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hlibusbip.c
index 2a38ded99..763503f7a 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hlibusbip.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hlibusbip.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hmanager.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hmanager.c
index c26d8aabc..84a8fd86e 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hmanager.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hmanager.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hscheduler.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hscheduler.c
index 9e4ba71ec..663e78cdf 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hscheduler.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hscheduler.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hsignal.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hsignal.c
index 85dc8352c..536533514 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hsignal.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hsignal.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hstdfunction.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hstdfunction.c
index 590c41bcd..5c840db66 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hstdfunction.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hstdfunction.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_pbc.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_pbc.c
index 3a6015b01..2bf71392a 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_pbc.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_pbc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_pcontrolrw.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_pcontrolrw.c
index b95c4a284..d0aa70219 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_pcontrolrw.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_pcontrolrw.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_pdriver.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_pdriver.c
index de86b18d1..f2cb06198 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_pdriver.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_pdriver.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -511,11 +511,13 @@ static void usb_pstd_interrupt (usb_utr_t * p_mess)
                         {
                             tx_timer_deactivate(&g_usb_otg_detach_timer);
                         }
+
+   #if USB_NUM_USBIP == 2
                         else
                         {
                             tx_timer_deactivate(&g_usb2_otg_detach_timer);
                         }
-
+   #endif                              /* USB_NUM_USBIP == 2 */
                         _ux_system_otg->ux_system_otg_device_type = UX_OTG_DEVICE_A;
                         (*g_p_otg_callback[p_mess->ip])(UX_OTG_MODE_HOST);
                     }
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_pintfifo.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_pintfifo.c
index 02fe662a6..ff8b83e31 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_pintfifo.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_pintfifo.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_pinthandler_usbip0.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_pinthandler_usbip0.c
index 06d4f565f..95ff2cd77 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_pinthandler_usbip0.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_pinthandler_usbip0.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_plibusbip.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_plibusbip.c
index bc3269794..502c87534 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_plibusbip.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_plibusbip.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_psignal.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_psignal.c
index 05a29e274..bb0657fa3 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_psignal.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_psignal.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_pstdfunction.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_pstdfunction.c
index 948c84c09..9a28cec5e 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_pstdfunction.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_pstdfunction.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_pstdrequest.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_pstdrequest.c
index 9f38c6926..17291b3e8 100644
--- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_pstdrequest.c
+++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_pstdrequest.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -50,11 +50,11 @@
 #define FSP_SETUP_REQUEST          (1)
 #define FSP_SETUP_VALUE            (2)
 #define FSP_SETUP_LENGTH           (6)
-#if defined(USB_CFG_PAUD_USE)
+#if defined(USB_CFG_PAUD_USE) || defined(USB_CFG_DFU_USE)
  #define FSP_SETUP_REQUEST_TYPE    (0)
  #define FSP_SETUP_INDEX_L         (4)
  #define FSP_SETUP_INDEX_H         (5)
-#endif                                 /* #if defined(USB_CFG_PAUD_USE) */
+#endif                                 /* #if defined(USB_CFG_PAUD_USE) || defined(USB_CFG_DFU_USE)*/
 
 /******************************************************************************
  * Exported global variables (to be accessed by other files)
@@ -1564,9 +1564,9 @@ static void usb_pstd_set_interface3 (usb_utr_t * p_utr)
 
                 /* Search endpoint setting */
                 usb_pstd_set_eptbl_index(g_usb_pstd_req_index, g_usb_pstd_alt_num[g_usb_pstd_req_index]);
-  #ifndef USB_CFG_PAUD_USE
+  #if !defined(USB_CFG_PAUD_USE) && !defined(USB_CFG_DFU_USE)
                 usb_pstd_set_pipe_reg(p_utr);
-  #endif                               /* USB_CFG_PAUD_USE */
+  #endif                               /* #if !defined(USB_CFG_PAUD_USE) && !defined(USB_CFG_DFU_USE) */
   #if BSP_CFG_RTOS == 1
    #ifdef  USB_CFG_PAUD_USE
                 if (0 == (g_usb_pstd_req_value & USB_ALT_SET))
@@ -1673,14 +1673,14 @@ static void usb_peri_class_request_usbx (usb_setup_t * p_req)
                                FSP_SETUP_VALUE) = p_req->request_value;
                 *(uint16_t *) (transfer_request->ux_slave_transfer_request_setup +
                                FSP_SETUP_LENGTH) = p_req->request_length;
-  #if defined(USB_CFG_PAUD_USE)
+  #if defined(USB_CFG_PAUD_USE) || defined(USB_CFG_DFU_USE)
                 *(transfer_request->ux_slave_transfer_request_setup +
                   FSP_SETUP_REQUEST_TYPE) = (uint8_t) (p_req->request_type & VALUE_FFH);
                 *(transfer_request->ux_slave_transfer_request_setup +
                   FSP_SETUP_INDEX_L) = (uint8_t) (p_req->request_index & VALUE_FFH);
                 *(transfer_request->ux_slave_transfer_request_setup +
                   FSP_SETUP_INDEX_H) = (uint8_t) (p_req->request_index >> 8);
-  #endif                               /* #if defined(USB_CFG_PAUD_USE) */
+  #endif                               /* #if defined(USB_CFG_PAUD_USE) || defined(USB_CFG_DFU_USE)*/
                 class_command.ux_slave_class_command_class_ptr = class;
                 status = class->ux_slave_class_entry_function(&class_command);
                 if (status == UX_SUCCESS)
@@ -2056,9 +2056,9 @@ void usb_peri_class_request_wss (usb_setup_t * req, usb_utr_t * p_utr)
 
     usb_pstd_ctrl_end((uint16_t) USB_CTRL_END, p_utr);
  #if (BSP_CFG_RTOS == 1)
-  #if defined(USB_CFG_PAUD_USE)
+  #if defined(USB_CFG_PAUD_USE) || defined(USB_CFG_DFU_USE)
     usb_peri_usbx_set_control_length(req);
-  #endif                               /* #if defined(USB_CFG_PAUD_USE) */
+  #endif                               /* #if defined(USB_CFG_PAUD_USE) || defined(USB_CFG_DFU_USE)*/
     usb_peri_class_request_usbx(req);
  #endif                                /* #if (BSP_CFG_RTOS == 1) */
 }                                      /* End of function usb_peri_class_request_wss */
diff --git a/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h b/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h
index 5eb253f06..76675e9f9 100644
--- a/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h
+++ b/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_dmac.h b/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_dmac.h
index 720213f66..db7f2d56c 100644
--- a/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_dmac.h
+++ b/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_dmac.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_reg_access.h b/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_reg_access.h
index 4ce2a9c43..5539786be 100644
--- a/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_reg_access.h
+++ b/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_reg_access.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_abs.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_abs.c
index 9227ce88d..2d7fe0ea1 100644
--- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_abs.c
+++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_abs.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_access.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_access.c
index c1100da6d..34992ea4e 100644
--- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_access.c
+++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_access.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -2091,11 +2091,14 @@ void hw_usb_set_bempenb (usb_utr_t * ptr, uint16_t pipeno)
             g_usb_cstd_bemp_skip[USB_IP0][pipeno] = USB_OFF;
             USB_M0->BEMPENB = (uint16_t) (USB_M0->BEMPENB | (1 << pipeno));
         }
+
+ #if USB_NUM_USBIP == 2
         else
         {
             g_usb_cstd_bemp_skip[USB_IP1][pipeno] = USB_OFF;
             USB_M1->BEMPENB = (uint16_t) (USB_M1->BEMPENB | (1 << pipeno));
         }
+ #endif                                /* USB_NUM_USBIP == 2 */
 #endif                                 /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */
     }
     else
diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_dma.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_dma.c
index 82c97d4eb..2086ba065 100644
--- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_dma.c
+++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_dma.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -595,16 +595,19 @@ void usb_cstd_dma_send_continue (usb_utr_t * ptr, uint16_t useport)
                     g_usb_cstd_dma_fraction_size[ip][channel] = g_usb_cstd_dma_size[ip][channel] & USB_BIT_MBW16; /* fraction size(1-3) */
                     dma_size = (uint16_t) (dma_size & ~USB_BIT_MBW16);
                 }
+
+ #if USB_NUM_USBIP == 2
                 else
                 {
- #if defined(USB_HIGH_SPEED_MODULE)
+  #if defined(USB_HIGH_SPEED_MODULE)
                     g_usb_cstd_dma_fraction_size[ip][channel] = g_usb_cstd_dma_size[ip][channel] & USB_BIT_MBW32; /* fraction size(1-3) */
                     dma_size = (uint16_t) (dma_size & ~USB_BIT_MBW32);
- #else                                                                                                            /* defined (USB_HIGH_SPEED_MODULE) */
+  #else                                                                                                           /* defined (USB_HIGH_SPEED_MODULE) */
                     g_usb_cstd_dma_fraction_size[ip][channel] = g_usb_cstd_dma_size[ip][channel] & USB_BIT_MBW16; /* fraction size(1-3) */
                     dma_size = (uint16_t) (dma_size & ~USB_BIT_MBW16);
- #endif                                                                                                           /* defined (USB_HIGH_SPEED_MODULE) */
+  #endif                                                                                                          /* defined (USB_HIGH_SPEED_MODULE) */
                 }
+ #endif /* USB_NUM_USBIP == 2 */
 
                 g_usb_cstd_dma_fraction_adr[ip][channel] = (uint32_t) (p_src_adr + dma_size);                     /* fraction data address */
 
@@ -871,7 +874,11 @@ void usb_cstd_dma_send_complete (uint8_t ip_no, uint16_t use_port)
     }
 
  #if (BSP_CFG_RTOS != 0)
+  #if USB_NUM_USBIP == 2
     if (USB_MODE_HOST == g_usb_usbmode[ip_no])
+  #else                                /* USB_NUM_USBIP == 2 */
+    if (USB_MODE_HOST == g_usb_usbmode[0])
+  #endif /* USB_NUM_USBIP == 2 */
     {
   #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST)
         utr.ip  = ip_no;
@@ -917,7 +924,11 @@ void usb_cstd_dma_send_complete (uint8_t ip_no, uint16_t use_port)
     gs_usb_cstd_dma_int.buf[gs_usb_cstd_dma_int.wp].p_cfg = p_cfg;
 
     utr.ip = ip_no;
+  #if USB_NUM_USBIP == 2
     if (USB_MODE_HOST == g_usb_usbmode[utr.ip])
+  #else                                /* USB_NUM_USBIP == 2 */
+    if (USB_MODE_HOST == g_usb_usbmode[0])
+  #endif /* USB_NUM_USBIP == 2 */
     {
   #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST)
         utr.ipp = usb_hstd_get_usb_ip_adr(utr.ip);
diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_hostelectrical.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_hostelectrical.c
index fcf6460aa..d9b89acb5 100644
--- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_hostelectrical.c
+++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_hostelectrical.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_abs.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_abs.c
index 73d758e80..cea69ced1 100644
--- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_abs.c
+++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_abs.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_access.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_access.c
index 06e0f1263..43ef5caa6 100644
--- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_access.c
+++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_access.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -759,9 +759,9 @@ void hw_usb_hmodule_init (uint8_t usb_ip)
             /* none */
         }
 
- #if defined(USB_HIGH_SPEED_MODULE)
-        USB_M0->PHYSLEW = 0x5;
- #endif                                /* defined (USB_HIGH_SPEED_MODULE) */
+ #if defined(USB_SUPPORT_PHYSLEW)
+        USB_M0->PHYSLEW = USB_PHYSLEW_VALUE;
+ #endif                                /* defined(USB_SUPPORT_PHYSLEW) */
 
         USB_M0->SYSCFG |= USB_DCFM;
 
diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_mcu.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_mcu.c
index 504607b5f..7a8354aa0 100644
--- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_mcu.c
+++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_mcu.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_abs.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_abs.c
index 78b5b2540..bc3448f49 100644
--- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_abs.c
+++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_abs.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_access.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_access.c
index 0a6988a36..e4cb08fac 100644
--- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_access.c
+++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_access.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -230,9 +230,9 @@ void hw_usb_pmodule_init (uint8_t usb_ip)
             /* Wait for Set of SCKE */
         }
 
- #if defined(USB_HIGH_SPEED_MODULE)
-        USB_M0->PHYSLEW = 0x5;
- #endif                                /* defined (USB_HIGH_SPEED_MODULE) */
+ #if defined(USB_SUPPORT_PHYSLEW)
+        USB_M0->PHYSLEW = USB_PHYSLEW_VALUE;
+ #endif                                /* defined(USB_SUPPORT_PHYSLEW) */
 
         USB_M0->SYSCFG &= (uint16_t) (~USB_DRPD);
 
diff --git a/ra/fsp/src/r_usb_hcdc/src/inc/r_usb_hcdc.h b/ra/fsp/src/r_usb_hcdc/src/inc/r_usb_hcdc.h
index f7a38a4b5..1ec4780e7 100644
--- a/ra/fsp/src/r_usb_hcdc/src/inc/r_usb_hcdc.h
+++ b/ra/fsp/src/r_usb_hcdc/src/inc/r_usb_hcdc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_hcdc/src/r_usb_hcdc_driver.c b/ra/fsp/src/r_usb_hcdc/src/r_usb_hcdc_driver.c
index fd8240414..5500e881d 100644
--- a/ra/fsp/src/r_usb_hcdc/src/r_usb_hcdc_driver.c
+++ b/ra/fsp/src/r_usb_hcdc/src/r_usb_hcdc_driver.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_hhid/r_usb_hhid.c b/ra/fsp/src/r_usb_hhid/r_usb_hhid.c
index c691da936..fa4438f16 100644
--- a/ra/fsp/src/r_usb_hhid/r_usb_hhid.c
+++ b/ra/fsp/src/r_usb_hhid/r_usb_hhid.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_hhid/src/inc/r_usb_hhid_driver.h b/ra/fsp/src/r_usb_hhid/src/inc/r_usb_hhid_driver.h
index 3de292113..6c3a24d4f 100644
--- a/ra/fsp/src/r_usb_hhid/src/inc/r_usb_hhid_driver.h
+++ b/ra/fsp/src/r_usb_hhid/src/inc/r_usb_hhid_driver.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_hhid/src/r_usb_hhid_driver.c b/ra/fsp/src/r_usb_hhid/src/r_usb_hhid_driver.c
index beb42f53f..81e66c930 100644
--- a/ra/fsp/src/r_usb_hhid/src/r_usb_hhid_driver.c
+++ b/ra/fsp/src/r_usb_hhid/src/r_usb_hhid_driver.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_hmsc/r_usb_hmsc.c b/ra/fsp/src/r_usb_hmsc/r_usb_hmsc.c
index 65c7187fd..da9c555c3 100644
--- a/ra/fsp/src/r_usb_hmsc/r_usb_hmsc.c
+++ b/ra/fsp/src/r_usb_hmsc/r_usb_hmsc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_hmsc/src/inc/r_usb_hmsc_driver.h b/ra/fsp/src/r_usb_hmsc/src/inc/r_usb_hmsc_driver.h
index 46eec033a..256bf23b8 100644
--- a/ra/fsp/src/r_usb_hmsc/src/inc/r_usb_hmsc_driver.h
+++ b/ra/fsp/src/r_usb_hmsc/src/inc/r_usb_hmsc_driver.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_hmsc/src/r_usb_hmsc_driver.c b/ra/fsp/src/r_usb_hmsc/src/r_usb_hmsc_driver.c
index abc6bd8b8..89c04168b 100644
--- a/ra/fsp/src/r_usb_hmsc/src/r_usb_hmsc_driver.c
+++ b/ra/fsp/src/r_usb_hmsc/src/r_usb_hmsc_driver.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_hmsc/src/r_usb_hstorage_driver.c b/ra/fsp/src/r_usb_hmsc/src/r_usb_hstorage_driver.c
index 9b2766282..ab8336a12 100644
--- a/ra/fsp/src/r_usb_hmsc/src/r_usb_hstorage_driver.c
+++ b/ra/fsp/src/r_usb_hmsc/src/r_usb_hstorage_driver.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_pcdc/src/inc/r_usb_pcdc.h b/ra/fsp/src/r_usb_pcdc/src/inc/r_usb_pcdc.h
index 6a84d85aa..c3ad7217f 100644
--- a/ra/fsp/src/r_usb_pcdc/src/inc/r_usb_pcdc.h
+++ b/ra/fsp/src/r_usb_pcdc/src/inc/r_usb_pcdc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_pcdc/src/r_usb_pcdc_driver.c b/ra/fsp/src/r_usb_pcdc/src/r_usb_pcdc_driver.c
index dfee37ee5..9f80e9226 100644
--- a/ra/fsp/src/r_usb_pcdc/src/r_usb_pcdc_driver.c
+++ b/ra/fsp/src/r_usb_pcdc/src/r_usb_pcdc_driver.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_pmsc/src/inc/r_usb_patapi.h b/ra/fsp/src/r_usb_pmsc/src/inc/r_usb_patapi.h
index a498dcc45..74adbca0b 100644
--- a/ra/fsp/src/r_usb_pmsc/src/inc/r_usb_patapi.h
+++ b/ra/fsp/src/r_usb_pmsc/src/inc/r_usb_patapi.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_pmsc/src/inc/r_usb_pmsc.h b/ra/fsp/src/r_usb_pmsc/src/inc/r_usb_pmsc.h
index 396373ae8..f0bf61e86 100644
--- a/ra/fsp/src/r_usb_pmsc/src/inc/r_usb_pmsc.h
+++ b/ra/fsp/src/r_usb_pmsc/src/inc/r_usb_pmsc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_pmsc/src/inc/r_usb_pmsc_driver.h b/ra/fsp/src/r_usb_pmsc/src/inc/r_usb_pmsc_driver.h
index 5b5e9267d..5d89ae82c 100644
--- a/ra/fsp/src/r_usb_pmsc/src/inc/r_usb_pmsc_driver.h
+++ b/ra/fsp/src/r_usb_pmsc/src/inc/r_usb_pmsc_driver.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_pmsc/src/r_media_driver_api.c b/ra/fsp/src/r_usb_pmsc/src/r_media_driver_api.c
index 7a0556dce..4fac2a537 100644
--- a/ra/fsp/src/r_usb_pmsc/src/r_media_driver_api.c
+++ b/ra/fsp/src/r_usb_pmsc/src/r_media_driver_api.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_pmsc/src/r_usb_atapi_driver.c b/ra/fsp/src/r_usb_pmsc/src/r_usb_atapi_driver.c
index eca616d82..76849c829 100644
--- a/ra/fsp/src/r_usb_pmsc/src/r_usb_atapi_driver.c
+++ b/ra/fsp/src/r_usb_pmsc/src/r_usb_atapi_driver.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_pmsc/src/r_usb_pmsc_driver.c b/ra/fsp/src/r_usb_pmsc/src/r_usb_pmsc_driver.c
index 842488d47..88f959cf5 100644
--- a/ra/fsp/src/r_usb_pmsc/src/r_usb_pmsc_driver.c
+++ b/ra/fsp/src/r_usb_pmsc/src/r_usb_pmsc_driver.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_pprn/src/inc/r_usb_pprn.h b/ra/fsp/src/r_usb_pprn/src/inc/r_usb_pprn.h
index 039292d1d..6d279b45b 100644
--- a/ra/fsp/src/r_usb_pprn/src/inc/r_usb_pprn.h
+++ b/ra/fsp/src/r_usb_pprn/src/inc/r_usb_pprn.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_usb_pprn/src/r_usb_pprn_driver.c b/ra/fsp/src/r_usb_pprn/src/r_usb_pprn_driver.c
index 7a07af611..38e5ef442 100644
--- a/ra/fsp/src/r_usb_pprn/src/r_usb_pprn_driver.c
+++ b/ra/fsp/src/r_usb_pprn/src/r_usb_pprn_driver.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/r_wdt/r_wdt.c b/ra/fsp/src/r_wdt/r_wdt.c
index 08d560639..4434b21ae 100644
--- a/ra/fsp/src/r_wdt/r_wdt.c
+++ b/ra/fsp/src/r_wdt/r_wdt.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_adpcm_decoder/rm_adpcm_decoder.c b/ra/fsp/src/rm_adpcm_decoder/rm_adpcm_decoder.c
index 93df70d90..5e01d1009 100644
--- a/ra/fsp/src/rm_adpcm_decoder/rm_adpcm_decoder.c
+++ b/ra/fsp/src/rm_adpcm_decoder/rm_adpcm_decoder.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_audio_playback_pwm/rm_audio_playback_pwm.c b/ra/fsp/src/rm_audio_playback_pwm/rm_audio_playback_pwm.c
index 25504486e..6c5af53df 100644
--- a/ra/fsp/src/rm_audio_playback_pwm/rm_audio_playback_pwm.c
+++ b/ra/fsp/src/rm_audio_playback_pwm/rm_audio_playback_pwm.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_bl2_port/tfm_common_config.h b/ra/fsp/src/rm_bl2_port/tfm_common_config.h
index e3792f1ed..b771362c7 100644
--- a/ra/fsp/src/rm_bl2_port/tfm_common_config.h
+++ b/ra/fsp/src/rm_bl2_port/tfm_common_config.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_ble_abs/rm_ble_abs.c b/ra/fsp/src/rm_ble_abs/rm_ble_abs.c
index 36acf5955..07a389f31 100644
--- a/ra/fsp/src/rm_ble_abs/rm_ble_abs.c
+++ b/ra/fsp/src/rm_ble_abs/rm_ble_abs.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_ble_abs_gtl/rm_ble_abs_gtl.c b/ra/fsp/src/rm_ble_abs_gtl/rm_ble_abs_gtl.c
new file mode 100644
index 000000000..24e688ac1
--- /dev/null
+++ b/ra/fsp/src/rm_ble_abs_gtl/rm_ble_abs_gtl.c
@@ -0,0 +1,1254 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+#include <rm_ble_abs.h>
+#include <rm_ble_abs_api.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include "fsp_common_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* "BLE_ABS" in ASCII, used to determine if module is open. */
+#define BLE_ABS_OPEN    (0X00424C45ULL)
+
+/* Advertising handles */
+typedef enum e_ble_abs_handle_type
+{
+    BLE_ABS_LEGACY_HDL   = 0x00,       // Advertising Handle for Legacy Advertising
+    BLE_ABS_NON_CONN_HDL = 0x02,       // Advertising Handle for Non-Connectable Advertising
+} ble_abs_handle_type_t;
+
+/* Advertising status */
+typedef enum e_ble_abs_adv_status
+{
+    BLE_ABS_ADV_STATUS_PARAM_FAST     = 0x00000001, // Set fast advertising parameters
+    BLE_ABS_ADV_STATUS_PARAM_SLOW     = 0x00000002, // Set slow advertising parameters
+    BLE_ABS_ADV_STATUS_ADV_DATA       = 0x00000010, // Set advertising data
+    BLE_ABS_ADV_STATUS_SRES_DATA      = 0x00000020, // Set scan response data
+    BLE_ABS_ADV_STATUS_PERD_DATA      = 0x00000040, // Set periodic advertising data
+    BLE_ABS_ADV_STATUS_ADV_FAST_START = 0x00000100, // Start fast advertising
+    BLE_ABS_ADV_STATUS_ADV_SLOW_START = 0x00000200, // Start slow advertising
+    BLE_ABS_ADV_STATUS_PERD_PARAM     = 0x00001000, // Set periodic advertising parameters
+    BLE_ABS_ADV_STATUS_PERD_START     = 0x00010000, // Start periodic advertising
+} ble_abs_adv_status_t;
+
+/* Scan status */
+typedef enum e_ble_abs_scan_status
+{
+    BLE_ABS_SCAN_STATUS_FAST_START = 0x00000001, // Start fast scan
+    BLE_ABS_SCAN_STATUS_SLOW_START = 0x00000002, // Start slow scan
+} ble_abs_scan_status_t;
+
+/* Privacy status */
+typedef enum e_ble_abs_pv_status
+{
+    BLE_ABS_PV_STATUS_CREATE_IRK = 0x00000001, // Create irk
+    BLE_ABS_PV_STATUS_ADD_RSLV   = 0x00000002, // Add irk to resolving list
+    BLE_ABS_PV_STATUS_SET_MODE   = 0x00000004, // Set privacy mode
+    BLE_ABS_PV_STATUS_EN_RPA     = 0x00000008, // Enable resolvable private address function
+} ble_abs_pv_status_t;
+
+/*********************************/
+/* Define for create connection  */
+/*********************************/
+
+/* Minimum advertising data length */
+#define BLE_ABS_LEGACY_ADV_DATA_LEN    (31)
+
+/* The invalid timer handle. */
+#define BLE_TIMER_INVALID_HDL          (0xFF)
+
+/***********************************************************************************************************************
+ * Local Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_convert_legacy_advertising_parameter(
+    ble_abs_legacy_advertising_parameter_t * p_legacy_advertising_parameter,
+    st_ble_gap_adv_param_t                 * p_gap_advertising_parameter);
+
+static fsp_err_t ble_abs_advertising_report_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                                    st_ble_evt_data_t             * p_event_data);
+
+static void ble_abs_gap_callback(uint16_t event_type, ble_status_t event_result, st_ble_evt_data_t * p_event_data);
+static void ble_abs_set_abs_callback(ble_abs_instance_ctrl_t * const            p_instance_ctrl,
+                                     ble_gap_application_callback_t             gap_callback,
+                                     ble_vendor_specific_application_callback_t vendor_specific_callback);
+static void ble_abs_set_advertising_status(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                           uint8_t                         advertising_handle,
+                                           uint32_t                        set,
+                                           uint32_t                        clear);
+static void ble_abs_set_advertising_parameter(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                              void                          * p_advertising_parameter,
+                                              uint8_t                         advertising_handle);
+
+static void ble_abs_update_data_status(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                       uint32_t                        advertising_status,
+                                       uint8_t                       * p_advertising_data,
+                                       uint16_t                        advertising_data_len,
+                                       uint8_t                         advertising_handle);
+
+static void ble_abs_advertising_parameter_set_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                                      st_ble_evt_data_t             * p_event_data);
+static void ble_abs_advertising_data_set_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                                 st_ble_evt_data_t             * p_event_data);
+
+static void ble_abs_advertising_start(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint8_t advertising_handle);
+static void ble_abs_advertising_set_data(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                         uint8_t                         advertising_handle,
+                                         uint8_t                         data_type);
+static void ble_abs_set_legacy_scan_response_data(ble_abs_instance_ctrl_t * const p_instance_ctrl);
+
+static void ble_abs_set_connection_advertising_interval(st_ble_gap_adv_param_t * p_advertising_parameter,
+                                                        uint32_t                 fast_advertising_interval,
+                                                        uint32_t                 slow_advertising_interval,
+                                                        uint16_t                 fast_period);
+
+/* BLE ABS on BLE HAL API mapping for BLE ABS interface */
+const ble_abs_api_t g_ble_abs_on_ble =
+{
+    .open  = RM_BLE_ABS_Open,
+    .close = RM_BLE_ABS_Close,
+    .reset = RM_BLE_ABS_Reset,
+    .startLegacyAdvertising         = RM_BLE_ABS_StartLegacyAdvertising,
+    .startExtendedAdvertising       = RM_BLE_ABS_StartExtendedAdvertising,
+    .startNonConnectableAdvertising = RM_BLE_ABS_StartNonConnectableAdvertising,
+    .startPeriodicAdvertising       = RM_BLE_ABS_StartPeriodicAdvertising,
+    .startScanning         = RM_BLE_ABS_StartScanning,
+    .createConnection      = RM_BLE_ABS_CreateConnection,
+    .setLocalPrivacy       = RM_BLE_ABS_SetLocalPrivacy,
+    .startAuthentication   = RM_BLE_ABS_StartAuthentication,
+    .deleteBondInformation = RM_BLE_ABS_DeleteBondInformation,
+};
+
+ble_abs_instance_ctrl_t * gp_instance_ctrl;
+
+/***********************************************************************************************************************
+ * Exported global functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Host stack is initialized with this function. Before using All the R_BLE APIs,
+ * it's necessary to call this function. A callback functions are registered with this function.
+ * In order to receive the GAP, GATT, Vendor specific event,
+ * it's necessary to register a callback function.
+ * The result of this API call is notified in BLE_GAP_EVENT_STACK_ON event.
+ * Implements @ref ble_abs_api_t::open.
+ *
+ * Example:
+ * @snippet rm_ble_abs_gtl_example.c RM_BLE_ABS_Open
+ *
+ * @retval FSP_SUCCESS                                 Channel opened successfully.
+ * @retval FSP_ERR_ASSERTION                           Null pointer presented.
+ * @retval FSP_ERR_ALREADY_OPEN                        Requested channel is already open in a different configuration.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    Invalid input parameter.
+ * @retval FSP_ERR_INVALID_MODE                        Invalid mode during open call
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_Open (ble_abs_ctrl_t * const p_ctrl, ble_abs_cfg_t const * const p_cfg)
+{
+    int32_t      i;
+    ble_status_t ble_status = BLE_SUCCESS;
+
+    ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+    /* Parameter checking */
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ASSERT(p_cfg);
+    FSP_ASSERT(p_cfg->gap_callback);
+#endif
+
+    FSP_ERROR_RETURN(BLE_ABS_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
+
+    gp_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+    p_instance_ctrl->abs_gap_callback             = NULL;
+    p_instance_ctrl->abs_vendor_specific_callback = NULL;
+    p_instance_ctrl->privacy_mode                 = BLE_GAP_NET_PRIV_MODE;
+    p_instance_ctrl->set_privacy_status           = 0;
+    p_instance_ctrl->p_cfg = p_cfg;
+
+    ble_status = R_BLE_Open();
+    FSP_ERROR_RETURN(BLE_SUCCESS == ble_status, FSP_ERR_INVALID_MODE);
+
+    ble_abs_set_abs_callback(p_instance_ctrl, p_cfg->gap_callback, p_cfg->vendor_specific_callback);
+
+    FSP_ERROR_RETURN(BLE_SUCCESS == R_BLE_VS_Init(p_instance_ctrl->abs_vendor_specific_callback),
+                     FSP_ERR_INVALID_ARGUMENT);
+
+    /* Initialize GAP layer */
+    ble_status = R_BLE_GAP_Init(ble_abs_gap_callback);
+    FSP_ERROR_RETURN(BLE_SUCCESS == ble_status, FSP_ERR_INVALID_ARGUMENT);
+
+    p_instance_ctrl->advertising_sets[0].advertising_status = 0;
+
+    p_instance_ctrl->abs_scan.scan_status    = 0;
+    p_instance_ctrl->connection_timer_handle = BLE_TIMER_INVALID_HDL;
+    p_instance_ctrl->set_privacy_status      = 0;
+
+    if ((0 < p_cfg->gatt_server_callback_list_number) && (NULL != p_cfg->p_gatt_server_callback_list))
+    {
+        FSP_ERROR_RETURN(BLE_SUCCESS == R_BLE_GATTS_Init(p_cfg->gatt_server_callback_list_number),
+                         FSP_ERR_INVALID_ARGUMENT);
+
+        for (i = 0; i < p_cfg->gatt_server_callback_list_number; i++)
+        {
+            if (NULL != p_cfg->p_gatt_server_callback_list[i].gatt_server_callback_function)
+            {
+                FSP_ERROR_RETURN(BLE_SUCCESS ==
+                                 R_BLE_GATTS_RegisterCb(p_cfg->p_gatt_server_callback_list[i].
+                                                        gatt_server_callback_function,
+                                                        p_cfg->p_gatt_server_callback_list[i].
+                                                        gatt_server_callback_priority),
+                                 FSP_ERR_INVALID_ARGUMENT);
+            }
+            else
+            {
+                break;
+            }
+        }
+    }
+
+    if ((0 < p_cfg->gatt_client_callback_list_number) && (NULL != p_cfg->p_gatt_client_callback_list))
+    {
+        FSP_ERROR_RETURN(BLE_SUCCESS == R_BLE_GATTC_Init(p_cfg->gatt_client_callback_list_number),
+                         FSP_ERR_INVALID_ARGUMENT);
+
+        for (i = 0; i < p_cfg->gatt_client_callback_list_number; i++)
+        {
+            ble_abs_gatt_client_callback_set_t   * p_cb_list = &(p_cfg->p_gatt_client_callback_list[i]);
+            ble_gatt_client_application_callback_t callback  = p_cb_list->gatt_client_callback_function;
+
+            if (NULL != callback)
+            {
+                FSP_ERROR_RETURN(BLE_SUCCESS ==
+                                 R_BLE_GATTC_RegisterCb(callback, p_cb_list->gatt_client_callback_priority),
+                                 FSP_ERR_INVALID_ARGUMENT);
+            }
+            else
+            {
+                break;
+            }
+        }
+    }
+
+    p_instance_ctrl->open = BLE_ABS_OPEN;
+
+    return FSP_SUCCESS;
+}                                      /* End of function RM_BLE_ABS_Open() */
+
+/*******************************************************************************************************************//**
+ * @brief Close the BLE channel.
+ * Implements @ref ble_abs_api_t::close.
+ *
+ * Example:
+ * @snippet rm_ble_abs_gtl_example.c RM_BLE_ABS_Close
+ *
+ * @retval  FSP_SUCCESS              Channel closed successfully.
+ * @retval  FSP_ERR_ASSERTION        Null pointer presented.
+ * @retval  FSP_ERR_NOT_OPEN         Control block not open.
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_Close (ble_abs_ctrl_t * const p_ctrl)
+{
+    ble_abs_instance_ctrl_t * p_ble_abs_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_ble_abs_ctrl);
+#endif
+    FSP_ERROR_RETURN(BLE_ABS_OPEN == p_ble_abs_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    R_BLE_Close();
+
+    p_ble_abs_ctrl->open = 0;
+
+    return FSP_SUCCESS;
+}                                      /* End of function RM_BLE_ABS_Close() */
+
+/*******************************************************************************************************************//**
+ * This function is not implemented. To perform this function call R_BLE_Close followed by R_BLE_Open.
+ * Implements @ref ble_abs_api_t::reset.
+ *
+ * @retval  FSP_ERR_UNSUPPORTED     Function is not supported
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_Reset (ble_abs_ctrl_t * const p_ctrl, ble_event_cb_t init_callback)
+{
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+    FSP_PARAMETER_NOT_USED(init_callback);
+
+    return FSP_ERR_UNSUPPORTED;
+}
+
+/*******************************************************************************************************************//**
+ * Start Legacy Advertising after setting advertising parameters, advertising data and scan response data.
+ * The legacy advertising uses the advertising set whose advertising handle is 0.
+ * The advertising type is connectable and scannable(ADV_IND).
+ * The address type of local device is Public Identity Address or
+ * RPA(If the resolving list contains no matching entry, use the public address.).
+ * Scan request event(BLE_GAP_EVENT_SCAN_REQ_RECV) is not notified.
+ * Implements @ref ble_abs_api_t::startLegacyAdvertising
+ *
+ * Example:
+ * @snippet rm_ble_abs_gtl_example.c RM_BLE_ABS_StartLegacyAdvertising
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded
+ * @retval FSP_ERR_ASSERTION                           p_instance_ctrl is specified as NULL.
+ * @retval FSP_ERR_NOT_OPEN                            Control block not open.
+ * @retval FSP_ERR_INVALID_STATE                       Host stack hasn't been initialized.
+ * @retval FSP_ERR_INVALID_POINTER                     p_advertising_parameter is specified as NULL.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    The advertising parameter is out of range.
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_StartLegacyAdvertising (ble_abs_ctrl_t * const                               p_ctrl,
+                                             ble_abs_legacy_advertising_parameter_t const * const p_advertising_parameter)
+{
+    st_ble_gap_adv_param_t    advertising_parameter;
+    ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+    uint8_t advertising_handle = BLE_ABS_LEGACY_HDL;
+
+    /* Parameter checking */
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(NULL != p_advertising_parameter, FSP_ERR_INVALID_POINTER);
+#endif
+
+    /* Status check */
+    FSP_ERROR_RETURN(0 == (p_instance_ctrl->advertising_sets[advertising_handle].advertising_status &
+                           (BLE_ABS_ADV_STATUS_ADV_FAST_START | BLE_ABS_ADV_STATUS_ADV_SLOW_START)),
+                     FSP_ERR_INVALID_STATE);
+
+    ble_abs_set_advertising_status(p_instance_ctrl, advertising_handle, 0,
+                                   (BLE_ABS_ADV_STATUS_PARAM_FAST | BLE_ABS_ADV_STATUS_PARAM_SLOW));
+
+    FSP_ERROR_RETURN(FSP_SUCCESS ==
+                     ble_abs_convert_legacy_advertising_parameter((ble_abs_legacy_advertising_parameter_t *)
+                                                                  p_advertising_parameter,
+                                                                  &advertising_parameter),
+                     FSP_ERR_INVALID_ARGUMENT);
+
+    /* Check data length */
+    FSP_ERROR_RETURN((BLE_ABS_LEGACY_ADV_DATA_LEN >= p_advertising_parameter->advertising_data_length) &&
+                     (BLE_ABS_LEGACY_ADV_DATA_LEN >= p_advertising_parameter->scan_response_data_length),
+                     FSP_ERR_INVALID_ARGUMENT);
+
+    /* Check advertising interval */
+    ble_abs_set_connection_advertising_interval(&advertising_parameter,
+                                                p_advertising_parameter->fast_advertising_interval,
+                                                p_advertising_parameter->slow_advertising_interval,
+                                                p_advertising_parameter->fast_advertising_period);
+
+    /* Advertising data update check */
+    ble_abs_update_data_status(p_instance_ctrl,
+                               BLE_ABS_ADV_STATUS_ADV_DATA,
+                               p_advertising_parameter->p_advertising_data,
+                               p_advertising_parameter->advertising_data_length,
+                               advertising_handle);
+
+    /* Scan response data update check */
+    ble_abs_update_data_status(p_instance_ctrl,
+                               BLE_ABS_ADV_STATUS_SRES_DATA,
+                               p_advertising_parameter->p_scan_response_data,
+                               p_advertising_parameter->scan_response_data_length,
+                               advertising_handle);
+
+    ble_abs_set_advertising_parameter(p_instance_ctrl,
+                                      (ble_abs_legacy_advertising_parameter_t *) p_advertising_parameter,
+                                      BLE_ABS_LEGACY_HDL);
+
+    /* Do NOT set the MAC address because it clears the current attribute database */
+    /* MAC Address set at boot only */
+
+    FSP_ERROR_RETURN(BLE_SUCCESS == R_BLE_GAP_SetAdvParam(&advertising_parameter), FSP_ERR_INVALID_ARGUMENT);
+
+    if ((NULL != p_advertising_parameter->p_advertising_data) && (0 < p_advertising_parameter->advertising_data_length))
+    {
+        /* Configure the GAP Advertisment Payload. */
+        st_ble_gap_adv_data_t advertising_data = {0};
+        advertising_data.data_type   = (uint8_t) (BLE_GAP_ADV_DATA_MODE);
+        advertising_data.data_length = p_advertising_parameter->advertising_data_length;
+        advertising_data.p_data      = p_advertising_parameter->p_advertising_data;
+        FSP_ERROR_RETURN(BLE_SUCCESS == R_BLE_GAP_SetAdvSresData(&advertising_data), FSP_ERR_INVALID_ARGUMENT);
+    }
+
+    if ((NULL != p_advertising_parameter->p_scan_response_data) &&
+        (0 < p_advertising_parameter->scan_response_data_length))
+    {
+        /* Configure the GAP Scan Response Payload. */
+        st_ble_gap_adv_data_t advertising_data = {0};
+        advertising_data.data_type   = (uint8_t) (BLE_GAP_SCAN_RSP_DATA_MODE);
+        advertising_data.data_length = p_advertising_parameter->scan_response_data_length;
+        advertising_data.p_data      = p_advertising_parameter->p_scan_response_data;
+        FSP_ERROR_RETURN(BLE_SUCCESS == R_BLE_GAP_SetAdvSresData(&advertising_data), FSP_ERR_INVALID_ARGUMENT);
+    }
+
+    /* Start Legacy Advertisment. */
+    FSP_ERROR_RETURN(BLE_SUCCESS == R_BLE_GAP_StartAdv(0, 0, 0), FSP_ERR_INVALID_ARGUMENT);
+
+    /* Set the internal status flags to indicate the advertisment mode. */
+    uint32_t status =
+        p_advertising_parameter->fast_advertising_period ? BLE_ABS_ADV_STATUS_PARAM_FAST : BLE_ABS_ADV_STATUS_PARAM_SLOW;
+    ble_abs_set_advertising_status(p_instance_ctrl, advertising_handle, status, 0);
+
+    return FSP_SUCCESS;
+}                                      /* End of function RM_BLE_ABS_StartLegacyAdvertising() */
+
+/*******************************************************************************************************************//**
+ * Start Extended Advertising after setting advertising parameters, advertising data.
+ * The extended advertising uses the advertising set whose advertising handle is 1.
+ * The advertising type is connectable and non-scannable.
+ * The address type of local device is Public Identity Address or
+ * RPA(If the resolving list contains no matching entry, use the public address.).
+ * Scan request event(BLE_GAP_EVENT_SCAN_REQ_RECV) is not notified.
+ * Implements @ref ble_abs_api_t::startExtendedAdvertising
+ *
+ * @retval FSP_ERR_ASSERTION                           p_instance_ctrl is specified as NULL.
+ * @retval FSP_ERR_NOT_OPEN                            Control block not open.
+ * @retval FSP_ERR_INVALID_POINTER                     p_advertising_parameter is specified as NULL.
+ * @retval FSP_ERR_UNSUPPORTED                         Subordinate modules do not support this feature.
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_StartExtendedAdvertising (ble_abs_ctrl_t * const                               p_ctrl,
+                                               ble_abs_extend_advertising_parameter_t const * const p_advertising_parameter)
+{
+    ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+    /* Parameter checking */
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+
+    /* Verify the pointers are valid */
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ERROR_RETURN(NULL != p_advertising_parameter, FSP_ERR_INVALID_POINTER);
+    FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#else
+    FSP_PARAMETER_NOT_USED(p_instance_ctrl);
+    FSP_PARAMETER_NOT_USED(p_advertising_parameter);
+#endif
+
+    return FSP_ERR_UNSUPPORTED;
+}                                      /* End of function RM_BLE_ABS_StartExtendedAdvertising() */
+
+/*******************************************************************************************************************//**
+ * Start Non-Connectable Advertising after setting advertising parameters, advertising data.
+ * The non-connectable advertising uses the advertising set whose advertising handle is 2.
+ * The advertising type is non-connectable and non-scannable.
+ * The address type of local device is Public Identity Address or
+ * RPA(If the resolving list contains no matching entry, use the public address.).
+ * Scan request event(BLE_GAP_EVENT_SCAN_REQ_RECV) is not notified.
+ * Secondary Advertising Max Skip is 0.
+ * Implements @ref ble_abs_api_t::startNonConnectableAdvertising.
+ *
+ * @retval FSP_ERR_ASSERTION                           p_instance_ctrl is specified as NULL.
+ * @retval FSP_ERR_NOT_OPEN                            Control block not open.
+ * @retval FSP_ERR_INVALID_POINTER                     p_advertising_parameter is specified as NULL.
+ * @retval FSP_ERR_UNSUPPORTED                         Feature not yet supported.
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_StartNonConnectableAdvertising (
+    ble_abs_ctrl_t * const                                        p_ctrl,
+    ble_abs_non_connectable_advertising_parameter_t const * const p_advertising_parameter)
+{
+    ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+    /* Parameter checking */
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+
+    /* Verify the pointers are valid */
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ERROR_RETURN(NULL != p_advertising_parameter, FSP_ERR_INVALID_POINTER);
+    FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#else
+    FSP_PARAMETER_NOT_USED(p_instance_ctrl);
+    FSP_PARAMETER_NOT_USED(p_advertising_parameter);
+#endif
+
+    return FSP_ERR_UNSUPPORTED;
+}                                      /* End of function RM_BLE_ABS_StartNonConnectableAdvertising() */
+
+/*******************************************************************************************************************//**
+ * Start Periodic Advertising after setting advertising parameters, periodic advertising parameters,
+ * advertising data and periodic advertising data.
+ * The periodic advertising uses the advertising set whose advertising handle is 3.
+ * The advertising type is non-connectable and non-scannable.
+ * The address type of local device is Public Identity Address or
+ * RPA(If the resolving list contains no matching entry, use the public address.).
+ * Scan request event(BLE_GAP_EVENT_SCAN_REQ_RECV) is not notified.
+ * Secondary Advertising Max Skip is 0.
+ * Implements @ref ble_abs_api_t::startPeriodicAdvertising
+ *
+ * @retval FSP_ERR_ASSERTION                           p_instance_ctrl is specified as NULL.
+ * @retval FSP_ERR_NOT_OPEN                            Control block not open.
+ * @retval FSP_ERR_INVALID_POINTER                     p_advertising_parameter is specified as NULL.
+ * @retval FSP_ERR_UNSUPPORTED                         Subordinate modules do not support this feature.
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_StartPeriodicAdvertising (ble_abs_ctrl_t * const                                 p_ctrl,
+                                               ble_abs_periodic_advertising_parameter_t const * const p_advertising_parameter)
+{
+    ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+
+    /* Verify the pointers are valid */
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ERROR_RETURN(NULL != p_advertising_parameter, FSP_ERR_INVALID_POINTER);
+    FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#else
+    FSP_PARAMETER_NOT_USED(p_instance_ctrl);
+    FSP_PARAMETER_NOT_USED(p_advertising_parameter);
+#endif
+
+    return FSP_ERR_UNSUPPORTED;
+}                                      /* End of function RM_BLE_ABS_StartPeriodicAdvertising() */
+
+/*******************************************************************************************************************//**
+ * Start scanning after setting scan parameters.
+ * The scanner address type is Public Identity Address.
+ * Fast scan is followed by slow scan.
+ * The end of fast scan or slow scan is notified with BLE_GAP_EVENT_SCAN_TO event.
+ * If fast_period is 0, only slow scan is carried out.
+ * If scan_period is 0, slow scan continues.
+ * Implements @ref ble_abs_api_t::startScanning.
+ *
+ * Example:
+ * @snippet rm_ble_abs_gtl_example.c RM_BLE_ABS_StartScanning
+ *
+ * @retval FSP_ERR_ASSERTION                           p_instance_ctrl is specified as NULL.
+ * @retval FSP_ERR_NOT_OPEN                            Control block not open.
+ * @retval FSP_ERR_INVALID_POINTER                     p_scan_parameter is specified as NULL.
+ * @retval FSP_ERR_UNSUPPORTED                         Function is not supported
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_StartScanning (ble_abs_ctrl_t * const                 p_ctrl,
+                                    ble_abs_scan_parameter_t const * const p_scan_parameter)
+{
+    ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+
+    /* Verify the pointers are valid */
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(NULL != p_scan_parameter, FSP_ERR_INVALID_POINTER);
+#else
+    FSP_PARAMETER_NOT_USED(p_instance_ctrl);
+    FSP_PARAMETER_NOT_USED(p_scan_parameter);
+#endif
+
+    return FSP_ERR_UNSUPPORTED;
+}                                      /* End of function RM_BLE_ABS_StartScanning() */
+
+/*******************************************************************************************************************//**
+ * Generate a IRK, add it to the resolving list, set privacy mode and enable RPA function.
+ * Register vendor specific callback function, if IRK is generated by this function.
+ * After configuring local device privacy,
+ * BLE_GAP_ADDR_RPA_ID_PUBLIC is specified as own device address
+ * in theadvertising/scan/create connection API.
+ * Implements @ref ble_abs_api_t::setLocalPrivacy
+ *
+ * @retval FSP_ERR_ASSERTION                           p_instance_ctrl is specified as NULL.
+ * @retval FSP_ERR_NOT_OPEN                            Control block not open.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    The privacy_mode parameter is out of range.
+ * @retval FSP_ERR_UNSUPPORTED                         Function is not supported
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_SetLocalPrivacy (ble_abs_ctrl_t * const p_ctrl,
+                                      uint8_t const * const  p_lc_irk,
+                                      uint8_t                privacy_mode)
+{
+    FSP_PARAMETER_NOT_USED(p_lc_irk);
+
+    ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+
+    /* Verify the pointers are valid */
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(BLE_GAP_DEV_PRIV_MODE >= privacy_mode, FSP_ERR_INVALID_ARGUMENT);
+#else
+    FSP_PARAMETER_NOT_USED(p_instance_ctrl);
+    FSP_PARAMETER_NOT_USED(privacy_mode);
+#endif
+
+    return FSP_ERR_UNSUPPORTED;
+}                                      /* End of function RM_BLE_ABS_SetLocalPrivacy() */
+
+/*******************************************************************************************************************//**
+ * Request create connection.
+ * The initiator address type is Public Identity Address.
+ * The scan interval is 60ms and the scan window is 30ms in case of 1M PHY or 2M PHY.
+ * The scan interval is 180ms and the scan window is 90ms in case of coded PHY.
+ * The Minimum CE Length and the Maximum CE Length are 0xFFFF.
+ * When the request for a connection has been received by the Controller,
+ * BLE_GAP_EVENT_CREATE_CONN_COMP event is notified.
+ * When a link has beens established, BLE_GAP_EVENT_CONN_IND event is notified.
+ * Implements @ref ble_abs_api_t::createConnection.
+ *
+ * Example:
+ * @snippet rm_ble_abs_gtl_example.c RM_BLE_ABS_CreateConnection
+ *
+ * @retval FSP_ERR_ASSERTION                           p_instance_ctrl is specified as NULL.
+ * @retval FSP_ERR_NOT_OPEN                            Control block not open.
+ * @retval FSP_ERR_INVALID_POINTER                     p_connection_parameter is specified as NULL.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    The create connection parameter is out of range.
+ * @retval FSP_ERR_UNSUPPORTED                         Function is not supported
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_CreateConnection (ble_abs_ctrl_t * const                       p_ctrl,
+                                       ble_abs_connection_parameter_t const * const p_connection_parameter)
+{
+    ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+
+    /* Verify the pointers are valid */
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(NULL != p_connection_parameter, FSP_ERR_INVALID_POINTER);
+    FSP_ERROR_RETURN(10 >= p_connection_parameter->connection_timeout, FSP_ERR_INVALID_ARGUMENT);
+#else
+    FSP_PARAMETER_NOT_USED(p_instance_ctrl);
+    FSP_PARAMETER_NOT_USED(p_connection_parameter);
+#endif
+
+    return FSP_ERR_UNSUPPORTED;
+}                                      /* End of function RM_BLE_ABS_CreateConnection() */
+
+/*******************************************************************************************************************//**
+ * Start pairing or encryption. If pairing has been done, start encryption.
+ * The pairing parameters are configured by RM_BLE_ABS_Open() or R_BLE_GAP_SetPairingParams().
+ * If the pairing parameters are configure by RM_BLE_ABS_Open(),
+ *    - bonding policy is that bonding information is stored.
+ *    - Key press notification is not supported.
+ * Implements @ref ble_abs_api_t::startAuthentication.
+ *
+ * Example:
+ * @snippet rm_ble_abs_gtl_example.c RM_BLE_ABS_StartAuthentication
+ *
+ * @retval FSP_ERR_ASSERTION                           p_instance_ctrl or connection_handle are specified as NULL.
+ * @retval FSP_ERR_NOT_OPEN                            Control block not open.
+ * @retval FSP_ERR_UNSUPPORTED                         Function is not supported
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_StartAuthentication (ble_abs_ctrl_t * const p_ctrl, uint16_t connection_handle)
+{
+    FSP_PARAMETER_NOT_USED(connection_handle);
+
+    ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+
+    /* Verify the pointers are valid */
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#else
+    FSP_PARAMETER_NOT_USED(p_instance_ctrl);
+#endif
+
+    return FSP_ERR_UNSUPPORTED;
+}                                      /* End of function RM_BLE_ABS_StartAuthentication() */
+
+/*******************************************************************************************************************//**
+ * Delete bonding information from BLE stack and storage.
+ * Implements @ref ble_abs_api_t::deleteBondInformation.
+ *
+ * Example:
+ * @snippet rm_ble_abs_gtl_example.c RM_BLE_ABS_DeleteBondInformation
+ *
+ * @retval FSP_SUCCESS             Operation was successful
+ * @retval FSP_ERR_ASSERTION       The parameter p_instance_ctrl is NULL.
+ * @retval FSP_ERR_INVALID_POINTER The parameter p_bond_information_parameter is NULL.
+ * @retval FSP_ERR_NOT_OPEN        Control block not open.
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_DeleteBondInformation (ble_abs_ctrl_t * const                             p_ctrl,
+                                            ble_abs_bond_information_parameter_t const * const p_bond_information_parameter)
+{
+    ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+
+    /* Verify the pointers are valid */
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ERROR_RETURN(NULL != p_bond_information_parameter, FSP_ERR_INVALID_POINTER);
+    FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#else
+    FSP_PARAMETER_NOT_USED(p_instance_ctrl);
+    FSP_PARAMETER_NOT_USED(p_bond_information_parameter);
+#endif
+
+    return FSP_SUCCESS;
+}
+
+/************************************************
+ *   Static function definitions                *
+ ***********************************************/
+
+/*******************************************************************************************************************//**
+ * Configure scan response data and start legacy advertising.
+ **********************************************************************************************************************/
+static void ble_abs_set_legacy_scan_response_data (ble_abs_instance_ctrl_t * const p_instance_ctrl)
+{
+    ble_abs_legacy_advertising_parameter_t * p_legacy_parameter =
+        &(p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_parameter.
+          legacy_advertising_parameter);
+
+    if (p_legacy_parameter->scan_response_data_length && p_legacy_parameter->p_scan_response_data)
+    {
+        if (p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_status & BLE_ABS_ADV_STATUS_SRES_DATA)
+        {
+            ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_LEGACY_HDL);
+        }
+        else
+        {
+            ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_LEGACY_HDL, BLE_GAP_SCAN_RSP_DATA_MODE);
+        }
+    }
+    else
+    {
+        ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_LEGACY_HDL);
+    }
+}                                      /* End of function ble_abs_set_legacy_scan_response_data() */
+
+/*******************************************************************************************************************//**
+ * Handler for GAP BLE_GAP_EVENT_ADV_PARAM_SET_COMP event.
+ **********************************************************************************************************************/
+static void ble_abs_advertising_parameter_set_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                                       st_ble_evt_data_t             * p_event_data)
+{
+    st_ble_gap_adv_set_evt_t * p_advertising_set_parameter;
+    p_advertising_set_parameter = (st_ble_gap_adv_set_evt_t *) p_event_data->p_param;
+
+    switch (p_advertising_set_parameter->adv_hdl)
+    {
+        case BLE_ABS_LEGACY_HDL:
+        {
+            if ((p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_status &
+                 (BLE_ABS_ADV_STATUS_PARAM_FAST | BLE_ABS_ADV_STATUS_PARAM_SLOW)))
+            {
+                ble_abs_legacy_advertising_parameter_t * p_legacy_parameter =
+                    &(p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_parameter.
+                      legacy_advertising_parameter);
+
+                if (p_legacy_parameter->advertising_data_length && p_legacy_parameter->p_advertising_data)
+                {
+                    if (p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_status &
+                        BLE_ABS_ADV_STATUS_ADV_DATA)
+                    {
+                        ble_abs_set_legacy_scan_response_data(p_instance_ctrl);
+                    }
+                    else
+                    {
+                        ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_LEGACY_HDL, BLE_GAP_ADV_DATA_MODE);
+                    }
+                }
+                else
+                {
+                    ble_abs_set_legacy_scan_response_data(p_instance_ctrl);
+                }
+            }
+
+            break;
+        }
+
+        case BLE_ABS_NON_CONN_HDL:
+        {
+            if (p_instance_ctrl->advertising_sets[BLE_ABS_NON_CONN_HDL].advertising_status &
+                BLE_ABS_ADV_STATUS_PARAM_SLOW)
+            {
+                if ((p_instance_ctrl->advertising_sets[BLE_ABS_NON_CONN_HDL].advertising_parameter.
+                     non_connectable_advertising_parameter.advertising_data_length) &&
+                    (p_instance_ctrl->advertising_sets[BLE_ABS_NON_CONN_HDL].advertising_parameter.
+                     non_connectable_advertising_parameter.p_advertising_data))
+                {
+                    ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_NON_CONN_HDL, BLE_GAP_ADV_DATA_MODE);
+                }
+                else
+                {
+                    ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_NON_CONN_HDL);
+                }
+            }
+
+            break;
+        }
+
+        default:
+        {
+            break;
+        }
+    }
+}                                      /* End of function ble_abs_advertising_parameter_set_handler() */
+
+/*******************************************************************************************************************//**
+ * Start advertising.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ **********************************************************************************************************************/
+static void ble_abs_advertising_start (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint8_t advertising_handle)
+{
+    ble_status_t retval = BLE_SUCCESS;
+
+    uint32_t status      = 0;
+    uint16_t fast_period = 0;
+
+    if (BLE_ABS_LEGACY_HDL == advertising_handle)
+    {
+        fast_period = p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_parameter.
+                      legacy_advertising_parameter.fast_advertising_period;
+    }
+
+    if (0x0000 == fast_period)
+    {
+        status = BLE_ABS_ADV_STATUS_ADV_SLOW_START;
+    }
+    else
+    {
+        if (p_instance_ctrl->advertising_sets[advertising_handle].advertising_status & BLE_ABS_ADV_STATUS_PARAM_SLOW)
+        {
+            status = BLE_ABS_ADV_STATUS_ADV_SLOW_START;
+        }
+        else
+        {
+            status = BLE_ABS_ADV_STATUS_ADV_FAST_START;
+        }
+    }
+
+    retval = R_BLE_GAP_StartAdv(0, 0, 0);
+    if (BLE_SUCCESS == retval)
+    {
+        ble_abs_set_advertising_status(p_instance_ctrl, advertising_handle, status, 0);
+    }
+}                                      /* End of function ble_abs_advertising_start() */
+
+/*******************************************************************************************************************//**
+ * Configure advertising data or scan response data or periodic advertising data.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ **********************************************************************************************************************/
+static void ble_abs_advertising_set_data (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                          uint8_t                         advertising_handle,
+                                          uint8_t                         data_type)
+{
+    st_ble_gap_adv_data_t advertising_data;
+    ble_status_t          retval = BLE_SUCCESS;
+    uint32_t              status = 0;
+
+    advertising_data.adv_hdl          = advertising_handle;
+    advertising_data.zero_length_flag = BLE_GAP_DATA_0_CLEAR;
+
+    switch (advertising_handle)
+    {
+        case BLE_ABS_LEGACY_HDL:
+        {
+            ble_abs_legacy_advertising_parameter_t * p_legacy_parameter =
+                &(p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_parameter.
+                  legacy_advertising_parameter);
+
+            if (BLE_GAP_ADV_DATA_MODE == data_type)
+            {
+                status = BLE_ABS_ADV_STATUS_ADV_DATA;
+                advertising_data.data_type   = (uint8_t) (BLE_GAP_ADV_DATA_MODE);
+                advertising_data.data_length = p_legacy_parameter->advertising_data_length;
+                advertising_data.p_data      = p_legacy_parameter->p_advertising_data;
+            }
+            else
+            {
+                status = BLE_ABS_ADV_STATUS_SRES_DATA;
+                advertising_data.data_type   = (uint8_t) (BLE_GAP_SCAN_RSP_DATA_MODE);
+                advertising_data.data_length = p_legacy_parameter->scan_response_data_length;
+                advertising_data.p_data      = p_legacy_parameter->p_scan_response_data;
+            }
+
+            break;
+        }
+
+        case BLE_ABS_NON_CONN_HDL:
+        {
+            status = BLE_ABS_ADV_STATUS_ADV_DATA;
+            advertising_data.data_type = BLE_GAP_ADV_DATA_MODE;
+
+            ble_abs_non_connectable_advertising_parameter_t * p_non_conn_parameter =
+                &(p_instance_ctrl->advertising_sets[BLE_ABS_NON_CONN_HDL].
+                  advertising_parameter.non_connectable_advertising_parameter);
+
+            advertising_data.data_length = p_non_conn_parameter->advertising_data_length;
+            advertising_data.p_data      = p_non_conn_parameter->p_advertising_data;
+            break;
+        }
+
+        default:
+        {
+            break;
+        }
+    }
+
+    retval = R_BLE_GAP_SetAdvSresData(&advertising_data);
+    if (BLE_SUCCESS == retval)
+    {
+        ble_abs_set_advertising_status(p_instance_ctrl, advertising_handle, status, 0);
+    }
+}                                      /* End of function ble_abs_advertising_set_data() */
+
+/*******************************************************************************************************************//**
+ * Handler for GAP BLE_GAP_EVENT_ADV_DATA_UPD_COMP event.
+ **********************************************************************************************************************/
+static void ble_abs_advertising_data_set_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                                  st_ble_evt_data_t             * p_event_data)
+{
+    st_ble_gap_adv_data_evt_t * p_advertising_data_set_parameter;
+
+    p_advertising_data_set_parameter = (st_ble_gap_adv_data_evt_t *) p_event_data->p_param;
+
+    switch (p_advertising_data_set_parameter->adv_hdl)
+    {
+        case BLE_ABS_LEGACY_HDL:
+        {
+            if (BLE_GAP_ADV_DATA_MODE == p_advertising_data_set_parameter->data_type)
+            {
+                ble_abs_set_legacy_scan_response_data(p_instance_ctrl);
+            }
+            else
+            {
+                ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_LEGACY_HDL);
+            }
+
+            break;
+        }
+
+        case BLE_ABS_NON_CONN_HDL:
+        {
+            ble_abs_advertising_start(p_instance_ctrl, p_advertising_data_set_parameter->adv_hdl);
+            break;
+        }
+
+        default:
+        {
+            break;
+        }
+    }
+}                                      /* End of function ble_abs_advertising_data_set_handler() */
+
+/*******************************************************************************************************************//**
+ * Handler for GAP BLE_GAP_EVENT_ADV_REPT_IND event.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_BLE_ABS_NOT_FOUND                   Filtering data is not included in the advertising data.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_advertising_report_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                                     st_ble_evt_data_t             * p_event_data)
+{
+    st_ble_gap_adv_rept_evt_t * p_advertising_report_parameter;
+    uint8_t * p_buf  = NULL;
+    uint32_t  len    = 0;
+    fsp_err_t retval = FSP_ERR_BLE_ABS_NOT_FOUND;
+
+    if ((NULL == p_instance_ctrl->abs_scan.scan_parameter.p_filter_data) ||
+        (0 == p_instance_ctrl->abs_scan.scan_parameter.filter_data_length))
+    {
+        retval = FSP_SUCCESS;
+    }
+    else
+    {
+        p_advertising_report_parameter = (st_ble_gap_adv_rept_evt_t *) p_event_data->p_param;
+
+        /* Only Legacy advertising is supported */
+        p_buf = p_advertising_report_parameter->param.p_adv_rpt->p_data;
+        len   = p_advertising_report_parameter->param.p_adv_rpt->len;
+
+        uint32_t cnt;
+
+        if ((len + 1) >= (uint32_t) p_instance_ctrl->abs_scan.scan_parameter.filter_data_length)
+        {
+            cnt = len - (uint32_t) p_instance_ctrl->abs_scan.scan_parameter.filter_data_length + 1;
+        }
+        else
+        {
+            cnt = 0;
+        }
+
+        if (1 <= cnt)
+        {
+            uint32_t i;
+            uint32_t pos = 0U;
+
+            while (pos < len)
+            {
+                /* Each advertising structure have following constructs.
+                 * - Lenght: 1 byte (The length of AD type + AD data)
+                 * - AD type: 1 byte
+                 * - AD data: variable
+                 */
+                uint8_t ad_len = (uint8_t) (p_buf[pos] - 1);
+                uint8_t type   = p_buf[pos + 1];
+
+                pos = (uint16_t) (pos + 2UL);
+
+                if (type == p_instance_ctrl->abs_scan.scan_parameter.filter_ad_type)
+                {
+                    for (i = 0; i < ad_len; i++)
+                    {
+                        if (0 ==
+                            memcmp(&p_buf[pos + i], p_instance_ctrl->abs_scan.scan_parameter.p_filter_data,
+                                   (uint32_t) p_instance_ctrl->abs_scan.scan_parameter.filter_data_length))
+                        {
+                            return FSP_SUCCESS;
+                        }
+                    }
+                }
+
+                pos = (uint16_t) (pos + ad_len);
+            }
+        }
+    }
+
+    return retval;
+}                                      /* End of function ble_abs_advertising_report_handler() */
+
+/**********************************************************************************************************************
+ * Set gap callback and vendor specific callback function.
+ **********************************************************************************************************************/
+static void ble_abs_set_abs_callback (ble_abs_instance_ctrl_t * const            p_instance_ctrl,
+                                      ble_gap_application_callback_t             gap_callback,
+                                      ble_vendor_specific_application_callback_t vendor_specific_callback)
+{
+    p_instance_ctrl->abs_gap_callback             = gap_callback;
+    p_instance_ctrl->abs_vendor_specific_callback = vendor_specific_callback;
+}                                      /* End of function ble_abs_set_abs_callback() */
+
+/**********************************************************************************************************************
+ * Set advertising interval.
+ **********************************************************************************************************************/
+static void ble_abs_set_connection_advertising_interval (st_ble_gap_adv_param_t * p_advertising_parameter,
+                                                         uint32_t                 fast_advertising_interval,
+                                                         uint32_t                 slow_advertising_interval,
+                                                         uint16_t                 fast_period)
+{
+    /* Check advertising interval */
+    if (fast_period)
+    {
+        p_advertising_parameter->adv_intv_min = fast_advertising_interval;
+        p_advertising_parameter->adv_intv_max = fast_advertising_interval;
+    }
+    else
+    {
+        p_advertising_parameter->adv_intv_min = slow_advertising_interval;
+        p_advertising_parameter->adv_intv_max = slow_advertising_interval;
+    }
+}                                      /* End of function ble_abs_set_connection_advertising_interval() */
+
+/*******************************************************************************************************************//**
+ * Update advertising data status.
+ **********************************************************************************************************************/
+static void ble_abs_update_data_status (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                        uint32_t                        advertising_status,
+                                        uint8_t                       * p_advertising_data,
+                                        uint16_t                        advertising_data_len,
+                                        uint8_t                         advertising_handle)
+{
+    if (p_instance_ctrl->advertising_sets[advertising_handle].advertising_status & advertising_status)
+    {
+        if ((0 != advertising_data_len) && (NULL != p_advertising_data))
+        {
+            ble_abs_set_advertising_status(p_instance_ctrl, advertising_handle, 0, advertising_status);
+        }
+    }
+}                                      /* End of function ble_abs_update_data_status() */
+
+/*******************************************************************************************************************//**
+ * Convert the legacy advertising parameters to GAP advertising parameters.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    The advertising parameter is out of range.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_convert_legacy_advertising_parameter (
+    ble_abs_legacy_advertising_parameter_t * p_legacy_advertising_parameter,
+    st_ble_gap_adv_param_t                 * p_gap_advertising_parameter)
+{
+    p_gap_advertising_parameter->adv_hdl       = BLE_ABS_LEGACY_HDL;
+    p_gap_advertising_parameter->adv_prop_type = BLE_GAP_LEGACY_PROP_ADV_IND;
+    p_gap_advertising_parameter->adv_ch_map    = p_legacy_advertising_parameter->advertising_channel_map;
+
+    FSP_ERROR_RETURN((BLE_GAP_ADDR_RPA_ID_PUBLIC >= p_legacy_advertising_parameter->own_bluetooth_address_type),
+                     FSP_ERR_INVALID_ARGUMENT);
+
+    memcpy(p_gap_advertising_parameter->o_addr,
+           (void *) p_legacy_advertising_parameter->own_bluetooth_address,
+           BLE_BD_ADDR_LEN);
+
+    p_gap_advertising_parameter->o_addr_type = p_legacy_advertising_parameter->own_bluetooth_address_type;
+
+    if (p_legacy_advertising_parameter->p_peer_address)
+    {
+        memcpy(p_gap_advertising_parameter->p_addr,
+               p_legacy_advertising_parameter->p_peer_address->addr,
+               BLE_BD_ADDR_LEN);
+        p_gap_advertising_parameter->p_addr_type = p_legacy_advertising_parameter->p_peer_address->type;
+    }
+    else
+    {
+        p_gap_advertising_parameter->p_addr_type = BLE_GAP_ADDR_PUBLIC;
+    }
+
+    p_gap_advertising_parameter->filter_policy = p_legacy_advertising_parameter->advertising_filter_policy;
+
+    p_gap_advertising_parameter->adv_phy           = BLE_GAP_ADV_PHY_1M;
+    p_gap_advertising_parameter->sec_adv_max_skip  = 0x00;
+    p_gap_advertising_parameter->sec_adv_phy       = BLE_GAP_ADV_PHY_1M;
+    p_gap_advertising_parameter->scan_req_ntf_flag = BLE_GAP_SCAN_REQ_NTF_DISABLE;
+
+    return FSP_SUCCESS;
+}                                      /* End of function ble_abs_convert_legacy_advertising_parameter() */
+
+/*******************************************************************************************************************//**
+ * Set advertising status.
+ **********************************************************************************************************************/
+static void ble_abs_set_advertising_status (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                            uint8_t                         advertising_handle,
+                                            uint32_t                        set,
+                                            uint32_t                        clear)
+{
+    p_instance_ctrl->advertising_sets[advertising_handle].advertising_status |= set;
+    p_instance_ctrl->advertising_sets[advertising_handle].advertising_status &= ~clear;
+}                                      /* End of function ble_abs_set_advertising_status() */
+
+/*******************************************************************************************************************//**
+ * Store advertising configuration.
+ **********************************************************************************************************************/
+static void ble_abs_set_advertising_parameter (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                               void                          * p_advertising_parameter,
+                                               uint8_t                         advertising_handle)
+{
+    switch (advertising_handle)
+    {
+        case BLE_ABS_LEGACY_HDL:
+        {
+            ble_abs_legacy_advertising_parameter_t * p_abs_legacy;
+            p_abs_legacy = (ble_abs_legacy_advertising_parameter_t *) p_advertising_parameter;
+
+            memcpy(
+                &p_instance_ctrl->advertising_sets[advertising_handle].advertising_parameter.legacy_advertising_parameter,
+                p_abs_legacy,
+                sizeof(ble_abs_legacy_advertising_parameter_t));
+            if (NULL != p_abs_legacy->p_peer_address)
+            {
+                memcpy(&p_instance_ctrl->advertising_sets[advertising_handle].remote_device_address,
+                       p_abs_legacy->p_peer_address,
+                       sizeof(ble_device_address_t));
+                p_instance_ctrl->advertising_sets[advertising_handle].advertising_parameter.legacy_advertising_parameter
+                .p_peer_address = &p_instance_ctrl->advertising_sets[advertising_handle].remote_device_address;
+            }
+
+            break;
+        }
+
+        case BLE_ABS_NON_CONN_HDL:
+        {
+            ble_abs_non_connectable_advertising_parameter_t * p_abs_non_conn;
+            p_abs_non_conn = (ble_abs_non_connectable_advertising_parameter_t *) p_advertising_parameter;
+
+            memcpy(
+                &p_instance_ctrl->advertising_sets[advertising_handle].advertising_parameter.non_connectable_advertising_parameter,
+                p_abs_non_conn,
+                sizeof(ble_abs_non_connectable_advertising_parameter_t));
+            if (NULL != p_abs_non_conn->p_peer_address)
+            {
+                memcpy(&p_instance_ctrl->advertising_sets[advertising_handle].remote_device_address,
+                       p_abs_non_conn->p_peer_address,
+                       sizeof(ble_device_address_t));
+                p_instance_ctrl->advertising_sets[advertising_handle].advertising_parameter.
+                non_connectable_advertising_parameter.p_peer_address =
+                    &p_instance_ctrl->advertising_sets[advertising_handle].remote_device_address;
+            }
+
+            break;
+        }
+
+        default:
+        {
+            break;
+        }
+    }
+}                                      /* End of function ble_abs_set_advertising_parameter() */
+
+/*******************************************************************************************************************//**
+ * GAP Event handler.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ **********************************************************************************************************************/
+static void ble_abs_gap_callback (uint16_t event_type, ble_status_t event_result, st_ble_evt_data_t * p_event_data)
+{
+    switch (event_type)
+    {
+        case BLE_GAP_EVENT_STACK_ON:
+        {
+            uint8_t              irk[BLE_GAP_IRK_SIZE];
+            ble_device_address_t identity_address;
+
+            R_BLE_GAP_SetLocIdInfo((st_ble_dev_addr_t *) (&identity_address), irk);
+
+            break;
+        }
+
+        case BLE_GAP_EVENT_DISCONN_IND:
+        {
+            break;
+        }
+
+        case BLE_GAP_EVENT_ADV_REPT_IND:
+        {
+            if (FSP_SUCCESS != ble_abs_advertising_report_handler(gp_instance_ctrl, p_event_data))
+            {
+                return;
+            }
+
+            break;
+        }
+
+        case BLE_GAP_EVENT_ADV_PARAM_SET_COMP:
+        {
+            ble_abs_advertising_parameter_set_handler(gp_instance_ctrl, p_event_data);
+            break;
+        }
+
+        case BLE_GAP_EVENT_ADV_DATA_UPD_COMP:
+        {
+            ble_abs_advertising_data_set_handler(gp_instance_ctrl, p_event_data);
+            break;
+        }
+
+        case BLE_GAP_EVENT_CONN_IND:
+        {
+            ble_abs_set_advertising_status(gp_instance_ctrl, BLE_ABS_LEGACY_HDL, 0,
+                                           (BLE_ABS_ADV_STATUS_ADV_FAST_START | BLE_ABS_ADV_STATUS_ADV_SLOW_START));
+
+            R_BLE_GAP_StopAdv(0);
+
+            break;
+        }
+
+        default:
+        {
+            break;
+        }
+    }
+
+    gp_instance_ctrl->abs_gap_callback(event_type, event_result, p_event_data);
+}                                      /* End of function ble_abs_gap_callback() */                                  /* End of function ble_abs_random_handler() */
diff --git a/ra/fsp/src/rm_ble_abs_spp/r_ble_spp_api.c b/ra/fsp/src/rm_ble_abs_spp/r_ble_spp_api.c
index ec19e5aec..9b6f611bf 100644
--- a/ra/fsp/src/rm_ble_abs_spp/r_ble_spp_api.c
+++ b/ra/fsp/src/rm_ble_abs_spp/r_ble_spp_api.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_ble_abs_spp/rm_ble_abs_spp.c b/ra/fsp/src/rm_ble_abs_spp/rm_ble_abs_spp.c
index 877ef0068..920e053a7 100644
--- a/ra/fsp/src/rm_ble_abs_spp/rm_ble_abs_spp.c
+++ b/ra/fsp/src/rm_ble_abs_spp/rm_ble_abs_spp.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_block_media_sdmmc/rm_block_media_sdmmc.c b/ra/fsp/src/rm_block_media_sdmmc/rm_block_media_sdmmc.c
index 43be18fc0..90626ea75 100644
--- a/ra/fsp/src/rm_block_media_sdmmc/rm_block_media_sdmmc.c
+++ b/ra/fsp/src/rm_block_media_sdmmc/rm_block_media_sdmmc.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_block_media_spi/rm_block_media_spi.c b/ra/fsp/src/rm_block_media_spi/rm_block_media_spi.c
index 05503d9ff..7e79901c2 100644
--- a/ra/fsp/src/rm_block_media_spi/rm_block_media_spi.c
+++ b/ra/fsp/src/rm_block_media_spi/rm_block_media_spi.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_block_media_usb/rm_block_media_usb.c b/ra/fsp/src/rm_block_media_usb/rm_block_media_usb.c
index 73e1ba5b3..46bc8c78a 100644
--- a/ra/fsp/src/rm_block_media_usb/rm_block_media_usb.c
+++ b/ra/fsp/src/rm_block_media_usb/rm_block_media_usb.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_cellular_comm_uart_aws/rm_cellular_comm_uart_aws.c b/ra/fsp/src/rm_cellular_comm_uart_aws/rm_cellular_comm_uart_aws.c
index a51815011..aeb6c4157 100644
--- a/ra/fsp/src/rm_cellular_comm_uart_aws/rm_cellular_comm_uart_aws.c
+++ b/ra/fsp/src/rm_cellular_comm_uart_aws/rm_cellular_comm_uart_aws.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_cellular_platform_aws/cellular_platform.c b/ra/fsp/src/rm_cellular_platform_aws/cellular_platform.c
index 796df3e18..ae489c326 100644
--- a/ra/fsp/src/rm_cellular_platform_aws/cellular_platform.c
+++ b/ra/fsp/src/rm_cellular_platform_aws/cellular_platform.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz.c b/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz.c
index 4d86b8025..ae0c5bcee 100644
--- a/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz.c
+++ b/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz.h b/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz.h
index e6ae7a1b6..0d563905f 100644
--- a/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz.h
+++ b/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz_api.c b/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz_api.c
index 6764c11ab..928801aa4 100644
--- a/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz_api.c
+++ b/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz_api.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz_urc_handler.c b/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz_urc_handler.c
index 019a32043..419e98b26 100644
--- a/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz_urc_handler.c
+++ b/ra/fsp/src/rm_cellular_ryz_aws/cellular_ryz_urc_handler.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_comms_i2c/rm_comms_i2c.c b/ra/fsp/src/rm_comms_i2c/rm_comms_i2c.c
index ec9ce61fd..b2c0a7ad0 100644
--- a/ra/fsp/src/rm_comms_i2c/rm_comms_i2c.c
+++ b/ra/fsp/src/rm_comms_i2c/rm_comms_i2c.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_comms_i2c/rm_comms_i2c_driver_ra.c b/ra/fsp/src/rm_comms_i2c/rm_comms_i2c_driver_ra.c
index 33c1073d4..2dea349d3 100644
--- a/ra/fsp/src/rm_comms_i2c/rm_comms_i2c_driver_ra.c
+++ b/ra/fsp/src/rm_comms_i2c/rm_comms_i2c_driver_ra.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_filex_block_media/rm_filex_block_media.c b/ra/fsp/src/rm_filex_block_media/rm_filex_block_media.c
index 243ada747..eeb90aecf 100644
--- a/ra/fsp/src/rm_filex_block_media/rm_filex_block_media.c
+++ b/ra/fsp/src/rm_filex_block_media/rm_filex_block_media.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_filex_levelx_nor/rm_filex_levelx_nor.c b/ra/fsp/src/rm_filex_levelx_nor/rm_filex_levelx_nor.c
index cb50188eb..20d9f0fcc 100644
--- a/ra/fsp/src/rm_filex_levelx_nor/rm_filex_levelx_nor.c
+++ b/ra/fsp/src/rm_filex_levelx_nor/rm_filex_levelx_nor.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_freertos_plus_fat/FreeRTOSConfigMinimal.h b/ra/fsp/src/rm_freertos_plus_fat/FreeRTOSConfigMinimal.h
index fca630805..1992526c3 100644
--- a/ra/fsp/src/rm_freertos_plus_fat/FreeRTOSConfigMinimal.h
+++ b/ra/fsp/src/rm_freertos_plus_fat/FreeRTOSConfigMinimal.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_freertos_plus_fat/rm_freertos_plus_fat.c b/ra/fsp/src/rm_freertos_plus_fat/rm_freertos_plus_fat.c
index 24b81b295..a789a881f 100644
--- a/ra/fsp/src/rm_freertos_plus_fat/rm_freertos_plus_fat.c
+++ b/ra/fsp/src/rm_freertos_plus_fat/rm_freertos_plus_fat.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_fs1015/rm_fs1015.c b/ra/fsp/src/rm_fs1015/rm_fs1015.c
index af9562a48..35279e5f7 100644
--- a/ra/fsp/src/rm_fs1015/rm_fs1015.c
+++ b/ra/fsp/src/rm_fs1015/rm_fs1015.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_fs2012/rm_fs2012.c b/ra/fsp/src/rm_fs2012/rm_fs2012.c
index 7b2c8762c..69b7525d7 100644
--- a/ra/fsp/src/rm_fs2012/rm_fs2012.c
+++ b/ra/fsp/src/rm_fs2012/rm_fs2012.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_fs3000/rm_fs3000.c b/ra/fsp/src/rm_fs3000/rm_fs3000.c
index bcacc60b3..269946fb2 100644
--- a/ra/fsp/src/rm_fs3000/rm_fs3000.c
+++ b/ra/fsp/src/rm_fs3000/rm_fs3000.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_guix_port/gx_display_driver_dave2d.c b/ra/fsp/src/rm_guix_port/gx_display_driver_dave2d.c
index 49fb649ce..3c95894cd 100644
--- a/ra/fsp/src/rm_guix_port/gx_display_driver_dave2d.c
+++ b/ra/fsp/src/rm_guix_port/gx_display_driver_dave2d.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -1472,8 +1472,22 @@ static VOID gx_dave2d_pixelmap_draw (GX_DRAW_CONTEXT * context,
         CHECK_DAVE_STATUS(d2_settexclut(dave, (d2_color *) pixelmap->gx_pixelmap_aux_data))
     }
 
-    CHECK_DAVE_STATUS(d2_setblitsrc(dave, (void *) pixelmap->gx_pixelmap_data, pixelmap->gx_pixelmap_width,
-                                    pixelmap->gx_pixelmap_width, pixelmap->gx_pixelmap_height, mode))
+    GX_VALUE width;
+    GX_VALUE height;
+
+    /* Swap width and height if image was generated in a rotated orientation */
+    if (pixelmap->gx_pixelmap_flags & (GX_PIXELMAP_ROTATED_CW | GX_PIXELMAP_ROTATED_CCW))
+    {
+        width  = pixelmap->gx_pixelmap_height;
+        height = pixelmap->gx_pixelmap_width;
+    }
+    else
+    {
+        width  = pixelmap->gx_pixelmap_width;
+        height = pixelmap->gx_pixelmap_height;
+    }
+
+    CHECK_DAVE_STATUS(d2_setblitsrc(dave, (void *) pixelmap->gx_pixelmap_data, width, width, height, mode))
 
     mode = (d2_u32) d2_bf_no_blitctxbackup;
 
@@ -1482,11 +1496,10 @@ static VOID gx_dave2d_pixelmap_draw (GX_DRAW_CONTEXT * context,
         mode |= (d2_u32) d2_bf_usealpha;
     }
 
-    CHECK_DAVE_STATUS(d2_blitcopy(dave, pixelmap->gx_pixelmap_width, pixelmap->gx_pixelmap_height, 0, 0,
-                                  (d2_width) (D2_FIX4((USHORT) pixelmap->gx_pixelmap_width)),
-                                  (d2_width) (D2_FIX4((USHORT) pixelmap->gx_pixelmap_height)),
-                                  (d2_point) (D2_FIX4((USHORT) xpos)),
-                                  (d2_point) (D2_FIX4((USHORT) ypos)), mode))
+    CHECK_DAVE_STATUS(d2_blitcopy(dave, width, height, 0, 0, (d2_width) (D2_FIX4((USHORT) width)),
+                                  (d2_width) (D2_FIX4((USHORT) height)), (d2_point) (D2_FIX4((USHORT) xpos)),
+                                  (d2_point) (D2_FIX4((USHORT) ypos)),
+                                  mode))
 
     /** Reset the alpha value. */
     gx_dave2d_alpha_set(dave, (UCHAR) GX_ALPHA_VALUE_OPAQUE);
diff --git a/ra/fsp/src/rm_guix_port/gx_display_driver_dave2d_8bit_palette.c b/ra/fsp/src/rm_guix_port/gx_display_driver_dave2d_8bit_palette.c
index 826cf6ec6..3e6e31db3 100644
--- a/ra/fsp/src/rm_guix_port/gx_display_driver_dave2d_8bit_palette.c
+++ b/ra/fsp/src/rm_guix_port/gx_display_driver_dave2d_8bit_palette.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_guix_port/rm_guix_port.c b/ra/fsp/src/rm_guix_port/rm_guix_port.c
index 9995f6ce4..f884d19ac 100644
--- a/ra/fsp/src/rm_guix_port/rm_guix_port.c
+++ b/ra/fsp/src/rm_guix_port/rm_guix_port.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_hs300x/rm_hs300x.c b/ra/fsp/src/rm_hs300x/rm_hs300x.c
index 7a94366b5..1e303894b 100644
--- a/ra/fsp/src/rm_hs300x/rm_hs300x.c
+++ b/ra/fsp/src/rm_hs300x/rm_hs300x.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -250,7 +250,7 @@ fsp_err_t RM_HS300X_DataCalculate (rm_hs300x_ctrl_t * const     p_api_ctrl,
 {
     rm_hs300x_instance_ctrl_t * p_ctrl = (rm_hs300x_instance_ctrl_t *) p_api_ctrl;
     uint8_t  status;
-    int32_t  tmp = 0;
+    int32_t  tmp_32  = 0;
     uint16_t tmp_u16 = 0x0000U;
 
 #if RM_HS300X_CFG_PARAM_CHECKING_ENABLE
@@ -267,19 +267,26 @@ fsp_err_t RM_HS300X_DataCalculate (rm_hs300x_ctrl_t * const     p_api_ctrl,
     FSP_ERROR_RETURN(RM_HS300X_DATA_STATUS_VALID == status, FSP_ERR_SENSOR_INVALID_DATA);
 
     /* Relative Humidity [%RH] */
-    tmp_u16 = (uint16_t) ((uint16_t) (p_raw_data->humidity[0] & RM_HS300X_MASK_HUMIDITY_UPPER_0X3F) << 8);
-    tmp_u16 = (uint16_t)(tmp_u16 | (uint16_t) (p_raw_data->humidity[1]));
-    tmp = (tmp_u16 * RM_HS300X_CALC_HUMD_VALUE_100 * 100) / RM_HS300X_CALC_STATIC_VALUE;
-    p_hs300x_data->humidity.integer_part = (int16_t)(tmp / 100);
-    p_hs300x_data->humidity.decimal_part = (int16_t)(tmp % 100);
+    tmp_u16 =
+        (uint16_t) ((uint16_t) (p_raw_data->humidity[0] & RM_HS300X_MASK_HUMIDITY_UPPER_0X3F) << 8);
+    tmp_u16 = (uint16_t) (tmp_u16 | (uint16_t) (p_raw_data->humidity[1]));
+    tmp_32  = (int32_t) (((int32_t) tmp_u16 * RM_HS300X_CALC_HUMD_VALUE_100 * RM_HS300X_CALC_DECIMAL_VALUE_100) /
+                         RM_HS300X_CALC_STATIC_VALUE);
+    p_hs300x_data->humidity.integer_part = (int16_t) (tmp_32 / RM_HS300X_CALC_DECIMAL_VALUE_100);
+    p_hs300x_data->humidity.decimal_part = (int16_t) (tmp_32 % RM_HS300X_CALC_DECIMAL_VALUE_100);
 
 #if RM_HS300X_CFG_DATA_BOTH_HUMIDITY_TEMPERATURE
+
     /* Temperature [Celsius] */
     tmp_u16 = (uint16_t) ((uint16_t) (p_raw_data->temperature[0]) << 8);
-    tmp_u16 = (uint16_t)((tmp_u16 | (uint16_t) (p_raw_data->temperature[1] & RM_HS300X_MASK_TEMPERATURE_LOWER_0XFC)) >> 2);
-    tmp = ((tmp_u16 * RM_HS300X_CALC_TEMP_C_VALUE_165 * 100) / RM_HS300X_CALC_STATIC_VALUE) - (RM_HS300X_CALC_TEMP_C_VALUE_40 * 100);
-    p_hs300x_data->temperature.integer_part = (int16_t)(tmp / 100);
-    p_hs300x_data->temperature.decimal_part = (int16_t)(tmp % 100);
+    tmp_u16 =
+        (uint16_t) ((tmp_u16 | (uint16_t) (p_raw_data->temperature[1] & RM_HS300X_MASK_TEMPERATURE_LOWER_0XFC)) >> 2);
+    tmp_32 =
+        (int32_t) ((((int32_t) tmp_u16 * RM_HS300X_CALC_TEMP_C_VALUE_165 * RM_HS300X_CALC_DECIMAL_VALUE_100) /
+                    RM_HS300X_CALC_STATIC_VALUE) -
+                   (RM_HS300X_CALC_TEMP_C_VALUE_40 * RM_HS300X_CALC_DECIMAL_VALUE_100));
+    p_hs300x_data->temperature.integer_part = (int16_t) (tmp_32 / RM_HS300X_CALC_DECIMAL_VALUE_100);
+    p_hs300x_data->temperature.decimal_part = (int16_t) (tmp_32 % RM_HS300X_CALC_DECIMAL_VALUE_100);
 #endif
 
     return FSP_SUCCESS;
diff --git a/ra/fsp/src/rm_hs300x/rm_hs300x_ra_driver.c b/ra/fsp/src/rm_hs300x/rm_hs300x_ra_driver.c
index 255895325..c489341f7 100644
--- a/ra/fsp/src/rm_hs300x/rm_hs300x_ra_driver.c
+++ b/ra/fsp/src/rm_hs300x/rm_hs300x_ra_driver.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_hs400x/rm_hs400x.c b/ra/fsp/src/rm_hs400x/rm_hs400x.c
index ee89a8f2f..34ce57a79 100644
--- a/ra/fsp/src/rm_hs400x/rm_hs400x.c
+++ b/ra/fsp/src/rm_hs400x/rm_hs400x.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_hs400x/rm_hs400x_ra_driver.c b/ra/fsp/src/rm_hs400x/rm_hs400x_ra_driver.c
index 3ee4004a9..7b033608e 100644
--- a/ra/fsp/src/rm_hs400x/rm_hs400x_ra_driver.c
+++ b/ra/fsp/src/rm_hs400x/rm_hs400x_ra_driver.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_levelx_nor_spi/rm_levelx_nor_spi.c b/ra/fsp/src/rm_levelx_nor_spi/rm_levelx_nor_spi.c
index 4e4ee3328..94b4a6c3a 100644
--- a/ra/fsp/src/rm_levelx_nor_spi/rm_levelx_nor_spi.c
+++ b/ra/fsp/src/rm_levelx_nor_spi/rm_levelx_nor_spi.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_littlefs_flash/rm_littlefs_flash.c b/ra/fsp/src/rm_littlefs_flash/rm_littlefs_flash.c
index 037b7a9c3..a5f04d4b7 100644
--- a/ra/fsp/src/rm_littlefs_flash/rm_littlefs_flash.c
+++ b/ra/fsp/src/rm_littlefs_flash/rm_littlefs_flash.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_mcuboot_port/crypto/sce9_ecdsa_p256.h b/ra/fsp/src/rm_mcuboot_port/crypto/sce9_ecdsa_p256.h
index 2a10b7d55..df25a2637 100644
--- a/ra/fsp/src/rm_mcuboot_port/crypto/sce9_ecdsa_p256.h
+++ b/ra/fsp/src/rm_mcuboot_port/crypto/sce9_ecdsa_p256.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_mcuboot_port/crypto/sce9_keys.c b/ra/fsp/src/rm_mcuboot_port/crypto/sce9_keys.c
index ecdb20a15..bffd33e63 100644
--- a/ra/fsp/src/rm_mcuboot_port/crypto/sce9_keys.c
+++ b/ra/fsp/src/rm_mcuboot_port/crypto/sce9_keys.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_mcuboot_port/crypto/sce9_keys.h b/ra/fsp/src/rm_mcuboot_port/crypto/sce9_keys.h
index e1253b90d..367dd0d7e 100644
--- a/ra/fsp/src/rm_mcuboot_port/crypto/sce9_keys.h
+++ b/ra/fsp/src/rm_mcuboot_port/crypto/sce9_keys.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_mcuboot_port/crypto/sce9_sha256.h b/ra/fsp/src/rm_mcuboot_port/crypto/sce9_sha256.h
index cb46d3b53..3e57edf1e 100644
--- a/ra/fsp/src/rm_mcuboot_port/crypto/sce9_sha256.h
+++ b/ra/fsp/src/rm_mcuboot_port/crypto/sce9_sha256.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_motor_120_control_hall/rm_motor_120_control_hall.c b/ra/fsp/src/rm_motor_120_control_hall/rm_motor_120_control_hall.c
index 9812cd0dd..ca4ead48d 100644
--- a/ra/fsp/src/rm_motor_120_control_hall/rm_motor_120_control_hall.c
+++ b/ra/fsp/src/rm_motor_120_control_hall/rm_motor_120_control_hall.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -179,6 +179,11 @@ fsp_err_t RM_MOTOR_120_CONTROL_HALL_Open (motor_120_control_ctrl_t * const
         p_extended_cfg->p_speed_calc_timer_instance->p_api->open(p_extended_cfg->p_speed_calc_timer_instance->p_ctrl,
                                                                  p_extended_cfg->p_speed_calc_timer_instance->p_cfg);
         p_extended_cfg->p_speed_calc_timer_instance->p_api->start(p_extended_cfg->p_speed_calc_timer_instance->p_ctrl);
+
+        timer_info_t timer_info;
+        p_extended_cfg->p_speed_calc_timer_instance->p_api->infoGet(p_extended_cfg->p_speed_calc_timer_instance->p_ctrl,
+                                                                    &timer_info);
+        p_instance_ctrl->timer_direction = timer_info.count_direction;
     }
 
     /* Open hall interrupt module */
@@ -924,23 +929,47 @@ static void rm_motor_120_control_hall_speed_calc (motor_120_control_hall_instanc
                                                                   &gpt_timer_status); /* get value of timer counter */
     p_ctrl->u4_hall_timer_cnt = gpt_timer_status.counter;
 
-    if (p_ctrl->u4_pre_hall_timer_cnt != 0)
+    if (TIMER_DIRECTION_UP == p_ctrl->timer_direction)
     {
-        if (p_ctrl->u4_hall_timer_cnt >= p_ctrl->u4_pre_hall_timer_cnt)
+        if (p_ctrl->u4_pre_hall_timer_cnt != 0)
         {
-            u4_temp = (p_ctrl->u4_hall_timer_cnt - p_ctrl->u4_pre_hall_timer_cnt);
+            if (p_ctrl->u4_hall_timer_cnt >= p_ctrl->u4_pre_hall_timer_cnt)
+            {
+                u4_temp = (p_ctrl->u4_hall_timer_cnt - p_ctrl->u4_pre_hall_timer_cnt);
 
-            /* calculate timer count in 60 degrees */
+                /* calculate timer count in 60 degrees */
+            }
+            else
+            {
+                u4_temp = ((p_extended_cfg->p_speed_calc_timer_instance->p_cfg->period_counts - 1) -
+                           p_ctrl->u4_pre_hall_timer_cnt) + p_ctrl->u4_hall_timer_cnt;
+            }
         }
         else
         {
-            u4_temp = ((p_extended_cfg->p_speed_calc_timer_instance->p_cfg->period_counts - 1) -
-                       p_ctrl->u4_pre_hall_timer_cnt) + p_ctrl->u4_hall_timer_cnt;
+            u4_temp = p_ctrl->u4_hall_timer_cnt;
         }
     }
     else
     {
-        u4_temp = p_ctrl->u4_hall_timer_cnt;
+        if (p_ctrl->u4_pre_hall_timer_cnt != 0)
+        {
+            if (p_ctrl->u4_hall_timer_cnt <= p_ctrl->u4_pre_hall_timer_cnt)
+            {
+                u4_temp = (p_ctrl->u4_pre_hall_timer_cnt - p_ctrl->u4_hall_timer_cnt);
+
+                /* calculate timer count in 60 degrees */
+            }
+            else
+            {
+                u4_temp = ((p_extended_cfg->p_speed_calc_timer_instance->p_cfg->period_counts - 1) -
+                           p_ctrl->u4_hall_timer_cnt) + p_ctrl->u4_pre_hall_timer_cnt;
+            }
+        }
+        else
+        {
+            u4_temp = p_ctrl->u4_hall_timer_cnt;
+        }
     }
 
     /* average 6 times of motor speed timer */
diff --git a/ra/fsp/src/rm_motor_120_control_sensorless/rm_motor_120_control_sensorless.c b/ra/fsp/src/rm_motor_120_control_sensorless/rm_motor_120_control_sensorless.c
index 60bb71b8e..6297415c8 100644
--- a/ra/fsp/src/rm_motor_120_control_sensorless/rm_motor_120_control_sensorless.c
+++ b/ra/fsp/src/rm_motor_120_control_sensorless/rm_motor_120_control_sensorless.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -229,6 +229,11 @@ fsp_err_t RM_MOTOR_120_CONTROL_SENSORLESS_Open (motor_120_control_ctrl_t * const
         p_extended_cfg->p_speed_calc_timer_instance->p_api->open(p_extended_cfg->p_speed_calc_timer_instance->p_ctrl,
                                                                  p_extended_cfg->p_speed_calc_timer_instance->p_cfg);
         p_extended_cfg->p_speed_calc_timer_instance->p_api->start(p_extended_cfg->p_speed_calc_timer_instance->p_ctrl);
+
+        timer_info_t timer_info;
+        p_extended_cfg->p_speed_calc_timer_instance->p_api->infoGet(p_extended_cfg->p_speed_calc_timer_instance->p_ctrl,
+                                                                    &timer_info);
+        p_instance_ctrl->timer_direction = timer_info.count_direction;
     }
 
     /* Mark driver as open */
@@ -1029,23 +1034,47 @@ static void rm_motor_120_control_sensorless_speed_calc (motor_120_control_sensor
                                                                 &gpt_timer_status);
     p_ctrl->u4_bemf_timer_cnt = gpt_timer_status.counter;
 
-    if (p_ctrl->u4_pre_bemf_timer_cnt != 0)
+    if (TIMER_DIRECTION_UP == p_ctrl->timer_direction)
     {
-        if (p_ctrl->u4_bemf_timer_cnt >= p_ctrl->u4_pre_bemf_timer_cnt)
+        if (p_ctrl->u4_pre_bemf_timer_cnt != 0)
         {
-            u4_temp = (p_ctrl->u4_bemf_timer_cnt - p_ctrl->u4_pre_bemf_timer_cnt);
+            if (p_ctrl->u4_bemf_timer_cnt >= p_ctrl->u4_pre_bemf_timer_cnt)
+            {
+                u4_temp = (p_ctrl->u4_bemf_timer_cnt - p_ctrl->u4_pre_bemf_timer_cnt);
 
-            /* calculate timer count in 60 degrees */
+                /* calculate timer count in 60 degrees */
+            }
+            else
+            {
+                u4_temp = ((p_extend_cfg->p_speed_calc_timer_instance->p_cfg->period_counts - 1) -
+                           p_ctrl->u4_pre_bemf_timer_cnt) + p_ctrl->u4_bemf_timer_cnt;
+            }
         }
         else
         {
-            u4_temp = ((p_extend_cfg->p_speed_calc_timer_instance->p_cfg->period_counts - 1) -
-                       p_ctrl->u4_pre_bemf_timer_cnt) + p_ctrl->u4_bemf_timer_cnt;
+            u4_temp = p_ctrl->u4_bemf_timer_cnt;
         }
     }
     else
     {
-        u4_temp = p_ctrl->u4_bemf_timer_cnt;
+        if (p_ctrl->u4_pre_bemf_timer_cnt != 0)
+        {
+            if (p_ctrl->u4_bemf_timer_cnt <= p_ctrl->u4_pre_bemf_timer_cnt)
+            {
+                u4_temp = (p_ctrl->u4_pre_bemf_timer_cnt - p_ctrl->u4_bemf_timer_cnt);
+
+                /* calculate timer count in 60 degrees */
+            }
+            else
+            {
+                u4_temp = ((p_extend_cfg->p_speed_calc_timer_instance->p_cfg->period_counts - 1) -
+                           p_ctrl->u4_bemf_timer_cnt) + p_ctrl->u4_pre_bemf_timer_cnt;
+            }
+        }
+        else
+        {
+            u4_temp = p_ctrl->u4_bemf_timer_cnt;
+        }
     }
 
     /* average 6 times of motor speed timer */
diff --git a/ra/fsp/src/rm_motor_120_degree/rm_motor_120_degree.c b/ra/fsp/src/rm_motor_120_degree/rm_motor_120_degree.c
index 340c990b2..e66af55a7 100644
--- a/ra/fsp/src/rm_motor_120_degree/rm_motor_120_degree.c
+++ b/ra/fsp/src/rm_motor_120_degree/rm_motor_120_degree.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -136,6 +136,7 @@ const motor_api_t g_motor_on_motor_120_degree =
     .speedGet        = RM_MOTOR_120_DEGREE_SpeedGet,
     .waitStopFlagGet = RM_MOTOR_120_DEGREE_WaitStopFlagGet,
     .errorCheck      = RM_MOTOR_120_DEGREE_ErrorCheck,
+    .functionSelect  = RM_MOTOR_120_DEGREE_FunctionSelect,
 };
 
 /*******************************************************************************************************************//**
@@ -574,8 +575,6 @@ fsp_err_t RM_MOTOR_120_DEGREE_ErrorCheck (motor_ctrl_t * const p_ctrl, uint16_t
 /*******************************************************************************************************************//**
  * @brief Set position reference. Implements @ref motor_api_t::positionSet.
  *
- * Example:
- *
  * @retval FSP_ERR_UNSUPPORTED      Unsupported.
  *
  * @note
@@ -593,8 +592,6 @@ fsp_err_t RM_MOTOR_120_DEGREE_PositionSet (motor_ctrl_t * const
 /*******************************************************************************************************************//**
  * @brief Set position reference. Implements @ref motor_api_t::angleGet.
  *
- * Example:
- *
  * @retval FSP_ERR_UNSUPPORTED      Unsupported.
  *
  * @note
@@ -608,6 +605,22 @@ fsp_err_t RM_MOTOR_120_DEGREE_AngleGet (motor_ctrl_t * const p_ctrl, float * con
     return FSP_ERR_UNSUPPORTED;
 }
 
+/*******************************************************************************************************************//**
+ * @brief Select using function. Implements @ref motor_api_t::functionSelect.
+ *
+ * @retval FSP_ERR_UNSUPPORTED      Unsupported.
+ *
+ * @note
+ *
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_120_DEGREE_FunctionSelect (motor_ctrl_t * const p_ctrl, motor_function_select_t const function)
+{
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+    FSP_PARAMETER_NOT_USED(function);
+
+    return FSP_ERR_UNSUPPORTED;
+}
+
 /*******************************************************************************************************************//**
  * @} (end addtogroup MOTOR_120_DEGREE)
  **********************************************************************************************************************/
@@ -804,19 +817,19 @@ static uint16_t rm_motor_120_degree_statemachine_event (motor_120_degree_instanc
 /***********************************************************************************************************************
  * Function Name : rm_motor_check_over_speed_error
  * Description   : Checks over-speed error
- * Arguments     : f4_speed_rad - The electrical speed[rad/s]
- *                 f4_speed_limit_rad - The speed[rad/s] threshold of the over-speed error, should be a positive value
+ * Arguments     : f4_speed - The electrical speed
+ *                 f4_speed_limit - The speed threshold of the over-speed error, should be a positive value
  * Return Value  : The over-speed error flag
  **********************************************************************************************************************/
-static inline uint16_t rm_motor_check_over_speed_error (float f4_speed_rad, float f4_speed_limit_rad)
+static inline uint16_t rm_motor_check_over_speed_error (float f4_speed, float f4_speed_limit)
 {
     float    f4_temp0;
     uint16_t u2_temp0;
 
     u2_temp0 = MOTOR_ERROR_NONE;
 
-    f4_temp0 = fabsf(f4_speed_rad);
-    if (f4_temp0 > f4_speed_limit_rad)
+    f4_temp0 = fabsf(f4_speed);
+    if (f4_temp0 > f4_speed_limit)
     {
         u2_temp0 = MOTOR_ERROR_OVER_SPEED;
     }
diff --git a/ra/fsp/src/rm_motor_120_driver/rm_motor_120_driver.c b/ra/fsp/src/rm_motor_120_driver/rm_motor_120_driver.c
index 392af3ea7..9fd7e9bf5 100644
--- a/ra/fsp/src/rm_motor_120_driver/rm_motor_120_driver.c
+++ b/ra/fsp/src/rm_motor_120_driver/rm_motor_120_driver.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_motor_current/rm_motor_current.c b/ra/fsp/src/rm_motor_current/rm_motor_current.c
index 7bb55d381..e49d1af9d 100644
--- a/ra/fsp/src/rm_motor_current/rm_motor_current.c
+++ b/ra/fsp/src/rm_motor_current/rm_motor_current.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -701,7 +701,7 @@ void rm_motor_current_cyclic (motor_driver_callback_args_t * p_args)
         /* Current Control Timing */
         case MOTOR_DRIVER_EVENT_CURRENT:
         {
-            /* Get A/D coverted data */
+            /* Get A/D converted data */
             p_driver_instance->p_api->currentGet(p_driver_instance->p_ctrl, &temp_drv_crnt_get);
             f_iu_ad  = temp_drv_crnt_get.iu;
             f_iw_ad  = temp_drv_crnt_get.iw;
diff --git a/ra/fsp/src/rm_motor_current/rm_motor_current_library.h b/ra/fsp/src/rm_motor_current/rm_motor_current_library.h
index 310ad2b27..d8c361d93 100644
--- a/ra/fsp/src/rm_motor_current/rm_motor_current_library.h
+++ b/ra/fsp/src/rm_motor_current/rm_motor_current_library.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_motor_driver/rm_motor_driver.c b/ra/fsp/src/rm_motor_driver/rm_motor_driver.c
index 1e6b6156e..06870599e 100644
--- a/ra/fsp/src/rm_motor_driver/rm_motor_driver.c
+++ b/ra/fsp/src/rm_motor_driver/rm_motor_driver.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -34,27 +34,27 @@
  * Macro definitions
  **********************************************************************************************************************/
 
-#define     MOTOR_DRIVER_OPEN             (0X4D445241L)
+#define     MOTOR_DRIVER_OPEN                   (0X4D445241L)
 
-#define     MOTOR_DRIVER_FLG_CLR          (0)     /* For flag clear */
-#define     MOTOR_DRIVER_FLG_SET          (1)     /* For flag set */
+#define     MOTOR_DRIVER_FLG_CLR                (0)     /* For flag clear */
+#define     MOTOR_DRIVER_FLG_SET                (1)     /* For flag set */
 
-#define     MOTOR_DRIVER_KHZ_TRANS        (1000U) /* x1000 */
+#define     MOTOR_DRIVER_KHZ_TRANS              (1000U) /* x1000 */
 
-#define     MOTOR_DRIVER_DEF_HALF         (0.5F)
-#define     MOTOR_DRIVER_MULTIPLE_TWO     (2.0F)
+#define     MOTOR_DRIVER_DEF_HALF               (0.5F)
+#define     MOTOR_DRIVER_MULTIPLE_TWO           (2.0F)
 
-#define     MOTOR_DRIVER_ADC_DATA_MASK    (0x00000FFF)
+#define     MOTOR_DRIVER_ADC_DATA_MASK          (0x00000FFF)
 
 /* Select SVPWM as default method when MOD_METHOD is undefined */
-#define     MOTOR_DRIVER_METHOD_SPWM      (0)      /* Sinusoidal pulse-width-modulation */
-#define     MOTOR_DRIVER_METHOD_SVPWM     (1)      /* Space vector pulse-width-modulation */
-#define     MOTOR_DRIVER_SATFLAG_BITU     (1 << 0) /* Saturation flag bit for U phase */
-#define     MOTOR_DRIVER_SATFLAG_BITV     (1 << 1) /* Saturation flag bit for V phase */
-#define     MOTOR_DRIVER_SATFLAG_BITW     (1 << 2) /* Saturation flag bit for W phase */
+#define     MOTOR_DRIVER_METHOD_SPWM            (0)      /* Sinusoidal pulse-width-modulation */
+#define     MOTOR_DRIVER_METHOD_SVPWM           (1)      /* Space vector pulse-width-modulation */
+#define     MOTOR_DRIVER_SATFLAG_BITU           (1 << 0) /* Saturation flag bit for U phase */
+#define     MOTOR_DRIVER_SATFLAG_BITV           (1 << 1) /* Saturation flag bit for V phase */
+#define     MOTOR_DRIVER_SATFLAG_BITW           (1 << 2) /* Saturation flag bit for W phase */
 
 #ifndef MOTOR_DRIVER_METHOD
- #define MOTOR_DRIVER_METHOD              (MOTOR_DRIVER_METHOD_SPWM)
+ #define MOTOR_DRIVER_METHOD                    (MOTOR_DRIVER_METHOD_SPWM)
 #endif
 
 /*
@@ -62,8 +62,13 @@
  *   SVPWM :  Vdc * (MOD_VDC_TO_VAMAX_MULT) * (Max duty - Min duty) * (MOD_SVPWM_MULT)
  *   SPWM  :  Vdc * (MOD_VDC_TO_VAMAX_MULT) * (Max duty - Min duty)
  */
-#define MOTOR_DRIVER_VDC_TO_VAMAX_MULT    (0.6124F) /* The basic coefficient used to convert Vdc to Vamax */
-#define MOTOR_DRIVER_SVPWM_MULT           (1.155F)  /* The usable voltage is multiplied by sqrt(4/3) when using SVPWM */
+#define MOTOR_DRIVER_VDC_TO_VAMAX_MULT          (0.6124F)   /* The basic coefficient used to convert Vdc to Vamax */
+#define MOTOR_DRIVER_SVPWM_MULT                 (1.155F)    /* The usable voltage is multiplied by sqrt(4/3) when using SVPWM */
+
+#define MOTOR_DRIVER_IO_PORT_CFG_LOW            (0x3000004) /* Set I/O port with low output */
+#define MOTOR_DRIVER_IO_PORT_CFG_HIGH           (0x3000005) /* Set I/O port with high output*/
+#define MOTOR_DRIVER_IO_PORT_PERIPHERAL_MASK    (0x0010000) /* Mask for pin to operate as a peripheral pin */
+#define MOTOR_DRIVER_IO_PORT_GPIO_MASK          (0xFFEFFFF) /* Mask for pin to operate as a GPIO pin */
 
 #ifndef MOTOR_DRIVER_ERROR_RETURN
  #define    MOTOR_DRIVER_ERROR_RETURN(a, err)    FSP_ERROR_RETURN((a), (err))
@@ -89,6 +94,10 @@ static void rm_motor_driver_1shunt_current_get(motor_driver_instance_ctrl_t * p_
 static void rm_motor_driver_modulation(motor_driver_instance_ctrl_t * p_ctrl);
 static void rm_motor_driver_1shunt_modulation(motor_driver_instance_ctrl_t * p_ctrl);
 
+static void rm_motor_driver_pin_cfg(bsp_io_port_pin_t pin, uint32_t cfg);
+static void rm_motor_driver_output_enable(motor_driver_instance_ctrl_t * p_ctrl);
+static void rm_motor_driver_output_disable(motor_driver_instance_ctrl_t * p_ctrl);
+
 /* Modulation functions */
 static void rm_motor_driver_mod_run(motor_driver_instance_ctrl_t * p_ctrl,
                                     const float                  * p_f4_v_in,
@@ -166,6 +175,35 @@ fsp_err_t RM_MOTOR_DRIVER_Open (motor_driver_ctrl_t * const p_ctrl, motor_driver
     /* Start GPT three phase module */
     if (p_cfg->p_three_phase_instance != NULL)
     {
+        /* For Port setting */
+        three_phase_instance_t const * p_three_phase;
+        timer_instance_t const       * p_u_phase_gpt;
+        timer_cfg_t const            * p_u_phase_gpt_cfg;
+        gpt_extended_cfg_t const     * p_u_phase_gpt_extend;
+
+        p_three_phase        = p_cfg->p_three_phase_instance;
+        p_u_phase_gpt        = p_three_phase->p_cfg->p_timer_instance[0];
+        p_u_phase_gpt_cfg    = p_u_phase_gpt->p_cfg;
+        p_u_phase_gpt_extend = p_u_phase_gpt_cfg->p_extend;
+
+        if (p_u_phase_gpt_extend->gtioca.stop_level == GPT_PIN_LEVEL_LOW)
+        {
+            p_instance_ctrl->u4_gtioca_low_cfg = MOTOR_DRIVER_IO_PORT_CFG_LOW;
+        }
+        else
+        {
+            p_instance_ctrl->u4_gtioca_low_cfg = MOTOR_DRIVER_IO_PORT_CFG_HIGH;
+        }
+
+        if (p_u_phase_gpt_extend->gtiocb.stop_level == GPT_PIN_LEVEL_HIGH)
+        {
+            p_instance_ctrl->u4_gtiocb_low_cfg = MOTOR_DRIVER_IO_PORT_CFG_LOW;
+        }
+        else
+        {
+            p_instance_ctrl->u4_gtiocb_low_cfg = MOTOR_DRIVER_IO_PORT_CFG_HIGH;
+        }
+
         p_cfg->p_three_phase_instance->p_api->open(p_cfg->p_three_phase_instance->p_ctrl,
                                                    p_cfg->p_three_phase_instance->p_cfg);
 
@@ -185,6 +223,11 @@ fsp_err_t RM_MOTOR_DRIVER_Open (motor_driver_ctrl_t * const p_ctrl, motor_driver
                                          p_instance_ctrl->st_modulation.f4_neutral_duty);
         }
 
+        if (p_extended_cfg->port_up != 0)
+        {
+            rm_motor_driver_output_disable(p_instance_ctrl);
+        }
+
         p_cfg->p_three_phase_instance->p_api->start(p_cfg->p_three_phase_instance->p_ctrl);
     }
 
@@ -247,7 +290,13 @@ fsp_err_t RM_MOTOR_DRIVER_Close (motor_driver_ctrl_t * const p_ctrl)
     MOTOR_DRIVER_ERROR_RETURN(MOTOR_DRIVER_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
 #endif
 
-    motor_driver_cfg_t * p_cfg = (motor_driver_cfg_t *) p_instance_ctrl->p_cfg;
+    motor_driver_cfg_t          * p_cfg          = (motor_driver_cfg_t *) p_instance_ctrl->p_cfg;
+    motor_driver_extended_cfg_t * p_extended_cfg = (motor_driver_extended_cfg_t *) p_cfg->p_extend;
+
+    if (p_extended_cfg->port_up != 0)
+    {
+        rm_motor_driver_output_disable(p_instance_ctrl);
+    }
 
     rm_motor_driver_reset(p_instance_ctrl);
 
@@ -292,6 +341,9 @@ fsp_err_t RM_MOTOR_DRIVER_Reset (motor_driver_ctrl_t * const p_ctrl)
     MOTOR_DRIVER_ERROR_RETURN(MOTOR_DRIVER_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
 #endif
 
+    motor_driver_cfg_t          * p_cfg          = (motor_driver_cfg_t *) p_instance_ctrl->p_cfg;
+    motor_driver_extended_cfg_t * p_extended_cfg = (motor_driver_extended_cfg_t *) p_cfg->p_extend;
+
     p_instance_ctrl->f_refu = p_instance_ctrl->st_modulation.f4_neutral_duty;
     p_instance_ctrl->f_refv = p_instance_ctrl->st_modulation.f4_neutral_duty;
     p_instance_ctrl->f_refw = p_instance_ctrl->st_modulation.f4_neutral_duty;
@@ -300,6 +352,12 @@ fsp_err_t RM_MOTOR_DRIVER_Reset (motor_driver_ctrl_t * const p_ctrl)
                                  p_instance_ctrl->st_modulation.f4_neutral_duty,
                                  p_instance_ctrl->st_modulation.f4_neutral_duty,
                                  p_instance_ctrl->st_modulation.f4_neutral_duty);
+
+    if (p_extended_cfg->port_up != 0)
+    {
+        rm_motor_driver_output_disable(p_instance_ctrl);
+    }
+
     rm_motor_driver_reset(p_instance_ctrl);
 
     return FSP_SUCCESS;
@@ -396,35 +454,39 @@ fsp_err_t RM_MOTOR_DRIVER_FlagCurrentOffsetGet (motor_driver_ctrl_t * const p_ct
     motor_driver_extended_cfg_t * p_extended_cfg =
         (motor_driver_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
 
+    /* Enable PWM output */
+    if (p_extended_cfg->port_up != 0)
+    {
+        rm_motor_driver_output_enable(p_instance_ctrl);
+    }
+
     /* Measure current A/D offset */
     if (MOTOR_DRIVER_FLG_CLR == p_instance_ctrl->u1_flag_offset_calc)
     {
         /* 2 or 3 shunt */
         if (MOTOR_DRIVER_SHUNT_TYPE_1_SHUNT != p_instance_ctrl->p_cfg->shunt)
         {
-            /* Output neautral PWM */
+            /* Output neutral PWM */
             rm_motor_driver_set_uvw_duty(p_instance_ctrl,
                                          p_instance_ctrl->st_modulation.f4_neutral_duty,
                                          p_instance_ctrl->st_modulation.f4_neutral_duty,
                                          p_instance_ctrl->st_modulation.f4_neutral_duty);
 
             u2_temp_offset_count = p_extended_cfg->u2_offset_calc_count;
-            if (MOTOR_DRIVER_FLG_CLR == p_instance_ctrl->u1_flag_offset_calc)
+
+            if (p_instance_ctrl->u2_offset_calc_times < u2_temp_offset_count)
             {
-                if (p_instance_ctrl->u2_offset_calc_times < u2_temp_offset_count)
-                {
-                    p_instance_ctrl->f_sum_iu_ad += p_instance_ctrl->f_iu_ad;
-                    p_instance_ctrl->f_sum_iv_ad += p_instance_ctrl->f_iv_ad;
-                    p_instance_ctrl->f_sum_iw_ad += p_instance_ctrl->f_iw_ad;
-                    p_instance_ctrl->u2_offset_calc_times++;
-                }
-                else
-                {
-                    p_instance_ctrl->f_offset_iu         = p_instance_ctrl->f_sum_iu_ad / u2_temp_offset_count;
-                    p_instance_ctrl->f_offset_iv         = p_instance_ctrl->f_sum_iv_ad / u2_temp_offset_count;
-                    p_instance_ctrl->f_offset_iw         = p_instance_ctrl->f_sum_iw_ad / u2_temp_offset_count;
-                    p_instance_ctrl->u1_flag_offset_calc = MOTOR_DRIVER_FLG_SET;
-                }
+                p_instance_ctrl->f_sum_iu_ad += p_instance_ctrl->f_iu_ad;
+                p_instance_ctrl->f_sum_iv_ad += p_instance_ctrl->f_iv_ad;
+                p_instance_ctrl->f_sum_iw_ad += p_instance_ctrl->f_iw_ad;
+                p_instance_ctrl->u2_offset_calc_times++;
+            }
+            else
+            {
+                p_instance_ctrl->f_offset_iu         = p_instance_ctrl->f_sum_iu_ad / u2_temp_offset_count;
+                p_instance_ctrl->f_offset_iv         = p_instance_ctrl->f_sum_iv_ad / u2_temp_offset_count;
+                p_instance_ctrl->f_offset_iw         = p_instance_ctrl->f_sum_iw_ad / u2_temp_offset_count;
+                p_instance_ctrl->u1_flag_offset_calc = MOTOR_DRIVER_FLG_SET;
             }
         }
         /* 1 shunt */
@@ -1048,6 +1110,85 @@ static void rm_motor_driver_1shunt_modulation (motor_driver_instance_ctrl_t * p_
     }
 }                                      /* End of function rm_motor_driver_1shunt_modulation */
 
+/***********************************************************************************************************************
+ * Function Name: rm_motor_driver_pin_cfg
+ * Description  : Configure a pin
+ * Arguments    : pin -
+ *                    The pin
+ *                cfg -
+ *                    Configuration for the pin (PmnPFS register setting)
+ * Return Value : None
+ **********************************************************************************************************************/
+static void rm_motor_driver_pin_cfg (bsp_io_port_pin_t pin, uint32_t cfg)
+{
+    R_BSP_PinAccessEnable();
+    R_BSP_PinCfg(pin, cfg);
+    R_BSP_PinAccessDisable();
+}                                      /* End of function rm_motor_driver_pin_cfg() */
+
+/***********************************************************************************************************************
+ * Function Name : rm_motor_driver_output_enable
+ * Description   : Enable PWM output
+ * Arguments     : p_ctrl - The pointer to the motor driver module instance
+ * Return Value  : None
+ **********************************************************************************************************************/
+static void rm_motor_driver_output_enable (motor_driver_instance_ctrl_t * p_ctrl)
+{
+    motor_driver_cfg_t           * p_cfg         = (motor_driver_cfg_t *) p_ctrl->p_cfg;
+    motor_driver_extended_cfg_t  * p_extended    = (motor_driver_extended_cfg_t *) p_cfg->p_extend;
+    three_phase_instance_t const * p_three_phase = p_cfg->p_three_phase_instance;
+    timer_instance_t const       * p_u_phase_gpt = p_three_phase->p_cfg->p_timer_instance[0];
+    timer_instance_t const       * p_v_phase_gpt = p_three_phase->p_cfg->p_timer_instance[1];
+    timer_instance_t const       * p_w_phase_gpt = p_three_phase->p_cfg->p_timer_instance[2];
+
+    p_ctrl->u4_gtioca_low_cfg |= MOTOR_DRIVER_IO_PORT_PERIPHERAL_MASK;
+    p_ctrl->u4_gtiocb_low_cfg |= MOTOR_DRIVER_IO_PORT_PERIPHERAL_MASK;
+
+    /* Set pin function */
+    rm_motor_driver_pin_cfg(p_extended->port_up, p_ctrl->u4_gtioca_low_cfg);
+    rm_motor_driver_pin_cfg(p_extended->port_un, p_ctrl->u4_gtiocb_low_cfg);
+    rm_motor_driver_pin_cfg(p_extended->port_vp, p_ctrl->u4_gtioca_low_cfg);
+    rm_motor_driver_pin_cfg(p_extended->port_vn, p_ctrl->u4_gtiocb_low_cfg);
+    rm_motor_driver_pin_cfg(p_extended->port_wp, p_ctrl->u4_gtioca_low_cfg);
+    rm_motor_driver_pin_cfg(p_extended->port_wn, p_ctrl->u4_gtiocb_low_cfg);
+
+    /* PWM output enable */
+    R_GPT_OutputEnable(p_u_phase_gpt->p_ctrl, GPT_IO_PIN_GTIOCA_AND_GTIOCB);
+    R_GPT_OutputEnable(p_v_phase_gpt->p_ctrl, GPT_IO_PIN_GTIOCA_AND_GTIOCB);
+    R_GPT_OutputEnable(p_w_phase_gpt->p_ctrl, GPT_IO_PIN_GTIOCA_AND_GTIOCB);
+}                                      /* End of function rm_motor_driver_output_enable */
+
+/***********************************************************************************************************************
+ * Function Name : rm_motor_driver_output_disable
+ * Description   : Disable PWM output
+ * Arguments     : p_ctrl - The pointer to the motor driver module instance
+ * Return Value  : None
+ **********************************************************************************************************************/
+static void rm_motor_driver_output_disable (motor_driver_instance_ctrl_t * p_ctrl)
+{
+    motor_driver_cfg_t           * p_cfg         = (motor_driver_cfg_t *) p_ctrl->p_cfg;
+    motor_driver_extended_cfg_t  * p_extended    = (motor_driver_extended_cfg_t *) p_cfg->p_extend;
+    three_phase_instance_t const * p_three_phase = p_cfg->p_three_phase_instance;
+    timer_instance_t const       * p_u_phase_gpt = p_three_phase->p_cfg->p_timer_instance[0];
+    timer_instance_t const       * p_v_phase_gpt = p_three_phase->p_cfg->p_timer_instance[1];
+    timer_instance_t const       * p_w_phase_gpt = p_three_phase->p_cfg->p_timer_instance[2];
+
+    /* PWM output disable */
+    R_GPT_OutputDisable(p_u_phase_gpt->p_ctrl, GPT_IO_PIN_GTIOCA_AND_GTIOCB);
+    R_GPT_OutputDisable(p_v_phase_gpt->p_ctrl, GPT_IO_PIN_GTIOCA_AND_GTIOCB);
+    R_GPT_OutputDisable(p_w_phase_gpt->p_ctrl, GPT_IO_PIN_GTIOCA_AND_GTIOCB);
+
+    p_ctrl->u4_gtioca_low_cfg &= MOTOR_DRIVER_IO_PORT_GPIO_MASK;
+    p_ctrl->u4_gtiocb_low_cfg &= MOTOR_DRIVER_IO_PORT_GPIO_MASK;
+
+    rm_motor_driver_pin_cfg(p_extended->port_up, p_ctrl->u4_gtioca_low_cfg);
+    rm_motor_driver_pin_cfg(p_extended->port_un, p_ctrl->u4_gtiocb_low_cfg);
+    rm_motor_driver_pin_cfg(p_extended->port_vp, p_ctrl->u4_gtioca_low_cfg);
+    rm_motor_driver_pin_cfg(p_extended->port_vn, p_ctrl->u4_gtiocb_low_cfg);
+    rm_motor_driver_pin_cfg(p_extended->port_wp, p_ctrl->u4_gtioca_low_cfg);
+    rm_motor_driver_pin_cfg(p_extended->port_wn, p_ctrl->u4_gtiocb_low_cfg);
+}                                      /* End of function rm_motor_driver_output_disable */
+
 /***********************************************************************************************************************
  * Function Name: rm_motor_driver_mod_svpwm
  * Description  : Space vector modulation
diff --git a/ra/fsp/src/rm_motor_encoder/rm_motor_encoder.c b/ra/fsp/src/rm_motor_encoder/rm_motor_encoder.c
index fba282318..e28fbc950 100644
--- a/ra/fsp/src/rm_motor_encoder/rm_motor_encoder.c
+++ b/ra/fsp/src/rm_motor_encoder/rm_motor_encoder.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -80,6 +80,10 @@ static void rm_motor_encoder_init_speed_output(motor_speed_output_t * p_output);
 static void rm_motor_encoder_copy_speed_current(motor_speed_output_t * p_output, motor_current_input_t * p_input);
 static void rm_motor_encoder_copy_current_speed(motor_current_output_t * p_output, motor_speed_input_t * p_input);
 
+static void rm_motor_encoder_inertia_estimate_current_process(motor_instance_t * p_instance);
+static void rm_motor_encoder_inertia_estimate_speed_process(motor_instance_t * p_instance);
+static void rm_motor_encoder_return_origin_speed_process(motor_instance_t * p_instance);
+
 /* Action functions */
 static motor_encoder_action_return_t rm_motor_encoder_active(motor_encoder_instance_ctrl_t * p_ctrl);
 static motor_encoder_action_return_t rm_motor_encoder_inactive(motor_encoder_instance_ctrl_t * p_ctrl);
@@ -145,6 +149,7 @@ const motor_api_t g_motor_on_encoder =
     .speedGet        = RM_MOTOR_ENCODER_SpeedGet,
     .errorCheck      = RM_MOTOR_ENCODER_ErrorCheck,
     .waitStopFlagGet = RM_MOTOR_ENCODER_WaitStopFlagGet,
+    .functionSelect  = RM_MOTOR_ENCODER_FunctionSelect,
 };
 
 /*******************************************************************************************************************//**
@@ -181,16 +186,21 @@ fsp_err_t RM_MOTOR_ENCODER_Open (motor_ctrl_t * const p_ctrl, motor_cfg_t const
 #if MOTOR_ENCODER_CFG_PARAM_CHECKING_ENABLE
     FSP_ASSERT(NULL != p_instance_ctrl);
     FSP_ASSERT(NULL != p_cfg);
-    MOTOR_ENCODER_ERROR_RETURN(MOTOR_ENCODER_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
 
     /* Using modules' instance check */
     MOTOR_ENCODER_ERROR_RETURN(NULL != p_cfg->p_motor_speed_instance, FSP_ERR_ASSERTION);
     MOTOR_ENCODER_ERROR_RETURN(NULL != p_cfg->p_motor_current_instance, FSP_ERR_ASSERTION);
 
     MOTOR_ENCODER_ERROR_RETURN(NULL != p_cfg->p_extend, FSP_ERR_ASSERTION);
+#endif
 
     motor_encoder_extended_cfg_t * p_extended_cfg = (motor_encoder_extended_cfg_t *) p_cfg->p_extend;
 
+#if MOTOR_ENCODER_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_extended_cfg);
+
+    MOTOR_ENCODER_ERROR_RETURN(MOTOR_ENCODER_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
+
     MOTOR_ENCODER_ERROR_RETURN(p_extended_cfg->f_overcurrent_limit >= 0.0F, FSP_ERR_INVALID_ARGUMENT);
     MOTOR_ENCODER_ERROR_RETURN(p_extended_cfg->f_overvoltage_limit >= 0.0F, FSP_ERR_INVALID_ARGUMENT);
     MOTOR_ENCODER_ERROR_RETURN(p_extended_cfg->f_overspeed_limit >= 0.0F, FSP_ERR_INVALID_ARGUMENT);
@@ -208,6 +218,24 @@ fsp_err_t RM_MOTOR_ENCODER_Open (motor_ctrl_t * const p_ctrl, motor_cfg_t const
         {
             p_instance_ctrl->p_cfg = p_cfg;
 
+            // Open Inertia estimate when supported
+            if (p_extended_cfg->p_motor_inertia_estimate_instance != NULL)
+            {
+                err = p_extended_cfg->p_motor_inertia_estimate_instance->p_api->open(
+                    p_extended_cfg->p_motor_inertia_estimate_instance->p_ctrl,
+                    p_extended_cfg->p_motor_inertia_estimate_instance->p_cfg);
+            }
+
+            // Open Return origin function when supported
+            if (p_extended_cfg->p_motor_return_origin_instance != NULL)
+            {
+                err = p_extended_cfg->p_motor_return_origin_instance->p_api->open(
+                    p_extended_cfg->p_motor_return_origin_instance->p_ctrl,
+                    p_extended_cfg->p_motor_return_origin_instance->p_cfg);
+            }
+
+            p_instance_ctrl->e_function = MOTOR_FUNCTION_SELECT_NONE;
+
             p_instance_ctrl->u2_error_info = MOTOR_ERROR_NONE;
 
             rm_motor_encoder_init_speed_input(&(p_instance_ctrl->st_speed_input));
@@ -246,6 +274,12 @@ fsp_err_t RM_MOTOR_ENCODER_Close (motor_ctrl_t * const p_ctrl)
     MOTOR_ENCODER_ERROR_RETURN(MOTOR_ENCODER_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
 #endif
 
+    motor_encoder_extended_cfg_t * p_extended_cfg = (motor_encoder_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+
+#if MOTOR_ENCODER_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_extended_cfg);
+#endif
+
     /* Close using modules */
     err = p_instance_ctrl->p_cfg->p_motor_speed_instance->p_api->close(
         p_instance_ctrl->p_cfg->p_motor_speed_instance->p_ctrl);
@@ -255,6 +289,20 @@ fsp_err_t RM_MOTOR_ENCODER_Close (motor_ctrl_t * const p_ctrl)
         err = p_instance_ctrl->p_cfg->p_motor_current_instance->p_api->close(
             p_instance_ctrl->p_cfg->p_motor_current_instance->p_ctrl);
 
+        // Close Inertia estimate when supported
+        if (p_extended_cfg->p_motor_inertia_estimate_instance != NULL)
+        {
+            err = p_extended_cfg->p_motor_inertia_estimate_instance->p_api->close(
+                p_extended_cfg->p_motor_inertia_estimate_instance->p_ctrl);
+        }
+
+        // Close Return origin function when supported
+        if (p_extended_cfg->p_motor_return_origin_instance != NULL)
+        {
+            err = p_extended_cfg->p_motor_return_origin_instance->p_api->close(
+                p_extended_cfg->p_motor_return_origin_instance->p_ctrl);
+        }
+
         if (FSP_SUCCESS == err)
         {
             rm_motor_encoder_init_speed_input(&(p_instance_ctrl->st_speed_input));
@@ -328,7 +376,10 @@ fsp_err_t RM_MOTOR_ENCODER_Run (motor_ctrl_t * const p_ctrl)
     MOTOR_ENCODER_ERROR_RETURN(MOTOR_ENCODER_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
 #endif
 
-    rm_motor_encoder_statemachine_event(p_instance_ctrl, MOTOR_ENCODER_CTRL_EVENT_RUN);
+    if (MOTOR_FUNCTION_SELECT_NONE == p_instance_ctrl->e_function)
+    {
+        rm_motor_encoder_statemachine_event(p_instance_ctrl, MOTOR_ENCODER_CTRL_EVENT_RUN);
+    }
 
     return err;
 }
@@ -356,7 +407,10 @@ fsp_err_t RM_MOTOR_ENCODER_Stop (motor_ctrl_t * const p_ctrl)
     MOTOR_ENCODER_ERROR_RETURN(MOTOR_ENCODER_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
 #endif
 
-    rm_motor_encoder_statemachine_event(p_instance_ctrl, MOTOR_ENCODER_CTRL_EVENT_STOP);
+    if (MOTOR_FUNCTION_SELECT_NONE == p_instance_ctrl->e_function)
+    {
+        rm_motor_encoder_statemachine_event(p_instance_ctrl, MOTOR_ENCODER_CTRL_EVENT_STOP);
+    }
 
     return err;
 }
@@ -446,9 +500,12 @@ fsp_err_t RM_MOTOR_ENCODER_PositionSet (motor_ctrl_t * const
     MOTOR_ENCODER_ERROR_RETURN(p_position != NULL, FSP_ERR_INVALID_ARGUMENT);
 #endif
 
-    err = p_instance_ctrl->p_cfg->p_motor_speed_instance->p_api->positionReferenceSet(
-        p_instance_ctrl->p_cfg->p_motor_speed_instance->p_ctrl,
-        p_position);
+    if (MOTOR_FUNCTION_SELECT_NONE == p_instance_ctrl->e_function)
+    {
+        err = p_instance_ctrl->p_cfg->p_motor_speed_instance->p_api->positionReferenceSet(
+            p_instance_ctrl->p_cfg->p_motor_speed_instance->p_ctrl,
+            p_position);
+    }
 
     return err;
 }
@@ -650,6 +707,267 @@ fsp_err_t RM_MOTOR_ENCODER_WaitStopFlagGet (motor_ctrl_t * const p_ctrl, motor_w
     return FSP_ERR_UNSUPPORTED;
 }
 
+/*******************************************************************************************************************//**
+ * @brief Select using function. Implements @ref motor_api_t::functionSelect.
+ *
+ * @retval FSP_SUCCESS              Successfully resetted.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ * @retval FSP_ERR_INVALID_MODE     Mode unmatch
+ *
+ * @note
+ *
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_ENCODER_FunctionSelect (motor_ctrl_t * const p_ctrl, motor_function_select_t const function)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    motor_encoder_instance_ctrl_t * p_instance_ctrl = (motor_encoder_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_ENCODER_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_instance_ctrl);
+    MOTOR_ENCODER_ERROR_RETURN(MOTOR_ENCODER_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    switch (p_instance_ctrl->e_function)
+    {
+        default:
+        {
+            /* Do nothing */
+            break;
+        }
+
+        case MOTOR_FUNCTION_SELECT_NONE:
+        {
+            if (MOTOR_FUNCTION_SELECT_NONE == function)
+            {
+                err = FSP_ERR_INVALID_MODE;
+            }
+            else
+            {
+                p_instance_ctrl->e_function = function;
+
+                /* Run */
+                rm_motor_encoder_active(p_instance_ctrl);
+            }
+
+            break;
+        }
+
+        case MOTOR_FUNCTION_SELECT_INERTIA_ESTIMATE:
+        {
+            if (MOTOR_FUNCTION_SELECT_NONE == function)
+            {
+                p_instance_ctrl->e_function = function;
+
+                /* Stop */
+                rm_motor_encoder_inactive(p_instance_ctrl);
+            }
+            else
+            {
+                err = FSP_ERR_INVALID_MODE;
+            }
+
+            break;
+        }
+
+        case MOTOR_FUNCTION_SELECT_RETURN_ORIGIN:
+        {
+            if (MOTOR_FUNCTION_SELECT_NONE == function)
+            {
+                p_instance_ctrl->e_function = function;
+
+                /* Stop */
+                rm_motor_encoder_inactive(p_instance_ctrl);
+            }
+            else
+            {
+                err = FSP_ERR_INVALID_MODE;
+            }
+
+            break;
+        }
+    }
+
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Start inertia estimation function.
+ *
+ * @retval FSP_SUCCESS              Successfully resetted.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ * @retval FSP_ERR_INVALID_MODE     Mode unmatch
+ *
+ * @note
+ *
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_ENCODER_InertiaEstimateStart (motor_ctrl_t * const p_ctrl)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    motor_encoder_instance_ctrl_t * p_instance_ctrl = (motor_encoder_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_ENCODER_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_instance_ctrl);
+    MOTOR_ENCODER_ERROR_RETURN(MOTOR_ENCODER_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    motor_encoder_extended_cfg_t * p_extended_cfg = (motor_encoder_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+
+#if MOTOR_ENCODER_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_extended_cfg);
+#endif
+
+    /* Only effective when Inertia estimation is selected */
+    if (MOTOR_FUNCTION_SELECT_INERTIA_ESTIMATE == p_instance_ctrl->e_function)
+    {
+        if (p_extended_cfg->p_motor_inertia_estimate_instance != NULL)
+        {
+            err = p_extended_cfg->p_motor_inertia_estimate_instance->p_api->start(
+                p_extended_cfg->p_motor_inertia_estimate_instance->p_ctrl);
+        }
+    }
+    else
+    {
+        err = FSP_ERR_INVALID_MODE;
+    }
+
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Stop(Cancel) inertia estimation function.
+ *
+ * @retval FSP_SUCCESS              Successfully resetted.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ * @retval FSP_ERR_INVALID_MODE     Mode unmatch
+ *
+ * @note
+ *
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_ENCODER_InertiaEstimateStop (motor_ctrl_t * const p_ctrl)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    motor_encoder_instance_ctrl_t * p_instance_ctrl = (motor_encoder_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_ENCODER_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_instance_ctrl);
+    MOTOR_ENCODER_ERROR_RETURN(MOTOR_ENCODER_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    motor_encoder_extended_cfg_t * p_extended_cfg = (motor_encoder_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+
+#if MOTOR_ENCODER_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_extended_cfg);
+#endif
+
+    /* Only effective when Inertia estimation is selected */
+    if (MOTOR_FUNCTION_SELECT_INERTIA_ESTIMATE == p_instance_ctrl->e_function)
+    {
+        if (p_extended_cfg->p_motor_inertia_estimate_instance != NULL)
+        {
+            err = p_extended_cfg->p_motor_inertia_estimate_instance->p_api->stop(
+                p_extended_cfg->p_motor_inertia_estimate_instance->p_ctrl);
+        }
+    }
+    else
+    {
+        err = FSP_ERR_INVALID_MODE;
+    }
+
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Start return origin function.
+ *
+ * @retval FSP_SUCCESS              Successfully resetted.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ * @retval FSP_ERR_INVALID_MODE     Mode unmatch
+ *
+ * @note
+ *
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_ENCODER_ReturnOriginStart (motor_ctrl_t * const p_ctrl)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    motor_encoder_instance_ctrl_t * p_instance_ctrl = (motor_encoder_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_ENCODER_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_instance_ctrl);
+    MOTOR_ENCODER_ERROR_RETURN(MOTOR_ENCODER_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    motor_encoder_extended_cfg_t * p_extended_cfg =
+        (motor_encoder_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+
+#if MOTOR_ENCODER_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_extended_cfg);
+#endif
+
+    /* Only effective when Return origin is selected */
+    if (MOTOR_FUNCTION_SELECT_RETURN_ORIGIN == p_instance_ctrl->e_function)
+    {
+        if (p_extended_cfg->p_motor_return_origin_instance != NULL)
+        {
+            err = p_extended_cfg->p_motor_return_origin_instance->p_api->start(
+                p_extended_cfg->p_motor_return_origin_instance->p_ctrl);
+        }
+    }
+    else
+    {
+        err = FSP_ERR_INVALID_MODE;
+    }
+
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Stop(Cancel) return origin function.
+ *
+ * @retval FSP_SUCCESS              Successfully resetted.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ * @retval FSP_ERR_INVALID_MODE     Mode unmatch
+ *
+ * @note
+ *
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_ENCODER_ReturnOriginStop (motor_ctrl_t * const p_ctrl)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    motor_encoder_instance_ctrl_t * p_instance_ctrl = (motor_encoder_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_ENCODER_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_instance_ctrl);
+    MOTOR_ENCODER_ERROR_RETURN(MOTOR_ENCODER_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    motor_encoder_extended_cfg_t * p_extended_cfg = (motor_encoder_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+
+#if MOTOR_ENCODER_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_extended_cfg);
+#endif
+
+    /* Only effective when Return origin is selected */
+    if (MOTOR_FUNCTION_SELECT_RETURN_ORIGIN == p_instance_ctrl->e_function)
+    {
+        if (p_extended_cfg->p_motor_return_origin_instance != NULL)
+        {
+            err = p_extended_cfg->p_motor_return_origin_instance->p_api->stop(
+                p_extended_cfg->p_motor_return_origin_instance->p_ctrl);
+        }
+    }
+    else
+    {
+        err = FSP_ERR_INVALID_MODE;
+    }
+
+    return err;
+}
+
 /*******************************************************************************************************************//**
  * @} (end addtogroup MOTOR_ENCODER)
  **********************************************************************************************************************/
@@ -853,19 +1171,19 @@ static uint32_t rm_motor_encoder_statemachine_event (motor_encoder_instance_ctrl
 /***********************************************************************************************************************
  * Function Name : rm_motor_check_over_speed_error
  * Description   : Checks over-speed error
- * Arguments     : f4_speed_rad - The electrical speed[rad/s]
- *                 f4_speed_limit_rad - The speed[rad/s] threshold of the over-speed error, should be a positive value
+ * Arguments     : f4_speed - The electrical speed
+ *                 f4_speed_limit - The speed
  * Return Value  : The over-speed error flag
  **********************************************************************************************************************/
-static inline uint16_t rm_motor_check_over_speed_error (float f4_speed_rad, float f4_speed_limit_rad)
+static inline uint16_t rm_motor_check_over_speed_error (float f4_speed, float f4_speed_limit)
 {
     float    f4_temp0;
     uint16_t u2_temp0;
 
     u2_temp0 = MOTOR_ERROR_NONE;
 
-    f4_temp0 = fabsf(f4_speed_rad);
-    if (f4_temp0 > f4_speed_limit_rad)
+    f4_temp0 = fabsf(f4_speed);
+    if (f4_temp0 > f4_speed_limit)
     {
         u2_temp0 = MOTOR_ERROR_OVER_SPEED;
     }
@@ -1031,6 +1349,114 @@ static void rm_motor_encoder_init_speed_output (motor_speed_output_t * p_output)
     p_output->u1_flag_pi = MOTOR_ENCODER_FLAG_CLEAR;
 }                                      /* End of function rm_motor_encoder_init_speed_output() */
 
+/***********************************************************************************************************************
+ * Function Name : rm_motor_encoder_inertia_estimate_current_process
+ * Description   : Inertia estimate process in current cyclic
+ * Arguments     : p_instance - motor instance pointer
+ * Return Value  : None
+ **********************************************************************************************************************/
+static void rm_motor_encoder_inertia_estimate_current_process (motor_instance_t * p_instance)
+{
+    motor_encoder_instance_ctrl_t   * p_ctrl         = (motor_encoder_instance_ctrl_t *) p_instance->p_ctrl;
+    motor_encoder_extended_cfg_t    * p_extended_cfg = (motor_encoder_extended_cfg_t *) p_ctrl->p_cfg->p_extend;
+    motor_position_instance_t const * p_position     =
+        (motor_position_instance_t *) p_instance->p_cfg->p_motor_speed_instance->p_cfg->p_position_instance;
+    motor_position_info_t temp_position_info;
+    motor_inertia_estimate_instance_t const * p_ie_instance = p_extended_cfg->p_motor_inertia_estimate_instance;
+
+    if (p_ie_instance != NULL)
+    {
+        if (MOTOR_FUNCTION_SELECT_INERTIA_ESTIMATE == p_ctrl->e_function)
+        {
+            p_ctrl->st_ie_set_data.f_iq = p_ctrl->st_current_output.f_iq;
+            p_ctrl->st_ie_set_data.f_speed_radian_control = p_ctrl->st_current_input.f_ref_speed_rad_ctrl;
+
+            p_position->p_api->infoGet(p_position->p_ctrl, &temp_position_info);
+
+            p_ctrl->st_ie_set_data.s2_position_degree = temp_position_info.s2_position_degree;
+            p_ctrl->st_ie_set_data.u1_position_state  = temp_position_info.u1_state_position_profile;
+
+            p_ie_instance->p_api->dataSet(p_ie_instance->p_ctrl, &(p_ctrl->st_ie_set_data));
+            p_ie_instance->p_api->infoGet(p_ie_instance->p_ctrl, &(p_ctrl->st_ie_get_data));
+            p_ie_instance->p_api->currentCyclic(p_ie_instance->p_ctrl);
+        }
+    }
+}                                      /* End of function rm_motor_encoder_inertia_estimate_current_process() */
+
+/***********************************************************************************************************************
+ * Function Name : rm_motor_encoder_inertia_estimate_speed_process
+ * Description   : Inertia estimate process in speed cyclic
+ * Arguments     : p_instance - motor instance pointer
+ * Return Value  : None
+ **********************************************************************************************************************/
+static void rm_motor_encoder_inertia_estimate_speed_process (motor_instance_t * p_instance)
+{
+    motor_encoder_instance_ctrl_t           * p_ctrl         = (motor_encoder_instance_ctrl_t *) p_instance->p_ctrl;
+    motor_encoder_extended_cfg_t            * p_extended_cfg = (motor_encoder_extended_cfg_t *) p_ctrl->p_cfg->p_extend;
+    motor_inertia_estimate_instance_t const * p_ie_instance  = p_extended_cfg->p_motor_inertia_estimate_instance;
+    motor_speed_position_data_t               temp_position_data;
+
+    if (p_ie_instance != NULL)
+    {
+        if (MOTOR_FUNCTION_SELECT_INERTIA_ESTIMATE == p_ctrl->e_function)
+        {
+            p_ie_instance->p_api->speedCyclic(p_ie_instance->p_ctrl);
+
+            temp_position_data.e_step_mode               = MOTOR_SPEED_STEP_DISABLE;
+            temp_position_data.e_loop_mode               = MOTOR_SPEED_LOOP_MODE_POSITION;
+            temp_position_data.position_reference_degree =
+                p_ctrl->st_ie_get_data.s2_position_reference_degree;
+
+            /* Set position reference */
+            p_instance->p_cfg->p_motor_speed_instance->p_api->positionReferenceSet(
+                p_instance->p_cfg->p_motor_speed_instance->p_ctrl,
+                &temp_position_data);
+        }
+    }
+}                                      /* End of function rm_motor_encoder_inertia_estimate_speed_process() */
+
+/***********************************************************************************************************************
+ * Function Name : rm_motor_encoder_return_origin_speed_process
+ * Description   : Return origin process in speed cyclic
+ * Arguments     : p_instance - motor instance pointer
+ * Return Value  : None
+ **********************************************************************************************************************/
+static void rm_motor_encoder_return_origin_speed_process (motor_instance_t * p_instance)
+{
+    motor_encoder_instance_ctrl_t        * p_ctrl         = (motor_encoder_instance_ctrl_t *) p_instance->p_ctrl;
+    motor_encoder_extended_cfg_t         * p_extended_cfg = (motor_encoder_extended_cfg_t *) p_ctrl->p_cfg->p_extend;
+    motor_return_origin_instance_t const * p_ro_instance  = p_extended_cfg->p_motor_return_origin_instance;
+    motor_speed_position_data_t            temp_position_data;
+    int16_t s2_temp_position;
+
+    /* Return origin process */
+    if (p_ro_instance != NULL)
+    {
+        if (MOTOR_FUNCTION_SELECT_RETURN_ORIGIN == p_ctrl->e_function)
+        {
+            p_ctrl->st_ro_set_data.f_iq = p_ctrl->st_current_output.f_iq;
+            p_instance->p_cfg->p_motor_speed_instance->p_cfg->p_position_instance->p_api->positionGet(
+                p_instance->p_cfg->p_motor_speed_instance->p_cfg->p_position_instance->p_ctrl,
+                &s2_temp_position);
+            p_ctrl->st_ro_set_data.f_position_degree = (float) s2_temp_position;
+            p_ro_instance->p_api->dataSet(p_ro_instance->p_ctrl, &(p_ctrl->st_ro_set_data));
+
+            p_ro_instance->p_api->speedCyclic(p_ro_instance->p_ctrl);
+            p_ro_instance->p_api->infoGet(p_ro_instance->p_ctrl, &(p_ctrl->st_ro_info));
+
+            temp_position_data.e_step_mode               = MOTOR_SPEED_STEP_ENABLE;
+            temp_position_data.e_loop_mode               = MOTOR_SPEED_LOOP_MODE_POSITION;
+            temp_position_data.position_reference_degree =
+                (int16_t) p_ctrl->st_ro_info.f_position_reference_degree;
+
+            /* Set position reference */
+            p_instance->p_cfg->p_motor_speed_instance->p_api->positionReferenceSet(
+                p_instance->p_cfg->p_motor_speed_instance->p_ctrl,
+                &temp_position_data);
+        }
+    }
+}                                      /* End of function rm_motor_encoder_return_origin_speed_process() */
+
 /* Callback function */
 
 /***********************************************************************************************************************
@@ -1071,6 +1497,8 @@ void rm_motor_encoder_current_callback (motor_current_callback_args_t * p_args)
 
         case MOTOR_CURRENT_EVENT_BACKWARD:
         {
+            rm_motor_encoder_inertia_estimate_current_process(p_instance);
+
             /* Invoke the callback function if it is set. */
             if (NULL != p_ctrl->p_cfg->p_callback)
             {
@@ -1124,6 +1552,9 @@ void rm_motor_encoder_speed_callback (motor_speed_callback_args_t * p_args)
 
         case MOTOR_SPEED_EVENT_BACKWARD:
         {
+            rm_motor_encoder_inertia_estimate_speed_process(p_instance);
+            rm_motor_encoder_return_origin_speed_process(p_instance);
+
             /* Invoke the callback function if it is set. */
             if (NULL != p_ctrl->p_cfg->p_callback)
             {
diff --git a/ra/fsp/src/rm_motor_estimate/rm_motor_estimate.c b/ra/fsp/src/rm_motor_estimate/rm_motor_estimate.c
index acfd7b9ae..ca9d1fde6 100644
--- a/ra/fsp/src/rm_motor_estimate/rm_motor_estimate.c
+++ b/ra/fsp/src/rm_motor_estimate/rm_motor_estimate.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_motor_hall/rm_motor_hall.c b/ra/fsp/src/rm_motor_hall/rm_motor_hall.c
index efb2efbae..27799223c 100644
--- a/ra/fsp/src/rm_motor_hall/rm_motor_hall.c
+++ b/ra/fsp/src/rm_motor_hall/rm_motor_hall.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -139,6 +139,7 @@ const motor_api_t g_motor_on_motor_hall =
     .errorCheck      = RM_MOTOR_HALL_ErrorCheck,
     .positionSet     = RM_MOTOR_HALL_PositionSet,
     .waitStopFlagGet = RM_MOTOR_HALL_WaitStopFlagGet,
+    .functionSelect  = RM_MOTOR_HALL_FunctionSelect,
 };
 
 /*******************************************************************************************************************//**
@@ -594,8 +595,6 @@ fsp_err_t RM_MOTOR_HALL_ErrorCheck (motor_ctrl_t * const p_ctrl, uint16_t * cons
 /*******************************************************************************************************************//**
  * @brief Set position reference. Implements @ref motor_api_t::positionSet.
  *
- * Example:
- *
  * @retval FSP_ERR_UNSUPPORTED      Unsupported.
  *
  * @note
@@ -612,8 +611,6 @@ fsp_err_t RM_MOTOR_HALL_PositionSet (motor_ctrl_t * const p_ctrl, motor_speed_po
 /*******************************************************************************************************************//**
  * @brief Get wait stop flag. Implements @ref motor_api_t::waitStopFlagGet.
  *
- * Example:
- *
  * @retval FSP_ERR_UNSUPPORTED      Unsupported.
  *
  * @note
@@ -627,6 +624,22 @@ fsp_err_t RM_MOTOR_HALL_WaitStopFlagGet (motor_ctrl_t * const p_ctrl, motor_wait
     return FSP_ERR_UNSUPPORTED;
 }
 
+/*******************************************************************************************************************//**
+ * @brief Select function. Implements @ref motor_api_t::functionSelect.
+ *
+ * @retval FSP_ERR_UNSUPPORTED      Unsupported.
+ *
+ * @note
+ *
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_HALL_FunctionSelect (motor_ctrl_t * const p_ctrl, motor_function_select_t const function)
+{
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+    FSP_PARAMETER_NOT_USED(function);
+
+    return FSP_ERR_UNSUPPORTED;
+}
+
 /*******************************************************************************************************************//**
  * @} (end addtogroup MOTOR_HALL)
  **********************************************************************************************************************/
@@ -828,19 +841,19 @@ static uint16_t rm_motor_hall_statemachine_event (motor_hall_instance_ctrl_t * p
 /***********************************************************************************************************************
  * Function Name : rm_motor_check_over_speed_error
  * Description   : Checks over-speed error
- * Arguments     : f4_speed_rad - The electrical speed[rad/s]
- *                 f4_speed_limit_rad - The speed[rad/s] threshold of the over-speed error, should be a positive value
+ * Arguments     : f4_speed - The electrical speed
+ *                 f4_speed_limit - The speed threshold of the over-speed error, should be a positive value
  * Return Value  : The over-speed error flag
  **********************************************************************************************************************/
-static inline uint16_t rm_motor_check_over_speed_error (float f4_speed_rad, float f4_speed_limit_rad)
+static inline uint16_t rm_motor_check_over_speed_error (float f4_speed, float f4_speed_limit)
 {
     float    f4_temp0;
     uint16_t u2_temp0;
 
     u2_temp0 = MOTOR_ERROR_NONE;
 
-    f4_temp0 = fabsf(f4_speed_rad);
-    if (f4_temp0 > f4_speed_limit_rad)
+    f4_temp0 = fabsf(f4_speed);
+    if (f4_temp0 > f4_speed_limit)
     {
         u2_temp0 = MOTOR_ERROR_OVER_SPEED;
     }
diff --git a/ra/fsp/src/rm_motor_induction/rm_motor_induction.c b/ra/fsp/src/rm_motor_induction/rm_motor_induction.c
index 6476a3205..c83fdbc53 100644
--- a/ra/fsp/src/rm_motor_induction/rm_motor_induction.c
+++ b/ra/fsp/src/rm_motor_induction/rm_motor_induction.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -81,6 +81,10 @@ static void rm_motor_induction_init_speed_output(motor_speed_output_t * p_output
 static void rm_motor_induction_copy_speed_current(motor_speed_output_t * p_output, motor_current_input_t * p_input);
 static void rm_motor_induction_copy_current_speed(motor_current_output_t * p_output, motor_speed_input_t * p_input);
 
+static void rm_motor_induction_inertia_estimate_current_process(motor_instance_t * p_instance);
+static void rm_motor_induction_inertia_estimate_speed_process(motor_instance_t * p_instance);
+static void rm_motor_induction_return_origin_speed_process(motor_instance_t * p_instance);
+
 /* Action functions */
 static motor_induction_action_return_t rm_motor_induction_active(motor_induction_instance_ctrl_t * p_ctrl);
 static motor_induction_action_return_t rm_motor_induction_inactive(motor_induction_instance_ctrl_t * p_ctrl);
@@ -145,6 +149,7 @@ const motor_api_t g_motor_on_motor_induction =
     .speedGet        = RM_MOTOR_INDUCTION_SpeedGet,
     .errorCheck      = RM_MOTOR_INDUCTION_ErrorCheck,
     .waitStopFlagGet = RM_MOTOR_INDUCTION_WaitStopFlagGet,
+    .functionSelect  = RM_MOTOR_INDUCTION_FunctionSelect,
 };
 
 /*******************************************************************************************************************//**
@@ -181,16 +186,21 @@ fsp_err_t RM_MOTOR_INDUCTION_Open (motor_ctrl_t * const p_ctrl, motor_cfg_t cons
 #if MOTOR_INDUCTION_CFG_PARAM_CHECKING_ENABLE
     FSP_ASSERT(NULL != p_instance_ctrl);
     FSP_ASSERT(NULL != p_cfg);
-    MOTOR_INDUCTION_ERROR_RETURN(MOTOR_INDUCTION_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
 
     /* Using modules' instance check */
     MOTOR_INDUCTION_ERROR_RETURN(NULL != p_cfg->p_motor_speed_instance, FSP_ERR_ASSERTION);
     MOTOR_INDUCTION_ERROR_RETURN(NULL != p_cfg->p_motor_current_instance, FSP_ERR_ASSERTION);
 
     MOTOR_INDUCTION_ERROR_RETURN(NULL != p_cfg->p_extend, FSP_ERR_ASSERTION);
+#endif
 
     motor_induction_extended_cfg_t * p_extended_cfg = (motor_induction_extended_cfg_t *) p_cfg->p_extend;
 
+#if MOTOR_INDUCTION_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_extended_cfg);
+
+    MOTOR_INDUCTION_ERROR_RETURN(MOTOR_INDUCTION_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
+
     MOTOR_INDUCTION_ERROR_RETURN(p_extended_cfg->f_overcurrent_limit >= 0.0F, FSP_ERR_INVALID_ARGUMENT);
     MOTOR_INDUCTION_ERROR_RETURN(p_extended_cfg->f_overvoltage_limit >= 0.0F, FSP_ERR_INVALID_ARGUMENT);
     MOTOR_INDUCTION_ERROR_RETURN(p_extended_cfg->f_overspeed_limit >= 0.0F, FSP_ERR_INVALID_ARGUMENT);
@@ -208,6 +218,24 @@ fsp_err_t RM_MOTOR_INDUCTION_Open (motor_ctrl_t * const p_ctrl, motor_cfg_t cons
         {
             p_instance_ctrl->p_cfg = p_cfg;
 
+            // Open Inertia estimate when supported
+            if (p_extended_cfg->p_motor_inertia_estimate_instance != NULL)
+            {
+                err = p_extended_cfg->p_motor_inertia_estimate_instance->p_api->open(
+                    p_extended_cfg->p_motor_inertia_estimate_instance->p_ctrl,
+                    p_extended_cfg->p_motor_inertia_estimate_instance->p_cfg);
+            }
+
+            // Open Return origin function when supported
+            if (p_extended_cfg->p_motor_return_origin_instance != NULL)
+            {
+                err = p_extended_cfg->p_motor_return_origin_instance->p_api->open(
+                    p_extended_cfg->p_motor_return_origin_instance->p_ctrl,
+                    p_extended_cfg->p_motor_return_origin_instance->p_cfg);
+            }
+
+            p_instance_ctrl->e_function = MOTOR_FUNCTION_SELECT_NONE;
+
             p_instance_ctrl->u2_error_info = MOTOR_ERROR_NONE;
 
             rm_motor_induction_init_speed_input(&(p_instance_ctrl->st_speed_input));
@@ -224,7 +252,7 @@ fsp_err_t RM_MOTOR_INDUCTION_Open (motor_ctrl_t * const p_ctrl, motor_cfg_t cons
 }
 
 /*******************************************************************************************************************//**
- * @brief Disables specified Motor Encoder Control block. Implements @ref motor_api_t::close.
+ * @brief Disables specified Motor Induction Control block. Implements @ref motor_api_t::close.
  *
  * Example:
  * @snippet rm_motor_induction_example.c RM_MOTOR_INDUCTION_Close
@@ -246,6 +274,13 @@ fsp_err_t RM_MOTOR_INDUCTION_Close (motor_ctrl_t * const p_ctrl)
     MOTOR_INDUCTION_ERROR_RETURN(MOTOR_INDUCTION_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
 #endif
 
+    motor_induction_extended_cfg_t * p_extended_cfg =
+        (motor_induction_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+
+#if MOTOR_INDUCTION_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_extended_cfg);
+#endif
+
     /* Close using modules */
     err = p_instance_ctrl->p_cfg->p_motor_speed_instance->p_api->close(
         p_instance_ctrl->p_cfg->p_motor_speed_instance->p_ctrl);
@@ -255,6 +290,20 @@ fsp_err_t RM_MOTOR_INDUCTION_Close (motor_ctrl_t * const p_ctrl)
         err = p_instance_ctrl->p_cfg->p_motor_current_instance->p_api->close(
             p_instance_ctrl->p_cfg->p_motor_current_instance->p_ctrl);
 
+        // Close Inertia estimate when supported
+        if (p_extended_cfg->p_motor_inertia_estimate_instance != NULL)
+        {
+            err = p_extended_cfg->p_motor_inertia_estimate_instance->p_api->close(
+                p_extended_cfg->p_motor_inertia_estimate_instance->p_ctrl);
+        }
+
+        // Close Return origin function when supported
+        if (p_extended_cfg->p_motor_return_origin_instance != NULL)
+        {
+            err = p_extended_cfg->p_motor_return_origin_instance->p_api->close(
+                p_extended_cfg->p_motor_return_origin_instance->p_ctrl);
+        }
+
         if (FSP_SUCCESS == err)
         {
             rm_motor_induction_init_speed_input(&(p_instance_ctrl->st_speed_input));
@@ -268,7 +317,7 @@ fsp_err_t RM_MOTOR_INDUCTION_Close (motor_ctrl_t * const p_ctrl)
 }
 
 /*******************************************************************************************************************//**
- * @brief Reset Motor Encoder Control block. Implements @ref motor_api_t::reset.
+ * @brief Reset Motor Induction Control block. Implements @ref motor_api_t::reset.
  *
  * Example:
  * @snippet rm_motor_induction_example.c RM_MOTOR_INDUCTION_Reset
@@ -328,7 +377,10 @@ fsp_err_t RM_MOTOR_INDUCTION_Run (motor_ctrl_t * const p_ctrl)
     MOTOR_INDUCTION_ERROR_RETURN(MOTOR_INDUCTION_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
 #endif
 
-    rm_motor_induction_statemachine_event(p_instance_ctrl, MOTOR_INDUCTION_CTRL_EVENT_RUN);
+    if (MOTOR_FUNCTION_SELECT_NONE == p_instance_ctrl->e_function)
+    {
+        rm_motor_induction_statemachine_event(p_instance_ctrl, MOTOR_INDUCTION_CTRL_EVENT_RUN);
+    }
 
     return err;
 }
@@ -356,7 +408,10 @@ fsp_err_t RM_MOTOR_INDUCTION_Stop (motor_ctrl_t * const p_ctrl)
     MOTOR_INDUCTION_ERROR_RETURN(MOTOR_INDUCTION_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
 #endif
 
-    rm_motor_induction_statemachine_event(p_instance_ctrl, MOTOR_INDUCTION_CTRL_EVENT_STOP);
+    if (MOTOR_FUNCTION_SELECT_NONE == p_instance_ctrl->e_function)
+    {
+        rm_motor_induction_statemachine_event(p_instance_ctrl, MOTOR_INDUCTION_CTRL_EVENT_STOP);
+    }
 
     return err;
 }
@@ -446,9 +501,12 @@ fsp_err_t RM_MOTOR_INDUCTION_PositionSet (motor_ctrl_t * const
     MOTOR_INDUCTION_ERROR_RETURN(p_position != NULL, FSP_ERR_INVALID_ARGUMENT);
 #endif
 
-    err = p_instance_ctrl->p_cfg->p_motor_speed_instance->p_api->positionReferenceSet(
-        p_instance_ctrl->p_cfg->p_motor_speed_instance->p_ctrl,
-        p_position);
+    if (MOTOR_FUNCTION_SELECT_NONE == p_instance_ctrl->e_function)
+    {
+        err = p_instance_ctrl->p_cfg->p_motor_speed_instance->p_api->positionReferenceSet(
+            p_instance_ctrl->p_cfg->p_motor_speed_instance->p_ctrl,
+            p_position);
+    }
 
     return err;
 }
@@ -647,6 +705,270 @@ fsp_err_t RM_MOTOR_INDUCTION_WaitStopFlagGet (motor_ctrl_t * const p_ctrl, motor
     return FSP_ERR_UNSUPPORTED;
 }
 
+/*******************************************************************************************************************//**
+ * @brief Select using function. Implements @ref motor_api_t::functionSelect.
+ *
+ * @retval FSP_SUCCESS              Successfully resetted.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ * @retval FSP_ERR_INVALID_MODE     Mode unmatch
+ *
+ * @note
+ *
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_INDUCTION_FunctionSelect (motor_ctrl_t * const p_ctrl, motor_function_select_t const function)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    motor_induction_instance_ctrl_t * p_instance_ctrl = (motor_induction_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_INDUCTION_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_instance_ctrl);
+    MOTOR_INDUCTION_ERROR_RETURN(MOTOR_INDUCTION_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    switch (p_instance_ctrl->e_function)
+    {
+        default:
+        {
+            /* Do nothing */
+            break;
+        }
+
+        case MOTOR_FUNCTION_SELECT_NONE:
+        {
+            if (MOTOR_FUNCTION_SELECT_NONE == function)
+            {
+                err = FSP_ERR_INVALID_MODE;
+            }
+            else
+            {
+                p_instance_ctrl->e_function = function;
+
+                /* Run */
+                rm_motor_induction_active(p_instance_ctrl);
+            }
+
+            break;
+        }
+
+        case MOTOR_FUNCTION_SELECT_INERTIA_ESTIMATE:
+        {
+            if (MOTOR_FUNCTION_SELECT_NONE == function)
+            {
+                p_instance_ctrl->e_function = function;
+
+                /* Stop */
+                rm_motor_induction_inactive(p_instance_ctrl);
+            }
+            else
+            {
+                err = FSP_ERR_INVALID_MODE;
+            }
+
+            break;
+        }
+
+        case MOTOR_FUNCTION_SELECT_RETURN_ORIGIN:
+        {
+            if (MOTOR_FUNCTION_SELECT_NONE == function)
+            {
+                p_instance_ctrl->e_function = function;
+
+                /* Stop */
+                rm_motor_induction_inactive(p_instance_ctrl);
+            }
+            else
+            {
+                err = FSP_ERR_INVALID_MODE;
+            }
+
+            break;
+        }
+    }
+
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Start inertia estimation function.
+ *
+ * @retval FSP_SUCCESS              Successfully resetted.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ * @retval FSP_ERR_INVALID_MODE     Mode unmatch
+ *
+ * @note
+ *
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_INDUCTION_InertiaEstimateStart (motor_ctrl_t * const p_ctrl)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    motor_induction_instance_ctrl_t * p_instance_ctrl = (motor_induction_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_INDUCTION_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_instance_ctrl);
+    MOTOR_INDUCTION_ERROR_RETURN(MOTOR_INDUCTION_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    motor_induction_extended_cfg_t * p_extended_cfg =
+        (motor_induction_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+
+#if MOTOR_INDUCTION_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_extended_cfg);
+#endif
+
+    /* Only effective when Inertia estimation is selected */
+    if (MOTOR_FUNCTION_SELECT_INERTIA_ESTIMATE == p_instance_ctrl->e_function)
+    {
+        if (p_extended_cfg->p_motor_inertia_estimate_instance != NULL)
+        {
+            err = p_extended_cfg->p_motor_inertia_estimate_instance->p_api->start(
+                p_extended_cfg->p_motor_inertia_estimate_instance->p_ctrl);
+        }
+    }
+    else
+    {
+        err = FSP_ERR_INVALID_MODE;
+    }
+
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Stop(Cancel) inertia estimation function.
+ *
+ * @retval FSP_SUCCESS              Successfully resetted.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ * @retval FSP_ERR_INVALID_MODE     Mode unmatch
+ *
+ * @note
+ *
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_INDUCTION_InertiaEstimateStop (motor_ctrl_t * const p_ctrl)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    motor_induction_instance_ctrl_t * p_instance_ctrl = (motor_induction_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_INDUCTION_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_instance_ctrl);
+    MOTOR_INDUCTION_ERROR_RETURN(MOTOR_INDUCTION_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    motor_induction_extended_cfg_t * p_extended_cfg =
+        (motor_induction_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+
+#if MOTOR_INDUCTION_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_extended_cfg);
+#endif
+
+    /* Only effective when Inertia estimation is selected */
+    if (MOTOR_FUNCTION_SELECT_INERTIA_ESTIMATE == p_instance_ctrl->e_function)
+    {
+        if (p_extended_cfg->p_motor_inertia_estimate_instance != NULL)
+        {
+            err = p_extended_cfg->p_motor_inertia_estimate_instance->p_api->stop(
+                p_extended_cfg->p_motor_inertia_estimate_instance->p_ctrl);
+        }
+    }
+    else
+    {
+        err = FSP_ERR_INVALID_MODE;
+    }
+
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Start return origin function.
+ *
+ * @retval FSP_SUCCESS              Successfully resetted.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ * @retval FSP_ERR_INVALID_MODE     Mode unmatch
+ *
+ * @note
+ *
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_INDUCTION_ReturnOriginStart (motor_ctrl_t * const p_ctrl)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    motor_induction_instance_ctrl_t * p_instance_ctrl = (motor_induction_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_INDUCTION_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_instance_ctrl);
+    MOTOR_INDUCTION_ERROR_RETURN(MOTOR_INDUCTION_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    motor_induction_extended_cfg_t * p_extended_cfg =
+        (motor_induction_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+
+#if MOTOR_INDUCTION_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_extended_cfg);
+#endif
+
+    /* Only effective when return origin is selected */
+    if (MOTOR_FUNCTION_SELECT_RETURN_ORIGIN == p_instance_ctrl->e_function)
+    {
+        if (p_extended_cfg->p_motor_return_origin_instance != NULL)
+        {
+            err = p_extended_cfg->p_motor_return_origin_instance->p_api->start(
+                p_extended_cfg->p_motor_return_origin_instance->p_ctrl);
+        }
+    }
+    else
+    {
+        err = FSP_ERR_INVALID_MODE;
+    }
+
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Stop(Cancel) return origin function.
+ *
+ * @retval FSP_SUCCESS              Successfully resetted.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ * @retval FSP_ERR_INVALID_MODE     Mode unmatch
+ *
+ * @note
+ *
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_INDUCTION_ReturnOriginStop (motor_ctrl_t * const p_ctrl)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    motor_induction_instance_ctrl_t * p_instance_ctrl = (motor_induction_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_INDUCTION_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_instance_ctrl);
+    MOTOR_INDUCTION_ERROR_RETURN(MOTOR_INDUCTION_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    motor_induction_extended_cfg_t * p_extended_cfg =
+        (motor_induction_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+
+#if MOTOR_INDUCTION_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_extended_cfg);
+#endif
+
+    /* Only effective when return origin is selected */
+    if (MOTOR_FUNCTION_SELECT_RETURN_ORIGIN == p_instance_ctrl->e_function)
+    {
+        if (p_extended_cfg->p_motor_return_origin_instance != NULL)
+        {
+            err = p_extended_cfg->p_motor_return_origin_instance->p_api->stop(
+                p_extended_cfg->p_motor_return_origin_instance->p_ctrl);
+        }
+    }
+    else
+    {
+        err = FSP_ERR_INVALID_MODE;
+    }
+
+    return err;
+}
+
 /*******************************************************************************************************************//**
  * @} (end addtogroup MOTOR_INDUCTION)
  **********************************************************************************************************************/
@@ -860,19 +1182,19 @@ static uint32_t rm_motor_induction_statemachine_event (motor_induction_instance_
 /***********************************************************************************************************************
  * Function Name : rm_motor_check_over_speed_error
  * Description   : Checks over-speed error
- * Arguments     : f4_speed_rad - The electrical speed[rad/s]
- *                 f4_speed_limit_rad - The speed[rad/s] threshold of the over-speed error, should be a positive value
+ * Arguments     : f4_speed - The electrical speed
+ *                 f4_speed_limit - The speed threshold of the over-speed error, should be a positive value
  * Return Value  : The over-speed error flag
  **********************************************************************************************************************/
-static inline uint16_t rm_motor_check_over_speed_error (float f4_speed_rad, float f4_speed_limit_rad)
+static inline uint16_t rm_motor_check_over_speed_error (float f4_speed, float f4_speed_limit)
 {
     float    f4_temp0;
     uint16_t u2_temp0;
 
     u2_temp0 = MOTOR_ERROR_NONE;
 
-    f4_temp0 = fabsf(f4_speed_rad);
-    if (f4_temp0 > f4_speed_limit_rad)
+    f4_temp0 = fabsf(f4_speed);
+    if (f4_temp0 > f4_speed_limit)
     {
         u2_temp0 = MOTOR_ERROR_OVER_SPEED;
     }
@@ -1052,6 +1374,116 @@ static void rm_motor_induction_init_speed_output (motor_speed_output_t * p_outpu
     p_output->u1_flag_pi = MOTOR_INDUCTION_FLAG_CLEAR;
 }                                      /* End of function rm_motor_induction_init_speed_output() */
 
+/***********************************************************************************************************************
+ * Function Name : rm_motor_induction_inertia_estimate_current_process
+ * Description   : Inertia estimate process in current cyclic
+ * Arguments     : p_instance - motor instance pointer
+ * Return Value  : None
+ **********************************************************************************************************************/
+static void rm_motor_induction_inertia_estimate_current_process (motor_instance_t * p_instance)
+{
+    motor_induction_instance_ctrl_t * p_ctrl         = (motor_induction_instance_ctrl_t *) p_instance->p_ctrl;
+    motor_induction_extended_cfg_t  * p_extended_cfg =
+        (motor_induction_extended_cfg_t *) p_ctrl->p_cfg->p_extend;
+    motor_position_instance_t const * p_position =
+        (motor_position_instance_t *) p_instance->p_cfg->p_motor_speed_instance->p_cfg->p_position_instance;
+    motor_position_info_t temp_position_info;
+    motor_inertia_estimate_instance_t const * p_ie_instance = p_extended_cfg->p_motor_inertia_estimate_instance;
+
+    if (p_ie_instance != NULL)
+    {
+        if (MOTOR_FUNCTION_SELECT_INERTIA_ESTIMATE == p_ctrl->e_function)
+        {
+            p_ctrl->st_ie_set_data.f_iq = p_ctrl->st_current_output.f_iq;
+            p_ctrl->st_ie_set_data.f_speed_radian_control = p_ctrl->st_current_input.f_ref_speed_rad_ctrl;
+
+            p_position->p_api->infoGet(p_position->p_ctrl, &temp_position_info);
+
+            p_ctrl->st_ie_set_data.s2_position_degree = temp_position_info.s2_position_degree;
+            p_ctrl->st_ie_set_data.u1_position_state  = temp_position_info.u1_state_position_profile;
+
+            p_ie_instance->p_api->dataSet(p_ie_instance->p_ctrl, &(p_ctrl->st_ie_set_data));
+            p_ie_instance->p_api->infoGet(p_ie_instance->p_ctrl, &(p_ctrl->st_ie_get_data));
+            p_ie_instance->p_api->currentCyclic(p_ie_instance->p_ctrl);
+        }
+    }
+}                                      /* End of function rm_motor_induction_inertia_estimate_current_process() */
+
+/***********************************************************************************************************************
+ * Function Name : rm_motor_induction_inertia_estimate_speed_process
+ * Description   : Inertia estimate process in speed cyclic
+ * Arguments     : p_instance - motor instance pointer
+ * Return Value  : None
+ **********************************************************************************************************************/
+static void rm_motor_induction_inertia_estimate_speed_process (motor_instance_t * p_instance)
+{
+    motor_induction_instance_ctrl_t * p_ctrl         = (motor_induction_instance_ctrl_t *) p_instance->p_ctrl;
+    motor_induction_extended_cfg_t  * p_extended_cfg =
+        (motor_induction_extended_cfg_t *) p_ctrl->p_cfg->p_extend;
+    motor_inertia_estimate_instance_t const * p_ie_instance = p_extended_cfg->p_motor_inertia_estimate_instance;
+    motor_speed_position_data_t               temp_position_data;
+
+    if (p_ie_instance != NULL)
+    {
+        if (MOTOR_FUNCTION_SELECT_INERTIA_ESTIMATE == p_ctrl->e_function)
+        {
+            p_ie_instance->p_api->speedCyclic(p_ie_instance->p_ctrl);
+
+            temp_position_data.e_step_mode               = MOTOR_SPEED_STEP_DISABLE;
+            temp_position_data.e_loop_mode               = MOTOR_SPEED_LOOP_MODE_POSITION;
+            temp_position_data.position_reference_degree =
+                p_ctrl->st_ie_get_data.s2_position_reference_degree;
+
+            /* Set position reference */
+            p_instance->p_cfg->p_motor_speed_instance->p_api->positionReferenceSet(
+                p_instance->p_cfg->p_motor_speed_instance->p_ctrl,
+                &temp_position_data);
+        }
+    }
+}                                      /* End of function rm_motor_induction_inertia_estimate_speed_process() */
+
+/***********************************************************************************************************************
+ * Function Name : rm_motor_induction_return_origin_speed_process
+ * Description   : Return origin process in speed cyclic
+ * Arguments     : p_instance - motor instance pointer
+ * Return Value  : None
+ **********************************************************************************************************************/
+static void rm_motor_induction_return_origin_speed_process (motor_instance_t * p_instance)
+{
+    motor_induction_instance_ctrl_t      * p_ctrl         = (motor_induction_instance_ctrl_t *) p_instance->p_ctrl;
+    motor_induction_extended_cfg_t       * p_extended_cfg = (motor_induction_extended_cfg_t *) p_ctrl->p_cfg->p_extend;
+    motor_return_origin_instance_t const * p_ro_instance  = p_extended_cfg->p_motor_return_origin_instance;
+    motor_speed_position_data_t            temp_position_data;
+    int16_t s2_temp_position;
+
+    /* Return origin process */
+    if (p_ro_instance != NULL)
+    {
+        if (MOTOR_FUNCTION_SELECT_RETURN_ORIGIN == p_ctrl->e_function)
+        {
+            p_ctrl->st_ro_set_data.f_iq = p_ctrl->st_current_output.f_iq;
+            p_instance->p_cfg->p_motor_speed_instance->p_cfg->p_position_instance->p_api->positionGet(
+                p_instance->p_cfg->p_motor_speed_instance->p_cfg->p_position_instance->p_ctrl,
+                &s2_temp_position);
+            p_ctrl->st_ro_set_data.f_position_degree = (float) s2_temp_position;
+            p_ro_instance->p_api->dataSet(p_ro_instance->p_ctrl, &(p_ctrl->st_ro_set_data));
+
+            p_ro_instance->p_api->speedCyclic(p_ro_instance->p_ctrl);
+            p_ro_instance->p_api->infoGet(p_ro_instance->p_ctrl, &(p_ctrl->st_ro_info));
+
+            temp_position_data.e_step_mode               = MOTOR_SPEED_STEP_ENABLE;
+            temp_position_data.e_loop_mode               = MOTOR_SPEED_LOOP_MODE_POSITION;
+            temp_position_data.position_reference_degree =
+                (int16_t) p_ctrl->st_ro_info.f_position_reference_degree;
+
+            /* Set position reference */
+            p_instance->p_cfg->p_motor_speed_instance->p_api->positionReferenceSet(
+                p_instance->p_cfg->p_motor_speed_instance->p_ctrl,
+                &temp_position_data);
+        }
+    }
+}                                      /* End of function rm_motor_induction_return_origin_speed_process() */
+
 /* Callback function */
 
 /***********************************************************************************************************************
@@ -1092,6 +1524,8 @@ void rm_motor_induction_current_callback (motor_current_callback_args_t * p_args
 
         case MOTOR_CURRENT_EVENT_BACKWARD:
         {
+            rm_motor_induction_inertia_estimate_current_process(p_instance);
+
             /* Invoke the callback function if it is set. */
             if (NULL != p_ctrl->p_cfg->p_callback)
             {
@@ -1145,6 +1579,9 @@ void rm_motor_induction_speed_callback (motor_speed_callback_args_t * p_args)
 
         case MOTOR_SPEED_EVENT_BACKWARD:
         {
+            rm_motor_induction_inertia_estimate_speed_process(p_instance);
+            rm_motor_induction_return_origin_speed_process(p_instance);
+
             /* Invoke the callback function if it is set. */
             if (NULL != p_ctrl->p_cfg->p_callback)
             {
diff --git a/ra/fsp/src/rm_motor_inertia_estimate/rm_motor_inertia_estimate.c b/ra/fsp/src/rm_motor_inertia_estimate/rm_motor_inertia_estimate.c
new file mode 100644
index 000000000..4d26558c6
--- /dev/null
+++ b/ra/fsp/src/rm_motor_inertia_estimate/rm_motor_inertia_estimate.c
@@ -0,0 +1,861 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include <math.h>
+#include <stdint.h>
+#include "rm_motor_inertia_estimate.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+#define     MOTOR_INERTIA_ESTIMATE_OPEN                (('M' << 24U) | ('T' << 16U) | ('I' << 8U) | ('E' << 0U))
+
+#define     MOTOR_INERTIA_ESTIMATE_TWO_PI              (6.283185307F)
+#define     MOTOR_INERTIA_ESTIMATE_TWO_PI_60           (MOTOR_INERTIA_ESTIMATE_TWO_PI / 60.0F)
+#define     MOTOR_INERTIA_ESTIMATE_DEGREE_TO_RAD       (MOTOR_INERTIA_ESTIMATE_TWO_PI / 360.0F)
+#define     MOTOR_INERTIA_ESTIMATE_HALF                (0.5F)
+#define     MOTOR_INERTIA_ESTIMATE_TWO                 (2.0F)
+#define     MOTOR_INERTIA_ESTIMATE_THREE               (3.0F)
+
+#define     MOTOR_INERTIA_ESTIMATE_MOVE_TRIANGLE       (0)
+#define     MOTOR_INERTIA_ESTIMATE_MOVE_TRAPEZOIDAL    (1)
+
+#define     MOTOR_INERTIA_ESTIMATE_POS_STEADY          (0)
+#define     MOTOR_INERTIA_ESTIMATE_POS_TRANSITION      (1)
+
+#ifndef MOTOR_INERTIA_ESTIMATE_ERROR_RETURN
+
+ #define    MOTOR_INERTIA_ESTIMATE_ERROR_RETURN(a, err)    FSP_ERROR_RETURN((a), (err))
+#endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+static void rm_motor_inertia_estimate_initialize(motor_inertia_estimate_instance_ctrl_t * p_ctrl);
+static void rm_motor_inertia_estimate_set_parameter(motor_inertia_estimate_instance_ctrl_t * p_ctrl);
+
+static void rm_motor_inertia_estimate_speed_cyclic(motor_inertia_estimate_ctrl_t * const p_ctrl);
+static void rm_motor_inertia_estimate_steady_process(motor_inertia_estimate_instance_ctrl_t * p_ctrl);
+static void rm_motor_inertia_estimate_transition_process(motor_inertia_estimate_instance_ctrl_t * p_ctrl);
+
+/***********************************************************************************************************************
+ * Private global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Global variables
+ **********************************************************************************************************************/
+const motor_inertia_estimate_api_t g_motor_inertia_estimate_on_motor_inertia_estimate =
+{
+    .open            = RM_MOTOR_INERTIA_ESTIMATE_Open,
+    .close           = RM_MOTOR_INERTIA_ESTIMATE_Close,
+    .start           = RM_MOTOR_INERTIA_ESTIMATE_Start,
+    .stop            = RM_MOTOR_INERTIA_ESTIMATE_Stop,
+    .reset           = RM_MOTOR_INERTIA_ESTIMATE_Reset,
+    .infoGet         = RM_MOTOR_INERTIA_ESTIMATE_InfoGet,
+    .dataSet         = RM_MOTOR_INERTIA_ESTIMATE_DataSet,
+    .speedCyclic     = RM_MOTOR_INERTIA_ESTIMATE_SpeedCyclic,
+    .currentCyclic   = RM_MOTOR_INERTIA_ESTIMATE_CurrentCyclic,
+    .parameterUpdate = RM_MOTOR_INERTIA_ESTIMATE_ParameterUpdate,
+};
+
+/*******************************************************************************************************************//**
+ * @addtogroup MOTOR_INERTIA_ESTIMATE
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @brief Opens and configures the motor inertia estimate module. Implements @ref motor_inertia_estimate_api_t::open.
+ *
+ * Example:
+ * @snippet rm_motor_inertia_estimate_example.c RM_MOTOR_INERTIA_ESTIMATE_Open
+ *
+ * @retval FSP_SUCCESS              Motor inertia estimate module successfully configured.
+ * @retval FSP_ERR_ASSERTION        Null pointer, or one or more configuration options is invalid.
+ * @retval FSP_ERR_ALREADY_OPEN     Module is already open.  This module can only be opened once.
+ * @retval FSP_ERR_INVALID_ARGUMENT Input parameter error.
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_INERTIA_ESTIMATE_Open (motor_inertia_estimate_ctrl_t * const      p_ctrl,
+                                          motor_inertia_estimate_cfg_t const * const p_cfg)
+{
+    motor_inertia_estimate_instance_ctrl_t * p_instance_ctrl = (motor_inertia_estimate_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_INERTIA_ESTIMATE_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT(NULL != p_cfg);
+    MOTOR_INERTIA_ESTIMATE_ERROR_RETURN(MOTOR_INERTIA_ESTIMATE_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
+#endif
+
+    motor_inertia_estimate_extended_cfg_t * p_extend = (motor_inertia_estimate_extended_cfg_t *) p_cfg->p_extend;
+
+#if MOTOR_INERTIA_ESTIMATE_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_extend);
+
+    MOTOR_INERTIA_ESTIMATE_ERROR_RETURN(p_extend->u1_motor_polepairs != 0, FSP_ERR_INVALID_ARGUMENT);
+#endif
+    p_instance_ctrl->p_cfg = p_cfg;
+
+    rm_motor_inertia_estimate_initialize(p_instance_ctrl);
+
+    p_instance_ctrl->f_inverse_motor_polepairs = 1.0F / (float) p_extend->u1_motor_polepairs;
+
+    rm_motor_inertia_estimate_set_parameter(p_instance_ctrl);
+
+    /* Mark driver as open */
+    p_instance_ctrl->open = MOTOR_INERTIA_ESTIMATE_OPEN;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Disables specified motor inertia estimate module. Implements @ref motor_inertia_estimate_api_t::close.
+ *
+ * Example:
+ * @snippet rm_motor_inertia_estimate_example.c RM_MOTOR_INERTIA_ESTIMATE_Close
+ *
+ * @retval FSP_SUCCESS              Successfully closed.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_INERTIA_ESTIMATE_Close (motor_inertia_estimate_ctrl_t * const p_ctrl)
+{
+    motor_inertia_estimate_instance_ctrl_t * p_instance_ctrl = (motor_inertia_estimate_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_INERTIA_ESTIMATE_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    MOTOR_INERTIA_ESTIMATE_ERROR_RETURN(MOTOR_INERTIA_ESTIMATE_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    rm_motor_inertia_estimate_initialize(p_instance_ctrl);
+
+    p_instance_ctrl->open = 0U;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Start inertia estimation. Implements @ref motor_inertia_estimate_api_t::start.
+ *
+ * Example:
+ * @snippet rm_motor_inertia_estimate_example.c RM_MOTOR_INERTIA_ESTIMATE_Start
+ *
+ * @retval FSP_SUCCESS              Successfully started.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_INERTIA_ESTIMATE_Start (motor_inertia_estimate_ctrl_t * const p_ctrl)
+{
+    motor_inertia_estimate_instance_ctrl_t * p_instance_ctrl = (motor_inertia_estimate_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_INERTIA_ESTIMATE_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    MOTOR_INERTIA_ESTIMATE_ERROR_RETURN(MOTOR_INERTIA_ESTIMATE_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    rm_motor_inertia_estimate_initialize(p_instance_ctrl);
+
+    p_instance_ctrl->start_flag = MOTOR_INERTIA_ESTIMATE_START_FLAG_START;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Stop (Cancel) inertia estimation. Implements @ref motor_inertia_estimate_api_t::stop.
+ *
+ * Example:
+ * @snippet rm_motor_inertia_estimate_example.c RM_MOTOR_INERTIA_ESTIMATE_Stop
+ *
+ * @retval FSP_SUCCESS              Successfully stopped (canceled).
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_INERTIA_ESTIMATE_Stop (motor_inertia_estimate_ctrl_t * const p_ctrl)
+{
+    motor_inertia_estimate_instance_ctrl_t * p_instance_ctrl = (motor_inertia_estimate_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_INERTIA_ESTIMATE_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    MOTOR_INERTIA_ESTIMATE_ERROR_RETURN(MOTOR_INERTIA_ESTIMATE_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    rm_motor_inertia_estimate_initialize(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Reset variables of inertia estimate module. Implements @ref motor_inertia_estimate_api_t::reset.
+ *
+ * @retval FSP_SUCCESS              Successfully reset.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_INERTIA_ESTIMATE_Reset (motor_inertia_estimate_ctrl_t * const p_ctrl)
+{
+    motor_inertia_estimate_instance_ctrl_t * p_instance_ctrl = (motor_inertia_estimate_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_INERTIA_ESTIMATE_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    MOTOR_INERTIA_ESTIMATE_ERROR_RETURN(MOTOR_INERTIA_ESTIMATE_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    rm_motor_inertia_estimate_initialize(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Get information of inertia estimation. Implements @ref motor_inertia_estimate_api_t::infoGet.
+ *
+ * Example:
+ * @snippet rm_motor_inertia_estimate_example.c RM_MOTOR_INERTIA_ESTIMATE_InfoGet
+ *
+ * @retval FSP_SUCCESS              Successfully get data.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ * @retval FSP_ERR_INVALID_ARGUMENT Argument pointer is invalid.
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_INERTIA_ESTIMATE_InfoGet (motor_inertia_estimate_ctrl_t * const p_ctrl,
+                                             motor_inertia_estimate_info_t * const p_info)
+{
+    motor_inertia_estimate_instance_ctrl_t * p_instance_ctrl = (motor_inertia_estimate_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_INERTIA_ESTIMATE_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    MOTOR_INERTIA_ESTIMATE_ERROR_RETURN(MOTOR_INERTIA_ESTIMATE_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    MOTOR_INERTIA_ESTIMATE_ERROR_RETURN(p_info != NULL, FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_info->s2_position_reference_degree = p_instance_ctrl->s2_position_reference_degree;
+    p_info->mode                = p_instance_ctrl->mode;
+    p_info->f_estimated_inertia = p_instance_ctrl->f_estimated_value;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Set necessary data to inertia estimation. Implements @ref motor_inertia_estimate_api_t::dataSet.
+ *
+ * Example:
+ * @snippet rm_motor_inertia_estimate_example.c RM_MOTOR_INERTIA_ESTIMATE_DataSet
+ *
+ * @retval FSP_SUCCESS              Successfully set data.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ * @retval FSP_ERR_INVALID_ARGUMENT Input parameter error.
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_INERTIA_ESTIMATE_DataSet (motor_inertia_estimate_ctrl_t * const     p_ctrl,
+                                             motor_inertia_estimate_set_data_t * const p_set_data)
+{
+    motor_inertia_estimate_instance_ctrl_t * p_instance_ctrl = (motor_inertia_estimate_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_INERTIA_ESTIMATE_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    MOTOR_INERTIA_ESTIMATE_ERROR_RETURN(MOTOR_INERTIA_ESTIMATE_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    MOTOR_INERTIA_ESTIMATE_ERROR_RETURN(p_set_data != NULL, FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    motor_inertia_estimate_extended_cfg_t * p_extend =
+        (motor_inertia_estimate_extended_cfg_t *) (p_instance_ctrl->p_cfg->p_extend);
+
+    p_instance_ctrl->receive_data = *p_set_data;
+
+    p_instance_ctrl->f_iq_ad = p_set_data->f_iq * p_extend->f_current_ctrl_period;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Cyclic process of inertia estimation at speed control period.
+ * Implements @ref motor_inertia_estimate_api_t::speedCyclic.
+ *
+ * @retval FSP_SUCCESS              Successfully perform the process.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_INERTIA_ESTIMATE_SpeedCyclic (motor_inertia_estimate_ctrl_t * const p_ctrl)
+{
+    motor_inertia_estimate_instance_ctrl_t * p_instance_ctrl = (motor_inertia_estimate_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_INERTIA_ESTIMATE_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    MOTOR_INERTIA_ESTIMATE_ERROR_RETURN(MOTOR_INERTIA_ESTIMATE_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Only work at inertia estimation started */
+    if (MOTOR_INERTIA_ESTIMATE_START_FLAG_START == p_instance_ctrl->start_flag)
+    {
+        /* Copy moving state */
+        p_instance_ctrl->speed_period_buffer = p_instance_ctrl->speed_period;
+
+        /* Perform cyclic process */
+        rm_motor_inertia_estimate_speed_cyclic(p_ctrl);
+    }
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Cyclic process of inertia estimation at current control period (called at A/D conversion finish interrupt).
+ * Implements @ref motor_inertia_estimate_api_t::currentCyclic.
+ *
+ * @retval FSP_SUCCESS              Successfully perform the process.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_INERTIA_ESTIMATE_CurrentCyclic (motor_inertia_estimate_ctrl_t * const p_ctrl)
+{
+    motor_inertia_estimate_instance_ctrl_t * p_instance_ctrl = (motor_inertia_estimate_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_INERTIA_ESTIMATE_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    MOTOR_INERTIA_ESTIMATE_ERROR_RETURN(MOTOR_INERTIA_ESTIMATE_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    motor_inertia_estimate_extended_cfg_t * p_extend =
+        (motor_inertia_estimate_extended_cfg_t *) (p_instance_ctrl->p_cfg->p_extend);
+
+#if MOTOR_INERTIA_ESTIMATE_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_extend);
+#endif
+
+    float f_inertia = 0.0F;
+    float f_iq_ad   = 0.0F;
+    float f_time    = 0.0F;
+    float f_temp    = 0.0F;
+
+    /* Only work at inertia estimation started */
+    if (MOTOR_INERTIA_ESTIMATE_START_FLAG_START == p_instance_ctrl->start_flag)
+    {
+        if (MOTOR_INERTIA_ESTIMATE_PERIOD_MEASURE_FINISH == p_instance_ctrl->speed_period)
+        {
+            /* Do nothing */
+        }
+        /* Reached at calculate position */
+        else if (MOTOR_INERTIA_ESTIMATE_PERIOD_NO_MOVE == p_instance_ctrl->speed_period)
+        {
+            // Memorize current speed
+            f_inertia = p_instance_ctrl->receive_data.f_speed_radian_control *
+                        p_instance_ctrl->f_inverse_motor_polepairs;
+
+            // Memorize sum of iq
+            f_iq_ad = p_instance_ctrl->f_summary_iq_ad;
+
+            // Memorize moving time
+            f_time = (float) p_instance_ctrl->u4_measure_count * p_extend->f_current_ctrl_period;
+
+            switch (p_instance_ctrl->speed_period_buffer)
+            {
+                default:
+                case MOTOR_INERTIA_ESTIMATE_PERIOD_NO_MOVE:
+                {
+                    p_instance_ctrl->f_summary_iq_ad  = 0.0F;
+                    p_instance_ctrl->u4_measure_count = 0U;
+                    break;
+                }
+
+                case MOTOR_INERTIA_ESTIMATE_PERIOD_FORWARD_ACCELL:
+                {
+                    p_instance_ctrl->f_inertia_speed_ctrl2 = f_inertia;
+                    p_instance_ctrl->f_inertia_integ_iq1   = f_iq_ad;
+                    p_instance_ctrl->f_inertia_integ_time1 = f_time;
+                    break;
+                }
+
+                case MOTOR_INERTIA_ESTIMATE_PERIOD_FORWARD_DECELERATE:
+                {
+                    p_instance_ctrl->f_inertia_speed_ctrl4 = f_inertia;
+                    p_instance_ctrl->f_inertia_integ_iq2   = f_iq_ad;
+                    p_instance_ctrl->f_inertia_integ_time2 = f_time;
+                    break;
+                }
+
+                case MOTOR_INERTIA_ESTIMATE_PERIOD_REVERSE_ACCELL:
+                {
+                    p_instance_ctrl->f_inertia_speed_ctrl6 = f_inertia;
+                    p_instance_ctrl->f_inertia_integ_iq3   = f_iq_ad;
+                    p_instance_ctrl->f_inertia_integ_time3 = f_time;
+                    break;
+                }
+
+                case MOTOR_INERTIA_ESTIMATE_PERIOD_REVERSE_DECELERATE:
+                {
+                    p_instance_ctrl->f_inertia_speed_ctrl8 = f_inertia;
+                    p_instance_ctrl->f_inertia_integ_iq4   = f_iq_ad;
+                    p_instance_ctrl->f_inertia_integ_time4 = f_time;
+                    break;
+                }
+            }
+        }
+        /* During the motor moves */
+        else
+        {
+            /* When reached reference position */
+            if (MOTOR_INERTIA_ESTIMATE_PERIOD_NO_MOVE == p_instance_ctrl->speed_period_buffer)
+            {
+                /* Memorize current speed */
+                f_temp = p_instance_ctrl->receive_data.f_speed_radian_control *
+                         p_instance_ctrl->f_inverse_motor_polepairs;
+                switch (p_instance_ctrl->speed_period)
+                {
+                    default:
+                    {
+                        break;
+                    }
+
+                    case MOTOR_INERTIA_ESTIMATE_PERIOD_FORWARD_ACCELL:
+                    {
+                        p_instance_ctrl->f_inertia_speed_ctrl1 = f_temp;
+                        break;
+                    }
+
+                    case MOTOR_INERTIA_ESTIMATE_PERIOD_FORWARD_DECELERATE:
+                    {
+                        p_instance_ctrl->f_inertia_speed_ctrl3 = f_temp;
+                        break;
+                    }
+
+                    case MOTOR_INERTIA_ESTIMATE_PERIOD_REVERSE_ACCELL:
+                    {
+                        p_instance_ctrl->f_inertia_speed_ctrl5 = f_temp;
+                        break;
+                    }
+
+                    case MOTOR_INERTIA_ESTIMATE_PERIOD_REVERSE_DECELERATE:
+                    {
+                        p_instance_ctrl->f_inertia_speed_ctrl7 = f_temp;
+                        break;
+                    }
+                }
+            }
+
+            p_instance_ctrl->f_summary_iq_ad += p_instance_ctrl->f_iq_ad;
+
+            // measure moving time
+            p_instance_ctrl->u4_measure_count++;
+        }
+    }
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Update the parameters of inertia estimate. Implements @ref motor_inertia_estimate_api_t::parameterUpdate
+ *
+ * @retval FSP_SUCCESS              Successfully data was updated.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ * @retval FSP_ERR_INVALID_ARGUMENT Input parameter error.
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_INERTIA_ESTIMATE_ParameterUpdate (motor_inertia_estimate_ctrl_t * const      p_ctrl,
+                                                     motor_inertia_estimate_cfg_t const * const p_cfg)
+{
+    motor_inertia_estimate_instance_ctrl_t * p_instance_ctrl = (motor_inertia_estimate_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_INERTIA_ESTIMATE_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT(NULL != p_cfg);
+    MOTOR_INERTIA_ESTIMATE_ERROR_RETURN(MOTOR_INERTIA_ESTIMATE_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    motor_inertia_estimate_extended_cfg_t * p_extend = (motor_inertia_estimate_extended_cfg_t *) p_cfg->p_extend;
+
+#if MOTOR_INERTIA_ESTIMATE_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_extend);
+
+    MOTOR_INERTIA_ESTIMATE_ERROR_RETURN(p_extend->u1_motor_polepairs != 0, FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_instance_ctrl->p_cfg = p_cfg;
+
+    p_instance_ctrl->f_inverse_motor_polepairs = 1.0F / (float) p_extend->u1_motor_polepairs;
+
+    rm_motor_inertia_estimate_set_parameter(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup MOTOR_INERTIA_ESTIMATE)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private Functions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Function Name : rm_motor_inertia_estimate_initialize
+ * Description   : Initialize variables
+ * Arguments     : p_ctrl - pointer of module data
+ * Return Value  : None
+ **********************************************************************************************************************/
+static void rm_motor_inertia_estimate_initialize (motor_inertia_estimate_instance_ctrl_t * const p_ctrl)
+{
+    motor_inertia_estimate_extended_cfg_t * p_extend =
+        (motor_inertia_estimate_extended_cfg_t *) p_ctrl->p_cfg->p_extend;
+
+    p_ctrl->start_flag = MOTOR_INERTIA_ESTIMATE_START_FLAG_STOP;
+
+    p_ctrl->mode                = MOTOR_INERTIA_ESTIMATE_MODE_START;
+    p_ctrl->u1_mode_count       = (uint8_t) MOTOR_INERTIA_ESTIMATE_MODE_START;
+    p_ctrl->speed_period        = MOTOR_INERTIA_ESTIMATE_PERIOD_NO_MOVE;
+    p_ctrl->speed_period_buffer = p_ctrl->speed_period;
+
+    p_ctrl->u4_measure_count = 0U;
+    p_ctrl->u4_wait_count    = 0U;
+
+    p_ctrl->u1_position_move_mode = MOTOR_INERTIA_ESTIMATE_MOVE_TRIANGLE;
+
+    p_ctrl->f_iq_ad              = 0.0F;
+    p_ctrl->f_summary_iq_ad      = 0.0F;
+    p_ctrl->f_position_mode_time = 0.0F;
+
+    p_ctrl->f_estimated_value = p_extend->f_rotor_inertia;
+    p_ctrl->f_inertia_value1  = 0.0F;
+    p_ctrl->f_inertia_value2  = 0.0F;
+
+    p_ctrl->f_inertia_speed_ctrl1 = 0.0F;
+    p_ctrl->f_inertia_speed_ctrl2 = 0.0F;
+    p_ctrl->f_inertia_speed_ctrl3 = 0.0F;
+    p_ctrl->f_inertia_speed_ctrl4 = 0.0F;
+    p_ctrl->f_inertia_speed_ctrl5 = 0.0F;
+    p_ctrl->f_inertia_speed_ctrl6 = 0.0F;
+    p_ctrl->f_inertia_speed_ctrl7 = 0.0F;
+    p_ctrl->f_inertia_speed_ctrl8 = 0.0F;
+
+    p_ctrl->f_inertia_integ_iq1 = 0.0F;
+    p_ctrl->f_inertia_integ_iq2 = 0.0F;
+    p_ctrl->f_inertia_integ_iq3 = 0.0F;
+    p_ctrl->f_inertia_integ_iq4 = 0.0F;
+
+    p_ctrl->f_inertia_integ_time1 = 0.0F;
+    p_ctrl->f_inertia_integ_time2 = 0.0F;
+    p_ctrl->f_inertia_integ_time3 = 0.0F;
+    p_ctrl->f_inertia_integ_time4 = 0.0F;
+}                                      /* End of function rm_motor_inertia_estimate_initialize */
+
+/***********************************************************************************************************************
+ * Function Name : rm_motor_inertia_estimate_set_parameter
+ * Description   : Necessary parameters are calculated according to extended settings
+ * Arguments     : p_ctrl - pointer of module instance
+ * Return Value  : None
+ **********************************************************************************************************************/
+static void rm_motor_inertia_estimate_set_parameter (motor_inertia_estimate_instance_ctrl_t * p_ctrl)
+{
+    float f_temp_move_rad  = 0.0F;
+    float f_temp_max_speed = 0.0F;
+
+    motor_inertia_estimate_extended_cfg_t * p_extend =
+        (motor_inertia_estimate_extended_cfg_t *) p_ctrl->p_cfg->p_extend;
+
+    /* Decision of the profile mode of position control */
+    f_temp_move_rad                = fabsf((float) p_extend->s2_move_degree * MOTOR_INERTIA_ESTIMATE_DEGREE_TO_RAD);
+    f_temp_max_speed               = (float) p_extend->u2_J_max_speed_rpm * MOTOR_INERTIA_ESTIMATE_TWO_PI_60;
+    p_ctrl->f_position_dt_time_sec = f_temp_move_rad / f_temp_max_speed;
+
+    f_temp_max_speed = p_extend->f_accel_time * f_temp_max_speed;
+    if (f_temp_max_speed >= f_temp_move_rad)
+    {
+        p_ctrl->u1_position_move_mode = MOTOR_INERTIA_ESTIMATE_MOVE_TRIANGLE;
+    }
+    else
+    {
+        p_ctrl->u1_position_move_mode = MOTOR_INERTIA_ESTIMATE_MOVE_TRAPEZOIDAL;
+    }
+
+    /* Set interval time */
+    p_ctrl->f_interval_time = p_extend->f_position_interval * p_extend->f_speed_ctrl_period;
+}
+
+/***********************************************************************************************************************
+ * Function Name : rm_motor_inertia_estimate_speed_cyclic
+ * Description   : Cyclic process at speed control (Call at timer interrupt)
+ * Arguments     : p_ctrl - pointer of module instance
+ * Return Value  : None
+ **********************************************************************************************************************/
+static void rm_motor_inertia_estimate_speed_cyclic (motor_inertia_estimate_ctrl_t * const p_ctrl)
+{
+    motor_inertia_estimate_instance_ctrl_t * p_instance_ctrl = (motor_inertia_estimate_instance_ctrl_t *) p_ctrl;
+
+    /* Position control reached to reference */
+    if (MOTOR_INERTIA_ESTIMATE_POS_STEADY == p_instance_ctrl->receive_data.u1_position_state)
+    {
+        rm_motor_inertia_estimate_steady_process(p_instance_ctrl);
+    }
+    /* Position control transition */
+    else
+    {
+        rm_motor_inertia_estimate_transition_process(p_instance_ctrl);
+    }
+}                                      /* End of function rm_motor_inertia_estimate_speed_cyclic */
+
+/***********************************************************************************************************************
+ * Function Name : rm_motor_inertia_estimate_steady_process
+ * Description   : Process at positon control in steady state (reached to reference position)
+ * Arguments     : p_ctrl - pointer of module data
+ * Return Value  : None
+ **********************************************************************************************************************/
+static void rm_motor_inertia_estimate_steady_process (motor_inertia_estimate_instance_ctrl_t * p_ctrl)
+{
+    motor_inertia_estimate_extended_cfg_t * p_extend =
+        (motor_inertia_estimate_extended_cfg_t *) p_ctrl->p_cfg->p_extend;
+
+    float f_temp1 = 0.0F;
+    float f_temp2 = 0.0F;
+    float f_time1 = 0.0F;
+    float f_time2 = 0.0F;
+
+    switch (p_ctrl->mode)
+    {
+        default:
+        {
+            // Do nothing
+            break;
+        }
+
+        case MOTOR_INERTIA_ESTIMATE_MODE_START:
+        {
+            p_ctrl->s2_initial_position_degree = p_ctrl->receive_data.s2_position_degree;
+            p_ctrl->u1_mode_count              = (uint8_t) MOTOR_INERTIA_ESTIMATE_MODE_WAIT;
+            p_ctrl->mode = MOTOR_INERTIA_ESTIMATE_MODE_WAIT;
+            break;
+        }
+
+        case MOTOR_INERTIA_ESTIMATE_MODE_WAIT:
+        {
+            p_ctrl->u4_wait_count++;
+
+            /* wait set time (confirm the stability of position control) */
+            if (p_ctrl->u4_wait_count >= (uint32_t) p_extend->f_change_mode_time)
+            {
+                /* Move to next step(mode) */
+                p_ctrl->u1_mode_count++;
+                p_ctrl->mode = (motor_inertia_estimate_mode_t) p_ctrl->u1_mode_count;
+
+                /* measurement finished */
+                if ((uint8_t) MOTOR_INERTIA_ESTIMATE_MODE_CALCULATE == p_ctrl->u1_mode_count)
+                {
+                    p_ctrl->u1_mode_count = (uint8_t) MOTOR_INERTIA_ESTIMATE_MODE_START;
+                }
+
+                /* Shorten last state transition */
+                if ((uint8_t) MOTOR_INERTIA_ESTIMATE_MODE_REVERSE == p_ctrl->u1_mode_count)
+                {
+                    p_ctrl->u4_wait_count = (uint32_t) (p_extend->f_change_mode_time * MOTOR_INERTIA_ESTIMATE_HALF);
+                }
+                else
+                {
+                    p_ctrl->u4_wait_count = 0U;
+                }
+            }
+
+            break;
+        }
+
+        case MOTOR_INERTIA_ESTIMATE_MODE_FORWARD:
+        {
+            // Set position reference to forward (initial + set degree)
+            p_ctrl->s2_position_reference_degree =
+                (int16_t) (p_extend->s2_move_degree + p_ctrl->s2_initial_position_degree);
+
+            // return to wait steady state (wait the motor will move to the reference.)
+            p_ctrl->mode = MOTOR_INERTIA_ESTIMATE_MODE_WAIT;
+            break;
+        }
+
+        case MOTOR_INERTIA_ESTIMATE_MODE_REVERSE:
+        {
+            // Set position reference to reverse (initial)
+            p_ctrl->s2_position_reference_degree = p_ctrl->s2_initial_position_degree;
+
+            // return to wait steady state (wait the motor will move to the reference.)
+            p_ctrl->mode = MOTOR_INERTIA_ESTIMATE_MODE_WAIT;
+            break;
+        }
+
+        case MOTOR_INERTIA_ESTIMATE_MODE_CALCULATE:
+        {
+            /* Stop current cyclic process */
+            p_ctrl->speed_period = MOTOR_INERTIA_ESTIMATE_PERIOD_MEASURE_FINISH;
+
+            /* calculate estimated inertia data */
+            f_time1 = p_ctrl->f_inertia_integ_time1;
+            f_time2 = p_ctrl->f_inertia_integ_time2;
+
+            /* Check none zero */
+            if (((0.0F < f_time1) || (f_time1 < 0.0F)) && ((0.0F < f_time2) || (0.0F > f_time2)))
+            {
+                f_temp1 = (float) p_extend->u1_motor_polepairs * p_extend->f_motor_m *
+                          ((p_ctrl->f_inertia_integ_iq1 / f_time1) -
+                           (p_ctrl->f_inertia_integ_iq2 / f_time2));
+                f_temp2 = ((p_ctrl->f_inertia_speed_ctrl2 - p_ctrl->f_inertia_speed_ctrl1) / f_time1) -
+                          ((p_ctrl->f_inertia_speed_ctrl4 - p_ctrl->f_inertia_speed_ctrl3) / f_time2);
+                p_ctrl->f_inertia_value1 = f_temp1 / f_temp2;
+            }
+            else
+            {
+                /* set error value */
+                p_ctrl->f_inertia_value1 = -1.0F;
+            }
+
+            f_time1 = p_ctrl->f_inertia_integ_time3;
+            f_time2 = p_ctrl->f_inertia_integ_time4;
+
+            /* Check none zero */
+            if (((0.0F < f_time1) || (f_time1 < 0.0F)) && ((0.0F < f_time2) || (0.0F > f_time2)))
+            {
+                f_temp1 = (float) p_extend->u1_motor_polepairs * p_extend->f_motor_m *
+                          ((p_ctrl->f_inertia_integ_iq3 / f_time1) - (p_ctrl->f_inertia_integ_iq4 / f_time2));
+                f_temp2 = ((p_ctrl->f_inertia_speed_ctrl6 - p_ctrl->f_inertia_speed_ctrl5) / f_time1) -
+                          ((p_ctrl->f_inertia_speed_ctrl8 - p_ctrl->f_inertia_speed_ctrl7) / f_time2);
+                p_ctrl->f_inertia_value2 = f_temp1 / f_temp2;
+            }
+            else
+            {
+                /* set error value */
+                p_ctrl->f_inertia_value2 = -1.0F;
+            }
+
+            p_ctrl->f_estimated_value =
+                (p_ctrl->f_inertia_value1 + p_ctrl->f_inertia_value2) * MOTOR_INERTIA_ESTIMATE_HALF;
+
+            /* When estimated value is minus, an error happened */
+            if (p_ctrl->f_estimated_value < 0.0F)
+            {
+                p_ctrl->f_estimated_value = -1.0F;
+                p_ctrl->mode              = MOTOR_INERTIA_ESTIMATE_MODE_ERROR;
+            }
+            else
+            {
+                /* Set status to normal finish. */
+                p_ctrl->mode = MOTOR_INERTIA_ESTIMATE_MODE_FINISH;
+            }
+
+            break;
+        }
+    }
+}                                      /* End of function rm_motor_inertia_estimate_steady_process */
+
+/***********************************************************************************************************************
+ * Function Name : rm_motor_inertia_estimate_transition_process
+ * Description   : Process at positon control in transition state
+ * Arguments     : p_ctrl - pointer of module data
+ * Return Value  : None
+ **********************************************************************************************************************/
+static void rm_motor_inertia_estimate_transition_process (motor_inertia_estimate_instance_ctrl_t * p_ctrl)
+{
+    motor_inertia_estimate_extended_cfg_t * p_extend =
+        (motor_inertia_estimate_extended_cfg_t *) p_ctrl->p_cfg->p_extend;
+
+    float f_pos_mode_time = 0.0F;
+    float aTemp_time      = p_extend->f_accel_time;
+
+    p_ctrl->f_position_mode_time += p_extend->f_speed_ctrl_period;
+
+    /* Moving time */
+    f_pos_mode_time = p_ctrl->f_position_mode_time;
+
+    /* Triangle mode */
+    if (MOTOR_INERTIA_ESTIMATE_MOVE_TRIANGLE == p_ctrl->u1_position_move_mode)
+    {
+        if ((f_pos_mode_time >= (p_extend->f_judge_low_threshold * aTemp_time)) &&
+            (f_pos_mode_time <= (p_extend->f_judge_high_threshold * aTemp_time)))
+        {
+            p_ctrl->speed_period = MOTOR_INERTIA_ESTIMATE_PERIOD_FORWARD_ACCELL;
+        }
+        else if ((f_pos_mode_time >= ((1.0F + p_extend->f_judge_low_threshold) * aTemp_time)) &&
+                 (f_pos_mode_time <= ((1.0F + p_extend->f_judge_high_threshold) * aTemp_time)))
+        {
+            p_ctrl->speed_period = MOTOR_INERTIA_ESTIMATE_PERIOD_FORWARD_DECELERATE;
+        }
+        else if ((f_pos_mode_time >= ((MOTOR_INERTIA_ESTIMATE_TWO + p_extend->f_judge_low_threshold) * aTemp_time) +
+                  p_ctrl->f_interval_time) &&
+                 (f_pos_mode_time <= ((MOTOR_INERTIA_ESTIMATE_TWO + p_extend->f_judge_high_threshold) * aTemp_time) +
+                  p_ctrl->f_interval_time))
+        {
+            p_ctrl->speed_period = MOTOR_INERTIA_ESTIMATE_PERIOD_REVERSE_ACCELL;
+        }
+        else if ((f_pos_mode_time >= ((MOTOR_INERTIA_ESTIMATE_THREE + p_extend->f_judge_low_threshold) * aTemp_time) +
+                  p_ctrl->f_interval_time) &&
+                 (f_pos_mode_time <= ((MOTOR_INERTIA_ESTIMATE_THREE + p_extend->f_judge_high_threshold) * aTemp_time) +
+                  p_ctrl->f_interval_time))
+        {
+            p_ctrl->speed_period = MOTOR_INERTIA_ESTIMATE_PERIOD_REVERSE_DECELERATE;
+        }
+        else
+        {
+            p_ctrl->speed_period = MOTOR_INERTIA_ESTIMATE_PERIOD_NO_MOVE;
+        }
+    }
+    /* Trapezoidal mode */
+    else if (MOTOR_INERTIA_ESTIMATE_MOVE_TRAPEZOIDAL == p_ctrl->u1_position_move_mode)
+    {
+        if ((f_pos_mode_time >= (p_extend->f_judge_low_threshold * aTemp_time)) &&
+            (f_pos_mode_time <= (p_extend->f_judge_high_threshold * aTemp_time)))
+        {
+            p_ctrl->speed_period = MOTOR_INERTIA_ESTIMATE_PERIOD_FORWARD_ACCELL;
+        }
+        else if ((f_pos_mode_time >=
+                  (p_ctrl->f_position_dt_time_sec + p_extend->f_judge_low_threshold * aTemp_time)) &&
+                 (f_pos_mode_time <=
+                  (p_ctrl->f_position_dt_time_sec + p_extend->f_judge_high_threshold * aTemp_time)))
+        {
+            p_ctrl->speed_period = MOTOR_INERTIA_ESTIMATE_PERIOD_FORWARD_DECELERATE;
+        }
+        else if ((f_pos_mode_time >=
+                  (p_ctrl->f_position_dt_time_sec +
+                   (1.0F + p_extend->f_judge_low_threshold) * aTemp_time + p_ctrl->f_interval_time)) &&
+                 (f_pos_mode_time <=
+                  (p_ctrl->f_position_dt_time_sec +
+                   (1.0F + p_extend->f_judge_high_threshold) * aTemp_time + p_ctrl->f_interval_time)))
+        {
+            p_ctrl->speed_period = MOTOR_INERTIA_ESTIMATE_PERIOD_REVERSE_ACCELL;
+        }
+        else if ((f_pos_mode_time >=
+                  (MOTOR_INERTIA_ESTIMATE_TWO * p_ctrl->f_position_dt_time_sec +
+                   (1.0F + p_extend->f_judge_low_threshold) * aTemp_time + p_ctrl->f_interval_time)) &&
+                 (f_pos_mode_time <=
+                  (MOTOR_INERTIA_ESTIMATE_TWO * p_ctrl->f_position_dt_time_sec +
+                   (1.0F + p_extend->f_judge_high_threshold) * aTemp_time + p_ctrl->f_interval_time)))
+        {
+            p_ctrl->speed_period = MOTOR_INERTIA_ESTIMATE_PERIOD_REVERSE_DECELERATE;
+        }
+        else
+        {
+            p_ctrl->speed_period = MOTOR_INERTIA_ESTIMATE_PERIOD_NO_MOVE;
+        }
+    }
+    else
+    {
+        /* Do nothing */
+    }
+}                                      /* End of function rm_motor_inertia_estimate_transition_process */
diff --git a/ra/fsp/src/rm_motor_position/rm_motor_position.c b/ra/fsp/src/rm_motor_position/rm_motor_position.c
index c46fe8780..b4a4b7f8a 100644
--- a/ra/fsp/src/rm_motor_position/rm_motor_position.c
+++ b/ra/fsp/src/rm_motor_position/rm_motor_position.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -101,6 +101,7 @@ const motor_position_api_t g_motor_position_on_motor_position =
     .speedReferencePControlGet    = RM_MOTOR_POSITION_SpeedReferencePControlGet,
     .speedReferenceIpdControlGet  = RM_MOTOR_POSITION_SpeedReferenceIpdControlGet,
     .speedReferenceFeedforwardGet = RM_MOTOR_POSITION_SpeedReferenceFeedforwardGet,
+    .infoGet                      = RM_MOTOR_POSITION_InfoGet,
     .parameterUpdate              = RM_MOTOR_POSITION_ParameterUpdate,
 };
 
@@ -480,6 +481,31 @@ fsp_err_t RM_MOTOR_POSITION_SpeedReferenceFeedforwardGet (motor_position_ctrl_t
     return FSP_SUCCESS;
 }
 
+/*******************************************************************************************************************//**
+ * @brief Get position information.
+ *
+ * @retval FSP_SUCCESS              Successfully data is set.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ * @retval FSP_ERR_INVALID_ARGUMENT Output pointer is NULL.
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_POSITION_InfoGet (motor_position_ctrl_t * const p_ctrl, motor_position_info_t * const p_info)
+{
+    motor_position_instance_ctrl_t * p_instance_ctrl = (motor_position_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_POSITION_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_instance_ctrl);
+    MOTOR_POSITION_ERROR_RETURN(MOTOR_POSITION_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    MOTOR_POSITION_ERROR_RETURN(NULL != p_info, FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_info->u1_state_position_profile = p_instance_ctrl->st_profiling.u1_state_pos_pf;
+    p_info->s2_position_degree        =
+        (int16_t) (p_instance_ctrl->st_variable.f4_pos_rad * MOTOR_POSITION_360_TWOPI);
+
+    return FSP_SUCCESS;
+}
+
 /*******************************************************************************************************************//**
  * @brief Update the parameters of Position Control Calculation. Implements @ref motor_position_api_t::parameterUpdate
  *
diff --git a/ra/fsp/src/rm_motor_position/rm_motor_position_library.h b/ra/fsp/src/rm_motor_position/rm_motor_position_library.h
index 6755def07..d868c64e5 100644
--- a/ra/fsp/src/rm_motor_position/rm_motor_position_library.h
+++ b/ra/fsp/src/rm_motor_position/rm_motor_position_library.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_motor_return_origin/rm_motor_return_origin.c b/ra/fsp/src/rm_motor_return_origin/rm_motor_return_origin.c
new file mode 100644
index 000000000..cdb54e59a
--- /dev/null
+++ b/ra/fsp/src/rm_motor_return_origin/rm_motor_return_origin.c
@@ -0,0 +1,645 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include <math.h>
+#include <stdint.h>
+#include "rm_motor_return_origin.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+#define     MOTOR_RETURN_ORIGIN_OPEN             (('M' << 24U) | ('T' << 16U) | ('R' << 8U) | ('Z' << 0U))
+
+#define     MOTOR_RETURN_ORIGIN_TWO_PI           (6.283185307F)
+#define     MOTOR_RETURN_ORIGIN_TWO_PI_60        (6.283185307F / 60.0F)
+#define     MOTOR_RETURN_ORIGIN_RAD_TO_DEGREE    (360.0F / MOTOR_RETURN_ORIGIN_TWO_PI)
+#define     MOTOR_RETURN_ORIGIN_HALF             (0.5F)
+
+#ifndef MOTOR_RETURN_ORIGIN_ERROR_RETURN
+
+ #define    MOTOR_RETURN_ORIGIN_ERROR_RETURN(a, err)    FSP_ERROR_RETURN((a), (err))
+#endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+static void  rm_motor_return_origin_initialize(motor_return_origin_instance_ctrl_t * const p_ctrl);
+static void  rm_motor_return_origin_speed_cyclic(motor_return_origin_instance_ctrl_t * const p_ctrl);
+static float rm_motor_return_origin_push(motor_return_origin_instance_ctrl_t * const p_ctrl);
+static float rm_motor_return_origin_calculate_search_speed_accel(motor_return_origin_instance_ctrl_t * p_ctrl);
+static float rm_motor_return_origin_calculate_search_speed_decleration(motor_return_origin_instance_ctrl_t * p_ctrl);
+static float rm_motor_return_origin_calc_decele_rad(float f4_move_pos, float f4_speed, float f4_acc);
+
+/***********************************************************************************************************************
+ * Private global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Global variables
+ **********************************************************************************************************************/
+const motor_return_origin_api_t g_motor_return_origin_on_motor_return_origin =
+{
+    .open            = RM_MOTOR_RETURN_ORIGIN_Open,
+    .close           = RM_MOTOR_RETURN_ORIGIN_Close,
+    .start           = RM_MOTOR_RETURN_ORIGIN_Start,
+    .stop            = RM_MOTOR_RETURN_ORIGIN_Stop,
+    .reset           = RM_MOTOR_RETURN_ORIGIN_Reset,
+    .infoGet         = RM_MOTOR_RETURN_ORIGIN_InfoGet,
+    .dataSet         = RM_MOTOR_RETURN_ORIGIN_DataSet,
+    .speedCyclic     = RM_MOTOR_RETURN_ORIGIN_SpeedCyclic,
+    .parameterUpdate = RM_MOTOR_RETURN_ORIGIN_ParameterUpdate,
+};
+
+/*******************************************************************************************************************//**
+ * @addtogroup MOTOR_RETURN_ORIGIN
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @brief Opens and configures the motor return origin module. Implements @ref motor_return_origin_api_t::open.
+ *
+ * Example:
+ * @snippet rm_motor_return_origin_example.c RM_MOTOR_RETURN_ORIGIN_Open
+ *
+ * @retval FSP_SUCCESS              Motor return origin module successfully configured.
+ * @retval FSP_ERR_ASSERTION        Null pointer, or one or more configuration options is invalid.
+ * @retval FSP_ERR_ALREADY_OPEN     Module is already open.  This module can only be opened once.
+ * @retval FSP_ERR_INVALID_ARGUMENT Input parameter error.
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_RETURN_ORIGIN_Open (motor_return_origin_ctrl_t * const      p_ctrl,
+                                       motor_return_origin_cfg_t const * const p_cfg)
+{
+    motor_return_origin_instance_ctrl_t * p_instance_ctrl = (motor_return_origin_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_RETURN_ORIGIN_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT(NULL != p_cfg);
+    MOTOR_RETURN_ORIGIN_ERROR_RETURN(MOTOR_RETURN_ORIGIN_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
+#endif
+
+    motor_return_origin_extended_cfg_t * p_extended_cfg = (motor_return_origin_extended_cfg_t *) p_cfg->p_extend;
+
+#if MOTOR_RETURN_ORIGIN_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_extended_cfg);
+
+    MOTOR_RETURN_ORIGIN_ERROR_RETURN(p_extended_cfg->f_speed_ctrl_period >= 0, FSP_ERR_INVALID_ARGUMENT);
+#endif
+    p_instance_ctrl->p_cfg = p_cfg;
+
+    rm_motor_return_origin_initialize(p_instance_ctrl);
+
+    /* Pushing mode */
+    if (MOTOR_RETURN_ORIGIN_MODE_PUSH == p_instance_ctrl->p_cfg->mode)
+    {
+        float temp_search_speed;
+        p_instance_ctrl->st_pushing.f_judge_iq =
+            p_extended_cfg->f_maximum_current * p_extended_cfg->f_current_limit_percent_push;
+        p_instance_ctrl->st_pushing.f_pushing_counts =
+            p_extended_cfg->f_pushing_time / p_extended_cfg->f_speed_ctrl_period;
+        p_instance_ctrl->f_accel_speed =
+            fabsf((MOTOR_RETURN_ORIGIN_TWO_PI_60 * p_extended_cfg->f_speed_ctrl_period *
+                   p_extended_cfg->f_speed_ctrl_period) * p_extended_cfg->f_return_accel_rpm *
+                  p_extended_cfg->f_mechanical_gear_ratio);
+        temp_search_speed = p_extended_cfg->f_search_speed_rpm * p_extended_cfg->f_mechanical_gear_ratio *
+                            MOTOR_RETURN_ORIGIN_TWO_PI_60;
+        if (temp_search_speed < 0.0F)
+        {
+            p_instance_ctrl->s1_direction = -1;
+        }
+
+        p_instance_ctrl->f_search_speed = fabsf(temp_search_speed * p_extended_cfg->f_speed_ctrl_period);
+    }
+
+    /* Mark driver as open */
+    p_instance_ctrl->open = MOTOR_RETURN_ORIGIN_OPEN;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Disables specified motor return origin module. Implements @ref motor_return_origin_api_t::close.
+ *
+ * Example:
+ * @snippet rm_motor_return_origin_example.c RM_MOTOR_RETURN_ORIGIN_Close
+ *
+ * @retval FSP_SUCCESS              Successfully closed.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_RETURN_ORIGIN_Close (motor_return_origin_ctrl_t * const p_ctrl)
+{
+    motor_return_origin_instance_ctrl_t * p_instance_ctrl = (motor_return_origin_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_RETURN_ORIGIN_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    MOTOR_RETURN_ORIGIN_ERROR_RETURN(MOTOR_RETURN_ORIGIN_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    rm_motor_return_origin_initialize(p_instance_ctrl);
+
+    p_instance_ctrl->open = 0U;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Start return origin function. Implements @ref motor_return_origin_api_t::start.
+ *
+ * Example:
+ * @snippet rm_motor_return_origin_example.c RM_MOTOR_RETURN_ORIGIN_Start
+ *
+ * @retval FSP_SUCCESS              Successfully started.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_RETURN_ORIGIN_Start (motor_return_origin_ctrl_t * const p_ctrl)
+{
+    motor_return_origin_instance_ctrl_t * p_instance_ctrl = (motor_return_origin_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_RETURN_ORIGIN_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    MOTOR_RETURN_ORIGIN_ERROR_RETURN(MOTOR_RETURN_ORIGIN_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    p_instance_ctrl->start_flag = MOTOR_RETURN_ORIGIN_START_FLAG_START;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Stop (Cancel) return origin function. Implements @ref motor_return_origin_api_t::stop.
+ *
+ * Example:
+ * @snippet rm_motor_return_origin_example.c RM_MOTOR_RETURN_ORIGIN_Stop
+ *
+ * @retval FSP_SUCCESS              Successfully stopped (canceled).
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_RETURN_ORIGIN_Stop (motor_return_origin_ctrl_t * const p_ctrl)
+{
+    motor_return_origin_instance_ctrl_t * p_instance_ctrl = (motor_return_origin_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_RETURN_ORIGIN_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    MOTOR_RETURN_ORIGIN_ERROR_RETURN(MOTOR_RETURN_ORIGIN_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    p_instance_ctrl->start_flag = MOTOR_RETURN_ORIGIN_START_FLAG_STOP;
+
+    rm_motor_return_origin_initialize(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Reset variables of return origin module. Implements @ref motor_return_origin_api_t::reset.
+ *
+ * @retval FSP_SUCCESS              Successfully reset.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_RETURN_ORIGIN_Reset (motor_return_origin_ctrl_t * const p_ctrl)
+{
+    motor_return_origin_instance_ctrl_t * p_instance_ctrl = (motor_return_origin_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_RETURN_ORIGIN_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    MOTOR_RETURN_ORIGIN_ERROR_RETURN(MOTOR_RETURN_ORIGIN_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    rm_motor_return_origin_initialize(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Get information of return origin. Implements @ref motor_return_origin_api_t::infoGet.
+ *
+ * Example:
+ * @snippet rm_motor_return_origin_example.c RM_MOTOR_RETURN_ORIGIN_InfoGet
+ *
+ * @retval FSP_SUCCESS              Successfully get data.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ * @retval FSP_ERR_INVALID_ARGUMENT Input parameter error.
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_RETURN_ORIGIN_InfoGet (motor_return_origin_ctrl_t * const p_ctrl,
+                                          motor_return_origin_info_t * const p_info)
+{
+    motor_return_origin_instance_ctrl_t * p_instance_ctrl = (motor_return_origin_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_RETURN_ORIGIN_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    MOTOR_RETURN_ORIGIN_ERROR_RETURN(MOTOR_RETURN_ORIGIN_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    MOTOR_RETURN_ORIGIN_ERROR_RETURN(p_info != NULL, FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_info->f_position_reference_degree = p_instance_ctrl->f_position_reference_degree;
+    p_info->state          = p_instance_ctrl->state;
+    p_info->f_result_angle = p_instance_ctrl->f_angle_degree_on_edge;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Set necessary data to return origin function. Implements @ref motor_return_origin_api_t::dataSet.
+ *
+ * Example:
+ * @snippet rm_motor_return_origin_example.c RM_MOTOR_RETURN_ORIGIN_DataSet
+ *
+ * @retval FSP_SUCCESS              Successfully set data.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ * @retval FSP_ERR_INVALID_ARGUMENT Input parameter error.
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_RETURN_ORIGIN_DataSet (motor_return_origin_ctrl_t * const     p_ctrl,
+                                          motor_return_origin_set_data_t * const p_set_data)
+{
+    motor_return_origin_instance_ctrl_t * p_instance_ctrl = (motor_return_origin_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_RETURN_ORIGIN_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    MOTOR_RETURN_ORIGIN_ERROR_RETURN(MOTOR_RETURN_ORIGIN_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    MOTOR_RETURN_ORIGIN_ERROR_RETURN(p_set_data != NULL, FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_instance_ctrl->receive_data = *p_set_data;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Cyclic process of return origin function at speed control period. (Called at timer interrupt.)
+ * Implements @ref motor_return_origin_api_t::speedCyclic.
+ *
+ * @retval FSP_SUCCESS              Successfully perform the process.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_RETURN_ORIGIN_SpeedCyclic (motor_return_origin_ctrl_t * const p_ctrl)
+{
+    motor_return_origin_instance_ctrl_t * p_instance_ctrl = (motor_return_origin_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_RETURN_ORIGIN_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    MOTOR_RETURN_ORIGIN_ERROR_RETURN(MOTOR_RETURN_ORIGIN_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Only work after started */
+    if (MOTOR_RETURN_ORIGIN_START_FLAG_START == p_instance_ctrl->start_flag)
+    {
+        rm_motor_return_origin_speed_cyclic(p_instance_ctrl);
+    }
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @brief Update the parameters of return origin function. Implements @ref motor_return_origin_api_t::parameterUpdate
+ *
+ * @retval FSP_SUCCESS              Successfully data was updated.
+ * @retval FSP_ERR_ASSERTION        Null pointer.
+ * @retval FSP_ERR_NOT_OPEN         Module is not open.
+ * @retval FSP_ERR_INVALID_ARGUMENT Input parameter error.
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_RETURN_ORIGIN_ParameterUpdate (motor_return_origin_ctrl_t * const      p_ctrl,
+                                                  motor_return_origin_cfg_t const * const p_cfg)
+{
+    motor_return_origin_instance_ctrl_t * p_instance_ctrl = (motor_return_origin_instance_ctrl_t *) p_ctrl;
+
+#if MOTOR_RETURN_ORIGIN_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT(NULL != p_cfg);
+    MOTOR_RETURN_ORIGIN_ERROR_RETURN(MOTOR_RETURN_ORIGIN_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    motor_return_origin_extended_cfg_t * p_extended_cfg = (motor_return_origin_extended_cfg_t *) p_cfg->p_extend;
+
+#if MOTOR_RETURN_ORIGIN_CFG_PARAM_CHECKING_ENABLE
+    MOTOR_RETURN_ORIGIN_ERROR_RETURN(p_extended_cfg->f_speed_ctrl_period >= 0, FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    p_instance_ctrl->p_cfg = p_cfg;
+
+    if (MOTOR_RETURN_ORIGIN_MODE_PUSH == p_instance_ctrl->p_cfg->mode)
+    {
+        float temp_search_speed;
+        p_instance_ctrl->st_pushing.f_judge_iq =
+            p_extended_cfg->f_maximum_current * p_extended_cfg->f_current_limit_percent_push;
+        p_instance_ctrl->st_pushing.f_pushing_counts =
+            p_extended_cfg->f_pushing_time / p_extended_cfg->f_speed_ctrl_period;
+        p_instance_ctrl->f_accel_speed =
+            fabsf((MOTOR_RETURN_ORIGIN_TWO_PI_60 * p_extended_cfg->f_speed_ctrl_period *
+                   p_extended_cfg->f_speed_ctrl_period) * p_extended_cfg->f_return_accel_rpm *
+                  p_extended_cfg->f_mechanical_gear_ratio);
+        temp_search_speed = p_extended_cfg->f_search_speed_rpm * p_extended_cfg->f_mechanical_gear_ratio *
+                            MOTOR_RETURN_ORIGIN_TWO_PI_60;
+        if (temp_search_speed < 0.0F)
+        {
+            p_instance_ctrl->s1_direction = -1;
+        }
+
+        p_instance_ctrl->f_search_speed = fabsf(temp_search_speed * p_extended_cfg->f_speed_ctrl_period);
+    }
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup MOTOR_RETURN_ORIGIN)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private Functions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Function Name : rm_motor_return_origin_initialize
+ * Description   : Initialize variables
+ * Arguments     : p_ctrl - pointer of module data
+ * Return Value  : None
+ **********************************************************************************************************************/
+static void rm_motor_return_origin_initialize (motor_return_origin_instance_ctrl_t * const p_ctrl)
+{
+    p_ctrl->start_flag                     = MOTOR_RETURN_ORIGIN_START_FLAG_STOP;
+    p_ctrl->state                          = MOTOR_RETURN_ORIGIN_STATE_START;
+    p_ctrl->s1_direction                   = 1;
+    p_ctrl->f_angle_degree_on_edge         = 0.0F;
+    p_ctrl->f_current_speed                = 0.0F;
+    p_ctrl->f_origin_position_angle_degree = 0.0F;
+
+    p_ctrl->f_position_reference_degree = 0.0F;
+
+    if (MOTOR_RETURN_ORIGIN_MODE_PUSH == p_ctrl->p_cfg->mode)
+    {
+        p_ctrl->st_pushing.u4_time_counter = 0U;
+        p_ctrl->st_pushing.f_sum_position  = 0.0F;
+        p_ctrl->st_pushing.u4_sum_counter  = 0U;
+        p_ctrl->st_pushing.f_move_amount   = 0.0F;
+    }
+}                                      /* End of function rm_motor_return_origin_initialize */
+
+/***********************************************************************************************************************
+ * Function Name : rm_motor_return_origin_speed_cyclic
+ * Description   : Cyclic process at speed control (Call at timer interrupt)
+ * Arguments     : p_ctrl - pointer of module data
+ * Return Value  : None
+ **********************************************************************************************************************/
+static void rm_motor_return_origin_speed_cyclic (motor_return_origin_instance_ctrl_t * const p_ctrl)
+{
+    /* Select the origin return method. */
+    switch (p_ctrl->p_cfg->mode)
+    {
+        case MOTOR_RETURN_ORIGIN_MODE_PUSH:
+        {
+            p_ctrl->f_position_reference_degree = rm_motor_return_origin_push(p_ctrl);
+            break;
+        }
+
+        default:
+        {
+            /* Do Nothing */
+            break;
+        }
+    }
+}                                      /* End of function rm_motor_return_origin_speed_cyclic */
+
+/***********************************************************************************************************************
+ * Function Name : rm_motor_return_origin_push
+ * Description   : Cyclic process at speed control with pushing
+ * Arguments     : p_ctrl - pointer of module data
+ * Return Value  : Calculated position reference
+ **********************************************************************************************************************/
+static float rm_motor_return_origin_push (motor_return_origin_instance_ctrl_t * const p_ctrl)
+{
+    float          f_mechanical_reverse;      /* mechanical reverse angle [rad] */
+    volatile float f_calculated_ref_position; /* calculated reference potition */
+    motor_return_origin_extended_cfg_t * p_extended_cfg =
+        (motor_return_origin_extended_cfg_t *) p_ctrl->p_cfg->p_extend;
+
+    f_calculated_ref_position = p_ctrl->f_position_reference_degree;
+
+    switch (p_ctrl->state)
+    {
+        default:
+        {
+            /* Do Nothing */
+            break;
+        }
+
+        case MOTOR_RETURN_ORIGIN_STATE_START:
+        {
+            /* Initilize valiables to calculate */
+            p_ctrl->st_pushing.u4_time_counter = 0U;
+            p_ctrl->st_pushing.f_sum_position  = 0.0F;
+            p_ctrl->st_pushing.u4_sum_counter  = 0U;
+            p_ctrl->st_pushing.f_move_amount   = 0.0F;
+
+            /* Go to search the stopper */
+            p_ctrl->state = MOTOR_RETURN_ORIGIN_STATE_SEARCH_STOPPER;
+            break;
+        }
+
+        case MOTOR_RETURN_ORIGIN_STATE_SEARCH_STOPPER:
+        {
+            /* iq reached set the value to judge the collision (push to the stopper) */
+            if (fabsf(p_ctrl->receive_data.f_iq) >= p_ctrl->st_pushing.f_judge_iq)
+            {
+                /* Measure time for pushing */
+                p_ctrl->st_pushing.u4_time_counter++;
+
+                /* Reach to pushing time */
+                if (p_ctrl->st_pushing.u4_time_counter >= (uint32_t) p_ctrl->st_pushing.f_pushing_counts)
+                {
+                    /* Calculate stopper position (average) */
+                    p_ctrl->f_angle_degree_on_edge =
+                        p_ctrl->st_pushing.f_sum_position / (float) p_ctrl->st_pushing.u4_sum_counter;
+
+                    /* Calculate origin position */
+                    f_mechanical_reverse =
+                        fabsf(p_extended_cfg->f_mechanical_gear_ratio) *
+                        p_ctrl->s1_direction * p_extended_cfg->f_return_degree;
+                    p_ctrl->f_origin_position_angle_degree = p_ctrl->f_angle_degree_on_edge - f_mechanical_reverse;
+
+                    /* Set reference to current position */
+                    f_calculated_ref_position = p_ctrl->receive_data.f_position_degree;
+
+                    p_ctrl->f_current_speed = 0.0F;
+
+                    p_ctrl->st_pushing.f_move_amount  = fabsf(f_mechanical_reverse);
+                    p_ctrl->st_pushing.f_move_amount -=
+                        rm_motor_return_origin_calc_decele_rad(p_ctrl->st_pushing.f_move_amount,
+                                                               p_ctrl->f_search_speed,
+                                                               p_ctrl->f_accel_speed);
+
+                    p_ctrl->state = MOTOR_RETURN_ORIGIN_STATE_REVERSE;
+                }
+                /* Over the half of pushing time */
+                else if (p_ctrl->st_pushing.u4_time_counter >= ((uint32_t) p_ctrl->st_pushing.f_pushing_counts >> 1))
+                {
+                    /* Count up the summary counter */
+                    p_ctrl->st_pushing.u4_sum_counter++;
+
+                    /* Summurise current position data to calculate the average value of rotor position */
+                    p_ctrl->st_pushing.f_sum_position += p_ctrl->receive_data.f_position_degree;
+                }
+                else
+                {
+                    /* Do nothing */
+                }
+            }
+            /* The stopper could not be detected. */
+            else if (((p_extended_cfg->f_over_degree > 0.0F) || (p_extended_cfg->f_over_degree < 0.0F)) &&
+                     (p_ctrl->st_pushing.f_move_amount > p_extended_cfg->f_over_degree))
+            {
+                // Set state to error and stop the process
+                f_calculated_ref_position = (float) p_ctrl->s1_direction * p_ctrl->st_pushing.f_move_amount;
+                p_ctrl->state             = MOTOR_RETURN_ORIGIN_STATE_ERROR;
+                p_ctrl->start_flag        = MOTOR_RETURN_ORIGIN_START_FLAG_STOP;
+            }
+            else
+            {
+                /* Do nothing */
+            }
+
+            if (MOTOR_RETURN_ORIGIN_STATE_SEARCH_STOPPER == p_ctrl->state)
+            {
+                rm_motor_return_origin_calculate_search_speed_accel(p_ctrl);
+                p_ctrl->st_pushing.f_move_amount += p_ctrl->f_current_speed;
+                f_calculated_ref_position         = (float) p_ctrl->s1_direction * p_ctrl->st_pushing.f_move_amount;
+            }
+
+            break;
+        }
+
+        /* Reverse from stopper */
+        case MOTOR_RETURN_ORIGIN_STATE_REVERSE:
+        {
+            rm_motor_return_origin_calculate_search_speed_accel(p_ctrl);
+            p_ctrl->st_pushing.f_move_amount -= p_ctrl->f_current_speed;
+            f_calculated_ref_position         = (float) p_ctrl->s1_direction * p_ctrl->f_current_speed;
+            if (p_ctrl->st_pushing.f_move_amount <= 0.0F)
+            {
+                p_ctrl->state = MOTOR_RETURN_ORIGIN_STATE_DECELERATE;
+            }
+
+            break;
+        }
+
+        /* Deceleration of speed */
+        case MOTOR_RETURN_ORIGIN_STATE_DECELERATE:
+        {
+            f_calculated_ref_position -=
+                (float) p_ctrl->s1_direction * rm_motor_return_origin_calculate_search_speed_decleration(p_ctrl);
+            if ((p_ctrl->f_current_speed > 0.0F) || (p_ctrl->f_current_speed < 0.0F))
+            {
+                /* Do nothing */
+            }
+            else                       // p_ctrl->f_current_speed == 0.0F
+            {
+                f_calculated_ref_position = p_ctrl->f_origin_position_angle_degree;
+                p_ctrl->state             = MOTOR_RETURN_ORIGIN_STATE_DONE;
+                p_ctrl->start_flag        = MOTOR_RETURN_ORIGIN_START_FLAG_STOP;
+            }
+
+            break;
+        }
+    }
+
+    return f_calculated_ref_position;
+}                                      /* End of function rm_motor_return_origin_push */
+
+/***********************************************************************************************************************
+ * Function Name: rm_motor_return_origin_calculate_search_speed_accel
+ * Description  : Speed calculation when accelerating
+ * Arguments    : p_ctrl - pointer of module data
+ * Return Value : speed[rad / sample time] ,absolute value.
+ ***********************************************************************************************************************/
+static float rm_motor_return_origin_calculate_search_speed_accel (motor_return_origin_instance_ctrl_t * p_ctrl)
+{
+    p_ctrl->f_current_speed += p_ctrl->f_accel_speed;
+    if (p_ctrl->f_current_speed > p_ctrl->f_search_speed)
+    {
+        p_ctrl->f_current_speed = p_ctrl->f_search_speed;
+    }
+
+    return p_ctrl->f_current_speed;
+}                                      /* End of function rm_motor_return_origin_calculate_search_speed_accel */
+
+/***********************************************************************************************************************
+ * Function Name: rm_motor_return_origin_calculate_search_speed_decleration
+ * Description  : Speed calculation during deceleration
+ * Arguments    : p_ctrl - pointer of module data
+ * Return Value : speed[rad / sample time] ,absolute value.
+ ***********************************************************************************************************************/
+static float rm_motor_return_origin_calculate_search_speed_decleration (motor_return_origin_instance_ctrl_t * p_ctrl)
+{
+    p_ctrl->f_current_speed -= p_ctrl->f_accel_speed;
+    if (p_ctrl->f_current_speed <= 0.0F)
+    {
+        p_ctrl->f_current_speed = 0.0F;
+    }
+
+    return p_ctrl->f_current_speed;
+}                                      /* End of function rm_motor_return_origin_calculate_search_speed_decleration */
+
+/***********************************************************************************************************************
+ * Function Name: rm_motor_return_origin_calc_decele_rad
+ * Description  : Calculate deceleration distance.
+ * Arguments    : f4_move_pos - Amount of movement [rad]
+ *               f4_speed - max speed [rad / sample time] ,absolute value
+ *               f4_acc -  acc  [rad / sample time^2] ,absolute value
+ * Return Value : deceleration distance [rad] ,absolute value
+ ***********************************************************************************************************************/
+static float rm_motor_return_origin_calc_decele_rad (float f4_move_pos, float f4_speed, float f4_acc)
+{
+    float f4_ret = 0.0F;               /* return value */
+    float f4_work;                     /* work buffer */
+    float f4_ratio;                    /* movement amount ratio */
+
+    if ((f4_speed > 0.0F) || (f4_speed < 0.0F))
+    {
+        f4_work  = f4_speed * f4_speed / f4_acc;
+        f4_ratio = sqrtf(fabsf(f4_move_pos / f4_work));
+        if (f4_ratio < 1.0F)
+        {
+            f4_ret = fabsf(MOTOR_RETURN_ORIGIN_HALF * f4_ratio * f4_work);
+        }
+        else
+        {
+            f4_ret = fabsf(MOTOR_RETURN_ORIGIN_HALF * f4_work);
+        }
+    }
+
+    return f4_ret;
+}                                      /* End of function rm_motor_return_origin_calc_decele_rad */
diff --git a/ra/fsp/src/rm_motor_sense_encoder/rm_motor_sense_encoder.c b/ra/fsp/src/rm_motor_sense_encoder/rm_motor_sense_encoder.c
index 7eb83d355..8d89b8a3b 100644
--- a/ra/fsp/src/rm_motor_sense_encoder/rm_motor_sense_encoder.c
+++ b/ra/fsp/src/rm_motor_sense_encoder/rm_motor_sense_encoder.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_motor_sense_hall/rm_motor_sense_hall.c b/ra/fsp/src/rm_motor_sense_hall/rm_motor_sense_hall.c
index fb9cf51c2..0b9c8665f 100644
--- a/ra/fsp/src/rm_motor_sense_hall/rm_motor_sense_hall.c
+++ b/ra/fsp/src/rm_motor_sense_hall/rm_motor_sense_hall.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -363,12 +363,12 @@ fsp_err_t RM_MOTOR_SENSE_HALL_AngleSpeedGet (motor_angle_ctrl_t * const p_ctrl,
         }
     }
 
-    /* Angle limit within 0..2PI */
+    /* Converted angle within 0..2PI */
     if (f_temp_angle > MOTOR_SENSE_HALL_TWOPI)
     {
         f_temp_angle = f_temp_angle - MOTOR_SENSE_HALL_TWOPI;
     }
-    else if (f_temp_angle < -MOTOR_SENSE_HALL_TWOPI)
+    else if (f_temp_angle < 0.0F)
     {
         f_temp_angle = f_temp_angle + MOTOR_SENSE_HALL_TWOPI;
     }
@@ -377,11 +377,6 @@ fsp_err_t RM_MOTOR_SENSE_HALL_AngleSpeedGet (motor_angle_ctrl_t * const p_ctrl,
         /* Do nothing */
     }
 
-    if (f_temp_angle < 0.0F)
-    {
-        f_temp_angle = 0.0F;
-    }
-
     *p_speed = p_instance_ctrl->f_calculated_speed;
     *p_angle = f_temp_angle;
 
diff --git a/ra/fsp/src/rm_motor_sense_induction/rm_motor_sense_induction.c b/ra/fsp/src/rm_motor_sense_induction/rm_motor_sense_induction.c
index a7d708d32..d8ca7522f 100644
--- a/ra/fsp/src/rm_motor_sense_induction/rm_motor_sense_induction.c
+++ b/ra/fsp/src/rm_motor_sense_induction/rm_motor_sense_induction.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_motor_sensorless/rm_motor_sensorless.c b/ra/fsp/src/rm_motor_sensorless/rm_motor_sensorless.c
index f110b3296..450d6c9d4 100644
--- a/ra/fsp/src/rm_motor_sensorless/rm_motor_sensorless.c
+++ b/ra/fsp/src/rm_motor_sensorless/rm_motor_sensorless.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -143,6 +143,7 @@ const motor_api_t g_motor_on_sensorless =
     .errorCheck      = RM_MOTOR_SENSORLESS_ErrorCheck,
     .positionSet     = RM_MOTOR_SENSORLESS_PositionSet,
     .waitStopFlagGet = RM_MOTOR_SENSORLESS_WaitStopFlagGet,
+    .functionSelect  = RM_MOTOR_SENSORLESS_FunctionSelect,
 };
 
 /*******************************************************************************************************************//**
@@ -600,8 +601,6 @@ fsp_err_t RM_MOTOR_SENSORLESS_ErrorCheck (motor_ctrl_t * const p_ctrl, uint16_t
 /*******************************************************************************************************************//**
  * @brief Set position reference. Implements @ref motor_api_t::positionSet.
  *
- * Example:
- *
  * @retval FSP_ERR_UNSUPPORTED      Unsupported.
  *
  * @note
@@ -619,8 +618,6 @@ fsp_err_t RM_MOTOR_SENSORLESS_PositionSet (motor_ctrl_t * const
 /*******************************************************************************************************************//**
  * @brief Get wait stop flag. Implements @ref motor_api_t::waitStopFlagGet.
  *
- * Example:
- *
  * @retval FSP_ERR_UNSUPPORTED      Unsupported.
  *
  * @note
@@ -634,6 +631,22 @@ fsp_err_t RM_MOTOR_SENSORLESS_WaitStopFlagGet (motor_ctrl_t * const p_ctrl, moto
     return FSP_ERR_UNSUPPORTED;
 }
 
+/*******************************************************************************************************************//**
+ * @brief Select function. Implements @ref motor_api_t::functionSelect.
+ *
+ * @retval FSP_ERR_UNSUPPORTED      Unsupported.
+ *
+ * @note
+ *
+ **********************************************************************************************************************/
+fsp_err_t RM_MOTOR_SENSORLESS_FunctionSelect (motor_ctrl_t * const p_ctrl, motor_function_select_t const function)
+{
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+    FSP_PARAMETER_NOT_USED(function);
+
+    return FSP_ERR_UNSUPPORTED;
+}
+
 /*******************************************************************************************************************//**
  * @} (end addtogroup MOTOR_SENSORLESS)
  **********************************************************************************************************************/
@@ -836,19 +849,19 @@ static uint16_t rm_motor_sensorless_statemachine_event (motor_sensorless_instanc
 /***********************************************************************************************************************
  * Function Name : rm_motor_check_over_speed_error
  * Description   : Checks over-speed error
- * Arguments     : f4_speed_rad - The electrical speed[rad/s]
- *                 f4_speed_limit_rad - The speed[rad/s] threshold of the over-speed error, should be a positive value
+ * Arguments     : f4_speed - The electrical speed
+ *                 f4_speed_limit - The speed threshold of the over-speed error, should be a positive value
  * Return Value  : The over-speed error flag
  **********************************************************************************************************************/
-static inline uint16_t rm_motor_check_over_speed_error (float f4_speed_rad, float f4_speed_limit_rad)
+static inline uint16_t rm_motor_check_over_speed_error (float f4_speed, float f4_speed_limit)
 {
     float    f4_temp0;
     uint16_t u2_temp0;
 
     u2_temp0 = MOTOR_ERROR_NONE;
 
-    f4_temp0 = fabsf(f4_speed_rad);
-    if (f4_temp0 > f4_speed_limit_rad)
+    f4_temp0 = fabsf(f4_speed);
+    if (f4_temp0 > f4_speed_limit)
     {
         u2_temp0 = MOTOR_ERROR_OVER_SPEED;
     }
diff --git a/ra/fsp/src/rm_motor_speed/rm_motor_speed.c b/ra/fsp/src/rm_motor_speed/rm_motor_speed.c
index 2fcb87f98..13f4f160c 100644
--- a/ra/fsp/src/rm_motor_speed/rm_motor_speed.c
+++ b/ra/fsp/src/rm_motor_speed/rm_motor_speed.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -225,10 +225,20 @@ fsp_err_t RM_MOTOR_SPEED_Open (motor_speed_ctrl_t * const p_ctrl, motor_speed_cf
     /* Speed Observer */
     if (MOTOR_SPEED_OBSERVER_SWITCH_ENABLE == p_extended_cfg->u1_observer_swtich)
     {
-        rm_motor_speed_observer_init(&(p_instance_ctrl->st_observer));
-        rm_motor_speed_observer_gain_calc(&(p_instance_ctrl->st_observer),
-                                          &(p_extended_cfg->d_param),
-                                          p_extended_cfg->f_speed_ctrl_period);
+        if (MOTOR_SPEED_OBSERVER_SELECT_NORMAL == p_extended_cfg->observer_select)
+        {
+            rm_motor_speed_observer_init(&(p_instance_ctrl->st_observer));
+            rm_motor_speed_observer_gain_calc(&(p_instance_ctrl->st_observer),
+                                              &(p_extended_cfg->d_param),
+                                              p_extended_cfg->f_speed_ctrl_period);
+        }
+        else
+        {
+            rm_motor_speed_disturbance_observer_init(&(p_instance_ctrl->st_disturbance_observer),
+                                                     p_extended_cfg->f_natural_frequency,
+                                                     p_extended_cfg->f_speed_ctrl_period,
+                                                     p_extended_cfg->mtr_param.f4_mtr_j);
+        }
     }
 
     /* Set used timer instance */
@@ -280,7 +290,14 @@ fsp_err_t RM_MOTOR_SPEED_Close (motor_speed_ctrl_t * const p_ctrl)
 
     if (MOTOR_SPEED_OBSERVER_SWITCH_ENABLE == p_extended_cfg->u1_observer_swtich)
     {
-        rm_motor_speed_observer_reset(&(p_instance_ctrl->st_observer));
+        if (MOTOR_SPEED_OBSERVER_SELECT_NORMAL == p_extended_cfg->observer_select)
+        {
+            rm_motor_speed_observer_reset(&(p_instance_ctrl->st_observer));
+        }
+        else
+        {
+            rm_motor_speed_disturbance_observer_reset(&(p_instance_ctrl->st_disturbance_observer));
+        }
     }
 
     /* Close used timer instance */
@@ -346,7 +363,14 @@ fsp_err_t RM_MOTOR_SPEED_Reset (motor_speed_ctrl_t * const p_ctrl)
 
     if (MOTOR_SPEED_OBSERVER_SWITCH_ENABLE == p_extended_cfg->u1_observer_swtich)
     {
-        rm_motor_speed_observer_reset(&(p_instance_ctrl->st_observer));
+        if (MOTOR_SPEED_OBSERVER_SELECT_NORMAL == p_extended_cfg->observer_select)
+        {
+            rm_motor_speed_observer_reset(&(p_instance_ctrl->st_observer));
+        }
+        else
+        {
+            rm_motor_speed_disturbance_observer_reset(&(p_instance_ctrl->st_disturbance_observer));
+        }
     }
 
 #if (MOTOR_SPEED_CFG_POSITION_SUPPORTED == 1)
@@ -859,9 +883,19 @@ fsp_err_t RM_MOTOR_SPEED_ParameterUpdate (motor_speed_ctrl_t * const p_ctrl, mot
 
     if (MOTOR_SPEED_OBSERVER_SWITCH_ENABLE == p_extended_cfg->u1_observer_swtich)
     {
-        rm_motor_speed_observer_gain_calc(&(p_instance_ctrl->st_observer),
-                                          &(p_extended_cfg->d_param),
-                                          p_extended_cfg->f_speed_ctrl_period);
+        if (MOTOR_SPEED_OBSERVER_SELECT_NORMAL == p_extended_cfg->observer_select)
+        {
+            rm_motor_speed_observer_gain_calc(&(p_instance_ctrl->st_observer),
+                                              &(p_extended_cfg->d_param),
+                                              p_extended_cfg->f_speed_ctrl_period);
+        }
+        else
+        {
+            rm_motor_speed_disturbance_observer_init(&(p_instance_ctrl->st_disturbance_observer),
+                                                     p_extended_cfg->f_natural_frequency,
+                                                     p_extended_cfg->f_speed_ctrl_period,
+                                                     p_extended_cfg->mtr_param.f4_mtr_j);
+        }
     }
 
     return FSP_SUCCESS;
@@ -1088,7 +1122,6 @@ static float rm_motor_speed_set_speed_ref_encoder (motor_speed_instance_ctrl_t *
         {
             /* speed must be zero while encoder angle adjustment */
 
-            // if (MOTOR_ENCODER_CALCULATE_ANGLE_ADJUST_FIN == p_ctrl->st_input.u1_adjust_status)
             if (MOTOR_SPEED_CALCULATE_ANGLE_ADJUST_FIN == p_ctrl->st_input.u1_adjust_status)
             {
                 /* check control loop mode */
@@ -1262,9 +1295,6 @@ static float rm_motor_speed_set_speed_ref_induction (motor_speed_instance_ctrl_t
         {
             f4_speed_ref_calc_rad = p_ctrl->st_input.f_openloop_speed * p_ctrl->f_rpm2rad;
 
-            // f4_speed_ref_calc_rad = p_ctrl->st_input.f_openloop_speed * MOTOR_SPEED_TWOPI_60;
-            // f4_speed_ref_calc_rad *= p_extended_cfg->mtr_param.u2_mtr_pp;
-
             if (MOTOR_SPEED_CALCULATE_ANGLE_ADJUST_FIN == p_ctrl->st_input.u1_adjust_status)
             {
                 /* check control loop mode */
@@ -1564,10 +1594,26 @@ static float rm_motor_speed_set_iq_ref_hall (motor_speed_instance_ctrl_t * p_ctr
 
     if (MOTOR_SPEED_OBSERVER_SWITCH_ENABLE == p_extended_cfg->u1_observer_swtich)
     {
-        f4_temp_speed_rad = rm_motor_speed_observer(&p_ctrl->st_observer,
-                                                    &p_extended_cfg->mtr_param,
-                                                    p_ctrl->f_iq_ref,
-                                                    p_ctrl->st_input.f_speed_rad);
+        if (MOTOR_SPEED_OBSERVER_SELECT_NORMAL == p_extended_cfg->observer_select)
+        {
+            f4_temp_speed_rad = rm_motor_speed_observer(&p_ctrl->st_observer,
+                                                        &p_extended_cfg->mtr_param,
+                                                        p_ctrl->f_iq_ref,
+                                                        p_ctrl->st_input.f_speed_rad);
+        }
+        else
+        {
+            float f4_torque_num = 0.0F;
+            f4_torque_num = ((float) p_extended_cfg->mtr_param.u2_mtr_pp * p_extended_cfg->mtr_param.f4_mtr_m) *
+                            p_ctrl->f_iq_ref;
+            f4_temp_speed_rad = rm_motor_speed_disturbance_observer_run(&p_ctrl->st_disturbance_observer,
+                                                                        f4_torque_num,
+                                                                        p_ctrl->st_input.f_speed_rad);
+        }
+    }
+    else
+    {
+        f4_temp_speed_rad = p_ctrl->st_input.f_speed_rad;
     }
 
     f4_iq_ref_calc = rm_motor_speed_speed_pi(p_ctrl, f4_temp_speed_rad);
@@ -1670,15 +1716,30 @@ static float rm_motor_speed_set_iq_ref_encoder (motor_speed_instance_ctrl_t * p_
 
     motor_position_instance_t const * p_position = p_ctrl->p_position_instance;
 
-    // if (MOTOR_ENCODER_CALCULATE_ANGLE_ADJUST_FIN == p_ctrl->st_input.u1_adjust_status)
     if (MOTOR_SPEED_CALCULATE_ANGLE_ADJUST_FIN == p_ctrl->st_input.u1_adjust_status)
     {
         if (MOTOR_SPEED_OBSERVER_SWITCH_ENABLE == p_extended_cfg->u1_observer_swtich)
         {
-            f4_temp_speed_rad = rm_motor_speed_observer(&p_ctrl->st_observer,
-                                                        &p_extended_cfg->mtr_param,
-                                                        p_ctrl->f_iq_ref,
-                                                        p_ctrl->st_input.f_speed_rad);
+            if (MOTOR_SPEED_OBSERVER_SELECT_NORMAL == p_extended_cfg->observer_select)
+            {
+                f4_temp_speed_rad = rm_motor_speed_observer(&p_ctrl->st_observer,
+                                                            &p_extended_cfg->mtr_param,
+                                                            p_ctrl->f_iq_ref,
+                                                            p_ctrl->st_input.f_speed_rad);
+            }
+            else
+            {
+                float f4_torque_num = 0.0F;
+                f4_torque_num = ((float) p_extended_cfg->mtr_param.u2_mtr_pp * p_extended_cfg->mtr_param.f4_mtr_m) *
+                                p_ctrl->f_iq_ref;
+                f4_temp_speed_rad = rm_motor_speed_disturbance_observer_run(&p_ctrl->st_disturbance_observer,
+                                                                            f4_torque_num,
+                                                                            p_ctrl->st_input.f_speed_rad);
+            }
+        }
+        else
+        {
+            f4_temp_speed_rad = p_ctrl->st_input.f_speed_rad;
         }
 
         /*** speed PI control ***/
@@ -1752,7 +1813,6 @@ static float rm_motor_speed_set_id_ref_encoder (motor_speed_instance_ctrl_t * p_
 
                 /* angle adjusted to 0 degree */
 
-                // if (MOTOR_ENCODER_CALCULATE_ANGLE_ADJUST_0DEG == p_ctrl->st_input.u1_adjust_status)
                 if (MOTOR_SPEED_CALCULATE_ANGLE_ADJUST_0DEG == p_ctrl->st_input.u1_adjust_status)
                 {
                     /* repeat soft start */
@@ -1760,7 +1820,6 @@ static float rm_motor_speed_set_id_ref_encoder (motor_speed_instance_ctrl_t * p_
                 }
                 /* angle adjusted to Finish */
 
-                // else if (MOTOR_ENCODER_CALCULATE_ANGLE_ADJUST_FIN == p_ctrl->st_input.u1_adjust_status)
                 else if (MOTOR_SPEED_CALCULATE_ANGLE_ADJUST_FIN == p_ctrl->st_input.u1_adjust_status)
                 {
                     /* id mode transition to zero constant mode */
diff --git a/ra/fsp/src/rm_motor_speed/rm_motor_speed_library.h b/ra/fsp/src/rm_motor_speed/rm_motor_speed_library.h
index f46a441b0..48b4c4263 100644
--- a/ra/fsp/src/rm_motor_speed/rm_motor_speed_library.h
+++ b/ra/fsp/src/rm_motor_speed/rm_motor_speed_library.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -88,6 +88,15 @@ void rm_motor_speed_observer_SecondOrderLpffGainCalc(motor_speed_2nd_order_lpf_t
                                                      float                         f4_zeta,
                                                      float                         f4_ctrl_period);
 
+void rm_motor_speed_disturbance_observer_init(motor_speed_disturbance_observer_t * p_st_observer,
+                                              float                                f4_natural_freq_hz,
+                                              float                                f4_ctrl_period,
+                                              float                                f4_inertia_kgms2);
+void  rm_motor_speed_disturbance_observer_reset(motor_speed_disturbance_observer_t * p_st_observer);
+float rm_motor_speed_disturbance_observer_run(motor_speed_disturbance_observer_t * p_st_observer,
+                                              float                                f4_torque_cmd_nm,
+                                              float                                f4_speed_rad);
+
  #ifdef __cplusplus
 }
  #endif
diff --git a/ra/fsp/src/rm_netx_secure_crypto/inc/crypto_common/nx_crypto.h b/ra/fsp/src/rm_netx_secure_crypto/inc/crypto_common/nx_crypto.h
index 472fa23fe..24b143aa3 100644
--- a/ra/fsp/src/rm_netx_secure_crypto/inc/crypto_common/nx_crypto.h
+++ b/ra/fsp/src/rm_netx_secure_crypto/inc/crypto_common/nx_crypto.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_netx_secure_crypto/inc/rm_netx_secure_crypto.h b/ra/fsp/src/rm_netx_secure_crypto/inc/rm_netx_secure_crypto.h
index fde481256..8a6aa079e 100644
--- a/ra/fsp/src/rm_netx_secure_crypto/inc/rm_netx_secure_crypto.h
+++ b/ra/fsp/src/rm_netx_secure_crypto/inc/rm_netx_secure_crypto.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_aes_alt_process.c b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_aes_alt_process.c
index 1dc474aa6..bc5e5eb8a 100644
--- a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_aes_alt_process.c
+++ b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_aes_alt_process.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_cbc_alt_process.c b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_cbc_alt_process.c
index 27266731f..ccca25fad 100644
--- a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_cbc_alt_process.c
+++ b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_cbc_alt_process.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ctr_alt_process.c b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ctr_alt_process.c
index 71ba81bc8..138cd7ccb 100644
--- a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ctr_alt_process.c
+++ b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ctr_alt_process.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ec_alt_process.c b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ec_alt_process.c
index 9ae6c2058..32685644c 100644
--- a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ec_alt_process.c
+++ b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ec_alt_process.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ecdh_alt_process.c b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ecdh_alt_process.c
index d1a289e8e..5ef543083 100644
--- a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ecdh_alt_process.c
+++ b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ecdh_alt_process.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ecdsa_alt_process.c b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ecdsa_alt_process.c
index cd7d4ecd5..8cc0c724f 100644
--- a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ecdsa_alt_process.c
+++ b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ecdsa_alt_process.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_gcm_alt_process.c b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_gcm_alt_process.c
index 7d861036c..6a3041f3d 100644
--- a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_gcm_alt_process.c
+++ b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_gcm_alt_process.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_rsa_alt_process.c b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_rsa_alt_process.c
index 65851789a..ce13744f2 100644
--- a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_rsa_alt_process.c
+++ b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_rsa_alt_process.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_sha2_alt_process.c b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_sha2_alt_process.c
index d467a9766..579c2b6cf 100644
--- a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_sha2_alt_process.c
+++ b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_sha2_alt_process.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_netx_secure_crypto/rm_netx_secure_crypto.c b/ra/fsp/src/rm_netx_secure_crypto/rm_netx_secure_crypto.c
index c500c8303..71efb045a 100644
--- a/ra/fsp/src/rm_netx_secure_crypto/rm_netx_secure_crypto.c
+++ b/ra/fsp/src/rm_netx_secure_crypto/rm_netx_secure_crypto.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_netxduo_ether/rm_netxduo_ether.c b/ra/fsp/src/rm_netxduo_ether/rm_netxduo_ether.c
index f7fbe9892..83975af94 100644
--- a/ra/fsp/src/rm_netxduo_ether/rm_netxduo_ether.c
+++ b/ra/fsp/src/rm_netxduo_ether/rm_netxduo_ether.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_netxduo_ether/rm_netxduo_ether.h b/ra/fsp/src/rm_netxduo_ether/rm_netxduo_ether.h
index 14dbde14a..d35d3bcf1 100644
--- a/ra/fsp/src/rm_netxduo_ether/rm_netxduo_ether.h
+++ b/ra/fsp/src/rm_netxduo_ether/rm_netxduo_ether.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_netxduo_wifi/rm_netxduo_wifi.h b/ra/fsp/src/rm_netxduo_wifi/rm_netxduo_wifi.h
index b6d511cb3..3819dc20e 100644
--- a/ra/fsp/src/rm_netxduo_wifi/rm_netxduo_wifi.h
+++ b/ra/fsp/src/rm_netxduo_wifi/rm_netxduo_wifi.h
@@ -20,7 +20,7 @@
 /**************************************************************************/
 /**************************************************************************/
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_ob1203/light_mode/rm_ob1203_light_mode.c b/ra/fsp/src/rm_ob1203/light_mode/rm_ob1203_light_mode.c
index e849a0996..20d729ed0 100644
--- a/ra/fsp/src/rm_ob1203/light_mode/rm_ob1203_light_mode.c
+++ b/ra/fsp/src/rm_ob1203/light_mode/rm_ob1203_light_mode.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_ob1203/light_proximity_mode/rm_ob1203_light_proximity_mode.c b/ra/fsp/src/rm_ob1203/light_proximity_mode/rm_ob1203_light_proximity_mode.c
index dd59f0b55..73adcbcd2 100644
--- a/ra/fsp/src/rm_ob1203/light_proximity_mode/rm_ob1203_light_proximity_mode.c
+++ b/ra/fsp/src/rm_ob1203/light_proximity_mode/rm_ob1203_light_proximity_mode.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_ob1203/ppg_mode/rm_ob1203_ppg_mode.c b/ra/fsp/src/rm_ob1203/ppg_mode/rm_ob1203_ppg_mode.c
index e56a390ca..9d0656223 100644
--- a/ra/fsp/src/rm_ob1203/ppg_mode/rm_ob1203_ppg_mode.c
+++ b/ra/fsp/src/rm_ob1203/ppg_mode/rm_ob1203_ppg_mode.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_ob1203/proximity_mode/rm_ob1203_proximity_mode.c b/ra/fsp/src/rm_ob1203/proximity_mode/rm_ob1203_proximity_mode.c
index 123bc3317..79a4e958a 100644
--- a/ra/fsp/src/rm_ob1203/proximity_mode/rm_ob1203_proximity_mode.c
+++ b/ra/fsp/src/rm_ob1203/proximity_mode/rm_ob1203_proximity_mode.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_ob1203/rm_ob1203.c b/ra/fsp/src/rm_ob1203/rm_ob1203.c
index 49f121581..98c9a59c7 100644
--- a/ra/fsp/src/rm_ob1203/rm_ob1203.c
+++ b/ra/fsp/src/rm_ob1203/rm_ob1203.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_ob1203/rm_ob1203_ra_driver.c b/ra/fsp/src/rm_ob1203/rm_ob1203_ra_driver.c
index 11d1117a2..ed6981e17 100644
--- a/ra/fsp/src/rm_ob1203/rm_ob1203_ra_driver.c
+++ b/ra/fsp/src/rm_ob1203/rm_ob1203_ra_driver.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_psa_crypto/aes_alt.c b/ra/fsp/src/rm_psa_crypto/aes_alt.c
index c42cdea4b..42ccc7b63 100644
--- a/ra/fsp/src/rm_psa_crypto/aes_alt.c
+++ b/ra/fsp/src/rm_psa_crypto/aes_alt.c
@@ -1131,7 +1131,7 @@ int mbedtls_aes_crypt_xts( mbedtls_aes_xts_context *ctx,
     if( length > ( 1 << 20 ) * 16 )
         return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH;
 
-#if BSP_FEATURE_CRYPTO_HAS_SCE9
+#if !(BSP_FEATURE_BSP_HAS_SCE_ON_RA2)
     if( mode == MBEDTLS_AES_ENCRYPT )
         return( mbedtls_internal_aes_encrypt_xts( &ctx->tweak, length, data_unit, input, output ) );
     else
diff --git a/ra/fsp/src/rm_psa_crypto/aes_alt_process.c b/ra/fsp/src/rm_psa_crypto/aes_alt_process.c
index db35a8fb3..2e9a9bb41 100644
--- a/ra/fsp/src/rm_psa_crypto/aes_alt_process.c
+++ b/ra/fsp/src/rm_psa_crypto/aes_alt_process.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -64,7 +64,7 @@
   #endif
 
   #if defined(MBEDTLS_CIPHER_MODE_XTS)
-   #if BSP_FEATURE_CRYPTO_HAS_SCE9
+   #if !(BSP_FEATURE_BSP_HAS_SCE_ON_RA2)
 int aes_xts_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, unsigned int keybits)
 {
     FSP_ASSERT(ctx);
@@ -302,7 +302,7 @@ int mbedtls_aes_setkey_dec (mbedtls_aes_context * ctx, const unsigned char * key
 
   #if defined(MBEDTLS_CIPHER_MODE_XTS)
 
-   #if !(BSP_FEATURE_CRYPTO_HAS_SCE9)
+   #if BSP_FEATURE_BSP_HAS_SCE_ON_RA2
 static int mbedtls_aes_xts_decode_keys (const unsigned char  * key,
                                         unsigned int           keybits,
                                         const unsigned char ** key1,
@@ -345,7 +345,7 @@ int mbedtls_aes_xts_setkey_enc (mbedtls_aes_xts_context * ctx, const unsigned ch
     (void) key;
     (void) keybits;
 
-   #if BSP_FEATURE_CRYPTO_HAS_SCE9
+   #if !(BSP_FEATURE_BSP_HAS_SCE_ON_RA2)
     ret = aes_xts_setkey_generic(&ctx->tweak, key, keybits);
     if (ret != 0)
     {
@@ -353,7 +353,7 @@ int mbedtls_aes_xts_setkey_enc (mbedtls_aes_xts_context * ctx, const unsigned ch
     }
    #endif
 
-   #if !(BSP_FEATURE_CRYPTO_HAS_SCE9)
+   #if BSP_FEATURE_BSP_HAS_SCE_ON_RA2
     const unsigned char * key1;
     const unsigned char * key2;
     unsigned int          key1bits;
@@ -386,7 +386,7 @@ int mbedtls_aes_xts_setkey_dec (mbedtls_aes_xts_context * ctx, const unsigned ch
     (void) key;
     (void) keybits;
 
-   #if BSP_FEATURE_CRYPTO_HAS_SCE9
+   #if !(BSP_FEATURE_BSP_HAS_SCE_ON_RA2)
     ret = aes_xts_setkey_generic(&ctx->tweak, key, keybits);
     if (ret != 0)
     {
@@ -394,7 +394,7 @@ int mbedtls_aes_xts_setkey_dec (mbedtls_aes_xts_context * ctx, const unsigned ch
     }
    #endif
 
-   #if !(BSP_FEATURE_CRYPTO_HAS_SCE9)
+   #if BSP_FEATURE_BSP_HAS_SCE_ON_RA2
     const unsigned char * key1;
     const unsigned char * key2;
     unsigned int          key1bits;
@@ -560,7 +560,7 @@ int mbedtls_internal_aes_encrypt_cbc (mbedtls_aes_context * ctx,
     return ret;
 }
 
-   #if BSP_FEATURE_CRYPTO_HAS_SCE9
+   #if !(BSP_FEATURE_BSP_HAS_SCE_ON_RA2)
 int mbedtls_internal_aes_encrypt_xts (mbedtls_aes_context * ctx,
                                       unsigned int          length,
                                       const unsigned char * iv,
@@ -810,7 +810,7 @@ int mbedtls_internal_aes_decrypt_cbc (mbedtls_aes_context * ctx,
     return ret;
 }
 
-   #if BSP_FEATURE_CRYPTO_HAS_SCE9
+   #if !(BSP_FEATURE_BSP_HAS_SCE_ON_RA2)
 int mbedtls_internal_aes_decrypt_xts (mbedtls_aes_context * ctx,
                                       unsigned int          length,
                                       const unsigned char * iv,
diff --git a/ra/fsp/src/rm_psa_crypto/aes_vendor.c b/ra/fsp/src/rm_psa_crypto/aes_vendor.c
index d73490fd6..024e89d0a 100644
--- a/ra/fsp/src/rm_psa_crypto/aes_vendor.c
+++ b/ra/fsp/src/rm_psa_crypto/aes_vendor.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_psa_crypto/asymmetric_vendor.c b/ra/fsp/src/rm_psa_crypto/asymmetric_vendor.c
index 4e3bf5856..855ffba04 100644
--- a/ra/fsp/src/rm_psa_crypto/asymmetric_vendor.c
+++ b/ra/fsp/src/rm_psa_crypto/asymmetric_vendor.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_psa_crypto/ecdsa_alt.c b/ra/fsp/src/rm_psa_crypto/ecdsa_alt.c
index bfc4a4d52..7b8b2cbe9 100644
--- a/ra/fsp/src/rm_psa_crypto/ecdsa_alt.c
+++ b/ra/fsp/src/rm_psa_crypto/ecdsa_alt.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_psa_crypto/ecdsa_alt_process.c b/ra/fsp/src/rm_psa_crypto/ecdsa_alt_process.c
index baf9d69af..6a11b4a06 100644
--- a/ra/fsp/src/rm_psa_crypto/ecdsa_alt_process.c
+++ b/ra/fsp/src/rm_psa_crypto/ecdsa_alt_process.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_psa_crypto/ecp_alt_process.c b/ra/fsp/src/rm_psa_crypto/ecp_alt_process.c
index 2cf039237..9ab88d1f2 100644
--- a/ra/fsp/src/rm_psa_crypto/ecp_alt_process.c
+++ b/ra/fsp/src/rm_psa_crypto/ecp_alt_process.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_psa_crypto/gcm_alt_process.c b/ra/fsp/src/rm_psa_crypto/gcm_alt_process.c
index b5758ddbf..4027a76f4 100644
--- a/ra/fsp/src/rm_psa_crypto/gcm_alt_process.c
+++ b/ra/fsp/src/rm_psa_crypto/gcm_alt_process.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_psa_crypto/inc/platform_alt.h b/ra/fsp/src/rm_psa_crypto/inc/platform_alt.h
index 528a4c0ce..cbc21e7f3 100644
--- a/ra/fsp/src/rm_psa_crypto/inc/platform_alt.h
+++ b/ra/fsp/src/rm_psa_crypto/inc/platform_alt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_psa_crypto/inc/rm_psa_crypto.h b/ra/fsp/src/rm_psa_crypto/inc/rm_psa_crypto.h
index 174691288..c35595fa7 100644
--- a/ra/fsp/src/rm_psa_crypto/inc/rm_psa_crypto.h
+++ b/ra/fsp/src/rm_psa_crypto/inc/rm_psa_crypto.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_psa_crypto/inc/sha256_alt.h b/ra/fsp/src/rm_psa_crypto/inc/sha256_alt.h
index eb3789cf1..71939a147 100644
--- a/ra/fsp/src/rm_psa_crypto/inc/sha256_alt.h
+++ b/ra/fsp/src/rm_psa_crypto/inc/sha256_alt.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_psa_crypto/platform_alt.c b/ra/fsp/src/rm_psa_crypto/platform_alt.c
index 026ec6d98..973d3355b 100644
--- a/ra/fsp/src/rm_psa_crypto/platform_alt.c
+++ b/ra/fsp/src/rm_psa_crypto/platform_alt.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_psa_crypto/rm_psa_crypto.c b/ra/fsp/src/rm_psa_crypto/rm_psa_crypto.c
index df52e925e..6157a8ea9 100644
--- a/ra/fsp/src/rm_psa_crypto/rm_psa_crypto.c
+++ b/ra/fsp/src/rm_psa_crypto/rm_psa_crypto.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c b/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c
index 5abb0bfd8..a6d2ccf68 100644
--- a/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c
+++ b/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_psa_crypto/sha256_alt_process.c b/ra/fsp/src/rm_psa_crypto/sha256_alt_process.c
index c56fb0200..165b1c47b 100644
--- a/ra/fsp/src/rm_psa_crypto/sha256_alt_process.c
+++ b/ra/fsp/src/rm_psa_crypto/sha256_alt_process.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_psa_crypto/trng_entropy.c b/ra/fsp/src/rm_psa_crypto/trng_entropy.c
index bef92e35e..c61c8cca9 100644
--- a/ra/fsp/src/rm_psa_crypto/trng_entropy.c
+++ b/ra/fsp/src/rm_psa_crypto/trng_entropy.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_psa_crypto/vendor.c b/ra/fsp/src/rm_psa_crypto/vendor.c
index 408da7a64..f4375093e 100644
--- a/ra/fsp/src/rm_psa_crypto/vendor.c
+++ b/ra/fsp/src/rm_psa_crypto/vendor.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_tfm_port/ra/inc/rm_tfm_port.h b/ra/fsp/src/rm_tfm_port/ra/inc/rm_tfm_port.h
index 2fe64c11f..89ee19d42 100644
--- a/ra/fsp/src/rm_tfm_port/ra/inc/rm_tfm_port.h
+++ b/ra/fsp/src/rm_tfm_port/ra/inc/rm_tfm_port.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_tfm_port/tfm_common_config.h b/ra/fsp/src/rm_tfm_port/tfm_common_config.h
index 85824f2fc..7c328f754 100644
--- a/ra/fsp/src/rm_tfm_port/tfm_common_config.h
+++ b/ra/fsp/src/rm_tfm_port/tfm_common_config.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_threadx_port/tx_cmsis.h b/ra/fsp/src/rm_threadx_port/tx_cmsis.h
index ee8604a60..1f03150ae 100644
--- a/ra/fsp/src/rm_threadx_port/tx_cmsis.h
+++ b/ra/fsp/src/rm_threadx_port/tx_cmsis.h
@@ -34,6 +34,8 @@
 #include "../../src/bsp/mcu/all/bsp_arm_exceptions.h"
 #include "cmsis_compiler.h"
 
+#include "bsp_api.h"                   /* This include brings in a workaround for defining __ARM_ARCH_8_1M_MAIN__. It should be removed when this behaviour is fixed. */
+
 #if   __ARM_ARCH_7EM__
  #define __MPU_PRESENT             1   /*!< MPU present or not                                                    */
  #define __NVIC_PRIO_BITS          4   /*!< Number of Bits used for Priority Levels                               */
diff --git a/ra/fsp/src/rm_threadx_port/tx_port_vendor.h b/ra/fsp/src/rm_threadx_port/tx_port_vendor.h
index 1cd6ff2d3..3186d1a86 100644
--- a/ra/fsp/src/rm_threadx_port/tx_port_vendor.h
+++ b/ra/fsp/src/rm_threadx_port/tx_port_vendor.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_threadx_port/tx_port_wait_thread_ready.c b/ra/fsp/src/rm_threadx_port/tx_port_wait_thread_ready.c
index 7e2c87847..9341d1c33 100644
--- a/ra/fsp/src/rm_threadx_port/tx_port_wait_thread_ready.c
+++ b/ra/fsp/src/rm_threadx_port/tx_port_wait_thread_ready.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_tinycrypt_port/inc/rm_tinycrypt_port.h b/ra/fsp/src/rm_tinycrypt_port/inc/rm_tinycrypt_port.h
index 3a99296ba..80438fd16 100644
--- a/ra/fsp/src/rm_tinycrypt_port/inc/rm_tinycrypt_port.h
+++ b/ra/fsp/src/rm_tinycrypt_port/inc/rm_tinycrypt_port.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_tinycrypt_port/rm_mcuboot_tinycrypt_port_ctr_mode.c b/ra/fsp/src/rm_tinycrypt_port/rm_mcuboot_tinycrypt_port_ctr_mode.c
index da537120d..0cae663de 100644
--- a/ra/fsp/src/rm_tinycrypt_port/rm_mcuboot_tinycrypt_port_ctr_mode.c
+++ b/ra/fsp/src/rm_tinycrypt_port/rm_mcuboot_tinycrypt_port_ctr_mode.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_tinycrypt_port/rm_tinycrypt_port.c b/ra/fsp/src/rm_tinycrypt_port/rm_tinycrypt_port.c
index 7f9977922..31f1a88b3 100644
--- a/ra/fsp/src/rm_tinycrypt_port/rm_tinycrypt_port.c
+++ b/ra/fsp/src/rm_tinycrypt_port/rm_tinycrypt_port.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_tinycrypt_port/rm_tinycrypt_port_aes_decrypt.c b/ra/fsp/src/rm_tinycrypt_port/rm_tinycrypt_port_aes_decrypt.c
index 54005d2f4..02cd396ab 100644
--- a/ra/fsp/src/rm_tinycrypt_port/rm_tinycrypt_port_aes_decrypt.c
+++ b/ra/fsp/src/rm_tinycrypt_port/rm_tinycrypt_port_aes_decrypt.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_tinycrypt_port/rm_tinycrypt_port_aes_encrypt.c b/ra/fsp/src/rm_tinycrypt_port/rm_tinycrypt_port_aes_encrypt.c
index f40a04e16..96ad99136 100644
--- a/ra/fsp/src/rm_tinycrypt_port/rm_tinycrypt_port_aes_encrypt.c
+++ b/ra/fsp/src/rm_tinycrypt_port/rm_tinycrypt_port_aes_encrypt.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_tinycrypt_port/rm_tinycrypt_port_cbc_mode.c b/ra/fsp/src/rm_tinycrypt_port/rm_tinycrypt_port_cbc_mode.c
index 5d24456e0..ece8b75cd 100644
--- a/ra/fsp/src/rm_tinycrypt_port/rm_tinycrypt_port_cbc_mode.c
+++ b/ra/fsp/src/rm_tinycrypt_port/rm_tinycrypt_port_cbc_mode.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_tinycrypt_port/rm_tinycrypt_port_ctr_mode.c b/ra/fsp/src/rm_tinycrypt_port/rm_tinycrypt_port_ctr_mode.c
index 1ef4acbb8..e25df152a 100644
--- a/ra/fsp/src/rm_tinycrypt_port/rm_tinycrypt_port_ctr_mode.c
+++ b/ra/fsp/src/rm_tinycrypt_port/rm_tinycrypt_port_ctr_mode.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_touch/rm_touch.c b/ra/fsp/src/rm_touch/rm_touch.c
index 0adf93768..c854146d9 100644
--- a/ra/fsp/src/rm_touch/rm_touch.c
+++ b/ra/fsp/src/rm_touch/rm_touch.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -1777,27 +1777,27 @@ void touch_button_on (touch_button_info_t * p_binfo, uint16_t value, uint8_t but
     if (p_binfo->on_freq <= (*(p_binfo->p_on_count + button_id)))
     {
         p_binfo->status |= ((uint64_t) 1 << button_id);
+
+        /* ===== The reset judgment processing at the time of continuation on ===== */
+        if (p_binfo->cancel_freq > p_binfo->on_freq)
+        {
+            /* If reaching max_on_threshold, it makes result off and it revises a drift. */
+            if (p_binfo->cancel_freq <= (*(p_binfo->p_on_count + button_id)))
+            {
+                p_binfo->status &= ~(((uint64_t) 1 << button_id));
+                *(p_binfo->p_on_count + button_id)  = 0;
+                *(p_binfo->p_reference + button_id) = value;
+            }
+            else
+            {
+                (*(p_binfo->p_on_count + button_id))++;
+            }
+        }
     }
     else
     {
         (*(p_binfo->p_on_count + button_id))++;
     }
-
-    /* ===== The reset judgment processing at the time of continuation on ===== */
-    if (p_binfo->cancel_freq > p_binfo->on_freq)
-    {
-        /* If reaching max_on_threshold, it makes result off and it revises a drift. */
-        if (p_binfo->cancel_freq <= (*(p_binfo->p_on_count + button_id)))
-        {
-            p_binfo->status &= ~(((uint64_t) 1 << button_id));
-            *(p_binfo->p_on_count + button_id)  = 0;
-            *(p_binfo->p_reference + button_id) = value;
-        }
-        else
-        {
-            (*(p_binfo->p_on_count + button_id))++;
-        }
-    }
 }                                      /* End of function touch_button_on() */
 
 /***********************************************************************************************************************
diff --git a/ra/fsp/src/rm_tz_context/tz_context.c b/ra/fsp/src/rm_tz_context/tz_context.c
index c50cb5f8e..dc85b27f0 100644
--- a/ra/fsp/src/rm_tz_context/tz_context.c
+++ b/ra/fsp/src/rm_tz_context/tz_context.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_usbx_port/rm_usbx_dfu_descriptor.c.template b/ra/fsp/src/rm_usbx_port/rm_usbx_dfu_descriptor.c.template
new file mode 100644
index 000000000..30661fbe7
--- /dev/null
+++ b/ra/fsp/src/rm_usbx_port/rm_usbx_dfu_descriptor.c.template
@@ -0,0 +1,683 @@
+/* ${REA_DISCLAIMER_PLACEHOLDER} */
+/******************************************************************************
+ Includes   <System Includes> , "Project Includes"
+ ******************************************************************************/
+#include <r_usb_basic.h>
+#include <r_usb_basic_api.h>
+#include "r_usb_basic_cfg.h"
+
+/******************************************************************************
+ Macro definitions
+ ******************************************************************************/
+/* bcdUSB */
+#define USB_BCDNUM                      (0x0200U)
+/* Release Number */
+#define USB_RELEASE                     (0x0200U)
+/* DCP max packet size */
+#define USB_DCPMAXP                     (64U)
+/* Configuration number */
+#define USB_CONFIGNUM                   (1U)
+/* Vendor ID */
+#define USB_VENDORID                    (0x0000U)
+/* Product ID */
+#define USB_PRODUCTID                   (0x0002U)
+
+/* Interface Association Descriptor Type */
+#define USB_IAD_TYPE                    (0x0B)
+
+/* Communications Class Subclass Codes */
+#define USB_PCDC_CLASS_SUBCLASS_CODE_ABS_CTR_MDL                (0x02U)
+
+/* Class-Specific Configuration Descriptors */
+#define     USB_PCDC_CS_INTERFACE                               (0x24U)
+
+/* bDescriptor SubType in Communications Class Functional Descriptors */
+/* Header Functional Descriptor */
+#define     USB_PCDC_DT_SUBTYPE_HEADER_FUNC                     (0x00U)
+/* Call Management Functional Descriptor. */
+#define     USB_PCDC_DT_SUBTYPE_CALL_MANAGE_FUNC                (0x01U)
+/* Abstract Control Management Functional Descriptor. */
+#define     USB_PCDC_DT_SUBTYPE_ABSTRACT_CTR_MANAGE_FUNC        (0x02U)
+/* Union Functional Descriptor */
+#define     USB_PCDC_DT_SUBTYPE_UNION_FUNC                      (0x06U)
+
+/* Communications Class Subclass Codes */
+#define     USB_PCDC_CLASS_SUBCLASS_CODE_ABS_CTR_MDL            (0x02U)
+
+/* USB Class Definitions for Communications Devices Specification
+ release number in binary-coded decimal. */
+#define     USB_PCDC_BCD_CDC          (0x0110U)
+
+/* Descriptor length */
+#define USB_PCDC_QD_LEN               (10U)
+#define USB_PCDC_CD1_LEN              (101U) /* CDC(75) + IAD(8) + DFU(9*2) */
+#define STRING_DESCRIPTOR0_LEN        (4U)
+#define STRING_DESCRIPTOR1_LEN        (16U)
+#define STRING_DESCRIPTOR2_LEN        (44U)
+#define STRING_DESCRIPTOR3_LEN        (46U)
+#define STRING_DESCRIPTOR4_LEN        (22U)
+#define STRING_DESCRIPTOR5_LEN        (18U)
+#define STRING_DESCRIPTOR6_LEN        (28U)
+
+/* Descriptor data Mask */
+#define USB_UCHAR_MAX                 (0xffU)
+#define USB_W_TOTAL_LENGTH_MASK       (256U)
+#define USB_W_MAX_PACKET_SIZE_MASK    (64U)
+
+#define VALUE_103                     (103U)
+#define VALUE_93                      (93U)
+#define VALUE_105                     (105U)
+#define VALUE_2                       (2U)
+
+#define VALUE_20H                     (0x20U)
+#define VALUE_21H                     (0x21U)
+#define VALUE_32H                     (0x32U)
+#define VALUE_40H                     (0x40U)
+#define VALUE_99H                     (0x99U)
+#define VALUE_C0H                     (0xC0U)
+#define VALUE_E8H                     (0xE8U)
+#define VALUE_EFH                     (0xEFU)
+#define VALUE_FEH                     (0xFEU)
+
+/******************************************************************************
+ Private global variables and functions
+ ******************************************************************************/
+
+/******************************************************************************
+ Exported global variables
+ ******************************************************************************/
+
+/******************************************************************************
+ Exported global functions (to be accessed by other files)
+ ******************************************************************************/
+
+#define DEVICE_FRAME_LENGTH_FULL_SPEED  (119)  /* CDC(93) + IAD(8) + DFU(9*2) */
+
+/* Run-Time Descriptor Set =
+      Run-Time Device and Configuration Descriptors  +
+      Run-Time DFU Interface Descriptor              +
+      Run-Time DFU Functional Descriptor                                      */
+uint8_t g_device_framework_full_speed[DEVICE_FRAME_LENGTH_FULL_SPEED] =
+{
+    USB_DD_BLENGTH,                                     /*  0:bLength */
+    USB_DT_DEVICE,                                      /*  1:bDescriptorType */
+    (USB_BCDNUM & (uint8_t) USB_UCHAR_MAX),                     /*  2:bcdUSB_lo */
+    ((uint8_t) (USB_BCDNUM >> 8) & (uint8_t) USB_UCHAR_MAX),    /*  3:bcdUSB_hi */
+    VALUE_EFH,                                               /*  4:bDeviceClass */
+    0x02,                                               /*  5:bDeviceSubClass */
+    0x01,                                               /*  6:bDeviceProtocol */
+    (uint8_t) USB_DCPMAXP,                              /*  7:bMAXPacketSize(for DCP) */
+    (USB_VENDORID & (uint8_t) USB_UCHAR_MAX),                   /*  8:idVendor_lo */
+    ((uint8_t) (USB_VENDORID >> 8) & (uint8_t) USB_UCHAR_MAX),  /*  9:idVendor_hi */
+    ((uint16_t) USB_PRODUCTID & (uint8_t) USB_UCHAR_MAX),       /* 10:idProduct_lo */
+    ((uint8_t) (USB_PRODUCTID >> 8) & (uint8_t) USB_UCHAR_MAX), /* 11:idProduct_hi */
+    (USB_RELEASE & (uint8_t) USB_UCHAR_MAX),                    /* 12:bcdDevice_lo */
+    ((uint8_t) (USB_RELEASE >> 8) & (uint8_t) USB_UCHAR_MAX),   /* 13:bcdDevice_hi */
+    1,                                                  /* 14:iManufacturer */
+    2,                                                  /* 15:iProduct */
+    6,                                                  /* 16:iSerialNumber */
+    USB_CONFIGNUM,                                      /* 17:bNumConfigurations */
+
+    USB_CD_BLENGTH,                 /*  0:bLength */
+    USB_SOFT_CHANGE,        /*  1:bDescriptorType */ /* For High-speed */
+    USB_PCDC_CD1_LEN % USB_W_TOTAL_LENGTH_MASK, /*  2:wTotalLength(L) */
+    USB_PCDC_CD1_LEN / USB_W_TOTAL_LENGTH_MASK, /*  3:wTotalLength(H) */
+    3,                              /*  4:bNumInterfaces */
+    1,                              /*  5:bConfigurationValue */
+    0,                              /*  6:iConfiguration */
+    USB_CF_RESERVED | USB_CF_SELFP, /*  7:bmAttributes */
+    (10 / 2),                       /*  8:MAXPower (2mA unit) */
+
+    /* Interface Association Descriptor (IAD) */
+    0x08,                           /*  0:bLength */
+    USB_IAD_TYPE,                   /*  1:bDescriptorType */
+    0x00,                           /*  2:bFirstInterface */
+    0x02,                           /*  3:bInterfaceCount */
+    USB_IFCLS_CDCC,                 /*  4:bFunctionClass  */
+    USB_PCDC_CLASS_SUBCLASS_CODE_ABS_CTR_MDL, /* 5:bFunctionSubClass */
+    0x00,                           /*  6:bFunctionProtocol */
+    0x00,                           /*  7:iFunction */
+
+    /* Interface Descriptor */
+    USB_ID_BLENGTH,                 /*  0:bLength */
+    USB_DT_INTERFACE,               /*  1:bDescriptor */
+    0,                              /*  2:bInterfaceNumber */
+    0,                              /*  3:bAlternateSetting */
+    1,                              /*  4:bNumEndpoints */
+    USB_IFCLS_CDCC,                 /*  5:bInterfaceClass */
+    USB_PCDC_CLASS_SUBCLASS_CODE_ABS_CTR_MDL,   /*  6:bInterfaceSubClass */
+    1,                              /*  7:bInterfaceProtocol */
+    0,                              /*  8:iInterface */
+
+        /* Communications Class Functional Descriptorss */
+        5,                          /*  0:bLength */
+        USB_PCDC_CS_INTERFACE,      /*  1:bDescriptorType */
+        USB_PCDC_DT_SUBTYPE_HEADER_FUNC,    /*  2:bDescriptorSubtype */
+        USB_PCDC_BCD_CDC % USB_W_TOTAL_LENGTH_MASK,     /*  3:bcdCDC_lo */
+        USB_PCDC_BCD_CDC / USB_W_TOTAL_LENGTH_MASK,     /*  4:bcdCDC_hi */
+
+        /* Communications Class Functional Descriptorss */
+        4,                          /*  0:bLength */
+        USB_PCDC_CS_INTERFACE,      /*  1:bDescriptorType */
+        USB_PCDC_DT_SUBTYPE_ABSTRACT_CTR_MANAGE_FUNC,   /*  2:bDescriptorSubtype */
+        2,                          /*  3:bmCapabilities */
+
+        /* Communications Class Functional Descriptorss */
+        5,                          /*  0:bLength */
+        USB_PCDC_CS_INTERFACE,      /*  1:bDescriptorType */
+        USB_PCDC_DT_SUBTYPE_UNION_FUNC, /*  2:bDescriptorSubtype */
+        0,                          /*  3:bMasterInterface */
+        1,                          /*  4:bSlaveInterface0 */
+
+        /* Communications Class Functional Descriptorss */
+        5,                          /*  0:bLength */
+        USB_PCDC_CS_INTERFACE,      /*  1:bDescriptorType */
+        USB_PCDC_DT_SUBTYPE_CALL_MANAGE_FUNC,   /*  2:bDescriptorSubtype */
+        /* D1:1-Device can send/receive call management
+         information over a Data Class interface. */
+        /* D0:1-Device handles call management itself. */
+        3,                          /*  3:bmCapabilities */
+        1,                          /*  4:bDataInterface */
+
+        /* Endpoint Descriptor 0 */
+        7,                          /*  0:bLength */
+        USB_DT_ENDPOINT,            /*  1:bDescriptorType */
+        USB_EP_IN | USB_EP3,        /*  2:bEndpointAddress */
+        USB_EP_INT,                 /*  3:bmAttribute */
+        16,                         /*  4:wMAXPacketSize_lo */
+        0,                          /*  5:wMAXPacketSize_hi */
+        0x10,                       /*  6:bInterval */
+
+    /* Interface Descriptor */
+    USB_ID_BLENGTH,                 /*  0:bLength */
+    USB_DT_INTERFACE,               /*  1:bDescriptor */
+    1,                              /*  2:bInterfaceNumber */
+    0,                              /*  3:bAlternateSetting */
+    2,                              /*  4:bNumEndpoints */
+    USB_IFCLS_CDCD,                 /*  5:bInterfaceClass */
+    0,                              /*  6:bInterfaceSubClass */
+    0,                              /*  7:bInterfaceProtocol */
+    0,                              /*  8:iInterface */
+
+        /* Endpoint Descriptor 0 */
+        USB_ED_BLENGTH,             /*  0:bLength */
+        USB_DT_ENDPOINT,            /*  1:bDescriptorType */
+        USB_EP_IN | USB_EP1,        /*  2:bEndpointAddress */
+        USB_EP_BULK,                /*  3:bmAttribute */
+		USB_W_MAX_PACKET_SIZE_MASK, /*  4:wMAXPacketSize_lo */
+        0,                          /*  5:wMAXPacketSize_hi */
+        0,                          /*  6:bInterval */
+
+        /* Endpoint Descriptor 1 */
+        USB_ED_BLENGTH,             /*  0:bLength */
+        USB_DT_ENDPOINT,            /*  1:bDescriptorType */
+        USB_EP_OUT | USB_EP2,       /*  2:bEndpointAddress */
+        USB_EP_BULK,                /*  3:bmAttribute */
+		USB_W_MAX_PACKET_SIZE_MASK, /*  4:wMAXPacketSize_lo */
+        0,                          /*  5:wMAXPacketSize_hi */
+        0,                          /*  6:bInterval */
+
+    /* Interface Association Descriptor (IAD) */
+    0x08,                           /*  0:bLength */
+    USB_IAD_TYPE,                   /*  1:bDescriptorType */
+    0x02,                           /*  2:bFirstInterface */
+    0x01,                           /*  3:bInterfaceCount */
+    VALUE_FEH,                      /*  4:bFunctionClass  */
+    0x01,                           /* 5:bFunctionSubClass */
+    0x01,                           /*  6:bFunctionProtocol */
+    0x00,                           /*  7:iFunction */
+
+    /* Run-Time DFU Interface Descriptor */
+    USB_ID_BLENGTH,                 /*  0:bLength */
+    USB_DT_INTERFACE,               /*  1:bDescriptor */
+    2,                              /*  2:bInterfaceNumber */
+    0,                              /*  3:bAlternateSetting */
+    0,                              /*  4:bNumEndpoints */
+    VALUE_FEH,                      /*  5:bInterfaceClass */
+    0x01,                           /*  6:bInterfaceSubClass */
+    0x01,                           /*  7:bInterfaceProtocol */
+    0,                              /*  8:iInterface */
+
+    /* Run-Time DFU Functional Descriptor */
+    USB_ID_BLENGTH,                 /*  0:bLength */
+    VALUE_21H,                      /*  1:bDescriptorType */
+    0x0F,                           /*  2:bmAttributes */
+    VALUE_E8H,                      /*  3:wDetachTimeOut */
+    0x03,
+    VALUE_40H,                      /*  5:wTransferSize */
+    0x00,
+    0x00,                           /*  7:bcdDFUVersion */
+    0x01,
+};
+
+/* Run-Time Descriptor Set =
+      Run-Time Device and Configuration Descriptors  +
+      Run-Time DFU Interface Descriptor              +
+      Run-Time DFU Functional Descriptor                                      */
+#define DEVICE_FRAME_LENGTH_HI_SPEED    (129)   /* CDC(103) + IAD(8) + DFU(9*2) */
+uint8_t g_device_framework_hi_speed[DEVICE_FRAME_LENGTH_HI_SPEED] =
+{
+    USB_DD_BLENGTH,                                     /*  0:bLength */
+    USB_DT_DEVICE,                                      /*  1:bDescriptorType */
+    (USB_BCDNUM & (uint8_t) USB_UCHAR_MAX),                     /*  2:bcdUSB_lo */
+    ((uint8_t) (USB_BCDNUM >> 8) & (uint8_t) USB_UCHAR_MAX),    /*  3:bcdUSB_hi */
+    VALUE_EFH,                                               /*  4:bDeviceClass */
+    0x02,                                               /*  5:bDeviceSubClass */
+    0x01,                                               /*  6:bDeviceProtocol */
+    (uint8_t) USB_DCPMAXP,                              /*  7:bMAXPacketSize(for DCP) */
+    (USB_VENDORID & (uint8_t) USB_UCHAR_MAX),                   /*  8:idVendor_lo */
+    ((uint8_t) (USB_VENDORID >> 8) & (uint8_t) USB_UCHAR_MAX),  /*  9:idVendor_hi */
+    ((uint16_t) USB_PRODUCTID & (uint8_t) USB_UCHAR_MAX),       /* 10:idProduct_lo */
+    ((uint8_t) (USB_PRODUCTID >> 8) & (uint8_t) USB_UCHAR_MAX), /* 11:idProduct_hi */
+    (USB_RELEASE & (uint8_t) USB_UCHAR_MAX),                    /* 12:bcdDevice_lo */
+    ((uint8_t) (USB_RELEASE >> 8) & (uint8_t) USB_UCHAR_MAX),   /* 13:bcdDevice_hi */
+    1,                                                  /* 14:iManufacturer */
+    2,                                                  /* 15:iProduct */
+    6,                                                  /* 16:iSerialNumber */
+    USB_CONFIGNUM,                                      /* 17:bNumConfigurations */
+
+    USB_PCDC_QD_LEN,                                    /*  0:bLength */
+    USB_DT_DEVICE_QUALIFIER,                            /*  1:bDescriptorType */
+    (USB_BCDNUM & (uint8_t) USB_UCHAR_MAX),                     /*  2:bcdUSB_lo */
+    ((uint8_t) (USB_BCDNUM >> 8) & (uint8_t) USB_UCHAR_MAX),    /*  3:bcdUSB_hi */
+    0,                                                  /*  4:bDeviceClass */
+    0,                                                  /*  5:bDeviceSubClass */
+    0,                                                  /*  6:bDeviceProtocol */
+    (uint8_t) USB_DCPMAXP,                              /*  7:bMAXPacketSize(for DCP) */
+    USB_CONFIGNUM,                                      /*  8:bNumConfigurations */
+    0,                                                  /*  9:bReserved */
+
+    USB_CD_BLENGTH,                 /*  0:bLength */
+    USB_SOFT_CHANGE,           /*  1:bDescriptorType */ /* For High-speed */
+    USB_PCDC_CD1_LEN % USB_W_TOTAL_LENGTH_MASK, /*  2:wTotalLength(L) */
+    USB_PCDC_CD1_LEN / USB_W_TOTAL_LENGTH_MASK, /*  3:wTotalLength(H) */
+    3,                              /*  4:bNumInterfaces */
+    1,                              /*  5:bConfigurationValue */
+    0,                              /*  6:iConfiguration */
+    USB_CF_RESERVED | USB_CF_SELFP, /*  7:bmAttributes */
+    (10 / 2),                       /*  8:MAXPower (2mA unit) */
+
+    /* Interface Association Descriptor (IAD) */
+    0x08,                           /*  0:bLength */
+    USB_IAD_TYPE,                   /*  1:bDescriptorType */
+    0x00,                           /*  2:bFirstInterface */
+    0x02,                           /*  3:bInterfaceCount */
+    USB_IFCLS_CDCC,                 /*  4:bFunctionClass  */
+    USB_PCDC_CLASS_SUBCLASS_CODE_ABS_CTR_MDL, /* 5:bFunctionSubClass */
+    0x00,                           /*  6:bFunctionProtocol */
+    0x00,                           /*  7:iFunction */
+
+    /* Interface Descriptor */
+    9,                              /*  0:bLength */
+    USB_DT_INTERFACE,               /*  1:bDescriptor */
+    0,                              /*  2:bInterfaceNumber */
+    0,                              /*  3:bAlternateSetting */
+    1,                              /*  4:bNumEndpoints */
+    USB_IFCLS_CDCC,                 /*  5:bInterfaceClass */
+    USB_PCDC_CLASS_SUBCLASS_CODE_ABS_CTR_MDL,   /*  6:bInterfaceSubClass */
+    1,                              /*  7:bInterfaceProtocol */
+    0,                              /*  8:iInterface */
+
+        /* Communications Class Functional Descriptorss */
+        5, /*  0:bLength */
+        USB_PCDC_CS_INTERFACE,      /*  1:bDescriptorType */
+        USB_PCDC_DT_SUBTYPE_HEADER_FUNC,    /*  2:bDescriptorSubtype */
+        USB_PCDC_BCD_CDC % USB_W_TOTAL_LENGTH_MASK,     /*  3:bcdCDC_lo */
+        USB_PCDC_BCD_CDC / USB_W_TOTAL_LENGTH_MASK,     /*  4:bcdCDC_hi */
+
+        /* Communications Class Functional Descriptorss */
+        4,                          /*  0:bLength */
+        USB_PCDC_CS_INTERFACE,      /*  1:bDescriptorType */
+        USB_PCDC_DT_SUBTYPE_ABSTRACT_CTR_MANAGE_FUNC,   /*  2:bDescriptorSubtype */
+        2,                          /*  3:bmCapabilities */
+
+        /* Communications Class Functional Descriptorss */
+        5,                          /*  0:bLength */
+        USB_PCDC_CS_INTERFACE,      /*  1:bDescriptorType */
+        USB_PCDC_DT_SUBTYPE_UNION_FUNC, /*  2:bDescriptorSubtype */
+        0,                          /*  3:bMasterInterface */
+        1,                          /*  4:bSlaveInterface0 */
+
+        /* Communications Class Functional Descriptorss */
+        5,                          /*  0:bLength */
+        USB_PCDC_CS_INTERFACE,      /*  1:bDescriptorType */
+        USB_PCDC_DT_SUBTYPE_CALL_MANAGE_FUNC,   /*  2:bDescriptorSubtype */
+        /* D1:1-Device can send/receive call management
+         information over a Data Class interface. */
+        /* D0:1-Device handles call management itself. */
+        3,                          /*  3:bmCapabilities */
+        1,                          /*  4:bDataInterface */
+
+        /* Endpoint Descriptor 0 */
+        7,                          /*  0:bLength */
+        USB_DT_ENDPOINT,            /*  1:bDescriptorType */
+        USB_EP_IN | USB_EP3,        /*  2:bEndpointAddress */
+        USB_EP_INT,                 /*  3:bmAttribute */
+        16,                         /*  4:wMAXPacketSize_lo */
+        0,                          /*  5:wMAXPacketSize_hi */
+        0x10,                       /*  6:bInterval */
+
+    /* Interface Descriptor */
+    9,                              /*  0:bLength */
+    USB_DT_INTERFACE,               /*  1:bDescriptor */
+    1,                              /*  2:bInterfaceNumber */
+    0,                              /*  3:bAlternateSetting */
+    2,                              /*  4:bNumEndpoints */
+    USB_IFCLS_CDCD,                 /*  5:bInterfaceClass */
+    0,                              /*  6:bInterfaceSubClass */
+    0,                              /*  7:bInterfaceProtocol */
+    0,                              /*  8:iInterface */
+
+        /* Endpoint Descriptor 0 */
+        7,                          /*  0:bLength */
+        USB_DT_ENDPOINT,            /*  1:bDescriptorType */
+        USB_EP_IN | USB_EP1,        /*  2:bEndpointAddress */
+        USB_EP_BULK,                /*  3:bmAttribute */
+        0,                          /*  4:wMAXPacketSize_lo */
+        2,                          /*  5:wMAXPacketSize_hi */
+        0,                          /*  6:bInterval */
+
+        /* Endpoint Descriptor 1 */
+        7,                          /*  0:bLength */
+        USB_DT_ENDPOINT,            /*  1:bDescriptorType */
+        USB_EP_OUT | USB_EP2,       /*  2:bEndpointAddress */
+        USB_EP_BULK,                /*  3:bmAttribute */
+        0,                          /*  4:wMAXPacketSize_lo */
+        2,                          /*  5:wMAXPacketSize_hi */
+        0,                          /*  6:bInterval */
+
+    /* Interface Association Descriptor (IAD) */
+    0x08,                           /*  0:bLength */
+    USB_IAD_TYPE,                   /*  1:bDescriptorType */
+    0x02,                           /*  2:bFirstInterface */
+    0x01,                           /*  3:bInterfaceCount */
+    VALUE_FEH,                      /*  4:bFunctionClass  */
+    0x01,                           /* 5:bFunctionSubClass */
+    0x01,                           /*  6:bFunctionProtocol */
+    0x00,                           /*  7:iFunction */
+
+    /* Run-Time DFU Interface Descriptor */
+    USB_ID_BLENGTH,                 /*  0:bLength */
+    USB_DT_INTERFACE,               /*  1:bDescriptor */
+    2,                              /*  2:bInterfaceNumber */
+    0,                              /*  3:bAlternateSetting */
+    0,                              /*  4:bNumEndpoints */
+    VALUE_FEH,                      /*  5:bInterfaceClass */
+    0x01,                           /*  6:bInterfaceSubClass */
+    0x01,                           /*  7:bInterfaceProtocol */
+    0,                              /*  8:iInterface */
+
+    /* Run-Time DFU Functional Descriptor */
+    USB_ID_BLENGTH,                 /*  0:bLength */
+    VALUE_21H,                      /*  1:bDescriptorType */
+    0x0F,                           /*  2:bmAttributes */
+    VALUE_E8H,                      /*  3:wDetachTimeOut */
+    0x03,
+    VALUE_40H,                      /*  5:wTransferSize */
+    0x00,
+    0x00,                           /*  7:bcdDFUVersion */
+    0x01,
+};
+
+#define STRING_FRAMEWORK_LENGTH (VALUE_105)
+uint8_t g_string_framework[] =
+{
+    /* iManufacturer */
+    0x09, 0x04, 0x1, 7,
+    'R',
+    'E',
+    'N',
+    'E',
+    'S',
+    'A',
+    'S',
+
+    /* iProduct */
+    0x09, 0x04, 0x2, 21,
+    'C',
+    'D',
+    'C',
+    ' ',
+    'U',
+    'S',
+    'B',
+    ' ',
+    'D',
+    'e',
+    'm',
+    'o',
+    'n',
+    's',
+    't',
+    'r',
+    'a',
+    't',
+    'i',
+    'o',
+    'n',
+
+    /* iInterface */
+    0x09, 0x04, 0x3, 22,
+    'C',
+    'o',
+    'm',
+    'm',
+    'u',
+    'n',
+    'i',
+    'c',
+    'a',
+    't',
+    'i',
+    'o',
+    'n',
+    's',
+    ' ',
+    'D',
+    'e',
+    'v',
+    'i',
+    'c',
+    'e',
+    's',
+
+    /* iConfiguration */
+    0x09, 0x04, 0x4, 10,
+    'F',
+    'u',
+    'l',
+    'l',
+    '-',
+    'S',
+    'p',
+    'e',
+    'e',
+    'd',
+
+    /* iConfiguration */
+    0x09, 0x04, 0x5, 8,
+    'H',
+    'i',
+    '-',
+    'S',
+    'p',
+    'e',
+    'e',
+    'd',
+
+    /* iConfiguration */
+    0x09, 0x04, 0x6, 13,
+    '0',
+    '0',
+    '0',
+    '0',
+    '0',
+    '0',
+    '0',
+    '0',
+    '0',
+    '0',
+    '0',
+    '0',
+    '1',
+};
+
+#define LANGUAGE_ID_FRAME_WORK_LENGTH  (VALUE_2)
+uint8_t g_language_id_framework[] =
+{
+    0x09,
+    0x04,
+};
+
+/* DFU Mode Descriptor Set (Full Speed) */
+UCHAR g_dfu_device_framework_full_speed[] = {
+
+    /* Device descriptor */
+    0x12,                               /*  0:bLength */
+    0x01,                               /*  1:bDescriptorType */
+    0x10,                               /*  2:bcdUSB_lo */
+    0x01,                               /*  3:bcdUSB_hi */
+    0x00,                               /*  4:bDeviceClass */
+    0x00,                               /*  5:bDeviceSubClass */
+    0x00,                               /*  6:bDeviceProtocol */
+    VALUE_40H,                          /*  7:bMAXPacketSize(for DCP) */
+    VALUE_99H,                          /*  8:idVendor_lo */
+    VALUE_99H,                          /*  9:idVendor_hi */
+    0x00,                               /* 10:idProduct_lo */
+    0x00,                               /* 11:idProduct_hi */
+    0x00,                               /* 12:bcdDevice_lo */
+    0x00,                               /* 13:bcdDevice_hi */
+    0x01,                               /* 14:iManufacturer */
+    0x02,                               /* 15:iProduct */
+    0x03,                               /* 16:iSerialNumber */
+    0x01,                               /* 17:bNumConfigurations */
+
+    /* Configuration descriptor */
+    0x09,                               /*  0:bLength */
+    0x02,                               /*  1:bDescriptorType */
+    0x1b,                               /*  2:wTotalLength(L) */
+    0x00,                               /*  3:wTotalLength(H) */
+    0x01,                               /*  4:bNumInterfaces */
+    0x01,                               /*  5:bConfigurationValue */
+    0x00,                               /*  6:iConfiguration */
+    VALUE_C0H,                          /*  7:bmAttributes */
+    VALUE_32H,                          /*  8:MAXPower (2mA unit) */
+
+    /* Interface descriptor for DFU. */
+    0x09,                               /*  0:bLength */
+    0x04,                               /*  1:bDescriptor */
+    0x00,                               /*  2:bInterfaceNumber */
+    0x00,                               /*  3:bAlternateSetting */
+    0x00,                               /*  4:bNumEndpoints */
+    VALUE_FEH,                          /*  5:bInterfaceClass */
+    0x01,                               /*  6:bInterfaceSubClass */
+    0x02,                               /*  7:bInterfaceProtocol */
+    0x00,                               /*  8:iInterface */
+
+    /* Functional descriptor for DFU. */
+    0x09,                               /*  0:bLength */
+    VALUE_21H,                          /*  1:bDescriptorType */
+    0x0D,                               /*  2:bmAttributes */
+    VALUE_E8H,                          /*  3:wDetachTimeOut */
+    0x03,
+    VALUE_40H,                          /*  5:wTransferSize */
+    0x00,
+    0x00,                               /*  7:bcdDFUVersion */
+    0x01,
+};
+
+UCHAR g_dfu_string_framework[] =
+{
+    /* iManufacturer */
+    0x09, 0x04, 0x1, 7,
+    'R',
+    'E',
+    'N',
+    'E',
+    'S',
+    'A',
+    'S',
+
+    /* iProduct */
+    0x09, 0x04, 0x2, 21,
+    'D',
+    'F',
+    'U',
+    ' ',
+    'U',
+    'S',
+    'B',
+    ' ',
+    'D',
+    'e',
+    'm',
+    'o',
+    'n',
+    's',
+    't',
+    'r',
+    'a',
+    't',
+    'i',
+    'o',
+    'n',
+
+    /* iInterface */
+    0x09, 0x04, 0x3, 11,
+    'D',
+    'F',
+    'U',
+    ' ',
+    'D',
+    'e',
+    'v',
+    'i',
+    'c',
+    'e',
+    's',
+
+    /* iConfiguration */
+    0x09, 0x04, 0x4, 10,
+    'F',
+    'u',
+    'l',
+    'l',
+    '-',
+    'S',
+    'p',
+    'e',
+    'e',
+    'd',
+
+    /* iConfiguration */
+    0x09, 0x04, 0x5, 8,
+    'H',
+    'i',
+    '-',
+    'S',
+    'p',
+    'e',
+    'e',
+    'd',
+
+    /* iConfiguration */
+    0x09, 0x04, 0x6, 13,
+    '0',
+    '0',
+    '0',
+    '0',
+    '0',
+    '0',
+    '0',
+    '0',
+    '0',
+    '0',
+    '0',
+    '0',
+    '1',
+};
+
+
+/******************************************************************************
+ End  Of File
+ ******************************************************************************/
diff --git a/ra/fsp/src/rm_usbx_port/rm_usbx_port.c b/ra/fsp/src/rm_usbx_port/rm_usbx_port.c
index a3fce9b56..c10af39f8 100644
--- a/ra/fsp/src/rm_usbx_port/rm_usbx_port.c
+++ b/ra/fsp/src/rm_usbx_port/rm_usbx_port.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -70,6 +70,10 @@
   #include "r_usb_pprn_cfg.h"
  #endif                                /* defined(USB_CFG_PPRN_USE) */
 
+ #if defined(USB_CFG_DFU_USE)
+  #include "ux_device_class_dfu.h"
+ #endif                                /* defined(USB_CFG_DFU_USE) */
+
  #if defined(USB_CFG_HPRN_USE)
   #include "ux_host_class_printer.h"
   #define USB_MAX_CONNECT_DEVICE_NUM    2
@@ -167,8 +171,11 @@ static void usb_peri_usbx_pmsc_storage_uninit(void);
 
  #if defined(USB_CFG_OTG_USE)
 static UINT usb_otg_hnp_swap(ULONG type);
+
+  #if USB_NUM_USBIP == 2
 static UINT usb2_otg_hnp_swap(ULONG type);
 
+  #endif                               /* USB_NUM_USBIP == 2 */
  #endif                                /* defined(USB_CFG_OTG_USE) */
 
  #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST)
@@ -461,7 +468,7 @@ uint32_t usb_peri_usbx_initialize_complete (void)
     return UX_SUCCESS;
 }                                      /* End of function usb_peri_usbx_initialize_complete() */
 
-  #if defined(USB_CFG_PAUD_USE)
+  #if defined(USB_CFG_PAUD_USE) || defined(USB_CFG_DFU_USE)
 
 /******************************************************************************
  * Function Name   : usb_peri_usbx_set_control_length
@@ -474,7 +481,7 @@ void usb_peri_usbx_set_control_length (usb_setup_t * p_req)
     *g_p_usb_actural_length[USB_PIPE0] = p_req->request_length;
 }                                      /* End of function usb_peri_usbx_set_control_length() */
 
-  #endif  /* #if defined(USB_CFG_PAUD_USE) */
+  #endif  /* #if defined(USB_CFG_PAUD_USE) || defined(USB_CFG_DFU_USE)*/
 
 /******************************************************************************
  * Function Name   : usb_peri_usbx_transfer_complete_cb
@@ -578,7 +585,7 @@ static UINT usb_peri_usbx_to_basic (UX_SLAVE_DCD * dcd, UINT function, VOID * pa
             else
             {
                 pipe = USB_PIPE0;
-  #if defined(USB_CFG_PAUD_USE)
+  #if defined(USB_CFG_PAUD_USE) || defined(USB_CFG_DFU_USE)
                 if ((transfer_request->ux_slave_transfer_request_setup[0] & UX_ENDPOINT_DIRECTION) == UX_ENDPOINT_IN)
                 {
                     transfer_request->ux_slave_transfer_request_phase = UX_TRANSFER_PHASE_DATA_OUT;
@@ -587,7 +594,7 @@ static UINT usb_peri_usbx_to_basic (UX_SLAVE_DCD * dcd, UINT function, VOID * pa
                 {
                     transfer_request->ux_slave_transfer_request_phase = UX_TRANSFER_PHASE_DATA_IN;
                 }
-  #endif                                                                         /* #if defined(USB_CFG_PAUD_USE) */
+  #endif                                                                         /* #if defined(USB_CFG_PAUD_USE) || defined(USB_CFG_DFU_USE)*/
             }
 
             size = transfer_request->ux_slave_transfer_request_requested_length; /* Save Read Request Length */
@@ -845,6 +852,37 @@ static UINT usb_peri_usbx_to_basic (UX_SLAVE_DCD * dcd, UINT function, VOID * pa
                 /* This function is called when the device wants to wake up the host.  */
                 usb_peri_usbx_remote_wakeup(module_number);
             }
+
+  #if defined(USB_CFG_DFU_USE)
+            else if (parameter == (void *) UX_DEVICE_FORCE_DISCONNECT)
+            {
+                /* D+ Pullup Off */
+                hw_usb_pclear_dprpu(tran_data.ip);
+
+                if (_ux_system_slave->ux_system_slave_speed == (uint32_t) UX_HIGH_SPEED_DEVICE)
+                {
+                    hw_usb_clear_hse(&tran_data);
+                }
+
+                for (pipe = USB_MIN_PIPE_NO; pipe < (USB_MAXPIPE_NUM + 1); pipe++)
+                {
+                    if (USB_TRUE == g_usb_pipe_table[tran_data.ip][pipe].use_flag)
+                    {
+                        usb_pstd_forced_termination(pipe, (uint16_t) USB_DATA_STOP, &tran_data);
+                    }
+                }
+
+                /* Notify the application to switch (reinitialize) from normal mode to DFU mode in the application. */
+                if (UX_NULL != _ux_system_slave->ux_system_slave_change_function)
+                {
+                    _ux_system_slave->ux_system_slave_change_function(UX_DEVICE_REMOVED);
+                }
+
+                /* "D+ Pullup On" is done by the application. */
+
+                status = (uint32_t) UX_SUCCESS;
+            }
+  #endif                               /* #if defined(USB_CFG_DFU_USE) */
             else
             {
                 if (parameter == (void *) UX_DEVICE_CONFIGURED)
@@ -1297,11 +1335,13 @@ static uint32_t usb_host_usbx_initialize_common (UX_HCD * hcd)
     hcd->ux_hcd_nb_root_hubs = 1U;
 
   #if defined(USB_CFG_OTG_USE)
+   #if USB_NUM_USBIP == 2
     if (R_USB_HS0_BASE == hcd->ux_hcd_io)
     {
         _ux_system_otg->ux_system_otg_function = usb2_otg_hnp_swap;
     }
     else
+   #endif                              /* USB_NUM_USBIP == 2 */
     {
         _ux_system_otg->ux_system_otg_function = usb_otg_hnp_swap;
     }
diff --git a/ra/fsp/src/rm_vee_flash/rm_vee_flash.c b/ra/fsp/src/rm_vee_flash/rm_vee_flash.c
index d6f004fb1..eb7bd4878 100644
--- a/ra/fsp/src/rm_vee_flash/rm_vee_flash.c
+++ b/ra/fsp/src/rm_vee_flash/rm_vee_flash.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_wifi_onchip_da16200/rm_wifi_api_da16200.c b/ra/fsp/src/rm_wifi_onchip_da16200/rm_wifi_api_da16200.c
index 573d051c9..5824199bf 100644
--- a/ra/fsp/src/rm_wifi_onchip_da16200/rm_wifi_api_da16200.c
+++ b/ra/fsp/src/rm_wifi_onchip_da16200/rm_wifi_api_da16200.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_wifi_onchip_da16200/rm_wifi_onchip_da16200.c b/ra/fsp/src/rm_wifi_onchip_da16200/rm_wifi_onchip_da16200.c
index c81036906..f294e2589 100644
--- a/ra/fsp/src/rm_wifi_onchip_da16200/rm_wifi_onchip_da16200.c
+++ b/ra/fsp/src/rm_wifi_onchip_da16200/rm_wifi_onchip_da16200.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
@@ -509,6 +509,17 @@ fsp_err_t rm_wifi_onchip_da16200_open (wifi_onchip_da16200_cfg_t const * const p
     /* Delay after open */
     vTaskDelay(pdMS_TO_TICKS(WIFI_ONCHIP_DA16200_TIMEOUT_100MS));
 
+    /* Test basic communications with an AT command. */
+    err = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl,
+                                            p_instance_ctrl->curr_cmd_port,
+                                            "ATZ\r",
+                                            0,
+                                            WIFI_ONCHIP_DA16200_TIMEOUT_500MS,
+                                            WIFI_ONCHIP_DA16200_DELAY_20MS,
+                                            WIFI_ONCHIP_DA16200_RETURN_TEXT_OK);
+
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_INIT_FAILED);
+
     /* Set AP mode */
     err = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl,
                                             p_instance_ctrl->curr_cmd_port,
@@ -1770,22 +1781,32 @@ int32_t rm_wifi_onchip_da16200_recv (uint32_t socket_no, uint8_t * p_data, uint3
     FSP_ERROR_RETURN(0 != length, FSP_ERR_INVALID_ARGUMENT);
 #endif
 
-    /* if socket read has been disabled by shutdown call then return 0 bytes received. */
+    /* if socket read has been disabled by shutdown call then return any bytes left in the stream buffer. 
+       However if 0 bytes left, return error. */
     if (!(p_instance_ctrl->sockets[socket_no].socket_read_write_flag & WIFI_ONCHIP_DA16200_SOCKET_READ))
     {
-        return 0;
+        size_t xReceivedBytes = xStreamBufferReceiveAlt(p_instance_ctrl->sockets[socket_no].socket_byteq_hdl,
+                                                        p_data,
+                                                        length,
+                                                        0); /* No wait needed as data is already in stream buffer*/
+        if (0 < xReceivedBytes)
+        {
+            return (int32_t)xReceivedBytes;
+        }
+        
+        return -FSP_ERR_WIFI_FAILED;                
     }
 
     /* Take the receive mutex */
     mutex_flag = (WIFI_ONCHIP_DA16200_MUTEX_RX);
     FSP_ERROR_RETURN(pdTRUE == rm_wifi_onchip_da16200_send_basic_take_mutex(p_instance_ctrl, mutex_flag),
-                     FSP_ERR_WIFI_FAILED);
+                     -FSP_ERR_WIFI_FAILED);
 
     if (0 == p_instance_ctrl->sockets[socket_no].socket_create_flag)
     {
         rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag);
 
-        return FSP_ERR_WIFI_FAILED;
+        return -FSP_ERR_WIFI_FAILED;
     }
 
     if (socket_no != p_instance_ctrl->curr_socket_index)
diff --git a/ra/fsp/src/rm_wifi_onchip_silex/rm_wifi_api_silex.c b/ra/fsp/src/rm_wifi_onchip_silex/rm_wifi_api_silex.c
index 79d409c39..e07db911c 100644
--- a/ra/fsp/src/rm_wifi_onchip_silex/rm_wifi_api_silex.c
+++ b/ra/fsp/src/rm_wifi_onchip_silex/rm_wifi_api_silex.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_wifi_onchip_silex/rm_wifi_onchip_silex.c b/ra/fsp/src/rm_wifi_onchip_silex/rm_wifi_onchip_silex.c
index ea93b288f..31d0a2337 100644
--- a/ra/fsp/src/rm_wifi_onchip_silex/rm_wifi_onchip_silex.c
+++ b/ra/fsp/src/rm_wifi_onchip_silex/rm_wifi_onchip_silex.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/iaq_1st_gen/iaq_1st_gen.h b/ra/fsp/src/rm_zmod4xxx/iaq_1st_gen/iaq_1st_gen.h
index 200693922..c45d230e5 100644
--- a/ra/fsp/src/rm_zmod4xxx/iaq_1st_gen/iaq_1st_gen.h
+++ b/ra/fsp/src/rm_zmod4xxx/iaq_1st_gen/iaq_1st_gen.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/iaq_1st_gen/rm_zmod4410_iaq_1st_gen.c b/ra/fsp/src/rm_zmod4xxx/iaq_1st_gen/rm_zmod4410_iaq_1st_gen.c
index 49dec886d..f2b704bcc 100644
--- a/ra/fsp/src/rm_zmod4xxx/iaq_1st_gen/rm_zmod4410_iaq_1st_gen.c
+++ b/ra/fsp/src/rm_zmod4xxx/iaq_1st_gen/rm_zmod4410_iaq_1st_gen.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/iaq_1st_gen/zmod4410_config_iaq1.h b/ra/fsp/src/rm_zmod4xxx/iaq_1st_gen/zmod4410_config_iaq1.h
index 8f6e125ee..8d51e9a01 100644
--- a/ra/fsp/src/rm_zmod4xxx/iaq_1st_gen/zmod4410_config_iaq1.h
+++ b/ra/fsp/src/rm_zmod4xxx/iaq_1st_gen/zmod4410_config_iaq1.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/iaq_2nd_gen.h b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/iaq_2nd_gen.h
index 688d105c7..5e234e337 100644
--- a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/iaq_2nd_gen.h
+++ b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/iaq_2nd_gen.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/rm_zmod4410_iaq_2nd_gen.c b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/rm_zmod4410_iaq_2nd_gen.c
index 1668f6126..ae9d15250 100644
--- a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/rm_zmod4410_iaq_2nd_gen.c
+++ b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/rm_zmod4410_iaq_2nd_gen.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/zmod4410_config_iaq2.h b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/zmod4410_config_iaq2.h
index da991aa3b..6864defd2 100644
--- a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/zmod4410_config_iaq2.h
+++ b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/zmod4410_config_iaq2.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/iaq_2nd_gen_ulp.h b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/iaq_2nd_gen_ulp.h
index 2da48f9c0..4f33079c9 100644
--- a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/iaq_2nd_gen_ulp.h
+++ b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/iaq_2nd_gen_ulp.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/rm_zmod4410_iaq_2nd_gen_ulp.c b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/rm_zmod4410_iaq_2nd_gen_ulp.c
index 8c1e02391..2ca8058e2 100644
--- a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/rm_zmod4410_iaq_2nd_gen_ulp.c
+++ b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/rm_zmod4410_iaq_2nd_gen_ulp.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/zmod4410_config_iaq2_ulp.h b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/zmod4410_config_iaq2_ulp.h
index 308a455a1..c5df13dd2 100644
--- a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/zmod4410_config_iaq2_ulp.h
+++ b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/zmod4410_config_iaq2_ulp.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/oaq_1st_gen/oaq_1st_gen.h b/ra/fsp/src/rm_zmod4xxx/oaq_1st_gen/oaq_1st_gen.h
index 589c8efa4..1dfbf210f 100644
--- a/ra/fsp/src/rm_zmod4xxx/oaq_1st_gen/oaq_1st_gen.h
+++ b/ra/fsp/src/rm_zmod4xxx/oaq_1st_gen/oaq_1st_gen.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/oaq_1st_gen/rm_zmod4510_oaq_1st_gen.c b/ra/fsp/src/rm_zmod4xxx/oaq_1st_gen/rm_zmod4510_oaq_1st_gen.c
index 2aca24911..fa9e70046 100644
--- a/ra/fsp/src/rm_zmod4xxx/oaq_1st_gen/rm_zmod4510_oaq_1st_gen.c
+++ b/ra/fsp/src/rm_zmod4xxx/oaq_1st_gen/rm_zmod4510_oaq_1st_gen.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/oaq_1st_gen/zmod4510_config_oaq1.h b/ra/fsp/src/rm_zmod4xxx/oaq_1st_gen/zmod4510_config_oaq1.h
index b05485195..bccd30686 100644
--- a/ra/fsp/src/rm_zmod4xxx/oaq_1st_gen/zmod4510_config_oaq1.h
+++ b/ra/fsp/src/rm_zmod4xxx/oaq_1st_gen/zmod4510_config_oaq1.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/oaq_2nd_gen.h b/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/oaq_2nd_gen.h
index 705076c71..8b39f8b0a 100644
--- a/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/oaq_2nd_gen.h
+++ b/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/oaq_2nd_gen.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/rm_zmod4510_oaq_2nd_gen.c b/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/rm_zmod4510_oaq_2nd_gen.c
index 61d446253..85759cf63 100644
--- a/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/rm_zmod4510_oaq_2nd_gen.c
+++ b/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/rm_zmod4510_oaq_2nd_gen.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/zmod4510_config_oaq2.h b/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/zmod4510_config_oaq2.h
index 4e6d5af5a..cd6c434d0 100644
--- a/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/zmod4510_config_oaq2.h
+++ b/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/zmod4510_config_oaq2.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/odor/odor.h b/ra/fsp/src/rm_zmod4xxx/odor/odor.h
index 579e38ffb..f72eaefaf 100644
--- a/ra/fsp/src/rm_zmod4xxx/odor/odor.h
+++ b/ra/fsp/src/rm_zmod4xxx/odor/odor.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/odor/rm_zmod4410_odor.c b/ra/fsp/src/rm_zmod4xxx/odor/rm_zmod4410_odor.c
index 2eb1f0397..383fe836f 100644
--- a/ra/fsp/src/rm_zmod4xxx/odor/rm_zmod4410_odor.c
+++ b/ra/fsp/src/rm_zmod4xxx/odor/rm_zmod4410_odor.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/odor/zmod4410_config_odor.h b/ra/fsp/src/rm_zmod4xxx/odor/zmod4410_config_odor.h
index c80d27416..883aaf037 100644
--- a/ra/fsp/src/rm_zmod4xxx/odor/zmod4410_config_odor.h
+++ b/ra/fsp/src/rm_zmod4xxx/odor/zmod4410_config_odor.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/raq/raq.h b/ra/fsp/src/rm_zmod4xxx/raq/raq.h
index 2017c26ff..0a7c889a7 100644
--- a/ra/fsp/src/rm_zmod4xxx/raq/raq.h
+++ b/ra/fsp/src/rm_zmod4xxx/raq/raq.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/raq/rm_zmod4450_raq.c b/ra/fsp/src/rm_zmod4xxx/raq/rm_zmod4450_raq.c
index 45f199c33..26eaa7110 100644
--- a/ra/fsp/src/rm_zmod4xxx/raq/rm_zmod4450_raq.c
+++ b/ra/fsp/src/rm_zmod4xxx/raq/rm_zmod4450_raq.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/raq/zmod4450_config_raq.h b/ra/fsp/src/rm_zmod4xxx/raq/zmod4450_config_raq.h
index 35ec430dc..30bad7a6f 100644
--- a/ra/fsp/src/rm_zmod4xxx/raq/zmod4450_config_raq.h
+++ b/ra/fsp/src/rm_zmod4xxx/raq/zmod4450_config_raq.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/rm_zmod4xxx.c b/ra/fsp/src/rm_zmod4xxx/rm_zmod4xxx.c
index 8f1c2811a..d65207aa7 100644
--- a/ra/fsp/src/rm_zmod4xxx/rm_zmod4xxx.c
+++ b/ra/fsp/src/rm_zmod4xxx/rm_zmod4xxx.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/rm_zmod4xxx_ra_driver.c b/ra/fsp/src/rm_zmod4xxx/rm_zmod4xxx_ra_driver.c
index 4a2f20e3a..bbfcee1f9 100644
--- a/ra/fsp/src/rm_zmod4xxx/rm_zmod4xxx_ra_driver.c
+++ b/ra/fsp/src/rm_zmod4xxx/rm_zmod4xxx_ra_driver.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/sulfur_odor/rm_zmod4410_sulfur_odor.c b/ra/fsp/src/rm_zmod4xxx/sulfur_odor/rm_zmod4410_sulfur_odor.c
index 3e56a12a7..bc125866a 100644
--- a/ra/fsp/src/rm_zmod4xxx/sulfur_odor/rm_zmod4410_sulfur_odor.c
+++ b/ra/fsp/src/rm_zmod4xxx/sulfur_odor/rm_zmod4410_sulfur_odor.c
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/sulfur_odor/sulfur_odor.h b/ra/fsp/src/rm_zmod4xxx/sulfur_odor/sulfur_odor.h
index b6598dab6..8d65f2267 100644
--- a/ra/fsp/src/rm_zmod4xxx/sulfur_odor/sulfur_odor.h
+++ b/ra/fsp/src/rm_zmod4xxx/sulfur_odor/sulfur_odor.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/sulfur_odor/zmod4410_config_sulfur_odor.h b/ra/fsp/src/rm_zmod4xxx/sulfur_odor/zmod4410_config_sulfur_odor.h
index 4776e3e9c..f23ae8c0a 100644
--- a/ra/fsp/src/rm_zmod4xxx/sulfur_odor/zmod4410_config_sulfur_odor.h
+++ b/ra/fsp/src/rm_zmod4xxx/sulfur_odor/zmod4410_config_sulfur_odor.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
diff --git a/ra/fsp/src/rm_zmod4xxx/zmod4xxx_types.h b/ra/fsp/src/rm_zmod4xxx/zmod4xxx_types.h
index 08a04f152..f20ded077 100644
--- a/ra/fsp/src/rm_zmod4xxx/zmod4xxx_types.h
+++ b/ra/fsp/src/rm_zmod4xxx/zmod4xxx_types.h
@@ -1,5 +1,5 @@
 /***********************************************************************************************************************
- * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
  *
  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are