From e49528b011f795c2f0b0d1965f0350a269f8f937 Mon Sep 17 00:00:00 2001 From: ranvd Date: Sat, 15 Jun 2024 13:23:12 +0800 Subject: [PATCH] Enable SMP by `make check SMP=1` Before testing the SMP, you need to recompile Linux kernel. Please substitude the configuration file in `configs/linux.config` to Linux source code with .config file name, and cross compile it. --- Makefile | 16 +++-- configs/linux.config | 2 +- minimal-quad.dts | 140 +++++++++++++++++++++++++++++++++++++++++++ minimal.dts | 60 +------------------ 4 files changed, 155 insertions(+), 63 deletions(-) create mode 100644 minimal-quad.dts diff --git a/Makefile b/Makefile index a07f54b..627f201 100644 --- a/Makefile +++ b/Makefile @@ -74,6 +74,12 @@ minimal.dtb: minimal.dts $(subst ^,$S,$(filter -D^SEMU_FEATURE_%, $(subst -D$(S)SEMU_FEATURE,-D^SEMU_FEATURE,$(CFLAGS)))) $< \ | $(DTC) - > $@ +minimal-quad.dtb: minimal-quad.dts + $(VECHO) " DTC\t$@\n" + $(Q)$(CC) -nostdinc -E -P -x assembler-with-cpp -undef \ + $(subst ^,$S,$(filter -D^SEMU_FEATURE_%, $(subst -D$(S)SEMU_FEATURE,-D^SEMU_FEATURE,$(CFLAGS)))) $< \ + | $(DTC) - > $@ + # Rules for downloading prebuilt Linux kernel image include mk/external.mk @@ -81,12 +87,14 @@ ext4.img: $(Q)dd if=/dev/zero of=$@ bs=4k count=600 $(Q)$(MKFS_EXT4) -F $@ -check: $(BIN) minimal.dtb $(KERNEL_DATA) $(INITRD_DATA) $(DISKIMG_FILE) +SMP ?= 0 +check: $(BIN) minimal.dtb minimal-quad.dtb $(KERNEL_DATA) $(INITRD_DATA) $(DISKIMG_FILE) @$(call notice, Ready to launch Linux kernel. Please be patient.) +ifeq ($(SMP),1) + $(Q)./$(BIN) -k $(KERNEL_DATA) -b minimal-quad.dtb -i $(INITRD_DATA) $(OPTS) +else $(Q)./$(BIN) -k $(KERNEL_DATA) -b minimal.dtb -i $(INITRD_DATA) $(OPTS) - -debug: $(BIN) minimal.dtb $(KERNEL_DATA) $(INITRD_DATA) $(DISKIMG_FILE) - $(Q)gdb --args ./$(BIN) -k $(KERNEL_DATA) -b minimal.dtb -i $(INITRD_DATA) $(OPTS) +endif build-image: scripts/build-image.sh diff --git a/configs/linux.config b/configs/linux.config index fc3584e..99078d4 100644 --- a/configs/linux.config +++ b/configs/linux.config @@ -223,7 +223,7 @@ CONFIG_ARCH_RV32I=y # CONFIG_CMODEL_MEDLOW is not set CONFIG_CMODEL_MEDANY=y CONFIG_MODULE_SECTIONS=y -# CONFIG_SMP is not set +CONFIG_SMP=y CONFIG_TUNE_GENERIC=y # CONFIG_RISCV_ISA_C is not set CONFIG_TOOLCHAIN_HAS_ZICBOM=y diff --git a/minimal-quad.dts b/minimal-quad.dts new file mode 100644 index 0000000..7b52cbe --- /dev/null +++ b/minimal-quad.dts @@ -0,0 +1,140 @@ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "semu"; + + aliases { + serial0 = "/soc@F0000000/serial@4000000"; + }; + + chosen { + bootargs = "earlycon console=ttyS0"; + stdout-path = "serial0"; + linux,initrd-start = <0x1f700000>; /* @403 MiB (503 * 1024 * 1024) */ + linux,initrd-end = <0x1fefffff>; /* @511 MiB (511 * 1024 * 1024 - 1) */ + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <65000000>; + cpu0: cpu@0 { + status = "okay"; + device_type = "cpu"; + compatible = "riscv"; + reg = <0>; + riscv,isa = "rv32ima"; + mmu-type = "riscv,rv32"; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + #address-cells = <0>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + cpu1: cpu@1 { + status = "okay"; + device_type = "cpu"; + compatible = "riscv"; + reg = <1>; + riscv,isa = "rv32ima"; + mmu-type = "riscv,rv32"; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + #address-cells = <0>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + cpu2: cpu@2 { + status = "okay"; + device_type = "cpu"; + compatible = "riscv"; + reg = <2>; + riscv,isa = "rv32ima"; + mmu-type = "riscv,rv32"; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + #address-cells = <0>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + cpu3: cpu@3 { + status = "okay"; + device_type = "cpu"; + compatible = "riscv"; + reg = <3>; + riscv,isa = "rv32ima"; + mmu-type = "riscv,rv32"; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + #address-cells = <0>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + }; + + sram: memory@0 { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + reg-names = "sram0"; + }; + + soc: soc@F0000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x0 0xF0000000 0x10000000>; + interrupt-parent = <&plic0>; + + plic0: interrupt-controller@0 { + #interrupt-cells = <1>; + #address-cells = <0>; + compatible = "sifive,plic-1.0.0"; + reg = <0x0000000 0x4000000>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>, <&cpu2_intc 9>, <&cpu3_intc 9>; + riscv,ndev = <31>; + }; + + serial@4000000 { + compatible = "ns16550"; + reg = <0x4000000 0x100000>; + interrupts = <1>; + no-loopback-test; + clock-frequency = <5000000>; /* the baudrate divisor is ignored */ + }; + +#if SEMU_FEATURE_VIRTIONET + net0: virtio@4100000 { + compatible = "virtio,mmio"; + reg = <0x4100000 0x100000>; + interrupts = <2>; + }; +#endif + +#if SEMU_FEATURE_VIRTIOBLK + blk0: virtio@4200000 { + compatible = "virtio,mmio"; + reg = <0x4200000 0x200>; + interrupts = <3>; + }; +#endif + clint0: clint@4300000 { + compatible = "riscv,clint0"; + interrupt-controller; + interrupts-extended = + <&cpu0_intc 3 &cpu0_intc 7>, + <&cpu1_intc 3 &cpu1_intc 7>, + <&cpu2_intc 3 &cpu2_intc 7>, + <&cpu3_intc 3 &cpu3_intc 7>; + reg = <0x4300000 0x10000>; + }; + }; + +}; diff --git a/minimal.dts b/minimal.dts index 59cc546..0ebb69a 100644 --- a/minimal.dts +++ b/minimal.dts @@ -21,7 +21,6 @@ #size-cells = <0>; timebase-frequency = <65000000>; cpu0: cpu@0 { - status = "okay"; device_type = "cpu"; compatible = "riscv"; reg = <0>; @@ -34,49 +33,6 @@ compatible = "riscv,cpu-intc"; }; }; - cpu1: cpu@1 { - status = "okay"; - device_type = "cpu"; - compatible = "riscv"; - reg = <1>; - riscv,isa = "rv32ima"; - mmu-type = "riscv,rv32"; - cpu1_intc: interrupt-controller { - #interrupt-cells = <1>; - #address-cells = <0>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - }; - }; - cpu2: cpu@2 { - status = "okay"; - device_type = "cpu"; - compatible = "riscv"; - reg = <2>; - riscv,isa = "rv32ima"; - mmu-type = "riscv,rv32"; - cpu2_intc: interrupt-controller { - #interrupt-cells = <1>; - #address-cells = <0>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - }; - }; - cpu3: cpu@3 { - status = "okay"; - device_type = "cpu"; - compatible = "riscv"; - reg = <3>; - riscv,isa = "rv32ima"; - mmu-type = "riscv,rv32"; - cpu3_intc: interrupt-controller { - #interrupt-cells = <1>; - #address-cells = <0>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - }; - }; - }; sram: memory@0 { @@ -98,8 +54,7 @@ compatible = "sifive,plic-1.0.0"; reg = <0x0000000 0x4000000>; interrupt-controller; - interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>, <&cpu2_intc 9>, <&cpu3_intc 9>; -// interrupts-extended = <&cpu0_intc 9 &cpu0_intc 11>, <&cpu1_intc 9 &cpu1_intc 11>, <&cpu2_intc 9 &cpu2_intc 11>, <&cpu3_intc 9 &cpu3_intc 11>; + interrupts-extended = <&cpu0_intc 9>; riscv,ndev = <31>; }; @@ -126,16 +81,5 @@ interrupts = <3>; }; #endif - clint0: clint@4300000 { - compatible = "riscv,clint0"; - interrupt-controller; - interrupts-extended = - <&cpu0_intc 3 &cpu0_intc 7>, - <&cpu1_intc 3 &cpu1_intc 7>, - <&cpu2_intc 3 &cpu2_intc 7>, - <&cpu3_intc 3 &cpu3_intc 7>; - reg = <0x4300000 0x10000>; - }; }; - -}; +}; \ No newline at end of file