From 182731c6d4b6d542adb3b6f38fc3108492e5f6c5 Mon Sep 17 00:00:00 2001 From: "Kevin J. Sung" Date: Thu, 9 May 2024 21:45:37 -0400 Subject: [PATCH] remove unnecessary parens --- qiskit_research/utils/pulse_scaling.py | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/qiskit_research/utils/pulse_scaling.py b/qiskit_research/utils/pulse_scaling.py index 8a30e6f..af173eb 100644 --- a/qiskit_research/utils/pulse_scaling.py +++ b/qiskit_research/utils/pulse_scaling.py @@ -253,18 +253,12 @@ def run(self, dag: DAGCircuit) -> DAGCircuit: gp1 = next(dag.bfs_successors(rz_node)) if cx2_node in gp1[1]: if ( - ( - dag.find_bit(cx1_node.qargs[0]).index - == dag.find_bit(cx2_node.qargs[0]).index - ) - and ( - dag.find_bit(cx1_node.qargs[1]).index - == dag.find_bit(cx2_node.qargs[1]).index - ) - and ( - dag.find_bit(cx2_node.qargs[1]).index - == dag.find_bit(rz_node.qargs[0]).index - ) + dag.find_bit(cx1_node.qargs[0]).index + == dag.find_bit(cx2_node.qargs[0]).index + and dag.find_bit(cx1_node.qargs[1]).index + == dag.find_bit(cx2_node.qargs[1]).index + and dag.find_bit(cx2_node.qargs[1]).index + == dag.find_bit(rz_node.qargs[0]).index ): dag = self.sub_zz_in_dag( dag, cx1_node, rz_node, cx2_node