diff --git a/hal/hal-opencm3.c b/hal/hal-opencm3.c index 42af05b..c908249 100644 --- a/hal/hal-opencm3.c +++ b/hal/hal-opencm3.c @@ -70,14 +70,13 @@ const struct rcc_clock_scale benchmarkclock = { /* Patched function for newer PLL not yet supported by opencm3 */ void _rcc_set_main_pll(uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pllp, - uint32_t pllq, uint32_t pllr) -{ - RCC_PLLCFGR = (RCC_PLLCFGR_PLLM(pllm) << RCC_PLLCFGR_PLLM_SHIFT) | - (plln << RCC_PLLCFGR_PLLN_SHIFT) | - ((pllp & 0x1Fu) << 27u) | /* NEWER PLLP */ - (source << RCC_PLLCFGR_PLLSRC_SHIFT) | - (pllq << RCC_PLLCFGR_PLLQ_SHIFT) | - (pllr << RCC_PLLCFGR_PLLR_SHIFT) | RCC_PLLCFGR_PLLREN; + uint32_t pllq, uint32_t pllr) { + RCC_PLLCFGR = (RCC_PLLCFGR_PLLM(pllm) << RCC_PLLCFGR_PLLM_SHIFT) | + (plln << RCC_PLLCFGR_PLLN_SHIFT) | + ((pllp & 0x1Fu) << 27u) | /* NEWER PLLP */ + (source << RCC_PLLCFGR_PLLSRC_SHIFT) | + (pllq << RCC_PLLCFGR_PLLQ_SHIFT) | + (pllr << RCC_PLLCFGR_PLLR_SHIFT) | RCC_PLLCFGR_PLLREN; } #else @@ -181,69 +180,69 @@ static void clock_setup(enum clock_mode clock) { # else # error Unsupported STM32F2 Board # endif -#elif defined(NUCLEO_L4R5_BOARD) - rcc_periph_clock_enable(RCC_PWR); - rcc_periph_clock_enable(RCC_SYSCFG); - pwr_set_vos_scale(PWR_SCALE1); - /* The L4R5ZI chip also needs the R1MODE bit in PWR_CR5 register set, but - OpenCM3 doesn't support this yet. But luckily the default value for the bit - is 1. */ - switch (clock) { - case CLOCK_BENCHMARK: - /* Benchmark straight from the HSI16 without prescaling */ - rcc_osc_on(RCC_HSI16); - rcc_wait_for_osc_ready(RCC_HSI16); - rcc_ahb_frequency = 20000000; - rcc_apb1_frequency = 20000000; - rcc_apb2_frequency = 20000000; - _clock_freq = 20000000; - rcc_set_hpre(RCC_CFGR_HPRE_NODIV); - rcc_set_ppre1(RCC_CFGR_PPRE_NODIV); - rcc_set_ppre2(RCC_CFGR_PPRE_NODIV); - rcc_osc_off(RCC_PLL); - while(rcc_is_osc_ready(RCC_PLL)); - /* Configure the PLL oscillator (use CUBEMX tool -> scale HSI16 to 20MHz). */ - _rcc_set_main_pll(RCC_PLLCFGR_PLLSRC_HSI16, 1, 10, 2, RCC_PLLCFGR_PLLQ_DIV2, RCC_PLLCFGR_PLLR_DIV8); - /* Enable PLL oscillator and wait for it to stabilize. */ - rcc_osc_on(RCC_PLL); - flash_dcache_enable(); - flash_icache_enable(); - flash_set_ws(FLASH_ACR_LATENCY_0WS); - flash_prefetch_enable(); - rcc_set_sysclk_source(RCC_CFGR_SW_PLL); - rcc_wait_for_sysclk_status(RCC_PLL); - break; - case CLOCK_FAST: - default: - rcc_osc_on(RCC_HSI16); - rcc_wait_for_osc_ready(RCC_HSI16); - rcc_ahb_frequency = 120000000; - rcc_apb1_frequency = 120000000; - rcc_apb2_frequency = 120000000; - _clock_freq = 120000000; - rcc_set_hpre(RCC_CFGR_HPRE_NODIV); - rcc_set_ppre1(RCC_CFGR_PPRE_NODIV); - rcc_set_ppre2(RCC_CFGR_PPRE_NODIV); - rcc_osc_off(RCC_PLL); - while(rcc_is_osc_ready(RCC_PLL)); - /* Configure the PLL oscillator (use CUBEMX tool -> scale HSI16 to 120MHz). */ - _rcc_set_main_pll(RCC_PLLCFGR_PLLSRC_HSI16, 1, 15, 2, RCC_PLLCFGR_PLLQ_DIV2, RCC_PLLCFGR_PLLR_DIV2); - /* Enable PLL oscillator and wait for it to stabilize. */ - rcc_osc_on(RCC_PLL); - rcc_wait_for_osc_ready(RCC_PLL); - flash_dcache_enable(); - flash_icache_enable(); - flash_set_ws(0x05); - flash_prefetch_enable(); - rcc_set_sysclk_source(RCC_CFGR_SW_PLL); - rcc_wait_for_sysclk_status(RCC_PLL); - break; - } - rcc_osc_on(RCC_HSI48); /* HSI48 must always be on for RNG */ - rcc_wait_for_osc_ready(RCC_HSI48); - rcc_periph_clock_enable(RCC_RNG); - rcc_set_clock48_source(RCC_CCIPR_CLK48SEL_HSI48); - rng_enable(); + #elif defined(NUCLEO_L4R5_BOARD) + rcc_periph_clock_enable(RCC_PWR); + rcc_periph_clock_enable(RCC_SYSCFG); + pwr_set_vos_scale(PWR_SCALE1); + /* The L4R5ZI chip also needs the R1MODE bit in PWR_CR5 register set, but + OpenCM3 doesn't support this yet. But luckily the default value for the bit + is 1. */ + switch (clock) { + case CLOCK_BENCHMARK: + /* Benchmark straight from the HSI16 without prescaling */ + rcc_osc_on(RCC_HSI16); + rcc_wait_for_osc_ready(RCC_HSI16); + rcc_ahb_frequency = 20000000; + rcc_apb1_frequency = 20000000; + rcc_apb2_frequency = 20000000; + _clock_freq = 20000000; + rcc_set_hpre(RCC_CFGR_HPRE_NODIV); + rcc_set_ppre1(RCC_CFGR_PPRE_NODIV); + rcc_set_ppre2(RCC_CFGR_PPRE_NODIV); + rcc_osc_off(RCC_PLL); + while (rcc_is_osc_ready(RCC_PLL)); + /* Configure the PLL oscillator (use CUBEMX tool -> scale HSI16 to 20MHz). */ + _rcc_set_main_pll(RCC_PLLCFGR_PLLSRC_HSI16, 1, 10, 2, RCC_PLLCFGR_PLLQ_DIV2, RCC_PLLCFGR_PLLR_DIV8); + /* Enable PLL oscillator and wait for it to stabilize. */ + rcc_osc_on(RCC_PLL); + flash_dcache_enable(); + flash_icache_enable(); + flash_set_ws(FLASH_ACR_LATENCY_0WS); + flash_prefetch_enable(); + rcc_set_sysclk_source(RCC_CFGR_SW_PLL); + rcc_wait_for_sysclk_status(RCC_PLL); + break; + case CLOCK_FAST: + default: + rcc_osc_on(RCC_HSI16); + rcc_wait_for_osc_ready(RCC_HSI16); + rcc_ahb_frequency = 120000000; + rcc_apb1_frequency = 120000000; + rcc_apb2_frequency = 120000000; + _clock_freq = 120000000; + rcc_set_hpre(RCC_CFGR_HPRE_NODIV); + rcc_set_ppre1(RCC_CFGR_PPRE_NODIV); + rcc_set_ppre2(RCC_CFGR_PPRE_NODIV); + rcc_osc_off(RCC_PLL); + while (rcc_is_osc_ready(RCC_PLL)); + /* Configure the PLL oscillator (use CUBEMX tool -> scale HSI16 to 120MHz). */ + _rcc_set_main_pll(RCC_PLLCFGR_PLLSRC_HSI16, 1, 15, 2, RCC_PLLCFGR_PLLQ_DIV2, RCC_PLLCFGR_PLLR_DIV2); + /* Enable PLL oscillator and wait for it to stabilize. */ + rcc_osc_on(RCC_PLL); + rcc_wait_for_osc_ready(RCC_PLL); + flash_dcache_enable(); + flash_icache_enable(); + flash_set_ws(0x05); + flash_prefetch_enable(); + rcc_set_sysclk_source(RCC_CFGR_SW_PLL); + rcc_wait_for_sysclk_status(RCC_PLL); + break; + } + rcc_osc_on(RCC_HSI48); /* HSI48 must always be on for RNG */ + rcc_wait_for_osc_ready(RCC_HSI48); + rcc_periph_clock_enable(RCC_RNG); + rcc_set_clock48_source(RCC_CCIPR_CLK48SEL_HSI48); + rng_enable(); #else #error Unsupported platform #endif @@ -259,23 +258,23 @@ void usart_setup() { #elif defined(NUCLEO_BOARD) rcc_periph_clock_enable(RCC_GPIOA); rcc_periph_clock_enable(RCC_USART2); -#elif defined(NUCLEO_L4R5_BOARD) - rcc_periph_clock_enable(RCC_GPIOG); - rcc_periph_clock_enable(RCC_LPUART1); - - PWR_CR2 |= PWR_CR2_IOSV; - gpio_set_output_options(SERIAL_GPIO, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, SERIAL_PINS); - gpio_set_af(SERIAL_GPIO, GPIO_AF8, SERIAL_PINS); - gpio_mode_setup(SERIAL_GPIO, GPIO_MODE_AF, GPIO_PUPD_NONE, SERIAL_PINS); - usart_set_baudrate(SERIAL_USART, SERIAL_BAUD); - usart_set_databits(SERIAL_USART, 8); - usart_set_stopbits(SERIAL_USART, USART_STOPBITS_1); - usart_set_mode(SERIAL_USART, USART_MODE_TX_RX); - usart_set_parity(SERIAL_USART, USART_PARITY_NONE); - usart_set_flow_control(SERIAL_USART, USART_FLOWCONTROL_NONE); - usart_disable_rx_interrupt(SERIAL_USART); - usart_disable_tx_interrupt(SERIAL_USART); - usart_enable(SERIAL_USART); + #elif defined(NUCLEO_L4R5_BOARD) + rcc_periph_clock_enable(RCC_GPIOG); + rcc_periph_clock_enable(RCC_LPUART1); + + PWR_CR2 |= PWR_CR2_IOSV; + gpio_set_output_options(SERIAL_GPIO, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, SERIAL_PINS); + gpio_set_af(SERIAL_GPIO, GPIO_AF8, SERIAL_PINS); + gpio_mode_setup(SERIAL_GPIO, GPIO_MODE_AF, GPIO_PUPD_NONE, SERIAL_PINS); + usart_set_baudrate(SERIAL_USART, SERIAL_BAUD); + usart_set_databits(SERIAL_USART, 8); + usart_set_stopbits(SERIAL_USART, USART_STOPBITS_1); + usart_set_mode(SERIAL_USART, USART_MODE_TX_RX); + usart_set_parity(SERIAL_USART, USART_PARITY_NONE); + usart_set_flow_control(SERIAL_USART, USART_FLOWCONTROL_NONE); + usart_disable_rx_interrupt(SERIAL_USART); + usart_disable_tx_interrupt(SERIAL_USART); + usart_enable(SERIAL_USART); #else #error Unsupported platform #endif diff --git a/scripts/tests b/scripts/tests index 619c05a..38d9fd3 100755 --- a/scripts/tests +++ b/scripts/tests @@ -157,7 +157,6 @@ platform_map = RecursiveNamespace( f"{PLATFORM.NUCLEO_L4R5ZI}": { "openocd_cfg": f"{ROOT}/hal/nucleo_l4r5.cfg", }, - } )