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title = 'Box64 Now Provides Initial Support for RVV 1.0, with Up to 300% Performance Boost – Code is Now Open Source and Upstreamed' | ||
date = 2024-09-24 | ||
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The Box64 RISC-V backend initially used scalar instructions to emulate MMX, SSE*, and other x86_64 vector extensions, achieving good compatibility with rv64gc. However, since emulating a single vector instruction often requires several dozen scalar instructions, the performance of Box64 suffers significantly when running x86_64 programs that heavily rely on vector instructions. | ||
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Recently, engineers and interns from PLCT Lab have introduced initial support for RVV 1.0 in the Box64 RISC-V backend, submitting over 30 related PRs. This new support allows efficient translation of over 100 SSE instructions to RVV instructions. | ||
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[Read the full article](https://mp.weixin.qq.com/s/HxPo3ONjdJ52-Dsls8hl0A) |
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title = 'Box64 Now Provides Initial Support for RVV 1.0, with Up to 300% Performance Boost – Code is Now Open Source and Upstreamed' | ||
date = 2024-09-24 | ||
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The Box64 RISC-V backend initially used scalar instructions to emulate MMX, SSE*, and other x86_64 vector extensions, achieving good compatibility with rv64gc. However, since emulating a single vector instruction often requires several dozen scalar instructions, the performance of Box64 suffers significantly when running x86_64 programs that heavily rely on vector instructions. | ||
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Recently, engineers and interns from PLCT Lab have introduced initial support for RVV 1.0 in the Box64 RISC-V backend, submitting over 30 related PRs. This new support allows efficient translation of over 100 SSE instructions to RVV instructions. | ||
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[Read the full article](https://mp.weixin.qq.com/s/HxPo3ONjdJ52-Dsls8hl0A) |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,11 @@ | ||
+++ | ||
title = 'Box64 Now Provides Initial Support for RVV 1.0, with Up to 300% Performance Boost – Code is Now Open Source and Upstreamed' | ||
date = 2024-09-24 | ||
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The Box64 RISC-V backend initially used scalar instructions to emulate MMX, SSE*, and other x86_64 vector extensions, achieving good compatibility with rv64gc. However, since emulating a single vector instruction often requires several dozen scalar instructions, the performance of Box64 suffers significantly when running x86_64 programs that heavily rely on vector instructions. | ||
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Recently, engineers and interns from PLCT Lab have introduced initial support for RVV 1.0 in the Box64 RISC-V backend, submitting over 30 related PRs. This new support allows efficient translation of over 100 SSE instructions to RVV instructions. | ||
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||
[Read the full article](https://mp.weixin.qq.com/s/HxPo3ONjdJ52-Dsls8hl0A) |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,11 @@ | ||
+++ | ||
title = 'Box64 Now Provides Initial Support for RVV 1.0, with Up to 300% Performance Boost – Code is Now Open Source and Upstreamed' | ||
date = 2024-09-24 | ||
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+++ | ||
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The Box64 RISC-V backend initially used scalar instructions to emulate MMX, SSE*, and other x86_64 vector extensions, achieving good compatibility with rv64gc. However, since emulating a single vector instruction often requires several dozen scalar instructions, the performance of Box64 suffers significantly when running x86_64 programs that heavily rely on vector instructions. | ||
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Recently, engineers and interns from PLCT Lab have introduced initial support for RVV 1.0 in the Box64 RISC-V backend, submitting over 30 related PRs. This new support allows efficient translation of over 100 SSE instructions to RVV instructions. | ||
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||
[Read the full article](https://mp.weixin.qq.com/s/HxPo3ONjdJ52-Dsls8hl0A) |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
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Original file line number | Diff line number | Diff line change |
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title = 'Box64 初步支持 RVV 1.0,最高300%性能提升,代码已开源并合入上游(upstream)' | ||
date = 2024-09-24 | ||
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Box64 RISC-V 后端使用标量指令模拟实现了 MMX、SSE* 等 x86_64 向量扩展,实现了对于 rv64gc 的良好兼容性,但一条向量指令往往需要十几条甚至几十条标量指令才能模拟,因此,对于大量使用向量指令的 x86_64 程序,Box64 的性能损失相对较大。 | ||
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近日,PLCT 实验室的工程师和实习生为 Box64 RISC-V 后端新增了初步的 RVV 1.0 支持,提交相关 PR 30 余个,目前已经支持了百余条 SSE 指令到 RVV 指令的高效翻译。 | ||
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[阅读全文](https://mp.weixin.qq.com/s/HxPo3ONjdJ52-Dsls8hl0A) | ||
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