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vivado_4153.backup.log
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vivado_4153.backup.log
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#-----------------------------------------------------------
# Vivado v2013.4 (64-bit)
# SW Build 353583 on Mon Dec 9 17:26:26 MST 2013
# IP Build 208076 on Mon Dec 2 12:38:17 MST 2013
# Start of session at: Sat May 7 01:26:34 2016
# Process ID: 12807
# Log file: /home/snoperator/project_tubii_7020/vivado.log
# Journal file: /home/snoperator/project_tubii_7020/vivado.jou
#-----------------------------------------------------------
Attempting to get a license: Implementation
WARNING: [Common 17-301] Failed to get a license: Implementation
WARNING: [Vivado 15-19] WARNING: No 'Implementation' license found. This message may be safely ignored if a Vivado WebPACK or device-locked license, common for board kits, will be used during implementation.
Attempting to get a license: Synthesis
WARNING: [Common 17-301] Failed to get a license: Synthesis
Loading parts and site information from /home/snoperator/Xilinx/Vivado/2013.4/data/parts/arch.xml
Parsing RTL primitives file [/home/snoperator/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [/home/snoperator/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
start_gui
open_project /home/snoperator/project_tubii_7020/project_tubii_7020.xpr
INFO: [Project 1-313] Project file moved from 'C:/Users/Ian/project_tubii_7020' since last save.
CRITICAL WARNING: [Project 1-311] Could not find the file '/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/ip/system_triggerOut_0_0/system_triggerOut_0_0.upgrade_log', nor could it be found using path '/home/snoperator/project_tubii_7020/C:/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/ip/system_triggerOut_0_0/system_triggerOut_0_0.upgrade_log'.
CRITICAL WARNING: [Project 1-311] Could not find the file '/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/ip/system_ShiftRegs_0_0/system_ShiftRegs_0_0.upgrade_log', nor could it be found using path '/home/snoperator/project_tubii_7020/C:/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/ip/system_ShiftRegs_0_0/system_ShiftRegs_0_0.upgrade_log'.
IP Repository Path: Could not find the directory '/home/snoperator/project_tubii_7020/sync_gtid_1.0', nor could it be found using path '/home/snoperator/project_tubii_7020/C:/Users/Ian/project_tubii_7020/sync_gtid_1.0'.
IP Repository Path: Could not find the directory '/home/snoperator/project_tubii_7020/SyncGTID_1.0', nor could it be found using path '/home/snoperator/project_tubii_7020/C:/Users/Ian/project_tubii_7020/SyncGTID_1.0'.
IP Repository Path: Could not find the directory '/home/snoperator/project_tubii_7020/tubii_triggers_1.0', nor could it be found using path '/home/snoperator/project_tubii_7020/C:/Users/Ian/project_tubii_7020/tubii_triggers_1.0'.
IP Repository Path: Could not find the directory '/home/snoperator/project_tubii_7020/tubii_triggers_1.0', nor could it be found using path '/home/snoperator/project_tubii_7020/C:/Users/Ian/project_tubii_7020/tubii_triggers_1.0'.
IP Repository Path: Could not find the directory '/home/snoperator/project_tubii_7020/ShiftReg_1.0', nor could it be found using path '/home/snoperator/project_tubii_7020/C:/Users/Ian/project_tubii_7020/ShiftReg_1.0'.
IP Repository Path: Could not find the directory '/project_tubii_7020/ShiftRegs_1.0', nor could it be found using path '/home/snoperator/project_tubii_7020/C:/project_tubii_7020/ShiftRegs_1.0'.
IP Repository Path: Could not find the directory '/home/snoperator/project_tubii_7020/triggerOut_1.0', nor could it be found using path '/home/snoperator/project_tubii_7020/C:/Users/Ian/project_tubii_7020/triggerOut_1.0'.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/snoperator/project_tubii_7020/sync_gtid_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/snoperator/project_tubii_7020/SyncGTID_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/triggers_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/snoperator/project_tubii_7020/tubii_triggers_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
WARNING: [IP_Flow 19-2207] Repository '/home/snoperator/project_tubii_7020/tubii_triggers_1.0' already exists; ignoring attempt to add it again.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/snoperator/project_tubii_7020/tubii_triggers_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/ShiftRegisters_1.0'.
WARNING: [IP_Flow 19-2207] Repository '/home/snoperator/project_tubii_7020/ShiftRegisters_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/ShiftRegisters_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/buttonTrigger_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/snoperator/project_tubii_7020/ShiftReg_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/implement_gtid_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/TrigWordDelay_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/oneshot_pulse_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/fifo_readout_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/counter_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/project_tubii_7020/ShiftRegs_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/countDisplay_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/comboTrigger_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/testPulser_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/snoperator/project_tubii_7020/triggerOut_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/clockLogic_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/triggerSplit_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/testDelay_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/prescaleTrigger_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/burstTrigger_1.0'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/snoperator/Xilinx/Vivado/2013.4/data/ip'.
open_project: Time (s): cpu = 00:00:15 ; elapsed = 00:00:08 . Memory (MB): peak = 5052.395 ; gain = 167.184
open_bd_design {/home/snoperator/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/system.bd}
Adding component instance block -- xilinx.com:ip:processing_system7:5.3 - processing_system7_0
Adding component instance block -- xilinx.com:user:clockLogic:1.0 - clockLogic_0
Adding component instance block -- xilinx.com:ip:fifo_generator:11.0 - fifo_generator_0
INFO: [xilinx.com:ip:fifo_generator:11.0-5968] /fifo_generator_0Executing the post_config_ip from bd
Adding component instance block -- xilinx.com:user:triggerCombine:1.0 - triggerSplit_0
Adding component instance block -- xilinx.com:user:countDisplay:1.0 - countDisplay_0
Adding component instance block -- xilinx.com:user:comboTrigger:1.0 - comboTrigger_0
Adding component instance block -- xilinx.com:user:prescaleTrigger:1.0 - prescaleTrigger_0
Adding component instance block -- xilinx.com:user:counter:1.0 - counter_0
Adding component instance block -- xilinx.com:user:testPulser:1.0 - MZ_Happy
Adding component instance block -- xilinx.com:user:testPulser:1.0 - genericPulser
Adding component instance block -- xilinx.com:user:testPulser:1.0 - smelliePulser
Adding component instance block -- xilinx.com:user:testPulser:1.0 - telliePulser
Adding component instance block -- xilinx.com:user:oneshot_pulse:1.0 - oneshot_pulse_0
Adding component instance block -- xilinx.com:user:oneshot_pulse:1.0 - oneshot_pulse_1
Adding component instance block -- xilinx.com:user:testDelay:1.0 - genericDelay
Adding component instance block -- xilinx.com:user:testDelay:1.0 - gtDelay
Adding component instance block -- xilinx.com:user:testDelay:1.0 - smellieDelay
Adding component instance block -- xilinx.com:user:testDelay:1.0 - tellieDelay
Adding component instance block -- xilinx.com:user:TrigWordDelay:1.0 - TrigWordDelay_0
Adding component instance block -- xilinx.com:user:buttonTrigger:1.0 - buttonTrigger_0
Adding component instance block -- xilinx.com:user:burstTrigger:1.0 - burstTrigger_0
Adding component instance block -- xilinx.com:user:ShiftRegisters:1.0 - ShiftRegisters_0
Adding component instance block -- xilinx.com:ip:xadc_wiz:3.0 - xadc_wiz_0
Adding component instance block -- xilinx.com:user:fifo_readout:1.0 - fifo_readout_0
Adding component instance block -- xilinx.com:user:implement_gtid:1.0 - implement_gtid_0
Adding component instance block -- xilinx.com:user:triggers:1.0 - triggers_0
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - tier2_xbar_0
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - tier2_xbar_1
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - tier2_xbar_2
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Successfully read diagram <system> from BD file </home/snoperator/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/system.bd>
open_bd_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 5178.535 ; gain = 117.633
reset_run impl_1 -prev_step
WARNING: [Vivado 12-1017] Problems encountered:
1. Process appears to be on host 'IAN-PENN' and cannot be killed from host 'monag2.sp.snolab.ca'
ipx::edit_ip_in_project -upgrade true -name {triggers_v1_0_project} -directory {/home/snoperator/project_tubii_7020/triggers_1.0/triggers_v1_0_project} {/home/snoperator/project_tubii_7020/triggers_1.0/component.xml}
CRITICAL WARNING: [IP_Flow 19-2328] The specified repository '/home/snoperator/project_tubii_7020/sync_gtid_1.0' could not be found, so it will not be added.
CRITICAL WARNING: [IP_Flow 19-2328] The specified repository '/home/snoperator/project_tubii_7020/SyncGTID_1.0' could not be found, so it will not be added.
CRITICAL WARNING: [IP_Flow 19-2328] The specified repository '/home/snoperator/project_tubii_7020/tubii_triggers_1.0' could not be found, so it will not be added.
CRITICAL WARNING: [IP_Flow 19-2328] The specified repository '/home/snoperator/project_tubii_7020/tubii_triggers_1.0' could not be found, so it will not be added.
CRITICAL WARNING: [IP_Flow 19-2329] The specified repository '/home/snoperator/project_tubii_7020/ShiftRegisters_1.0' is already a user repository, so not adding it.
CRITICAL WARNING: [IP_Flow 19-2328] The specified repository '/home/snoperator/project_tubii_7020/ShiftReg_1.0' could not be found, so it will not be added.
CRITICAL WARNING: [IP_Flow 19-2328] The specified repository '/project_tubii_7020/ShiftRegs_1.0' could not be found, so it will not be added.
CRITICAL WARNING: [IP_Flow 19-2328] The specified repository '/home/snoperator/project_tubii_7020/triggerOut_1.0' could not be found, so it will not be added.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/triggers_1.0'.
WARNING: [IP_Flow 19-3299] If you move the project, the path for repository '/home/snoperator/project_tubii_7020/triggers_1.0' may become invalid. A better location for the repository would be in a path adjacent to the project.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/ShiftRegisters_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/buttonTrigger_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/implement_gtid_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/TrigWordDelay_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/oneshot_pulse_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/fifo_readout_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/counter_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/countDisplay_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/comboTrigger_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/testPulser_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/clockLogic_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/triggerSplit_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/testDelay_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/prescaleTrigger_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/burstTrigger_1.0'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/snoperator/Xilinx/Vivado/2013.4/data/ip'.
update_compile_order -fileset sim_1
launch_runs synth_1
[Sat May 7 01:43:13 2016] Launched synth_1...
Run output will be captured here: /home/snoperator/project_tubii_7020/triggers_1.0/triggers_v1_0_project/triggers_v1_0_project.runs/synth_1/runme.log
ipx::update_ip_instances -delete_project true
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/snoperator/project_tubii_7020/sync_gtid_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/snoperator/project_tubii_7020/SyncGTID_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/triggers_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/snoperator/project_tubii_7020/tubii_triggers_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
WARNING: [IP_Flow 19-2207] Repository '/home/snoperator/project_tubii_7020/tubii_triggers_1.0' already exists; ignoring attempt to add it again.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/snoperator/project_tubii_7020/tubii_triggers_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/ShiftRegisters_1.0'.
WARNING: [IP_Flow 19-2207] Repository '/home/snoperator/project_tubii_7020/ShiftRegisters_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/ShiftRegisters_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/buttonTrigger_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/snoperator/project_tubii_7020/ShiftReg_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/implement_gtid_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/TrigWordDelay_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/oneshot_pulse_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/fifo_readout_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/counter_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/project_tubii_7020/ShiftRegs_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/countDisplay_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/comboTrigger_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/testPulser_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/snoperator/project_tubii_7020/triggerOut_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/clockLogic_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/triggerSplit_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/testDelay_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/prescaleTrigger_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/snoperator/project_tubii_7020/burstTrigger_1.0'.
INFO: [IP_Flow 19-3422] Upgraded system_triggers_0_0 (triggers_v1_0 1.0) from revision 24 to revision 25
INFO: [IP_Flow 19-3471] Wrote upgrade log to '/home/snoperator/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/ip/system_triggers_0_0/system_triggers_0_0.upgrade_log'.
Wrote : </home/snoperator/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/system.bd>
ipx::update_ip_instances: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 5299.133 ; gain = 0.000
reset_run synth_1
launch_runs impl_1
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified.
Please check your design and connect them if needed:
/xadc_wiz_0/vp_in
/xadc_wiz_0/vn_in
VHDL Output written to : system.vhd
VHDL Output written to : system_wrapper.vhd
Wrote : </home/snoperator/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/system.bd>
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_processing_system7_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /processing_system7_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_triggerSplit_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /triggerSplit_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_xbar_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_xbar_0' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/xbar .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_comboTrigger_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /comboTrigger_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_burstTrigger_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /burstTrigger_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_prescaleTrigger_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /prescaleTrigger_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_countDisplay_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /countDisplay_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_clockLogic_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /clockLogic_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_testDelay_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /genericDelay .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_testDelay_2_5'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /tellieDelay .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_testDelay_3_6'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /smellieDelay .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_testPulser_0_7'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /MZ_Happy .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_testDelay_0_7'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /gtDelay .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_testPulser_0_9'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /genericPulser .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_testPulser_0_10'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /telliePulser .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_testPulser_1_11'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /smelliePulser .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_fifo_generator_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /fifo_generator_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_fifo_readout_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /fifo_readout_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_counter_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /counter_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_oneshot_pulse_1_1'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /oneshot_pulse_1 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_oneshot_pulse_0_2'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /oneshot_pulse_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_TrigWordDelay_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /TrigWordDelay_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_implement_gtid_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /implement_gtid_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_buttonTrigger_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /buttonTrigger_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_ShiftRegisters_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /ShiftRegisters_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_triggers_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /triggers_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_xadc_wiz_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /xadc_wiz_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_tier2_xbar_0_1304'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_tier2_xbar_0_1304' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/tier2_xbar_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_tier2_xbar_1_1305'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_tier2_xbar_1_1305' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/tier2_xbar_1 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_tier2_xbar_2_1306'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_tier2_xbar_2_1306' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/tier2_xbar_2 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_auto_cc_391'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_cc_391' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m14_couplers/auto_cc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_auto_cc_392'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_cc_392' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m16_couplers/auto_cc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_auto_cc_393'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_cc_393' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m17_couplers/auto_cc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_auto_cc_394'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_cc_394' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m19_couplers/auto_cc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_auto_cc_395'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_cc_395' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m21_couplers/auto_cc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_auto_pc_77'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_pc_77' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/s00_couplers/auto_pc .
INFO: [BD 41-539] Not generating up to date 'Implementation' target for block design system
INFO: [BD 41-1029] Generation completed for the IP Integrator block /processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /triggerSplit_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /comboTrigger_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /burstTrigger_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /prescaleTrigger_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /countDisplay_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /clockLogic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /genericDelay .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /tellieDelay .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /smellieDelay .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /MZ_Happy .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /gtDelay .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /genericPulser .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /telliePulser .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /smelliePulser .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /fifo_generator_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /fifo_readout_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /counter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /oneshot_pulse_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /oneshot_pulse_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /TrigWordDelay_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /implement_gtid_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /buttonTrigger_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /ShiftRegisters_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /triggers_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /xadc_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/tier2_xbar_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/tier2_xbar_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/tier2_xbar_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m14_couplers/auto_cc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m16_couplers/auto_cc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m17_couplers/auto_cc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m19_couplers/auto_cc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m21_couplers/auto_cc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/s00_couplers/auto_pc .
[Sat May 7 01:45:35 2016] Launched synth_1...
Run output will be captured here: /home/snoperator/project_tubii_7020/project_tubii_7020.runs/synth_1/runme.log
[Sat May 7 01:45:35 2016] Launched impl_1...
Run output will be captured here: /home/snoperator/project_tubii_7020/project_tubii_7020.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 5329.422 ; gain = 30.289
open_run impl_1
INFO: [Netlist 29-17] Analyzing 244 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2013.4
Loading clock regions from /home/snoperator/Xilinx/Vivado/2013.4/data/parts/xilinx/zynq/zynq/xc7z020/ClockRegion.xml
Loading clock buffers from /home/snoperator/Xilinx/Vivado/2013.4/data/parts/xilinx/zynq/zynq/xc7z020/ClockBuffers.xml
Loading clock placement rules from /home/snoperator/Xilinx/Vivado/2013.4/data/parts/xilinx/zynq/ClockPlacerRules.xml
Loading package pin functions from /home/snoperator/Xilinx/Vivado/2013.4/data/parts/xilinx/zynq/PinFunctions.xml...
Loading package from /home/snoperator/Xilinx/Vivado/2013.4/data/parts/xilinx/zynq/zynq/xc7z020/clg400/Package.xml
Loading io standards from /home/snoperator/Xilinx/Vivado/2013.4/data/./parts/xilinx/zynq/IOStandards.xml
Parsing XDC File [/home/snoperator/project_tubii_7020/.Xil/Vivado-12807-monag2.sp.snolab.ca/dcp/system_wrapper.xdc]
Finished Parsing XDC File [/home/snoperator/project_tubii_7020/.Xil/Vivado-12807-monag2.sp.snolab.ca/dcp/system_wrapper.xdc]
Reading XDEF placement.
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00.94 ; elapsed = 00:00:00.93 . Memory (MB): peak = 5963.645 ; gain = 18.000
Restoring placement.
Restored 5568 out of 5568 XDEF sites from archive | CPU: 3.050000 secs | Memory: 47.636887 MB |
INFO: [Opt 31-138] Pushed 0 inverter(s).
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files:
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 130 instances were transformed.
RAM16X1D => RAM16X1D (RAMD32, RAMD32, GND): 10 instances
RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 120 instances
open_run: Time (s): cpu = 00:00:32 ; elapsed = 00:00:25 . Memory (MB): peak = 6139.621 ; gain = 798.199
launch_runs impl_1 -to_step write_bitstream
[Sat May 7 02:04:48 2016] Launched impl_1...
Run output will be captured here: /home/snoperator/project_tubii_7020/project_tubii_7020.runs/impl_1/runme.log
export_hardware [get_files /home/snoperator/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/system.bd] [get_runs impl_1] -bitstream
WARNING: [Vivado 12-690] Backannotated BMM file does not exist in the run dir:/home/snoperator/project_tubii_7020/project_tubii_7020.runs/impl_1/system_wrapper_bd.bmm
Exporting to file /home/snoperator/project_tubii_7020/project_tubii_7020.sdk/SDK/SDK_Export/hw/system.xml
INFO: [BD 41-436] exporting bit file '/home/snoperator/project_tubii_7020/project_tubii_7020.runs/impl_1/system_wrapper.bit'...
export_hardware: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 6194.859 ; gain = 22.188
export_hardware [get_files /home/snoperator/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/system.bd] [get_runs impl_1] -bitstream
WARNING: [Vivado 12-690] Backannotated BMM file does not exist in the run dir:/home/snoperator/project_tubii_7020/project_tubii_7020.runs/impl_1/system_wrapper_bd.bmm
Exporting to file /home/snoperator/project_tubii_7020/project_tubii_7020.sdk/SDK/SDK_Export/hw/system.xml
INFO: [BD 41-436] exporting bit file '/home/snoperator/project_tubii_7020/project_tubii_7020.runs/impl_1/system_wrapper.bit'...
export_hardware: Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 6194.859 ; gain = 0.000
open_bd_design {/home/snoperator/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/system.bd}
exit
INFO: [Common 17-206] Exiting Vivado at Sat May 7 02:08:34 2016...