Verilog / VHDL code sample on hover for "extern" modules

[VonTum]

When the user declares an extern module, their intention is to include some external Verilog or VHDL code.

It would be convenient if we would provide a Verilog or VHDL code sample for the interface of this extern module, such that the user can copy or verify it.

Example:

extern module MEMORY_M20K #(int WIDTH, int DEPTH_LOG2, bool FORCE_TO_ZERO) {
  domain clk
  
  interface write: bool writeEnable, int writeAddr, bool[WIDTH] dataIn
  
  interface read: bool readEnable, int readAddr -> bool[WIDTH] dataOut, bool eccStatus
} 

What the hover signature could then say is: (lifted straight from https://github.com/VonTum/Dedekind/blob/main/hardware/src/memory.v#L112C1-L129C3)

module MEMORY_M20K #(
    parameter WIDTH = 20,
    parameter DEPTH_LOG2 = 9,
    parameter FORCE_TO_ZERO = 1 // Force output to 0 when not readEnable
) (
    input clk,
    
    // Write Side
    input writeEnable,
    input[DEPTH_LOG2-1:0] writeAddr,
    input[WIDTH-1:0] dataIn,
    
    // Read Side
    input readEnable,
    input[DEPTH_LOG2-1:0] readAddr,
    output[WIDTH-1:0] dataOut,
    output eccStatus
);

This may be a bit of a complicated example, especially because it's parametrized (which is an open issue #25), but the basic point stands.