Submodule Latency Count Inference

[VonTum]

Infer Latency Count-based parameters. Typical example: The FIFO.

FIFO #(DEPTH: 100) fromFIFO
FIFO #(DEPTH: 100) f // No T, no LATENCY_MARGIN

if f.ready() {
  if fromFIFO.pop() : int d { // Let's say this takes 3 cycles
    reg int data = d * d // Another pipeline stage
    f.push(data) // Compiler should infer LATENCY_MARGIN = 4; T: type int
  }
}

• Concrete Typecheck with HM
• Instantiate Modules interleaved with Concrete Typecheck
• Delayed Constraints for HM
• Partial Concrete Typechecking
• Type Inference for Concrete Types -> First to get my toes wet
• Inference from Ports
• Inference from Generative Parameters
• Extend inference to Latency Count
• Hover for inline submodules too

This is the main goal for the Nov 27th Talk!