Systementwurf Teamproject 2024

[VonTum]

Development of the SUS Hardware Design Language

Hi all, I (Lennart) am developing a new Hardware Design Language (HDL) called SUS, intended to compete with Synthesizable Verilog and VHDL. SUS focuses on offering a thin, intuitive syntax for hardware designers, that encapsulates the concepts programmers have in their heads (like pipelining) without reducing the possible design space.

At the Paderborn Center for Parallel Computing (PC2), FPGA hardware design is a key area of research. We are one of the few centers in the world focused on this type of hardware accelerator design. This project is motivated by the current shortcomings in contemporary high-level synthesis (HLS) toolflows, and the need for more reliable and efficient design solutions.

We are seeking a group of bachelor's students to collaborate on the project, contributing to different areas of development. This is an opportunity to get involved in cutting-edge hardware language design and make impactful contributions to a growing project.

The project will be instructed in English.

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Project Objectives:

The goal of this project is to involve students in the development of SUS. Depending on your skills and interests, there are several areas you can contribute to:

1. Core Feature Development for SUS:
   Students with experience in Rust programming and a deep understanding of hardware design are invited to work on the core language features of SUS. This role requires a solid grasp of hardware design principles, as you’ll be involved in the actual language design aspects. To see what kind of work there is still to be done, have a look at the issues tab.

2. Language Server Protocol (LSP) Development:
   If you’re interested in improving the user experience, you can help build the LSP for SUS. This will enhance IDE integrations, such as VSCode, allowing for real-time feedback during development.

3. Website Creation for SUS:
   For students skilled in web development, there is the opportunity to create a modern and accessible website for SUS, which will house documentation, tutorials, and project updates.

4. Standard Library Development:
   Contributing to the SUS standard library involves creating essential modules, such as floating-point operation wrappers and memory blocks, which form the backbone of the language’s functionality.

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Team Structure & Topic Selection:

Students can choose the area that aligns with their interests, and teams of 2-3 will be formed for each topic. We aim to focus on 2 of the following areas:

• Core feature development for SUS
• LSP development
• Website creation
• Standard library module development

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SUS Background:

SUS aims to improve upon existing hardware description languages like Verilog and VHDL by offering several unique features:

1. Generative Variables and Types:
   SUS allows for flexible combinations of variables and types, deferring type checking until after instantiation, thus avoiding the challenges posed by "Dependent Types."

2. Easy Pipelining:
   SUS introduces “Latency Counting,” an orthogonal construct that simplifies pipelining by allowing pipeline registers to be added without interfering with other language features.

3. Interface-based Pipeline Separation:
   SUS prevents users from crossing unrelated signals through interfaces, while handling Clock Domain Crossings at the pipeline level, maintaining logical signal separation.

SUS is designed to generate netlists that are fully analyzable by traditional synthesis tools, while focusing on synchronous hardware design. While asynchronous hardware is unsupported, SUS offers an IDE plugin for VSCode that enables a seamless development feedback loop through in-IDE compiling, type checking, and instantiation.

To learn more, you can visit the GitHub repository or join our Discord community:

• GitHub Repository: https://github.com/pc2/sus-compiler
• Discord Server: https://discord.gg/ZCgzjbrppz

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Expectations and Requirements:

• Core Feature Development: Proficiency in Rust and a strong understanding of hardware design principles.
• LSP Development: Experience with language server protocols or IDE plugin development is helpful.
• Web Development: Familiarity with modern web frameworks (e.g., React, Vue.js) is ideal.
• Standard Library Development: Basic knowledge of hardware design, particularly for modules like floating-point operations.

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Why Join Us?

This project provides a chance to contribute to an innovative hardware design tool that addresses real-world challenges in FPGA and hardware accelerator development. You’ll gain hands-on experience, collaborate with peers, and help create a tool that could shape the future of hardware design.

If interested, please reach out with your preferred area of contribution. Together, we can build something revolutionary!