From a093db5667d14fe56eb0cbc97b25fe7433beb9fb Mon Sep 17 00:00:00 2001 From: Lennart Van Hirtum Date: Wed, 3 Jan 2024 15:23:32 +0100 Subject: [PATCH] Store name itself in NamedWire instead of DeclID --- src/codegen_fallback.rs | 2 +- src/flattening.rs | 27 +++++++++++++++++++-------- src/instantiation/mod.rs | 6 +++--- 3 files changed, 23 insertions(+), 12 deletions(-) diff --git a/src/codegen_fallback.rs b/src/codegen_fallback.rs index cb6c04a..14e7e98 100644 --- a/src/codegen_fallback.rs +++ b/src/codegen_fallback.rs @@ -67,7 +67,7 @@ pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule) -> String program_text.push_str(");\n"); for (_id, w) in &instance.wires { - if let WireSource::NamedWire{read_only : _, identifier_type, decl_id : _} = &md.flattened.instantiations[w.original_wire].extract_wire().inst { + if let WireSource::NamedWire{read_only : _, identifier_type, name : _, name_token : _} = &md.flattened.instantiations[w.original_wire].extract_wire().inst { // Don't print named inputs and outputs, already did that in interface match identifier_type { IdentifierType::Input | IdentifierType::Output => {continue;} diff --git a/src/flattening.rs b/src/flattening.rs index f859a16..0b8609d 100644 --- a/src/flattening.rs +++ b/src/flattening.rs @@ -55,7 +55,7 @@ pub struct InterfacePort { #[derive(Debug)] pub enum WireSource { - NamedWire{read_only : bool, identifier_type : IdentifierType, decl_id : Option}, + NamedWire{read_only : bool, identifier_type : IdentifierType, name : Box, name_token : Option}, UnaryOp{op : Operator, right : SpanFlatID}, BinaryOp{op : Operator, left : SpanFlatID, right : SpanFlatID}, ArrayAccess{arr : SpanFlatID, arr_idx : SpanFlatID}, @@ -157,7 +157,18 @@ impl<'l, 'm, 'fl> FlatteningContext<'l, 'm, 'fl> { } else { IdentifierType::Output }; - InterfacePort{is_input : port.is_input, id : self.instantiations.alloc(Instantiation::Wire(WireInstance{typ: port.typ.clone(), is_compiletime : false, span : typ_span, inst : WireSource::NamedWire { read_only : !port.is_input, identifier_type, decl_id : None }}))} + let id = self.instantiations.alloc(Instantiation::Wire(WireInstance{ + typ: port.typ.clone(), + is_compiletime : false, + span : typ_span, + inst : WireSource::NamedWire{ + read_only : !port.is_input, + identifier_type, + name : format!("{}_{}", &module.link_info.name, &port.port_name).into_boxed_str(), + name_token : None + } + })); + InterfacePort{is_input : port.is_input, id} }).collect(); Instantiation::SubModule{name, module_uuid, typ_span, interface_wires} @@ -276,7 +287,7 @@ impl<'l, 'm, 'fl> FlatteningContext<'l, 'm, 'fl> { Some(match expr { AssignableExpression::Named{local_idx} => { let root = self.decl_to_flat_map[*local_idx].unwrap(); - let WireSource::NamedWire { read_only, identifier_type : _, decl_id : _ } = &self.instantiations[root].extract_wire().inst else { + let WireSource::NamedWire{read_only, identifier_type : _, name : _, name_token : _} = &self.instantiations[root].extract_wire().inst else { unreachable!("Attempting to assign to a Instantiation::PlainWire") }; if *read_only { @@ -337,7 +348,7 @@ impl<'l, 'm, 'fl> FlatteningContext<'l, 'm, 'fl> { Named::Type(_) => { assert!(decl.identifier_type != IdentifierType::Input); assert!(decl.identifier_type != IdentifierType::Output); - Instantiation::Wire(WireInstance{typ, is_compiletime : decl.identifier_type == IdentifierType::Generative, span : typ_span, inst : WireSource::NamedWire{read_only : false, identifier_type : decl.identifier_type, decl_id : Some(*decl_id)}}) + Instantiation::Wire(WireInstance{typ, is_compiletime : decl.identifier_type == IdentifierType::Generative, span : typ_span, inst : WireSource::NamedWire{read_only : false, identifier_type : decl.identifier_type, name : decl.name.clone(), name_token : Some(decl.name_token)}}) } } } else { @@ -491,7 +502,7 @@ impl FlattenedModule { }; let typ = context.map_to_type(&decl.typ.0, &module.link_info.global_references); - let wire_id = context.instantiations.alloc(Instantiation::Wire(WireInstance{typ : typ.clone(), is_compiletime : false, span : decl.typ.1, inst : WireSource::NamedWire{read_only: is_input, identifier_type : decl.identifier_type, decl_id : Some(decl_id)}})); + let wire_id = context.instantiations.alloc(Instantiation::Wire(WireInstance{typ : typ.clone(), is_compiletime : false, span : decl.typ.1, inst : WireSource::NamedWire{read_only: is_input, identifier_type : decl.identifier_type, name : decl.name.clone(), name_token : Some(decl.name_token)}})); interface.interface_wires.push(FlattenedInterfacePort { wire_id, is_input, typ, port_name: decl.name.clone(), span: decl.span }); context.decl_to_flat_map[decl_id] = Some(wire_id); @@ -557,7 +568,7 @@ impl FlattenedModule { match &self.instantiations[item] { Instantiation::Wire(wire) => { match &wire.inst { - WireSource::NamedWire{read_only : _, identifier_type : _, decl_id : _} => {} + WireSource::NamedWire{read_only : _, identifier_type : _, name : _, name_token : _} => {} WireSource::UnaryOp{op : _, right} => {func(right.0);} WireSource::BinaryOp{op : _, left, right} => {func(left.0); func(right.0);} WireSource::ArrayAccess{arr, arr_idx} => {func(arr.0); func(arr_idx.0)} @@ -585,8 +596,8 @@ impl FlattenedModule { // Now produce warnings from the unused list for (id, inst) in &self.instantiations { if !is_instance_used_map[id] { - if let Instantiation::Wire(WireInstance{typ : _, is_compiletime : _, span : _, inst : WireSource::NamedWire { read_only : _, identifier_type : _, decl_id : Some(decl_id) }}) = inst { - self.errors.warn_basic(Span::from(md.declarations[*decl_id].name_token), "Unused Variable: This variable does not affect the output ports of this module"); + if let Instantiation::Wire(WireInstance{typ : _, is_compiletime : _, span : _, inst : WireSource::NamedWire { read_only : _, identifier_type : _, name : _, name_token : Some(name_token)}}) = inst { + self.errors.warn_basic(Span::from(*name_token), "Unused Variable: This variable does not affect the output ports of this module"); } } } diff --git a/src/instantiation/mod.rs b/src/instantiation/mod.rs index dfd3735..2e08319 100644 --- a/src/instantiation/mod.rs +++ b/src/instantiation/mod.rs @@ -282,7 +282,7 @@ impl<'fl, 'l> InstantiationContext<'fl, 'l> { } fn compute_compile_time(&self, wire_inst : &WireSource, typ : &ConcreteType) -> Option { Some(match &wire_inst { - WireSource::NamedWire{read_only, identifier_type: _, decl_id: _} => { + WireSource::NamedWire{read_only, identifier_type: _, name : _, name_token : _} => { /*Do nothing (in fact re-initializes the wire to 'empty'), just corresponds to wire declaration*/ if *read_only { todo!("Modules can't be computed at compile time yet"); @@ -349,7 +349,7 @@ impl<'fl, 'l> InstantiationContext<'fl, 'l> { SubModuleOrWire::CompileTimeValue(value_computed) } else { let (name, source) = match &w.inst { - WireSource::NamedWire{read_only, identifier_type, decl_id} => { + WireSource::NamedWire{read_only, identifier_type, name, name_token : _} => { let source = if *read_only { RealWireDataSource::ReadOnly } else { @@ -357,7 +357,7 @@ impl<'fl, 'l> InstantiationContext<'fl, 'l> { let is_state = if *identifier_type == IdentifierType::State{StateInitialValue::State{initial_value: Value::Unset}} else {StateInitialValue::Combinatorial}; RealWireDataSource::Multiplexer{is_state, sources : Vec::new()} }; - (decl_id.map(|id| self.module.declarations[id].name.clone()), source) + (Some(name.clone()), source) } WireSource::UnaryOp{op, right} => { let Some(right) = self.get_wire_or_constant_as_wire(right) else {return};