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output1.txt
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output1.txt
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*** Important settings for the Xilinx Backend module ***
Synthesis top module: snake
FPGA part (PART): xc6slx16-3-csg324
Constraints file: lab.ucf
nice -n 19 make -f Makefile lab-synthdir/layoutdefault/design.bit PROJNAME="lab" S="snake.vhd GPU/GPU.vhd GMEM/GMEM.vhd CPU/cpu.vhd CPU/alu.vhd CPU/asr.vhd CPU/grx.vhd CPU/ir.vhd CPU/kr2.vhd CPU/pm.vhd CPU/pm.vhd CPU/kr1.vhd CPU/pc.vhd CPU/upc.vhd leddriver.vhd SPI/spi.vhd SPI/spimaster.vhd UART/UART.vhd Common/shiftregister.vhd Common/register.vhd" U="lab.ucf" XST_OPT="" PART="xc6slx16-3-csg324" INCDIRS=""
make[1]: Entering directory `/edu/tobhu543/TSEA83/projekt'
*** Creating synthesis scripts ***
mkdir -p lab-synthdir/xst/synth
echo "-top $(basename $(echo snake.vhd | sed 's/\..*$//'))" >> lab-synthdir/xst/synth/design.scr.tmp
echo "-p xc6slx16-3-csg324" >> lab-synthdir/xst/synth/design.scr.tmp
echo >> lab-synthdir/xst/synth/design.scr.tmp
rm -f lab-synthdir/xst/synth/design.prj
touch lab-synthdir/xst/synth/design.prj
echo 'vhdl work "../../../snake.vhd"' >> lab-synthdir/xst/synth/design.prj; echo 'vhdl work "../../../GPU/GPU.vhd"' >> lab-synthdir/xst/synth/design.prj; echo 'vhdl work "../../../GMEM/GMEM.vhd"' >> lab-synthdir/xst/synth/design.prj; echo 'vhdl work "../../../CPU/cpu.vhd"' >> lab-synthdir/xst/synth/design.prj; echo 'vhdl work "../../../CPU/alu.vhd"' >> lab-synthdir/xst/synth/design.prj; echo 'vhdl work "../../../CPU/asr.vhd"' >> lab-synthdir/xst/synth/design.prj; echo 'vhdl work "../../../CPU/grx.vhd"' >> lab-synthdir/xst/synth/design.prj; echo 'vhdl work "../../../CPU/ir.vhd"' >> lab-synthdir/xst/synth/design.prj; echo 'vhdl work "../../../CPU/kr2.vhd"' >> lab-synthdir/xst/synth/design.prj; echo 'vhdl work "../../../CPU/pm.vhd"' >> lab-synthdir/xst/synth/design.prj; echo 'vhdl work "../../../CPU/pm.vhd"' >> lab-synthdir/xst/synth/design.prj; echo 'vhdl work "../../../CPU/kr1.vhd"' >> lab-synthdir/xst/synth/design.prj; echo 'vhdl work "../../../CPU/pc.vhd"' >> lab-synthdir/xst/synth/design.prj; echo 'vhdl work "../../../CPU/upc.vhd"' >> lab-synthdir/xst/synth/design.prj; echo 'vhdl work "../../../leddriver.vhd"' >> lab-synthdir/xst/synth/design.prj; echo 'vhdl work "../../../SPI/spi.vhd"' >> lab-synthdir/xst/synth/design.prj; echo 'vhdl work "../../../SPI/spimaster.vhd"' >> lab-synthdir/xst/synth/design.prj; echo 'vhdl work "../../../UART/UART.vhd"' >> lab-synthdir/xst/synth/design.prj; echo 'vhdl work "../../../Common/shiftregister.vhd"' >> lab-synthdir/xst/synth/design.prj; echo 'vhdl work "../../../Common/register.vhd"' >> lab-synthdir/xst/synth/design.prj;
mv lab-synthdir/xst/synth/design.scr.tmp lab-synthdir/xst/synth/design.scr
*** Synthesizing ***
rm -rf lab-synthdir/xst/synth/tmpdir
mkdir -p lab-synthdir/xst/synth/tmpdir
rm -rf lab-synthdir/xst/synth/xst
mkdir -p lab-synthdir/xst/synth/xst
cd lab-synthdir/xst/synth; source /sw/xilinx/ise_14.2i/ISE_DS/settings64.sh; xst -ifn design.scr -ofn design.syr
Release 12.4 - xst M.81d (lin64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to tmpdir
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 0.08 secs
-->
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "design.prj"
---- Target Parameters
Output File Name : "design.ngc"
Target Device : xc6slx16-3-csg324
---- Source Options
Top Module Name : snake
=========================================================================
WARNING:Xst:29 - Optimization Effort not specified
The following parameters have been added:
Optimization Goal : SPEED
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "/edu/tobhu543/TSEA83/projekt/lab-synthdir/xst/synth/../../../snake.vhd" into library work
Parsing entity <snake>.
Parsing architecture <behv> of entity <snake>.
Parsing VHDL file "/edu/tobhu543/TSEA83/projekt/lab-synthdir/xst/synth/../../../GPU/GPU.vhd" into library work
Parsing entity <GPU>.
Parsing architecture <behv> of entity <gpu>.
Parsing VHDL file "/edu/tobhu543/TSEA83/projekt/lab-synthdir/xst/synth/../../../GMEM/GMEM.vhd" into library work
Parsing entity <GMEM>.
Parsing architecture <GMbehv> of entity <gmem>.
Parsing VHDL file "/edu/tobhu543/TSEA83/projekt/lab-synthdir/xst/synth/../../../CPU/cpu.vhd" into library work
Parsing entity <cpu>.
Parsing architecture <behav> of entity <cpu>.
Parsing VHDL file "/edu/tobhu543/TSEA83/projekt/lab-synthdir/xst/synth/../../../CPU/alu.vhd" into library work
Parsing entity <alu>.
Parsing architecture <behav> of entity <alu>.
Parsing VHDL file "/edu/tobhu543/TSEA83/projekt/lab-synthdir/xst/synth/../../../CPU/asr.vhd" into library work
Parsing entity <asr>.
Parsing architecture <behav> of entity <asr>.
Parsing VHDL file "/edu/tobhu543/TSEA83/projekt/lab-synthdir/xst/synth/../../../CPU/grx.vhd" into library work
Parsing entity <grx>.
Parsing architecture <behav> of entity <grx>.
Parsing VHDL file "/edu/tobhu543/TSEA83/projekt/lab-synthdir/xst/synth/../../../CPU/ir.vhd" into library work
Parsing entity <ir>.
Parsing architecture <behav> of entity <ir>.
Parsing VHDL file "/edu/tobhu543/TSEA83/projekt/lab-synthdir/xst/synth/../../../CPU/kr2.vhd" into library work
Parsing entity <kr2>.
Parsing architecture <behav> of entity <kr2>.
Parsing VHDL file "/edu/tobhu543/TSEA83/projekt/lab-synthdir/xst/synth/../../../CPU/pm.vhd" into library work
Parsing entity <pm>.
Parsing architecture <behav> of entity <pm>.
Parsing VHDL file "/edu/tobhu543/TSEA83/projekt/lab-synthdir/xst/synth/../../../CPU/pm.vhd" into library work
Parsing entity <pm>.
Parsing architecture <behav> of entity <pm>.
Parsing VHDL file "/edu/tobhu543/TSEA83/projekt/lab-synthdir/xst/synth/../../../CPU/kr1.vhd" into library work
Parsing entity <kr1>.
Parsing architecture <behav> of entity <kr1>.
Parsing VHDL file "/edu/tobhu543/TSEA83/projekt/lab-synthdir/xst/synth/../../../CPU/pc.vhd" into library work
Parsing entity <pc>.
Parsing architecture <behav> of entity <pc>.
Parsing VHDL file "/edu/tobhu543/TSEA83/projekt/lab-synthdir/xst/synth/../../../CPU/upc.vhd" into library work
Parsing entity <upc>.
Parsing architecture <behav> of entity <upc>.
Parsing VHDL file "/edu/tobhu543/TSEA83/projekt/lab-synthdir/xst/synth/../../../leddriver.vhd" into library work
Parsing entity <leddriver>.
Parsing architecture <Behavioral> of entity <leddriver>.
Parsing VHDL file "/edu/tobhu543/TSEA83/projekt/lab-synthdir/xst/synth/../../../SPI/spi.vhd" into library work
Parsing entity <spi>.
Parsing architecture <behav> of entity <spi>.
Parsing VHDL file "/edu/tobhu543/TSEA83/projekt/lab-synthdir/xst/synth/../../../SPI/spimaster.vhd" into library work
Parsing entity <spimaster>.
Parsing architecture <behav> of entity <spimaster>.
Parsing VHDL file "/edu/tobhu543/TSEA83/projekt/lab-synthdir/xst/synth/../../../UART/UART.vhd" into library work
Parsing entity <UART>.
Parsing architecture <behav> of entity <uart>.
Parsing VHDL file "/edu/tobhu543/TSEA83/projekt/lab-synthdir/xst/synth/../../../Common/shiftregister.vhd" into library work
Parsing entity <shiftregi>.
Parsing architecture <behav> of entity <shiftregi>.
Parsing VHDL file "/edu/tobhu543/TSEA83/projekt/lab-synthdir/xst/synth/../../../Common/register.vhd" into library work
Parsing entity <regi>.
Parsing architecture <behav> of entity <regi>.
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating entity <snake> (architecture <behv>) from library <work>.
Elaborating entity <spimaster> (architecture <behav>) with generics from library <work>.
Elaborating entity <spi> (architecture <behav>) from library <work>.
Elaborating entity <UART> (architecture <behav>) with generics from library <work>.
Elaborating entity <shiftregi> (architecture <behav>) with generics from library <work>.
Elaborating entity <regi> (architecture <behav>) with generics from library <work>.
Elaborating entity <leddriver> (architecture <Behavioral>) from library <work>.
Elaborating entity <cpu> (architecture <behav>) from library <work>.
Elaborating entity <grx> (architecture <behav>) from library <work>.
Elaborating entity <alu> (architecture <behav>) from library <work>.
Elaborating entity <pm> (architecture <behav>) from library <work>.
Elaborating entity <kr1> (architecture <behav>) from library <work>.
Elaborating entity <kr2> (architecture <behav>) from library <work>.
Elaborating entity <upc> (architecture <behav>) from library <work>.
Elaborating entity <ir> (architecture <behav>) from library <work>.
Elaborating entity <asr> (architecture <behav>) from library <work>.
Elaborating entity <pc> (architecture <behav>) from library <work>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <snake>.
Related source file is "/edu/tobhu543/TSEA83/projekt/snake.vhd".
WARNING:Xst:647 - Input <sw<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3010 - "/edu/tobhu543/TSEA83/projekt/snake.vhd" line 173: Output port <dbus> of the instance <uart_inst> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/edu/tobhu543/TSEA83/projekt/snake.vhd" line 173: Output port <debug_signal> of the instance <uart_inst> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/edu/tobhu543/TSEA83/projekt/snake.vhd" line 173: Output port <uart_word_ready> of the instance <uart_inst> is unconnected or connected to loadless signal.
Summary:
no macro.
Unit <snake> synthesized.
Synthesizing Unit <spimaster>.
Related source file is "/edu/tobhu543/TSEA83/projekt/SPI/spimaster.vhd".
amount = 4
Found 1-bit tristate buffer for signal <buss<15>> created at line 43
Found 1-bit tristate buffer for signal <buss<14>> created at line 43
Found 1-bit tristate buffer for signal <buss<13>> created at line 43
Found 1-bit tristate buffer for signal <buss<12>> created at line 43
Found 1-bit tristate buffer for signal <buss<11>> created at line 43
Found 1-bit tristate buffer for signal <buss<10>> created at line 43
Found 1-bit tristate buffer for signal <buss<9>> created at line 43
Found 1-bit tristate buffer for signal <buss<8>> created at line 43
Found 1-bit tristate buffer for signal <buss<7>> created at line 43
Found 1-bit tristate buffer for signal <buss<6>> created at line 43
Found 1-bit tristate buffer for signal <buss<5>> created at line 43
Found 1-bit tristate buffer for signal <buss<4>> created at line 43
Found 1-bit tristate buffer for signal <buss<3>> created at line 43
Found 1-bit tristate buffer for signal <buss<2>> created at line 43
Found 1-bit tristate buffer for signal <buss<1>> created at line 43
Found 1-bit tristate buffer for signal <buss<0>> created at line 43
Summary:
inferred 16 Tristate(s).
Unit <spimaster> synthesized.
Synthesizing Unit <spi>.
Related source file is "/edu/tobhu543/TSEA83/projekt/SPI/spi.vhd".
WARNING:Xst:2563 - Inout <flags> is never assigned. Tied to value Z.
Found 6-bit register for signal <count6bit>.
Found 1-bit register for signal <ss_tmp>.
Found 1-bit register for signal <sclk_tmp>.
Found 10-bit register for signal <count10bit>.
Found 1-bit register for signal <mosi_tmp>.
Found 3-bit register for signal <count3bit>.
Found 3-bit register for signal <count3bit2>.
Found 16-bit register for signal <xreg>.
Found 4-bit register for signal <buss>.
Found 16-bit register for signal <yreg>.
Found 8-bit register for signal <breg>.
Found 8-bit register for signal <count7bit>.
Found 8-bit adder for signal <count7bit[7]_GND_8_o_add_0_OUT> created at line 50.
Found 10-bit adder for signal <count10bit[9]_GND_8_o_add_6_OUT> created at line 65.
Found 6-bit adder for signal <count6bit[5]_GND_8_o_add_15_OUT> created at line 77.
Found 3-bit adder for signal <count3bit[2]_GND_8_o_add_18_OUT> created at line 79.
Found 3-bit adder for signal <count3bit2[2]_GND_8_o_add_20_OUT> created at line 81.
Found 7-bit tristate buffer for signal <flags> created at line 8
Found 3-bit comparator lessequal for signal <n0025> created at line 83
Found 16-bit comparator greater for signal <yreg[15]_GND_8_o_LessThan_30_o> created at line 98
Found 16-bit comparator greater for signal <GND_8_o_yreg[15]_LessThan_31_o> created at line 100
Found 16-bit comparator greater for signal <xreg[15]_GND_8_o_LessThan_32_o> created at line 102
Found 16-bit comparator greater for signal <GND_8_o_xreg[15]_LessThan_33_o> created at line 104
Summary:
inferred 5 Adder/Subtractor(s).
inferred 77 D-type flip-flop(s).
inferred 5 Comparator(s).
inferred 29 Multiplexer(s).
inferred 1 Tristate(s).
Unit <spi> synthesized.
Synthesizing Unit <UART>.
Related source file is "/edu/tobhu543/TSEA83/projekt/UART/UART.vhd".
N = 16
Found 1-bit register for signal <uart2>.
Found 14-bit register for signal <count>.
Found 1-bit register for signal <cur_byte>.
Found 1-bit register for signal <uart_word_flipflop>.
Found 1-bit register for signal <uart1>.
Found 14-bit adder for signal <count[13]_GND_25_o_add_5_OUT> created at line 97.
Found 1-bit tristate buffer for signal <dbus<15>> created at line 155
Found 1-bit tristate buffer for signal <dbus<14>> created at line 155
Found 1-bit tristate buffer for signal <dbus<13>> created at line 155
Found 1-bit tristate buffer for signal <dbus<12>> created at line 155
Found 1-bit tristate buffer for signal <dbus<11>> created at line 155
Found 1-bit tristate buffer for signal <dbus<10>> created at line 155
Found 1-bit tristate buffer for signal <dbus<9>> created at line 155
Found 1-bit tristate buffer for signal <dbus<8>> created at line 155
Found 1-bit tristate buffer for signal <dbus<7>> created at line 155
Found 1-bit tristate buffer for signal <dbus<6>> created at line 155
Found 1-bit tristate buffer for signal <dbus<5>> created at line 155
Found 1-bit tristate buffer for signal <dbus<4>> created at line 155
Found 1-bit tristate buffer for signal <dbus<3>> created at line 155
Found 1-bit tristate buffer for signal <dbus<2>> created at line 155
Found 1-bit tristate buffer for signal <dbus<1>> created at line 155
Found 1-bit tristate buffer for signal <dbus<0>> created at line 155
Summary:
inferred 1 Adder/Subtractor(s).
inferred 18 D-type flip-flop(s).
inferred 12 Multiplexer(s).
inferred 16 Tristate(s).
Unit <UART> synthesized.
Synthesizing Unit <shiftregi>.
Related source file is "/edu/tobhu543/TSEA83/projekt/Common/shiftregister.vhd".
N = 10
Found 10-bit register for signal <regi>.
Found 1-bit tristate buffer for signal <output<9>> created at line 34
Found 1-bit tristate buffer for signal <output<8>> created at line 34
Found 1-bit tristate buffer for signal <output<7>> created at line 34
Found 1-bit tristate buffer for signal <output<6>> created at line 34
Found 1-bit tristate buffer for signal <output<5>> created at line 34
Found 1-bit tristate buffer for signal <output<4>> created at line 34
Found 1-bit tristate buffer for signal <output<3>> created at line 34
Found 1-bit tristate buffer for signal <output<2>> created at line 34
Found 1-bit tristate buffer for signal <output<1>> created at line 34
Found 1-bit tristate buffer for signal <output<0>> created at line 34
Summary:
inferred 10 D-type flip-flop(s).
inferred 10 Tristate(s).
Unit <shiftregi> synthesized.
Synthesizing Unit <regi>.
Related source file is "/edu/tobhu543/TSEA83/projekt/Common/register.vhd".
N = 8
Found 8-bit register for signal <regi>.
Found 1-bit tristate buffer for signal <output<7>> created at line 30
Found 1-bit tristate buffer for signal <output<6>> created at line 30
Found 1-bit tristate buffer for signal <output<5>> created at line 30
Found 1-bit tristate buffer for signal <output<4>> created at line 30
Found 1-bit tristate buffer for signal <output<3>> created at line 30
Found 1-bit tristate buffer for signal <output<2>> created at line 30
Found 1-bit tristate buffer for signal <output<1>> created at line 30
Found 1-bit tristate buffer for signal <output<0>> created at line 30
Summary:
inferred 8 D-type flip-flop(s).
inferred 8 Tristate(s).
Unit <regi> synthesized.
Synthesizing Unit <leddriver>.
Related source file is "/edu/tobhu543/TSEA83/projekt/leddriver.vhd".
WARNING:Xst:647 - Input <rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 7-bit register for signal <segments>.
Found 4-bit register for signal <an>.
Found 18-bit register for signal <counter_r>.
Found 18-bit adder for signal <counter_r[17]_GND_62_o_add_2_OUT> created at line 1241.
Found 16x7-bit Read Only RAM for signal <v[3]_GND_62_o_wide_mux_3_OUT>
Found 4x4-bit Read Only RAM for signal <counter_r[17]_PWR_16_o_wide_mux_4_OUT>
Found 1-bit 4-to-1 multiplexer for signal <v<3>> created at line 39.
Found 1-bit 4-to-1 multiplexer for signal <v<2>> created at line 39.
Found 1-bit 4-to-1 multiplexer for signal <v<1>> created at line 39.
Found 1-bit 4-to-1 multiplexer for signal <v<0>> created at line 39.
Summary:
inferred 2 RAM(s).
inferred 1 Adder/Subtractor(s).
inferred 29 D-type flip-flop(s).
inferred 4 Multiplexer(s).
Unit <leddriver> synthesized.
Synthesizing Unit <cpu>.
Related source file is "/edu/tobhu543/TSEA83/projekt/CPU/cpu.vhd".
INFO:Xst:2774 - HDL ADVISOR - KEEP property attached to signal dflags<2> may hinder XST clustering optimizations.
Summary:
no macro.
Unit <cpu> synthesized.
Synthesizing Unit <grx>.
Related source file is "/edu/tobhu543/TSEA83/projekt/CPU/grx.vhd".
Found 16-bit register for signal <gr<1>>.
Found 16-bit register for signal <gr<2>>.
Found 16-bit register for signal <gr<3>>.
Found 16-bit register for signal <gr<4>>.
Found 16-bit register for signal <gr<5>>.
Found 16-bit register for signal <gr<6>>.
Found 16-bit register for signal <gr<7>>.
Found 16-bit register for signal <gr<8>>.
Found 16-bit register for signal <gr<9>>.
Found 16-bit register for signal <gr<10>>.
Found 16-bit register for signal <gr<11>>.
Found 16-bit register for signal <gr<12>>.
Found 16-bit register for signal <gr<13>>.
Found 16-bit register for signal <gr<14>>.
Found 16-bit register for signal <gr<15>>.
Found 16-bit register for signal <gr<0>>.
INFO:Xst:3019 - HDL ADVISOR - 256 flip-flops were inferred for signal <gr>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
INFO:Xst:3019 - HDL ADVISOR - 256 flip-flops were inferred for signal <gr>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
Found 16-bit 16-to-1 multiplexer for signal <at[3]_gr[15][15]_wide_mux_51_OUT> created at line 33.
Found 16-bit 16-to-1 multiplexer for signal <ind[3]_gr[15][15]_wide_mux_54_OUT> created at line 34.
Found 1-bit tristate buffer for signal <buss<15>> created at line 33
Found 1-bit tristate buffer for signal <buss<14>> created at line 33
Found 1-bit tristate buffer for signal <buss<13>> created at line 33
Found 1-bit tristate buffer for signal <buss<12>> created at line 33
Found 1-bit tristate buffer for signal <buss<11>> created at line 33
Found 1-bit tristate buffer for signal <buss<10>> created at line 33
Found 1-bit tristate buffer for signal <buss<9>> created at line 33
Found 1-bit tristate buffer for signal <buss<8>> created at line 33
Found 1-bit tristate buffer for signal <buss<7>> created at line 33
Found 1-bit tristate buffer for signal <buss<6>> created at line 33
Found 1-bit tristate buffer for signal <buss<5>> created at line 33
Found 1-bit tristate buffer for signal <buss<4>> created at line 33
Found 1-bit tristate buffer for signal <buss<3>> created at line 33
Found 1-bit tristate buffer for signal <buss<2>> created at line 33
Found 1-bit tristate buffer for signal <buss<1>> created at line 33
Found 1-bit tristate buffer for signal <buss<0>> created at line 33
Found 1-bit tristate buffer for signal <buss<15>> created at line 34
Found 1-bit tristate buffer for signal <buss<14>> created at line 34
Found 1-bit tristate buffer for signal <buss<13>> created at line 34
Found 1-bit tristate buffer for signal <buss<12>> created at line 34
Found 1-bit tristate buffer for signal <buss<11>> created at line 34
Found 1-bit tristate buffer for signal <buss<10>> created at line 34
Found 1-bit tristate buffer for signal <buss<9>> created at line 34
Found 1-bit tristate buffer for signal <buss<8>> created at line 34
Found 1-bit tristate buffer for signal <buss<7>> created at line 34
Found 1-bit tristate buffer for signal <buss<6>> created at line 34
Found 1-bit tristate buffer for signal <buss<5>> created at line 34
Found 1-bit tristate buffer for signal <buss<4>> created at line 34
Found 1-bit tristate buffer for signal <buss<3>> created at line 34
Found 1-bit tristate buffer for signal <buss<2>> created at line 34
Found 1-bit tristate buffer for signal <buss<1>> created at line 34
Found 1-bit tristate buffer for signal <buss<0>> created at line 34
Summary:
inferred 256 D-type flip-flop(s).
inferred 3 Multiplexer(s).
inferred 32 Tristate(s).
Unit <grx> synthesized.
Synthesizing Unit <alu>.
Related source file is "/edu/tobhu543/TSEA83/projekt/CPU/alu.vhd".
Found 4-bit register for signal <flags<6:3>>.
Found 1-bit register for signal <random_tmp>.
Found 32-bit register for signal <random_reg>.
Found 16-bit register for signal <ar>.
Found 18-bit subtractor for signal <n0177> created at line 86.
Found 18-bit subtractor for signal <n0178> created at line 85.
Found 18-bit subtractor for signal <n0179> created at line 84.
Found 18-bit subtractor for signal <n0180> created at line 83.
Found 16-bit adder for signal <ar[15]_signed_buss[15]_add_29_OUT> created at line 68.
Found 17-bit adder for signal <n0181> created at line 82.
Found 17-bit adder for signal <n0182> created at line 81.
Found 17-bit adder for signal <n0183> created at line 80.
Found 17-bit adder for signal <n0184> created at line 79.
Found 16-bit subtractor for signal <ar[15]_signed_buss[15]_sub_36_OUT<15:0>> created at line 65.
Found 16-bit subtractor for signal <PWR_20_o_signed_buss[15]_sub_41_OUT<15:0>> created at line 1326.
WARNING:Xst:737 - Found 1-bit latch for signal <alu_out_extra<16>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Found 1-bit tristate buffer for signal <flags<2>> created at line 55
Found 1-bit tristate buffer for signal <flags<1>> created at line 55
Found 1-bit tristate buffer for signal <flags<0>> created at line 55
Found 1-bit tristate buffer for signal <buss<15>> created at line 57
Found 1-bit tristate buffer for signal <buss<14>> created at line 57
Found 1-bit tristate buffer for signal <buss<13>> created at line 57
Found 1-bit tristate buffer for signal <buss<12>> created at line 57
Found 1-bit tristate buffer for signal <buss<11>> created at line 57
Found 1-bit tristate buffer for signal <buss<10>> created at line 57
Found 1-bit tristate buffer for signal <buss<9>> created at line 57
Found 1-bit tristate buffer for signal <buss<8>> created at line 57
Found 1-bit tristate buffer for signal <buss<7>> created at line 57
Found 1-bit tristate buffer for signal <buss<6>> created at line 57
Found 1-bit tristate buffer for signal <buss<5>> created at line 57
Found 1-bit tristate buffer for signal <buss<4>> created at line 57
Found 1-bit tristate buffer for signal <buss<3>> created at line 57
Found 1-bit tristate buffer for signal <buss<2>> created at line 57
Found 1-bit tristate buffer for signal <buss<1>> created at line 57
Found 1-bit tristate buffer for signal <buss<0>> created at line 57
Found 16-bit comparator greater for signal <n0076> created at line 84
Found 16-bit comparator greater for signal <n0079> created at line 85
Found 16-bit comparator greater for signal <n> created at line 103
Summary:
inferred 11 Adder/Subtractor(s).
inferred 53 D-type flip-flop(s).
inferred 1 Latch(s).
inferred 3 Comparator(s).
inferred 24 Multiplexer(s).
inferred 19 Tristate(s).
Unit <alu> synthesized.
Synthesizing Unit <pm>.
Related source file is "/edu/tobhu543/TSEA83/projekt/CPU/pm.vhd".
Found 4096x16-bit single-port RAM <Mram_pmem> for signal <pmem>.
Found 16-bit register for signal <out_tmp>.
Found 1-bit tristate buffer for signal <buss<15>> created at line 102
Found 1-bit tristate buffer for signal <buss<14>> created at line 102
Found 1-bit tristate buffer for signal <buss<13>> created at line 102
Found 1-bit tristate buffer for signal <buss<12>> created at line 102
Found 1-bit tristate buffer for signal <buss<11>> created at line 102
Found 1-bit tristate buffer for signal <buss<10>> created at line 102
Found 1-bit tristate buffer for signal <buss<9>> created at line 102
Found 1-bit tristate buffer for signal <buss<8>> created at line 102
Found 1-bit tristate buffer for signal <buss<7>> created at line 102
Found 1-bit tristate buffer for signal <buss<6>> created at line 102
Found 1-bit tristate buffer for signal <buss<5>> created at line 102
Found 1-bit tristate buffer for signal <buss<4>> created at line 102
Found 1-bit tristate buffer for signal <buss<3>> created at line 102
Found 1-bit tristate buffer for signal <buss<2>> created at line 102
Found 1-bit tristate buffer for signal <buss<1>> created at line 102
Found 1-bit tristate buffer for signal <buss<0>> created at line 102
Found 1-bit tristate buffer for signal <in_tmp<15>> created at line 103
Found 1-bit tristate buffer for signal <in_tmp<14>> created at line 103
Found 1-bit tristate buffer for signal <in_tmp<13>> created at line 103
Found 1-bit tristate buffer for signal <in_tmp<12>> created at line 103
Found 1-bit tristate buffer for signal <in_tmp<11>> created at line 103
Found 1-bit tristate buffer for signal <in_tmp<10>> created at line 103
Found 1-bit tristate buffer for signal <in_tmp<9>> created at line 103
Found 1-bit tristate buffer for signal <in_tmp<8>> created at line 103
Found 1-bit tristate buffer for signal <in_tmp<7>> created at line 103
Found 1-bit tristate buffer for signal <in_tmp<6>> created at line 103
Found 1-bit tristate buffer for signal <in_tmp<5>> created at line 103
Found 1-bit tristate buffer for signal <in_tmp<4>> created at line 103
Found 1-bit tristate buffer for signal <in_tmp<3>> created at line 103
Found 1-bit tristate buffer for signal <in_tmp<2>> created at line 103
Found 1-bit tristate buffer for signal <in_tmp<1>> created at line 103
Found 1-bit tristate buffer for signal <in_tmp<0>> created at line 103
Summary:
inferred 1 RAM(s).
inferred 16 D-type flip-flop(s).
inferred 32 Tristate(s).
Unit <pm> synthesized.
Synthesizing Unit <kr1>.
Related source file is "/edu/tobhu543/TSEA83/projekt/CPU/kr1.vhd".
Found 64x8-bit Read Only RAM for signal <output>
Summary:
inferred 1 RAM(s).
Unit <kr1> synthesized.
Synthesizing Unit <kr2>.
Related source file is "/edu/tobhu543/TSEA83/projekt/CPU/kr2.vhd".
Found 4x8-bit Read Only RAM for signal <output>
Summary:
inferred 1 RAM(s).
Unit <kr2> synthesized.
Synthesizing Unit <upc>.
Related source file is "/edu/tobhu543/TSEA83/projekt/CPU/upc.vhd".
Found 4-bit register for signal <tobus_tmp>.
Found 4-bit register for signal <frombus_tmp>.
Found 1-bit register for signal <p_tmp>.
Found 1-bit register for signal <flags<2>>.
Found 16-bit register for signal <lc>.
Found 8-bit register for signal <upc>.
Found 4-bit register for signal <alu_tmp>.
Found 8-bit adder for signal <upc[7]_GND_169_o_add_63_OUT> created at line 273.
Found 16-bit subtractor for signal <GND_169_o_GND_169_o_sub_9_OUT<15:0>> created at line 216.
Found 256x27-bit Read Only RAM for signal <n0068>
Found 16-bit comparator lessequal for signal <n0053> created at line 284
Summary:
inferred 1 RAM(s).
inferred 2 Adder/Subtractor(s).
inferred 38 D-type flip-flop(s).
inferred 1 Comparator(s).
inferred 20 Multiplexer(s).
Unit <upc> synthesized.
Synthesizing Unit <ir>.
Related source file is "/edu/tobhu543/TSEA83/projekt/CPU/ir.vhd".
Found 16-bit register for signal <val>.
Found 1-bit tristate buffer for signal <buss<15>> created at line 30
Found 1-bit tristate buffer for signal <buss<14>> created at line 30
Found 1-bit tristate buffer for signal <buss<13>> created at line 30
Found 1-bit tristate buffer for signal <buss<12>> created at line 30
Found 1-bit tristate buffer for signal <buss<11>> created at line 30
Found 1-bit tristate buffer for signal <buss<10>> created at line 30
Found 1-bit tristate buffer for signal <buss<9>> created at line 30
Found 1-bit tristate buffer for signal <buss<8>> created at line 30
Found 1-bit tristate buffer for signal <buss<7>> created at line 30
Found 1-bit tristate buffer for signal <buss<6>> created at line 30
Found 1-bit tristate buffer for signal <buss<5>> created at line 30
Found 1-bit tristate buffer for signal <buss<4>> created at line 30
Found 1-bit tristate buffer for signal <buss<3>> created at line 30
Found 1-bit tristate buffer for signal <buss<2>> created at line 30
Found 1-bit tristate buffer for signal <buss<1>> created at line 30
Found 1-bit tristate buffer for signal <buss<0>> created at line 30
Summary:
inferred 16 D-type flip-flop(s).
inferred 1 Multiplexer(s).
inferred 16 Tristate(s).
Unit <ir> synthesized.
Synthesizing Unit <asr>.
Related source file is "/edu/tobhu543/TSEA83/projekt/CPU/asr.vhd".
Found 12-bit register for signal <val>.
Found 1-bit tristate buffer for signal <buss<15>> created at line 27
Found 1-bit tristate buffer for signal <buss<14>> created at line 27
Found 1-bit tristate buffer for signal <buss<13>> created at line 27
Found 1-bit tristate buffer for signal <buss<12>> created at line 27
Found 1-bit tristate buffer for signal <buss<11>> created at line 27
Found 1-bit tristate buffer for signal <buss<10>> created at line 27
Found 1-bit tristate buffer for signal <buss<9>> created at line 27
Found 1-bit tristate buffer for signal <buss<8>> created at line 27
Found 1-bit tristate buffer for signal <buss<7>> created at line 27
Found 1-bit tristate buffer for signal <buss<6>> created at line 27
Found 1-bit tristate buffer for signal <buss<5>> created at line 27
Found 1-bit tristate buffer for signal <buss<4>> created at line 27
Found 1-bit tristate buffer for signal <buss<3>> created at line 27
Found 1-bit tristate buffer for signal <buss<2>> created at line 27
Found 1-bit tristate buffer for signal <buss<1>> created at line 27
Found 1-bit tristate buffer for signal <buss<0>> created at line 27
Summary:
inferred 12 D-type flip-flop(s).
inferred 16 Tristate(s).
Unit <asr> synthesized.
Synthesizing Unit <pc>.
Related source file is "/edu/tobhu543/TSEA83/projekt/CPU/pc.vhd".
Found 12-bit register for signal <val>.
Found 12-bit adder for signal <val[11]_GND_204_o_add_0_OUT> created at line 23.
Found 1-bit tristate buffer for signal <buss<15>> created at line 34
Found 1-bit tristate buffer for signal <buss<14>> created at line 34
Found 1-bit tristate buffer for signal <buss<13>> created at line 34
Found 1-bit tristate buffer for signal <buss<12>> created at line 34
Found 1-bit tristate buffer for signal <buss<11>> created at line 34
Found 1-bit tristate buffer for signal <buss<10>> created at line 34
Found 1-bit tristate buffer for signal <buss<9>> created at line 34
Found 1-bit tristate buffer for signal <buss<8>> created at line 34
Found 1-bit tristate buffer for signal <buss<7>> created at line 34
Found 1-bit tristate buffer for signal <buss<6>> created at line 34
Found 1-bit tristate buffer for signal <buss<5>> created at line 34
Found 1-bit tristate buffer for signal <buss<4>> created at line 34
Found 1-bit tristate buffer for signal <buss<3>> created at line 34
Found 1-bit tristate buffer for signal <buss<2>> created at line 34
Found 1-bit tristate buffer for signal <buss<1>> created at line 34
Found 1-bit tristate buffer for signal <buss<0>> created at line 34
Summary:
inferred 1 Adder/Subtractor(s).
inferred 12 D-type flip-flop(s).
inferred 1 Multiplexer(s).
inferred 16 Tristate(s).
Unit <pc> synthesized.
RTL-Simplification CPUSTAT: 0.17
RTL-BasicInf CPUSTAT: 0.30
RTL-BasicOpt CPUSTAT: 0.00
RTL-Remain-Bus CPUSTAT: 0.00
=========================================================================
HDL Synthesis Report
Macro Statistics
# RAMs : 6
16x7-bit single-port Read Only RAM : 1
256x27-bit single-port Read Only RAM : 1
4096x16-bit single-port RAM : 1
4x4-bit single-port Read Only RAM : 1
4x8-bit single-port Read Only RAM : 1
64x8-bit single-port Read Only RAM : 1
# Adders/Subtractors : 36
10-bit adder : 4
12-bit adder : 1
14-bit adder : 1
16-bit adder : 1
16-bit subtractor : 3
17-bit adder : 4
18-bit adder : 1
18-bit subtractor : 4
3-bit adder : 8
6-bit adder : 4
8-bit adder : 5
# Registers : 90
1-bit register : 19
10-bit register : 5
12-bit register : 2
14-bit register : 1
16-bit register : 28
18-bit register : 1
3-bit register : 8
32-bit register : 1
4-bit register : 9
6-bit register : 4
7-bit register : 1
8-bit register : 11
# Latches : 1
1-bit latch : 1
# Comparators : 24
16-bit comparator greater : 19
16-bit comparator lessequal : 1
3-bit comparator lessequal : 4
# Multiplexers : 181
1-bit 2-to-1 multiplexer : 119
1-bit 4-to-1 multiplexer : 4
10-bit 2-to-1 multiplexer : 4
12-bit 2-to-1 multiplexer : 1
14-bit 2-to-1 multiplexer : 2
16-bit 16-to-1 multiplexer : 2
16-bit 2-to-1 multiplexer : 26
32-bit 2-to-1 multiplexer : 1
4-bit 2-to-1 multiplexer : 4
8-bit 2-to-1 multiplexer : 18
# Tristates : 193
1-bit tristate buffer : 189
7-bit tristate buffer : 4
# Xors : 3
1-bit xor2 : 1
4-bit xor2 : 2
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Synthesizing (advanced) Unit <kr1>.
INFO:Xst:3031 - HDL ADVISOR - The RAM <Mram_output> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 64-word x 8-bit | |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <index> | |
| diA | connected to signal <GND> | |
| doA | connected to signal <output> | |
-----------------------------------------------------------------------
Unit <kr1> synthesized (advanced).
Synthesizing (advanced) Unit <kr2>.
INFO:Xst:3031 - HDL ADVISOR - The RAM <Mram_output> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 4-word x 8-bit | |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <index> | |
| diA | connected to signal <GND> | |
| doA | connected to signal <output> | |
-----------------------------------------------------------------------
Unit <kr2> synthesized (advanced).
Synthesizing (advanced) Unit <leddriver>.
The following registers are absorbed into counter <counter_r>: 1 register on signal <counter_r>.
INFO:Xst:3048 - The small RAM <Mram_v[3]_GND_62_o_wide_mux_3_OUT> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 16-word x 7-bit | |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <v> | |
| diA | connected to signal <GND> | |
| doA | connected to internal node | |
-----------------------------------------------------------------------
INFO:Xst:3048 - The small RAM <Mram_counter_r[17]_PWR_16_o_wide_mux_4_OUT> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 4-word x 4-bit | |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <counter_r> | |
| diA | connected to signal <GND> | |
| doA | connected to internal node | |
-----------------------------------------------------------------------
Unit <leddriver> synthesized (advanced).
Synthesizing (advanced) Unit <pc>.
The following registers are absorbed into counter <val>: 1 register on signal <val>.
Unit <pc> synthesized (advanced).
Synthesizing (advanced) Unit <pm>.
INFO:Xst:3040 - The RAM <Mram_pmem> will be implemented as a BLOCK RAM, absorbing the following register(s): <out_tmp>
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 4096-word x 16-bit | |
| mode | read-first | |
| clkA | connected to signal <clk> | rise |
| weA | connected to internal node | high |
| addrA | connected to signal <adr> | |
| diA | connected to signal <in_tmp> | |
| doA | connected to signal <out_tmp> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
Unit <pm> synthesized (advanced).
Synthesizing (advanced) Unit <spi>.
The following registers are absorbed into counter <count7bit>: 1 register on signal <count7bit>.
The following registers are absorbed into counter <count3bit>: 1 register on signal <count3bit>.
The following registers are absorbed into counter <count3bit2>: 1 register on signal <count3bit2>.
The following registers are absorbed into counter <count6bit>: 1 register on signal <count6bit>.
The following registers are absorbed into counter <count10bit>: 1 register on signal <count10bit>.
Unit <spi> synthesized (advanced).
Synthesizing (advanced) Unit <upc>.
The following registers are absorbed into counter <lc>: 1 register on signal <lc>.
INFO:Xst:3040 - The RAM <Mram_n0068> will be implemented as a BLOCK RAM, absorbing the following register(s): <upc>
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 256-word x 27-bit | |
| mode | write-first | |
| clkA | connected to signal <clk> | rise |
| enA | connected to internal node | low |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <upc[7]_upc[7]_mux_76_OUT> | |
| diA | connected to signal <GND> | |
| doA | connected to internal node | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
Unit <upc> synthesized (advanced).
WARNING:Xst:2677 - Node <breg_2> of sequential type is unconnected in block <spi>.
WARNING:Xst:2677 - Node <breg_3> of sequential type is unconnected in block <spi>.
WARNING:Xst:2677 - Node <breg_4> of sequential type is unconnected in block <spi>.
WARNING:Xst:2677 - Node <breg_5> of sequential type is unconnected in block <spi>.
WARNING:Xst:2677 - Node <breg_6> of sequential type is unconnected in block <spi>.
WARNING:Xst:2677 - Node <breg_7> of sequential type is unconnected in block <spi>.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# RAMs : 6
16x7-bit single-port distributed Read Only RAM : 1
256x27-bit single-port block Read Only RAM : 1
4096x16-bit single-port block RAM : 1
4x4-bit single-port distributed Read Only RAM : 1
4x8-bit single-port distributed Read Only RAM : 1
64x8-bit single-port distributed Read Only RAM : 1
# Adders/Subtractors : 13
14-bit adder : 1
16-bit adder : 1
16-bit subtractor : 2
17-bit adder : 4
17-bit subtractor : 4
8-bit adder : 1
# Counters : 23
10-bit up counter : 4
12-bit up counter : 1
16-bit down counter : 1
18-bit up counter : 1
3-bit up counter : 8
6-bit up counter : 4
8-bit up counter : 4
# Registers : 578
Flip-Flops : 578
# Comparators : 24
16-bit comparator greater : 19
16-bit comparator lessequal : 1
3-bit comparator lessequal : 4
# Multiplexers : 247
1-bit 16-to-1 multiplexer : 32
1-bit 2-to-1 multiplexer : 167
1-bit 4-to-1 multiplexer : 4
14-bit 2-to-1 multiplexer : 2
16-bit 2-to-1 multiplexer : 23
32-bit 2-to-1 multiplexer : 1
8-bit 2-to-1 multiplexer : 18
# Xors : 3
1-bit xor2 : 1
4-bit xor2 : 2
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:2677 - Node <yreg_0> of sequential type is unconnected in block <spi>.
WARNING:Xst:2677 - Node <yreg_1> of sequential type is unconnected in block <spi>.
WARNING:Xst:2677 - Node <yreg_2> of sequential type is unconnected in block <spi>.
WARNING:Xst:2677 - Node <yreg_3> of sequential type is unconnected in block <spi>.
WARNING:Xst:2677 - Node <yreg_4> of sequential type is unconnected in block <spi>.
WARNING:Xst:2677 - Node <yreg_5> of sequential type is unconnected in block <spi>.
WARNING:Xst:2677 - Node <yreg_6> of sequential type is unconnected in block <spi>.
WARNING:Xst:2677 - Node <yreg_7> of sequential type is unconnected in block <spi>.
WARNING:Xst:2677 - Node <xreg_0> of sequential type is unconnected in block <spi>.
WARNING:Xst:2677 - Node <xreg_1> of sequential type is unconnected in block <spi>.
WARNING:Xst:2677 - Node <xreg_2> of sequential type is unconnected in block <spi>.
WARNING:Xst:2677 - Node <xreg_3> of sequential type is unconnected in block <spi>.
WARNING:Xst:2677 - Node <xreg_4> of sequential type is unconnected in block <spi>.
WARNING:Xst:2677 - Node <xreg_5> of sequential type is unconnected in block <spi>.
WARNING:Xst:2677 - Node <xreg_6> of sequential type is unconnected in block <spi>.
WARNING:Xst:2677 - Node <xreg_7> of sequential type is unconnected in block <spi>.
WARNING:Xst:2042 - Unit UART: 16 internal tristates are replaced by logic (pull-up yes): dbus<0>, dbus<10>, dbus<11>, dbus<12>, dbus<13>, dbus<14>, dbus<15>, dbus<1>, dbus<2>, dbus<3>, dbus<4>, dbus<5>, dbus<6>, dbus<7>, dbus<8>, dbus<9>.
WARNING:Xst:2042 - Unit spimaster: 16 internal tristates are replaced by logic (pull-up yes): buss<0>, buss<10>, buss<11>, buss<12>, buss<13>, buss<14>, buss<15>, buss<1>, buss<2>, buss<3>, buss<4>, buss<5>, buss<6>, buss<7>, buss<8>, buss<9>.
WARNING:Xst:2042 - Unit pc: 16 internal tristates are replaced by logic (pull-up yes): buss<0>, buss<10>, buss<11>, buss<12>, buss<13>, buss<14>, buss<15>, buss<1>, buss<2>, buss<3>, buss<4>, buss<5>, buss<6>, buss<7>, buss<8>, buss<9>.
WARNING:Xst:2042 - Unit asr: 16 internal tristates are replaced by logic (pull-up yes): buss<0>, buss<10>, buss<11>, buss<12>, buss<13>, buss<14>, buss<15>, buss<1>, buss<2>, buss<3>, buss<4>, buss<5>, buss<6>, buss<7>, buss<8>, buss<9>.
WARNING:Xst:2042 - Unit ir: 16 internal tristates are replaced by logic (pull-up yes): buss<0>, buss<10>, buss<11>, buss<12>, buss<13>, buss<14>, buss<15>, buss<1>, buss<2>, buss<3>, buss<4>, buss<5>, buss<6>, buss<7>, buss<8>, buss<9>.
WARNING:Xst:2042 - Unit pm: 32 internal tristates are replaced by logic (pull-up yes): buss<0>, buss<10>, buss<11>, buss<12>, buss<13>, buss<14>, buss<15>, buss<1>, buss<2>, buss<3>, buss<4>, buss<5>, buss<6>, buss<7>, buss<8>, buss<9>, in_tmp<0>, in_tmp<10>, in_tmp<11>, in_tmp<12>, in_tmp<13>, in_tmp<14>, in_tmp<15>, in_tmp<1>, in_tmp<2>, in_tmp<3>, in_tmp<4>, in_tmp<5>, in_tmp<6>, in_tmp<7>, in_tmp<8>, in_tmp<9>.
WARNING:Xst:2042 - Unit alu: 18 internal tristates are replaced by logic (pull-up yes): buss<0>, buss<10>, buss<11>, buss<12>, buss<13>, buss<14>, buss<15>, buss<1>, buss<2>, buss<3>, buss<4>, buss<5>, buss<6>, buss<7>, buss<8>, buss<9>, flags<0>, flags<1>.
WARNING:Xst:2183 - Unit alu: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): flags<2>.
WARNING:Xst:2040 - Unit grx: 16 multi-source signals are replaced by logic (pull-up yes): buss<0>, buss<10>, buss<11>, buss<12>, buss<13>, buss<14>, buss<15>, buss<1>, buss<2>, buss<3>, buss<4>, buss<5>, buss<6>, buss<7>, buss<8>, buss<9>.
WARNING:Xst:2042 - Unit spi: 2 internal tristates are replaced by logic (pull-up yes): flags<0>, flags<1>.
WARNING:Xst:2183 - Unit spi: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): flags<2>, flags<3>, flags<4>, flags<5>, flags<6>.
WARNING:Xst:2677 - Node <uart_inst/uart_word_flipflop> of sequential type is unconnected in block <snake>.
Optimizing unit <snake> ...
Optimizing unit <shiftregi> ...
Optimizing unit <leddriver> ...
Optimizing unit <upc> ...
WARNING:Xst:2677 - Node <uart_inst/shiftreg/regi_0> of sequential type is unconnected in block <snake>.
Mapping all equations...
WARNING:Xst:2170 - Unit cpu_inst : the following signal(s) form a combinatorial loop: op<3>, snake/cpu_inst/xgrx/mux13_4_f7, kr1sig<0>, snake/dbus<13>, snake/cpu_inst/xgrx/mux4_4_f7, snake/dbus<13>LogicTrst1, snake/cpu_inst/xgrx/at[3]_gr[15][15]_wide_mux_51_OUT<13>, snake/cpu_inst/grat<1>, snake/cpu_inst/xgrx/at[3]_gr[15][15]_wide_mux_51_OUT<7>, snake/cpu_inst/xgrx/mux13_6, snake/dbus<7>, snake/cpu_inst/op<3>, snake/cpu_inst/xgrx/mux4_6, snake/dbus<7>LogicTrst2.
WARNING:Xst:2170 - Unit cpu_inst : the following signal(s) form a combinatorial loop: snake/cpu_inst/xgrx/at[3]_gr[15][15]_wide_mux_51_OUT<10>, snake/cpu_inst/xgrx/mux12_4_f7, op<0>, snake/dbus<10>, snake/cpu_inst/grat<0>, snake/cpu_inst/xgrx/mux1_4_f7, snake/cpu_inst/xgrx/mux12_6, snake/dbus<6>LogicTrst2, snake/cpu_inst/op<0>, snake/cpu_inst/xgrx/mux1_6, snake/dbus<6>, snake/dbus<10>LogicTrst2, kr1sig<1>, snake/cpu_inst/xgrx/at[3]_gr[15][15]_wide_mux_51_OUT<6>.
WARNING:Xst:2170 - Unit cpu_inst : the following signal(s) form a combinatorial loop: snake/cpu_inst/xgrx/at[3]_gr[15][15]_wide_mux_51_OUT<8>, snake/dbus<8>, op<4>, snake/cpu_inst/xgrx/mux5_4_f7, snake/dbus<14>LogicTrst1, snake/cpu_inst/op<4>, snake/dbus<8>LogicTrst2, kr1sig<2>, snake/cpu_inst/xgrx/at[3]_gr[15][15]_wide_mux_51_OUT<14>, snake/cpu_inst/grat<2>, snake/dbus<14>, snake/cpu_inst/xgrx/mux14_4_f7.
WARNING:Xst:2170 - Unit cpu_inst : the following signal(s) form a combinatorial loop: snake/dbus<12>LogicTrst1, snake/cpu_inst/xgrx/at[3]_gr[15][15]_wide_mux_51_OUT<12>, op<2>, snake/dbus<9>, snake/dbus<12>, snake/cpu_inst/op<2>, kr1sig<3>, snake/cpu_inst/xgrx/at[3]_gr[15][15]_wide_mux_51_OUT<9>, snake/dbus<9>LogicTrst2, snake/cpu_inst/grat<3>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 0) on block snake, actual ratio is 15.
FlipFlop cpu_inst/xir/val_0 has been replicated 1 time(s)
FlipFlop cpu_inst/xir/val_1 has been replicated 1 time(s)
FlipFlop cpu_inst/xir/val_2 has been replicated 1 time(s)
FlipFlop cpu_inst/xupc/tobus_tmp_0 has been replicated 1 time(s)
FlipFlop cpu_inst/xupc/tobus_tmp_1 has been replicated 2 time(s)
FlipFlop cpu_inst/xupc/tobus_tmp_2 has been replicated 2 time(s)
FlipFlop cpu_inst/xupc/tobus_tmp_3 has been replicated 2 time(s)
Final Macro Processing ...
Processing Unit <snake> :
Found 2-bit shift register for signal <spi_inst/SPIGEN[3].spi_inst/breg_1>.
Found 2-bit shift register for signal <spi_inst/SPIGEN[2].spi_inst/breg_1>.
Found 2-bit shift register for signal <spi_inst/SPIGEN[1].spi_inst/breg_1>.
Found 2-bit shift register for signal <spi_inst/SPIGEN[0].spi_inst/breg_1>.
Unit <snake> processed.
=========================================================================
Final Register Report
Macro Statistics
# Registers : 680
Flip-Flops : 680
# Shift Registers : 4
2-bit shift register : 4
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Top Level Output File Name : design.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 1679
# GND : 1
# INV : 15
# LUT1 : 98
# LUT2 : 41
# LUT3 : 51
# LUT4 : 114
# LUT5 : 217
# LUT6 : 591
# MUXCY : 278
# MUXF7 : 72
# MUXF8 : 32
# VCC : 1
# XORCY : 168
# FlipFlops/Latches : 685
# FD : 127
# FDE : 439
# FDR : 41
# FDRE : 77
# LD : 1
# RAMS : 5
# RAMB16BWER : 5
# Shift Registers : 4
# SRLC16E : 4
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 30
# IBUF : 6
# OBUF : 24
Device utilization summary:
---------------------------
Selected Device : 6slx16csg324-3
Slice Logic Utilization:
Number of Slice Registers: 685 out of 18224 3%
Number of Slice LUTs: 1131 out of 9112 12%
Number used as Logic: 1127 out of 9112 12%
Number used as Memory: 4 out of 2176 0%
Number used as SRL: 4
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 1425
Number with an unused Flip Flop: 740 out of 1425 51%
Number with an unused LUT: 294 out of 1425 20%
Number of fully used LUT-FF pairs: 391 out of 1425 27%
Number of unique control sets: 54
IO Utilization:
Number of IOs: 49
Number of bonded IOBs: 31 out of 232 13%
Specific Feature Utilization:
Number of Block RAM/FIFO: 5 out of 32 15%
Number using Block RAM only: 5
Number of BUFG/BUFGCTRLs: 1 out of 16 6%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------