Subsystem.vhd.bak

-- -------------------------------------------------------------
-- 
-- File Name: hdlsrc\top_sim_mod2_fixed_point_rev2\Subsystem.vhd
-- Created: 2017-12-09 20:43:07
-- 
-- Generated by MATLAB 9.3 and HDL Coder 3.11
-- 
-- 
-- -------------------------------------------------------------
-- Rate and Clocking Details
-- -------------------------------------------------------------
-- Model base rate: 8.13802e-06
-- Target subsystem base rate: 8.13802e-06
-- 
-- 
-- Clock Enable  Sample Time
-- -------------------------------------------------------------
-- ce_out        8.13802e-06
-- -------------------------------------------------------------
-- 
-- 
-- Output Signal                 Clock Enable  Sample Time
-- -------------------------------------------------------------
-- Modulator_Output              ce_out        8.13802e-06
-- -------------------------------------------------------------
-- 
-- -------------------------------------------------------------


-- -------------------------------------------------------------
-- 
-- Module: Subsystem
-- Source Path: top_sim_mod2_fixed_point_rev2/Subsystem
-- Hierarchy Level: 0
-- 
-- -------------------------------------------------------------
use work.cordic_types.all;
use work.dsm_pkg.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.fixed_pkg.all;

-- Realized with (c)MATLAB (R2017b)
-- From : Pavan, Shanthi, et al. Understanding Delta-Sigma Data Converters. Wiley, 2017.
-- Chapter 3 : Alternative Second-Order Modulator Structures
-- Page 80-81
-- Section 3.4.2 : The Silva Steensgaard Structure
-- Figure : 3.16
ENTITY  Silva_Steensgaard_Structure IS
  PORT( clk                               :   IN    std_logic;
        reset                             :   IN    std_logic;
        Baseband_signal                   :   IN    std_logic_vector(35 downto 0);
        Modulator_Output                  :   OUT   std_logic_vector(35 downto 0)
        );
END Silva_Steensgaard_Structure;


ARCHITECTURE rtl OF Silva_Steensgaard_Structure IS

	-- Component Declarations
	COMPONENT quantizer
	PORT(
		u :   IN    dsm_t;
		y :   OUT   dsm_t
	);
	END COMPONENT;

	-- Signals
	SIGNAL Digital_PCM_signal : dsm_t;
	SIGNAL Integrator_1 : dsm_t;
	SIGNAL Gain1_out1 : dsm_t;
	SIGNAL y : dsm_t;
	SIGNAL Sigma : dsm_t;
	SIGNAL Sum_out1 : dsm_t;
	SIGNAL Integrator_2 : dsm_t;
	SIGNAL Sum1_out1 : dsm_t;
	SIGNAL Add_out1 : dsm_t;
	SIGNAL Quant_in : dsm_t;

BEGIN

	U0: quantizer
		PORT MAP ( 
		u => Quant_in,
		y => y
	);
				  
  Digital_PCM_signal <= to_sfixed(Baseband_signal, Digital_PCM_signal);
  Gain1_out1 <= resize(shift_left(Integrator_1, 1), Digital_PCM_signal);
  Sigma <= resize(Digital_PCM_signal - y, Digital_PCM_signal);
  Sum_out1 <= resize(Sigma + Integrator_1, Digital_PCM_signal);
  Sum1_out1 <= resize(Integrator_1 + Integrator_2, Digital_PCM_signal);
  
  Delay1_process : PROCESS (clk, reset)
	BEGIN
		IF reset = '0' THEN
			Integrator_1 <= to_sfixed(0, Integrator_1);
			Integrator_2 <= to_sfixed(0, Integrator_2);
		ELSIF clk'EVENT AND clk = '1' THEN
			Integrator_1 <= Sum_out1;
			Integrator_2 <= Sum1_out1;
		END IF;
	END PROCESS Delay1_process;

  Add_out1 <= resize(Digital_PCM_signal + Integrator_2, Digital_PCM_signal);
  Quant_in <= resize(Add_out1 + Gain1_out1, Digital_PCM_signal);
  Modulator_Output <= to_slv(y);

END rtl;