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[WIP] Pull in global hsfll clock device driver #2300

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@bjarki-andreasen bjarki-andreasen commented Nov 26, 2024

Blocked until WiFi changes have been merged.

Code has been run locally, sample and tests passes. Validating that frequency indeed changes still needed.

Build the samples:

west build -p -b nrf54h20dk/nrf54h20/cpuapp zephyr/samples/boards/nordic/clock_control/ -T sample.boards.nrf.clock_control.global_hsfll

and

west build -p -b nrf54h20dk/nrf54h20/cpuapp zephyr/tests/drivers/clock_control/nrf_clock_control/

to test it locally.

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NordicBuilder commented Nov 26, 2024

The following west manifest projects have been modified in this Pull Request:

Name Old Revision New Revision Diff
hal_nordic zephyrproject-rtos/hal_nordic@54bde38 zephyrproject-rtos/hal_nordic#265 zephyrproject-rtos/hal_nordic#265/files

Note: This message is automatically posted and updated by the Manifest GitHub Action.

Comment on lines 86 to 89
config SOC_NRF54H20_GLOBAL_HSFLL_MIN_FREQ_HZ
int "Minimum global HSFLL clock frequency in Hertz"
range 64000000 320000000
default 320000000
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Having a range here is pretty pointless IMHO because the only allowed frequencies are: 64, 128, 256 and 320 MHz. Please change it into a choice of one of the allowed values.

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will do

krish2718 and others added 9 commits November 29, 2024 17:15
Pulls PR that removed nRF Wi-Fi.

Signed-off-by: Chaitanya Tata <[email protected]>
(cherry picked from commit e512151)
Update hal_nordic revision to include nrfs services:
- GDPWR
- GDFS

Signed-off-by: Bjarki Arge Andreasen <[email protected]>

Upstream PR #: 81735
nRFs exposes now all power domains, following their actual name in the
specification. Add support for all of them in the GPD service. Note that
this is a breaking change: running this code requires a new SCFW as IDs
have changed in nRFs and so SCFW.

Upstream PR #: 82216

Signed-off-by: Gerard Marull-Paretas <[email protected]>
Adding the implementation for the GDFS service

Upstream PR #: 81735

Signed-off-by: Paweł Pelikan <[email protected]>
Add specific device model for global hsfll clock and update dts tree
to use specific model. The clock is not fixed, and configurable at
runtime to predefined frequencies specified by the platform.

Upstream PR #: 81735

Signed-off-by: Bjarki Arge Andreasen <[email protected]>
…fsll clock

Add device driver support for global hsfll clock.

Upstream PR #: 81735

Signed-off-by: Bjarki Arge Andreasen <[email protected]>
… hsfll

Extend sample to support global hsfll clock control.

Upstream PR #: 81735

Signed-off-by: Bjarki Arge Andreasen <[email protected]>
…lock

Extend test suite to test global HSFLL clock.

Upstream PR #: 81735

Signed-off-by: Bjarki Arge Andreasen <[email protected]>
Introduce feature which restricts the minimum global hsfll
frequency. This feature is selected by default to preserve the
behavior of the global hsfll before the clock control driver for
it was introduced, which configured it as a fixed clock at 320MHz.

Upstream PR #: 81735

Signed-off-by: Bjarki Arge Andreasen <[email protected]>
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7 participants