From 1589d1b807a247bb874f5c2de073fb635215be59 Mon Sep 17 00:00:00 2001 From: Grzegorz Swiderski Date: Thu, 31 Oct 2024 11:54:12 +0100 Subject: [PATCH] [nrf fromlist] soc: nordic: dmm: Fix DMM_REG_ALIGN_SIZE macro when CONFIG_DCACHE=n Upstream PR #: 80676 Make sure this expansion doesn't include `CONFIG_DCACHE_LINE_SIZE`, which would be undefined and produce a build error. Signed-off-by: Grzegorz Swiderski (cherry picked from commit cf5405a59931a55b34ed7223ec82f30e3548f339) --- soc/nordic/common/dmm.h | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/soc/nordic/common/dmm.h b/soc/nordic/common/dmm.h index e92f01d07b8..34b517c92df 100644 --- a/soc/nordic/common/dmm.h +++ b/soc/nordic/common/dmm.h @@ -23,12 +23,13 @@ extern "C" { /** @cond INTERNAL_HIDDEN */ +#ifdef CONFIG_DCACHE + /* Determine if memory region is cacheable. */ -#define DMM_IS_REG_CACHEABLE(node_id) \ - COND_CODE_1(CONFIG_DCACHE, \ - (COND_CODE_1(DT_NODE_HAS_PROP(node_id, zephyr_memory_attr), \ - ((DT_PROP(node_id, zephyr_memory_attr) & DT_MEM_CACHEABLE)), \ - (0))), (0)) +#define DMM_IS_REG_CACHEABLE(node_id) \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, zephyr_memory_attr), \ + ((DT_PROP(node_id, zephyr_memory_attr) & DT_MEM_CACHEABLE)), \ + (0)) /* Determine required alignment of the data buffers in specified memory region. * Cache line alignment is required if region is cacheable and data cache is enabled. @@ -36,6 +37,13 @@ extern "C" { #define DMM_REG_ALIGN_SIZE(node_id) \ (DMM_IS_REG_CACHEABLE(node_id) ? CONFIG_DCACHE_LINE_SIZE : sizeof(uint8_t)) +#else + +#define DMM_IS_REG_CACHEABLE(node_id) 0 +#define DMM_REG_ALIGN_SIZE(node_id) (sizeof(uint8_t)) + +#endif /* CONFIG_DCACHE */ + /* Determine required alignment of the data buffers in memory region * associated with specified device node. */