From f052fa4e11cdb5283db21d278e09691c49f4c726 Mon Sep 17 00:00:00 2001 From: Hyeeun Lee Date: Mon, 2 Sep 2024 22:48:30 +0900 Subject: [PATCH] risc64: Add description for arch registers It'd be a lot easier to understand the assembly code by having description table for architecture registers. This patch adds the register table to mcount.S for RISC-V[1]. References: [1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/v1.0/riscv-cc.adoc#integer-register-convention Co-authored-by: Yunseong Kim Co-authored-by: Choi Wonsick Signed-off-by: Hyeeun Lee --- arch/riscv64/mcount.S | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/riscv64/mcount.S b/arch/riscv64/mcount.S index e5fc30479..80c7bd6c4 100644 --- a/arch/riscv64/mcount.S +++ b/arch/riscv64/mcount.S @@ -1,5 +1,21 @@ #include "utils/asm.h" +/* + * RISC-V Integer Register Convention + * + * | Name | ABI Mnemonic | Meaning | Preserved across calls? + * | x0 | zero | Zero | -- (Immutable) + * | x1 | ra | Return address | No + * | x2 | sp | Stack pointer | Yes + * | x3 | gp | Global pointer | -- (Unallocatable) + * | x4 | tp | Thread pointer | -- (Unallocatable) + * | x5 - x7 | t0 - t2 | Temporary registers | No + * | x8 - x9 | s0 - s1 | Callee-saved registers | Yes + * | x10 - x17 | a0 - a7 | Argument registers | No + * | x18 - x27 | s2 - s11 | Callee-saved registers | Yes + * | x28 - x31 | t3 - t6 | Temporary registers | No + */ + .text GLOBAL(_mcount)