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mlme.c
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/*
*************************************************************************
* Ralink Tech Inc.
* 5F., No.36, Taiyuan St., Jhubei City,
* Hsinchu County 302,
* Taiwan, R.O.C.
*
* (c) Copyright 2002-2010, Ralink Technology, Inc.
*
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
* *
*************************************************************************/
#include "rt_config.h"
#include <stdarg.h>
UCHAR CISCO_OUI[] = {0x00, 0x40, 0x96};
UCHAR RALINK_OUI[] = {0x00, 0x0c, 0x43};
UCHAR WPA_OUI[] = {0x00, 0x50, 0xf2, 0x01};
UCHAR RSN_OUI[] = {0x00, 0x0f, 0xac};
UCHAR WAPI_OUI[] = {0x00, 0x14, 0x72};
UCHAR WME_INFO_ELEM[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01};
UCHAR WME_PARM_ELEM[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01};
UCHAR BROADCOM_OUI[] = {0x00, 0x90, 0x4c};
UCHAR WPS_OUI[] = {0x00, 0x50, 0xf2, 0x04};
#ifdef CONFIG_STA_SUPPORT
#ifdef DOT11_N_SUPPORT
UCHAR PRE_N_HT_OUI[] = {0x00, 0x90, 0x4c};
#endif // DOT11_N_SUPPORT //
#endif // CONFIG_STA_SUPPORT //
UCHAR RateSwitchTable[] = {
// Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF)
0x11, 0x00, 0, 0, 0, // Initial used item after association
0x00, 0x00, 0, 40, 101,
0x01, 0x00, 1, 40, 50,
0x02, 0x00, 2, 35, 45,
0x03, 0x00, 3, 20, 45,
0x04, 0x21, 0, 30, 50,
0x05, 0x21, 1, 20, 50,
0x06, 0x21, 2, 20, 50,
0x07, 0x21, 3, 15, 50,
0x08, 0x21, 4, 15, 30,
0x09, 0x21, 5, 10, 25,
0x0a, 0x21, 6, 8, 25,
0x0b, 0x21, 7, 8, 25,
0x0c, 0x20, 12, 15, 30,
0x0d, 0x20, 13, 8, 20,
0x0e, 0x20, 14, 8, 20,
0x0f, 0x20, 15, 8, 25,
0x10, 0x22, 15, 8, 25,
0x11, 0x00, 0, 0, 0,
0x12, 0x00, 0, 0, 0,
0x13, 0x00, 0, 0, 0,
0x14, 0x00, 0, 0, 0,
0x15, 0x00, 0, 0, 0,
0x16, 0x00, 0, 0, 0,
0x17, 0x00, 0, 0, 0,
0x18, 0x00, 0, 0, 0,
0x19, 0x00, 0, 0, 0,
0x1a, 0x00, 0, 0, 0,
0x1b, 0x00, 0, 0, 0,
0x1c, 0x00, 0, 0, 0,
0x1d, 0x00, 0, 0, 0,
0x1e, 0x00, 0, 0, 0,
0x1f, 0x00, 0, 0, 0,
};
UCHAR RateSwitchTable11B[] = {
// Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF)
0x04, 0x03, 0, 0, 0, // Initial used item after association
0x00, 0x00, 0, 40, 101,
0x01, 0x00, 1, 40, 50,
0x02, 0x00, 2, 35, 45,
0x03, 0x00, 3, 20, 45,
};
UCHAR RateSwitchTable11BG[] = {
// Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF)
0x0a, 0x00, 0, 0, 0, // Initial used item after association
0x00, 0x00, 0, 40, 101,
0x01, 0x00, 1, 40, 50,
0x02, 0x00, 2, 35, 45,
0x03, 0x00, 3, 20, 45,
0x04, 0x10, 2, 20, 35,
0x05, 0x10, 3, 16, 35,
0x06, 0x10, 4, 10, 25,
0x07, 0x10, 5, 16, 25,
0x08, 0x10, 6, 10, 25,
0x09, 0x10, 7, 10, 13,
};
UCHAR RateSwitchTable11G[] = {
// Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF)
0x08, 0x00, 0, 0, 0, // Initial used item after association
0x00, 0x10, 0, 20, 101,
0x01, 0x10, 1, 20, 35,
0x02, 0x10, 2, 20, 35,
0x03, 0x10, 3, 16, 35,
0x04, 0x10, 4, 10, 25,
0x05, 0x10, 5, 16, 25,
0x06, 0x10, 6, 10, 25,
0x07, 0x10, 7, 10, 13,
};
#ifdef DOT11_N_SUPPORT
UCHAR RateSwitchTable11N1S[] = {
// Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF)
0x0c, 0x0a, 0, 0, 0, // Initial used item after association
0x00, 0x00, 0, 40, 101,
0x01, 0x00, 1, 40, 50,
0x02, 0x00, 2, 25, 45,
0x03, 0x21, 0, 20, 35,
0x04, 0x21, 1, 20, 35,
0x05, 0x21, 2, 20, 35,
0x06, 0x21, 3, 15, 35,
0x07, 0x21, 4, 15, 30,
0x08, 0x21, 5, 10, 25,
0x09, 0x21, 6, 8, 14,
0x0a, 0x21, 7, 8, 14,
0x0b, 0x23, 7, 8, 14,
};
UCHAR RateSwitchTable11N2S[] = {
// Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF)
0x0e, 0x0c, 0, 0, 0, // Initial used item after association
0x00, 0x00, 0, 40, 101,
0x01, 0x00, 1, 40, 50,
0x02, 0x00, 2, 25, 45,
0x03, 0x21, 0, 20, 35,
0x04, 0x21, 1, 20, 35,
0x05, 0x21, 2, 20, 35,
0x06, 0x21, 3, 15, 35,
0x07, 0x21, 4, 15, 30,
0x08, 0x20, 11, 15, 30,
0x09, 0x20, 12, 15, 30,
0x0a, 0x20, 13, 8, 20,
0x0b, 0x20, 14, 8, 20,
0x0c, 0x20, 15, 8, 25,
0x0d, 0x22, 15, 8, 15,
};
#ifdef NEW_RATE_ADAPT_SUPPORT
// 3x3 rate switch table for new rate adaption (default: for good siganl environment (RSSI > -65))
// Target: Good throughput
UCHAR RateSwitchTable11N3S[] = {
// item no. mcs highPERThrd upMcs3 upMcs1 // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF)
// mode lowPERThrd downMcs upMcs2
0x19, 0x18, 0, 0, 0, 0, 0, 0, 0, 0,// Initial used item after association: the number of rate indexes, the initial mcs
0x00, 0x21, 0, 30, 101, 0, 16, 8, 1, 7,//mcs0
0x01, 0x21, 1, 20, 50, 0, 16, 9, 2, 13,//mcs1
0x02, 0x21, 2, 20, 50, 1, 17, 9, 3, 20,//mcs2
0x03, 0x21, 3, 15, 50, 2, 17, 10, 4, 26,//mcs3
0x04, 0x21, 4, 15, 30, 3, 18, 11, 5, 39,//mcs4
0x05, 0x21, 5, 10, 25, 4, 18, 12, 6, 52,//mcs5
0x06, 0x21, 6, 8, 14, 5, 19, 12, 7, 59,//mcs6
0x07, 0x21, 7, 8, 14, 6, 19, 12, 7, 65,//mcs7
0x08, 0x20, 8, 30, 50, 0, 16, 9, 2, 13,//mcs8
0x09, 0x20, 9, 20, 50, 8, 17, 10, 4, 26,//mcs9
0x0a, 0x20, 10, 20, 50, 9, 18, 11, 5, 39,//mcs10
0x0b, 0x20, 11, 15, 30, 10, 18, 12, 6, 52,//mcs11
0x0c, 0x20, 12, 15, 30, 11, 20, 13, 12, 78,//mcs12
0x0d, 0x20, 13, 8, 20, 12, 20, 14, 13, 104,//mcs13
0x0e, 0x20, 14, 8, 18, 13, 21, 15, 14, 117,//mcs14
0x0f, 0x20, 15, 8, 14, 14, 21, 15, 15, 130,//mcs15
0x10, 0x20, 16, 30, 50, 8, 17, 9, 3, 20,//mcs16
0x11, 0x20, 17, 20, 50, 16, 18, 11, 5, 39,//mcs17
0x12, 0x20, 18, 20, 50, 17, 19, 12, 7, 59,//mcs18
0x13, 0x20, 19, 15, 30, 18, 20, 13, 19, 78,//mcs19
0x14, 0x20, 20, 15, 30, 19, 21, 15, 20, 117,//mcs20
0x15, 0x20, 21, 8, 20, 20, 22, 21, 21, 156,//mcs21
0x16, 0x20, 22, 8, 20, 21, 23, 22, 22, 176,//mcs22
0x17, 0x20, 23, 6, 18, 22, 24, 23, 23, 196,//mcs23
0x18, 0x22, 23, 6, 14, 23, 24, 24, 24, 217,//mcs23+shortGI
};
#else
UCHAR RateSwitchTable11N3S[] = {
// Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF)
0x11, 0x0c, 0, 0, 0, // Initial used item after association
0x00, 0x00, 0, 40, 101,
0x01, 0x00, 1, 40, 50,
0x02, 0x00, 2, 25, 45,
0x03, 0x21, 0, 20, 35,
0x04, 0x21, 1, 20, 35,
0x05, 0x21, 2, 20, 35,
0x06, 0x21, 3, 15, 35,
0x07, 0x21, 4, 15, 30,
0x08, 0x20, 11, 15, 30,
0x09, 0x20, 12, 15, 22,
0x0a, 0x20, 13, 8, 20,
0x0b, 0x20, 14, 8, 20,
0x0c, 0x20, 20, 8, 20,
0x0d, 0x20, 21, 8, 20,
0x0e, 0x20, 22, 8, 20,
0x0f, 0x20, 23, 8, 20,
0x10, 0x22, 23, 8, 15,
};
#endif // NEW_RATE_ADAPT_SUPPORT //
// SYNC with Rory!! In order to solve the issue that the throughput drop dramatically at middle-long rage!!
// 3x3 rate switch table for new rate adaption (replacement: for bad siganl environment (RSSI < -65))
// Target: Good sensibility
UCHAR RateSwitchTable11N3SReplacement[] = {
// item no. mcs highPERThrd upMcs3 upMcs1 // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF)
// mode lowPERThrd downMcs upMcs2
0x19, 0x18, 0, 0, 0, 0, 0, 0, 0, 0, // Initial used item after association: the number of rate indexes, the initial mcs
0x00, 0x21, 0, 30, 101, 0, 16, 8, 1, 7, // MCS 0
0x01, 0x21, 1, 20, 50, 0, 16, 9, 2, 13, // MCS 1
0x02, 0x21, 2, 20, 50, 1, 17, 9, 3, 20, // MCS 2
0x03, 0x21, 3, 15, 50, 2, 17, 10, 4, 26, // MCS 3
0x04, 0x21, 4, 15, 30, 3, 18, 11, 5, 39, // MCS 4
0x05, 0x21, 5, 10, 25, 4, 18, 12, 6, 52, // MCS 5
0x06, 0x21, 6, 8, 14, 5, 19, 12, 7, 59, // MCS 6
0x07, 0x21, 7, 8, 14, 6, 19, 12, 7, 65, // MCS 7
0x08, 0x20, 8, 30, 50, 0, 16, 9, 8, 13, // MCS 8
0x09, 0x20, 9, 20, 50, 8, 17, 10, 9, 26, // MCS 9
0x0a, 0x20, 10, 20, 50, 9, 18, 11, 10, 39, // MCS 10
0x0b, 0x20, 11, 15, 30, 10, 18, 12, 11, 52, // MCS 11
0x0c, 0x20, 12, 15, 30, 11, 20, 13, 12, 78, // MCS 12
0x0d, 0x20, 13, 8, 20, 12, 20, 14, 13, 104, // MCS 13
0x0e, 0x20, 14, 8, 18, 13, 21, 15, 14, 117, // MCS 14
0x0f, 0x20, 15, 8, 14, 14, 21, 15, 15, 130, // MCS 15
0x10, 0x20, 16, 30, 50, 8, 17, 16, 16, 20, // MCS 16
0x11, 0x20, 17, 20, 50, 16, 18, 17, 17, 39, // MCS 17
0x12, 0x20, 18, 20, 50, 17, 19, 18, 18, 59, // MCS 18
0x13, 0x20, 19, 15, 30, 18, 20, 19, 19, 78, // MCS 19
0x14, 0x20, 20, 15, 30, 19, 21, 20, 20, 117, // MCS 20
0x15, 0x20, 21, 8, 20, 20, 22, 21, 21, 156, // MCS 21
0x16, 0x20, 22, 8, 20, 21, 23, 22, 22, 176, // MCS 22
0x17, 0x20, 23, 6, 18, 22, 24, 23, 23, 196, // MCS 23
0x18, 0x22, 23, 6, 14, 23, 24, 24, 24, 217, // MCS 23 + Short GI
};
UCHAR RateSwitchTable11N2SForABand[] = {
// Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF)
0x0b, 0x09, 0, 0, 0, // Initial used item after association
0x00, 0x21, 0, 30, 101,
0x01, 0x21, 1, 20, 50,
0x02, 0x21, 2, 20, 50,
0x03, 0x21, 3, 15, 50,
0x04, 0x21, 4, 15, 30,
0x05, 0x21, 5, 15, 30,
0x06, 0x20, 12, 15, 30,
0x07, 0x20, 13, 8, 20,
0x08, 0x20, 14, 8, 20,
0x09, 0x20, 15, 8, 25,
0x0a, 0x22, 15, 8, 25,
};
UCHAR RateSwitchTable11N3SForABand[] = { // 3*3
// Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF)
0x0e, 0x09, 0, 0, 0, // Initial used item after association
0x00, 0x21, 0, 30, 101,
0x01, 0x21, 1, 20, 50,
0x02, 0x21, 2, 20, 50,
0x03, 0x21, 3, 15, 50,
0x04, 0x21, 4, 15, 30,
0x05, 0x21, 5, 15, 30,
0x06, 0x20, 12, 15, 30,
0x07, 0x20, 13, 8, 20,
0x08, 0x20, 14, 8, 20,
0x09, 0x20, 15, 8, 25,
//0x0a, 0x22, 15, 8, 25,
//0x0a, 0x20, 20, 15, 30,
0x0a, 0x20, 21, 8, 20,
0x0b, 0x20, 22, 8, 20,
0x0c, 0x20, 23, 8, 25,
0x0d, 0x22, 23, 8, 25,
};
UCHAR RateSwitchTable11BGN1S[] = {
// Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF)
0x0c, 0x0a, 0, 0, 0, // Initial used item after association
0x00, 0x00, 0, 40, 101,
0x01, 0x00, 1, 40, 50,
0x02, 0x00, 2, 25, 45,
0x03, 0x21, 0, 20, 35,
0x04, 0x21, 1, 20, 35,
0x05, 0x21, 2, 20, 35,
0x06, 0x21, 3, 15, 35,
0x07, 0x21, 4, 15, 30,
0x08, 0x21, 5, 10, 25,
0x09, 0x21, 6, 8, 14,
0x0a, 0x21, 7, 8, 14,
0x0b, 0x23, 7, 8, 14,
};
UCHAR RateSwitchTable11BGN2S[] = {
// Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF)
0x0e, 0x0c, 0, 0, 0, // Initial used item after association
0x00, 0x00, 0, 40, 101,
0x01, 0x00, 1, 40, 50,
0x02, 0x00, 2, 25, 45,
0x03, 0x21, 0, 20, 35,
0x04, 0x21, 1, 20, 35,
0x05, 0x21, 2, 20, 35,
0x06, 0x21, 3, 15, 35,
0x07, 0x21, 4, 15, 30,
0x08, 0x20, 11, 15, 30,
0x09, 0x20, 12, 15, 22,
0x0a, 0x20, 13, 8, 20,
0x0b, 0x20, 14, 8, 20,
0x0c, 0x20, 15, 8, 20,
0x0d, 0x22, 15, 8, 15,
};
UCHAR RateSwitchTable11BGN3S[] = { // 3*3
// Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF)
0x0e, 0x00, 0, 0, 0, // Initial used item after association
0x00, 0x21, 0, 30,101, //50
0x01, 0x21, 1, 20, 50,
0x02, 0x21, 2, 20, 50,
0x03, 0x21, 3, 20, 50,
0x04, 0x21, 4, 15, 50,
0x05, 0x20, 11, 15, 30,
0x06, 0x20, 12, 15, 30,
0x07, 0x20, 13, 8, 20,
0x08, 0x20, 14, 8, 20,
0x09, 0x20, 15, 8, 25,
//0x0a, 0x20, 20, 15, 30,
0x0a, 0x20, 21, 8, 20,
0x0b, 0x20, 22, 8, 20,
0x0c, 0x20, 23, 8, 25,
0x0d, 0x22, 23, 8, 25,
};
UCHAR RateSwitchTable11BGN2SForABand[] = {
// Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF)
0x0b, 0x09, 0, 0, 0, // Initial used item after association
0x00, 0x21, 0, 30,101, //50
0x01, 0x21, 1, 20, 50,
0x02, 0x21, 2, 20, 50,
0x03, 0x21, 3, 15, 50,
0x04, 0x21, 4, 15, 30,
0x05, 0x21, 5, 15, 30,
0x06, 0x20, 12, 15, 30,
0x07, 0x20, 13, 8, 20,
0x08, 0x20, 14, 8, 20,
0x09, 0x20, 15, 8, 25,
0x0a, 0x22, 15, 8, 25,
};
UCHAR RateSwitchTable11BGN3SForABand[] = { // 3*3
// Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF)
0x0e, 0x09, 0, 0, 0, // Initial used item after association
0x00, 0x21, 0, 30,101, //50
0x01, 0x21, 1, 20, 50,
0x02, 0x21, 2, 20, 50,
0x03, 0x21, 3, 15, 50,
0x04, 0x21, 4, 15, 30,
0x05, 0x21, 5, 15, 30,
0x06, 0x20, 12, 15, 30,
0x07, 0x20, 13, 8, 20,
0x08, 0x20, 14, 8, 20,
0x09, 0x20, 15, 8, 25,
//0x0a, 0x22, 15, 8, 25,
//0x0a, 0x20, 20, 15, 30,
0x0a, 0x20, 21, 8, 20,
0x0b, 0x20, 22, 8, 20,
0x0c, 0x20, 23, 8, 25,
0x0d, 0x22, 23, 8, 25,
};
#endif // DOT11_N_SUPPORT //
extern UCHAR OfdmRateToRxwiMCS[];
// since RT61 has better RX sensibility, we have to limit TX ACK rate not to exceed our normal data TX rate.
// otherwise the WLAN peer may not be able to receive the ACK thus downgrade its data TX rate
ULONG BasicRateMask[12] = {0xfffff001 /* 1-Mbps */, 0xfffff003 /* 2 Mbps */, 0xfffff007 /* 5.5 */, 0xfffff00f /* 11 */,
0xfffff01f /* 6 */ , 0xfffff03f /* 9 */ , 0xfffff07f /* 12 */ , 0xfffff0ff /* 18 */,
0xfffff1ff /* 24 */ , 0xfffff3ff /* 36 */ , 0xfffff7ff /* 48 */ , 0xffffffff /* 54 */};
UCHAR BROADCAST_ADDR[MAC_ADDR_LEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
UCHAR ZERO_MAC_ADDR[MAC_ADDR_LEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
// e.g. RssiSafeLevelForTxRate[RATE_36]" means if the current RSSI is greater than
// this value, then it's quaranteed capable of operating in 36 mbps TX rate in
// clean environment.
// TxRate: 1 2 5.5 11 6 9 12 18 24 36 48 54 72 100
CHAR RssiSafeLevelForTxRate[] ={ -92, -91, -90, -87, -88, -86, -85, -83, -81, -78, -72, -71, -40, -40 };
UCHAR RateIdToMbps[] = { 1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54, 72, 100};
USHORT RateIdTo500Kbps[] = { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108, 144, 200};
UCHAR SsidIe = IE_SSID;
UCHAR SupRateIe = IE_SUPP_RATES;
UCHAR ExtRateIe = IE_EXT_SUPP_RATES;
#ifdef DOT11_N_SUPPORT
UCHAR HtCapIe = IE_HT_CAP;
UCHAR AddHtInfoIe = IE_ADD_HT;
UCHAR NewExtChanIe = IE_SECONDARY_CH_OFFSET;
UCHAR BssCoexistIe = IE_2040_BSS_COEXIST;
UCHAR ExtHtCapIe = IE_EXT_CAPABILITY;
#endif // DOT11_N_SUPPORT //
UCHAR ExtCapIe = IE_EXT_CAPABILITY;
UCHAR ErpIe = IE_ERP;
UCHAR DsIe = IE_DS_PARM;
UCHAR TimIe = IE_TIM;
UCHAR WpaIe = IE_WPA;
UCHAR Wpa2Ie = IE_WPA2;
UCHAR IbssIe = IE_IBSS_PARM;
UCHAR WapiIe = IE_WAPI;
extern UCHAR WPA_OUI[];
UCHAR SES_OUI[] = {0x00, 0x90, 0x4c};
UCHAR ZeroSsid[32] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
#ifdef INF_AMAZON_SE
UINT16 MaxBulkOutsSizeLimit[5][4] =
{
// Priority high -> low
{ 24576, 2048, 2048, 2048 }, // 0 AC
{ 24576, 2048, 2048, 2048 }, // 1 AC
{ 24576, 2048, 2048, 2048 }, // 2 ACs
{ 24576, 6144, 2048, 2048 }, // 3 ACs
{ 24576, 6144, 4096, 2048 } // 4 ACs
};
VOID SoftwareFlowControl(
IN PRTMP_ADAPTER pAd)
{
BOOLEAN ResetBulkOutSize=FALSE;
UCHAR i=0,RunningQueueNo=0,QueIdx=0,HighWorkingAcCount=0;
UINT PacketsInQueueSize=0;
UCHAR Priority[]={1,0,2,3};
for (i=0;i<NUM_OF_TX_RING;i++)
{
if (pAd->TxContext[i].CurWritePosition>=pAd->TxContext[i].NextBulkOutPosition)
{
PacketsInQueueSize=pAd->TxContext[i].CurWritePosition-pAd->TxContext[i].NextBulkOutPosition;
}
else
{
PacketsInQueueSize=MAX_TXBULK_SIZE-pAd->TxContext[i].NextBulkOutPosition+pAd->TxContext[i].CurWritePosition;
}
if (pAd->BulkOutDataSizeCount[i]>20480 || PacketsInQueueSize>6144)
{
RunningQueueNo++;
pAd->BulkOutDataFlag[i]=TRUE;
}
else
pAd->BulkOutDataFlag[i]=FALSE;
pAd->BulkOutDataSizeCount[i]=0;
}
if (RunningQueueNo>pAd->LastRunningQueueNo)
{
DBGPRINT(RT_DEBUG_INFO,("SoftwareFlowControl reset %d > %d \n",RunningQueueNo,pAd->LastRunningQueueNo));
ResetBulkOutSize=TRUE;
pAd->RunningQueueNoCount=0;
pAd->LastRunningQueueNo=RunningQueueNo;
}
else if (RunningQueueNo==pAd->LastRunningQueueNo)
{
pAd->RunningQueueNoCount=0;
}
else if (RunningQueueNo<pAd->LastRunningQueueNo)
{
DBGPRINT(RT_DEBUG_INFO,("SoftwareFlowControl reset %d < %d \n",RunningQueueNo,pAd->LastRunningQueueNo));
pAd->RunningQueueNoCount++;
if (pAd->RunningQueueNoCount>=6)
{
ResetBulkOutSize=TRUE;
pAd->RunningQueueNoCount=0;
pAd->LastRunningQueueNo=RunningQueueNo;
}
}
if (ResetBulkOutSize==TRUE)
{
for (QueIdx=0;QueIdx<NUM_OF_TX_RING;QueIdx++)
{
HighWorkingAcCount=0;
for (i=0;i<NUM_OF_TX_RING;i++)
{
if (QueIdx==i)
continue;
if (pAd->BulkOutDataFlag[i]==TRUE && Priority[i]>Priority[QueIdx])
HighWorkingAcCount++;
}
pAd->BulkOutDataSizeLimit[QueIdx]=MaxBulkOutsSizeLimit[RunningQueueNo][HighWorkingAcCount];
}
DBGPRINT(RT_DEBUG_TRACE, ("Reset bulkout size AC0(BE):%7d AC1(BK):%7d AC2(VI):%7d AC3(VO):%7d %d\n",pAd->BulkOutDataSizeLimit[0]
,pAd->BulkOutDataSizeLimit[1]
,pAd->BulkOutDataSizeLimit[2]
,pAd->BulkOutDataSizeLimit[3]
,RunningQueueNo));
}
}
#endif // INF_AMAZON_SE //
/*
==========================================================================
Description:
initialize the MLME task and its data structure (queue, spinlock,
timer, state machines).
IRQL = PASSIVE_LEVEL
Return:
always return NDIS_STATUS_SUCCESS
==========================================================================
*/
NDIS_STATUS MlmeInit(
IN PRTMP_ADAPTER pAd)
{
NDIS_STATUS Status = NDIS_STATUS_SUCCESS;
DBGPRINT(RT_DEBUG_TRACE, ("--> MLME Initialize\n"));
do
{
Status = MlmeQueueInit(&pAd->Mlme.Queue);
if(Status != NDIS_STATUS_SUCCESS)
break;
pAd->Mlme.bRunning = FALSE;
NdisAllocateSpinLock(&pAd->Mlme.TaskLock);
#ifdef CONFIG_STA_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_STA(pAd)
{
BssTableInit(&pAd->ScanTab);
// init STA state machines
AssocStateMachineInit(pAd, &pAd->Mlme.AssocMachine, pAd->Mlme.AssocFunc);
AuthStateMachineInit(pAd, &pAd->Mlme.AuthMachine, pAd->Mlme.AuthFunc);
AuthRspStateMachineInit(pAd, &pAd->Mlme.AuthRspMachine, pAd->Mlme.AuthRspFunc);
SyncStateMachineInit(pAd, &pAd->Mlme.SyncMachine, pAd->Mlme.SyncFunc);
#ifdef QOS_DLS_SUPPORT
DlsStateMachineInit(pAd, &pAd->Mlme.DlsMachine, pAd->Mlme.DlsFunc);
#endif // QOS_DLS_SUPPORT //
// Since we are using switch/case to implement it, the init is different from the above
// state machine init
MlmeCntlInit(pAd, &pAd->Mlme.CntlMachine, NULL);
#ifdef PCIE_PS_SUPPORT
if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE))
{
// only PCIe cards need these two timers
RTMPInitTimer(pAd, &pAd->Mlme.PsPollTimer, GET_TIMER_FUNCTION(PsPollWakeExec), pAd, FALSE);
RTMPInitTimer(pAd, &pAd->Mlme.RadioOnOffTimer, GET_TIMER_FUNCTION(RadioOnExec), pAd, FALSE);
}
#endif // PCIE_PS_SUPPORT //
RTMPInitTimer(pAd, &pAd->Mlme.LinkDownTimer, GET_TIMER_FUNCTION(LinkDownExec), pAd, FALSE);
RTMPInitTimer(pAd, &pAd->StaCfg.StaQuickResponeForRateUpTimer, GET_TIMER_FUNCTION(StaQuickResponeForRateUpExec), pAd, FALSE);
pAd->StaCfg.StaQuickResponeForRateUpTimerRunning = FALSE;
RTMPInitTimer(pAd, &pAd->StaCfg.WpaDisassocAndBlockAssocTimer, GET_TIMER_FUNCTION(WpaDisassocApAndBlockAssoc), pAd, FALSE);
}
#endif // CONFIG_STA_SUPPORT //
WpaStateMachineInit(pAd, &pAd->Mlme.WpaMachine, pAd->Mlme.WpaFunc);
ActionStateMachineInit(pAd, &pAd->Mlme.ActMachine, pAd->Mlme.ActFunc);
// Init mlme periodic timer
RTMPInitTimer(pAd, &pAd->Mlme.PeriodicTimer, GET_TIMER_FUNCTION(MlmePeriodicExec), pAd, TRUE);
// Set mlme periodic timer
RTMPSetTimer(&pAd->Mlme.PeriodicTimer, MLME_TASK_EXEC_INTV);
// software-based RX Antenna diversity
RTMPInitTimer(pAd, &pAd->Mlme.RxAntEvalTimer, GET_TIMER_FUNCTION(AsicRxAntEvalTimeout), pAd, FALSE);
} while (FALSE);
DBGPRINT(RT_DEBUG_TRACE, ("<-- MLME Initialize\n"));
return Status;
}
/*
==========================================================================
Description:
main loop of the MLME
Pre:
Mlme has to be initialized, and there are something inside the queue
Note:
This function is invoked from MPSetInformation and MPReceive;
This task guarantee only one MlmeHandler will run.
IRQL = DISPATCH_LEVEL
==========================================================================
*/
VOID MlmeHandler(
IN PRTMP_ADAPTER pAd)
{
MLME_QUEUE_ELEM *Elem = NULL;
// Only accept MLME and Frame from peer side, no other (control/data) frame should
// get into this state machine
NdisAcquireSpinLock(&pAd->Mlme.TaskLock);
if(pAd->Mlme.bRunning)
{
NdisReleaseSpinLock(&pAd->Mlme.TaskLock);
return;
}
else
{
pAd->Mlme.bRunning = TRUE;
}
NdisReleaseSpinLock(&pAd->Mlme.TaskLock);
while (!MlmeQueueEmpty(&pAd->Mlme.Queue))
{
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_MLME_RESET_IN_PROGRESS) ||
RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS) ||
RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))
{
DBGPRINT(RT_DEBUG_TRACE, ("Device Halted or Removed or MlmeRest, exit MlmeHandler! (queue num = %ld)\n", pAd->Mlme.Queue.Num));
break;
}
#ifdef RALINK_ATE
if(ATE_ON(pAd))
{
DBGPRINT(RT_DEBUG_TRACE, ("The driver is in ATE mode now in MlmeHandler\n"));
break;
}
#endif // RALINK_ATE //
//From message type, determine which state machine I should drive
if (MlmeDequeue(&pAd->Mlme.Queue, &Elem))
{
// if dequeue success
switch (Elem->Machine)
{
// STA state machines
#ifdef CONFIG_STA_SUPPORT
case ASSOC_STATE_MACHINE:
StateMachinePerformAction(pAd, &pAd->Mlme.AssocMachine,
Elem, pAd->Mlme.AssocMachine.CurrState);
break;
case AUTH_STATE_MACHINE:
StateMachinePerformAction(pAd, &pAd->Mlme.AuthMachine,
Elem, pAd->Mlme.AuthMachine.CurrState);
break;
case AUTH_RSP_STATE_MACHINE:
StateMachinePerformAction(pAd, &pAd->Mlme.AuthRspMachine,
Elem, pAd->Mlme.AuthRspMachine.CurrState);
break;
case SYNC_STATE_MACHINE:
StateMachinePerformAction(pAd, &pAd->Mlme.SyncMachine,
Elem, pAd->Mlme.SyncMachine.CurrState);
break;
case MLME_CNTL_STATE_MACHINE:
MlmeCntlMachinePerformAction(pAd, &pAd->Mlme.CntlMachine, Elem);
break;
case WPA_PSK_STATE_MACHINE:
StateMachinePerformAction(pAd, &pAd->Mlme.WpaPskMachine,
Elem, pAd->Mlme.WpaPskMachine.CurrState);
break;
#ifdef QOS_DLS_SUPPORT
case DLS_STATE_MACHINE:
StateMachinePerformAction(pAd, &pAd->Mlme.DlsMachine,
Elem, pAd->Mlme.DlsMachine.CurrState);
break;
#endif // QOS_DLS_SUPPORT //
#endif // CONFIG_STA_SUPPORT //
case ACTION_STATE_MACHINE:
StateMachinePerformAction(pAd, &pAd->Mlme.ActMachine,
Elem, pAd->Mlme.ActMachine.CurrState);
break;
case WPA_STATE_MACHINE:
StateMachinePerformAction(pAd, &pAd->Mlme.WpaMachine, Elem, pAd->Mlme.WpaMachine.CurrState);
break;
default:
DBGPRINT(RT_DEBUG_TRACE, ("ERROR: Illegal machine %ld in MlmeHandler()\n", Elem->Machine));
break;
} // end of switch
// free MLME element
Elem->Occupied = FALSE;
Elem->MsgLen = 0;
}
else {
DBGPRINT_ERR(("MlmeHandler: MlmeQueue empty\n"));
}
}
NdisAcquireSpinLock(&pAd->Mlme.TaskLock);
pAd->Mlme.bRunning = FALSE;
NdisReleaseSpinLock(&pAd->Mlme.TaskLock);
}
/*
==========================================================================
Description:
Destructor of MLME (Destroy queue, state machine, spin lock and timer)
Parameters:
Adapter - NIC Adapter pointer
Post:
The MLME task will no longer work properly
IRQL = PASSIVE_LEVEL
==========================================================================
*/
VOID MlmeHalt(
IN PRTMP_ADAPTER pAd)
{
BOOLEAN Cancelled;
DBGPRINT(RT_DEBUG_TRACE, ("==> MlmeHalt\n"));
if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))
{
// disable BEACON generation and other BEACON related hardware timers
AsicDisableSync(pAd);
}
RTMPCancelTimer(&pAd->Mlme.PeriodicTimer, &Cancelled);
#ifdef CONFIG_STA_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_STA(pAd)
{
#ifdef QOS_DLS_SUPPORT
UCHAR i;
#endif // QOS_DLS_SUPPORT //
// Cancel pending timers
RTMPCancelTimer(&pAd->MlmeAux.AssocTimer, &Cancelled);
RTMPCancelTimer(&pAd->MlmeAux.ReassocTimer, &Cancelled);
RTMPCancelTimer(&pAd->MlmeAux.DisassocTimer, &Cancelled);
RTMPCancelTimer(&pAd->MlmeAux.AuthTimer, &Cancelled);
RTMPCancelTimer(&pAd->MlmeAux.BeaconTimer, &Cancelled);
RTMPCancelTimer(&pAd->MlmeAux.ScanTimer, &Cancelled);
#ifdef PCIE_PS_SUPPORT
if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)
&&(pAd->StaCfg.PSControl.field.EnableNewPS == TRUE))
{
RTMPCancelTimer(&pAd->Mlme.PsPollTimer, &Cancelled);
RTMPCancelTimer(&pAd->Mlme.RadioOnOffTimer, &Cancelled);
}
#endif // PCIE_PS_SUPPORT //
#ifdef QOS_DLS_SUPPORT
for (i=0; i<MAX_NUM_OF_DLS_ENTRY; i++)
{
RTMPCancelTimer(&pAd->StaCfg.DLSEntry[i].Timer, &Cancelled);
}
#endif // QOS_DLS_SUPPORT //
RTMPCancelTimer(&pAd->Mlme.LinkDownTimer, &Cancelled);
if (pAd->StaCfg.StaQuickResponeForRateUpTimerRunning)
{
RTMPCancelTimer(&pAd->StaCfg.StaQuickResponeForRateUpTimer, &Cancelled);
pAd->StaCfg.StaQuickResponeForRateUpTimerRunning = FALSE;
}
RTMPCancelTimer(&pAd->StaCfg.WpaDisassocAndBlockAssocTimer, &Cancelled);
}
#endif // CONFIG_STA_SUPPORT //
RTMPCancelTimer(&pAd->Mlme.RxAntEvalTimer, &Cancelled);
if ((pAd->bHwCoexInit == TRUE) && IS_ENABLE_MISC_TIMER(pAd))
{
RTMPCancelTimer(&pAd->Mlme.MiscDetectTimer,&Cancelled);
}
if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))
{
RTMP_CHIP_OP *pChipOps = &pAd->chipOps;
#ifdef LED_CONTROL_SUPPORT
// Set LED
RTMPSetLED(pAd, LED_HALT);
RTMPSetSignalLED(pAd, -100); // Force signal strength Led to be turned off, firmware is not done it.
#endif // LED_CONTROL_SUPPORT //
if (pChipOps->AsicHaltAction)
pChipOps->AsicHaltAction(pAd);
}
RTMPusecDelay(5000); // 5 msec to gurantee Ant Diversity timer canceled
MlmeQueueDestroy(&pAd->Mlme.Queue);
NdisFreeSpinLock(&pAd->Mlme.TaskLock);
DBGPRINT(RT_DEBUG_TRACE, ("<== MlmeHalt\n"));
}
VOID MlmeResetRalinkCounters(
IN PRTMP_ADAPTER pAd)
{
pAd->RalinkCounters.LastOneSecRxOkDataCnt = pAd->RalinkCounters.OneSecRxOkDataCnt;
/* for performace enchanement */
NdisZeroMemory(&pAd->RalinkCounters,
&pAd->RalinkCounters.OneSecEnd -
&pAd->RalinkCounters.OneSecStart);
return;
}
/*
==========================================================================
Description:
This routine is executed periodically to -
1. Decide if it's a right time to turn on PwrMgmt bit of all
outgoiing frames
2. Calculate ChannelQuality based on statistics of the last
period, so that TX rate won't toggling very frequently between a
successful TX and a failed TX.
3. If the calculated ChannelQuality indicated current connection not
healthy, then a ROAMing attempt is tried here.
IRQL = DISPATCH_LEVEL
==========================================================================
*/
#define ADHOC_BEACON_LOST_TIME (8*OS_HZ) // 8 sec
VOID MlmePeriodicExec(
IN PVOID SystemSpecific1,
IN PVOID FunctionContext,
IN PVOID SystemSpecific2,
IN PVOID SystemSpecific3)
{
ULONG TxTotalCnt;
PRTMP_ADAPTER pAd = (RTMP_ADAPTER *)FunctionContext;
#ifdef RTMP_MAC_PCI
#ifdef CONFIG_STA_SUPPORT
#ifdef RT30xx
// not for USB device!
// FWv.18 and after needs the timer tick command every 200 ms
// LedMode = 0 : Slow Blink, Fast blink, light all normal. So need to set 0x84 software timer command.
if ((IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3593(pAd)) &&
(pAd->Mlme.PeriodicRound % 2 == 0) &&
(pAd->StaCfg.PSControl.field.LedMode == 0) &&
(!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) &&
(!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)))
{
AsicSendCommandToMcu(pAd, 0x84, 0xff, 0xff, 0xff);
}
#endif // RT30xx //
#endif // CONFIG_STA_SUPPORT //
#endif // RTMP_MAC_PCI //
#ifdef INF_AMAZON_SE
SoftwareFlowControl(pAd);
#endif // INF_AMAZON_SE //
#ifdef CONFIG_STA_SUPPORT
#ifdef RTMP_MAC_PCI
IF_DEV_CONFIG_OPMODE_ON_STA(pAd)
{
// If Hardware controlled Radio enabled, we have to check GPIO pin2 every 2 second.
// Move code to here, because following code will return when radio is off
if ((pAd->Mlme.PeriodicRound % (MLME_TASK_EXEC_MULTIPLE * 2) == 0) &&
// (pAd->StaCfg.bHardwareRadio == TRUE) &&
((IDLE_ON(pAd)) || (pAd->StaCfg.Psm == PWR_ACTIVE)) &&
(!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) &&
(!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)) &&
((pAd->StaCfg.bHardwareRadio == TRUE))
// || (pAd->StaCfg.WscControl.CheckHWPBCState == HWPBCState_GUI)))
/*&&(pAd->bPCIclkOff == FALSE)*/)
{
UINT32 data = 0;
#ifdef RT30xx
// If in power save state, force wake up to configure register, AsicRadioOff will be called later n STAMlmePeriodicExec
if ((OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)
|| (RTMP_TEST_PSFLAG(pAd, fRTMP_PS_SET_PCI_CLK_OFF_COMMAND))
|| RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF))
&& (IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3593(pAd))
&& (pAd->StaCfg.bRadio == TRUE))
{
RT28xxPciAsicRadioOn(pAd, GUI_IDLE_POWER_SAVE);
}
#endif // RT30xx //
// Read GPIO pin2 as Hardware controlled radio state
//#ifndef RT3090
//RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &data);
//#endif // RT3090 //
//KH(PCIE PS):Added based on Jane<--
#ifdef PCIE_PS_SUPPORT
// Read GPIO pin2 as Hardware controlled radio state
// We need to Read GPIO if HW said so no mater what advance power saving
if ((pAd->OpMode == OPMODE_STA) && (IDLE_ON(pAd))
&& (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF))
&& (pAd->StaCfg.PSControl.field.EnablePSinIdle == TRUE))
{
// Want to make sure device goes to L0 state before reading register.
RTMPPCIeLinkCtrlValueRestore(pAd, 0);
RTMP_IO_FORCE_READ32(pAd, GPIO_CTRL_CFG, &data);
RTMPPCIeLinkCtrlSetting(pAd, 3);
}
else
RTMP_IO_FORCE_READ32(pAd, GPIO_CTRL_CFG, &data);
#else
RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &data);
#endif // defined(RT3090) || defined(RT3592) || defined(RT3390) //
//KH(PCIE PS):Added based on Jane-->
// Update Radio state from GPIO
if (pAd->StaCfg.bHardwareRadio == TRUE)
{
if (data & 0x04)
{
pAd->StaCfg.bHwRadio = TRUE;
}
else
{
pAd->StaCfg.bHwRadio = FALSE;
}
#ifdef RT_CFG80211_SUPPORT
#ifdef RFKILL_HW_SUPPORT
RFKillStatusUpdate(pAd, pAd->StaCfg.bHwRadio);
#endif // RFKILL_HW_SUPPORT //
#endif /* RT_CFG80211_SUPPORT */
}
if (IS_RT3592CB(pAd) && WM_COEX_TEST_FLAG(pAd, fWM_CHECK_RADIO))
{
rt3592cb_ant_switch(pAd, data);
}
// Always read HW radio configuration.