Makefile.coco

# Makefile

# defaults
SIM ?= icarus
TOPLEVEL_LANG ?= verilog
COMPILE_ARGS = -grelative-include

# must contain also included files to correctly trigger recompilation as needed
VERILOG_SOURCES += \
		lib/verilog-uart/rtl/uart_rx.v \
		lib/verilog-uart/rtl/uart_tx.v \
		lib/verilog-uart/rtl/uart.v \
		rtl/clk_25_250_125_25.v \
		rtl/CPU_Rom.sv \
		rtl/Interrupt_Ctrl.sv \
		rtl/Memory_Ctrl.sv \
		rtl/memory_map.sv \
		rtl/pll.v \
		rtl/RGB_Color_Bars_Generator.v \
		rtl/Sdram_Arbiter.sv \
		rtl/Text_Generator.v \
		rtl/tmds_encoder.v \
		rtl/top.sv \
		rtl/VGA_Timing_Generator.sv \
		rtl/Video_Ctrl.sv \
		rtl/generated/top_csr.v \
		rtl/generated/VexRiscv.v \
		rtl/ip/sdram_pnru.v \
		rtl/model/mt48lc16m16a2.v \
		rtl/sim/top_sim.sv

# use VHDL_SOURCES for VHDL files

# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
TOPLEVEL = top_sim

# MODULE is the basename of the Python test file
MODULE = test_my_design

# include cocotb's make rules to take care of the simulator setup
include $(shell cocotb-config --makefiles)/Makefile.sim