Mksocfpga Failing builds #116

the-snowwhite · 2020-10-22T20:46:26Z

@cerna
https://github.com/machinekit/mksocfpga/pull/115/checks?check_run_id=1294764215

AFAIK someone pulled the plug on the old build system a while ago and
someone is yet to place in the replacement ?

cerna · 2020-10-22T21:46:50Z

@the-snowwhite,
yes. This is the same as what is root behind machinekit/machinekit-hal#268 - the Jenkins server was turned off silently with everything dependent on it shut down too.

I knew this was going to cause a problem with mksocfpga, but A) the repository was long-time dormant and B) I am FPGA virgin - I have read multiple articles and tutorials, looked into the AMBA AXI interface and affiliated Linux kernel modules, have few devices which have FPGA integrated and was generally interested in the technology, but never actually programmed any nor own development board. So I was very bashful about building a CI/CD workflow for it.

The failure in #115 looks like was on Jessie system and a first build after the repository was changed from TRAVIS-CI ORG to COM. Jessie is EOLed and I actually turned off building and testing Machinekit-HAL for it. While the error does not look as connected to issues which generally happen after Debian distribution is laid to rest, it is still valid point if this test is viable.

Have you tried what the Travis does locally on your machine?

the-snowwhite · 2020-10-22T22:11:03Z

Unh I found the online travis report seems like it failed early in the
(to my pr unrelated)
quartus build fase.
Since @cdsteinkuehler mastered this docker image I hope he can chime in on what seems to be happening there.
AKAIK this failure is unrelated to any changes to code in the mksocfpga repo.

cerna · 2020-10-22T22:51:35Z

First try on #115 using the same commands as TRACI-CI locally was too unsuccessful, but it failed on different error:

docker run -v $(pwd):/work cdsteinkuehler/jessie-quartus-15.1.2 /work/Scripts/travis_build.sh
qsys-generate soc_system.qsys --synthesis=VERILOG 
2020.10.22.22:37:20 Info: Saving generation log to /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/soc_system_generation.rpt
2020.10.22.22:37:20 Info: Starting: <b>Create HDL design files for synthesis</b>
2020.10.22.22:37:20 Info: qsys-generate /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system.qsys --synthesis=VERILOG --output-directory=/work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis --family="Cyclone V" --part=5CSEMA4U23C6
2020.10.22.22:37:20 Info: Loading DE0_Nano_SoC_Cramps/soc_system.qsys
2020.10.22.22:37:20 Info: Reading input file
2020.10.22.22:37:20 Info: Adding button_pio [altera_avalon_pio 15.1]
2020.10.22.22:37:20 Info: Parameterizing module button_pio
2020.10.22.22:37:20 Info: Adding clk_0 [clock_source 15.1]
2020.10.22.22:37:20 Info: Parameterizing module clk_0
2020.10.22.22:37:20 Info: Adding dipsw_pio [altera_avalon_pio 15.1]
2020.10.22.22:37:20 Info: Parameterizing module dipsw_pio
2020.10.22.22:37:20 Info: Adding fpga_only_master [altera_jtag_avalon_master 15.1]
2020.10.22.22:37:20 Info: Parameterizing module fpga_only_master
2020.10.22.22:37:20 Info: Adding hm2reg_io_0 [hm2reg_io 1.0]
2020.10.22.22:37:20 Info: Parameterizing module hm2reg_io_0
2020.10.22.22:37:20 Info: Adding hps_0 [altera_hps 15.1]
2020.10.22.22:37:20 Info: Parameterizing module hps_0
2020.10.22.22:37:20 Info: Adding hps_only_master [altera_jtag_avalon_master 15.1]
2020.10.22.22:37:20 Info: Parameterizing module hps_only_master
2020.10.22.22:37:20 Info: Adding intr_capturer_0 [intr_capturer 100.99.98.97]
2020.10.22.22:37:20 Info: Parameterizing module intr_capturer_0
2020.10.22.22:37:20 Info: Adding jtag_uart [altera_avalon_jtag_uart 15.1]
2020.10.22.22:37:20 Info: Parameterizing module jtag_uart
2020.10.22.22:37:20 Info: Adding led_pio [altera_avalon_pio 15.1]
2020.10.22.22:37:20 Info: Parameterizing module led_pio
2020.10.22.22:37:20 Info: Adding mm_bridge_0 [altera_avalon_mm_bridge 15.1]
2020.10.22.22:37:20 Info: Parameterizing module mm_bridge_0
2020.10.22.22:37:20 Info: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 15.1]
2020.10.22.22:37:20 Info: Parameterizing module onchip_memory2_0
2020.10.22.22:37:20 Info: Adding pll_0 [altera_pll 15.1]
2020.10.22.22:37:20 Info: Parameterizing module pll_0
2020.10.22.22:37:20 Info: Adding sysid_qsys [altera_avalon_sysid_qsys 15.1]
2020.10.22.22:37:20 Info: Parameterizing module sysid_qsys
2020.10.22.22:37:20 Info: Building connections
2020.10.22.22:37:20 Info: Parameterizing connections
2020.10.22.22:37:20 Info: Validating
2020.10.22.22:37:29 Info: Done reading input file
2020.10.22.22:37:32 Info: soc_system.hps_0: HPS Main PLL counter settings: n = 0  m = 73
2020.10.22.22:37:32 Info: soc_system.hps_0: HPS peripherial PLL counter settings: n = 0  m = 39
2020.10.22.22:37:32 Info: soc_system.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz
2020.10.22.22:37:32 Info: soc_system.pll_0: Able to implement PLL with user settings
2020.10.22.22:37:32 Info: soc_system.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
2020.10.22.22:37:32 Info: soc_system.sysid_qsys: Time stamp will be automatically updated when this component is generated.
2020.10.22.22:38:06 Info: soc_system: Generating <b>soc_system</b> "<b>soc_system</b>" for QUARTUS_SYNTH
2020.10.22.22:38:13 Info: Interconnect is inserted between master hps_0.h2f_lw_axi_master and slave mm_bridge_0.s0 because the master is of type axi and the slave is of type avalon.
2020.10.22.22:38:18 Info: Interconnect is inserted between master hps_only_master.master and slave hps_0.f2h_axi_slave because the master is of type avalon and the slave is of type axi.
2020.10.22.22:38:19 Warning: hps_0.f2h_irq0: Cannot connect clock for <b>irq_mapper.sender</b>
2020.10.22.22:38:19 Warning: hps_0.f2h_irq0: Cannot connect reset for <b>irq_mapper.sender</b>
2020.10.22.22:38:19 Warning: hps_0.f2h_irq1: Cannot connect clock for <b>irq_mapper_001.sender</b>
2020.10.22.22:38:19 Warning: hps_0.f2h_irq1: Cannot connect reset for <b>irq_mapper_001.sender</b>
2020.10.22.22:38:25 Info: button_pio: Starting RTL generation for module 'soc_system_button_pio'
2020.10.22.22:38:25 Info: button_pio:   Generation command is [exec /home/builder/altera_lite/15.1/quartus/linux64/perl/bin/perl -I /home/builder/altera_lite/15.1/quartus/linux64/perl/lib -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin/europa -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin/perl_lib -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin -I /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=soc_system_button_pio --dir=/tmp/alt8557_2162494273812915309.dir/0001_button_pio_gen/ --quartus_dir=/home/builder/altera_lite/15.1/quartus --verilog --config=/tmp/alt8557_2162494273812915309.dir/0001_button_pio_gen//soc_system_button_pio_component_configuration.pl  --do_build_sim=0  ]
2020.10.22.22:38:25 Info: button_pio: Done RTL generation for module 'soc_system_button_pio'
2020.10.22.22:38:25 Info: button_pio: "<b>soc_system</b>" instantiated <b>altera_avalon_pio</b> "<b>button_pio</b>"
2020.10.22.22:38:25 Info: dipsw_pio: Starting RTL generation for module 'soc_system_dipsw_pio'
2020.10.22.22:38:25 Info: dipsw_pio:   Generation command is [exec /home/builder/altera_lite/15.1/quartus/linux64/perl/bin/perl -I /home/builder/altera_lite/15.1/quartus/linux64/perl/lib -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin/europa -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin/perl_lib -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin -I /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=soc_system_dipsw_pio --dir=/tmp/alt8557_2162494273812915309.dir/0002_dipsw_pio_gen/ --quartus_dir=/home/builder/altera_lite/15.1/quartus --verilog --config=/tmp/alt8557_2162494273812915309.dir/0002_dipsw_pio_gen//soc_system_dipsw_pio_component_configuration.pl  --do_build_sim=0  ]
2020.10.22.22:38:25 Info: dipsw_pio: Done RTL generation for module 'soc_system_dipsw_pio'
2020.10.22.22:38:25 Info: dipsw_pio: "<b>soc_system</b>" instantiated <b>altera_avalon_pio</b> "<b>dipsw_pio</b>"
2020.10.22.22:38:25 Info: fpga_only_master: "<b>soc_system</b>" instantiated <b>altera_jtag_avalon_master</b> "<b>fpga_only_master</b>"
2020.10.22.22:38:25 Info: hm2reg_io_0: "<b>soc_system</b>" instantiated <b>hm2reg_io</b> "<b>hm2reg_io_0</b>"
2020.10.22.22:38:25 Info: hps_0: "Running  for module: hps_0"
2020.10.22.22:38:26 Info: hps_0: HPS Main PLL counter settings: n = 0  m = 73
2020.10.22.22:38:27 Info: hps_0: HPS peripherial PLL counter settings: n = 0  m = 39
2020.10.22.22:38:28 Info: hps_0: "<b>soc_system</b>" instantiated <b>altera_hps</b> "<b>hps_0</b>"
2020.10.22.22:38:28 Info: intr_capturer_0: "<b>soc_system</b>" instantiated <b>intr_capturer</b> "<b>intr_capturer_0</b>"
2020.10.22.22:38:28 Info: jtag_uart: Starting RTL generation for module 'soc_system_jtag_uart'
2020.10.22.22:38:28 Info: jtag_uart:   Generation command is [exec /home/builder/altera_lite/15.1/quartus/linux64/perl/bin/perl -I /home/builder/altera_lite/15.1/quartus/linux64/perl/lib -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin/europa -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin/perl_lib -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin -I /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=soc_system_jtag_uart --dir=/tmp/alt8557_2162494273812915309.dir/0005_jtag_uart_gen/ --quartus_dir=/home/builder/altera_lite/15.1/quartus --verilog --config=/tmp/alt8557_2162494273812915309.dir/0005_jtag_uart_gen//soc_system_jtag_uart_component_configuration.pl  --do_build_sim=0  ]
2020.10.22.22:38:28 Info: jtag_uart: Done RTL generation for module 'soc_system_jtag_uart'
2020.10.22.22:38:28 Info: jtag_uart: "<b>soc_system</b>" instantiated <b>altera_avalon_jtag_uart</b> "<b>jtag_uart</b>"
2020.10.22.22:38:28 Info: led_pio: Starting RTL generation for module 'soc_system_led_pio'
2020.10.22.22:38:28 Info: led_pio:   Generation command is [exec /home/builder/altera_lite/15.1/quartus/linux64/perl/bin/perl -I /home/builder/altera_lite/15.1/quartus/linux64/perl/lib -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin/europa -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin/perl_lib -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin -I /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=soc_system_led_pio --dir=/tmp/alt8557_2162494273812915309.dir/0006_led_pio_gen/ --quartus_dir=/home/builder/altera_lite/15.1/quartus --verilog --config=/tmp/alt8557_2162494273812915309.dir/0006_led_pio_gen//soc_system_led_pio_component_configuration.pl  --do_build_sim=0  ]
2020.10.22.22:38:29 Info: led_pio: Done RTL generation for module 'soc_system_led_pio'
2020.10.22.22:38:29 Info: led_pio: "<b>soc_system</b>" instantiated <b>altera_avalon_pio</b> "<b>led_pio</b>"
2020.10.22.22:38:29 Info: mm_bridge_0: "<b>soc_system</b>" instantiated <b>altera_avalon_mm_bridge</b> "<b>mm_bridge_0</b>"
2020.10.22.22:38:29 Info: onchip_memory2_0: Starting RTL generation for module 'soc_system_onchip_memory2_0'
2020.10.22.22:38:29 Info: onchip_memory2_0:   Generation command is [exec /home/builder/altera_lite/15.1/quartus/linux64/perl/bin/perl -I /home/builder/altera_lite/15.1/quartus/linux64/perl/lib -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin/europa -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin/perl_lib -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin -I /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=soc_system_onchip_memory2_0 --dir=/tmp/alt8557_2162494273812915309.dir/0007_onchip_memory2_0_gen/ --quartus_dir=/home/builder/altera_lite/15.1/quartus --verilog --config=/tmp/alt8557_2162494273812915309.dir/0007_onchip_memory2_0_gen//soc_system_onchip_memory2_0_component_configuration.pl  --do_build_sim=0  ]
2020.10.22.22:38:29 Info: onchip_memory2_0: Done RTL generation for module 'soc_system_onchip_memory2_0'
2020.10.22.22:38:29 Info: onchip_memory2_0: "<b>soc_system</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>onchip_memory2_0</b>"
2020.10.22.22:38:29 Info: pll_0: "<b>soc_system</b>" instantiated <b>altera_pll</b> "<b>pll_0</b>"
2020.10.22.22:38:29 Info: sysid_qsys: "<b>soc_system</b>" instantiated <b>altera_avalon_sysid_qsys</b> "<b>sysid_qsys</b>"
2020.10.22.22:38:29 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2020.10.22.22:38:29 Info: mm_interconnect_0: "<b>soc_system</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_0</b>"
2020.10.22.22:38:30 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2020.10.22.22:38:30 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
2020.10.22.22:38:30 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
2020.10.22.22:38:31 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
2020.10.22.22:38:31 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
2020.10.22.22:38:31 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
2020.10.22.22:38:31 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
2020.10.22.22:38:31 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0
2020.10.22.22:38:32 Info: mm_interconnect_1: "<b>soc_system</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_1</b>"
2020.10.22.22:38:32 Info: mm_interconnect_2: "<b>soc_system</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_2</b>"
2020.10.22.22:38:32 Info: irq_mapper: "<b>soc_system</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper</b>"
2020.10.22.22:38:32 Info: irq_mapper_001: "<b>soc_system</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper_001</b>"
2020.10.22.22:38:32 Info: rst_controller: "<b>soc_system</b>" instantiated <b>altera_reset_controller</b> "<b>rst_controller</b>"
2020.10.22.22:38:32 Info: jtag_phy_embedded_in_jtag_master: "<b>fpga_only_master</b>" instantiated <b>altera_jtag_dc_streaming</b> "<b>jtag_phy_embedded_in_jtag_master</b>"
2020.10.22.22:38:32 Info: timing_adt: "<b>fpga_only_master</b>" instantiated <b>timing_adapter</b> "<b>timing_adt</b>"
2020.10.22.22:38:32 Info: fifo: "<b>fpga_only_master</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>fifo</b>"
2020.10.22.22:38:32 Info: b2p: "<b>fpga_only_master</b>" instantiated <b>altera_avalon_st_bytes_to_packets</b> "<b>b2p</b>"
2020.10.22.22:38:32 Info: p2b: "<b>fpga_only_master</b>" instantiated <b>altera_avalon_st_packets_to_bytes</b> "<b>p2b</b>"
2020.10.22.22:38:32 Info: transacto: "<b>fpga_only_master</b>" instantiated <b>altera_avalon_packets_to_master</b> "<b>transacto</b>"
2020.10.22.22:38:32 Info: b2p_adapter: "<b>fpga_only_master</b>" instantiated <b>channel_adapter</b> "<b>b2p_adapter</b>"
2020.10.22.22:38:32 Info: p2b_adapter: "<b>fpga_only_master</b>" instantiated <b>channel_adapter</b> "<b>p2b_adapter</b>"
2020.10.22.22:38:32 Info: fpga_interfaces: "<b>hps_0</b>" instantiated <b>altera_interface_generator</b> "<b>fpga_interfaces</b>"
2020.10.22.22:38:32 Info: hps_io: "<b>hps_0</b>" instantiated <b>altera_hps_io</b> "<b>hps_io</b>"
2020.10.22.22:38:32 Info: mm_bridge_0_s0_translator: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>mm_bridge_0_s0_translator</b>"
2020.10.22.22:38:32 Info: hps_0_h2f_lw_axi_master_agent: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_axi_master_ni</b> "<b>hps_0_h2f_lw_axi_master_agent</b>"
2020.10.22.22:38:32 Info: mm_bridge_0_s0_agent: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>mm_bridge_0_s0_agent</b>"
2020.10.22.22:38:32 Info: router: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"
2020.10.22.22:38:32 Info: router_002: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>"
2020.10.22.22:38:32 Info: mm_bridge_0_s0_burst_adapter: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_burst_adapter</b> "<b>mm_bridge_0_s0_burst_adapter</b>"
2020.10.22.22:38:32 Info: Reusing file <b>/work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv</b>
2020.10.22.22:38:32 Info: Reusing file <b>/work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv</b>
2020.10.22.22:38:32 Info: Reusing file <b>/work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v</b>
2020.10.22.22:38:32 Info: cmd_demux: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"
2020.10.22.22:38:33 Info: cmd_mux: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"
2020.10.22.22:38:33 Info: rsp_demux: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"
2020.10.22.22:38:33 Info: rsp_mux: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"
2020.10.22.22:38:33 Info: Reusing file <b>/work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv</b>
2020.10.22.22:38:33 Info: avalon_st_adapter: "<b>mm_interconnect_0</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter</b>"
2020.10.22.22:38:33 Info: mm_bridge_0_m0_translator: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_translator</b> "<b>mm_bridge_0_m0_translator</b>"
2020.10.22.22:38:33 Info: mm_bridge_0_m0_agent: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_agent</b> "<b>mm_bridge_0_m0_agent</b>"
2020.10.22.22:38:33 Info: router: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"
2020.10.22.22:38:33 Info: router_001: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_001</b>"
2020.10.22.22:38:33 Info: router_002: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>"
2020.10.22.22:38:33 Info: router_007: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_007</b>"
2020.10.22.22:38:33 Info: router_009: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_009</b>"
2020.10.22.22:38:33 Info: mm_bridge_0_m0_limiter: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_traffic_limiter</b> "<b>mm_bridge_0_m0_limiter</b>"
2020.10.22.22:38:33 Info: Reusing file <b>/work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_sc_fifo.v</b>
2020.10.22.22:38:33 Info: Reusing file <b>/work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v</b>
2020.10.22.22:38:33 Info: cmd_demux: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"
2020.10.22.22:38:33 Info: cmd_demux_001: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux_001</b>"
2020.10.22.22:38:33 Info: cmd_mux: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"
2020.10.22.22:38:33 Info: Reusing file <b>/work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv</b>
2020.10.22.22:38:33 Info: cmd_mux_007: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_007</b>"
2020.10.22.22:38:33 Info: Reusing file <b>/work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv</b>
2020.10.22.22:38:33 Info: rsp_demux: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"
2020.10.22.22:38:33 Info: rsp_demux_007: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_007</b>"
2020.10.22.22:38:33 Info: rsp_mux: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"
2020.10.22.22:38:33 Info: Reusing file <b>/work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv</b>
2020.10.22.22:38:33 Info: rsp_mux_001: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux_001</b>"
2020.10.22.22:38:33 Info: Reusing file <b>/work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv</b>
2020.10.22.22:38:33 Info: onchip_memory2_0_s1_cmd_width_adapter: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_width_adapter</b> "<b>onchip_memory2_0_s1_cmd_width_adapter</b>"
2020.10.22.22:38:33 Info: Reusing file <b>/work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv</b>
2020.10.22.22:38:33 Info: Reusing file <b>/work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>
2020.10.22.22:38:33 Info: avalon_st_adapter_005: "<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter_005</b>"
2020.10.22.22:38:33 Info: hps_0_f2h_axi_slave_agent: "<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_axi_slave_ni</b> "<b>hps_0_f2h_axi_slave_agent</b>"
2020.10.22.22:38:33 Info: Reusing file <b>/work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>
2020.10.22.22:38:33 Info: Reusing file <b>/work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_sc_fifo.v</b>
2020.10.22.22:38:33 Info: Reusing file <b>/work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv</b>
2020.10.22.22:38:33 Info: router: "<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"
2020.10.22.22:38:33 Info: router_001: "<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_router</b> "<b>router_001</b>"
2020.10.22.22:38:33 Info: cmd_demux: "<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"
2020.10.22.22:38:33 Info: cmd_mux: "<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"
2020.10.22.22:38:33 Info: Reusing file <b>/work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv</b>
2020.10.22.22:38:33 Info: rsp_demux: "<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"
2020.10.22.22:38:33 Info: rsp_mux: "<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"
2020.10.22.22:38:33 Info: Reusing file <b>/work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv</b>
2020.10.22.22:39:15 Info: border: "<b>hps_io</b>" instantiated <b>altera_interface_generator</b> "<b>border</b>"
2020.10.22.22:39:15 Info: error_adapter_0: "<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"
2020.10.22.22:39:15 Info: error_adapter_0: "<b>avalon_st_adapter_005</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"
2020.10.22.22:39:15 Info: soc_system: Done "<b>soc_system</b>" with 68 modules, 137 files
2020.10.22.22:39:17 Info: qsys-generate succeeded.
2020.10.22.22:39:17 Info: Finished: <b>Create HDL design files for synthesis</b>
quartus_map DE0_Nano_SoC_Cramps.qpf
sopc2dts --input soc_system.sopcinfo --output soc_system.dts  --board soc_system_board_info.xml --board hps_common_board_info.xml --bridge-removal all --clocks
sopc2dts --input soc_system.sopcinfo --output soc_system.dtb --type dtb --board soc_system_board_info.xml --board hps_common_board_info.xml --bridge-removal all --clocks
Component pll_0 of class altera_pll is unknown
Component pll_0 of class altera_pll is unknown
Component pll_0 of class altera_pll is unknown
Component pll_0 of class altera_pll is unknown
Component pll_0 of class altera_pll is unknown
Component pll_0 of class altera_pll is unknown
Inconsistency detected by ld.so: dl-close.c: 762: _dl_close: Assertion `map->l_init_called' failed!
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 15.1.2 Build 193 02/01/2016 SJ Lite Edition
    Info: Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, the Altera Quartus Prime License Agreement,
    Info: the Altera MegaCore Function License Agreement, or other 
    Info: applicable license agreement, including, without limitation, 
    Info: that your use is for the sole purpose of programming logic 
    Info: devices manufactured by Altera and sold by Altera or its 
    Info: authorized distributors.  Please refer to the applicable 
    Info: agreement for further details.
    Info: Processing started: Thu Oct 22 22:39:19 2020
Info: Command: quartus_map DE0_Nano_SoC_Cramps.qpf
Warning (125092): Tcl Script File hm3_DE0_Nano_SoC_Cramps.qip not found
    Info (125063): set_global_assignment -name QIP_FILE hm3_DE0_Nano_SoC_Cramps.qip
Warning (125092): Tcl Script File hm3_pin_config.qip not found
    Info (125063): set_global_assignment -name QIP_FILE hm3_pin_config.qip
Critical Warning (138067): Current license file does not support incremental compilation. The Quartus Prime software removes all the user-specified design partitions in the design automatically.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/QuartusProjects/Common/firmware_id.vhd
    Info (12022): Found design unit 1: firmware_id-arch File: /work/HW/QuartusProjects/Common/firmware_id.vhd Line: 81
    Info (12023): Found entity 1: firmware_id File: /work/HW/QuartusProjects/Common/firmware_id.vhd Line: 72
Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/cv-megawizard/lpm_pack.vhd
    Info (12022): Found design unit 1: LPM_COMPONENTS File: /work/HW/cv-megawizard/lpm_pack.vhd Line: 170
    Info (12022): Found design unit 2: LPM_COMPONENTS-body File: /work/HW/cv-megawizard/lpm_pack.vhd Line: 678
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/cv-megawizard/lpm-ip/lpm_mux16.vhd
    Info (12022): Found design unit 1: lpm_mux16-SYN File: /work/HW/cv-megawizard/lpm-ip/lpm_mux16.vhd Line: 68
    Info (12023): Found entity 1: lpm_mux16 File: /work/HW/cv-megawizard/lpm-ip/lpm_mux16.vhd Line: 43
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/cv-megawizard/lpm-ip/lpm_shiftreg16.vhd
    Info (12022): Found design unit 1: lpm_shiftreg16-SYN File: /work/HW/cv-megawizard/lpm-ip/lpm_shiftreg16.vhd Line: 54
    Info (12023): Found entity 1: lpm_shiftreg16 File: /work/HW/cv-megawizard/lpm-ip/lpm_shiftreg16.vhd Line: 43
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/cv-megawizard/SRL16E.vhd
    Info (12022): Found design unit 1: SRL16E-arch File: /work/HW/cv-megawizard/SRL16E.vhd Line: 26
    Info (12023): Found entity 1: SRL16E File: /work/HW/cv-megawizard/SRL16E.vhd Line: 9
Info (12021): Found 1 design units, including 0 entities, in source file /work/HW/hm2/config/IDROMConst.vhd
    Info (12022): Found design unit 1: IDROMConst File: /work/HW/hm2/config/IDROMConst.vhd Line: 70
Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/PinExists.vhd
    Info (12022): Found design unit 1: PinExists File: /work/HW/hm2/functions/PinExists.vhd Line: 71
    Info (12022): Found design unit 2: PinExists-body File: /work/HW/hm2/functions/PinExists.vhd Line: 75
Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/oneofndecode.vhd
    Info (12022): Found design unit 1: oneofndecode File: /work/HW/hm2/functions/oneofndecode.vhd Line: 70
    Info (12022): Found design unit 2: oneofndecode-body File: /work/HW/hm2/functions/oneofndecode.vhd Line: 74
Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/NumberOfModules.vhd
    Info (12022): Found design unit 1: NumberOfModules File: /work/HW/hm2/functions/NumberOfModules.vhd Line: 71
    Info (12022): Found design unit 2: NumberOfModules-body File: /work/HW/hm2/functions/NumberOfModules.vhd Line: 75
Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/ModuleExists.vhd
    Info (12022): Found design unit 1: ModuleExists File: /work/HW/hm2/functions/ModuleExists.vhd Line: 71
    Info (12022): Found design unit 2: ModuleExists-body File: /work/HW/hm2/functions/ModuleExists.vhd Line: 75
Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/MaxPinsPerModule.vhd
    Info (12022): Found design unit 1: MaxPinsPerModule File: /work/HW/hm2/functions/MaxPinsPerModule.vhd Line: 71
    Info (12022): Found design unit 2: MaxPinsPerModule-body File: /work/HW/hm2/functions/MaxPinsPerModule.vhd Line: 75
Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/MaxOutputPinsPerModule.vhd
    Info (12022): Found design unit 1: MaxOutputPinsPerModule File: /work/HW/hm2/functions/MaxOutputPinsPerModule.vhd Line: 71
    Info (12022): Found design unit 2: MaxOutputPinsPerModule-body File: /work/HW/hm2/functions/MaxOutputPinsPerModule.vhd Line: 75
Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/MaxIOPinsPerModule.vhd
    Info (12022): Found design unit 1: MaxIOPinsPerModule File: /work/HW/hm2/functions/MaxIOPinsPerModule.vhd Line: 71
    Info (12022): Found design unit 2: MaxIOPinsPerModule-body File: /work/HW/hm2/functions/MaxIOPinsPerModule.vhd Line: 75
Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/MaxInputPinsPerModule.vhd
    Info (12022): Found design unit 1: MaxInputPinsPerModule File: /work/HW/hm2/functions/MaxInputPinsPerModule.vhd Line: 71
    Info (12022): Found design unit 2: MaxInputPinsPerModule-body File: /work/HW/hm2/functions/MaxInputPinsPerModule.vhd Line: 75
Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/log2.vhd
    Info (12022): Found design unit 1: log2 File: /work/HW/hm2/functions/log2.vhd Line: 70
    Info (12022): Found design unit 2: log2-body File: /work/HW/hm2/functions/log2.vhd Line: 74
Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/InputPinsPerModule.vhd
    Info (12022): Found design unit 1: InputPinsPerModule File: /work/HW/hm2/functions/InputPinsPerModule.vhd Line: 71
    Info (12022): Found design unit 2: InputPinsPerModule-body File: /work/HW/hm2/functions/InputPinsPerModule.vhd Line: 75
Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/decodedstrobe.vhd
    Info (12022): Found design unit 1: decodedstrobe File: /work/HW/hm2/functions/decodedstrobe.vhd Line: 70
    Info (12022): Found design unit 2: decodedstrobe-body File: /work/HW/hm2/functions/decodedstrobe.vhd Line: 74
Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/CountPinsInRange.vhd
    Info (12022): Found design unit 1: CountPinsInRange File: /work/HW/hm2/functions/CountPinsInRange.vhd Line: 71
    Info (12022): Found design unit 2: CountPinsInRange-body File: /work/HW/hm2/functions/CountPinsInRange.vhd Line: 75
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/hostmot3.vhd
    Info (12022): Found design unit 1: HostMot3-dataflow File: /work/HW/hm2/hostmot3.vhd Line: 142
    Info (12023): Found entity 1: HostMot3 File: /work/HW/hm2/hostmot3.vhd Line: 84
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakeIOPorts.vhd
    Info (12022): Found design unit 1: MakeIOPorts-dataflow File: /work/HW/hm2/wrappers/MakeIOPorts.vhd Line: 93
    Info (12023): Found entity 1: MakeIOPorts File: /work/HW/hm2/wrappers/MakeIOPorts.vhd Line: 19
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakeHm2Dpllmods.vhd
    Info (12022): Found design unit 1: MakeHm2Dpllmods-dataflow File: /work/HW/hm2/wrappers/MakeHm2Dpllmods.vhd Line: 62
    Info (12023): Found entity 1: MakeHm2Dpllmods File: /work/HW/hm2/wrappers/MakeHm2Dpllmods.vhd Line: 16
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakeStepgens.vhd
    Info (12022): Found design unit 1: MakeStepgens-dataflow File: /work/HW/hm2/wrappers/MakeStepgens.vhd Line: 62
    Info (12023): Found entity 1: MakeStepgens File: /work/HW/hm2/wrappers/MakeStepgens.vhd Line: 16
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakeQCounters.vhd
    Info (12022): Found design unit 1: MakeQCounters-dataflow File: /work/HW/hm2/wrappers/MakeQCounters.vhd Line: 62
    Info (12023): Found entity 1: MakeQCounters File: /work/HW/hm2/wrappers/MakeQCounters.vhd Line: 16
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakeMuxedQCounters.vhd
    Info (12022): Found design unit 1: MakeMuxedQCounters-dataflow File: /work/HW/hm2/wrappers/MakeMuxedQCounters.vhd Line: 62
    Info (12023): Found entity 1: MakeMuxedQCounters File: /work/HW/hm2/wrappers/MakeMuxedQCounters.vhd Line: 16
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakePwmgens.vhd
    Info (12022): Found design unit 1: MakePWMgens-dataflow File: /work/HW/hm2/wrappers/MakePwmgens.vhd Line: 62
    Info (12023): Found entity 1: MakePWMgens File: /work/HW/hm2/wrappers/MakePwmgens.vhd Line: 16
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakeTPPWMGens.vhd
    Info (12022): Found design unit 1: MakeTPPWMGens-dataflow File: /work/HW/hm2/wrappers/MakeTPPWMGens.vhd Line: 62
    Info (12023): Found entity 1: MakeTPPWMGens File: /work/HW/hm2/wrappers/MakeTPPWMGens.vhd Line: 16
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakeSPIs.vhd
    Info (12022): Found design unit 1: MakeSPIs-dataflow File: /work/HW/hm2/wrappers/MakeSPIs.vhd Line: 63
    Info (12023): Found entity 1: MakeSPIs File: /work/HW/hm2/wrappers/MakeSPIs.vhd Line: 16
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakeBSPIs.vhd
    Info (12022): Found design unit 1: MakeBSPIs-dataflow File: /work/HW/hm2/wrappers/MakeBSPIs.vhd Line: 65
    Info (12023): Found entity 1: MakeBSPIs File: /work/HW/hm2/wrappers/MakeBSPIs.vhd Line: 16
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakeDBSPIs.vhd
    Info (12022): Found design unit 1: MakeDBSPIs-dataflow File: /work/HW/hm2/wrappers/MakeDBSPIs.vhd Line: 67
    Info (12023): Found entity 1: MakeDBSPIs File: /work/HW/hm2/wrappers/MakeDBSPIs.vhd Line: 16
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakeSSerials.vhd
    Info (12022): Found design unit 1: MakeSSerials-dataflow File: /work/HW/hm2/wrappers/MakeSSerials.vhd Line: 71
    Info (12023): Found entity 1: MakeSSerials File: /work/HW/hm2/wrappers/MakeSSerials.vhd Line: 18
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/kubstepgenzi.vhd
    Info (12022): Found design unit 1: stepgeni-Behavioral File: /work/HW/hm2/kubstepgenzi.vhd Line: 111
    Info (12023): Found entity 1: stepgeni File: /work/HW/hm2/kubstepgenzi.vhd Line: 73
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/kubstepgenz.vhd
    Info (12022): Found design unit 1: stepgen-Behavioral File: /work/HW/hm2/kubstepgenz.vhd Line: 108
    Info (12023): Found entity 1: stepgen File: /work/HW/hm2/kubstepgenz.vhd Line: 73
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wordrb.vhd
    Info (12022): Found design unit 1: wordrb-behavioral File: /work/HW/hm2/wordrb.vhd Line: 79
    Info (12023): Found entity 1: wordrb File: /work/HW/hm2/wordrb.vhd Line: 70
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wordpr.vhd
    Info (12022): Found design unit 1: wordpr-behavioral File: /work/HW/hm2/wordpr.vhd Line: 92
    Info (12023): Found entity 1: wordpr File: /work/HW/hm2/wordpr.vhd Line: 70
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/watchdog.vhd
    Info (12022): Found design unit 1: watchdog-Behavioral File: /work/HW/hm2/watchdog.vhd Line: 88
    Info (12023): Found entity 1: watchdog File: /work/HW/hm2/watchdog.vhd Line: 72
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/pwmrefh.vhd
    Info (12022): Found design unit 1: pwmrefh-behavioral File: /work/HW/hm2/pwmrefh.vhd Line: 86
    Info (12023): Found entity 1: pwmrefh File: /work/HW/hm2/pwmrefh.vhd Line: 70
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/pwmpdmgenh.vhd
    Info (12022): Found design unit 1: pwmpdmgenh-behavioral File: /work/HW/hm2/pwmpdmgenh.vhd Line: 88
    Info (12023): Found entity 1: pwmpdmgenh File: /work/HW/hm2/pwmpdmgenh.vhd Line: 70
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/irqlogics.vhd
    Info (12022): Found design unit 1: irqlogics-Behavioral File: /work/HW/hm2/irqlogics.vhd Line: 85
    Info (12023): Found entity 1: irqlogics File: /work/HW/hm2/irqlogics.vhd Line: 70
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/hostmotid.vhd
    Info (12022): Found design unit 1: hostmotid-Behavioral File: /work/HW/hm2/hostmotid.vhd Line: 85
    Info (12023): Found entity 1: hostmotid File: /work/HW/hm2/hostmotid.vhd Line: 72
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/hmtimers.vhd
    Info (12022): Found design unit 1: hm2dpll-behavioral File: /work/HW/hm2/hmtimers.vhd Line: 95
    Info (12023): Found entity 1: hm2dpll File: /work/HW/hm2/hmtimers.vhd Line: 69
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/drqlogic.vhd
    Info (12022): Found design unit 1: dmdrqlogic-Behavioral File: /work/HW/hm2/drqlogic.vhd Line: 21
    Info (12023): Found entity 1: dmdrqlogic File: /work/HW/hm2/drqlogic.vhd Line: 8
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/boutreg.vhd
    Info (12022): Found design unit 1: boutreg-Behavioral File: /work/HW/hm2/boutreg.vhd Line: 87
    Info (12023): Found entity 1: boutreg File: /work/HW/hm2/boutreg.vhd Line: 70
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/ubrategen.vhd
    Info (12022): Found design unit 1: rategen-Behavioral File: /work/HW/hm2/ubrategen.vhd Line: 80
    Info (12023): Found entity 1: rategen File: /work/HW/hm2/ubrategen.vhd Line: 70
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/qcountersf.vhd
    Info (12022): Found design unit 1: qcounter-behavioral File: /work/HW/hm2/qcountersf.vhd Line: 91
    Info (12023): Found entity 1: qcounter File: /work/HW/hm2/qcountersf.vhd Line: 70
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/qcounterate.vhd
    Info (12022): Found design unit 1: qcounterate-Behavioral File: /work/HW/hm2/qcounterate.vhd Line: 80
    Info (12023): Found entity 1: qcounterate File: /work/HW/hm2/qcounterate.vhd Line: 71
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/qcountersfp.vhd
    Info (12022): Found design unit 1: qcounterp-behavioral File: /work/HW/hm2/qcountersfp.vhd Line: 92
    Info (12023): Found entity 1: qcounterp File: /work/HW/hm2/qcountersfp.vhd Line: 70
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/timestamp.vhd
    Info (12022): Found design unit 1: timestamp-Behavioral File: /work/HW/hm2/timestamp.vhd Line: 82
    Info (12023): Found entity 1: timestamp File: /work/HW/hm2/timestamp.vhd Line: 72
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/qcounteratesk.vhd
    Info (12022): Found design unit 1: qcounteratesk-Behavioral File: /work/HW/hm2/qcounteratesk.vhd Line: 84
    Info (12023): Found entity 1: qcounteratesk File: /work/HW/hm2/qcounteratesk.vhd Line: 74
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/srl16delay.vhd
    Info (12022): Found design unit 1: srl16delay-Behavioral File: /work/HW/hm2/srl16delay.vhd Line: 78
    Info (12023): Found entity 1: srl16delay File: /work/HW/hm2/srl16delay.vhd Line: 70
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/bufferedspi.vhd
    Info (12022): Found design unit 1: bufferedspi-behavioral File: /work/HW/hm2/bufferedspi.vhd Line: 94
    Info (12023): Found entity 1: bufferedspi File: /work/HW/hm2/bufferedspi.vhd Line: 70
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/threephasepwm.vhd
    Info (12022): Found design unit 1: threephasepwm-behavioral File: /work/HW/hm2/threephasepwm.vhd Line: 95
    Info (12023): Found entity 1: threephasepwm File: /work/HW/hm2/threephasepwm.vhd Line: 70
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/simplespix.vhd
    Info (12022): Found design unit 1: simplespi-behavioral File: /work/HW/hm2/simplespix.vhd Line: 92
    Info (12023): Found entity 1: simplespi File: /work/HW/hm2/simplespix.vhd Line: 70
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/idrom.vhd
    Info (12022): Found design unit 1: IDROM-syn File: /work/HW/hm2/idrom.vhd Line: 104
    Info (12023): Found entity 1: IDROM File: /work/HW/hm2/idrom.vhd Line: 73
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/sslbprom.vhd
    Info (12022): Found design unit 1: sslbp-syn File: /work/HW/hm2/sslbprom.vhd Line: 20
    Info (12023): Found entity 1: sslbp File: /work/HW/hm2/sslbprom.vhd Line: 9
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/sslbpram.vhd
    Info (12022): Found design unit 1: sslbpram-syn File: /work/HW/hm2/sslbpram.vhd Line: 20
    Info (12023): Found entity 1: sslbpram File: /work/HW/hm2/sslbpram.vhd Line: 9
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/adpram.vhd
    Info (12022): Found design unit 1: adpram-syn File: /work/HW/hm2/adpram.vhd Line: 86
    Info (12023): Found entity 1: adpram File: /work/HW/hm2/adpram.vhd Line: 71
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/uartx8.vhd
    Info (12022): Found design unit 1: uartx8-Behavioral File: /work/HW/hm2/uartx8.vhd Line: 93
    Info (12023): Found entity 1: uartx8 File: /work/HW/hm2/uartx8.vhd Line: 71
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/uartr8.vhd
    Info (12022): Found design unit 1: uartr8-Behavioral File: /work/HW/hm2/uartr8.vhd Line: 95
    Info (12023): Found entity 1: uartr8 File: /work/HW/hm2/uartr8.vhd Line: 73
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/sserialwa.vhd
    Info (12022): Found design unit 1: sserialwa-Behavioral File: /work/HW/hm2/sserialwa.vhd Line: 107
    Info (12023): Found entity 1: sserialwa File: /work/HW/hm2/sserialwa.vhd Line: 75
Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/d8o8sqws.vhd
    Info (12022): Found design unit 1: DumbAss8sqws-Behavioral File: /work/HW/hm2/d8o8sqws.vhd Line: 132
    Info (12023): Found entity 1: DumbAss8sqws File: /work/HW/hm2/d8o8sqws.vhd Line: 108
Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/QuartusProjects/Common/capsense.sv
    Info (12023): Found entity 1: capsense File: /work/HW/QuartusProjects/Common/capsense.sv Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/cv-ip/edge_detect/altera_edge_detector.v
    Info (12023): Found entity 1: altera_edge_detector File: /work/HW/cv-ip/edge_detect/altera_edge_detector.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/QuartusProjects/Common/top_io_modules.sv
    Info (12023): Found entity 1: top_io_modules File: /work/HW/QuartusProjects/Common/top_io_modules.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/cv-ip/debounce/debounce.v
    Info (12023): Found entity 1: debounce File: /work/HW/cv-ip/debounce/debounce.v Line: 13
Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/cv-ip/altsource_probe/hps_reset.v
    Info (12023): Found entity 1: hps_reset File: /work/HW/cv-ip/altsource_probe/hps_reset.v Line: 40
Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/cv-ip/intr_capturer/intr_capturer.v
    Info (12023): Found entity 1: intr_capturer File: /work/HW/cv-ip/intr_capturer/intr_capturer.v Line: 13
Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/QuartusProjects/Common/led_blinker.sv
    Info (12023): Found entity 1: led_blinker File: /work/HW/QuartusProjects/Common/led_blinker.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/soc_system.v
    Info (12023): Found entity 1: soc_system File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/soc_system.v Line: 6
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_reset_controller.v
    Info (12023): Found entity 1: altera_reset_controller File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_reset_controller.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_reset_synchronizer.v
    Info (12023): Found entity 1: altera_reset_synchronizer File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_reset_synchronizer.v Line: 24
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_irq_mapper_001.sv
    Info (12023): Found entity 1: soc_system_irq_mapper_001 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_irq_mapper_001.sv Line: 31
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_irq_mapper.sv
    Info (12023): Found entity 1: soc_system_irq_mapper File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_irq_mapper.sv Line: 31
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_2.v
    Info (12023): Found entity 1: soc_system_mm_interconnect_2 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_2.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_width_adapter.sv
    Info (12023): Found entity 1: altera_merlin_width_adapter File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_width_adapter.sv Line: 25
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_address_alignment.sv
    Info (12023): Found entity 1: altera_merlin_address_alignment File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv Line: 26
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv
    Info (12023): Found entity 1: altera_merlin_burst_uncompressor File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv Line: 40
Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/altera_merlin_arbitrator.sv
    Info (12023): Found entity 1: altera_merlin_arbitrator File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 103
    Info (12023): Found entity 2: altera_merlin_arb_adder File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 228
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_2_rsp_mux.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_2_rsp_mux File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_2_rsp_mux.sv Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_2_rsp_demux.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_2_rsp_demux File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_2_rsp_demux.sv Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_2_cmd_mux.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_2_cmd_mux File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_2_cmd_mux.sv Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_2_cmd_demux.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_2_cmd_demux File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_2_cmd_demux.sv Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_traffic_limiter.sv
    Info (12023): Found entity 1: altera_merlin_traffic_limiter File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_traffic_limiter.sv Line: 49
Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/altera_merlin_reorder_memory.sv
    Info (12023): Found entity 1: altera_merlin_reorder_memory File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_reorder_memory.sv Line: 28
    Info (12023): Found entity 2: memory_pointer_controller File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_reorder_memory.sv Line: 185
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_sc_fifo.v
    Info (12023): Found entity 1: altera_avalon_sc_fifo File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_sc_fifo.v Line: 21
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v
    Info (12023): Found entity 1: altera_avalon_st_pipeline_base File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v Line: 22
Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_2_router_001.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_2_router_001_default_decode File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_2_router_001.sv Line: 45
    Info (12023): Found entity 2: soc_system_mm_interconnect_2_router_001 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_2_router_001.sv Line: 84
Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_2_router.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_2_router_default_decode File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_2_router.sv Line: 45
    Info (12023): Found entity 2: soc_system_mm_interconnect_2_router File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_2_router.sv Line: 84
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_axi_slave_ni.sv
    Info (12023): Found entity 1: altera_merlin_axi_slave_ni File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_axi_slave_ni.sv Line: 22
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_master_agent.sv
    Info (12023): Found entity 1: altera_merlin_master_agent File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_master_agent.sv Line: 28
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_master_translator.sv
    Info (12023): Found entity 1: altera_merlin_master_translator File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_master_translator.sv Line: 32
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1.v
    Info (12023): Found entity 1: soc_system_mm_interconnect_1 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_avalon_st_adapter_005.v
    Info (12023): Found entity 1: soc_system_mm_interconnect_1_avalon_st_adapter_005 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_avalon_st_adapter_005.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_avalon_st_adapter_005_error_adapter_0.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_1_avalon_st_adapter_005_error_adapter_0 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_avalon_st_adapter_005_error_adapter_0.sv Line: 66
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter.v
    Info (12023): Found entity 1: soc_system_mm_interconnect_0_avalon_st_adapter File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv Line: 66
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_rsp_mux_001.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_1_rsp_mux_001 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_rsp_mux_001.sv Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_rsp_mux.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_1_rsp_mux File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_rsp_mux.sv Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_rsp_demux_007.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_1_rsp_demux_007 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_rsp_demux_007.sv Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_rsp_demux.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_1_rsp_demux File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_rsp_demux.sv Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_cmd_mux_007.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_1_cmd_mux_007 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_cmd_mux_007.sv Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_cmd_mux.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_1_cmd_mux File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_cmd_mux.sv Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_cmd_demux_001.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_1_cmd_demux_001 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_cmd_demux_001.sv Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_cmd_demux.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_1_cmd_demux File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_cmd_demux.sv Line: 43
Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router_009.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_1_router_009_default_decode File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router_009.sv Line: 45
    Info (12023): Found entity 2: soc_system_mm_interconnect_1_router_009 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router_009.sv Line: 84
Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router_007.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_1_router_007_default_decode File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router_007.sv Line: 45
    Info (12023): Found entity 2: soc_system_mm_interconnect_1_router_007 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router_007.sv Line: 84
Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router_002.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_1_router_002_default_decode File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router_002.sv Line: 45
    Info (12023): Found entity 2: soc_system_mm_interconnect_1_router_002 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router_002.sv Line: 84
Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router_001.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_1_router_001_default_decode File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router_001.sv Line: 45
    Info (12023): Found entity 2: soc_system_mm_interconnect_1_router_001 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router_001.sv Line: 84
Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_1_router_default_decode File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router.sv Line: 45
    Info (12023): Found entity 2: soc_system_mm_interconnect_1_router File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router.sv Line: 84
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_slave_agent.sv
    Info (12023): Found entity 1: altera_merlin_slave_agent File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_slave_translator.sv
    Info (12023): Found entity 1: altera_merlin_slave_translator File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_slave_translator.sv Line: 35
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0.v
    Info (12023): Found entity 1: soc_system_mm_interconnect_0 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_mux.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_0_rsp_mux File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_mux.sv Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_demux.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_0_rsp_demux File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_demux.sv Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_mux.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_0_cmd_mux File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_mux.sv Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_demux.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_0_cmd_demux File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_demux.sv Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_burst_adapter.sv
    Info (12023): Found entity 1: altera_merlin_burst_adapter File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 21
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv
    Info (12023): Found entity 1: altera_merlin_burst_adapter_uncompressed_only File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv Line: 39
Info (12021): Found 5 design units, including 5 entities, in source file soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv
    Info (12023): Found entity 1: altera_merlin_burst_adapter_burstwrap_increment File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 40
    Info (12023): Found entity 2: altera_merlin_burst_adapter_adder File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 55
    Info (12023): Found entity 3: altera_merlin_burst_adapter_subtractor File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 77
    Info (12023): Found entity 4: altera_merlin_burst_adapter_min File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 98
    Info (12023): Found entity 5: altera_merlin_burst_adapter_13_1 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 264
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_burst_adapter_new.sv
    Info (12023): Found entity 1: altera_merlin_burst_adapter_new File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_adapter_new.sv Line: 25
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_incr_burst_converter.sv
    Info (12023): Found entity 1: altera_incr_burst_converter File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_incr_burst_converter.sv Line: 28
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_wrap_burst_converter.sv
    Info (12023): Found entity 1: altera_wrap_burst_converter File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_wrap_burst_converter.sv Line: 27
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_default_burst_converter.sv
    Info (12023): Found entity 1: altera_default_burst_converter File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_default_burst_converter.sv Line: 30
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv
    Info (12023): Found entity 1: altera_avalon_st_pipeline_stage File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv Line: 22
Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_0_router_002_default_decode File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv Line: 45
    Info (12023): Found entity 2: soc_system_mm_interconnect_0_router_002 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv Line: 84
Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_0_router_default_decode File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv Line: 45
    Info (12023): Found entity 2: soc_system_mm_interconnect_0_router File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv Line: 84
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_axi_master_ni.sv
    Info (12023): Found entity 1: altera_merlin_axi_master_ni File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_merlin_axi_master_ni.sv Line: 27
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_sysid_qsys.v
    Info (12023): Found entity 1: soc_system_sysid_qsys File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_sysid_qsys.v Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_pll_0.v
    Info (12023): Found entity 1: soc_system_pll_0 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_pll_0.v Line: 2
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_onchip_memory2_0.v
    Info (12023): Found entity 1: soc_system_onchip_memory2_0 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_onchip_memory2_0.v Line: 21
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_mm_bridge.v
    Info (12023): Found entity 1: altera_avalon_mm_bridge File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_mm_bridge.v Line: 25
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_led_pio.v
    Info (12023): Found entity 1: soc_system_led_pio File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_led_pio.v Line: 21
Info (12021): Found 5 design units, including 5 entities, in source file soc_system/synthesis/submodules/soc_system_jtag_uart.v
    Info (12023): Found entity 1: soc_system_jtag_uart_sim_scfifo_w File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_jtag_uart.v Line: 21
    Info (12023): Found entity 2: soc_system_jtag_uart_scfifo_w File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_jtag_uart.v Line: 77
    Info (12023): Found entity 3: soc_system_jtag_uart_sim_scfifo_r File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_jtag_uart.v Line: 162
    Info (12023): Found entity 4: soc_system_jtag_uart_scfifo_r File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_jtag_uart.v Line: 240
    Info (12023): Found entity 5: soc_system_jtag_uart File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_jtag_uart.v Line: 327
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/intr_capturer.v
    Info (12023): Found entity 1: intr_capturer File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/intr_capturer.v Line: 13
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_hps_0.v
    Info (12023): Found entity 1: soc_system_hps_0 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_hps_0.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_hps_0_hps_io.v
    Info (12023): Found entity 1: soc_system_hps_0_hps_io File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_hps_0_hps_io.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram.v
    Info (12023): Found entity 1: hps_sdram File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/hps_sdram.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_mem_if_oct_cyclonev.sv
    Info (12023): Found entity 1: altera_mem_if_oct_cyclonev File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_mem_if_oct_cyclonev.sv Line: 23
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_acv_ldc.v
    Info (12023): Found entity 1: hps_sdram_p0_acv_ldc File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_acv_ldc.v Line: 17
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0.sv
    Info (12023): Found entity 1: hps_sdram_p0 File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/hps_sdram_p0.sv Line: 18
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_reset.v
    Info (12023): Found entity 1: hps_sdram_p0_reset File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_reset.v Line: 18
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v
    Info (12023): Found entity 1: hps_sdram_p0_acv_hard_memphy File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 21
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv
    Info (12023): Found entity 1: altdq_dqs2_acv_connect_to_hard_phy_cyclonev File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv Line: 19
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_mem_if_dll_cyclonev.sv
    Info (12023): Found entity 1: altera_mem_if_dll_cyclonev File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_mem_if_dll_cyclonev.sv Line: 23
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_reset_sync.v
    Info (12023): Found entity 1: hps_sdram_p0_reset_sync File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_reset_sync.v Line: 17
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v
    Info (12023): Found entity 1: altera_mem_if_hhp_qseq_synth_top File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v Line: 15
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_pll.sv
    Info (12023): Found entity 1: hps_sdram_pll File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/hps_sdram_pll.sv Line: 25
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_altdqdqs.v
    Info (12023): Found entity 1: hps_sdram_p0_altdqdqs File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_altdqdqs.v Line: 17
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v
    Info (12023): Found entity 1: hps_sdram_p0_acv_hard_io_pads File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 17
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_generic_ddio.v
    Info (12023): Found entity 1: hps_sdram_p0_generic_ddio File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_generic_ddio.v Line: 17
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v
    Info (12023): Found entity 1: hps_sdram_p0_acv_hard_addr_cmd_pads File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 17
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv
    Info (12023): Found entity 1: altera_mem_if_hard_memory_controller_top_cyclonev File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 18
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_phy_csr.sv
    Info (12023): Found entity 1: hps_sdram_p0_phy_csr File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_phy_csr.sv Line: 31
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v
    Info (12023): Found entity 1: hps_sdram_p0_clock_pair_generator File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v Line: 29
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_iss_probe.v
    Info (12023): Found entity 1: hps_sdram_p0_iss_probe File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_iss_probe.v Line: 17
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_hps_0_hps_io_border.sv
    Info (12023): Found entity 1: soc_system_hps_0_hps_io_border File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_hps_0_hps_io_border.sv Line: 14
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv
    Info (12023): Found entity 1: soc_system_hps_0_fpga_interfaces File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv Line: 14
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hm2reg_io.v
    Info (12023): Found entity 1: hm2reg_io File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/hm2reg_io.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_fpga_only_master.v
    Info (12023): Found entity 1: soc_system_fpga_only_master File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_fpga_only_master.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_fpga_only_master_p2b_adapter.sv
    Info (12023): Found entity 1: soc_system_fpga_only_master_p2b_adapter File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_fpga_only_master_p2b_adapter.sv Line: 55
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_fpga_only_master_b2p_adapter.sv
    Info (12023): Found entity 1: soc_system_fpga_only_master_b2p_adapter File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_fpga_only_master_b2p_adapter.sv Line: 55
Info (12021): Found 7 design units, including 7 entities, in source file soc_system/synthesis/submodules/altera_avalon_packets_to_master.v
    Info (12023): Found entity 1: altera_avalon_packets_to_master File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_packets_to_master.v Line: 22
    Info (12023): Found entity 2: packets_to_fifo File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_packets_to_master.v Line: 142
    Info (12023): Found entity 3: fifo_buffer_single_clock_fifo File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_packets_to_master.v Line: 512
    Info (12023): Found entity 4: fifo_buffer_scfifo_with_controls File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_packets_to_master.v Line: 573
    Info (12023): Found entity 5: fifo_buffer File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_packets_to_master.v Line: 627
    Info (12023): Found entity 6: fifo_to_packet File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_packets_to_master.v Line: 697
    Info (12023): Found entity 7: packets_to_master File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_packets_to_master.v Line: 851
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_packets_to_bytes.v
    Info (12023): Found entity 1: altera_avalon_st_packets_to_bytes File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_st_packets_to_bytes.v Line: 19
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_bytes_to_packets.v
    Info (12023): Found entity 1: altera_avalon_st_bytes_to_packets File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_st_bytes_to_packets.v Line: 19
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_fpga_only_master_timing_adt.sv
    Info (12023): Found entity 1: soc_system_fpga_only_master_timing_adt File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_fpga_only_master_timing_adt.sv Line: 60
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_jtag_interface.v
    Info (12023): Found entity 1: altera_avalon_st_jtag_interface File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_st_jtag_interface.v Line: 20
Info (12021): Found 3 design units, including 3 entities, in source file soc_system/synthesis/submodules/altera_jtag_dc_streaming.v
    Info (12023): Found entity 1: altera_jtag_control_signal_crosser File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_jtag_dc_streaming.v Line: 30
    Info (12023): Found entity 2: altera_jtag_src_crosser File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_jtag_dc_streaming.v Line: 72
    Info (12023): Found entity 3: altera_jtag_dc_streaming File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_jtag_dc_streaming.v Line: 135
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_jtag_sld_node.v
    Info (12023): Found entity 1: altera_jtag_sld_node File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_jtag_sld_node.v Line: 17
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_jtag_streaming.v
    Info (12023): Found entity 1: altera_jtag_streaming File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_jtag_streaming.v Line: 18
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_clock_crosser.v
    Info (12023): Found entity 1: altera_avalon_st_clock_crosser File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_st_clock_crosser.v Line: 22
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_std_synchronizer_nocut.v
    Info (12023): Found entity 1: altera_std_synchronizer_nocut File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_std_synchronizer_nocut.v Line: 44
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_idle_remover.v
    Info (12023): Found entity 1: altera_avalon_st_idle_remover File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_st_idle_remover.v Line: 19
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_idle_inserter.v
    Info (12023): Found entity 1: altera_avalon_st_idle_inserter File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/altera_avalon_st_idle_inserter.v Line: 19
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_dipsw_pio.v
    Info (12023): Found entity 1: soc_system_dipsw_pio File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_dipsw_pio.v Line: 21
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_button_pio.v
    Info (12023): Found entity 1: soc_system_button_pio File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system/synthesis/submodules/soc_system_button_pio.v Line: 21
Info (12021): Found 1 design units, including 1 entities, in source file DE0_Nano_SoC_Cramps.sv
    Info (12023): Found entity 1: DE0_Nano_SoC_Cramps File: /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/DE0_Nano_SoC_Cramps.sv Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/cv-ip/ADC_LTC2308_FIFO/adc_data_fifo.v
    Info (12023): Found entity 1: adc_data_fifo File: /work/HW/cv-ip/ADC_LTC2308_FIFO/adc_data_fifo.v Line: 40
Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/QuartusProjects/Common/adc_ltc2308.v
    Info (12023): Found entity 1: adc_ltc2308 File: /work/HW/QuartusProjects/Common/adc_ltc2308.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/QuartusProjects/Common/adc_ltc2308_fifo.sv
    Info (12023): Found entity 1: adc_ltc2308_fifo File: /work/HW/QuartusProjects/Common/adc_ltc2308_fifo.sv Line: 7
Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/QuartusProjects/Common/bidir_io.sv
    Info (12023): Found entity 1: bidir_io File: /work/HW/QuartusProjects/Common/bidir_io.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/QuartusProjects/Common/gpio_adr_decoder_reg.sv
    Info (12023): Found entity 1: gpio_adr_decoder_reg File: /work/HW/QuartusProjects/Common/gpio_adr_decoder_reg.sv Line: 44
Error (10481): VHDL Use Clause error at MakeIOPorts.vhd(12): design library "pin" does not contain primary unit "Pintypes". Verify that the primary unit exists in the library and has been successfully compiled. File: /work/HW/hm2/wrappers/MakeIOPorts.vhd Line: 12
Error (10800): VHDL error at MakeIOPorts.vhd(12): selected name in use clause is not an expanded name File: /work/HW/hm2/wrappers/MakeIOPorts.vhd Line: 12
Error (10349): VHDL Association List error at hostmot3.vhd(240): formal "ThePinDesc" does not exist File: /work/HW/hm2/hostmot3.vhd Line: 240
Error (10346): VHDL error at hostmot3.vhd(238): formal port or parameter "IDROMType" must have actual or default value File: /work/HW/hm2/hostmot3.vhd Line: 238
Error (10784): HDL error at MakeIOPorts.vhd(23): see declaration for object "IDROMType" File: /work/HW/hm2/wrappers/MakeIOPorts.vhd Line: 23
Error (10346): VHDL error at hostmot3.vhd(238): formal port or parameter "OffsetToModules" must have actual or default value File: /work/HW/hm2/hostmot3.vhd Line: 238
Error (10784): HDL error at MakeIOPorts.vhd(26): see declaration for object "OffsetToModules" File: /work/HW/hm2/wrappers/MakeIOPorts.vhd Line: 26
Error (10346): VHDL error at hostmot3.vhd(238): formal port or parameter "OffsetToPinDesc" must have actual or default value File: /work/HW/hm2/hostmot3.vhd Line: 238
Error (10784): HDL error at MakeIOPorts.vhd(27): see declaration for object "OffsetToPinDesc" File: /work/HW/hm2/wrappers/MakeIOPorts.vhd Line: 27
Error (10346): VHDL error at hostmot3.vhd(238): formal port or parameter "ClockHigh" must have actual or default value File: /work/HW/hm2/hostmot3.vhd Line: 238
Error (10784): HDL error at MakeIOPorts.vhd(28): see declaration for object "ClockHigh" File: /work/HW/hm2/wrappers/MakeIOPorts.vhd Line: 28
Error (10346): VHDL error at hostmot3.vhd(238): formal port or parameter "ClockLow" must have actual or default value File: /work/HW/hm2/hostmot3.vhd Line: 238
Error (10784): HDL error at MakeIOPorts.vhd(29): see declaration for object "ClockLow" File: /work/HW/hm2/wrappers/MakeIOPorts.vhd Line: 29
Error (10346): VHDL error at hostmot3.vhd(238): formal port or parameter "BoardNameLow" must have actual or default value File: /work/HW/hm2/hostmot3.vhd Line: 238
Error (10784): HDL error at MakeIOPorts.vhd(30): see declaration for object "BoardNameLow" File: /work/HW/hm2/wrappers/MakeIOPorts.vhd Line: 30
Error (10346): VHDL error at hostmot3.vhd(238): formal port or parameter "BoardNameHigh" must have actual or default value File: /work/HW/hm2/hostmot3.vhd Line: 238
Error (10784): HDL error at MakeIOPorts.vhd(31): see declaration for object "BoardNameHigh" File: /work/HW/hm2/wrappers/MakeIOPorts.vhd Line: 31
Error (10346): VHDL error at hostmot3.vhd(238): formal port or parameter "FPGASize" must have actual or default value File: /work/HW/hm2/hostmot3.vhd Line: 238
Error (10784): HDL error at MakeIOPorts.vhd(32): see declaration for object "FPGASize" File: /work/HW/hm2/wrappers/MakeIOPorts.vhd Line: 32
Info (144001): Generated suppressed messages file /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/output_files/DE0_Nano_SoC_Cramps.map.smsg
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 19 errors, 3 warnings
    Error: Peak virtual memory: 1249 megabytes
    Error: Processing ended: Thu Oct 22 22:45:54 2020
    Error: Elapsed time: 00:06:35
    Error: Total CPU time (on all processors): 00:07:08
make: *** [stamp/quartus_pin_assignments.stamp] Error 3
Makefile:210: recipe for target 'stamp/quartus_pin_assignments.stamp' failed

BTW, the situation with Jenkins is why I am proponent of public infrastructure. That way it will be quickly reproducible and not dependent on any Machinekit organization member.

EDIT:
On the other hand, I get the same error when building master branch. So...

the-snowwhite · 2020-10-22T23:42:23Z

That seem's like a correct run:
This Error:

Error (10481): VHDL Use Clause error at MakeIOPorts.vhd(12): design library "pin" does not contain primary unit "Pintypes". 
Verify that the primary unit exists in the library and has been successfully compiled. File: 
/work/HW/hm2/wrappers/MakeIOPorts.vhd Line: 12

Stems from this warning:

Warning (125092): Tcl Script File hm3_DE0_Nano_SoC_Cramps.qip not found

The problem is that:
travis_build.sh is broken:
it has to do more than just initiate the quartus build itself:

cd /work/HW/QuartusProjects/DE0_Nano_SoC_Cramps/
make -j$(nproc) rbf dts dtb

this file(hm3_DE0_Nano_SoC_Cramps.qip) is only generated when you initialize the build correctly by running some pre steps:

The way is pointed out in the readme (also if you do not do so next thing missing will be the firmware id memory file(.mif)):

Building a single CycloneV bit file:

build docker images from https://github.com/machinekit/mksocfpga.git

Launch a Docker build machine with the latest mksocfpga source code

docker pull cdsteinkuehler/jessie-quartus-15.1.2

git clone https://github.com/machinekit/mksocfpga.git/
cd mksocfpga
docker run -itv $(pwd):/work cdsteinkuehler/jessie-quartus-15.1.2 /bin/bash

# You should now have a command prompt for the Docker Quartus build image

Build the firmware-id protobuf bindings

# From the Docker Quartus build image command line, run:
cd /work/HW/firmware-tag
make TOPDIR=/work py-proto

See bitfile configs available in a project

# From the Docker Quartus build image command line, run:
cd /work/HW/QuartusProjects/<project>
./build.sh ?

Build the desired FPGA bit file

# From the Docker Quartus build image command line, run:
cd /work/HW/QuartusProjects/<project>
./build.sh <config>

As explained in machinekit#116 and machinekit#115, building and testing on Travis-ci.COM platform was always broken. To minimize changes to confuse users (as the runs are going to fail in their own repositories), let's remove these.

the-snowwhite · 2023-11-11T17:05:29Z

@cerna
I think if #117 solved this issue it can be closed ?

the-snowwhite mentioned this issue Oct 22, 2020

Addboard #115

Merged

the-snowwhite added the help wanted label Oct 22, 2020

the-snowwhite self-assigned this Oct 22, 2020

cerna mentioned this issue Oct 24, 2020

Remove Travis-CI recipes from codebase #117

Merged

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Mksocfpga Failing builds #116

Mksocfpga Failing builds #116

the-snowwhite commented Oct 22, 2020 •

edited

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cerna commented Oct 22, 2020

the-snowwhite commented Oct 22, 2020

cerna commented Oct 22, 2020 •

edited

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the-snowwhite commented Oct 22, 2020 •

edited

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the-snowwhite commented Nov 11, 2023

Mksocfpga Failing builds #116

Mksocfpga Failing builds #116

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the-snowwhite commented Oct 22, 2020 • edited Loading

cerna commented Oct 22, 2020

the-snowwhite commented Oct 22, 2020

cerna commented Oct 22, 2020 • edited Loading

the-snowwhite commented Oct 22, 2020 • edited Loading

Building a single CycloneV bit file:

Launch a Docker build machine with the latest mksocfpga source code

Build the firmware-id protobuf bindings

See bitfile configs available in a project

Build the desired FPGA bit file

the-snowwhite commented Nov 11, 2023

the-snowwhite commented Oct 22, 2020 •

edited

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cerna commented Oct 22, 2020 •

edited

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the-snowwhite commented Oct 22, 2020 •

edited

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