diff --git a/tools/topology/topology1/CMakeLists.txt b/tools/topology/topology1/CMakeLists.txt
index 37ed31c6b479..b181749ca6d9 100644
--- a/tools/topology/topology1/CMakeLists.txt
+++ b/tools/topology/topology1/CMakeLists.txt
@@ -29,6 +29,7 @@ set(TPLGS
 	"sof-hda-generic\;sof-hda-generic-4ch\;-DCHANNELS=4\;-DHSPROC=volume\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DDYNAMIC=1"
 	"sof-hda-generic\;sof-hda-generic-4ch-bt\;-DCHANNELS=4\;-DHSPROC=volume\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DDYNAMIC=1\;-DBT_OFFLOAD"
 	"sof-hda-generic\;sof-hda-generic-4ch-dts\;-DCHANNELS=4\;-DHSPROC=volume\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DDYNAMIC=1\;-DDTS=`DTS'"
+	"sof-hda-generic\;sof-hda-generic-4ch-waves\;-DCHANNELS=4\;-DHSPROC=volume\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DDYNAMIC=1\;-DWAVES"
 	## end HDaudio codec topologies
 
 	"sof-hda-generic-idisp\;sof-hda-generic-idisp\;-DCHANNELS=0\;-DDYNAMIC=1"
diff --git a/tools/topology/topology1/sof-hda-generic.m4 b/tools/topology/topology1/sof-hda-generic.m4
index cdd29df1d7d0..5b3dd078c186 100644
--- a/tools/topology/topology1/sof-hda-generic.m4
+++ b/tools/topology/topology1/sof-hda-generic.m4
@@ -46,6 +46,10 @@ define(`BT_PCM_ID', `8')
 define(`HW_CONFIG_ID', 8)
 include(`platform/intel/intel-generic-bt.m4')')
 
+# define HDA0_OUT DAI pipeline if the codec adapter is included.
+ifdef(`DTS',`define(PIPELINE_HDA0_OUT)')
+ifdef(`WAVES',`define(PIPELINE_HDA0_OUT)')
+
 # The pipeline naming notation is pipe-mixer-PROCESSING-dai-DIRECTION.m4
 # HSPROC is set by makefile, if not the default above is applied
 define(PIPE_HEADSET_PLAYBACK, `sof/pipe-mixer-`HSPROC'-dai-playback.m4')
@@ -107,18 +111,19 @@ DAI_ADD(PIPE_HEADSET_PLAYBACK,
 # Low Latency playback pipeline 1 on PCM 30 using max 2 channels of s32le.
 # 1000us deadline on core 0 with priority 0
 PIPELINE_PCM_ADD(
-	ifdef(`DTS', sof/pipe-eq-iir-dts-codec-playback.m4, sof/pipe-host-volume-playback.m4),
+	ifdef(`DTS', sof/pipe-eq-iir-dts-codec-playback.m4,
+	ifdef(`WAVES', sof/pipe-eq-iir-waves-codec-playback.m4, sof/pipe-host-volume-playback.m4)),
 	30, 0, 2, s32le,
 	1000, 0, 0,
 	48000, 48000, 48000,
 	SCHEDULE_TIME_DOMAIN_TIMER,
 	PIPELINE_PLAYBACK_SCHED_COMP_1)
 
-ifdef(`DTS',
+ifdef(`PIPELINE_HDA0_OUT',
 `
-# Because there is no dai pipeline.30 for HDA0.OUT in pipe-eq-iir-dts-codec-playback.m4, so
-# using macro defined W_PIPELINE_TOP() to add missing dai pipeline back. Instead of
-# modifying in pipe-eq-iir-dts-codec-playback.m4, these changes are not necessary for all others.
+# Because there is no dai pipeline.30 for HDA0.OUT in corresponding m4 file, so
+# using macro defined W_PIPELINE_TOP() to add missing dai pipeline back.
+# The changes are applying to connect codec adapter widget configuration.
 W_PIPELINE_TOP(30, HDA0.OUT, 1000, 0, 0, 1, pipe_dai_schedule_plat)
 ')
 
diff --git a/tools/topology/topology1/sof/pipe-eq-iir-waves-codec-playback.m4 b/tools/topology/topology1/sof/pipe-eq-iir-waves-codec-playback.m4
new file mode 100644
index 000000000000..4417dadc4dcd
--- /dev/null
+++ b/tools/topology/topology1/sof/pipe-eq-iir-waves-codec-playback.m4
@@ -0,0 +1,122 @@
+# Low Latency Passthrough with EQIIR and Waves codec Pipeline
+#
+# Pipeline Endpoints for connection are :
+#
+#  host PCM_P -- B0 --> EQIIR0 -> B1 --> Waves -- B2 --> sink DAI0
+#                                                              |
+
+DECLARE_SOF_RT_UUID("Waves codec", waves_codec_uuid, 0xd944281a, 0xafe9,
+		    0x4695, 0xa0, 0x43, 0xd7, 0xf6, 0x2b, 0x89, 0x53, 0x8e);
+define(`CA_UUID', waves_codec_uuid)
+
+# Include topology builder
+include(`utils.m4')
+include(`buffer.m4')
+include(`pcm.m4')
+include(`pga.m4')
+include(`bytecontrol.m4')
+include(`dai.m4')
+include(`pipeline.m4')
+include(`codec_adapter.m4')
+include(`eq_iir.m4')
+
+ifelse(PLATFORM, `tgl', `
+	define(SETUP_PARAMS_NAME, `MaxxChrome Setup' PIPELINE_ID)', `
+	define(SETUP_PARAMS_NAME, `Waves Codec Setup' PIPELINE_ID)')
+
+CONTROLBYTES_PRIV(PP_SETUP_CONFIG,
+`       bytes "0x53,0x4f,0x46,0x00,'
+`       0x00,0x00,0x00,0x00,'
+`       0x0c,0x00,0x00,0x00,'
+`       0x00,0x10,0x00,0x03,'
+`       0x00,0x00,0x00,0x00,'
+`       0x00,0x00,0x00,0x00,'
+`       0x00,0x00,0x00,0x00,'
+`       0x00,0x00,0x00,0x00,'
+`       0x00,0x00,0x00,0x00,'
+`       0x0c,0x00,0x00,0x00,'
+`       0x00,0x00,0x00,0x00"'
+)
+
+# Post process Bytes control for setup config
+C_CONTROLBYTES(SETUP_PARAMS_NAME, PIPELINE_ID,
+        CONTROLBYTES_OPS(bytes),
+        CONTROLBYTES_EXTOPS(void, 258, 258),
+        , , ,
+        CONTROLBYTES_MAX(, 8192),
+        ,
+        PP_SETUP_CONFIG)
+
+#
+# EQIIR
+#
+define(DEF_EQIIR_COEF, concat(`eqiir_coef_', PIPELINE_ID))
+define(DEF_EQIIR_PRIV, concat(`eqiir_priv_', PIPELINE_ID))
+
+# define filter. eq_iir_coef_flat.m4 is set by default
+ifdef(`PIPELINE_FILTER1', , `define(PIPELINE_FILTER1, eq_iir_coef_flat.m4)')
+include(PIPELINE_FILTER1)
+
+# EQ Bytes control with max value of 255
+C_CONTROLBYTES(DEF_EQIIR_COEF, PIPELINE_ID,
+	CONTROLBYTES_OPS(bytes, 258 binds the mixer control to bytes get/put handlers, 258, 258),
+	CONTROLBYTES_EXTOPS(258 binds the mixer control to bytes get/put handlers, 258, 258),
+	, , ,
+	CONTROLBYTES_MAX(, 1024),
+	,
+	DEF_EQIIR_PRIV)
+
+#
+# Components and Buffers
+#
+
+# Host "Low latency Playback" PCM
+# with 2 sink and 0 source periods
+W_PCM_PLAYBACK(PCM_ID, Low Latency Playback, 2, 0, SCHEDULE_CORE)
+
+W_CODEC_ADAPTER(0, PIPELINE_FORMAT, DAI_PERIODS, DAI_PERIODS, SCHEDULE_CORE,
+	LIST(`          ', "SETUP_PARAMS_NAME"))
+
+# "EQIIR0" has 2 sink period and 2 source periods
+W_EQ_IIR(0, PIPELINE_FORMAT, 2, 2, SCHEDULE_CORE,
+	LIST(`      ', "DEF_EQIIR_COEF"))
+
+# Low Latency Buffers
+W_BUFFER(0, COMP_BUFFER_SIZE(2,
+	COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)),
+	PLATFORM_HOST_MEM_CAP)
+W_BUFFER(1, COMP_BUFFER_SIZE(2,
+	COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)),
+	PLATFORM_COMP_MEM_CAP)
+W_BUFFER(2, COMP_BUFFER_SIZE(DAI_PERIODS,
+	COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)),
+	PLATFORM_COMP_MEM_CAP)
+
+#
+# Pipeline Graph
+#
+#  host PCM_P --> B0 --> EQ_IIR 0 --> B1 --> Waves Codec --> B2 --> sink DAI0
+
+P_GRAPH(pipe-eq-iir-waves-codec-playback, PIPELINE_ID,
+	LIST(`		',
+	`dapm(N_BUFFER(0), N_PCMP(PCM_ID))',
+	`dapm(N_EQ_IIR(0), N_BUFFER(0))',
+	`dapm(N_BUFFER(1), N_EQ_IIR(0))',
+	`dapm(N_CODEC_ADAPTER(0), N_BUFFER(1))',
+	`dapm(N_BUFFER(2), N_CODEC_ADAPTER(0))'))
+
+#
+# Pipeline Source and Sinks
+#
+indir(`define', concat(`PIPELINE_SOURCE_', PIPELINE_ID), N_BUFFER(2))
+indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Low Latency Playback PCM_ID)
+
+#
+# PCM Configuration
+#
+
+# PCM capabilities supported by FW
+PCM_CAPABILITIES(Low Latency Playback PCM_ID, CAPABILITY_FORMAT_NAME(PIPELINE_FORMAT), 48000, 48000, 2, PIPELINE_CHANNELS, 2, 16, 192, 16384, 65536, 65536)
+
+undefine(`DEF_EQIIR_COEF')
+undefine(`DEF_EQIIR_PRIV')