diff --git a/data/xbar_main.hjson b/data/xbar_main.hjson index 9510698a8..5416af0b7 100644 --- a/data/xbar_main.hjson +++ b/data/xbar_main.hjson @@ -38,7 +38,7 @@ xbar: false, addr_range: [{ base_addr: "0x00100000", - size_byte: "0x00040000", + size_byte: "0x00020000", }], }, { name: "hyperram", // HyperRAM memory @@ -58,7 +58,7 @@ xbar: false, addr_range: [{ base_addr: "0x30000000", - size_byte: "0x00004000", + size_byte: "0x00000800", }], }, { name: "gpio", // General purpose input and output diff --git a/data/xbar_main_generated.hjson b/data/xbar_main_generated.hjson index 6f3815ed5..aec8f2a19 100644 --- a/data/xbar_main_generated.hjson +++ b/data/xbar_main_generated.hjson @@ -38,7 +38,7 @@ xbar: false, addr_range: [{ base_addr: "0x00100000", - size_byte: "0x00040000", + size_byte: "0x00020000", }], }, { name: "hyperram", // HyperRAM memory @@ -58,7 +58,7 @@ xbar: false, addr_range: [{ base_addr: "0x30000000", - size_byte: "0x00004000", + size_byte: "0x00000800", }], }, { name: "gpio", // General purpose input and output diff --git a/dv/verilator/sonata_system_main.cc b/dv/verilator/sonata_system_main.cc index 8237d5835..ce76281af 100644 --- a/dv/verilator/sonata_system_main.cc +++ b/dv/verilator/sonata_system_main.cc @@ -8,7 +8,7 @@ int main(int argc, char **argv) { SonataSystem sonata_system( "TOP.top_verilator.u_sonata_system.u_sram_top.u_ram.gen_generic.u_impl_generic", 32 * 1024, // 32k words = 128 KiB - "TOP.top_verilator.u_sonata_system.g_hyperram.u_hyperram.u_hyperram_model.u_ram.gen_generic.u_impl_generic", + "TOP.top_verilator.u_sonata_system.u_hyperram.u_hyperram_model.u_ram.gen_generic.u_impl_generic", 256 * 1024 // 256k words = 1 MiB ); diff --git a/dv/verilator/sonata_verilator_lint.vlt b/dv/verilator/sonata_verilator_lint.vlt index 5bb412697..6e1fe596c 100644 --- a/dv/verilator/sonata_verilator_lint.vlt +++ b/dv/verilator/sonata_verilator_lint.vlt @@ -30,9 +30,6 @@ lint_off -rule UNOPTFLAT -file "*tlul_adapter_sram.sv" -match "*Signal unoptimiz // to the error responder for the HyperRAM disabled config). lint_off -rule UNOPTFLAT -file "*tlul_socket_m1.sv" -match "*Signal unoptimizable: Circular combinational logic: '*.u_hyperram_tl_socket.*'" -// False warning we're using 32-bit initial values for DisableHyperram parameter -lint_off -rule WIDTHTRUNC -file "*" -match "Operator VAR 'DisableHyperram' expects 1 bits on the Initial value*" - // Unimportant warning where compressed and uncompress instructions are printed in the same place. lint_off -rule WIDTHEXPAND -file "*ibex_controller.sv" -match "*Conditional True's VARREF 'instr_compressed_i' generates 16 bits." diff --git a/dv/verilator/top_verilator.sv b/dv/verilator/top_verilator.sv index d0ec78daf..4b80acb1a 100644 --- a/dv/verilator/top_verilator.sv +++ b/dv/verilator/top_verilator.sv @@ -6,8 +6,6 @@ module top_verilator (input logic clk_i, rst_ni); import sonata_pkg::*; - parameter bit DisableHyperram = 1'b0; - // System clock frequency. localparam int unsigned SysClkFreq = 40_000_000; // HyperRAM clock frequency. @@ -301,8 +299,7 @@ module top_verilator (input logic clk_i, rst_ni); sonata_system #( .CheriErrWidth ( CheriErrWidth ), .SysClkFreq ( SysClkFreq ), - .HRClkFreq ( HRClkFreq ), - .DisableHyperram ( DisableHyperram ) + .HRClkFreq ( HRClkFreq ) ) u_sonata_system ( // Main system clock and reset .clk_sys_i (clk_i), diff --git a/rtl/bus/tl_main_pkg.sv b/rtl/bus/tl_main_pkg.sv index 68f64db41..44d79a0c2 100644 --- a/rtl/bus/tl_main_pkg.sv +++ b/rtl/bus/tl_main_pkg.sv @@ -30,9 +30,9 @@ package tl_main_pkg; localparam logic [31:0] ADDR_SPACE_USBDEV = 32'h 80400000; localparam logic [31:0] ADDR_SPACE_RV_PLIC = 32'h 88000000; - localparam logic [31:0] ADDR_MASK_SRAM = 32'h 0003ffff; + localparam logic [31:0] ADDR_MASK_SRAM = 32'h 0001ffff; localparam logic [31:0] ADDR_MASK_HYPERRAM = 32'h 000fffff; - localparam logic [31:0] ADDR_MASK_REV_TAG = 32'h 00003fff; + localparam logic [31:0] ADDR_MASK_REV_TAG = 32'h 000007ff; localparam logic [31:0] ADDR_MASK_GPIO = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_PINMUX = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_RGBLED_CTRL = 32'h 00000fff; diff --git a/rtl/fpga/top_sonata.sv b/rtl/fpga/top_sonata.sv index 0697b3399..2d00cea48 100644 --- a/rtl/fpga/top_sonata.sv +++ b/rtl/fpga/top_sonata.sv @@ -206,7 +206,6 @@ module top_sonata parameter int unsigned HRClkFreq = 100_000_000; parameter SRAMInitFile = ""; - parameter DisableHyperram = 1'b0; // Main/board clock and reset logic main_clk_buf; @@ -270,8 +269,7 @@ module top_sonata .CheriErrWidth ( 9 ), .SRAMInitFile ( SRAMInitFile ), .SysClkFreq ( SysClkFreq ), - .HRClkFreq ( HRClkFreq ), - .DisableHyperram ( DisableHyperram ) + .HRClkFreq ( HRClkFreq ) ) u_sonata_system ( // Main system clock and reset .clk_sys_i (clk_sys), diff --git a/rtl/system/sonata_system.sv b/rtl/system/sonata_system.sv index 148c3df22..cdf1560b7 100644 --- a/rtl/system/sonata_system.sv +++ b/rtl/system/sonata_system.sv @@ -12,8 +12,7 @@ module sonata_system parameter int unsigned CheriErrWidth = 9, parameter SRAMInitFile = "", parameter int unsigned SysClkFreq = 30_000_000, - parameter int unsigned HRClkFreq = 100_000_000, - parameter bit DisableHyperram = 1'b0 + parameter int unsigned HRClkFreq = 100_000_000 ) ( // Main system clock and reset input logic clk_sys_i, @@ -107,7 +106,7 @@ module sonata_system // Signals, types and parameters for system. // /////////////////////////////////////////////// - localparam int unsigned MemSize = DisableHyperram ? 256 * 1024 : 128 * 1024; // 256 KiB + localparam int unsigned MemSize = 128 * 1024; // 128 KiB localparam int unsigned SRAMAddrWidth = $clog2(MemSize); localparam int unsigned HyperRAMSize = 1024 * 1024; // 1 MiB localparam int unsigned DebugStart = 32'h1a110000; @@ -499,54 +498,28 @@ module sonata_system .tl_b_o (tl_sram_b_d2h) ); - if (DisableHyperram) begin : g_no_hyperram - logic unused_clk_hr; - logic unused_clk_hr90p; - logic unused_clk_hr3x; - logic unused_rst_hr; - - assign unused_clk_hr = clk_hr_i; - assign unused_clk_hr90p = clk_hr90p_i; - assign unused_clk_hr3x = clk_hr3x_i; - assign unused_rst_hr = rst_hr_ni; - - assign hyperram_dq = '0; - assign hyperram_rwds = '0; - assign hyperram_ckp = 1'b0; - assign hyperram_ckn = 1'b0; - assign hyperram_nrst = 1'b0; - assign hyperram_cs = 1'b0; - - tlul_err_resp u_hyperram_err ( - .clk_i (clk_sys_i), - .rst_ni (rst_sys_ni), - .tl_h_i(tl_hyperram_ds_h2d), - .tl_h_o(tl_hyperram_ds_d2h) - ); - end else begin : g_hyperram - hyperram #( - .HRClkFreq (HRClkFreq), - .HyperRAMSize(HyperRAMSize) - ) u_hyperram ( - .clk_i (clk_sys_i), - .rst_ni (rst_sys_ni), - - .clk_hr_i, - .clk_hr90p_i, - .clk_hr3x_i, - .rst_hr_ni, - - .tl_i (tl_hyperram_ds_h2d), - .tl_o (tl_hyperram_ds_d2h), - - .hyperram_dq, - .hyperram_rwds, - .hyperram_ckp, - .hyperram_ckn, - .hyperram_nrst, - .hyperram_cs - ); - end + hyperram #( + .HRClkFreq (HRClkFreq), + .HyperRAMSize(HyperRAMSize) + ) u_hyperram ( + .clk_i (clk_sys_i), + .rst_ni (rst_sys_ni), + + .clk_hr_i, + .clk_hr90p_i, + .clk_hr3x_i, + .rst_hr_ni, + + .tl_i (tl_hyperram_ds_h2d), + .tl_o (tl_hyperram_ds_d2h), + + .hyperram_dq, + .hyperram_rwds, + .hyperram_ckp, + .hyperram_ckn, + .hyperram_nrst, + .hyperram_cs + ); // Manual M:1 socket instantiation as xbar generator cannot deal with multiple ports for one // device and we want to utilize the dual port SRAM. So totally separate crossbars are generated @@ -668,8 +641,8 @@ module sonata_system end end - // Size of revocation tag memory is 4 KiB, one bit for each 64 in SRAM - localparam int unsigned RevTagDepth = 4 * 1024 * 8 / BusDataWidth; + // Size of revocation tag memory is one bit for each 64 in SRAM. + localparam int unsigned RevTagDepth = (MemSize / 8) / BusDataWidth; localparam int unsigned RevTagAddrWidth = $clog2(RevTagDepth); tlul_adapter_sram #( diff --git a/sonata.core b/sonata.core index 24478917a..c54c8d75e 100644 --- a/sonata.core +++ b/sonata.core @@ -89,11 +89,6 @@ parameters: paramtype: vlogdefine description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric". - DisableHyperram: - datatype: bool - paramtype: vlogparam - description: Remove hyperram controller from the system (providing a larger SRAM) - USE_HYPERRAM_SIM_MODEL: datatype: bool paramtype: vlogdefine @@ -118,7 +113,6 @@ targets: parameters: - SRAMInitFile - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx - - DisableHyperram=false sim: <<: *default_target @@ -146,7 +140,6 @@ targets: - "--unroll-count 72" parameters: - PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric - - DisableHyperram=false - USE_HYPERRAM_SIM_MODEL=true lint: @@ -160,7 +153,6 @@ targets: mode: lint-only parameters: - PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric - - DisableHyperram=false # TODO: Introduce some blackboxes for the Xilinx IP used in the hyperram # controller so we can lint it, for now just exclude it from the lint run. - USE_HYPERRAM_SIM_MODEL=true diff --git a/sw/cheri/boot/boot.S b/sw/cheri/boot/boot.S index e2e43dcee..30fe67771 100644 --- a/sw/cheri/boot/boot.S +++ b/sw/cheri/boot/boot.S @@ -32,7 +32,7 @@ start: li a0, 0x30000000 csetaddr ca0, cs0, a0 li a1, 0 - li a2, 4096 + li a2, 2048 ccall bl_memset // Set cgp to correct location so globals can be used. diff --git a/sw/cheri/checks/revocation_test.cc b/sw/cheri/checks/revocation_test.cc index 97f1861c4..38df1e5f2 100644 --- a/sw/cheri/checks/revocation_test.cc +++ b/sw/cheri/checks/revocation_test.cc @@ -31,7 +31,7 @@ using namespace CHERI; uart.address() = UART_ADDRESS; uart.bounds() = UART_BOUNDS; - unsigned int size_of_revocation_tags = 0x4000; // 16 KiB + unsigned int size_of_revocation_tags = 0x0800; // 2 KiB unsigned int number_of_words = size_of_revocation_tags / 4; Capability revocation_tags = root.cast(); diff --git a/sw/cheri/common/boot.S b/sw/cheri/common/boot.S index 4a42831ec..827e3e9b3 100644 --- a/sw/cheri/common/boot.S +++ b/sw/cheri/common/boot.S @@ -80,7 +80,7 @@ start: li a0, 0x30000000 csetaddr ca0, cs0, a0 li a1, 0 - li a2, 4096 + li a2, 2048 ccall bl_memset // Set cgp to correct location so globals can be used.