disassembly printing

[ghost]

This is based on the https://github.com/lowRISC/riscv-llvm-integration repo at Latest commit 74e4050 on 3 Oct 2017.

Running llvm-objdump does not disassemble the instructions from the M extension and the jalr is formatted differently from the gnu objdump. Is this expected?

My command line is: (on windows msys2):
$ ./llvm-objdump.exe -arch=riscv32 -disassemble my_folder/riscv_blocks.elf

Corresponding gnu command:
$ bin/riscv64-unknown-elf-objdump.exe -d -M no-aliases blocks.elf

Sample output 1:
42000028: b7 57 c6 41 lui a5, 269413
4200002c: 93 87 d7 e6 addi a5, a5, -403
42000030: 33 07 f7 02
42000034: b7 07 00 42 lui a5, 270336
42000038: 23 a6 e7 2a sw a4, 684(a5)
4200003c: b7 07 00 42 lui a5, 270336

gnu objdump output: multiplication instruction expected (ignore hex/$ formatting/comments)
42000028: 41c657b7 lui a5,0x41c65
4200002c: e6d78793 addi a5,a5,-403 # 41c64e6d <STACK_SIZE+0x41c64a6d>
42000030: 02f70733 mul a4,a4,a5
42000034: 420007b7 lui a5,0x42000
42000038: 2ae7a623 sw a4,684(a5) # 420002ac
4200003c: 420007b7 lui a5,0x42000

Sample output 1: uses comma formatting for jalr

gnu objdump output: uses register offset bracket formatting for jalr (ignore hex/$ formatting/comments)
42000118: f8f714e3 bne a4,a5,420000a0 <draw_block+0x2c>
4200011c: 00000013 addi zero,zero,0
42000120: 03c12403 lw s0,60(sp)
42000124: 04010113 addi sp,sp,64
42000128: 00008067 jalr zero,0(ra)

The jalr difference can can be seen by using table-gen with gen-asm-writer option
$ ./bin/llvm-tblgen.exe -gen-asm-writer -I=../include -I=../lib/Target/RISCV ../lib/Target/RISCV/RISCV.td

[asb]

Thanks for the report Ben. The llvm-integration repo got somewhat out of date, as there seemed to be little interest in it. It was also hard to maintain as quite a few tablegen changes had to be backported. I'll likely give it another go with a llvm-integration branch based on the 6.0 release.

There are some known differences in behaviour between LLVM and GNU objdump. e.g. GNU objdump will eagerly try and disassemble instructions present in any known RISC-V extension, while LLVM requires the extension to be enabled explicitly. There were proposals to embed metadata in the generated ELF files to describe the ISA extensions being used, which would allow both tools to be more precise. I had been intending to wait for that proposal to materialise, but that's been taken longer than I expected. The reason for not removing this difference behaviour immediately is that the strictness of LLVM's objdump is quite useful when writing tests.

I can see that current binutils will assemble either jalr zero, ra, 0 or jalr zero, 0(ra), and as you observe it prefers to print the latter. I had assumed that jalr zero, ra, 0 was preferred, given that this is the form used throughout the ISA manual. I've opened an issue on the ISA manual for now to query this: riscv/riscv-isa-manual#145

If jalr $rd, $imm($rs1) is indeed the preferred form then I'd think jalr ($rs1) would be more consistent as a pseudoinstruction alias than jalr $rs1, but it seems RISC-V assembler syntax is fairly unprincipled (not to mention under-specified!)