[WIP] Added option to define subtile in tile_annotation section

[ganeshgore]

Motivate of the pull request

To support subtile feature of latest VPR.
Now you can define tile_name and sub_tile_name as follows.
sub_tile_name declaration is optional, if not defined it is same as tile_name

<tile_annotations>
    <global_port name="clk0" is_clock="true" default_val="0">
      <tile name="<tile_name>.<sub_tile_name>" port="clk[0:0]" x="-1" y="-1"/>

Describe the technical details

What is currently done? (Provide issue link if applicable)

What does this pull request change?

Which part of the code base require a change

• VPR
• Tileable routing architecture generator
• OpenFPGA libraries
• FPGA-Verilog
• FPGA-Bitstream
• FPGA-SDC
• FPGA-SPICE
• Flow scripts
• Architecture library
• Cell library
• Documentation
• Regression tests
• Continous Integration (CI) scripts

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.

[ganeshgore]

Is this already considered and merged? or we are waiting for more information?

[tangxifan]

@ganeshgore Can you resolve the merging conflicts? I will then review. You need a simple test case to validate this new feature.

[tangxifan]

@ganeshgore A good start on the subtile support. I think the tile annotation is where we should add more syntax. I will create an issue to detail the support we want. I will follow up on this PR.

[tangxifan]

@ganeshgore Changes are o.k. I will follow-up to finish the subtile support as planned in #916

[tangxifan]

Let me know if the changes on the python scripts are fine to merge. Then I will merge it.