From d0dfa97f58a183d7fab1e6ddf2ef29ba3b3c3f36 Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Wed, 24 Jan 2024 15:26:01 +0000 Subject: [PATCH] [FMV] Change feature priorities according to ACLE. This patch follows the latest ACLE specification as shown in PR https://github.com/ARM-software/acle/pull/279. It adjusts the priorities for FEAT_DOTPROD, FEAT_SM4, FEAT_FP16FML, FEAT_RDM. --- clang/test/CodeGen/attr-target-version.c | 30 +++++++++---------- .../llvm/TargetParser/AArch64TargetParser.h | 8 ++--- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/clang/test/CodeGen/attr-target-version.c b/clang/test/CodeGen/attr-target-version.c index feb6c094ab62b1..2a96697e4291b9 100644 --- a/clang/test/CodeGen/attr-target-version.c +++ b/clang/test/CodeGen/attr-target-version.c @@ -364,36 +364,36 @@ int hoo(void) { // CHECK-NEXT: ret ptr @fmv_inline._Mdpb2Mjscvt // CHECK: resolver_else22: // CHECK-NEXT: [[TMP48:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP49:%.*]] = and i64 [[TMP48]], 16400 -// CHECK-NEXT: [[TMP50:%.*]] = icmp eq i64 [[TMP49]], 16400 +// CHECK-NEXT: [[TMP49:%.*]] = and i64 [[TMP48]], 8 +// CHECK-NEXT: [[TMP50:%.*]] = icmp eq i64 [[TMP49]], 8 // CHECK-NEXT: [[TMP51:%.*]] = and i1 true, [[TMP50]] // CHECK-NEXT: br i1 [[TMP51]], label [[RESOLVER_RETURN23:%.*]], label [[RESOLVER_ELSE24:%.*]] // CHECK: resolver_return23: -// CHECK-NEXT: ret ptr @fmv_inline._MdotprodMaes +// CHECK-NEXT: ret ptr @fmv_inline._MsimdMfp16fml // CHECK: resolver_else24: // CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP53:%.*]] = and i64 [[TMP52]], 8 -// CHECK-NEXT: [[TMP54:%.*]] = icmp eq i64 [[TMP53]], 8 +// CHECK-NEXT: [[TMP53:%.*]] = and i64 [[TMP52]], 16400 +// CHECK-NEXT: [[TMP54:%.*]] = icmp eq i64 [[TMP53]], 16400 // CHECK-NEXT: [[TMP55:%.*]] = and i1 true, [[TMP54]] // CHECK-NEXT: br i1 [[TMP55]], label [[RESOLVER_RETURN25:%.*]], label [[RESOLVER_ELSE26:%.*]] // CHECK: resolver_return25: -// CHECK-NEXT: ret ptr @fmv_inline._Mfp16fmlMsimd +// CHECK-NEXT: ret ptr @fmv_inline._MdotprodMaes // CHECK: resolver_else26: // CHECK-NEXT: [[TMP56:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP57:%.*]] = and i64 [[TMP56]], 32 -// CHECK-NEXT: [[TMP58:%.*]] = icmp eq i64 [[TMP57]], 32 +// CHECK-NEXT: [[TMP57:%.*]] = and i64 [[TMP56]], 192 +// CHECK-NEXT: [[TMP58:%.*]] = icmp eq i64 [[TMP57]], 192 // CHECK-NEXT: [[TMP59:%.*]] = and i1 true, [[TMP58]] // CHECK-NEXT: br i1 [[TMP59]], label [[RESOLVER_RETURN27:%.*]], label [[RESOLVER_ELSE28:%.*]] // CHECK: resolver_return27: -// CHECK-NEXT: ret ptr @fmv_inline._Msm4Mfp +// CHECK-NEXT: ret ptr @fmv_inline._MlseMrdm // CHECK: resolver_else28: // CHECK-NEXT: [[TMP60:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP61:%.*]] = and i64 [[TMP60]], 192 -// CHECK-NEXT: [[TMP62:%.*]] = icmp eq i64 [[TMP61]], 192 +// CHECK-NEXT: [[TMP61:%.*]] = and i64 [[TMP60]], 32 +// CHECK-NEXT: [[TMP62:%.*]] = icmp eq i64 [[TMP61]], 32 // CHECK-NEXT: [[TMP63:%.*]] = and i1 true, [[TMP62]] // CHECK-NEXT: br i1 [[TMP63]], label [[RESOLVER_RETURN29:%.*]], label [[RESOLVER_ELSE30:%.*]] // CHECK: resolver_return29: -// CHECK-NEXT: ret ptr @fmv_inline._MrdmMlse +// CHECK-NEXT: ret ptr @fmv_inline._MfpMsm4 // CHECK: resolver_else30: // CHECK-NEXT: ret ptr @fmv_inline.default // @@ -659,21 +659,21 @@ int hoo(void) { // // // CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mfp16fmlMsimd +// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MsimdMfp16fml // CHECK-SAME: () #[[ATTR7]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 14 // // // CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msm4Mfp +// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfpMsm4 // CHECK-SAME: () #[[ATTR24:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 15 // // // CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MrdmMlse +// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MlseMrdm // CHECK-SAME: () #[[ATTR25:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 16 diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h index f5ec4bcd63725f..0dff2a0af9bd15 100644 --- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h +++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h @@ -222,7 +222,7 @@ inline constexpr ExtensionInfo Extensions[] = { {"d128", AArch64::AEK_D128, "+d128", "-d128", FEAT_INIT, "", 0}, {"dgh", AArch64::AEK_NONE, {}, {}, FEAT_DGH, "", 260}, {"dit", AArch64::AEK_NONE, {}, {}, FEAT_DIT, "+dit", 180}, - {"dotprod", AArch64::AEK_DOTPROD, "+dotprod", "-dotprod", FEAT_DOTPROD, "+dotprod,+fp-armv8,+neon", 50}, + {"dotprod", AArch64::AEK_DOTPROD, "+dotprod", "-dotprod", FEAT_DOTPROD, "+dotprod,+fp-armv8,+neon", 104}, {"dpb", AArch64::AEK_NONE, {}, {}, FEAT_DPB, "+ccpp", 190}, {"dpb2", AArch64::AEK_NONE, {}, {}, FEAT_DPB2, "+ccpp,+ccdp", 200}, {"ebf16", AArch64::AEK_NONE, {}, {}, FEAT_EBF16, "+bf16", 290}, @@ -233,7 +233,7 @@ inline constexpr ExtensionInfo Extensions[] = { {"flagm2", AArch64::AEK_NONE, {}, {}, FEAT_FLAGM2, "+flagm,+altnzcv", 30}, {"fp", AArch64::AEK_FP, "+fp-armv8", "-fp-armv8", FEAT_FP, "+fp-armv8,+neon", 90}, {"fp16", AArch64::AEK_FP16, "+fullfp16", "-fullfp16", FEAT_FP16, "+fullfp16,+fp-armv8,+neon", 170}, - {"fp16fml", AArch64::AEK_FP16FML, "+fp16fml", "-fp16fml", FEAT_FP16FML, "+fp16fml,+fullfp16,+fp-armv8,+neon", 40}, + {"fp16fml", AArch64::AEK_FP16FML, "+fp16fml", "-fp16fml", FEAT_FP16FML, "+fp16fml,+fullfp16,+fp-armv8,+neon", 175}, {"frintts", AArch64::AEK_NONE, {}, {}, FEAT_FRINTTS, "+fptoint", 250}, {"hbc", AArch64::AEK_HBC, "+hbc", "-hbc", FEAT_INIT, "", 0}, {"i8mm", AArch64::AEK_I8MM, "+i8mm", "-i8mm", FEAT_I8MM, "+i8mm", 270}, @@ -259,7 +259,7 @@ inline constexpr ExtensionInfo Extensions[] = { {"rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc", FEAT_RCPC, "+rcpc", 230}, {"rcpc2", AArch64::AEK_NONE, {}, {}, FEAT_RCPC2, "+rcpc", 240}, {"rcpc3", AArch64::AEK_RCPC3, "+rcpc3", "-rcpc3", FEAT_RCPC3, "+rcpc,+rcpc3", 241}, - {"rdm", AArch64::AEK_RDM, "+rdm", "-rdm", FEAT_RDM, "+rdm,+fp-armv8,+neon", 70}, + {"rdm", AArch64::AEK_RDM, "+rdm", "-rdm", FEAT_RDM, "+rdm,+fp-armv8,+neon", 108}, {"rng", AArch64::AEK_RAND, "+rand", "-rand", FEAT_RNG, "+rand", 10}, {"rpres", AArch64::AEK_NONE, {}, {}, FEAT_RPRES, "", 300}, {"sb", AArch64::AEK_SB, "+sb", "-sb", FEAT_SB, "+sb", 470}, @@ -267,7 +267,7 @@ inline constexpr ExtensionInfo Extensions[] = { {"sha2", AArch64::AEK_SHA2, "+sha2", "-sha2", FEAT_SHA2, "+sha2,+fp-armv8,+neon", 130}, {"sha3", AArch64::AEK_SHA3, "+sha3", "-sha3", FEAT_SHA3, "+sha3,+sha2,+fp-armv8,+neon", 140}, {"simd", AArch64::AEK_SIMD, "+neon", "-neon", FEAT_SIMD, "+fp-armv8,+neon", 100}, - {"sm4", AArch64::AEK_SM4, "+sm4", "-sm4", FEAT_SM4, "+sm4,+fp-armv8,+neon", 60}, + {"sm4", AArch64::AEK_SM4, "+sm4", "-sm4", FEAT_SM4, "+sm4,+fp-armv8,+neon", 106}, {"sme-f16f16", AArch64::AEK_SMEF16F16, "+sme-f16f16", "-sme-f16f16", FEAT_INIT, "", 0}, {"sme-f64f64", AArch64::AEK_SMEF64F64, "+sme-f64f64", "-sme-f64f64", FEAT_SME_F64, "+sme,+sme-f64f64,+bf16", 560}, {"sme-i16i64", AArch64::AEK_SMEI16I64, "+sme-i16i64", "-sme-i16i64", FEAT_SME_I64, "+sme,+sme-i16i64,+bf16", 570},