diff --git a/src/platform/intel/cavs/lib/CMakeLists.txt b/src/platform/intel/cavs/lib/CMakeLists.txt deleted file mode 100644 index 1ed93d8bf39a..000000000000 --- a/src/platform/intel/cavs/lib/CMakeLists.txt +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: BSD-3-Clause - -add_library(pdown STATIC "") -target_link_libraries(pdown sof_options) -target_compile_options(pdown PRIVATE -mtext-section-literals) - -add_local_sources(pdown power_down.S) -target_link_libraries(sof_static_libraries INTERFACE pdown) - -add_local_sources(sof - clk.c - dai.c - dma.c - memory.c - pm_runtime.c - pm_memory.c -) - -if(CONFIG_MEM_WND) - add_local_sources(sof mem_window.c) -endif() diff --git a/src/platform/intel/cavs/lib/clk.c b/src/platform/intel/cavs/lib/clk.c deleted file mode 100644 index b7b6fd8904d9..000000000000 --- a/src/platform/intel/cavs/lib/clk.c +++ /dev/null @@ -1,316 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2019 Intel Corporation. All rights reserved. -// -// Author: Janusz Jankowski - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -static SHARED_DATA struct clock_info platform_clocks_info[NUM_CLOCKS]; - -static inline void select_cpu_clock_hw(int freq_idx, bool release_unused) -{ - uint32_t enc = cpu_freq_enc[freq_idx]; - uint32_t status_mask = cpu_freq_status_mask[freq_idx]; - -#if CONFIG_TIGERLAKE - /* TGL specific HW recommended flow */ - if (freq_idx == CPU_HPRO_FREQ_IDX) - pm_runtime_get(PM_RUNTIME_DSP, PWRD_BY_HPRO | (CONFIG_CORE_COUNT - 1)); -#endif - - /* request clock */ - io_reg_write(SHIM_BASE + SHIM_CLKCTL, - io_reg_read(SHIM_BASE + SHIM_CLKCTL) | enc); - - /* wait for requested clock to be on */ - while ((io_reg_read(SHIM_BASE + SHIM_CLKSTS) & - status_mask) != status_mask) - idelay(PLATFORM_DEFAULT_DELAY); - - /* switch to requested clock */ - io_reg_update_bits(SHIM_BASE + SHIM_CLKCTL, - SHIM_CLKCTL_OSC_SOURCE_MASK, enc); - - if (release_unused) { - /* release other clocks */ - io_reg_write(SHIM_BASE + SHIM_CLKCTL, - (io_reg_read(SHIM_BASE + SHIM_CLKCTL) & - ~SHIM_CLKCTL_OSC_REQUEST_MASK) | enc); - } - -#if CONFIG_TIGERLAKE - /* TGL specific HW recommended flow */ - if (freq_idx != CPU_HPRO_FREQ_IDX) - pm_runtime_put(PM_RUNTIME_DSP, PWRD_BY_HPRO | (CONFIG_CORE_COUNT - 1)); -#endif - -#if CONFIG_DSP_RESIDENCY_COUNTERS - if (get_dsp_r_state() != r2_r_state) { - if (freq_idx == CPU_LPRO_FREQ_IDX) - report_dsp_r_state(r1_r_state); - else - report_dsp_r_state(r0_r_state); - } -#endif -} - -static void select_cpu_clock_unlocked(int freq_idx, bool release_unused) -{ - struct clock_info *clk_info = clocks_get(); - int i; - - /* change clock */ - select_cpu_clock_hw(freq_idx, release_unused); - for (i = 0; i < CONFIG_CORE_COUNT; i++) - clk_info[CLK_CPU(i)].current_freq_idx = freq_idx; -} - -static inline void select_cpu_clock(int freq_idx, bool release_unused) -{ - k_spinlock_key_t key; - - key = clock_lock(); - - select_cpu_clock_unlocked(freq_idx, release_unused); - - clock_unlock(key); -} - -/* USE_LPRO_IN_WAITI mode */ -#if CONFIG_CAVS_USE_LPRO_IN_WAITI - -/* Store clock source that was active before going to waiti, - * so it can be restored on wake up. - */ -static SHARED_DATA int active_freq_idx = CPU_DEFAULT_IDX; - -/* - * This is call from public API, so overwrite currently used frequency index - * in 'active' state with new value. This value will be used in each wakeup. - * Caller should hold the pm_runtime lock. - */ -static inline void set_cpu_current_freq_idx(int freq_idx, bool release_unused) -{ - int *uncached_freq_idx = cache_to_uncache((__sparse_force void __sparse_cache *)&active_freq_idx); - - select_cpu_clock(freq_idx, release_unused); - *uncached_freq_idx = freq_idx; -} - -static inline int get_current_freq_idx(int clock) -{ - struct clock_info *clk_info = clocks_get() + clock; - - return clk_info->current_freq_idx; -} - -static inline int get_lowest_freq_idx(int clock) -{ - struct clock_info *clk_info = clocks_get() + clock; - - return clk_info->lowest_freq_idx; -} - -static void platform_clock_low_power_mode(int clock, bool enable) -{ - int current_freq_idx = get_current_freq_idx(clock); - int freq_idx = *(int *)cache_to_uncache((__sparse_force void __sparse_cache *)&active_freq_idx); - - if (enable && current_freq_idx > CPU_LPRO_FREQ_IDX) - /* LPRO requests are fast, but requests for other ROs - * can take a lot of time. That's why it's better to - * not release active clock just for waiti, - * so they can be switched without delay on wake up. - */ - select_cpu_clock(CPU_LPRO_FREQ_IDX, false); - else if (!enable && current_freq_idx != freq_idx) - select_cpu_clock(freq_idx, true); -} - -void platform_clock_on_waiti(void) -{ - struct pm_runtime_data *prd = pm_runtime_data_get(); - k_spinlock_key_t key; - int freq_idx; - int lowest_freq_idx; - bool pm_is_active; - - /* hold the prd->lock for possible active_freq_idx switching */ - key = k_spin_lock(&prd->lock); - - freq_idx = *(int *)cache_to_uncache((__sparse_force void __sparse_cache *)&active_freq_idx); - lowest_freq_idx = get_lowest_freq_idx(CLK_CPU(cpu_get_id())); - pm_is_active = pm_runtime_is_active(PM_RUNTIME_DSP, PLATFORM_PRIMARY_CORE_ID); - - if (pm_is_active) { - /* set HPRO clock if not already enabled */ - if (freq_idx != CPU_HPRO_FREQ_IDX) - set_cpu_current_freq_idx(CPU_HPRO_FREQ_IDX, true); - } else { - /* set lowest clock if not already enabled */ - if (freq_idx != lowest_freq_idx) - set_cpu_current_freq_idx(lowest_freq_idx, true); - } - - k_spin_unlock(&prd->lock, key); - - /* check if waiti HPRO->LPRO switching is needed */ - pm_runtime_put(CORE_HP_CLK, cpu_get_id()); -} - -void platform_clock_on_wakeup(void) -{ - /* check if HPRO switching back is needed */ - pm_runtime_get(CORE_HP_CLK, cpu_get_id()); -} - -#else - -/* Store clock source that was active before going to waiti, - * so it can be restored on wake up. - */ -static SHARED_DATA int active_freq_idx = CPU_DEFAULT_IDX; - -/* - * This is call from public API, so overwrite currently used frequency index - * in 'active' state with new value. This value will be used in each wakeup. - * Caller should hold the pm_runtime lock. - */ -static inline void set_cpu_current_freq_idx(int freq_idx, bool release_unused) -{ - int *uncached_freq_idx = cache_to_uncache(&active_freq_idx); - - select_cpu_clock(freq_idx, release_unused); - *uncached_freq_idx = freq_idx; -} - -static inline int get_current_freq_idx(int clock) -{ - struct clock_info *clk_info = clocks_get() + clock; - - return clk_info->current_freq_idx; -} - -static inline int get_lowest_freq_idx(int clock) -{ - struct clock_info *clk_info = clocks_get() + clock; - - return clk_info->lowest_freq_idx; -} - -static void platform_clock_low_power_mode(int clock, bool enable) -{ -} - -void platform_clock_on_waiti(void) -{ - struct pm_runtime_data *prd = pm_runtime_data_get(); - k_spinlock_key_t key; - int freq_idx; - int lowest_freq_idx; - bool pm_is_active; - - /* hold the prd->lock for possible active_freq_idx switching */ - key = k_spin_lock(&prd->lock); - - freq_idx = *(int *)cache_to_uncache(&active_freq_idx); - lowest_freq_idx = get_lowest_freq_idx(CLK_CPU(cpu_get_id())); - pm_is_active = pm_runtime_is_active(PM_RUNTIME_DSP, PLATFORM_PRIMARY_CORE_ID); - - if (pm_is_active) { - /* set HPRO clock if not already enabled */ - if (freq_idx != CPU_HPRO_FREQ_IDX) - set_cpu_current_freq_idx(CPU_HPRO_FREQ_IDX, true); - } else { - /* set lowest clock if not already enabled */ - if (freq_idx != lowest_freq_idx) - set_cpu_current_freq_idx(lowest_freq_idx, true); - } - - k_spin_unlock(&prd->lock, key); -} - -void platform_clock_on_wakeup(void) -{ - struct pm_runtime_data *prd = pm_runtime_data_get(); - k_spinlock_key_t key; - int current_idx; - int target_idx; - - /* hold the prd->lock for possible active_freq_idx switching */ - key = k_spin_lock(&prd->lock); - - current_idx = get_current_freq_idx(CLK_CPU(cpu_get_id())); - target_idx = *(int *)cache_to_uncache(&active_freq_idx); - - /* restore the active cpu freq_idx manually */ - if (current_idx != target_idx) - set_cpu_current_freq_idx(target_idx, true); - - k_spin_unlock(&prd->lock, key); -} - -#endif - -static int clock_platform_set_cpu_freq(int clock, int freq_idx) -{ - select_cpu_clock_unlocked(freq_idx, true); - return 0; -} - -void platform_clock_init(struct sof *sof) -{ - uint32_t platform_lowest_clock = CPU_LOWEST_FREQ_IDX; - int i; - - sof->clocks = platform_shared_get(platform_clocks_info, sizeof(platform_clocks_info)); - -#if CAVS_VERSION == CAVS_VERSION_2_5 - /* - * Check HW version clock capabilities - * Try to request WOV_CRO clock, if it fails use LPRO clock - */ - - shim_write(SHIM_CLKCTL, shim_read(SHIM_CLKCTL) | SHIM_CLKCTL_WOV_CRO_REQUEST); - if (shim_read(SHIM_CLKCTL) & SHIM_CLKCTL_WOV_CRO_REQUEST) - shim_write(SHIM_CLKCTL, shim_read(SHIM_CLKCTL) & ~SHIM_CLKCTL_WOV_CRO_REQUEST); - else - platform_lowest_clock = CPU_LPRO_FREQ_IDX; -#endif - - for (i = 0; i < CONFIG_CORE_COUNT; i++) { - sof->clocks[i] = (struct clock_info) { - .freqs_num = NUM_CPU_FREQ, - .freqs = cpu_freq, - .default_freq_idx = CPU_DEFAULT_IDX, - .current_freq_idx = CPU_DEFAULT_IDX, - .lowest_freq_idx = platform_lowest_clock, - .notification_id = NOTIFIER_ID_CPU_FREQ, - .notification_mask = NOTIFIER_TARGET_CORE_MASK(i), - .set_freq = clock_platform_set_cpu_freq, - .low_power_mode = platform_clock_low_power_mode, - }; - } - - k_spinlock_init(&clk_lock); - - sof->clocks[CLK_SSP] = (struct clock_info) { - .freqs_num = NUM_SSP_FREQ, - .freqs = ssp_freq, - .default_freq_idx = SSP_DEFAULT_IDX, - .current_freq_idx = SSP_DEFAULT_IDX, - .notification_id = NOTIFIER_ID_SSP_FREQ, - .notification_mask = NOTIFIER_TARGET_CORE_ALL_MASK, - .set_freq = NULL, - }; -} diff --git a/src/platform/intel/cavs/lib/dai.c b/src/platform/intel/cavs/lib/dai.c deleted file mode 100644 index 442c0d73a227..000000000000 --- a/src/platform/intel/cavs/lib/dai.c +++ /dev/null @@ -1,235 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2018 Intel Corporation. All rights reserved. -// -// Author: Liam Girdwood -// Keyon Jie -// Rander Wang -// Janusz Jankowski - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if CONFIG_INTEL_SSP - -#include - -static SHARED_DATA struct dai ssp_shared[DAI_NUM_SSP_BASE + DAI_NUM_SSP_EXT]; - -#endif - -#if CONFIG_INTEL_DMIC - -#include - -static SHARED_DATA struct dai dmic_shared[2] = { - /* Testing idea if DMIC FIFOs A and B to access the same microphones - * with two different sample rate and PCM format could be presented - * similarly as SSP0..N. The difference however is that the DMIC - * programming is global and not per FIFO. - */ - - /* Primary FIFO A */ - { - .index = 0, - .plat_data = { - .base = DMIC_BASE, - .irq = IRQ_EXT_DMIC_LVL5(0), - .irq_name = irq_name_level5, - .fifo[SOF_IPC_STREAM_PLAYBACK] = { - .offset = 0, /* No playback */ - .handshake = 0, - }, - .fifo[SOF_IPC_STREAM_CAPTURE] = { - .offset = DMIC_BASE + OUTDATA0, - .handshake = DMA_HANDSHAKE_DMIC_CH0, - } - }, - .drv = &dmic_driver, - }, - /* Secondary FIFO B */ - { - .index = 1, - .plat_data = { - .base = DMIC_BASE, - .irq = IRQ_EXT_DMIC_LVL5(1), - .irq_name = irq_name_level5, - .fifo[SOF_IPC_STREAM_PLAYBACK] = { - .offset = 0, /* No playback */ - .handshake = 0, - }, - .fifo[SOF_IPC_STREAM_CAPTURE] = { - .offset = DMIC_BASE + OUTDATA1, - .handshake = DMA_HANDSHAKE_DMIC_CH1, - } - }, - .drv = &dmic_driver, - } -}; - -#endif - -#if CONFIG_INTEL_ALH - -#include - -static SHARED_DATA struct dai alh_shared[DAI_NUM_ALH_BI_DIR_LINKS]; -#endif - -static SHARED_DATA struct dai hda_shared[DAI_NUM_HDA_OUT + DAI_NUM_HDA_IN]; - -const struct dai_type_info dti[] = { -#if CONFIG_INTEL_SSP - { - .type = SOF_DAI_INTEL_SSP, - .dai_array = cache_to_uncache_init((struct dai *)ssp_shared), - .num_dais = ARRAY_SIZE(ssp_shared) - }, -#endif -#if CONFIG_INTEL_DMIC - { - .type = SOF_DAI_INTEL_DMIC, - .dai_array = cache_to_uncache_init((struct dai *)dmic_shared), - .num_dais = ARRAY_SIZE(dmic_shared) - }, -#endif - { - .type = SOF_DAI_INTEL_HDA, - .dai_array = cache_to_uncache_init((struct dai *)hda_shared), - .num_dais = ARRAY_SIZE(hda_shared) - }, -#if CONFIG_INTEL_ALH - { - .type = SOF_DAI_INTEL_ALH, - .dai_array = cache_to_uncache_init((struct dai *)alh_shared), - .num_dais = ARRAY_SIZE(alh_shared) - } -#endif -}; - -const struct dai_info lib_dai = { - .dai_type_array = dti, - .num_dai_types = ARRAY_SIZE(dti) -}; - -int dai_init(struct sof *sof) -{ - struct dai *dai; -#if CONFIG_INTEL_SSP - const struct dai_type_info *ssp = NULL; -#endif -#if CONFIG_INTEL_ALH - const struct dai_type_info *alh = NULL; -#endif -#if CONFIG_INTEL_DMIC - const struct dai_type_info *dmic = NULL; -#endif - const struct dai_type_info *hda = NULL; - int i; - - sof->dai_info = &lib_dai; - - for (i = 0; i < ARRAY_SIZE(dti); i++) - switch (dti[i].type) { -#if CONFIG_INTEL_ALH - case SOF_DAI_INTEL_ALH: - alh = dti + i; - break; -#endif -#if CONFIG_INTEL_DMIC - case SOF_DAI_INTEL_DMIC: - dmic = dti + i; - break; -#endif -#if CONFIG_INTEL_SSP - case SOF_DAI_INTEL_SSP: - ssp = dti + i; - break; -#endif - case SOF_DAI_INTEL_HDA: - hda = dti + i; - break; - } - -#if CONFIG_INTEL_SSP - if (ssp) { - dai = ssp->dai_array; - - /* init ssp */ - for (i = 0; i < ssp->num_dais; i++) { - dai[i].index = i; - dai[i].drv = &ssp_driver; - dai[i].plat_data.base = SSP_BASE(i); - dai[i].plat_data.irq = IRQ_EXT_SSPx_LVL5(i); - dai[i].plat_data.irq_name = irq_name_level5; - dai[i].plat_data.fifo[SOF_IPC_STREAM_PLAYBACK].offset = - SSP_BASE(i) + SSDR; - dai[i].plat_data.fifo[SOF_IPC_STREAM_PLAYBACK].handshake = - DMA_HANDSHAKE_SSP0_TX + 2 * i; - dai[i].plat_data.fifo[SOF_IPC_STREAM_CAPTURE].offset = - SSP_BASE(i) + SSDR; - dai[i].plat_data.fifo[SOF_IPC_STREAM_CAPTURE].handshake = - DMA_HANDSHAKE_SSP0_RX + 2 * i; - /* initialize spin locks early to enable ref counting */ - k_spinlock_init(&dai[i].lock); - } - } -#endif - -#if CONFIG_INTEL_MCLK - mn_init(sof); -#endif - - if (hda) { - dai = hda->dai_array; - - /* init hd/a, note that size depends on the platform caps */ - for (i = 0; i < hda->num_dais; i++) { - dai[i].index = i; - dai[i].drv = &hda_driver; - k_spinlock_init(&dai[i].lock); - } - } - -#if (CONFIG_INTEL_DMIC) - if (dmic) { - dai = dmic->dai_array; - - /* init dmic */ - for (i = 0; i < dmic->num_dais; i++) - k_spinlock_init(&dai[i].lock); - } -#endif - -#if CONFIG_INTEL_ALH - if (alh) { - dai = alh->dai_array; - - for (i = 0; i < alh->num_dais; i++) { - dai[i].index = (i / DAI_NUM_ALH_BI_DIR_LINKS_GROUP) << 8 | - (i % DAI_NUM_ALH_BI_DIR_LINKS_GROUP); - dai[i].drv = &alh_driver; - - /* set burst length to align with DMAT value in the - * Audio Link Hub. - */ - dai[i].plat_data.fifo[SOF_IPC_STREAM_PLAYBACK].depth = - ALH_GPDMA_BURST_LENGTH; - dai[i].plat_data.fifo[SOF_IPC_STREAM_CAPTURE].depth = - ALH_GPDMA_BURST_LENGTH; - k_spinlock_init(&dai[i].lock); - } - } -#endif - - return 0; -} diff --git a/src/platform/intel/cavs/lib/dma.c b/src/platform/intel/cavs/lib/dma.c deleted file mode 100644 index de73afa3de2a..000000000000 --- a/src/platform/intel/cavs/lib/dma.c +++ /dev/null @@ -1,285 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2018 Intel Corporation. All rights reserved. -// -// Author: Liam Girdwood -// Keyon Jie -// Rander Wang -// Janusz Jankowski - -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef __ZEPHYR__ -#include -#endif - -#if CONFIG_TIGERLAKE -#define DMAC0_CLASS 6 -#define DMAC1_CLASS 7 -#define DMAC_HOST_IN_CHANNELS_COUNT 7 -#define DMAC_HOST_OUT_CHANNELS_COUNT 9 -#define DMAC_LINK_IN_CHANNELS_COUNT 7 -#define DMAC_LINK_OUT_CHANNELS_COUNT 9 -#endif - -static const struct dw_drv_plat_data dmac0 = { - .chan[0] = { - .class = DMAC0_CLASS, - .weight = 0, - }, - .chan[1] = { - .class = DMAC0_CLASS, - .weight = 0, - }, - .chan[2] = { - .class = DMAC0_CLASS, - .weight = 0, - }, - .chan[3] = { - .class = DMAC0_CLASS, - .weight = 0, - }, - .chan[4] = { - .class = DMAC0_CLASS, - .weight = 0, - }, - .chan[5] = { - .class = DMAC0_CLASS, - .weight = 0, - }, - .chan[6] = { - .class = DMAC0_CLASS, - .weight = 0, - }, - .chan[7] = { - .class = DMAC0_CLASS, - .weight = 0, - }, -}; - -static const struct dw_drv_plat_data dmac1 = { - .chan[0] = { - .class = DMAC1_CLASS, - .weight = 0, - }, - .chan[1] = { - .class = DMAC1_CLASS, - .weight = 0, - }, - .chan[2] = { - .class = DMAC1_CLASS, - .weight = 0, - }, - .chan[3] = { - .class = DMAC1_CLASS, - .weight = 0, - }, - .chan[4] = { - .class = DMAC1_CLASS, - .weight = 0, - }, - .chan[5] = { - .class = DMAC1_CLASS, - .weight = 0, - }, - .chan[6] = { - .class = DMAC1_CLASS, - .weight = 0, - }, - .chan[7] = { - .class = DMAC1_CLASS, - .weight = 0, - }, -}; - -/* DMA number of buffer periods */ -#define HDA_DMA_BUFFER_PERIOD_COUNT 4 - -#if CONFIG_DMA_HW_LLI -#define DW_DMA_BUFFER_PERIOD_COUNT 4 -#else -#define DW_DMA_BUFFER_PERIOD_COUNT 2 -#endif - -static SHARED_DATA struct dma dma[PLATFORM_NUM_DMACS] = { -{ /* Low Power GP DMAC 0 */ - .plat_data = { - .id = DMA_GP_LP_DMAC0, - .dir = DMA_DIR_MEM_TO_MEM | DMA_DIR_MEM_TO_DEV | - DMA_DIR_DEV_TO_MEM | DMA_DIR_DEV_TO_DEV, - .caps = DMA_CAP_GP_LP, - .devs = DMA_DEV_SSP | DMA_DEV_DMIC | - DMA_DEV_ALH, - .base = LP_GP_DMA_BASE(0), - .channels = 8, - .irq = IRQ_EXT_LP_GPDMA0_LVL5(0), - .irq_name = irq_name_level5, - .drv_plat_data = &dmac0, -#ifdef __ZEPHYR__ - .period_count = DW_DMA_BUFFER_PERIOD_COUNT, -#endif - }, -#ifndef CONFIG_ZEPHYR_NATIVE_DRIVERS - .ops = &dw_dma_ops, -#endif -}, -{ /* Low Power GP DMAC 1 */ - .plat_data = { - .id = DMA_GP_LP_DMAC1, - .dir = DMA_DIR_MEM_TO_MEM | DMA_DIR_MEM_TO_DEV | - DMA_DIR_DEV_TO_MEM | DMA_DIR_DEV_TO_DEV, - .caps = DMA_CAP_GP_LP, - .devs = DMA_DEV_SSP | DMA_DEV_DMIC | - DMA_DEV_ALH, - .base = LP_GP_DMA_BASE(1), - .channels = 8, - .irq = IRQ_EXT_LP_GPDMA1_LVL5(0), - .irq_name = irq_name_level5, - .drv_plat_data = &dmac1, -#ifdef __ZEPHYR__ - .period_count = DW_DMA_BUFFER_PERIOD_COUNT, -#endif - }, -#ifndef CONFIG_ZEPHYR_NATIVE_DRIVERS - .ops = &dw_dma_ops, -#endif -}, -{ /* Host In DMAC */ - .plat_data = { - .id = DMA_HOST_IN_DMAC, - .dir = DMA_DIR_LMEM_TO_HMEM, - .caps = DMA_CAP_HDA, - .devs = DMA_DEV_HOST, - .base = GTW_HOST_IN_STREAM_BASE(0), - .channels = DMAC_HOST_IN_CHANNELS_COUNT, - .chan_size = GTW_HOST_IN_STREAM_SIZE, -#ifdef __ZEPHYR__ - .period_count = HDA_DMA_BUFFER_PERIOD_COUNT, -#endif - }, -#ifndef CONFIG_ZEPHYR_NATIVE_DRIVERS - .ops = &hda_host_dma_ops, -#endif -}, -{ /* Host out DMAC */ - .plat_data = { - .id = DMA_HOST_OUT_DMAC, - .dir = DMA_DIR_HMEM_TO_LMEM, - .caps = DMA_CAP_HDA, - .devs = DMA_DEV_HOST, - .base = GTW_HOST_OUT_STREAM_BASE(0), - .channels = DMAC_HOST_OUT_CHANNELS_COUNT, - .chan_size = GTW_HOST_OUT_STREAM_SIZE, -#ifdef __ZEPHYR__ - .period_count = HDA_DMA_BUFFER_PERIOD_COUNT, -#endif - }, -#ifndef CONFIG_ZEPHYR_NATIVE_DRIVERS - .ops = &hda_host_dma_ops, -#endif -}, -{ /* Link In DMAC */ - .plat_data = { - .id = DMA_LINK_IN_DMAC, - .dir = DMA_DIR_DEV_TO_MEM, - .caps = DMA_CAP_HDA, - .devs = DMA_DEV_HDA, - .base = GTW_LINK_IN_STREAM_BASE(0), - .channels = DMAC_LINK_IN_CHANNELS_COUNT, - .chan_size = GTW_LINK_IN_STREAM_SIZE, -#ifdef __ZEPHYR__ - .period_count = HDA_DMA_BUFFER_PERIOD_COUNT, -#endif - }, -#ifndef CONFIG_ZEPHYR_NATIVE_DRIVERS - .ops = &hda_link_dma_ops, -#endif -}, -{ /* Link out DMAC */ - .plat_data = { - .id = DMA_LINK_OUT_DMAC, - .dir = DMA_DIR_MEM_TO_DEV, - .caps = DMA_CAP_HDA, - .devs = DMA_DEV_HDA, - .base = GTW_LINK_OUT_STREAM_BASE(0), - .channels = DMAC_LINK_OUT_CHANNELS_COUNT, - .chan_size = GTW_LINK_OUT_STREAM_SIZE, -#ifdef __ZEPHYR__ - .period_count = HDA_DMA_BUFFER_PERIOD_COUNT, -#endif - }, -#ifndef CONFIG_ZEPHYR_NATIVE_DRIVERS - .ops = &hda_link_dma_ops, -#endif -},}; - -static const struct dma_info lib_dma = { - .dma_array = cache_to_uncache_init((struct dma *)dma), - .num_dmas = ARRAY_SIZE(dma) -}; - -/* Initialize all platform DMAC's */ -int dmac_init(struct sof *sof) -{ -#if CONFIG_ZEPHYR_NATIVE_DRIVERS - const struct device *z_dev = NULL; -#endif - int i; - /* no probing before first use */ - - /* TODO: dynamic init based on platform settings */ - - sof->dma_info = &lib_dma; - - /* early lock initialization for ref counting */ - for (i = 0; i < sof->dma_info->num_dmas; i++) { - k_spinlock_init(&sof->dma_info->dma_array[i].lock); -#if CONFIG_ZEPHYR_NATIVE_DRIVERS - switch (sof->dma_info->dma_array[i].plat_data.id) { - case DMA_HOST_IN_DMAC: -#if DT_NODE_HAS_STATUS(DT_NODELABEL(hda_host_in), okay) - z_dev = DEVICE_DT_GET(DT_NODELABEL(hda_host_in)); -#endif - break; - case DMA_HOST_OUT_DMAC: -#if DT_NODE_HAS_STATUS(DT_NODELABEL(hda_host_out), okay) - z_dev = DEVICE_DT_GET(DT_NODELABEL(hda_host_out)); -#endif - break; - case DMA_LINK_IN_DMAC: -#if DT_NODE_HAS_STATUS(DT_NODELABEL(hda_link_in), okay) - z_dev = DEVICE_DT_GET(DT_NODELABEL(hda_link_in)); -#endif - break; - case DMA_LINK_OUT_DMAC: -#if DT_NODE_HAS_STATUS(DT_NODELABEL(hda_link_out), okay) - z_dev = DEVICE_DT_GET(DT_NODELABEL(hda_link_out)); -#endif - break; - case DMA_GP_LP_DMAC0: -#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpgpdma0), okay) - z_dev = DEVICE_DT_GET(DT_NODELABEL(lpgpdma0)); -#endif - break; - case DMA_GP_LP_DMAC1: -#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpgpdma1), okay) - z_dev = DEVICE_DT_GET(DT_NODELABEL(lpgpdma1)); -#endif - break; - default: - continue; - } - if (!z_dev) - return -EINVAL; - - sof->dma_info->dma_array[i].z_dev = z_dev; -#endif - } - return 0; -} diff --git a/src/platform/intel/cavs/lib/mem_window.c b/src/platform/intel/cavs/lib/mem_window.c deleted file mode 100644 index a5e49c0328ee..000000000000 --- a/src/platform/intel/cavs/lib/mem_window.c +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2019 Intel Corporation. All rights reserved. -// -// Author: Marcin Maka - -/** - * \file - * \brief Memory windows programming and initialization - * \author Marcin Maka - */ - -#include -#include -#include -#include -#include - -static inline void memory_window_init(uint32_t index, - uint32_t base, uint32_t size, - uint32_t zero_base, uint32_t zero_size, - uint32_t wnd_flags, uint32_t init_flags) -{ - io_reg_write(DMWLO(index), size | 0x7); - io_reg_write(DMWBA(index), base | wnd_flags); - if (init_flags & MEM_WND_INIT_CLEAR) { - bzero((void *)zero_base, zero_size); - dcache_writeback_region((__sparse_force void __sparse_cache *)zero_base, zero_size); - } -} - -void platform_memory_windows_init(uint32_t flags) -{ - /* window0, for fw status & outbox/uplink mbox */ - memory_window_init(0, HP_SRAM_WIN0_BASE, HP_SRAM_WIN0_SIZE, - HP_SRAM_WIN0_BASE + SRAM_REG_FW_END, - HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END, - DMWBA_READONLY | DMWBA_ENABLE, flags); - - /* window1, for inbox/downlink mbox */ - memory_window_init(1, HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE, - HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE, - DMWBA_ENABLE, flags); - - /* window2, for debug */ - memory_window_init(2, HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE, - HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE, - DMWBA_ENABLE, flags); - - /* window3, for trace - * zeroed by trace initialization - */ - memory_window_init(3, HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE, - HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE, - DMWBA_READONLY | DMWBA_ENABLE, 0); -} diff --git a/src/platform/intel/cavs/lib/memory.c b/src/platform/intel/cavs/lib/memory.c deleted file mode 100644 index bb312b9e28b5..000000000000 --- a/src/platform/intel/cavs/lib/memory.c +++ /dev/null @@ -1,253 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2018 Intel Corporation. All rights reserved. -// -// Author: Liam Girdwood -// Janusz Jankowski - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define uncached_block_hdr(hdr) cache_to_uncache_init((struct block_hdr *)(hdr)) -#define uncached_block_map(map) cache_to_uncache((struct block_map *)(map)) - -extern uintptr_t _system_heap, _system_runtime_heap, _module_heap; -extern uintptr_t _buffer_heap, _sof_core_s_start; -#if CONFIG_CORE_COUNT > 1 -extern uintptr_t _runtime_shared_heap, _system_shared_heap; -#endif - -/* Heap blocks for system runtime for primary core */ -static SHARED_DATA struct block_hdr sys_rt_0_block64[HEAP_SYS_RT_0_COUNT64]; -static SHARED_DATA struct block_hdr sys_rt_0_block512[HEAP_SYS_RT_0_COUNT512]; -static SHARED_DATA struct block_hdr sys_rt_0_block1024[HEAP_SYS_RT_0_COUNT1024]; - -/* Heap blocks for system runtime for secondary core */ -#if CONFIG_CORE_COUNT > 1 -static SHARED_DATA struct block_hdr - sys_rt_x_block64[CONFIG_CORE_COUNT - 1][HEAP_SYS_RT_X_COUNT64]; -static SHARED_DATA struct block_hdr - sys_rt_x_block512[CONFIG_CORE_COUNT - 1][HEAP_SYS_RT_X_COUNT512]; -static SHARED_DATA struct block_hdr - sys_rt_x_block1024[CONFIG_CORE_COUNT - 1][HEAP_SYS_RT_X_COUNT1024]; -#endif - -/* Heap memory for system runtime */ -static SHARED_DATA struct block_map sys_rt_heap_map[CONFIG_CORE_COUNT][3] = { - { BLOCK_DEF(64, HEAP_SYS_RT_0_COUNT64, - uncached_block_hdr(sys_rt_0_block64)), - BLOCK_DEF(512, HEAP_SYS_RT_0_COUNT512, - uncached_block_hdr(sys_rt_0_block512)), - BLOCK_DEF(1024, HEAP_SYS_RT_0_COUNT1024, - uncached_block_hdr(sys_rt_0_block1024)), }, -#if CONFIG_CORE_COUNT > 1 - { BLOCK_DEF(64, HEAP_SYS_RT_X_COUNT64, - uncached_block_hdr(sys_rt_x_block64[0])), - BLOCK_DEF(512, HEAP_SYS_RT_X_COUNT512, - uncached_block_hdr(sys_rt_x_block512[0])), - BLOCK_DEF(1024, HEAP_SYS_RT_X_COUNT1024, - uncached_block_hdr(sys_rt_x_block1024[0])), }, -#endif -#if CONFIG_CORE_COUNT > 2 - { BLOCK_DEF(64, HEAP_SYS_RT_X_COUNT64, - uncached_block_hdr(sys_rt_x_block64[1])), - BLOCK_DEF(512, HEAP_SYS_RT_X_COUNT512, - uncached_block_hdr(sys_rt_x_block512[1])), - BLOCK_DEF(1024, HEAP_SYS_RT_X_COUNT1024, - uncached_block_hdr(sys_rt_x_block1024[1])), }, -#endif -#if CONFIG_CORE_COUNT > 3 - { BLOCK_DEF(64, HEAP_SYS_RT_X_COUNT64, - uncached_block_hdr(sys_rt_x_block64[2])), - BLOCK_DEF(512, HEAP_SYS_RT_X_COUNT512, - uncached_block_hdr(sys_rt_x_block512[2])), - BLOCK_DEF(1024, HEAP_SYS_RT_X_COUNT1024, - uncached_block_hdr(sys_rt_x_block1024[2])), }, -#endif -}; - -/* Heap blocks for modules */ -static SHARED_DATA struct block_hdr mod_block64[HEAP_RT_COUNT64]; -static SHARED_DATA struct block_hdr mod_block128[HEAP_RT_COUNT128]; -static SHARED_DATA struct block_hdr mod_block256[HEAP_RT_COUNT256]; -static SHARED_DATA struct block_hdr mod_block512[HEAP_RT_COUNT512]; -static SHARED_DATA struct block_hdr mod_block1024[HEAP_RT_COUNT1024]; -static SHARED_DATA struct block_hdr mod_block2048[HEAP_RT_COUNT2048]; -static SHARED_DATA struct block_hdr mod_block4096[HEAP_RT_COUNT4096]; - -/* Heap memory map for modules */ -static SHARED_DATA struct block_map rt_heap_map[] = { - BLOCK_DEF(64, HEAP_RT_COUNT64, uncached_block_hdr(mod_block64)), - BLOCK_DEF(128, HEAP_RT_COUNT128, uncached_block_hdr(mod_block128)), - BLOCK_DEF(256, HEAP_RT_COUNT256, uncached_block_hdr(mod_block256)), - BLOCK_DEF(512, HEAP_RT_COUNT512, uncached_block_hdr(mod_block512)), - BLOCK_DEF(1024, HEAP_RT_COUNT1024, uncached_block_hdr(mod_block1024)), - BLOCK_DEF(2048, HEAP_RT_COUNT2048, uncached_block_hdr(mod_block2048)), - BLOCK_DEF(4096, HEAP_RT_COUNT4096, uncached_block_hdr(mod_block4096)), -}; - -#if CONFIG_CORE_COUNT > 1 -/* Heap blocks for runtime shared */ -static SHARED_DATA struct block_hdr rt_shared_block64[HEAP_RUNTIME_SHARED_COUNT64]; -static SHARED_DATA struct block_hdr rt_shared_block128[HEAP_RUNTIME_SHARED_COUNT128]; -static SHARED_DATA struct block_hdr rt_shared_block256[HEAP_RUNTIME_SHARED_COUNT256]; -static SHARED_DATA struct block_hdr rt_shared_block512[HEAP_RUNTIME_SHARED_COUNT512]; -static SHARED_DATA struct block_hdr rt_shared_block1024[HEAP_RUNTIME_SHARED_COUNT1024]; - -/* Heap memory map for runtime shared */ -static SHARED_DATA struct block_map rt_shared_heap_map[] = { - BLOCK_DEF(64, HEAP_RUNTIME_SHARED_COUNT64, uncached_block_hdr(rt_shared_block64)), - BLOCK_DEF(128, HEAP_RUNTIME_SHARED_COUNT128, uncached_block_hdr(rt_shared_block128)), - BLOCK_DEF(256, HEAP_RUNTIME_SHARED_COUNT256, uncached_block_hdr(rt_shared_block256)), - BLOCK_DEF(512, HEAP_RUNTIME_SHARED_COUNT512, uncached_block_hdr(rt_shared_block512)), - BLOCK_DEF(1024, HEAP_RUNTIME_SHARED_COUNT1024, uncached_block_hdr(rt_shared_block1024)), -}; -#endif - -/* Heap blocks for buffers */ -static SHARED_DATA struct block_hdr buf_block[HEAP_BUFFER_COUNT_MAX]; -static SHARED_DATA struct block_hdr lp_buf_block[HEAP_LP_BUFFER_COUNT]; - -/* Heap memory map for buffers */ -static SHARED_DATA struct block_map buf_heap_map[] = { - BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT_MAX, - uncached_block_hdr(buf_block)), -}; - -static SHARED_DATA struct block_map lp_buf_heap_map[] = { - BLOCK_DEF(HEAP_LP_BUFFER_BLOCK_SIZE, HEAP_LP_BUFFER_COUNT, - uncached_block_hdr(lp_buf_block)), -}; - -static SHARED_DATA struct mm memmap; - -void platform_init_memmap(struct sof *sof) -{ - uint32_t heap_buffer_size = SOF_FW_END - (uint32_t)&_buffer_heap; - uint32_t buffer_count; - int i; - - /* calculate the buffer heap size */ - buffer_count = heap_buffer_size / HEAP_BUFFER_BLOCK_SIZE; - heap_buffer_size = buffer_count * HEAP_BUFFER_BLOCK_SIZE; - - for (i = 0; i < ARRAY_SIZE(buf_heap_map); i++) { - buf_heap_map[i].count = buffer_count; - buf_heap_map[i].free_count = buffer_count; - } - dcache_writeback_region(buf_heap_map, - sizeof(struct block_map) * ARRAY_SIZE(buf_heap_map)); - - /* access memory map through uncached region */ - sof->memory_map = platform_shared_get(&memmap, sizeof(memmap)); - - /* .system primary core initialization */ - sof->memory_map->system[0].heap = (uintptr_t)&_system_heap; - sof->memory_map->system[0].size = HEAP_SYSTEM_M_SIZE; - sof->memory_map->system[0].info.free = HEAP_SYSTEM_M_SIZE; - sof->memory_map->system[0].caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_EXT | - SOF_MEM_CAPS_CACHE; - - /* .system_runtime primary core initialization */ - sof->memory_map->system_runtime[0].blocks = - ARRAY_SIZE(sys_rt_heap_map[0]); - sof->memory_map->system_runtime[0].map = - uncached_block_map(sys_rt_heap_map[0]); - sof->memory_map->system_runtime[0].heap = - (uintptr_t)&_system_runtime_heap; - sof->memory_map->system_runtime[0].size = HEAP_SYS_RUNTIME_M_SIZE; - sof->memory_map->system_runtime[0].info.free = HEAP_SYS_RUNTIME_M_SIZE; - sof->memory_map->system_runtime[0].caps = SOF_MEM_CAPS_RAM | - SOF_MEM_CAPS_EXT | SOF_MEM_CAPS_CACHE | - SOF_MEM_CAPS_DMA; - - /* .system and .system_runtime secondary core initialization */ - for (i = 1; i < CONFIG_CORE_COUNT; i++) { - /* .system init */ - sof->memory_map->system[i].heap = - (uintptr_t)&_sof_core_s_start + - ((i - 1) * SOF_CORE_S_SIZE); - sof->memory_map->system[i].size = HEAP_SYSTEM_S_SIZE; - sof->memory_map->system[i].info.free = HEAP_SYSTEM_S_SIZE; - sof->memory_map->system[i].caps = SOF_MEM_CAPS_RAM | - SOF_MEM_CAPS_EXT | SOF_MEM_CAPS_CACHE; - - /* .system_runtime init */ - sof->memory_map->system_runtime[i].blocks = - ARRAY_SIZE(sys_rt_heap_map[i]); - sof->memory_map->system_runtime[i].map = - uncached_block_map(sys_rt_heap_map[i]); - sof->memory_map->system_runtime[i].heap = - (uintptr_t)&_sof_core_s_start + - ((i - 1) * SOF_CORE_S_SIZE) + HEAP_SYSTEM_S_SIZE; - sof->memory_map->system_runtime[i].size = - HEAP_SYS_RUNTIME_S_SIZE; - sof->memory_map->system_runtime[i].info.free = - HEAP_SYS_RUNTIME_S_SIZE; - sof->memory_map->system_runtime[i].caps = SOF_MEM_CAPS_RAM | - SOF_MEM_CAPS_EXT | SOF_MEM_CAPS_CACHE | - SOF_MEM_CAPS_DMA; - } - -#if CONFIG_CORE_COUNT > 1 - /* .runtime_shared init */ - sof->memory_map->runtime_shared[0].blocks = ARRAY_SIZE(rt_shared_heap_map); - sof->memory_map->runtime_shared[0].map = uncached_block_map(rt_shared_heap_map); - sof->memory_map->runtime_shared[0].heap = - (uint32_t)cache_to_uncache(&_runtime_shared_heap); - sof->memory_map->runtime_shared[0].size = HEAP_RUNTIME_SHARED_SIZE; - sof->memory_map->runtime_shared[0].info.free = HEAP_RUNTIME_SHARED_SIZE; - sof->memory_map->runtime_shared[0].caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_EXT | - SOF_MEM_CAPS_CACHE; - - /* .system_shared init */ - sof->memory_map->system_shared[0].heap = (uint32_t)cache_to_uncache(&_system_shared_heap); - sof->memory_map->system_shared[0].size = HEAP_SYSTEM_SHARED_SIZE; - sof->memory_map->system_shared[0].info.free = HEAP_SYSTEM_SHARED_SIZE; - sof->memory_map->system_shared[0].caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_EXT | - SOF_MEM_CAPS_CACHE; - -#endif - - /* .runtime init*/ - sof->memory_map->runtime[0].blocks = ARRAY_SIZE(rt_heap_map); - sof->memory_map->runtime[0].map = uncached_block_map(rt_heap_map); - sof->memory_map->runtime[0].heap = (uintptr_t)&_module_heap; - sof->memory_map->runtime[0].size = HEAP_RUNTIME_SIZE; - sof->memory_map->runtime[0].info.free = HEAP_RUNTIME_SIZE; - sof->memory_map->runtime[0].caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_EXT | - SOF_MEM_CAPS_CACHE; - - /* heap buffer init */ - sof->memory_map->buffer[0].blocks = ARRAY_SIZE(buf_heap_map); - sof->memory_map->buffer[0].map = uncached_block_map(buf_heap_map); - sof->memory_map->buffer[0].heap = (uint32_t)cache_to_uncache(&_buffer_heap); - sof->memory_map->buffer[0].size = heap_buffer_size; - sof->memory_map->buffer[0].info.free = heap_buffer_size; - sof->memory_map->buffer[0].caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_HP | - SOF_MEM_CAPS_CACHE | SOF_MEM_CAPS_DMA; - -#if PLATFORM_HEAP_BUFFER >= 2 - /* heap lp buffer init */ - sof->memory_map->buffer[1].blocks = ARRAY_SIZE(lp_buf_heap_map); - sof->memory_map->buffer[1].map = uncached_block_map(lp_buf_heap_map); - sof->memory_map->buffer[1].heap = HEAP_LP_BUFFER_BASE; - sof->memory_map->buffer[1].size = HEAP_LP_BUFFER_SIZE; - sof->memory_map->buffer[1].info.free = HEAP_LP_BUFFER_SIZE; - sof->memory_map->buffer[1].caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_LP | - SOF_MEM_CAPS_CACHE | SOF_MEM_CAPS_DMA; -#endif - - /* .total init */ - sof->memory_map->total.free = HEAP_SYSTEM_T_SIZE + - HEAP_SYS_RUNTIME_T_SIZE + HEAP_RUNTIME_SIZE + heap_buffer_size + - HEAP_LP_BUFFER_SIZE; - -} diff --git a/src/platform/intel/cavs/lib/pm_memory.c b/src/platform/intel/cavs/lib/pm_memory.c deleted file mode 100644 index 7f9dba10b95c..000000000000 --- a/src/platform/intel/cavs/lib/pm_memory.c +++ /dev/null @@ -1,85 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2019 Intel Corporation. All rights reserved. - * - * Author: Jakub Dabek - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -LOG_MODULE_REGISTER(pm_memory, CONFIG_SOF_LOG_LEVEL); - -/* 14f25ab6-3a4b-4e5d-b343-2a142d4e4d92 */ -DECLARE_SOF_UUID("pm-memory", pm_mem_uuid, 0x14f25ab6, 0x3a4b, 0x4e5d, - 0xb3, 0x43, 0x2a, 0x14, 0x2d, 0x4e, 0x4d, 0x92); - -DECLARE_TR_CTX(pm_mem_tr, SOF_UUID(pm_mem_uuid), LOG_LEVEL_INFO); - -/** - * \brief Retrieves memory banks based on start and end pointer. - * \param[in,out] start Start address of memory range. - * \param[in,out] end End address of memory range. - * \param[in] base Base address of memory range. - * \param[in,out] start_bank Start bank id calculated by this function. - * \param[in,out] end_bank End bank id calculated by this function. - */ -static void memory_banks_get(void *start, void *end, uint32_t base, - uint32_t *start_bank, uint32_t *end_bank) -{ - /* if ptr is not aligned to bank size change it to - * closest possible memory address at the start of bank - * or end for end address - */ - if ((uintptr_t)start % SRAM_BANK_SIZE) - start = (void *)ALIGN_UP_COMPILE((uintptr_t)start, SRAM_BANK_SIZE); - - if ((uintptr_t)end % SRAM_BANK_SIZE) - end = (void *)ALIGN_DOWN((uintptr_t)end, SRAM_BANK_SIZE); - - /* return if no full bank could be found for enabled gate control */ - if ((char *)end - (char *)start < SRAM_BANK_SIZE) { - tr_info(&pm_mem_tr, "cavs_pm_memory_banks_get(): cannot find full bank to perform gating operation"); - return; - } - - *start_bank = ((uintptr_t)start - base) / SRAM_BANK_SIZE; - /* Ending bank id has to be lowered by one because it is - * calculated from memory end ptr - */ - *end_bank = ((uintptr_t)end - base) / SRAM_BANK_SIZE - 1; -} - -void cavs_pm_memory_hp_sram_power_gate(void *ptr, uint32_t size, bool enabled) -{ - uint32_t start_bank = 0; - uint32_t end_bank = 0; - - memory_banks_get(ptr, (char *)ptr + size, HP_SRAM_BASE, &start_bank, - &end_bank); - - cavs_pm_memory_hp_sram_banks_power_gate(start_bank, end_bank, enabled); -} - -#if CONFIG_LP_SRAM - -void cavs_pm_memory_lp_sram_power_gate(void *ptr, uint32_t size, bool enabled) -{ - uint32_t start_bank = 0; - uint32_t end_bank = 0; - - memory_banks_get(ptr, (char *)ptr + size, LP_SRAM_BASE, &start_bank, - &end_bank); - - cavs_pm_memory_lp_sram_banks_power_gate(start_bank, end_bank, enabled); -} - -#endif /* CONFIG_LP_SRAM */ diff --git a/src/platform/intel/cavs/lib/pm_runtime.c b/src/platform/intel/cavs/lib/pm_runtime.c deleted file mode 100644 index c8f0381a3ae0..000000000000 --- a/src/platform/intel/cavs/lib/pm_runtime.c +++ /dev/null @@ -1,539 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2018 Intel Corporation. All rights reserved. -// -// Author: Tomasz Lauda -// Janusz Jankowski - -/** - * \file - * \brief Runtime power management implementation for Tiger Lake - * \author Tomasz Lauda - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -LOG_MODULE_REGISTER(power, CONFIG_SOF_LOG_LEVEL); - -/* 76cc9773-440c-4df9-95a8-72defe7796fc */ -DECLARE_SOF_UUID("power", power_uuid, 0x76cc9773, 0x440c, 0x4df9, - 0x95, 0xa8, 0x72, 0xde, 0xfe, 0x77, 0x96, 0xfc); - -DECLARE_TR_CTX(power_tr, SOF_UUID(power_uuid), LOG_LEVEL_INFO); - -/* - * To support Zephyr, some adaptation is needed to the driver. - */ -#ifdef __ZEPHYR__ -extern int cpu_enable_secondary_core(int id); -#endif - -/** - * \brief Registers Host DMA usage that should not trigger - * transition to L0 via forced L1 exit. - */ -static void cavs_pm_runtime_host_dma_l1_get(void) -{ - struct pm_runtime_data *prd = pm_runtime_data_get(); - struct cavs_pm_runtime_data *pprd = prd->platform_data; - k_spinlock_key_t key; - - key = k_spin_lock(&prd->lock); - - pprd->host_dma_l1_sref++; - - k_spin_unlock(&prd->lock, key); -} - -/** - * \brief Releases Host DMA usage preventing L1 exit. If this - * the last user, forced L1 exit is performed. - */ -static inline void cavs_pm_runtime_host_dma_l1_put(void) -{ - struct pm_runtime_data *prd = pm_runtime_data_get(); - struct cavs_pm_runtime_data *pprd = prd->platform_data; - k_spinlock_key_t key; - - key = k_spin_lock(&prd->lock); - - if (!--pprd->host_dma_l1_sref) { - shim_write(SHIM_SVCFG, - shim_read(SHIM_SVCFG) | SHIM_SVCFG_FORCE_L1_EXIT); - - wait_delay(PLATFORM_FORCE_L1_EXIT_TIME); - - shim_write(SHIM_SVCFG, - shim_read(SHIM_SVCFG) & ~(SHIM_SVCFG_FORCE_L1_EXIT)); - } - - k_spin_unlock(&prd->lock, key); -} - -static inline void cavs_pm_runtime_enable_dsp(bool enable) -{ - struct pm_runtime_data *prd = pm_runtime_data_get(); - struct cavs_pm_runtime_data *pprd = prd->platform_data; - uint32_t flags; - - /* request is always run on dsp0 and applies to dsp0, - * so no global lock is required. - */ - irq_local_disable(flags); - - pprd->dsp_d0 = !enable; - - irq_local_enable(flags); - - tr_info(&power_tr, "pm_runtime_enable_dsp dsp_d0_sref %d", - pprd->dsp_d0); - -#if CONFIG_DSP_RESIDENCY_COUNTERS - struct clock_info *clk_info = clocks_get() + CLK_CPU(cpu_get_id()); - - if (!clk_info) - return; - - if (pprd->dsp_d0) { - if (clk_info->current_freq_idx == CPU_LPRO_FREQ_IDX) - report_dsp_r_state(r1_r_state); - else - report_dsp_r_state(r0_r_state); - } else { - report_dsp_r_state(r2_r_state); - } -#endif -} - -static inline bool cavs_pm_runtime_is_active_dsp(void) -{ - struct pm_runtime_data *prd = pm_runtime_data_get(); - struct cavs_pm_runtime_data *pprd = prd->platform_data; - - /* even if dsp_d0 is false (dsp in D0ix state) function will return true - * until secondary cores be prepared of d0ix power down. - */ - return pprd->dsp_d0 || pprd->prepare_d0ix_core_mask; -} - -#if CONFIG_INTEL_SSP -static inline void cavs_pm_runtime_en_ssp_power(uint32_t index) -{ -#if CONFIG_TIGERLAKE - uint32_t reg; - - tr_info(&power_tr, "en_ssp_power index %d", index); - - io_reg_write(I2SLCTL, io_reg_read(I2SLCTL) | I2SLCTL_SPA(index)); - - /* Check if powered on. */ - do { - reg = io_reg_read(I2SLCTL); - } while (!(reg & I2SLCTL_CPA(index))); - - tr_info(&power_tr, "en_ssp_power I2SLCTL %08x", reg); -#endif -} - -static inline void cavs_pm_runtime_dis_ssp_power(uint32_t index) -{ -#if CONFIG_TIGERLAKE - uint32_t reg; - - tr_info(&power_tr, "dis_ssp_power index %d", index); - - io_reg_write(I2SLCTL, io_reg_read(I2SLCTL) & (~I2SLCTL_SPA(index))); - - /* Check if powered off. */ - do { - reg = io_reg_read(I2SLCTL); - } while (reg & I2SLCTL_CPA(index)); - - tr_info(&power_tr, "dis_ssp_power I2SLCTL %08x", reg); -#endif -} -#endif - -#if CONFIG_INTEL_DMIC -static inline void cavs_pm_runtime_dis_dmic_clk_gating(uint32_t index) -{ -#if CONFIG_TIGERLAKE - /* Disable DMIC clock gating */ - io_reg_write(DMICLCTL, - (io_reg_read(DMICLCTL) | DMIC_DCGD)); -#endif -} - -static inline void cavs_pm_runtime_en_dmic_clk_gating(uint32_t index) -{ -#if CONFIG_TIGERLAKE - /* Enable DMIC clock gating */ - io_reg_write(DMICLCTL, - (io_reg_read(DMICLCTL) & ~DMIC_DCGD)); -#endif -} -static inline void cavs_pm_runtime_en_dmic_power(uint32_t index) -{ - (void) index; -#if CONFIG_TIGERLAKE - /* Enable DMIC power */ - io_reg_write(DMICLCTL, - (io_reg_read(DMICLCTL) | DMICLCTL_SPA)); -#endif -} -static inline void cavs_pm_runtime_dis_dmic_power(uint32_t index) -{ - (void) index; -#if CONFIG_TIGERLAKE - /* Disable DMIC power */ - io_reg_write(DMICLCTL, - (io_reg_read(DMICLCTL) & (~DMICLCTL_SPA))); -#endif -} -#endif /* #if defined(CONFIG_INTEL_DMIC) */ - -#ifdef __ZEPHYR__ -/* TODO: Zephyr has it's own core start */ -static inline void cavs_pm_runtime_core_dis_memory(uint32_t index) -{ -} - -static inline void cavs_pm_runtime_core_en_memory(uint32_t index) -{ -} - -#else - -static inline void cavs_pm_runtime_core_dis_memory(uint32_t index) -{ - void *core_memory_ptr; - extern uintptr_t _sof_core_s_start; - - /* Address is calculated for index (0 for the primary core) minus one - * since _sof_core_s_start is first secondary core stack address - */ - core_memory_ptr = (char *)&_sof_core_s_start - + (index - 1) * SOF_CORE_S_SIZE; - - cavs_pm_memory_hp_sram_power_gate(core_memory_ptr, SOF_CORE_S_SIZE, - false); -} - -static inline void cavs_pm_runtime_core_en_memory(uint32_t index) -{ - void *core_memory_ptr; - extern uintptr_t _sof_core_s_start; - - /* Address is calculated for index (0 for the primary core) minus one - * since _sof_core_s_start is first secondary core stack address - */ - core_memory_ptr = (char *)&_sof_core_s_start - + (index - 1) * SOF_CORE_S_SIZE; - - cavs_pm_memory_hp_sram_power_gate(core_memory_ptr, SOF_CORE_S_SIZE, - true); -} -#endif - -static inline void cavs_pm_runtime_core_dis_hp_clk(uint32_t index) -{ - int all_active_cores_sleep; - int enabled_cores = cpu_enabled_cores(); - struct pm_runtime_data *prd = pm_runtime_data_get(); - struct cavs_pm_runtime_data *pprd = prd->platform_data; - k_spinlock_key_t key; - - key = k_spin_lock(&prd->lock); - - pprd->sleep_core_mask |= BIT(index); - - all_active_cores_sleep = - (enabled_cores & pprd->sleep_core_mask) == enabled_cores; - - if (all_active_cores_sleep) - clock_low_power_mode(CLK_CPU(index), true); - - k_spin_unlock(&prd->lock, key); -} - -static inline void cavs_pm_runtime_core_en_hp_clk(uint32_t index) -{ - struct pm_runtime_data *prd = pm_runtime_data_get(); - struct cavs_pm_runtime_data *pprd = prd->platform_data; - k_spinlock_key_t key; - - key = k_spin_lock(&prd->lock); - - pprd->sleep_core_mask &= ~BIT(index); - clock_low_power_mode(CLK_CPU(index), false); - - k_spin_unlock(&prd->lock, key); -} - -static inline void cavs_pm_runtime_dis_dsp_pg(uint32_t index) -{ - struct pm_runtime_data *prd = pm_runtime_data_get(); - struct cavs_pm_runtime_data *pprd = prd->platform_data; - uint32_t lps_ctl, tries = PLATFORM_PM_RUNTIME_DSP_TRIES; - uint32_t flag = PWRD_MASK & index; - - index &= ~PWRD_MASK; - - if (index == PLATFORM_PRIMARY_CORE_ID) { - lps_ctl = shim_read(SHIM_LPSCTL); - - shim_write16(SHIM_PWRCTL, shim_read16(SHIM_PWRCTL) | - SHIM_PWRCTL_TCPDSPPG(index) | - SHIM_PWRCTL_TCPCTLPG); - - lps_ctl &= ~SHIM_LPSCTL_BID; - lps_ctl &= ~SHIM_LPSCTL_BATTR_0; - lps_ctl |= SHIM_LPSCTL_FDSPRUN; - shim_write(SHIM_LPSCTL, lps_ctl); - } else { -#ifdef __ZEPHYR__ - /* - * In Zephyr secondary power-up needs to go via Zephyr - * SMP kernel core, so we can't program PWRCTL directly here. - */ - cpu_enable_secondary_core(index); -#else - /* Secondary core power up */ - shim_write16(SHIM_PWRCTL, shim_read16(SHIM_PWRCTL) | - SHIM_PWRCTL_TCPDSPPG(index) | - SHIM_PWRCTL_TCPCTLPG); -#endif - - /* Waiting for power up */ - while (((shim_read16(SHIM_PWRSTS) & SHIM_PWRCTL_TCPDSPPG(index)) != - SHIM_PWRCTL_TCPDSPPG(index)) && tries--) { - idelay(PLATFORM_PM_RUNTIME_DSP_DELAY); - } - /* Timeout check with warning log */ - if (tries == 0) - tr_err(&power_tr, "cavs_pm_runtime_dis_dsp_pg(): failed to power up core %d", - index); - pprd->dsp_client_bitmap[index] |= flag; - } -} - -static inline void cavs_pm_runtime_en_dsp_pg(uint32_t index) -{ - struct pm_runtime_data *prd = pm_runtime_data_get(); - struct cavs_pm_runtime_data *pprd = prd->platform_data; - uint32_t lps_ctl; - uint32_t flag = PWRD_MASK & index; - - index &= ~(PWRD_MASK); - - if (index == PLATFORM_PRIMARY_CORE_ID) { - lps_ctl = shim_read(SHIM_LPSCTL); - - shim_write16(SHIM_PWRCTL, 0); - - lps_ctl |= SHIM_LPSCTL_BID | SHIM_LPSCTL_BATTR_0; - lps_ctl &= ~SHIM_LPSCTL_FDSPRUN; - shim_write(SHIM_LPSCTL, lps_ctl); - } else { - pprd->dsp_client_bitmap[index] &= ~(flag); - - if (pprd->dsp_client_bitmap[index] == 0) - shim_write16(SHIM_PWRCTL, shim_read16(SHIM_PWRCTL) & - ~SHIM_PWRCTL_TCPDSPPG(index)); - } -} - -void platform_pm_runtime_init(struct pm_runtime_data *prd) -{ - struct cavs_pm_runtime_data *pprd; - - pprd = rzalloc(SOF_MEM_ZONE_SYS_SHARED, 0, SOF_MEM_CAPS_RAM, sizeof(*pprd)); - prd->platform_data = pprd; -} - -void platform_pm_runtime_get(enum pm_runtime_context context, uint32_t index, - uint32_t flags) -{ - /* Action based on context */ - switch (context) { - case PM_RUNTIME_HOST_DMA_L1: - cavs_pm_runtime_host_dma_l1_get(); - break; -#if CONFIG_INTEL_SSP - case SSP_CLK: - break; - case SSP_POW: - cavs_pm_runtime_en_ssp_power(index); - break; -#endif -#if CONFIG_INTEL_DMIC - case DMIC_CLK: - cavs_pm_runtime_dis_dmic_clk_gating(index); - break; - case DMIC_POW: - cavs_pm_runtime_en_dmic_power(index); - break; -#endif - case DW_DMAC_CLK: - break; - case CORE_MEMORY_POW: - cavs_pm_runtime_core_en_memory(index); - break; - case CORE_HP_CLK: - cavs_pm_runtime_core_en_hp_clk(index); - break; - case PM_RUNTIME_DSP: - cavs_pm_runtime_dis_dsp_pg(index); - break; - default: - break; - } -} - -void platform_pm_runtime_put(enum pm_runtime_context context, uint32_t index, - uint32_t flags) -{ - switch (context) { - case PM_RUNTIME_HOST_DMA_L1: - cavs_pm_runtime_host_dma_l1_put(); - break; -#if CONFIG_INTEL_SSP - case SSP_CLK: - break; - case SSP_POW: - cavs_pm_runtime_dis_ssp_power(index); - break; -#endif -#if CONFIG_INTEL_DMIC - case DMIC_CLK: - cavs_pm_runtime_en_dmic_clk_gating(index); - break; - case DMIC_POW: - cavs_pm_runtime_dis_dmic_power(index); - break; -#endif - case DW_DMAC_CLK: - break; - case CORE_MEMORY_POW: - cavs_pm_runtime_core_dis_memory(index); - break; - case CORE_HP_CLK: - cavs_pm_runtime_core_dis_hp_clk(index); - break; - case PM_RUNTIME_DSP: - cavs_pm_runtime_en_dsp_pg(index); - break; - default: - break; - } -} - -void platform_pm_runtime_enable(uint32_t context, uint32_t index) -{ - switch (context) { - case PM_RUNTIME_DSP: - cavs_pm_runtime_enable_dsp(true); - break; - default: - break; - } -} - -void platform_pm_runtime_prepare_d0ix_en(uint32_t index) -{ - struct pm_runtime_data *prd = pm_runtime_data_get(); - struct cavs_pm_runtime_data *pprd = prd->platform_data; - k_spinlock_key_t key; - - key = k_spin_lock(&prd->lock); - - pprd->prepare_d0ix_core_mask |= BIT(index); - - k_spin_unlock(&prd->lock, key); -} - -void platform_pm_runtime_prepare_d0ix_dis(uint32_t index) -{ - struct pm_runtime_data *prd = pm_runtime_data_get(); - struct cavs_pm_runtime_data *pprd = prd->platform_data; - k_spinlock_key_t key; - - key = k_spin_lock(&prd->lock); - - pprd->prepare_d0ix_core_mask &= ~BIT(index); - - k_spin_unlock(&prd->lock, key); -} - -int platform_pm_runtime_prepare_d0ix_is_req(uint32_t index) -{ - struct pm_runtime_data *prd = pm_runtime_data_get(); - struct cavs_pm_runtime_data *pprd = prd->platform_data; - - return pprd->prepare_d0ix_core_mask & BIT(index); -} - -void platform_pm_runtime_disable(uint32_t context, uint32_t index) -{ - switch (context) { - case PM_RUNTIME_DSP: - cavs_pm_runtime_enable_dsp(false); - break; - default: - break; - } -} - -bool platform_pm_runtime_is_active(uint32_t context, uint32_t index) -{ - switch (context) { - case PM_RUNTIME_DSP: - return cavs_pm_runtime_is_active_dsp(); - default: - assert(false); /* unsupported query */ - return false; - } - -} - -void platform_pm_runtime_power_off(void) -{ - uint32_t hpsram_mask[PLATFORM_HPSRAM_SEGMENTS], i; - int ret; - - /* check if DSP is busy sending IPC for 2ms */ - ret = poll_for_register_delay(IPC_HOST_BASE + IPC_DIPCIDR, - IPC_DIPCIDR_BUSY, 0, - 2000); - /* did command succeed */ - if (ret < 0) - tr_err(&power_tr, "failed to wait for DSP sent IPC handled."); - - /* power down entire HPSRAM */ - for (i = 0; i < PLATFORM_HPSRAM_SEGMENTS; i++) - hpsram_mask[i] = HPSRAM_MASK(i); - - power_down(true, uncache_to_cache(&hpsram_mask[0])); -} diff --git a/src/platform/intel/cavs/lib/power_down.S b/src/platform/intel/cavs/lib/power_down.S deleted file mode 100644 index c3f5523c144c..000000000000 --- a/src/platform/intel/cavs/lib/power_down.S +++ /dev/null @@ -1,187 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2016 Intel Corporation. All rights reserved. - * - * Author: Lech Betlej - */ - -/** - * \file platform/intel/cavs/lib/power_down.S - * \brief Power gating memory banks - implementation specific for platforms - * with cAVS 2.5 (i.e. Tiger Lake) - * \author Lech Betlej - */ - - -#include -#include -#include -#include -#include -#include - - .section .text, "ax" - .align 64 -power_down_literals: - .literal_position -#if CONFIG_IPC_MAJOR_3 -ipc_flag: - .word IPC_DIPCTDR_BUSY -#elif CONFIG_IPC_MAJOR_4 -set_dx_reply: - /* BUSY (bit31), MODULE_MSG (bit30), reply (bit29), SET_DX (bit 24-28: 7) */ - .word 0xE7000000 - -#endif -sram_dis_loop_cnt: - .word 4096 - - .global power_down - .type power_down, @function - -/** - * Perform power down. - * - * Depending on arguments, memories are switched off. - * A2 - argument for LPSRAM - * A3 - pointer to array containing power gating mask. - *Size of array is determined by MEMORY_SEGMENTS define. - * A4 - platform type - * A5 - response_to_ipc - */ - -#define b_enable_lpsram a2 -#define pu32_hpsram_mask a3 -#define temp_reg0 a6 -#define temp_reg1 a7 -#define temp_reg2 a8 -#define temp_reg3 a9 -#define host_base a10 -#define pfl_reg a15 - -power_down: - entry sp, 32 - // effectively executes: - // xthal_dcache_region_lock(&literals, 128); - // xthal_dcache_region_lock(&powerdown, 256); - // xthal_dcache_region_lock(&pu32_hpsram_mask, 64); - movi pfl_reg, power_down_literals - dpfl pfl_reg, 0 - dpfl pfl_reg, 64 - - movi pfl_reg, power_down - ipfl pfl_reg, 0 - ipfl pfl_reg, 64 - ipfl pfl_reg, 128 - ipfl pfl_reg, 192 - - mov pfl_reg, pu32_hpsram_mask - dpfl pfl_reg, 0 - -_PD_DISABLE_LPSRAM: -/* effectively executes: - * if (b_enable_lpsram){ - * cavs_lpsram_power_down_entire(); - * } - */ - movi host_base, IPC_HOST_BASE - - beqz b_enable_lpsram, _PD_DISABLE_HPSRAM - m_cavs_lpsram_power_down_entire temp_reg0, temp_reg1, temp_reg2,\ - sram_dis_loop_cnt - j _PD_DISABLE_HPSRAM - -_PD_DISABLE_HPSRAM: - /* if value in memory pointed by pu32_hpsram_mask = 0 - (hpsram_pwrgating_mask) - do not disable hpsram. */ - beqz pu32_hpsram_mask, _PD_SEND_IPC - -/* mandatory sequence for LDO ON - effectively executes: - * m_cavs_s_set_ldo_hpsram_on_state(); - * WAIT_300NS(); - */ - movi temp_reg0, SHIM_LDOCTL_HPSRAM_LDO_ON - m_cavs_set_hpldo_state temp_reg0, temp_reg1, temp_reg2 - movi temp_reg0, 128 -1 : - addi temp_reg0, temp_reg0, -1 - bnez temp_reg0, 1b - - -/* effectively executes: - * for (size_t seg_index = (MAX_MEMORY_SEGMENTS - 1); seg_index >= 0; - * --seg_index) { - * cavs_hpsram_power_change(seg_index, mask[seg_index]); - * } - * where mask is given in pu32_hpsram_mask register - */ - - .set seg_index, MAX_MEMORY_SEGMENTS - 1 - .rept MAX_MEMORY_SEGMENTS - l32i temp_reg0, pu32_hpsram_mask, 4 * seg_index - m_cavs_hpsram_power_change\ - /*segment_index=*/ seg_index,\ - /*mask=*/ temp_reg0,\ - temp_reg1,\ - temp_reg2,\ - temp_reg3 - .set seg_index, seg_index - 1 - .endr - - -/* mandatory sequence for LDO OFF - effectively executes: - * WAIT_300NS(); - * m_cavs_set_ldo_hpsram_on_state() - */ - movi temp_reg0, 128 -1 : - addi temp_reg0, temp_reg0, -1 - bnez temp_reg0, 1b - - movi temp_reg0, SHIM_LDOCTL_HPSRAM_LDO_OFF - m_cavs_set_hpldo_state temp_reg0, temp_reg1, temp_reg2 - -_PD_SEND_IPC: -#if CONFIG_IPC_MAJOR_3 -/* Send IPC to host informing of PD completion - Clear BUSY - * bit by writing IPC_DIPCTDR_BUSY to IPC_DIPCTDR - * and writing IPC_DIPCTDA_DONE to IPC_DIPCTDA - */ - l32i temp_reg1, host_base, IPC_DIPCTDR - movi temp_reg2, ipc_flag - l32i temp_reg2, temp_reg2, 0 - or temp_reg1, temp_reg1, temp_reg2 - s32i temp_reg1, host_base, IPC_DIPCTDR - - l32i temp_reg1, host_base, IPC_DIPCTDA - or temp_reg1, temp_reg1, temp_reg2 - s32i temp_reg1, host_base, IPC_DIPCTDA -#elif CONFIG_IPC_MAJOR_4 -/* Send IPC reply for SET_DX message */ - movi temp_reg1, 0 - s32i temp_reg1, host_base, IPC_DIPCIDD - - movi temp_reg1, set_dx_reply - l32i temp_reg1, temp_reg1, 0 - s32i temp_reg1, host_base, IPC_DIPCIDR -#else -#error "Support for this IPC version is not implemented" -#endif - -_PD_SLEEP: -/* effecfively executes: - * xmp_spin() - * waiti 5 - */ - movi temp_reg0, 128 -loop: - addi temp_reg0, temp_reg0, -1 - bnez temp_reg0, loop - - extw - extw - waiti 5 - 1: - j 1b - -.size power_down , . - power_down diff --git a/src/platform/tigerlake/CMakeLists.txt b/src/platform/tigerlake/CMakeLists.txt deleted file mode 100644 index d7462e527e47..000000000000 --- a/src/platform/tigerlake/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: BSD-3-Clause - -add_subdirectory(lib) - -add_executable(boot_module boot_module.c) -add_executable(base_module base_module.c) - -target_link_libraries(boot_module sof_options) -target_link_libraries(base_module sof_options) - -sof_append_relative_path_definitions(boot_module) -sof_append_relative_path_definitions(base_module) diff --git a/src/platform/tigerlake/base_module.c b/src/platform/tigerlake/base_module.c deleted file mode 100644 index 901fad20a925..000000000000 --- a/src/platform/tigerlake/base_module.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2018 Intel Corporation. All rights reserved. -// -// Author: Liam Girdwood -// Janusz Jankowski - -#include -#include - -/* - * Each module has an entry in the FW manifest header. This is NOT part of - * the SOF executable image but is inserted by object copy as a ELF section - * for parsing by rimage (to genrate the manifest). - */ -struct sof_man_module_manifest tgl_manifest = { - .module = { - .name = "BASEFW", - .uuid = {0x32, 0x8c, 0x39, 0x0e, 0xde, 0x5a, 0x4b, 0xba, - 0x93, 0xb1, 0xc5, 0x04, 0x32, 0x28, 0x0e, 0xe4}, - .entry_point = SOF_TEXT_START, - .type = { - .load_type = SOF_MAN_MOD_TYPE_MODULE, - .domain_ll = 1, - }, - .affinity_mask = 3, - }, -}; - -/* not used, but stops linker complaining */ -int _start; diff --git a/src/platform/tigerlake/boot_ldr.x.in b/src/platform/tigerlake/boot_ldr.x.in deleted file mode 100644 index 2375f2080ade..000000000000 --- a/src/platform/tigerlake/boot_ldr.x.in +++ /dev/null @@ -1,247 +0,0 @@ -/* - * Linker Script for Tigerlake Bootloader. - * - * This script is run through the GNU C preprocessor to align the memory - * offsets with headers. - * - * Use spaces for formatting as cpp ignore tab sizes. - */ - - -#include -#include - -OUTPUT_ARCH(xtensa) - -MEMORY -{ - boot_entry_text : - org = IMR_BOOT_LDR_TEXT_ENTRY_BASE, - len = IMR_BOOT_LDR_TEXT_ENTRY_SIZE - boot_entry_lit : - org = IMR_BOOT_LDR_LIT_BASE, - len = IMR_BOOT_LDR_LIT_SIZE - sof_text : - org = IMR_BOOT_LDR_TEXT_BASE, - len = IMR_BOOT_LDR_TEXT_SIZE, - sof_data : - org = IMR_BOOT_LDR_DATA_BASE, - len = IMR_BOOT_LDR_DATA_SIZE - sof_bss_data : - org = IMR_BOOT_LDR_BSS_BASE, - len = IMR_BOOT_LDR_BSS_SIZE - sof_stack : - org = BOOT_LDR_STACK_BASE, - len = BOOT_LDR_STACK_SIZE - wnd0 : - org = HP_SRAM_WIN0_BASE, - len = HP_SRAM_WIN0_SIZE - lpsram_mem : - org = LP_SRAM_BASE, - len = LP_SRAM_SIZE -} - -PHDRS -{ - boot_entry_text_phdr PT_LOAD; - boot_entry_lit_phdr PT_LOAD; - sof_text_phdr PT_LOAD; - sof_data_phdr PT_LOAD; - sof_bss_data_phdr PT_LOAD; - sof_stack_phdr PT_LOAD; - wnd0_phdr PT_LOAD; - lpsram_mem_phdr PT_LOAD; -} - -/* Default entry point: */ -ENTRY(boot_entry) -EXTERN(reset_vector) - -SECTIONS -{ - .boot_entry.text : ALIGN(4) - { - _boot_entry_text_start = ABSOLUTE(.); - KEEP (*(.boot_entry.text)) - _boot_entry_text_end = ABSOLUTE(.); - } >boot_entry_text :boot_entry_text_phdr - - .boot_entry.literal : ALIGN(4) - { - _boot_entry_literal_start = ABSOLUTE(.); - *(.boot_entry.literal) - *(.literal .literal.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - _boot_entry_literal_end = ABSOLUTE(.); - } >boot_entry_lit :boot_entry_lit_phdr - - .text : ALIGN(4) - { - _stext = .; - _text_start = ABSOLUTE(.); - *(.entry.text) - *(.init.literal) - KEEP(*(.init)) - *( .text .text.*) - *(.fini.literal) - KEEP(*(.fini)) - *(.gnu.version) - KEEP (*(.ResetVector.text)) - KEEP (*(.ResetHandler.text)) - _text_end = ABSOLUTE(.); - _etext = .; - } >sof_text :sof_text_phdr - - .rodata : ALIGN(4) - { - _rodata_start = ABSOLUTE(.); - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); - KEEP (*(.xt_except_table)) - KEEP (*(.gcc_except_table)) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - KEEP (*(.eh_frame)) - /* C++ constructor and destructor tables, properly ordered: */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); /* this table MUST be 4-byte aligned */ - _bss_table_start = ABSOLUTE(.); - LONG(_bss_start) - LONG(_bss_end) - _bss_table_end = ABSOLUTE(.); - _rodata_end = ABSOLUTE(.); - } >sof_data :sof_data_phdr - - .data : ALIGN(4) - { - _data_start = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - KEEP(*(.gnu.linkonce.d.*personality*)) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - KEEP(*(.jcr)) - _data_end = ABSOLUTE(.); - } >sof_data :sof_data_phdr - - .lit4 : ALIGN(4) - { - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - } >sof_data :sof_data_phdr - - .bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN (8); - _bss_end = ABSOLUTE(.); - } >sof_bss_data :sof_bss_data_phdr - - _man = 0x1234567; - - PROVIDE(_memmap_vecbase_reset = HP_SRAM_VECBASE_RESET); - - _memmap_cacheattr_wbna_trapnull = 0xFF42FFF2; - PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull); - - __stack = BOOT_LDR_STACK_BASE + BOOT_LDR_STACK_SIZE; - __wnd0 = HP_SRAM_WIN0_BASE; - __wnd0_size = HP_SRAM_WIN0_SIZE; - - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .xt.profile_range 0 : - { - KEEP (*(.xt.profile_range)) - KEEP (*(.gnu.linkonce.profile_range.*)) - } - .xt.profile_ranges 0 : - { - KEEP (*(.xt.profile_ranges)) - KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) - } - .xt.profile_files 0 : - { - KEEP (*(.xt.profile_files)) - KEEP (*(.gnu.linkonce.xt.profile_files.*)) - } - .lpsram(NOLOAD) : ALIGN(8) - { - _lpsram_start = ABSOLUTE(.); - KEEP (*(*.lpsram)) - _lpsram_end = ABSOLUTE(.); - } >lpsram_mem :lpsram_mem_phdr -} diff --git a/src/platform/tigerlake/boot_module.c b/src/platform/tigerlake/boot_module.c deleted file mode 100644 index 85886a1f79e7..000000000000 --- a/src/platform/tigerlake/boot_module.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2018 Intel Corporation. All rights reserved. -// -// Author: Liam Girdwood -// Janusz Jankowski - -#include -#include - -/* - * Each module has an entry in the FW manifest header. This is NOT part of - * the SOF executable image but is inserted by object copy as a ELF section - * for parsing by rimage (to genrate the manifest). - */ -struct sof_man_module_manifest tgl_bootldr_manifest = { - .module = { - .name = "BRNGUP", - .uuid = {0xf3, 0xe4, 0x79, 0x2b, 0x75, 0x46, 0x49, 0xf6, - 0x89, 0xdf, 0x3b, 0xc1, 0x94, 0xa9, 0x1a, 0xeb}, - .entry_point = IMR_BOOT_LDR_TEXT_ENTRY_BASE, - .type = { - .load_type = SOF_MAN_MOD_TYPE_MODULE, - .domain_ll = 1, - }, - .affinity_mask = 3, - }, -}; - -/* not used, but stops linker complaining */ -int _start; diff --git a/src/platform/tigerlake/include/arch/xtensa/config/core-isa.h b/src/platform/tigerlake/include/arch/xtensa/config/core-isa.h deleted file mode 100644 index 95afb9588332..000000000000 --- a/src/platform/tigerlake/include/arch/xtensa/config/core-isa.h +++ /dev/null @@ -1,636 +0,0 @@ -/* - * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa - * processor CORE configuration - * - * See , which includes this file, for more details. - */ - -/* Xtensa processor core configuration information. - - Copyright (c) 1999-2019 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#if !defined __XCC__ - -#ifndef _XTENSA_CORE_CONFIGURATION_H -#define _XTENSA_CORE_CONFIGURATION_H - - -/**************************************************************************** - Parameters Useful for Any Code, USER or PRIVILEGED - ****************************************************************************/ - -/* - * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is - * configured, and a value of 0 otherwise. These macros are always defined. - */ - - -/*---------------------------------------------------------------------- - ISA - ----------------------------------------------------------------------*/ - -#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ -#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ -#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ -#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ -#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */ -#define XCHAL_HAVE_DEBUG 1 /* debug option */ -#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ -#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ -#define XCHAL_LOOP_BUFFER_SIZE 64 /* zero-ov. loop instr buffer size */ -#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ -#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ -#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ -#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ -#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ -#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ -#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ -#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ -#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ -#define XCHAL_HAVE_L32R 1 /* L32R instruction */ -#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ -#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ -#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ -#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */ -#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ -#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ -#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ -#define XCHAL_HAVE_ABS 1 /* ABS instruction */ -/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ -/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ -#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ -#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ -#define XCHAL_HAVE_SPECULATION 0 /* speculation */ -#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ -#define XCHAL_NUM_CONTEXTS 1 /* */ -#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */ -#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ -#define XCHAL_HAVE_PRID 1 /* processor ID register */ -#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ -#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ -#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ -#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ -#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ -#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ -#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ -#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ -#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ -#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ -#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */ -#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ - -#define XCHAL_HAVE_FUSION 0 /* Fusion*/ -#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ -#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ -#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ -#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ -#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ -#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ -#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ -#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ -#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ -#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ -#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ -#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ -#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ -#define XCHAL_HAVE_HIFI3 1 /* HiFi3 Audio Engine pkg */ -#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ -#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */ -#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */ -#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ -#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ -#define XCHAL_HAVE_HIFI_MINI 0 - - - -#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ -#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ -#define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */ -#define XCHAL_HAVE_FP 1 /* single prec floating point */ -#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */ -#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ -#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ -#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ -#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ -#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ -#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ -#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ -#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ -#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ -#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ - -#define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */ -#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ -#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ -#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ - -#define XCHAL_HAVE_FUSIONG 0 /* FusionG */ -#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */ -#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */ -#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */ -#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */ -#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ - -#define XCHAL_HAVE_PDX 0 /* PDX */ -#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */ -#define XCHAL_HAVE_PDX4 0 /* PDX4 */ -#define XCHAL_HAVE_PDX8 0 /* PDX8 */ -#define XCHAL_HAVE_PDX16 0 /* PDX16 */ - -#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ -#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ -#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ -#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ -#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ -#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ -#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ -#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */ -#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ -#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ -#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ -#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ -#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ -#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ -#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ -#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ -#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ - -#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */ -#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ -#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, or P3 */ -#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */ -#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */ -#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6 */ -#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6 */ - -#define XCHAL_HAVE_VISIONC 0 /* Vision C */ - -/*---------------------------------------------------------------------- - MISC - ----------------------------------------------------------------------*/ - -#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ -#define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */ -#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */ -#define XCHAL_DATA_WIDTH 8 /* data width in bytes */ -#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay - (1 = 5-stage, 2 = 7-stage) */ -#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ -#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ -/* In T1050, applies to selected core load and store instructions (see ISA): */ -#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ -#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ -#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ -#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ - -#define XCHAL_SW_VERSION 1200008 /* sw version of this header */ - -#define XCHAL_CORE_ID "cavs2x_LX6HiFi3_2017_8" /* alphanum core name - (CoreID) set in the Xtensa - Processor Generator */ - -#define XCHAL_BUILD_UNIQUE_ID 0x0007AF71 /* 22-bit sw build ID */ - -/* - * These definitions describe the hardware targeted by this software. - */ -#define XCHAL_HW_CONFIGID0 0xC2F3FBFE /* ConfigID hi 32 bits*/ -#define XCHAL_HW_CONFIGID1 0x1CC6C29B /* ConfigID lo 32 bits*/ -#define XCHAL_HW_VERSION_NAME "LX6.0.3" /* full version name */ -#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */ -#define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */ -#define XCHAL_HW_VERSION 260003 /* major*100+minor */ -#define XCHAL_HW_REL_LX6 1 -#define XCHAL_HW_REL_LX6_0 1 -#define XCHAL_HW_REL_LX6_0_3 1 -#define XCHAL_HW_CONFIGID_RELIABLE 1 -/* If software targets a *range* of hardware versions, these are the bounds: */ -#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */ -#define XCHAL_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */ -#define XCHAL_HW_MIN_VERSION 260003 /* earliest targeted hw */ -#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */ -#define XCHAL_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */ -#define XCHAL_HW_MAX_VERSION 260003 /* latest targeted hw */ - - -/*---------------------------------------------------------------------- - CACHE - ----------------------------------------------------------------------*/ - -#define XCHAL_ICACHE_LINESIZE 64 /* I-cache line size in bytes */ -#define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */ -#define XCHAL_ICACHE_LINEWIDTH 6 /* log2(I line size in bytes) */ -#define XCHAL_DCACHE_LINEWIDTH 6 /* log2(D line size in bytes) */ - -#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ -#define XCHAL_DCACHE_SIZE 49152 /* D-cache size in bytes or 0 */ - -#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ -#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ - -#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ -#define XCHAL_HAVE_PREFETCH_L1 1 /* prefetch to L1 dcache */ -#define XCHAL_PREFETCH_CASTOUT_LINES 2 /* dcache pref. castout bufsz */ -#define XCHAL_PREFETCH_ENTRIES 8 /* cache prefetch entries */ -#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ -#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ -#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ -#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ -#define XCHAL_HAVE_ICACHE_DYN_WAYS 1 /* Icache dynamic way support */ -#define XCHAL_HAVE_DCACHE_DYN_WAYS 1 /* Dcache dynamic way support */ - - - - -/**************************************************************************** - Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code - ****************************************************************************/ - - -#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY - -/*---------------------------------------------------------------------- - CACHE - ----------------------------------------------------------------------*/ - -#define XCHAL_HAVE_PIF 1 /* any outbound bus present */ - -#define XCHAL_HAVE_AXI 0 /* AXI bus */ -#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */ -#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ - -#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ -#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */ - -/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ - -/* Number of cache sets in log2(lines per way): */ -#define XCHAL_ICACHE_SETWIDTH 6 -#define XCHAL_DCACHE_SETWIDTH 8 - -/* Cache set associativity (number of ways): */ -#define XCHAL_ICACHE_WAYS 4 -#define XCHAL_DCACHE_WAYS 3 - -/* Cache features: */ -#define XCHAL_ICACHE_LINE_LOCKABLE 1 -#define XCHAL_DCACHE_LINE_LOCKABLE 1 -#define XCHAL_ICACHE_ECC_PARITY XTHAL_MEMEP_ECC -#define XCHAL_DCACHE_ECC_PARITY XTHAL_MEMEP_ECC - -/* Cache access size in bytes (affects operation of SICW instruction): */ -#define XCHAL_ICACHE_ACCESS_SIZE 8 -#define XCHAL_DCACHE_ACCESS_SIZE 8 - -#define XCHAL_DCACHE_BANKS 1 /* number of banks */ - -/* Number of encoded cache attr bits (see for decoded bits): */ -#define XCHAL_CA_BITS 4 - - -/*---------------------------------------------------------------------- - INTERNAL I/D RAM/ROMs and XLMI - ----------------------------------------------------------------------*/ -#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ -#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ -#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ -#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */ -#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ -#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */ - -/* Instruction RAM 0: */ -#define XCHAL_INSTRAM0_VADDR 0x9F100000 /* virtual address */ -#define XCHAL_INSTRAM0_PADDR 0x9F100000 /* physical address */ -#define XCHAL_INSTRAM0_SIZE 1048576 /* size in bytes */ -#define XCHAL_INSTRAM0_ECC_PARITY XTHAL_MEMEP_ECC /* ECC/parity type, 0=none */ -#define XCHAL_HAVE_INSTRAM0 1 -#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */ - -/* Data RAM 0: */ -#define XCHAL_DATARAM0_VADDR 0x9F000000 /* virtual address */ -#define XCHAL_DATARAM0_PADDR 0x9F000000 /* physical address */ -#define XCHAL_DATARAM0_SIZE 524288 /* size in bytes */ -#define XCHAL_DATARAM0_ECC_PARITY XTHAL_MEMEP_ECC /* ECC/parity type, 0=none */ -#define XCHAL_DATARAM0_BANKS 1 /* number of banks */ -#define XCHAL_HAVE_DATARAM0 1 -#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */ - -/* XLMI Port 0: */ -#define XCHAL_XLMI0_VADDR 0x9F080000 /* virtual address */ -#define XCHAL_XLMI0_PADDR 0x9F080000 /* physical address */ -#define XCHAL_XLMI0_SIZE 65536 /* size in bytes */ -#define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */ - -#define XCHAL_HAVE_IDMA 0 -#define XCHAL_HAVE_IDMA_TRANSPOSE 0 - -#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ - - -/*---------------------------------------------------------------------- - INTERRUPTS and TIMERS - ----------------------------------------------------------------------*/ - -#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ -#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ -#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ -#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ -#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ -#define XCHAL_NUM_INTERRUPTS 21 /* number of interrupts */ -#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ -#define XCHAL_NUM_EXTINTERRUPTS 8 /* num of external interrupts */ -#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels - (not including level zero) */ -#define XCHAL_EXCM_LEVEL 5 /* level masked by PS.EXCM */ - /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ - -/* Masks of interrupts at each interrupt level: */ -#define XCHAL_INTLEVEL1_MASK 0x0000000F -#define XCHAL_INTLEVEL2_MASK 0x000000F0 -#define XCHAL_INTLEVEL3_MASK 0x00000F00 -#define XCHAL_INTLEVEL4_MASK 0x00007000 -#define XCHAL_INTLEVEL5_MASK 0x000F8000 -#define XCHAL_INTLEVEL6_MASK 0x00000000 -#define XCHAL_INTLEVEL7_MASK 0x00100000 - -/* Masks of interrupts at each range 1..n of interrupt levels: */ -#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x0000000F -#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x000000FF -#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00000FFF -#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00007FFF -#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x000FFFFF -#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x000FFFFF -#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x001FFFFF - -/* Level of each interrupt: */ -#define XCHAL_INT0_LEVEL 1 -#define XCHAL_INT1_LEVEL 1 -#define XCHAL_INT2_LEVEL 1 -#define XCHAL_INT3_LEVEL 1 -#define XCHAL_INT4_LEVEL 2 -#define XCHAL_INT5_LEVEL 2 -#define XCHAL_INT6_LEVEL 2 -#define XCHAL_INT7_LEVEL 2 -#define XCHAL_INT8_LEVEL 3 -#define XCHAL_INT9_LEVEL 3 -#define XCHAL_INT10_LEVEL 3 -#define XCHAL_INT11_LEVEL 3 -#define XCHAL_INT12_LEVEL 4 -#define XCHAL_INT13_LEVEL 4 -#define XCHAL_INT14_LEVEL 4 -#define XCHAL_INT15_LEVEL 5 -#define XCHAL_INT16_LEVEL 5 -#define XCHAL_INT17_LEVEL 5 -#define XCHAL_INT18_LEVEL 5 -#define XCHAL_INT19_LEVEL 5 -#define XCHAL_INT20_LEVEL 7 -#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ -#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ -#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with - EXCSAVE/EPS/EPC_n, RFI n) */ - -/* Type of each interrupt: */ -#define XCHAL_INT0_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT1_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT3_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT4_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT5_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT8_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT9_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT12_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT14_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT15_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT19_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT20_TYPE XTHAL_INTTYPE_NMI - -/* Masks of interrupts for each type of interrupt: */ -#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFE00000 -#define XCHAL_INTTYPE_MASK_SOFTWARE 0x0008D999 -#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000 -#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x00072444 -#define XCHAL_INTTYPE_MASK_TIMER 0x00000222 -#define XCHAL_INTTYPE_MASK_NMI 0x00100000 -#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 -#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000 -#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000 -#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000 -#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000 - -/* Interrupt numbers assigned to specific interrupt sources: */ -#define XCHAL_TIMER0_INTERRUPT 1 /* CCOMPARE0 */ -#define XCHAL_TIMER1_INTERRUPT 5 /* CCOMPARE1 */ -#define XCHAL_TIMER2_INTERRUPT 9 /* CCOMPARE2 */ -#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED -#define XCHAL_NMI_INTERRUPT 20 /* non-maskable interrupt */ - -/* Interrupt numbers for levels at which only one interrupt is configured: */ -#define XCHAL_INTLEVEL7_NUM 20 -/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */ - - -/* - * External interrupt mapping. - * These macros describe how Xtensa processor interrupt numbers - * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) - * map to external BInterrupt pins, for those interrupts - * configured as external (level-triggered, edge-triggered, or NMI). - * See the Xtensa processor databook for more details. - */ - -/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ -#define XCHAL_EXTINT0_NUM 2 /* (intlevel 1) */ -#define XCHAL_EXTINT1_NUM 6 /* (intlevel 2) */ -#define XCHAL_EXTINT2_NUM 10 /* (intlevel 3) */ -#define XCHAL_EXTINT3_NUM 13 /* (intlevel 4) */ -#define XCHAL_EXTINT4_NUM 16 /* (intlevel 5) */ -#define XCHAL_EXTINT5_NUM 17 /* (intlevel 5) */ -#define XCHAL_EXTINT6_NUM 18 /* (intlevel 5) */ -#define XCHAL_EXTINT7_NUM 20 /* (intlevel 7) */ -/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ -#define XCHAL_INT2_EXTNUM 0 /* (intlevel 1) */ -#define XCHAL_INT6_EXTNUM 1 /* (intlevel 2) */ -#define XCHAL_INT10_EXTNUM 2 /* (intlevel 3) */ -#define XCHAL_INT13_EXTNUM 3 /* (intlevel 4) */ -#define XCHAL_INT16_EXTNUM 4 /* (intlevel 5) */ -#define XCHAL_INT17_EXTNUM 5 /* (intlevel 5) */ -#define XCHAL_INT18_EXTNUM 6 /* (intlevel 5) */ -#define XCHAL_INT20_EXTNUM 7 /* (intlevel 7) */ - - -/*---------------------------------------------------------------------- - EXCEPTIONS and VECTORS - ----------------------------------------------------------------------*/ - -#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture - number: 1 == XEA1 (old) - 2 == XEA2 (new) - 0 == XEAX (extern) or TX */ -#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ -#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ -#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ -#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ -#define XCHAL_HAVE_HALT 0 /* halt architecture option */ -#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ -#define XCHAL_HAVE_MEM_ECC_PARITY 1 /* local memory ECC/parity */ -#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ -#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ -#define XCHAL_VECBASE_RESET_VADDR 0x9F180800 /* VECBASE reset value */ -#define XCHAL_VECBASE_RESET_PADDR 0x9F180800 -#define XCHAL_RESET_VECBASE_OVERLAP 0 - -#define XCHAL_RESET_VECTOR0_VADDR 0x9F180000 -#define XCHAL_RESET_VECTOR0_PADDR 0x9F180000 -#define XCHAL_RESET_VECTOR1_VADDR 0xBE800000 -#define XCHAL_RESET_VECTOR1_PADDR 0xBE800000 -#define XCHAL_RESET_VECTOR_VADDR 0x9F180000 -#define XCHAL_RESET_VECTOR_PADDR 0x9F180000 -#define XCHAL_MEMERROR_VECTOR0_VADDR 0x9F180400 -#define XCHAL_MEMERROR_VECTOR0_PADDR 0x9F180400 -#define XCHAL_MEMERROR_VECTOR1_VADDR 0xBE800400 -#define XCHAL_MEMERROR_VECTOR1_PADDR 0xBE800400 -#define XCHAL_MEMERROR_VECTOR_VADDR 0x9F180400 -#define XCHAL_MEMERROR_VECTOR_PADDR 0x9F180400 -#define XCHAL_USER_VECOFS 0x00000340 -#define XCHAL_USER_VECTOR_VADDR 0x9F180B40 -#define XCHAL_USER_VECTOR_PADDR 0x9F180B40 -#define XCHAL_KERNEL_VECOFS 0x00000300 -#define XCHAL_KERNEL_VECTOR_VADDR 0x9F180B00 -#define XCHAL_KERNEL_VECTOR_PADDR 0x9F180B00 -#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 -#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x9F180BC0 -#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x9F180BC0 -#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 -#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 -#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 -#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 -#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 -#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 -#define XCHAL_WINDOW_VECTORS_VADDR 0x9F180800 -#define XCHAL_WINDOW_VECTORS_PADDR 0x9F180800 -#define XCHAL_INTLEVEL2_VECOFS 0x00000180 -#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x9F180980 -#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x9F180980 -#define XCHAL_INTLEVEL3_VECOFS 0x000001C0 -#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x9F1809C0 -#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x9F1809C0 -#define XCHAL_INTLEVEL4_VECOFS 0x00000200 -#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x9F180A00 -#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x9F180A00 -#define XCHAL_INTLEVEL5_VECOFS 0x00000240 -#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x9F180A40 -#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x9F180A40 -#define XCHAL_INTLEVEL6_VECOFS 0x00000280 -#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x9F180A80 -#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x9F180A80 -#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS -#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR -#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR -#define XCHAL_NMI_VECOFS 0x000002C0 -#define XCHAL_NMI_VECTOR_VADDR 0x9F180AC0 -#define XCHAL_NMI_VECTOR_PADDR 0x9F180AC0 -#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS -#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR -#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR - - -/*---------------------------------------------------------------------- - DEBUG MODULE - ----------------------------------------------------------------------*/ - -/* Misc */ -#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */ -#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ -#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ - -/* On-Chip Debug (OCD) */ -#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ -#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ -#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ -#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ -#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ - -/* TRAX (in core) */ -#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */ -#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */ -#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ -#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ -#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ - -/* Perf counters */ -#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */ - - -/*---------------------------------------------------------------------- - MMU - ----------------------------------------------------------------------*/ - -/* See core-matmap.h header file for more details. */ - -#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ -#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ -#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ -#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ -#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ -#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ -#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ -#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table - [autorefill] and protection) - usable for an MMU-based OS */ - -/* If none of the above last 5 are set, it's a custom TLB configuration. */ - -#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ -#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ -#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ - -/*---------------------------------------------------------------------- - MPU - ----------------------------------------------------------------------*/ -#define XCHAL_HAVE_MPU 0 -#define XCHAL_MPU_ENTRIES 0 - -#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ -#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ -#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ - -#define XCHAL_MPU_ALIGN_BITS 0 -#define XCHAL_MPU_ALIGN 0 - -#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ - - -#endif /* _XTENSA_CORE_CONFIGURATION_H */ - -#else - -#error "xcc should not use this header" - -#endif /* __XCC__ */ diff --git a/src/platform/tigerlake/include/arch/xtensa/config/core-matmap.h b/src/platform/tigerlake/include/arch/xtensa/config/core-matmap.h deleted file mode 100644 index d7fd7795e3f1..000000000000 --- a/src/platform/tigerlake/include/arch/xtensa/config/core-matmap.h +++ /dev/null @@ -1,324 +0,0 @@ -/* - * xtensa/config/core-matmap.h -- Memory access and translation mapping - * parameters (CHAL) of the Xtensa processor core configuration. - * - * If you are using Xtensa Tools, see (which includes - * this file) for more details. - * - * In the Xtensa processor products released to date, all parameters - * defined in this file are derivable (at least in theory) from - * information contained in the core-isa.h header file. - * In particular, the following core configuration parameters are relevant: - * XCHAL_HAVE_CACHEATTR - * XCHAL_HAVE_MIMIC_CACHEATTR - * XCHAL_HAVE_XLT_CACHEATTR - * XCHAL_HAVE_PTP_MMU - * XCHAL_ITLB_ARF_ENTRIES_LOG2 - * XCHAL_DTLB_ARF_ENTRIES_LOG2 - * XCHAL_DCACHE_IS_WRITEBACK - * XCHAL_ICACHE_SIZE (presence of I-cache) - * XCHAL_DCACHE_SIZE (presence of D-cache) - * XCHAL_HW_VERSION_MAJOR - * XCHAL_HW_VERSION_MINOR - */ - -/* Copyright (c) 1999-2018 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#if !defined __XCC__ - -#ifndef XTENSA_CONFIG_CORE_MATMAP_H -#define XTENSA_CONFIG_CORE_MATMAP_H - - -/*---------------------------------------------------------------------- - CACHE (MEMORY ACCESS) ATTRIBUTES - ----------------------------------------------------------------------*/ - - - -/* Cache Attribute encodings -- lists of access modes for each cache attribute: */ -#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_CACHED XCHAL_SEP \ - XTHAL_FAM_BYPASS XCHAL_SEP \ - XTHAL_FAM_CACHED XCHAL_SEP \ - XTHAL_FAM_CACHED XCHAL_SEP \ - XTHAL_FAM_CACHED XCHAL_SEP \ - XTHAL_FAM_BYPASS XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION -#define XCHAL_LCA_LIST XTHAL_LAM_CACHED_NOALLOC XCHAL_SEP \ - XTHAL_LAM_CACHED XCHAL_SEP \ - XTHAL_LAM_BYPASSG XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_CACHED XCHAL_SEP \ - XTHAL_LAM_CACHED XCHAL_SEP \ - XTHAL_LAM_BYPASSG XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_ISOLATE XCHAL_SEP \ - XTHAL_LAM_EXCEPTION -#define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \ - XTHAL_SAM_WRITETHRU XCHAL_SEP \ - XTHAL_SAM_BYPASS XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_WRITEBACK XCHAL_SEP \ - XTHAL_SAM_WRITEBACK_NOALLOC XCHAL_SEP \ - XTHAL_SAM_BYPASS XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_ISOLATE XCHAL_SEP \ - XTHAL_SAM_EXCEPTION - -#define XCHAL_CA_R (0xC0 | 0x40000000) -#define XCHAL_CA_RX (0xD0 | 0x40000000) -#define XCHAL_CA_RW (0xE0 | 0x40000000) -#define XCHAL_CA_RWX (0xF0 | 0x40000000) - -/* - * Specific encoded cache attribute values of general interest. - * If a specific cache mode is not available, the closest available - * one is returned instead (eg. writethru instead of writeback, - * bypass instead of writethru). - */ -#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */ -#define XCHAL_CA_BYPASSBUF 6 /* cache disabled (bypassed) bufferable mode */ -#define XCHAL_CA_WRITETHRU 1 /* cache enabled (write-through) mode */ -#define XCHAL_CA_WRITEBACK 4 /* cache enabled (write-back) mode */ -#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1 /* write-back no-allocate availability */ -#define XCHAL_CA_WRITEBACK_NOALLOC 5 /* cache enabled (write-back no-allocate) mode */ -#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */ -#define XCHAL_CA_ISOLATE 14 /* cache isolate (accesses go to cache not memory) mode */ - -/*---------------------------------------------------------------------- - MMU - ----------------------------------------------------------------------*/ - -/* - * General notes on MMU parameters. - * - * Terminology: - * ASID = address-space ID (acts as an "extension" of virtual addresses) - * VPN = virtual page number - * PPN = physical page number - * CA = encoded cache attribute (access modes) - * TLB = translation look-aside buffer (term is stretched somewhat here) - * I = instruction (fetch accesses) - * D = data (load and store accesses) - * way = each TLB (ITLB and DTLB) consists of a number of "ways" - * that simultaneously match the virtual address of an access; - * a TLB successfully translates a virtual address if exactly - * one way matches the vaddr; if none match, it is a miss; - * if multiple match, one gets a "multihit" exception; - * each way can be independently configured in terms of number of - * entries, page sizes, which fields are writable or constant, etc. - * set = group of contiguous ways with exactly identical parameters - * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE - * from the page table and storing it in one of the auto-refill ways; - * if this PTE load also misses, a miss exception is posted for s/w. - * min-wired = a "min-wired" way can be used to map a single (minimum-sized) - * page arbitrarily under program control; it has a single entry, - * is non-auto-refill (some other way(s) must be auto-refill), - * all its fields (VPN, PPN, ASID, CA) are all writable, and it - * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current - * restriction is that this be the only page size it supports). - * - * TLB way entries are virtually indexed. - * TLB ways that support multiple page sizes: - * - must have all writable VPN and PPN fields; - * - can only use one page size at any given time (eg. setup at startup), - * selected by the respective ITLBCFG or DTLBCFG special register, - * whose bits n*4+3 .. n*4 index the list of page sizes for way n - * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n); - * this list may be sparse for auto-refill ways because auto-refill - * ways have independent lists of supported page sizes sharing a - * common encoding with PTE entries; the encoding is the index into - * this list; unsupported sizes for a given way are zero in the list; - * selecting unsupported sizes results in undefine hardware behaviour; - * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition). - */ - -#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */ -#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */ -#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */ -#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */ -#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */ -#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */ - - -/*** Instruction TLB: ***/ - -#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */ -#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ -#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */ -#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */ - -/* Way set to which each way belongs: */ -#define XCHAL_ITLB_WAY0_SET 0 - -/* Ways sets that are used by hardware auto-refill (ARF): */ -#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */ - -/* Way sets that are "min-wired" (see terminology comment above): */ -#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ - - -/* ITLB way set 0 (group of ways 0 thru 0): */ -#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */ -#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ -#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ -#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ -#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ -#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ -#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ -#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ -#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ -#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; - 2^PAGESZ_BITS entries in list, unsupported entries are zero */ -#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ -#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ -#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */ -#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ -#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ -#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ -#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ -#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ -/* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */ -#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000 -#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000 -#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000 -#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000 -#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000 -#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000 -#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000 -#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000 -/* Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero): */ -#define XCHAL_ITLB_SET0_E0_PPN_CONST 0x00000000 -#define XCHAL_ITLB_SET0_E1_PPN_CONST 0x20000000 -#define XCHAL_ITLB_SET0_E2_PPN_CONST 0x40000000 -#define XCHAL_ITLB_SET0_E3_PPN_CONST 0x60000000 -#define XCHAL_ITLB_SET0_E4_PPN_CONST 0x80000000 -#define XCHAL_ITLB_SET0_E5_PPN_CONST 0xA0000000 -#define XCHAL_ITLB_SET0_E6_PPN_CONST 0xC0000000 -#define XCHAL_ITLB_SET0_E7_PPN_CONST 0xE0000000 -/* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */ -#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02 - - -/*** Data TLB: ***/ - -#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */ -#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ -#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */ -#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */ - -/* Way set to which each way belongs: */ -#define XCHAL_DTLB_WAY0_SET 0 - -/* Ways sets that are used by hardware auto-refill (ARF): */ -#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */ - -/* Way sets that are "min-wired" (see terminology comment above): */ -#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ - - -/* DTLB way set 0 (group of ways 0 thru 0): */ -#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */ -#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ -#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ -#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ -#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ -#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ -#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ -#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ -#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ -#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; - 2^PAGESZ_BITS entries in list, unsupported entries are zero */ -#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ -#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ -#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */ -#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ -#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ -#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ -#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ -#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ -/* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */ -#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000 -#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000 -#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000 -#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000 -#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000 -#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000 -#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000 -#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000 -/* Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero): */ -#define XCHAL_DTLB_SET0_E0_PPN_CONST 0x00000000 -#define XCHAL_DTLB_SET0_E1_PPN_CONST 0x20000000 -#define XCHAL_DTLB_SET0_E2_PPN_CONST 0x40000000 -#define XCHAL_DTLB_SET0_E3_PPN_CONST 0x60000000 -#define XCHAL_DTLB_SET0_E4_PPN_CONST 0x80000000 -#define XCHAL_DTLB_SET0_E5_PPN_CONST 0xA0000000 -#define XCHAL_DTLB_SET0_E6_PPN_CONST 0xC0000000 -#define XCHAL_DTLB_SET0_E7_PPN_CONST 0xE0000000 -/* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */ -#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02 - - - - -#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/ - -#else - -#error "xcc should not use this header" - -#endif /* __XCC__ */ diff --git a/src/platform/tigerlake/include/arch/xtensa/config/defs.h b/src/platform/tigerlake/include/arch/xtensa/config/defs.h deleted file mode 100644 index d93272ae05a3..000000000000 --- a/src/platform/tigerlake/include/arch/xtensa/config/defs.h +++ /dev/null @@ -1,46 +0,0 @@ -/* Definitions for Xtensa instructions, types, and protos. */ - -/* Copyright (c) 2003-2004 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -/* NOTE: This file exists only for backward compatibility with T1050 - and earlier Xtensa releases. It includes only a subset of the - available header files. */ - -#if !defined __XCC__ - -#ifndef _XTENSA_BASE_HEADER -#define _XTENSA_BASE_HEADER - -#ifdef __XTENSA__ - -#include -#include -#include - -#endif /* __XTENSA__ */ -#endif /* !_XTENSA_BASE_HEADER */ - -#else - -#error "xcc should not use this header" - -#endif /* __XCC__ */ diff --git a/src/platform/tigerlake/include/arch/xtensa/config/specreg.h b/src/platform/tigerlake/include/arch/xtensa/config/specreg.h deleted file mode 100644 index 9d1d2ea95dad..000000000000 --- a/src/platform/tigerlake/include/arch/xtensa/config/specreg.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Xtensa Special Register symbolic names - */ - -/* $Id: //depot/rel/Foxhill/dot.8/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ - -/* Copyright (c) 1998-2002 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#if !defined __XCC__ - -#ifndef XTENSA_SPECREG_H -#define XTENSA_SPECREG_H - -/* Include these special register bitfield definitions, for historical reasons: */ -#include - - -/* Special registers: */ -#define LBEG 0 -#define LEND 1 -#define LCOUNT 2 -#define SAR 3 -#define BR 4 -#define SCOMPARE1 12 -#define PREFCTL 40 -#define WINDOWBASE 72 -#define WINDOWSTART 73 -#define IBREAKENABLE 96 -#define MEMCTL 97 -#define ATOMCTL 99 -#define DDR 104 -#define MEPC 106 -#define MEPS 107 -#define MESAVE 108 -#define MESR 109 -#define MECR 110 -#define MEVADDR 111 -#define IBREAKA_0 128 -#define IBREAKA_1 129 -#define DBREAKA_0 144 -#define DBREAKA_1 145 -#define DBREAKC_0 160 -#define DBREAKC_1 161 -#define EPC_1 177 -#define EPC_2 178 -#define EPC_3 179 -#define EPC_4 180 -#define EPC_5 181 -#define EPC_6 182 -#define EPC_7 183 -#define DEPC 192 -#define EPS_2 194 -#define EPS_3 195 -#define EPS_4 196 -#define EPS_5 197 -#define EPS_6 198 -#define EPS_7 199 -#define EXCSAVE_1 209 -#define EXCSAVE_2 210 -#define EXCSAVE_3 211 -#define EXCSAVE_4 212 -#define EXCSAVE_5 213 -#define EXCSAVE_6 214 -#define EXCSAVE_7 215 -#define CPENABLE 224 -#define INTERRUPT 226 -#define INTENABLE 228 -#define PS 230 -#define VECBASE 231 -#define EXCCAUSE 232 -#define DEBUGCAUSE 233 -#define CCOUNT 234 -#define PRID 235 -#define ICOUNT 236 -#define ICOUNTLEVEL 237 -#define EXCVADDR 238 -#define CCOMPARE_0 240 -#define CCOMPARE_1 241 -#define CCOMPARE_2 242 - -/* Special cases (bases of special register series): */ -#define IBREAKA 128 -#define DBREAKA 144 -#define DBREAKC 160 -#define EPC 176 -#define EPS 192 -#define EXCSAVE 208 -#define CCOMPARE 240 - -/* Special names for read-only and write-only interrupt registers: */ -#define INTREAD 226 -#define INTSET 226 -#define INTCLEAR 227 - -#endif /* XTENSA_SPECREG_H */ - -#else - -#error "xcc should not use this header" - -#endif /* __XCC__ */ diff --git a/src/platform/tigerlake/include/arch/xtensa/config/system.h b/src/platform/tigerlake/include/arch/xtensa/config/system.h deleted file mode 100644 index 0e434954c920..000000000000 --- a/src/platform/tigerlake/include/arch/xtensa/config/system.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration - * - * NOTE: The location and contents of this file are highly subject to change. - * - * Source for configuration-independent binaries (which link in a - * configuration-specific HAL library) must NEVER include this file. - * The HAL itself has historically included this file in some instances, - * but this is not appropriate either, because the HAL is meant to be - * core-specific but system independent. - */ - -/* Copyright (c) 2000-2010 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#if !defined __XCC__ - -#ifndef XTENSA_CONFIG_SYSTEM_H -#define XTENSA_CONFIG_SYSTEM_H - -/*#include */ - - - -/*---------------------------------------------------------------------- - CONFIGURED SOFTWARE OPTIONS - ----------------------------------------------------------------------*/ - -#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */ -#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ - -#define XSHAL_ABI XTHAL_ABI_WINDOWED /* (sw-only option, selected ABI) */ -/* The above maps to one of the following constants: */ -#define XTHAL_ABI_WINDOWED 0 -#define XTHAL_ABI_CALL0 1 -/* Alternatives: */ -/*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */ -/*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */ - -#define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */ -/* The above maps to one of the following constants: */ -#define XTHAL_CLIB_NEWLIB 0 -#define XTHAL_CLIB_UCLIBC 1 -#define XTHAL_CLIB_XCLIB 2 -/* Alternatives: */ -/*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */ -/*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */ -/*#define XSHAL_XCLIB 0*/ /* set if Xtensa C library selected */ - -#define XSHAL_USE_FLOATING_POINT 1 - -#define XSHAL_FLOATING_POINT_ABI 0 - -/* SW workarounds enabled for HW errata: */ - -/* SW options for functional safety: */ -#define XSHAL_FUNC_SAFETY_ENABLED 0 - -/*---------------------------------------------------------------------- - DEVICE ADDRESSES - ----------------------------------------------------------------------*/ - -/* - * Strange place to find these, but the configuration GUI - * allows moving these around to account for various core - * configurations. Specific boards (and their BSP software) - * will have specific meanings for these components. - */ - -/* I/O Block areas: */ -#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000 -#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000 -#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 - -#define XSHAL_IOBLOCK_BYPASS_VADDR 0x50000000 -#define XSHAL_IOBLOCK_BYPASS_PADDR 0x50000000 -#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000 - -/* System ROM: */ -#define XSHAL_ROM_VADDR 0xBEFE0000 -#define XSHAL_ROM_PADDR 0xBEFE0000 -#define XSHAL_ROM_SIZE 0x00020000 -/* Largest available area (free of vectors): */ -#define XSHAL_ROM_AVAIL_VADDR 0xBEFE0BC0 -#define XSHAL_ROM_AVAIL_VSIZE 0x0001F440 - -/* System RAM: */ -#define XSHAL_RAM_VADDR 0x80000000 -#define XSHAL_RAM_PADDR 0x80000000 -#define XSHAL_RAM_VSIZE 0x3EFE0000 -#define XSHAL_RAM_PSIZE 0x3EFE0000 -#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE -/* Largest available area (free of vectors): */ -#define XSHAL_RAM_AVAIL_VADDR 0x80000000 -#define XSHAL_RAM_AVAIL_VSIZE 0x3EFE0000 - -/* - * Shadow system RAM (same device as system RAM, at different address). - * (Emulation boards need this for the SONIC Ethernet driver - * when data caches are configured for writeback mode.) - * NOTE: on full MMU configs, this points to the BYPASS virtual address - * of system RAM, ie. is the same as XSHAL_RAM_* except that virtual - * addresses are viewed through the BYPASS static map rather than - * the CACHED static map. - */ -#define XSHAL_RAM_BYPASS_VADDR 0x20000000 -#define XSHAL_RAM_BYPASS_PADDR 0x20000000 -#define XSHAL_RAM_BYPASS_PSIZE 0x20000000 - -/* Alternate system RAM (different device than system RAM): */ -/*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/ -/*#define XSHAL_ALTRAM_SIZE ...not configured...*/ - -/* Some available location in which to place devices in a simulation (eg. XTMP): */ -#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000 -#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000 -#define XSHAL_SIMIO_PADDR 0xC0000000 -#define XSHAL_SIMIO_SIZE 0x20000000 - - -/*---------------------------------------------------------------------- - * For use by reference testbench exit and diagnostic routines. - */ -#define XSHAL_MAGIC_EXIT 0xe0000000 - -/*---------------------------------------------------------------------- - * DEVICE-ADDRESS DEPENDENT... - * - * Values written to CACHEATTR special register (or its equivalent) - * to enable and disable caches in various modes. - *----------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------- - BACKWARD COMPATIBILITY ... - ----------------------------------------------------------------------*/ - -/* - * NOTE: the following two macros are DEPRECATED. Use the latter - * board-specific macros instead, which are specially tuned for the - * particular target environments' memory maps. - */ -#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */ -#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */ - -/*---------------------------------------------------------------------- - GENERIC - ----------------------------------------------------------------------*/ - -/* For the following, a 512MB region is used if it contains a system (PIF) RAM, - * system (PIF) ROM, local memory, or XLMI. */ - -/* These set any unused 512MB region to cache-BYPASS attribute: */ -#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22442222 /* enable caches in write-back mode */ -#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22112222 /* enable caches in write-allocate mode */ -#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22112222 /* enable caches in write-through mode */ -#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */ -#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */ - -/* These set any unused 512MB region to ILLEGAL attribute: */ -#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFF44FFFF /* enable caches in write-back mode */ -#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFF11FFFF /* enable caches in write-allocate mode */ -#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFF11FFFF /* enable caches in write-through mode */ -#define XSHAL_STRICT_CACHEATTR_BYPASS 0xFF22FFFF /* disable caches in bypass mode */ -#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */ - -/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch - * NULL-pointer dereference bugs; all other unused 512MB regions are set - * to cache-BYPASS attribute: */ -#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2244222F /* enable caches in write-back mode */ -#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2211222F /* enable caches in write-allocate mode */ -#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2211222F /* enable caches in write-through mode */ -#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */ -#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */ - -/*---------------------------------------------------------------------- - ISS (Instruction Set Simulator) SPECIFIC ... - ----------------------------------------------------------------------*/ - -/* For now, ISS defaults to the TRAPNULL settings: */ -#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK -#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC -#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU -#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS -#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK - -#define XSHAL_ISS_PIPE_REGIONS 0 -#define XSHAL_ISS_SDRAM_REGIONS 0 - - -/*---------------------------------------------------------------------- - XT2000 BOARD SPECIFIC ... - ----------------------------------------------------------------------*/ - -/* For the following, a 512MB region is used if it contains any system RAM, - * system ROM, local memory, XLMI, or other XT2000 board device or memory. - * Regions containing devices are forced to cache-BYPASS mode regardless - * of whether the macro is _WRITEBACK vs. _BYPASS etc. */ - -/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */ -#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF44422F /* enable caches in write-back mode */ -#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF11122F /* enable caches in write-allocate mode */ -#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF11122F /* enable caches in write-through mode */ -#define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ -#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */ - -#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */ -#define XSHAL_XT2000_SDRAM_REGIONS 0x00000104 /* BusInt SDRAM regions */ - - -/*---------------------------------------------------------------------- - VECTOR INFO AND SIZES - ----------------------------------------------------------------------*/ - -#define XSHAL_VECTORS_PACKED 0 -#define XSHAL_STATIC_VECTOR_SELECT 0 -#define XSHAL_RESET_VECTOR_VADDR 0xBEFE0000 -#define XSHAL_RESET_VECTOR_PADDR 0xBEFE0000 -#define XSHAL_MEMERROR_VECTOR_VADDR 0xBEFE0400 -#define XSHAL_MEMERROR_VECTOR_PADDR 0xBEFE0400 - -/* - * Sizes allocated to vectors by the system (memory map) configuration. - * These sizes are constrained by core configuration (eg. one vector's - * code cannot overflow into another vector) but are dependent on the - * system or board (or LSP) memory map configuration. - * - * Whether or not each vector happens to be in a system ROM is also - * a system configuration matter, sometimes useful, included here also: - */ -#define XSHAL_RESET_VECTOR_SIZE 0x00000300 -#define XSHAL_RESET_VECTOR_ISROM 1 -#define XSHAL_USER_VECTOR_SIZE 0x00000038 -#define XSHAL_USER_VECTOR_ISROM 1 -#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ -#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ -#define XSHAL_KERNEL_VECTOR_SIZE 0x00000038 -#define XSHAL_KERNEL_VECTOR_ISROM 1 -#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ -#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ -#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040 -#define XSHAL_DOUBLEEXC_VECTOR_ISROM 1 -#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178 -#define XSHAL_WINDOW_VECTORS_ISROM 1 -#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038 -#define XSHAL_INTLEVEL2_VECTOR_ISROM 1 -#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038 -#define XSHAL_INTLEVEL3_VECTOR_ISROM 1 -#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038 -#define XSHAL_INTLEVEL4_VECTOR_ISROM 1 -#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038 -#define XSHAL_INTLEVEL5_VECTOR_ISROM 1 -#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038 -#define XSHAL_INTLEVEL6_VECTOR_ISROM 1 -#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE -#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM -#define XSHAL_NMI_VECTOR_SIZE 0x00000038 -#define XSHAL_NMI_VECTOR_ISROM 1 -#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE - - -#endif /*XTENSA_CONFIG_SYSTEM_H*/ - -#else - -#error "xcc should not use this header" - -#endif /* __XCC__ */ diff --git a/src/platform/tigerlake/include/arch/xtensa/config/tie-asm.h b/src/platform/tigerlake/include/arch/xtensa/config/tie-asm.h deleted file mode 100644 index f6210e126331..000000000000 --- a/src/platform/tigerlake/include/arch/xtensa/config/tie-asm.h +++ /dev/null @@ -1,376 +0,0 @@ -/* - * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE - * - * NOTE: This header file is not meant to be included directly. - */ - -/* This header file contains assembly-language definitions (assembly - macros, etc.) for this specific Xtensa processor's TIE extensions - and options. It is customized to this Xtensa processor configuration. - - Copyright (c) 1999-2018 Cadence Design Systems Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#if !defined __XCC__ - -#ifndef _XTENSA_CORE_TIE_ASM_H -#define _XTENSA_CORE_TIE_ASM_H - -/* Selection parameter values for save-area save/restore macros: */ -/* Option vs. TIE: */ -#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ -#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ -#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ -/* Whether used automatically by compiler: */ -#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ -#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ -#define XTHAL_SAS_ANYCC 0x000C /* both of the above */ -/* ABI handling across function calls: */ -#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ -#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ -#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ -#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ -/* Misc */ -#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ -#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ - | ((ccuse) & XTHAL_SAS_ANYCC) \ - | ((abi) & XTHAL_SAS_ANYABI) ) - - - /* - * Macro to store all non-coprocessor (extra) custom TIE and optional state - * (not including zero-overhead loop registers). - * Required parameters: - * ptr Save area pointer address register (clobbered) - * (register must contain a 4 byte aligned address). - * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS - * registers are clobbered, the remaining are unused). - * Optional parameters: - * continue If macro invoked as part of a larger store sequence, set to 1 - * if this is not the first in the sequence. Defaults to 0. - * ofs Offset from start of larger sequence (from value of first ptr - * in sequence) at which to store. Defaults to next available space - * (or 0 if is 0). - * select Select what category(ies) of registers to store, as a bitmask - * (see XTHAL_SAS_xxx constants). Defaults to all registers. - * alloc Select what category(ies) of registers to allocate; if any - * category is selected here that is not in , space for - * the corresponding registers is skipped without doing any load. - */ - .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 - xchal_sa_start \continue, \ofs - // Optional global registers used by default by the compiler: - .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) - xchal_sa_align \ptr, 0, 1016, 4, 4 - l32i \at1, \ptr, .Lxchal_ofs_+0 - wur.THREADPTR \at1 // threadptr option - .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 - .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 - xchal_sa_align \ptr, 0, 1016, 4, 4 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 - .endif - // Optional caller-saved registers not used by default by the compiler: - .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) - xchal_sa_align \ptr, 0, 1012, 4, 4 - l32i \at1, \ptr, .Lxchal_ofs_+0 - wsr.BR \at1 // boolean option - l32i \at1, \ptr, .Lxchal_ofs_+4 - wsr.SCOMPARE1 \at1 // conditional store option - .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 - .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 - xchal_sa_align \ptr, 0, 1012, 4, 4 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 - .endif - .endm // xchal_ncp_load - - -#define XCHAL_NCP_NUM_ATMPS 1 - - /* - * Macro to store the state of TIE coprocessor FPU. - * Required parameters: - * ptr Save area pointer address register (clobbered) - * (register must contain a 4 byte aligned address). - * at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS - * registers are clobbered, the remaining are unused). - * Optional parameters are the same as for xchal_ncp_store. - */ -#define xchal_cp_FPU_store xchal_cp0_store - .macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 - xchal_sa_start \continue, \ofs - // Custom caller-saved registers not used by default by the compiler: - .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) - xchal_sa_align \ptr, 0, 948, 4, 4 - rur.FCR \at1 // ureg 232 - s32i \at1, \ptr, .Lxchal_ofs_+0 - rur.FSR \at1 // ureg 233 - s32i \at1, \ptr, .Lxchal_ofs_+4 - ssi f0, \ptr, .Lxchal_ofs_+8 - ssi f1, \ptr, .Lxchal_ofs_+12 - ssi f2, \ptr, .Lxchal_ofs_+16 - ssi f3, \ptr, .Lxchal_ofs_+20 - ssi f4, \ptr, .Lxchal_ofs_+24 - ssi f5, \ptr, .Lxchal_ofs_+28 - ssi f6, \ptr, .Lxchal_ofs_+32 - ssi f7, \ptr, .Lxchal_ofs_+36 - ssi f8, \ptr, .Lxchal_ofs_+40 - ssi f9, \ptr, .Lxchal_ofs_+44 - ssi f10, \ptr, .Lxchal_ofs_+48 - ssi f11, \ptr, .Lxchal_ofs_+52 - ssi f12, \ptr, .Lxchal_ofs_+56 - ssi f13, \ptr, .Lxchal_ofs_+60 - ssi f14, \ptr, .Lxchal_ofs_+64 - ssi f15, \ptr, .Lxchal_ofs_+68 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 - .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 - xchal_sa_align \ptr, 0, 948, 4, 4 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 - .endif - .endm // xchal_cp0_store - - /* - * Macro to load the state of TIE coprocessor FPU. - * Required parameters: - * ptr Save area pointer address register (clobbered) - * (register must contain a 4 byte aligned address). - * at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS - * registers are clobbered, the remaining are unused). - * Optional parameters are the same as for xchal_ncp_load. - */ -#define xchal_cp_FPU_load xchal_cp0_load - .macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 - xchal_sa_start \continue, \ofs - // Custom caller-saved registers not used by default by the compiler: - .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) - xchal_sa_align \ptr, 0, 948, 4, 4 - l32i \at1, \ptr, .Lxchal_ofs_+0 - wur.FCR \at1 // ureg 232 - l32i \at1, \ptr, .Lxchal_ofs_+4 - wur.FSR \at1 // ureg 233 - lsi f0, \ptr, .Lxchal_ofs_+8 - lsi f1, \ptr, .Lxchal_ofs_+12 - lsi f2, \ptr, .Lxchal_ofs_+16 - lsi f3, \ptr, .Lxchal_ofs_+20 - lsi f4, \ptr, .Lxchal_ofs_+24 - lsi f5, \ptr, .Lxchal_ofs_+28 - lsi f6, \ptr, .Lxchal_ofs_+32 - lsi f7, \ptr, .Lxchal_ofs_+36 - lsi f8, \ptr, .Lxchal_ofs_+40 - lsi f9, \ptr, .Lxchal_ofs_+44 - lsi f10, \ptr, .Lxchal_ofs_+48 - lsi f11, \ptr, .Lxchal_ofs_+52 - lsi f12, \ptr, .Lxchal_ofs_+56 - lsi f13, \ptr, .Lxchal_ofs_+60 - lsi f14, \ptr, .Lxchal_ofs_+64 - lsi f15, \ptr, .Lxchal_ofs_+68 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 - .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 - xchal_sa_align \ptr, 0, 948, 4, 4 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 - .endif - .endm // xchal_cp0_load - -#define XCHAL_CP0_NUM_ATMPS 1 - /* - * Macro to store the state of TIE coprocessor AudioEngineLX. - * Required parameters: - * ptr Save area pointer address register (clobbered) - * (register must contain a 8 byte aligned address). - * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS - * registers are clobbered, the remaining are unused). - * Optional parameters are the same as for xchal_ncp_store. - */ -#define xchal_cp_AudioEngineLX_store xchal_cp1_store - .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 - xchal_sa_start \continue, \ofs - // Custom caller-saved registers not used by default by the compiler: - .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) - xchal_sa_align \ptr, 0, 0, 8, 8 - rur.AE_OVF_SAR \at1 // ureg 240 - s32i \at1, \ptr, .Lxchal_ofs_+0 - rur.AE_BITHEAD \at1 // ureg 241 - s32i \at1, \ptr, .Lxchal_ofs_+4 - rur.AE_TS_FTS_BU_BP \at1 // ureg 242 - s32i \at1, \ptr, .Lxchal_ofs_+8 - rur.AE_CW_SD_NO \at1 // ureg 243 - s32i \at1, \ptr, .Lxchal_ofs_+12 - rur.AE_CBEGIN0 \at1 // ureg 246 - s32i \at1, \ptr, .Lxchal_ofs_+16 - rur.AE_CEND0 \at1 // ureg 247 - s32i \at1, \ptr, .Lxchal_ofs_+20 - ae_s64.i aed0, \ptr, .Lxchal_ofs_+24 - ae_s64.i aed1, \ptr, .Lxchal_ofs_+32 - ae_s64.i aed2, \ptr, .Lxchal_ofs_+40 - ae_s64.i aed3, \ptr, .Lxchal_ofs_+48 - ae_s64.i aed4, \ptr, .Lxchal_ofs_+56 - addi \ptr, \ptr, 64 - ae_s64.i aed5, \ptr, .Lxchal_ofs_+0 - ae_s64.i aed6, \ptr, .Lxchal_ofs_+8 - ae_s64.i aed7, \ptr, .Lxchal_ofs_+16 - ae_s64.i aed8, \ptr, .Lxchal_ofs_+24 - ae_s64.i aed9, \ptr, .Lxchal_ofs_+32 - ae_s64.i aed10, \ptr, .Lxchal_ofs_+40 - ae_s64.i aed11, \ptr, .Lxchal_ofs_+48 - ae_s64.i aed12, \ptr, .Lxchal_ofs_+56 - addi \ptr, \ptr, 64 - ae_s64.i aed13, \ptr, .Lxchal_ofs_+0 - ae_s64.i aed14, \ptr, .Lxchal_ofs_+8 - ae_s64.i aed15, \ptr, .Lxchal_ofs_+16 - ae_salign64.i u0, \ptr, .Lxchal_ofs_+24 - ae_salign64.i u1, \ptr, .Lxchal_ofs_+32 - ae_salign64.i u2, \ptr, .Lxchal_ofs_+40 - ae_salign64.i u3, \ptr, .Lxchal_ofs_+48 - .set .Lxchal_pofs_, .Lxchal_pofs_ + 128 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 56 - .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 - xchal_sa_align \ptr, 0, 0, 8, 8 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 184 - .endif - .endm // xchal_cp1_store - - /* - * Macro to load the state of TIE coprocessor AudioEngineLX. - * Required parameters: - * ptr Save area pointer address register (clobbered) - * (register must contain a 8 byte aligned address). - * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS - * registers are clobbered, the remaining are unused). - * Optional parameters are the same as for xchal_ncp_load. - */ -#define xchal_cp_AudioEngineLX_load xchal_cp1_load - .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 - xchal_sa_start \continue, \ofs - // Custom caller-saved registers not used by default by the compiler: - .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) - xchal_sa_align \ptr, 0, 0, 8, 8 - l32i \at1, \ptr, .Lxchal_ofs_+0 - wur.AE_OVF_SAR \at1 // ureg 240 - l32i \at1, \ptr, .Lxchal_ofs_+4 - wur.AE_BITHEAD \at1 // ureg 241 - l32i \at1, \ptr, .Lxchal_ofs_+8 - wur.AE_TS_FTS_BU_BP \at1 // ureg 242 - l32i \at1, \ptr, .Lxchal_ofs_+12 - wur.AE_CW_SD_NO \at1 // ureg 243 - l32i \at1, \ptr, .Lxchal_ofs_+16 - wur.AE_CBEGIN0 \at1 // ureg 246 - l32i \at1, \ptr, .Lxchal_ofs_+20 - wur.AE_CEND0 \at1 // ureg 247 - ae_l64.i aed0, \ptr, .Lxchal_ofs_+24 - ae_l64.i aed1, \ptr, .Lxchal_ofs_+32 - ae_l64.i aed2, \ptr, .Lxchal_ofs_+40 - ae_l64.i aed3, \ptr, .Lxchal_ofs_+48 - ae_l64.i aed4, \ptr, .Lxchal_ofs_+56 - addi \ptr, \ptr, 64 - ae_l64.i aed5, \ptr, .Lxchal_ofs_+0 - ae_l64.i aed6, \ptr, .Lxchal_ofs_+8 - ae_l64.i aed7, \ptr, .Lxchal_ofs_+16 - ae_l64.i aed8, \ptr, .Lxchal_ofs_+24 - ae_l64.i aed9, \ptr, .Lxchal_ofs_+32 - ae_l64.i aed10, \ptr, .Lxchal_ofs_+40 - ae_l64.i aed11, \ptr, .Lxchal_ofs_+48 - ae_l64.i aed12, \ptr, .Lxchal_ofs_+56 - addi \ptr, \ptr, 64 - ae_l64.i aed13, \ptr, .Lxchal_ofs_+0 - ae_l64.i aed14, \ptr, .Lxchal_ofs_+8 - ae_l64.i aed15, \ptr, .Lxchal_ofs_+16 - addi \ptr, \ptr, 24 - ae_lalign64.i u0, \ptr, .Lxchal_ofs_+0 - ae_lalign64.i u1, \ptr, .Lxchal_ofs_+8 - ae_lalign64.i u2, \ptr, .Lxchal_ofs_+16 - ae_lalign64.i u3, \ptr, .Lxchal_ofs_+24 - .set .Lxchal_pofs_, .Lxchal_pofs_ + 152 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 32 - .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 - xchal_sa_align \ptr, 0, 0, 8, 8 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 184 - .endif - .endm // xchal_cp1_load - -#define XCHAL_CP1_NUM_ATMPS 1 -#define XCHAL_SA_NUM_ATMPS 1 - - /* Empty macros for unconfigured coprocessors: */ - .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - -#endif /*_XTENSA_CORE_TIE_ASM_H*/ - -#else - -#error "xcc should not use this header" - -#endif /* __XCC__ */ diff --git a/src/platform/tigerlake/include/arch/xtensa/config/tie.h b/src/platform/tigerlake/include/arch/xtensa/config/tie.h deleted file mode 100644 index 6865fad953af..000000000000 --- a/src/platform/tigerlake/include/arch/xtensa/config/tie.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration - * - * NOTE: This header file is not meant to be included directly. - */ - -/* This header file describes this specific Xtensa processor's TIE extensions - that extend basic Xtensa core functionality. It is customized to this - Xtensa processor configuration. - - Copyright (c) 1999-2018 Cadence Design Systems Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#if !defined __XCC__ - -#ifndef _XTENSA_CORE_TIE_H -#define _XTENSA_CORE_TIE_H - -#define XCHAL_CP_NUM 2 /* number of coprocessors */ -#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */ -#define XCHAL_CP_MASK 0x03 /* bitmask of all CPs by ID */ -#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ - -/* Basic parameters of each coprocessor: */ -#define XCHAL_CP0_NAME "FPU" -#define XCHAL_CP0_IDENT FPU -#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */ -#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */ -#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */ -#define XCHAL_CP1_NAME "AudioEngineLX" -#define XCHAL_CP1_IDENT AudioEngineLX -#define XCHAL_CP1_SA_SIZE 184 /* size of state save area */ -#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */ -#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */ - -/* Filler info for unassigned coprocessors, to simplify arrays etc: */ -#define XCHAL_CP2_SA_SIZE 0 -#define XCHAL_CP2_SA_ALIGN 1 -#define XCHAL_CP3_SA_SIZE 0 -#define XCHAL_CP3_SA_ALIGN 1 -#define XCHAL_CP4_SA_SIZE 0 -#define XCHAL_CP4_SA_ALIGN 1 -#define XCHAL_CP5_SA_SIZE 0 -#define XCHAL_CP5_SA_ALIGN 1 -#define XCHAL_CP6_SA_SIZE 0 -#define XCHAL_CP6_SA_ALIGN 1 -#define XCHAL_CP7_SA_SIZE 0 -#define XCHAL_CP7_SA_ALIGN 1 - -/* Save area for non-coprocessor optional and custom (TIE) state: */ -#define XCHAL_NCP_SA_SIZE 12 -#define XCHAL_NCP_SA_ALIGN 4 - -/* Total save area for optional and custom state (NCP + CPn): */ -#define XCHAL_TOTAL_SA_SIZE 272 /* with 16-byte align padding */ -#define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */ - -/* - * Detailed contents of save areas. - * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) - * before expanding the XCHAL_xxx_SA_LIST() macros. - * - * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, - * dbnum,base,regnum,bitsz,gapsz,reset,x...) - * - * s = passed from XCHAL_*_LIST(s), eg. to select how to expand - * ccused = set if used by compiler without special options or code - * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) - * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) - * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) - * name = lowercase reg name (no quotes) - * galign = group byte alignment (power of 2) (galign >= align) - * align = register byte alignment (power of 2) - * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) - * (not including any pad bytes required to galign this or next reg) - * dbnum = unique target number f/debug (see ) - * base = reg shortname w/o index (or sr=special, ur=TIE user reg) - * regnum = reg index in regfile, or special/TIE-user reg number - * bitsz = number of significant bits (regfile width, or ur/sr mask bits) - * gapsz = intervening bits, if bitsz bits not stored contiguously - * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) - * reset = register reset value (or 0 if undefined at reset) - * x = reserved for future use (0 until then) - * - * To filter out certain registers, e.g. to expand only the non-global - * registers used by the compiler, you can do something like this: - * - * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) - * #define SELCC0(p...) - * #define SELCC1(abikind,p...) SELAK##abikind(p) - * #define SELAK0(p...) REG(p) - * #define SELAK1(p...) REG(p) - * #define SELAK2(p...) - * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ - * ...what you want to expand... - */ - -#define XCHAL_NCP_SA_NUM 3 -#define XCHAL_NCP_SA_LIST(s) \ - XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \ - XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) - -#define XCHAL_CP0_SA_NUM 18 -#define XCHAL_CP0_SA_LIST(s) \ - XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0) - -#define XCHAL_CP1_SA_NUM 26 -#define XCHAL_CP1_SA_LIST(s) \ - XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 8,0,0,0) \ - XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \ - XCHAL_SA_REG(s,0,0,1,0, ae_cw_sd_no, 4, 4, 4,0x03F3, ur,243, 29,0,0,0) \ - XCHAL_SA_REG(s,0,0,1,0, ae_cbegin0, 4, 4, 4,0x03F6, ur,246, 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,1,0, ae_cend0, 4, 4, 4,0x03F7, ur,247, 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed0, 8, 8, 8,0x1000, aed,0 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed1, 8, 8, 8,0x1001, aed,1 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed2, 8, 8, 8,0x1002, aed,2 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed3, 8, 8, 8,0x1003, aed,3 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed4, 8, 8, 8,0x1004, aed,4 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed5, 8, 8, 8,0x1005, aed,5 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed6, 8, 8, 8,0x1006, aed,6 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed7, 8, 8, 8,0x1007, aed,7 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed8, 8, 8, 8,0x1008, aed,8 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed9, 8, 8, 8,0x1009, aed,9 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed10, 8, 8, 8,0x100A, aed,10 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed11, 8, 8, 8,0x100B, aed,11 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed12, 8, 8, 8,0x100C, aed,12 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed13, 8, 8, 8,0x100D, aed,13 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed14, 8, 8, 8,0x100E, aed,14 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed15, 8, 8, 8,0x100F, aed,15 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, u0, 8, 8, 8,0x1010, u,0 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, u1, 8, 8, 8,0x1011, u,1 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, u2, 8, 8, 8,0x1012, u,2 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, u3, 8, 8, 8,0x1013, u,3 , 64,0,0,0) - -#define XCHAL_CP2_SA_NUM 0 -#define XCHAL_CP2_SA_LIST(s) /* empty */ - -#define XCHAL_CP3_SA_NUM 0 -#define XCHAL_CP3_SA_LIST(s) /* empty */ - -#define XCHAL_CP4_SA_NUM 0 -#define XCHAL_CP4_SA_LIST(s) /* empty */ - -#define XCHAL_CP5_SA_NUM 0 -#define XCHAL_CP5_SA_LIST(s) /* empty */ - -#define XCHAL_CP6_SA_NUM 0 -#define XCHAL_CP6_SA_LIST(s) /* empty */ - -#define XCHAL_CP7_SA_NUM 0 -#define XCHAL_CP7_SA_LIST(s) /* empty */ - -/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ -#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8 -/* Byte length of instruction from its first byte, per FLIX. */ -#define XCHAL_BYTE0_FORMAT_LENGTHS \ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8 - -#endif /*_XTENSA_CORE_TIE_H*/ - -#else - -#error "xcc should not use this header" - -#endif /* __XCC__ */ diff --git a/src/platform/tigerlake/lib/CMakeLists.txt b/src/platform/tigerlake/lib/CMakeLists.txt deleted file mode 100644 index 47a1b5962abf..000000000000 --- a/src/platform/tigerlake/lib/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: BSD-3-Clause - -add_local_sources(sof clk.c) diff --git a/src/platform/tigerlake/rom.x.in b/src/platform/tigerlake/rom.x.in deleted file mode 100644 index 253a70dc436b..000000000000 --- a/src/platform/tigerlake/rom.x.in +++ /dev/null @@ -1,347 +0,0 @@ -/* - * Linker Script for Tigerlake Bootloader. - * - * This script is run through the GNU C preprocessor to align the memory - * offsets with headers. - * - * Use spaces for formatting as cpp ignore tab sizes. - */ - - -#include -#include - -OUTPUT_ARCH(xtensa) - -MEMORY -{ - vector_reset_text : - org = ROM_BASE, - len = ROM_RESET_TEXT_SIZE - vector_reset_lit : - org = ROM_BASE + ROM_RESET_TEXT_SIZE, - len = ROM_RESET_LIT_SIZE - vector_base_text : - org = ROM_BASE + ROM_RESET_TEXT_SIZE + ROM_RESET_LIT_SIZE, - len = SOF_MEM_VECBASE_LIT_SIZE - vector_int2_lit : - org = ROM_BASE + XCHAL_INTLEVEL2_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int2_text : - org = ROM_BASE + XCHAL_INTLEVEL2_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int3_lit : - org = ROM_BASE + XCHAL_INTLEVEL3_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int3_text : - org = ROM_BASE + XCHAL_INTLEVEL3_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int4_lit : - org = ROM_BASE + XCHAL_INTLEVEL4_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int4_text : - org = ROM_BASE + XCHAL_INTLEVEL4_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int5_lit : - org = ROM_BASE + XCHAL_INTLEVEL5_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int5_text : - org = ROM_BASE + XCHAL_INTLEVEL5_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int6_lit : - org = ROM_BASE + XCHAL_INTLEVEL6_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int6_text : - org = ROM_BASE + XCHAL_INTLEVEL6_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int7_lit : - org = ROM_BASE + XCHAL_INTLEVEL7_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int7_text : - org = ROM_BASE + XCHAL_INTLEVEL7_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_kernel_lit : - org = ROM_BASE + XCHAL_KERNEL_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_kernel_text : - org = ROM_BASE + XCHAL_KERNEL_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_user_lit : - org = ROM_BASE + XCHAL_USER_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_user_text : - org = ROM_BASE + XCHAL_USER_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_double_lit : - org = ROM_BASE + XCHAL_DOUBLEEXC_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_double_text : - org = ROM_BASE + XCHAL_DOUBLEEXC_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - sof_text : - org = ROM_BASE + 0x800, - len = ROM_SIZE, - sof_stack : - org = BOOT_LDR_STACK_BASE, - len = BOOT_LDR_STACK_SIZE -} - -PHDRS -{ - vector_reset_text_phdr PT_LOAD; - vector_reset_lit_phdr PT_LOAD; - vector_base_text_phdr PT_LOAD; - vector_int2_lit_phdr PT_LOAD; - vector_int2_text_phdr PT_LOAD; - vector_int3_lit_phdr PT_LOAD; - vector_int3_text_phdr PT_LOAD; - vector_int4_lit_phdr PT_LOAD; - vector_int4_text_phdr PT_LOAD; - vector_int5_lit_phdr PT_LOAD; - vector_int5_text_phdr PT_LOAD; - vector_int6_lit_phdr PT_LOAD; - vector_int6_text_phdr PT_LOAD; - vector_int7_lit_phdr PT_LOAD; - vector_int7_text_phdr PT_LOAD; - vector_kernel_lit_phdr PT_LOAD; - vector_kernel_text_phdr PT_LOAD; - vector_user_lit_phdr PT_LOAD; - vector_user_text_phdr PT_LOAD; - vector_double_lit_phdr PT_LOAD; - vector_double_text_phdr PT_LOAD; - sof_text_phdr PT_LOAD; - sof_stack_phdr PT_LOAD; -} - -_rom_store_table = 0; - -/* ABI0 does not use Window base */ -PROVIDE(_memmap_vecbase_reset = ROM_BASE); - -/* Various memory-map dependent cache attribute settings: */ -_memmap_cacheattr_wbna_trapnull = 0xFF42FFF2; -PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull); - -SECTIONS -{ - .ResetVector.text : ALIGN(4) - { - _ResetVector_text_start = ABSOLUTE(.); - KEEP (*(.ResetVector.text)) - _ResetVector_text_end = ABSOLUTE(.); - } >vector_reset_text :vector_reset_text_phdr - - .ResetVector.literal : ALIGN(4) - { - _ResetVector_literal_start = ABSOLUTE(.); - *(.ResetVector.literal) - _ResetVector_literal_end = ABSOLUTE(.); - } >vector_reset_lit :vector_reset_lit_phdr - - .WindowVectors.text : ALIGN(4) - { - _WindowVectors_text_start = ABSOLUTE(.); - KEEP (*(.WindowVectors.text)) - _WindowVectors_text_end = ABSOLUTE(.); - } >vector_base_text :vector_base_text_phdr - - .Level2InterruptVector.literal : ALIGN(4) - { - _Level2InterruptVector_literal_start = ABSOLUTE(.); - *(.Level2InterruptVector.literal) - _Level2InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int2_lit :vector_int2_lit_phdr - - .Level2InterruptVector.text : ALIGN(4) - { - _Level2InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level2InterruptVector.text)) - _Level2InterruptVector_text_end = ABSOLUTE(.); - } >vector_int2_text :vector_int2_text_phdr - - .Level3InterruptVector.literal : ALIGN(4) - { - _Level3InterruptVector_literal_start = ABSOLUTE(.); - *(.Level3InterruptVector.literal) - _Level3InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int3_lit :vector_int3_lit_phdr - - .Level3InterruptVector.text : ALIGN(4) - { - _Level3InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level3InterruptVector.text)) - _Level3InterruptVector_text_end = ABSOLUTE(.); - } >vector_int3_text :vector_int3_text_phdr - - .Level4InterruptVector.literal : ALIGN(4) - { - _Level4InterruptVector_literal_start = ABSOLUTE(.); - *(.Level4InterruptVector.literal) - _Level4InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int4_lit :vector_int4_lit_phdr - - .Level4InterruptVector.text : ALIGN(4) - { - _Level4InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level4InterruptVector.text)) - _Level4InterruptVector_text_end = ABSOLUTE(.); - } >vector_int4_text :vector_int4_text_phdr - - .Level5InterruptVector.literal : ALIGN(4) - { - _Level5InterruptVector_literal_start = ABSOLUTE(.); - *(.Level5InterruptVector.literal) - _Level5InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int5_lit :vector_int5_lit_phdr - - .Level5InterruptVector.text : ALIGN(4) - { - _Level5InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level5InterruptVector.text)) - _Level5InterruptVector_text_end = ABSOLUTE(.); - } >vector_int5_text :vector_int5_text_phdr - - .DebugExceptionVector.literal : ALIGN(4) - { - _DebugExceptionVector_literal_start = ABSOLUTE(.); - *(.DebugExceptionVector.literal) - _DebugExceptionVector_literal_end = ABSOLUTE(.); - } >vector_int6_lit :vector_int6_lit_phdr - - .DebugExceptionVector.text : ALIGN(4) - { - _DebugExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DebugExceptionVector.text)) - _DebugExceptionVector_text_end = ABSOLUTE(.); - } >vector_int6_text :vector_int6_text_phdr - - .NMIExceptionVector.literal : ALIGN(4) - { - _NMIExceptionVector_literal_start = ABSOLUTE(.); - *(.NMIExceptionVector.literal) - _NMIExceptionVector_literal_end = ABSOLUTE(.); - } >vector_int7_lit :vector_int7_lit_phdr - - .NMIExceptionVector.text : ALIGN(4) - { - _NMIExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.NMIExceptionVector.text)) - _NMIExceptionVector_text_end = ABSOLUTE(.); - } >vector_int7_text :vector_int7_text_phdr - - .KernelExceptionVector.literal : ALIGN(4) - { - _KernelExceptionVector_literal_start = ABSOLUTE(.); - *(.KernelExceptionVector.literal) - _KernelExceptionVector_literal_end = ABSOLUTE(.); - } >vector_kernel_lit :vector_kernel_lit_phdr - - .KernelExceptionVector.text : ALIGN(4) - { - _KernelExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.KernelExceptionVector.text)) - _KernelExceptionVector_text_end = ABSOLUTE(.); - } >vector_kernel_text :vector_kernel_text_phdr - - .UserExceptionVector.literal : ALIGN(4) - { - _UserExceptionVector_literal_start = ABSOLUTE(.); - *(.UserExceptionVector.literal) - _UserExceptionVector_literal_end = ABSOLUTE(.); - } >vector_user_lit :vector_user_lit_phdr - - .UserExceptionVector.text : ALIGN(4) - { - _UserExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.UserExceptionVector.text)) - _UserExceptionVector_text_end = ABSOLUTE(.); - } >vector_user_text :vector_user_text_phdr - - .DoubleExceptionVector.literal : ALIGN(4) - { - _DoubleExceptionVector_literal_start = ABSOLUTE(.); - *(.DoubleExceptionVector.literal) - _DoubleExceptionVector_literal_end = ABSOLUTE(.); - } >vector_double_lit :vector_double_lit_phdr - - .DoubleExceptionVector.text : ALIGN(4) - { - _DoubleExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DoubleExceptionVector.text)) - _DoubleExceptionVector_text_end = ABSOLUTE(.); - } >vector_double_text :vector_double_text_phdr - - .text : ALIGN(4) - { - _stext = .; - _text_start = ABSOLUTE(.); - KEEP (*(.MainEntry.text)) - *(.entry.text) - *(.init.literal) - KEEP(*(.init)) - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.fini.literal) - KEEP(*(.fini)) - *(.gnu.version) - _text_end = ABSOLUTE(.); - _etext = .; - } >sof_text :sof_text_phdr - - /* stack */ - _end = BOOT_LDR_STACK_BASE; - PROVIDE(end = BOOT_LDR_STACK_BASE); - _stack_sentry = BOOT_LDR_STACK_BASE; - __stack = BOOT_LDR_STACK_BASE + BOOT_LDR_STACK_SIZE; - - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .xt.profile_range 0 : - { - KEEP (*(.xt.profile_range)) - KEEP (*(.gnu.linkonce.profile_range.*)) - } - .xt.profile_ranges 0 : - { - KEEP (*(.xt.profile_ranges)) - KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) - } - .xt.profile_files 0 : - { - KEEP (*(.xt.profile_files)) - KEEP (*(.gnu.linkonce.xt.profile_files.*)) - } -} - diff --git a/src/platform/tigerlake/tigerlake.x.in b/src/platform/tigerlake/tigerlake.x.in deleted file mode 100644 index 5ff177bcf1e8..000000000000 --- a/src/platform/tigerlake/tigerlake.x.in +++ /dev/null @@ -1,687 +0,0 @@ -/* - * Linker Script for Tigerlake. - * - * This script is run through the GNU C preprocessor to align the memory - * offsets with headers. - * - * Use spaces for formatting as cpp ignore tab sizes. - */ - - -#include -#include - -OUTPUT_ARCH(xtensa) - -MEMORY -{ - vector_memory_lit : - org = XCHAL_MEMERROR_VECTOR_PADDR + SOF_MEM_ERROR_LIT_SIZE, - len = SOF_MEM_ERROR_LIT_SIZE - vector_memory_text : - org = XCHAL_MEMERROR_VECTOR_PADDR, - len = SOF_MEM_ERROR_TEXT_SIZE - vector_base_text : - org = SOF_MEM_VECBASE, - len = SOF_MEM_VECBASE_LIT_SIZE - vector_int2_lit : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL2_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int2_text : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL2_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int3_lit : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL3_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int3_text : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL3_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int4_lit : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL4_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int4_text : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL4_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int5_lit : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL5_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int5_text : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL5_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int6_lit : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL6_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int6_text : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL6_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int7_lit : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL7_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int7_text : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL7_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_kernel_lit : - org = SOF_MEM_VECBASE + XCHAL_KERNEL_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_kernel_text : - org = SOF_MEM_VECBASE + XCHAL_KERNEL_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_user_lit : - org = SOF_MEM_VECBASE + XCHAL_USER_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_user_text : - org = SOF_MEM_VECBASE + XCHAL_USER_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_double_lit : - org = SOF_MEM_VECBASE + XCHAL_DOUBLEEXC_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_double_text : - org = SOF_MEM_VECBASE + XCHAL_DOUBLEEXC_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - sof_fw : - org = SOF_FW_BASE, - len = SOF_FW_MAX_SIZE - buffer_hp_heap : - org = HEAP_HP_BUFFER_BASE, - len = HEAP_HP_BUFFER_SIZE - wnd0 : - org = HP_SRAM_WIN0_BASE, - len = HP_SRAM_WIN0_SIZE - wnd1 : - org = HP_SRAM_WIN1_BASE, - len = HP_SRAM_WIN1_SIZE - wnd2 : - org = HP_SRAM_WIN2_BASE, - len = HP_SRAM_WIN2_SIZE - wnd3 : - org = HP_SRAM_WIN3_BASE, - len = HP_SRAM_WIN3_SIZE - static_uuid_entries_seg (!ari) : - org = UUID_ENTRY_ELF_BASE, - len = UUID_ENTRY_ELF_SIZE - static_log_entries_seg (!ari) : - org = LOG_ENTRY_ELF_BASE, - len = LOG_ENTRY_ELF_SIZE - fw_metadata_seg (!ari) : - org = EXT_MANIFEST_ELF_BASE, - len = EXT_MANIFEST_ELF_SIZE -#if CONFIG_MULTICORE - lpsram_alt_reset_vec_seg : - org = LP_SRAM_ALT_RESET_VEC_BASE, - len = LP_SRAM_ALT_RESET_VEC_SIZE - lpsram_alt_reset_int_vec_seg : - org = LP_SRAM_ALT_RESET_INT_VEC_BASE, - len = LP_SRAM_ALT_RESET_INT_VEC_SIZE - lpsram_code_seg : - org = LP_SRAM_CODE_BASE, - len = LP_SRAM_CODE_SIZE -#endif - lpsram_mem : - org = LP_SRAM_START, - len = LP_SRAM_SIZE - (LP_SRAM_START - LP_SRAM_BASE) -} - -PHDRS -{ - vector_memory_lit_phdr PT_LOAD; - vector_memory_text_phdr PT_LOAD; - vector_base_text_phdr PT_LOAD; - vector_int2_lit_phdr PT_LOAD; - vector_int2_text_phdr PT_LOAD; - vector_int3_lit_phdr PT_LOAD; - vector_int3_text_phdr PT_LOAD; - vector_int4_lit_phdr PT_LOAD; - vector_int4_text_phdr PT_LOAD; - vector_int5_lit_phdr PT_LOAD; - vector_int5_text_phdr PT_LOAD; - vector_int6_lit_phdr PT_LOAD; - vector_int6_text_phdr PT_LOAD; - vector_int7_lit_phdr PT_LOAD; - vector_int7_text_phdr PT_LOAD; - vector_kernel_lit_phdr PT_LOAD; - vector_kernel_text_phdr PT_LOAD; - vector_user_lit_phdr PT_LOAD; - vector_user_text_phdr PT_LOAD; - vector_double_lit_phdr PT_LOAD; - vector_double_text_phdr PT_LOAD; - sof_fw_phdr PT_LOAD; - buffer_hp_heap_phdr PT_LOAD; - wnd0_phdr PT_LOAD; - wnd1_phdr PT_LOAD; - wnd2_phdr PT_LOAD; - wnd3_phdr PT_LOAD; - static_uuid_entries_phdr PT_NOTE; - static_log_entries_phdr PT_NOTE; - metadata_entries_phdr PT_NOTE; - lpsram_mem_phdr PT_LOAD; - sram_alt_fw_reset_vec_phdr PT_LOAD; - sram_alt_fw_reset_vec_int_phdr PT_LOAD; - lpsram_code_phdr PT_LOAD; -} - -/* Default entry point: */ -ENTRY(_MainEntry) -_rom_store_table = 0; - -/* ABI0 does not use Window base */ -PROVIDE(_memmap_vecbase_reset = HP_SRAM_VECBASE_RESET); - -/* Various memory-map dependent cache attribute settings: */ -_memmap_cacheattr_wbna_trapnull = 0xFF42FFF2; -PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull); - -_EXT_MAN_ALIGN_ = 16; -EXTERN(ext_man_fw_ver) -EXTERN(ext_man_cavs_config) -EXTERN(_LpsramHeader) -EXTERN(_AltResetVector) - -SECTIONS -{ - .MemoryExceptionVector.text : ALIGN(4) - { - _MemoryExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.MemoryExceptionVector.text)) - _MemoryExceptionVector_text_end = ABSOLUTE(.); - } >vector_memory_text :vector_memory_text_phdr - - .buffer_hp_heap (NOLOAD) : ALIGN(8) - { - . = ALIGN (32); - _buffer_hp_heap_start = ABSOLUTE(.); - . = . + HEAP_HP_BUFFER_SIZE; - _buffer_hp_heap_end = ABSOLUTE(.); - } >buffer_hp_heap :buffer_hp_heap_phdr - - .wnd0 (NOLOAD) : ALIGN(8) - { - . = ALIGN (32); - _wnd0_start = ABSOLUTE(.); - . = . + HP_SRAM_WIN0_SIZE; - _wnd0_end = ABSOLUTE(.); - } >wnd0 :wnd0_phdr - - .wnd1 (NOLOAD) : ALIGN(8) - { - . = ALIGN (32); - _wnd1_start = ABSOLUTE(.); - . = . + HP_SRAM_WIN1_SIZE; - _wnd1_end = ABSOLUTE(.); - } >wnd1 :wnd1_phdr - - .wnd2 (NOLOAD) : ALIGN(8) - { - . = ALIGN (32); - _wnd2_start = ABSOLUTE(.); - . = . + HP_SRAM_WIN2_SIZE; - _wnd2_end = ABSOLUTE(.); - } >wnd2 :wnd2_phdr - - .wnd3 (NOLOAD) : ALIGN(8) - { - . = ALIGN (32); - _wnd3_start = ABSOLUTE(.); - . = . + HP_SRAM_WIN3_SIZE; - _wnd3_end = ABSOLUTE(.); - } >wnd3 :wnd3_phdr - - .WindowVectors.text : ALIGN(4) - { - _WindowVectors_text_start = ABSOLUTE(.); - KEEP (*(.WindowVectors.text)) - _WindowVectors_text_end = ABSOLUTE(.); - } >vector_base_text :vector_base_text_phdr - - .Level2InterruptVector.literal : ALIGN(4) - { - _Level2InterruptVector_literal_start = ABSOLUTE(.); - *(.Level2InterruptVector.literal) - _Level2InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int2_lit :vector_int2_lit_phdr - - .Level2InterruptVector.text : ALIGN(4) - { - _Level2InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level2InterruptVector.text)) - _Level2InterruptVector_text_end = ABSOLUTE(.); - } >vector_int2_text :vector_int2_text_phdr - - .Level3InterruptVector.literal : ALIGN(4) - { - _Level3InterruptVector_literal_start = ABSOLUTE(.); - *(.Level3InterruptVector.literal) - _Level3InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int3_lit :vector_int3_lit_phdr - - .Level3InterruptVector.text : ALIGN(4) - { - _Level3InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level3InterruptVector.text)) - _Level3InterruptVector_text_end = ABSOLUTE(.); - } >vector_int3_text :vector_int3_text_phdr - - .Level4InterruptVector.literal : ALIGN(4) - { - _Level4InterruptVector_literal_start = ABSOLUTE(.); - *(.Level4InterruptVector.literal) - _Level4InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int4_lit :vector_int4_lit_phdr - - .Level4InterruptVector.text : ALIGN(4) - { - _Level4InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level4InterruptVector.text)) - _Level4InterruptVector_text_end = ABSOLUTE(.); - } >vector_int4_text :vector_int4_text_phdr - - .Level5InterruptVector.literal : ALIGN(4) - { - _Level5InterruptVector_literal_start = ABSOLUTE(.); - *(.Level5InterruptVector.literal) - _Level5InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int5_lit :vector_int5_lit_phdr - - .Level5InterruptVector.text : ALIGN(4) - { - _Level5InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level5InterruptVector.text)) - _Level5InterruptVector_text_end = ABSOLUTE(.); - } >vector_int5_text :vector_int5_text_phdr - - .DebugExceptionVector.literal : ALIGN(4) - { - _DebugExceptionVector_literal_start = ABSOLUTE(.); - *(.DebugExceptionVector.literal) - _DebugExceptionVector_literal_end = ABSOLUTE(.); - } >vector_int6_lit :vector_int6_lit_phdr - - .DebugExceptionVector.text : ALIGN(4) - { - _DebugExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DebugExceptionVector.text)) - _DebugExceptionVector_text_end = ABSOLUTE(.); - } >vector_int6_text :vector_int6_text_phdr - - .NMIExceptionVector.literal : ALIGN(4) - { - _NMIExceptionVector_literal_start = ABSOLUTE(.); - *(.NMIExceptionVector.literal) - _NMIExceptionVector_literal_end = ABSOLUTE(.); - } >vector_int7_lit :vector_int7_lit_phdr - - .NMIExceptionVector.text : ALIGN(4) - { - _NMIExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.NMIExceptionVector.text)) - _NMIExceptionVector_text_end = ABSOLUTE(.); - } >vector_int7_text :vector_int7_text_phdr - - .KernelExceptionVector.literal : ALIGN(4) - { - _KernelExceptionVector_literal_start = ABSOLUTE(.); - *(.KernelExceptionVector.literal) - _KernelExceptionVector_literal_end = ABSOLUTE(.); - } >vector_kernel_lit :vector_kernel_lit_phdr - - .KernelExceptionVector.text : ALIGN(4) - { - _KernelExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.KernelExceptionVector.text)) - _KernelExceptionVector_text_end = ABSOLUTE(.); - } >vector_kernel_text :vector_kernel_text_phdr - - .UserExceptionVector.literal : ALIGN(4) - { - _UserExceptionVector_literal_start = ABSOLUTE(.); - *(.UserExceptionVector.literal) - _UserExceptionVector_literal_end = ABSOLUTE(.); - } >vector_user_lit :vector_user_lit_phdr - - .UserExceptionVector.text : ALIGN(4) - { - _UserExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.UserExceptionVector.text)) - _UserExceptionVector_text_end = ABSOLUTE(.); - } >vector_user_text :vector_user_text_phdr - - .DoubleExceptionVector.literal : ALIGN(4) - { - _DoubleExceptionVector_literal_start = ABSOLUTE(.); - *(.DoubleExceptionVector.literal) - _DoubleExceptionVector_literal_end = ABSOLUTE(.); - } >vector_double_lit :vector_double_lit_phdr - - .DoubleExceptionVector.text : ALIGN(4) - { - _DoubleExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DoubleExceptionVector.text)) - _DoubleExceptionVector_text_end = ABSOLUTE(.); - } >vector_double_text :vector_double_text_phdr - - .text : ALIGN(4) - { - _stext = .; - _text_start = ABSOLUTE(.); - KEEP (*(.MainEntry.text)) - *(.entry.text) - *(.init.literal) - KEEP(*(.init)) - KEEP(*(.lps_vector)) - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.fini.literal) - KEEP(*(.fini)) - *(.gnu.version) - KEEP (*(.ResetHandler.text)) - _text_end = ABSOLUTE(.); - _etext = .; - } >sof_fw :sof_fw_phdr - -#if CONFIG_MULTICORE - .AlternateResetVector.text : ALIGN(64) - { - _alternate_reset_vector_start = ABSOLUTE(.); - KEEP (*(*.AlternateResetVector.text)) - . = ALIGN(16); - _alternate_reset_vector_start_end = ABSOLUTE(.); - } >lpsram_alt_reset_vec_seg AT> sof_fw : sram_alt_fw_reset_vec_phdr - - .AlternateResetL2IntVector.text : ALIGN(16) - { - _alternate_reset_l2_int_vector_start = ABSOLUTE(.); - KEEP (*(*.AlternateResetL2IntVector.text)) - . = ALIGN(16); - _alternate_reset_l2_int_vector_end = ABSOLUTE(.); - } >lpsram_alt_reset_int_vec_seg AT> sof_fw : sram_alt_fw_reset_vec_int_phdr - - .LpsramCode.text : ALIGN(16) - { - _lpsram_code_start = ABSOLUTE(.); - KEEP (*(*.LpsramCode.text)) - . = ALIGN(16); - _lpsram_code_end = ABSOLUTE(.); - } >lpsram_code_seg AT> sof_fw : lpsram_code_phdr -#endif - - .rodata : ALIGN(4096) - { - _rodata_start = ABSOLUTE(.); - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); - KEEP (*(.xt_except_table)) - KEEP (*(.gcc_except_table)) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - KEEP (*(.eh_frame)) - /* C++ constructor and destructor tables, properly ordered: */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); /* this table MUST be 4-byte aligned */ - _bss_table_start = ABSOLUTE(.); - LONG(_bss_start) - LONG(_bss_end) - _bss_table_end = ABSOLUTE(.); - _rodata_end = ABSOLUTE(.); - } >sof_fw :sof_fw_phdr - - .module_init : ALIGN(4) - { - _module_init_start = ABSOLUTE(.); - *(*.initcall) - _module_init_end = ABSOLUTE(.); - } >sof_fw :sof_fw_phdr - - .shared_data : ALIGN(PLATFORM_DCACHE_ALIGN) - { - _shared_data_start = ABSOLUTE(.); - *(*.shared_data) - _shared_data_end = ABSOLUTE(.); - . = ALIGN(PLATFORM_DCACHE_ALIGN); - } >sof_fw :sof_fw_phdr - - .data : ALIGN(4) - { - _data_start = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - KEEP(*(.gnu.linkonce.d.*personality*)) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - KEEP(*(.jcr)) - _trace_ctx_start = ABSOLUTE(.); - *(.trace_ctx) - _trace_ctx_end = ABSOLUTE(.); - _data_end = ABSOLUTE(.); - } >sof_fw :sof_fw_phdr - - .lit4 : ALIGN(4) - { - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - } >sof_fw :sof_fw_phdr - - .fw_ready : ALIGN(4) - { - KEEP (*(.fw_ready)) - KEEP (*(.fw_ready_metadata)) - } >sof_fw :sof_fw_phdr - - .AltBootManifest : ALIGN(8) - { - /* Single entry of strorage manifest - * consist of 3 items. Entries array - * is preceded by a single dword with - * entries count. */ - _loader_storage_manifest_start = ABSOLUTE(.); - /* Number of entries*/ - LONG(3); - /* Entry 1 */ - LONG(LOADADDR(.AlternateResetVector.text)); - LONG(ADDR(.AlternateResetVector.text)); - LONG(SIZEOF(.AlternateResetVector.text)); -#if CONFIG_MULTICORE - /* Entry 2 */ - LONG(LOADADDR(.AlternateResetL2IntVector.text)); - LONG(ADDR(.AlternateResetL2IntVector.text)); - LONG(SIZEOF(.AlternateResetL2IntVector.text)); -#endif - /* Entry 3 */ - LONG(LOADADDR(.LpsramCode.text)); - LONG(ADDR(.LpsramCode.text)); - LONG(SIZEOF(.LpsramCode.text)); - _loader_storage_manifest_end = ABSOLUTE(.); - } >sof_fw :sof_fw_phdr - - .bss (NOLOAD) : ALIGN(4096) - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - - . = ALIGN (SRAM_BANK_SIZE); - _system_heap_start = ABSOLUTE(.); - . = . + HEAP_SYSTEM_M_SIZE; - _system_heap_end = ABSOLUTE(.); - - . = ALIGN (HEAP_BUF_ALIGNMENT); - _system_runtime_heap_start = ABSOLUTE(.); - . = . + HEAP_SYS_RUNTIME_M_SIZE; - _system_runtime_heap_end = ABSOLUTE(.); - - . = ALIGN (4096); - _sof_stack_start = ABSOLUTE(.); - . = . + SOF_STACK_SIZE; - _sof_stack_end = ABSOLUTE(.); - -#if CONFIG_CORE_COUNT > 1 - . = ALIGN (PLATFORM_DCACHE_ALIGN); - _runtime_shared_heap_start = ABSOLUTE(.); - . = . + HEAP_RUNTIME_SHARED_SIZE; - . = ALIGN (PLATFORM_DCACHE_ALIGN); - _runtime_shared_heap_end = ABSOLUTE(.); - - . = ALIGN (PLATFORM_DCACHE_ALIGN); - _system_shared_heap_start = ABSOLUTE(.); - . = . + HEAP_SYSTEM_SHARED_SIZE; - . = ALIGN (PLATFORM_DCACHE_ALIGN); - _system_shared_heap_end = ABSOLUTE(.); -#endif - - . = ALIGN (SRAM_BANK_SIZE); - _sof_core_s_start = ABSOLUTE(.); - . = . + SOF_CORE_S_T_SIZE; - _sof_core_s_end = ABSOLUTE(.); - - . = ALIGN (SRAM_BANK_SIZE); - _runtime_heap_start = ABSOLUTE(.); - . = . + HEAP_RUNTIME_SIZE; - _runtime_heap_end = ABSOLUTE(.); - - . = ALIGN (HEAP_BUF_ALIGNMENT); - _buffer_heap_start = ABSOLUTE(.); - . = . + SOF_FW_END - _buffer_heap_start; - _buffer_heap_end = ABSOLUTE(.); - - _bss_end = ABSOLUTE(.); - } >sof_fw :sof_fw_phdr - - /* stack */ - _end = _sof_stack_start; - PROVIDE(end = _sof_stack_start); - _stack_sentry = _sof_stack_start; - __stack = _sof_stack_end; - - /* Secondary core size */ - _core_s_size = SOF_CORE_S_SIZE; - - /* System Heap */ - _system_heap = _system_heap_start; - - /* system runtime heap */ - _system_runtime_heap = _system_runtime_heap_start; - -#if CONFIG_CORE_COUNT > 1 - /* Shared Heap */ - _runtime_shared_heap = _runtime_shared_heap_start; - _system_shared_heap = _system_shared_heap_start; -#endif - - /* module heap */ - _module_heap = _runtime_heap_start; - - /* buffer heap */ - _buffer_heap = _buffer_heap_start; - _buffer_heap_end = _buffer_heap_end; - - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .xt.profile_range 0 : - { - KEEP (*(.xt.profile_range)) - KEEP (*(.gnu.linkonce.profile_range.*)) - } - .xt.profile_ranges 0 : - { - KEEP (*(.xt.profile_ranges)) - KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) - } - .xt.profile_files 0 : - { - KEEP (*(.xt.profile_files)) - KEEP (*(.gnu.linkonce.xt.profile_files.*)) - } - - .static_uuid_entries (COPY) : ALIGN(1024) - { - *(*.static_uuids) - } > static_uuid_entries_seg :static_uuid_entries_phdr - - .static_log_entries (COPY) : ALIGN(1024) - { - *(*.static_log*) - } > static_log_entries_seg :static_log_entries_phdr - - .fw_metadata (COPY) : ALIGN(1024) - { - KEEP (*(.fw_metadata)) - . = ALIGN(_EXT_MAN_ALIGN_); - } >fw_metadata_seg :metadata_entries_phdr - - .lpsram(NOLOAD) : ALIGN(8) - { - _lpsram_start = ABSOLUTE(.); - KEEP (*(*.lpsram)) - _lpsram_end = ABSOLUTE(.); - } >lpsram_mem :lpsram_mem_phdr - -}