Implementing RV32C instruction

[WeiCheng14159]

Hi,

I saw you put the implementation of RV32C on the TODO list, are you working on this topic now ?
We're a group of students from CSIE dept NCKU and want to contribute to this repo. This is part of our term project assigned by jserv. We're still working on it, some of our work (in progress) can be found here ,and work done by seniors can be found here

Many thanks !

[kuopinghsu]

I am glad to see that this is helpful, and your contributions are welcome. The implementation of RV32C is not my top priority. Maybe I will do ISS first to support RV32C, and then pass the compliance test to ensure that the necessary porting is completed.

[WeiCheng14159]

Thanks for your feedback !
It's extremely helpful for students to pick up concept on textbook when there is a working riscv core available
This is by far the most concise and well supported (on system level) RV32 core online
Thank you again for making this open source

I have been working on RV32C support on srv32 for a week and have a working implementation that passes all RV32IMC compliance test (v1.0). My work can be fonud in this branch and explain in details here

But my implementation lost 50% of performance when dealing with RV32C instructions ;(
There are definitely room for improvement and my code needs to be polished
Maybe I will open a pull request when finish. No hurry ;)

[kuopinghsu]

I have added RV32C support to the ISS simulator and passed the compliance test v1.

[WeiCheng14159]

👍 I will try to merge it this week

[jserv]

Is it ready to close this issue?

[kuopinghsu]

Is it ready to close this issue?

Not yet. Only the ISS simulator supports RV32C, not RTL. I will keep this issue open until RTL fully supports RV32C.

[jserv]

FYI: RISCVIMC is a fork of srv32 and implements compressed extension. See its report.

[kuopinghsu]

Thank you for the information. I will take a look. Thanks & Regards, Kuoping Jim Huang ***@***.***> 於 2022年9月28日 週三 下午4:31寫道：

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FYI: [RISCVIMC <https://github.com/nadeemasghar55/RISCVIMC> is a fork of srv32 and implements compressed extension. See its report <https://github.com/nadeemasghar55/RISCVIMC/blob/main/doc/Project_Report.md> . — Reply to this email directly, view it on GitHub <#5 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AGW6DIQOGJL2SUSZJ5LIJULWAP67LANCNFSM4VO72FWQ> . You are receiving this because you commented.Message ID: ***@***.***>

[kuopinghsu]

I checked RISCVIMC, which is an incomplete implementation. It only applies to test code under sw/C/C.s assembly file. This is a simple test of 3 compressed instructions without branches. Other tests fail even the simple "hello world" test. I will try to implement compressed instructions, but I am busy at this moment. Progress will be slow. Thanks & Regards, Kuoping Kuoping Hsu ***@***.***> 於 2022年9月28日 週三 下午4:39寫道：

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Thank you for the information. I will take a look. Thanks & Regards, Kuoping Jim Huang ***@***.***> 於 2022年9月28日 週三 下午4:31寫道： > FYI: [RISCVIMC <https://github.com/nadeemasghar55/RISCVIMC> is a fork of > srv32 and implements compressed extension. See its report > <https://github.com/nadeemasghar55/RISCVIMC/blob/main/doc/Project_Report.md> > . > > — > Reply to this email directly, view it on GitHub > <#5 (comment)>, > or unsubscribe > <https://github.com/notifications/unsubscribe-auth/AGW6DIQOGJL2SUSZJ5LIJULWAP67LANCNFSM4VO72FWQ> > . > You are receiving this because you commented.Message ID: > ***@***.***> >