fill.v.bak

// Part 2 skeleton

module fill
	(
		CLOCK_50,						//	On Board 50 MHz
		// Your inputs and outputs here
		KEY, SW,							// On Board Keys
		// The ports below are for the VGA output.  Do not change.
		VGA_CLK,   						//	VGA Clock
		VGA_HS,							//	VGA H_SYNC
		VGA_VS,							//	VGA V_SYNC
		VGA_BLANK_N,						//	VGA BLANK
		VGA_SYNC_N,						//	VGA SYNC
		VGA_R,   						//	VGA Red[9:0]
		VGA_G,	 						//	VGA Green[9:0]
		VGA_B   						//	VGA Blue[9:0]
	);

	input			CLOCK_50;				//	50 MHz
	input	[3:0]	KEY;
	input   [9:0]   SW;					
	// Declare your inputs and outputs here
	// Do not change the following outputs
	output			VGA_CLK;   				//	VGA Clock
	output			VGA_HS;					//	VGA H_SYNC
	output			VGA_VS;					//	VGA V_SYNC
	output			VGA_BLANK_N;				//	VGA BLANK
	output			VGA_SYNC_N;				//	VGA SYNC
	output	[7:0]	VGA_R;   				//	VGA Red[7:0] Changed from 10 to 8-bit DAC
	output	[7:0]	VGA_G;	 				//	VGA Green[7:0]
	output	[7:0]	VGA_B;   				//	VGA Blue[7:0]
	
	wire resetn;
	assign resetn = KEY[0];
	
	// Create the colour, x, y and writeEn wires that are inputs to the controller.

	wire [2:0] colour;
	wire [7:0] x;
	wire [6:0] y;
	wire writeEn;
	
	// Create an Instance of a VGA controller - there can be only one!
	// Define the number of colours as well as the initial background
	// image file (.MIF) for the controller.
	/*vga_adapter VGA(
			.resetn(resetn),
			.clock(CLOCK_50),
			.colour(colour),
			.x(x),
			.y(y),
			.plot(writeEn),
			// Signals for the DAC to drive the monitor.
			.VGA_R(VGA_R),
			.VGA_G(VGA_G),
			.VGA_B(VGA_B),
			.VGA_HS(VGA_HS),
			.VGA_VS(VGA_VS),
			.VGA_BLANK(VGA_BLANK_N),
			.VGA_SYNC(VGA_SYNC_N),
			.VGA_CLK(VGA_CLK));
		defparam VGA.RESOLUTION = "160x120";
		defparam VGA.MONOCHROME = "FALSE";
		defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
		defparam VGA.BACKGROUND_IMAGE = "black.mif"; */
			
	// Put your code here. Your code should produce signals x,y,colour and writeEn
	// for the VGA controller, in addition to any other functionality your design may require.
	
	wire go;
	wire clear;
	
	assign colour = SW[9:7];
	assign writeEn = ~KEY[1];
	assign go = ~KEY[3];
	assign clear = ~KEY[2];

	do inst(resetn, CLOCK_50, go, SW[6:0], x, y);
endmodule

module do(reset, clk, go, data_in, x, y);
	input reset;
	input clk;
	input go;
	input [6:0] data_in;
	output [7:0] x;
	output [6:0] y;

	wire ld_x;
	wire ld_y;
	
	control inst1(reset, clk, go, ld_x, ld_y);
	dataPath inst2(reset, clk, ld_x, ld_y, data_in, x, y);

endmodule


module control(reset, clk, go, ld_x, ld_y);
	input reset;
	input clk;
	input go;
	output reg ld_x;
	output reg ld_y;

	reg [2:0] current_state, next_state;
	localparam	S_WAIT_X = 2'd0,
					S_LOAD_X = 2'd1,
					S_WAIT_Y = 2'd2,
					S_LOAD_Y = 2'd3;
	
	always@(*)
	begin
		case(current_state)
			S_WAIT_X: next_state = go ? S_LOAD_X : S_WAIT_X;
			S_LOAD_X: next_state = go ? S_LOAD_X : S_WAIT_Y;
			S_WAIT_Y: next_state = go ? S_LOAD_Y : S_WAIT_Y;
			S_LOAD_Y: next_state = go ? S_LOAD_Y : S_WAIT_X;
		endcase
	end

	always@(*)
	begin
		ld_x = 0;
		ld_y = 0;
		case(current_state)
			S_LOAD_X: ld_x = 1;
			S_LOAD_Y: ld_y = 1;
		endcase
	end

	always@(posedge clk)
	begin
		if (~reset) current_state <= S_WAIT_X;
		else current_state <= next_state;
	end
endmodule



module dataPath(reset, clk, ld_x, ld_y, data_in, x, y);
	input reset;
	input [6:0] data_in;
	input ld_x;
	input ld_y;
	input clk;
	output reg [7:0] x;
	output reg [6:0] y;

	always@(posedge clk)
	begin
		if (reset) begin
			if (ld_x) begin
				x[7] <= 0;
				x[6:0] <= data_in;
			end
			if (ld_y) y <= data_in;
		end else begin
			x <= 7'd0;
			y <= 6'd0;
		end
	end
endmodule