diff --git a/doc/rst/modules/auto/arithmetic.rst b/doc/rst/modules/auto/arithmetic.rst new file mode 100644 index 0000000..883a2d9 --- /dev/null +++ b/doc/rst/modules/auto/arithmetic.rst @@ -0,0 +1,97 @@ +.. Generated from ../rtl/extras/arithmetic.vhdl on 2017-08-02 00:26:38.024403 +.. vhdl:package:: extras.arithmetic + + +Components +---------- + + +coloration_test +~~~~~~~~~~~~~~~ + +.. symbolator:: + :name: arithmetic-coloration_test + + component coloration_test is + port ( + --# {{aaa}} + aaa : in std_ulogic; + --# {{bbb}} + bbb : in std_ulogic; + --# {{ccc}} + ccc : out std_ulogic; + --# {{ddd}} + ddd : out std_ulogic; + --# {{eee}} + eee : inout std_ulogic; + --# {{fff}} + fff : in std_ulogic + ); + end component; + +| + + +.. vhdl:entity:: coloration_test + + + :port aaa: None + :ptype aaa: in std_ulogic + :port bbb: None + :ptype bbb: in std_ulogic + :port ccc: None + :ptype ccc: out std_ulogic + :port ddd: None + :ptype ddd: out std_ulogic + :port eee: None + :ptype eee: inout std_ulogic + :port fff: None + :ptype fff: in std_ulogic + +pipelined_adder +~~~~~~~~~~~~~~~ + +.. symbolator:: + :name: arithmetic-pipelined_adder + + component pipelined_adder is + generic ( + SLICES : positive; + CONST_B_INPUT : boolean; + RESET_ACTIVE_LEVEL : std_ulogic + ); + port ( + --# {{clocks|}} + Clock : in std_ulogic; + Reset : in std_ulogic; + --# {{data|}} + A : in unsigned; + B : in unsigned; + Sum : out unsigned + ); + end component; + +| + + +.. vhdl:entity:: pipelined_adder + + Variable size pipelined adder. + + :generic SLICES: Number of pipeline stages + :gtype SLICES: positive + :generic CONST_B_INPUT: Optimize when the B input is constant + :gtype CONST_B_INPUT: boolean + :generic RESET_ACTIVE_LEVEL: Asynch. reset control level + :gtype RESET_ACTIVE_LEVEL: std_ulogic + + :port Clock: System clock + :ptype Clock: in std_ulogic + :port Reset: Asynchronous reset + :ptype Reset: in std_ulogic + :port A: Addend A + :ptype A: in unsigned + :port B: Addend B + :ptype B: in unsigned + :port Sum: Result sum of A and B + :ptype Sum: out unsigned diff --git a/doc/rst/modules/auto/filtering.rst b/doc/rst/modules/auto/filtering.rst new file mode 100644 index 0000000..0313ede --- /dev/null +++ b/doc/rst/modules/auto/filtering.rst @@ -0,0 +1,339 @@ +.. Generated from ../rtl/extras_2008/filtering.vhdl on 2017-08-02 00:26:38.757514 +.. vhdl:package:: extras_2008.filtering + + +Subtypes +-------- + + +.. vhdl:subtype:: attenuation_factor + + Attenuation gain from 0.0 to 1.0. + +Components +---------- + + +fir_filter +~~~~~~~~~~ + +.. symbolator:: + :name: filtering-fir_filter + + component fir_filter is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic + ); + port ( + --# {{clocks|}} + Clock : in std_ulogic; + Reset : in std_ulogic; + --# {{control|}} + Coefficients : in signed_array; + --# {{data|}} + New_data : in std_ulogic; + Data_in : in signed; + Data_out : out signed + ); + end component; + +| + + +.. vhdl:entity:: fir_filter + + + :generic RESET_ACTIVE_LEVEL: Asynch. reset control level + :gtype RESET_ACTIVE_LEVEL: std_ulogic + + :port Clock: None + :ptype Clock: in std_ulogic + :port Reset: None + :ptype Reset: in std_ulogic + :port Coefficients: None + :ptype Coefficients: in signed_array + :port New_data: None + :ptype New_data: in std_ulogic + :port Data_in: None + :ptype Data_in: in signed + :port Data_out: None + :ptype Data_out: out signed + +fir_filter_2 +~~~~~~~~~~~~ + +.. symbolator:: + :name: filtering-fir_filter_2 + + component fir_filter_2 is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic + ); + port ( + --# {{clocks|}} + Clock : in std_ulogic; + Reset : in std_ulogic; + --# {{control|}} + Coefficients : in signed_array; + --# {{data|Write port}} + Data_valid : in std_ulogic; + Data : in signed; + Busy : out std_ulogic; + --# {{Read port}} + Result_valid : out std_ulogic; + Result : out signed; + In_use : in std_ulogic + ); + end component; + +| + + +.. vhdl:entity:: fir_filter_2 + + Finite Impulse Response filter. + + :generic RESET_ACTIVE_LEVEL: Asynch. reset control level + :gtype RESET_ACTIVE_LEVEL: std_ulogic + + :port Clock: System clock + :ptype Clock: in std_ulogic + :port Reset: Asynchronous reset + :ptype Reset: in std_ulogic + :port Coefficients: Filter tap coefficients + :ptype Coefficients: in signed_array + :port Data_valid: Indicate when ``Data`` is valid + :ptype Data_valid: in std_ulogic + :port Data: Data input to the filter + :ptype Data: in signed + :port Busy: Indicate when filter is ready to accept new data + :ptype Busy: out std_ulogic + :port Result_valid: Indicates when a new filter result is valid + :ptype Result_valid: out std_ulogic + :port Result: Filtered output + :ptype Result: out signed + :port In_use: Request to keep ``Result`` unchanged + :ptype In_use: in std_ulogic + +lowpass_filter +~~~~~~~~~~~~~~ + +.. symbolator:: + :name: filtering-lowpass_filter + + component lowpass_filter is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic; + ALPHA : real; + REGISTERED_MULTIPLY : boolean + ); + port ( + --# {{clocks|}} + Clock : in std_ulogic; + Reset : in std_ulogic; + --# {{data|}} + Data : in signed; + Result : out signed + ); + end component; + +| + + +.. vhdl:entity:: lowpass_filter + + First order lowpass filter. + This filter operates in two modes. When REGISTERED_MULTIPLY is false + the filter processes a new data sample on every clock cycle. + + :generic RESET_ACTIVE_LEVEL: Asynch. reset control level + :gtype RESET_ACTIVE_LEVEL: std_ulogic + :generic ALPHA: Alpha parameter computed with lowpass_alpha() + :gtype ALPHA: real + :generic REGISTERED_MULTIPLY: Control registration of internal mutiplier + :gtype REGISTERED_MULTIPLY: boolean + + :port Clock: System clock + :ptype Clock: in std_ulogic + :port Reset: Asynchronous reset + :ptype Reset: in std_ulogic + :port Data: Data input to the filter + :ptype Data: in signed + :port Result: Filtered output + :ptype Result: out signed + +attenuate +~~~~~~~~~ + +.. symbolator:: + :name: filtering-attenuate + + component attenuate is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic + ); + port ( + --# {{clocks|}} + Clock : in std_ulogic; + Reset : in std_ulogic; + --# {{control|}} + Gain : in signed; + --# {{data|Write port}} + Data_valid : in std_ulogic; + Data : in signed; + --# {{Read port}} + Result_valid : out std_ulogic; + Result : out signed + ); + end component; + +| + + +.. vhdl:entity:: attenuate + + Scale samples by an attenuation factor. + + :generic RESET_ACTIVE_LEVEL: Asynch. reset control level + :gtype RESET_ACTIVE_LEVEL: std_ulogic + + :port Clock: System clock + :ptype Clock: in std_ulogic + :port Reset: Asynchronous reset + :ptype Reset: in std_ulogic + :port Gain: Attenuation factor + :ptype Gain: in signed + :port Data_valid: Indicate when ``Data`` is valid + :ptype Data_valid: in std_ulogic + :port Data: Data input to the filter + :ptype Data: in signed + :port Result_valid: Indicates when a new filter result is valid + :ptype Result_valid: out std_ulogic + :port Result: Filtered output + :ptype Result: out signed + +sampler +~~~~~~~ + +.. symbolator:: + :name: filtering-sampler + + component sampler is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic + ); + port ( + --# {{clocks|}} + Clock : in std_ulogic; + Reset : in std_ulogic; + --# {{data|Write port}} + Data_valid : in std_ulogic; + Data : in std_ulogic; + --# {{Read port}} + Result_valid : out std_ulogic; + Result : out signed + ); + end component; + +| + + +.. vhdl:entity:: sampler + + Convert binary data into numeric samples. + + :generic RESET_ACTIVE_LEVEL: Asynch. reset control level + :gtype RESET_ACTIVE_LEVEL: std_ulogic + + :port Clock: System clock + :ptype Clock: in std_ulogic + :port Reset: Asynchronous reset + :ptype Reset: in std_ulogic + :port Data_valid: Indicate when ``Data`` is valid + :ptype Data_valid: in std_ulogic + :port Data: Data input to the filter + :ptype Data: in std_ulogic + :port Result_valid: Indicates when a new filter result is valid + :ptype Result_valid: out std_ulogic + :port Result: Filtered output + :ptype Result: out signed + +sample_and_hold +~~~~~~~~~~~~~~~ + +.. symbolator:: + :name: filtering-sample_and_hold + + component sample_and_hold is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic + ); + port ( + --# {{clocks|}} + Clock : in std_ulogic; + Reset : in std_ulogic; + --# {{data|Write port}} + Data_valid : in std_ulogic; + Data : in signed; + Busy : out std_ulogic; + --# {{Read port}} + Result_valid : out std_ulogic; + Result : out signed; + In_use : in std_ulogic + ); + end component; + +| + + +.. vhdl:entity:: sample_and_hold + + Capture and hold data samples. + + :generic RESET_ACTIVE_LEVEL: Asynch. reset control level + :gtype RESET_ACTIVE_LEVEL: std_ulogic + + :port Clock: System clock + :ptype Clock: in std_ulogic + :port Reset: Asynchronous reset + :ptype Reset: in std_ulogic + :port Data_valid: Indicate when ``Data`` is valid + :ptype Data_valid: in std_ulogic + :port Data: Data input to the filter + :ptype Data: in signed + :port Busy: Indicate when filter is ready to accept new data + :ptype Busy: out std_ulogic + :port Result_valid: Indicates when a new filter result is valid + :ptype Result_valid: out std_ulogic + :port Result: Filtered output + :ptype Result: out signed + :port In_use: Request to keep ``Result`` unchanged + :ptype In_use: in std_ulogic + +Subprograms +----------- + + +.. vhdl:function:: function attenuation_gain(Factor : attenuation_factor; Size : positive) return signed; + + Convert attenuation factor into a signed factor + + :param Factor: Factor for gain value + :type Factor: attenuation_factor + :param Size: Number of bits in the result + :type Size: positive + :returns: Signed value representing the Factor scaled to the range of Size. + + + +.. vhdl:function:: function lowpass_alpha(Tau : real; Sample_period : real) return real; + + Compute the alpha value for a lowpass filter + + :param Tau: Time constant + :type Tau: real + :param Sample_period: Sample period of the filtered data + :type Sample_period: real + :returns: Alpha constant passed to the lowpass_filter component. + + diff --git a/doc/rst/modules/auto/oscillator.rst b/doc/rst/modules/auto/oscillator.rst new file mode 100644 index 0000000..905606c --- /dev/null +++ b/doc/rst/modules/auto/oscillator.rst @@ -0,0 +1,308 @@ +.. Generated from ../rtl/extras/oscillator.vhdl on 2017-08-02 00:26:37.934436 +.. vhdl:package:: extras.oscillator + + +Components +---------- + + +fixed_oscillator +~~~~~~~~~~~~~~~~ + +.. symbolator:: + :name: oscillator-fixed_oscillator + + component fixed_oscillator is + generic ( + SYS_CLOCK_FREQ : frequency; + OUTPUT_FREQ : frequency; + TOLERANCE : real; + SIZE : positive; + ITERATIONS : positive; + MAGNITUDE : real; + RESET_ACTIVE_LEVEL : std_ulogic + ); + port ( + --# {{clocks|}} + Clock : in std_ulogic; + Reset : in std_ulogic; + --# {{control|}} + Load_phase : in std_ulogic; + New_phase : in unsigned; + --# {{data|}} + Sin : out signed(SIZE-1 downto 0); + Cos : out signed(SIZE-1 downto 0); + Angle : out signed(SIZE-1 downto 0); + Synth_clock : out std_ulogic + ); + end component; + +| + + +.. vhdl:entity:: fixed_oscillator + + Oscillator with a fixed frequency output. + Samples are generated on every clock cycle. + + :generic SYS_CLOCK_FREQ: System clock frequency + :gtype SYS_CLOCK_FREQ: frequency + :generic OUTPUT_FREQ: Generated frequency + :gtype OUTPUT_FREQ: frequency + :generic TOLERANCE: Error tolerance + :gtype TOLERANCE: real + :generic SIZE: Width of operands + :gtype SIZE: positive + :generic ITERATIONS: Number of iterations for CORDIC algorithm + :gtype ITERATIONS: positive + :generic MAGNITUDE: Scale factor for Sin and Cos + :gtype MAGNITUDE: real + :generic RESET_ACTIVE_LEVEL: Asynch. reset control level + :gtype RESET_ACTIVE_LEVEL: std_ulogic + + :port Clock: System clock + :ptype Clock: in std_ulogic + :port Reset: Asynchronous reset + :ptype Reset: in std_ulogic + :port Load_phase: Load a new phase angle + :ptype Load_phase: in std_ulogic + :port New_phase: Phase angle to load + :ptype New_phase: in unsigned + :port Sin: Sine output + :ptype Sin: out signed(SIZE-1 downto 0) + :port Cos: Cosine output + :ptype Cos: out signed(SIZE-1 downto 0) + :port Angle: Phase angle in brads + :ptype Angle: out signed(SIZE-1 downto 0) + :port Synth_clock: Generated clock + :ptype Synth_clock: out std_ulogic + +fixed_oscillator_sequential +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. symbolator:: + :name: oscillator-fixed_oscillator_sequential + + component fixed_oscillator_sequential is + generic ( + SYS_CLOCK_FREQ : frequency; + OUTPUT_FREQ : frequency; + TOLERANCE : real; + SIZE : positive; + ITERATIONS : positive; + MAGNITUDE : real; + CAPTURE_RESULT : boolean; + RESET_ACTIVE_LEVEL : std_ulogic + ); + port ( + --# {{clocks|}} + Clock : in std_ulogic; + Reset : in std_ulogic; + --# {{control|}} + Load_phase : in std_ulogic; + New_phase : in unsigned; + Result_valid : out std_ulogic; + --# {{data|}} + Sin : out signed(SIZE-1 downto 0); + Cos : out signed(SIZE-1 downto 0); + Angle : out signed(SIZE-1 downto 0); + Synth_clock : out std_ulogic + ); + end component; + +| + + +.. vhdl:entity:: fixed_oscillator_sequential + + Oscillator with a fixed frequency output. + Samples are generated on after every ITERATIONS clock cycles. + + :generic SYS_CLOCK_FREQ: System clock frequency + :gtype SYS_CLOCK_FREQ: frequency + :generic OUTPUT_FREQ: Generated frequency + :gtype OUTPUT_FREQ: frequency + :generic TOLERANCE: Error tolerance + :gtype TOLERANCE: real + :generic SIZE: Width of operands + :gtype SIZE: positive + :generic ITERATIONS: Number of iterations for CORDIC algorithm + :gtype ITERATIONS: positive + :generic MAGNITUDE: Scale factor for Sin and Cos + :gtype MAGNITUDE: real + :generic CAPTURE_RESULT: Register outputs when valid + :gtype CAPTURE_RESULT: boolean + :generic RESET_ACTIVE_LEVEL: Asynch. reset control level + :gtype RESET_ACTIVE_LEVEL: std_ulogic + + :port Clock: System clock + :ptype Clock: in std_ulogic + :port Reset: Asynchronous reset + :ptype Reset: in std_ulogic + :port Load_phase: Load a new phase angle + :ptype Load_phase: in std_ulogic + :port New_phase: Phase angle to load + :ptype New_phase: in unsigned + :port Result_valid: New samples are ready + :ptype Result_valid: out std_ulogic + :port Sin: Sine output + :ptype Sin: out signed(SIZE-1 downto 0) + :port Cos: Cosine output + :ptype Cos: out signed(SIZE-1 downto 0) + :port Angle: Phase angle in brads + :ptype Angle: out signed(SIZE-1 downto 0) + :port Synth_clock: Generated clock + :ptype Synth_clock: out std_ulogic + +dynamic_oscillator +~~~~~~~~~~~~~~~~~~ + +.. symbolator:: + :name: oscillator-dynamic_oscillator + + component dynamic_oscillator is + generic ( + SYS_CLOCK_FREQ : real; + MIN_TGT_FREQ : natural; + TOLERANCE : real; + SIZE : natural; + ITERATIONS : positive; + MAGNITUDE : real; + FREQ_SCALE : natural; + RESET_ACTIVE_LEVEL : std_ulogic + ); + port ( + --# {{clocks|}} + Clock : in std_ulogic; + Reset : in std_ulogic; + --# {{control|}} + Load_phase : in std_ulogic; + New_phase : in unsigned; + Dyn_freq : in unsigned; + --# {{data|}} + Sin : out signed(SIZE-1 downto 0); + Cos : out signed(SIZE-1 downto 0); + Angle : out signed(SIZE-1 downto 0); + Synth_clock : out std_ulogic + ); + end component; + +| + + +.. vhdl:entity:: dynamic_oscillator + + + :generic SYS_CLOCK_FREQ: System clock frequency + :gtype SYS_CLOCK_FREQ: real + :generic MIN_TGT_FREQ: Lowest supported output frequency + :gtype MIN_TGT_FREQ: natural + :generic TOLERANCE: Error tolerance + :gtype TOLERANCE: real + :generic SIZE: Width of operands + :gtype SIZE: natural + :generic ITERATIONS: Number of iterations for CORDIC algorithm + :gtype ITERATIONS: positive + :generic MAGNITUDE: Scale factor for Sin and Cos magnitude + :gtype MAGNITUDE: real + :generic FREQ_SCALE: Scale factor for target frequency + :gtype FREQ_SCALE: natural + :generic RESET_ACTIVE_LEVEL: Asynch. reset control level + :gtype RESET_ACTIVE_LEVEL: std_ulogic + + :port Clock: System clock + :ptype Clock: in std_ulogic + :port Reset: Asynchronous reset + :ptype Reset: in std_ulogic + :port Load_phase: Load a new phase angle + :ptype Load_phase: in std_ulogic + :port New_phase: Phase angle to load + :ptype New_phase: in unsigned + :port Dyn_freq: Dynamic frequency in FIXME + :ptype Dyn_freq: in unsigned + :port Sin: Sine output + :ptype Sin: out signed(SIZE-1 downto 0) + :port Cos: Cosine output + :ptype Cos: out signed(SIZE-1 downto 0) + :port Angle: Phase angle in brads + :ptype Angle: out signed(SIZE-1 downto 0) + :port Synth_clock: Generated clock + :ptype Synth_clock: out std_ulogic + +dynamic_oscillator_sequential +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. symbolator:: + :name: oscillator-dynamic_oscillator_sequential + + component dynamic_oscillator_sequential is + generic ( + SYS_CLOCK_FREQ : real; + MIN_TGT_FREQ : natural; + TOLERANCE : real; + SIZE : natural; + ITERATIONS : positive; + MAGNITUDE : real; + FREQ_SCALE : natural; + CAPTURE_RESULT : boolean; + RESET_ACTIVE_LEVEL : std_ulogic + ); + port ( + --# {{clocks|}} + Clock : in std_ulogic; + Reset : in std_ulogic; + --# {{control|}} + Load_phase : in std_ulogic; + New_phase : in unsigned; + Dyn_freq : in unsigned; + --# {{data|}} + Sin : out signed(SIZE-1 downto 0); + Cos : out signed(SIZE-1 downto 0); + Angle : out signed(SIZE-1 downto 0); + Synth_clock : out std_ulogic + ); + end component; + +| + + +.. vhdl:entity:: dynamic_oscillator_sequential + + + :generic SYS_CLOCK_FREQ: System clock frequency + :gtype SYS_CLOCK_FREQ: real + :generic MIN_TGT_FREQ: Lowest supported output frequency + :gtype MIN_TGT_FREQ: natural + :generic TOLERANCE: Error tolerance + :gtype TOLERANCE: real + :generic SIZE: Width of operands + :gtype SIZE: natural + :generic ITERATIONS: Number of iterations for CORDIC algorithm + :gtype ITERATIONS: positive + :generic MAGNITUDE: Scale factor for Sin and Cos magnitude + :gtype MAGNITUDE: real + :generic FREQ_SCALE: Scale factor for target frequency + :gtype FREQ_SCALE: natural + :generic CAPTURE_RESULT: Register outputs when valid + :gtype CAPTURE_RESULT: boolean + :generic RESET_ACTIVE_LEVEL: Asynch. reset control level + :gtype RESET_ACTIVE_LEVEL: std_ulogic + + :port Clock: System clock + :ptype Clock: in std_ulogic + :port Reset: Asynchronous reset + :ptype Reset: in std_ulogic + :port Load_phase: Load a new phase angle + :ptype Load_phase: in std_ulogic + :port New_phase: Phase angle to load + :ptype New_phase: in unsigned + :port Dyn_freq: Dynamic frequency in FIXME + :ptype Dyn_freq: in unsigned + :port Sin: Sine output + :ptype Sin: out signed(SIZE-1 downto 0) + :port Cos: Cosine output + :ptype Cos: out signed(SIZE-1 downto 0) + :port Angle: Phase angle in brads + :ptype Angle: out signed(SIZE-1 downto 0) + :port Synth_clock: Generated clock + :ptype Synth_clock: out std_ulogic diff --git a/doc/rst/modules/auto/pipelining_2008.rst b/doc/rst/modules/auto/pipelining_2008.rst new file mode 100644 index 0000000..945ebbc --- /dev/null +++ b/doc/rst/modules/auto/pipelining_2008.rst @@ -0,0 +1,53 @@ +.. Generated from ../rtl/extras_2008/pipelining_2008.vhdl on 2017-08-02 00:26:38.904736 +.. vhdl:package:: extras_2008.pipelining + + +Components +---------- + + +tapped_delay_line +~~~~~~~~~~~~~~~~~ + +.. symbolator:: + :name: pipelining-tapped_delay_line + + component tapped_delay_line is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic; + REGISTER_FIRST_STAGE : boolean + ); + port ( + --# {{clocks|}} + Clock : in std_ulogic; + Reset : in std_ulogic; + --# {{control|}} + Enable : in std_ulogic; + --# {{data|}} + Data : in std_ulogic_vector; + Taps : out sulv_array + ); + end component; + +| + + +.. vhdl:entity:: tapped_delay_line + + Vector delay line with an output for each stage. + + :generic RESET_ACTIVE_LEVEL: Asynch. reset control level + :gtype RESET_ACTIVE_LEVEL: std_ulogic + :generic REGISTER_FIRST_STAGE: Register or pass through the first stage + :gtype REGISTER_FIRST_STAGE: boolean + + :port Clock: System clock + :ptype Clock: in std_ulogic + :port Reset: Asynchronous reset + :ptype Reset: in std_ulogic + :port Enable: Enable delay line + :ptype Enable: in std_ulogic + :port Data: Input to the delay line + :ptype Data: in std_ulogic_vector + :port Taps: Taps from each stage + :ptype Taps: out sulv_array diff --git a/doc/rst/modules/auto/prng.rst b/doc/rst/modules/auto/prng.rst new file mode 100644 index 0000000..25cf470 --- /dev/null +++ b/doc/rst/modules/auto/prng.rst @@ -0,0 +1,105 @@ +.. Generated from ../rtl/extras/prng.vhdl on 2017-08-02 00:26:37.903735 +.. vhdl:package:: extras.prng + + +Components +---------- + + +weak_prng +~~~~~~~~~ + +.. symbolator:: + :name: prng-weak_prng + + component weak_prng is + generic ( + STATE_BITS : positive; + LCAR_RATIO : real; + RESET_ACTIVE_LEVEL : std_ulogic + ); + port ( + --# {{clocks|}} + Clock : in std_ulogic; + Reset : in std_ulogic; + Enable : in std_ulogic; + Load_seed : in std_ulogic; + Seed : in std_ulogic_vector; + Entropy_stream : in std_ulogic; + Initialized : out std_ulogic; + Result : out std_ulogic_vector + ); + end component; + +| + + +.. vhdl:entity:: weak_prng + + + :generic STATE_BITS: + :gtype STATE_BITS: positive + :generic LCAR_RATIO: + :gtype LCAR_RATIO: real + :generic RESET_ACTIVE_LEVEL: Asynch. reset control level + :gtype RESET_ACTIVE_LEVEL: std_ulogic + + :port Clock: System clock + :ptype Clock: in std_ulogic + :port Reset: Asynchronous reset + :ptype Reset: in std_ulogic + :port Enable: None + :ptype Enable: in std_ulogic + :port Load_seed: None + :ptype Load_seed: in std_ulogic + :port Seed: None + :ptype Seed: in std_ulogic_vector + :port Entropy_stream: None + :ptype Entropy_stream: in std_ulogic + :port Initialized: None + :ptype Initialized: out std_ulogic + :port Result: None + :ptype Result: out std_ulogic_vector + +xorshift128plus +~~~~~~~~~~~~~~~ + +.. symbolator:: + :name: prng-xorshift128plus + + component xorshift128plus is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic + ); + port ( + --# {{clocks|}} + Clock : in std_ulogic; + Reset : in std_ulogic; + Enable : in std_ulogic; + Load_seed : in std_ulogic; + Seed : in unsigned(127 downto 0); + Result : out unsigned(63 downto 0) + ); + end component; + +| + + +.. vhdl:entity:: xorshift128plus + + + :generic RESET_ACTIVE_LEVEL: Asynch. reset control level + :gtype RESET_ACTIVE_LEVEL: std_ulogic + + :port Clock: System clock + :ptype Clock: in std_ulogic + :port Reset: Asynchronous reset + :ptype Reset: in std_ulogic + :port Enable: None + :ptype Enable: in std_ulogic + :port Load_seed: None + :ptype Load_seed: in std_ulogic + :port Seed: None + :ptype Seed: in unsigned(127 downto 0) + :port Result: None + :ptype Result: out unsigned(63 downto 0) diff --git a/doc/rst/modules/oscillator.rst b/doc/rst/modules/oscillator.rst new file mode 100644 index 0000000..fd815cc --- /dev/null +++ b/doc/rst/modules/oscillator.rst @@ -0,0 +1,28 @@ +========== +oscillator +========== + +`extras/oscillator.vhdl `_ + + +Dependencies +------------ + +:doc:`ddfs`, +:doc:`cordic`, +:doc:`sizing`, +:doc:`timing_ops` + +Description +----------- + + +Example usage +~~~~~~~~~~~~~ + +.. code-block:: vhdl + + + +.. include:: auto/oscillator.rst + diff --git a/rtl/test/test_pipelined_adder.vhdl b/rtl/test/test_pipelined_adder.vhdl new file mode 100644 index 0000000..01c4c08 --- /dev/null +++ b/rtl/test/test_pipelined_adder.vhdl @@ -0,0 +1,87 @@ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library extras; +use extras.arithmetic.all; +use extras.timing_ops.all; +use extras.sizing.bit_size; + +entity test_pipelined_adder is +end entity; + +architecture sim of test_pipelined_adder is + constant SYS_CLOCK_FREQ : frequency := 50 MHz; + constant SYS_CLOCK_PERIOD : delay_length := to_period(SYS_CLOCK_FREQ); + + signal clock, reset : std_ulogic; + signal done : boolean := false; + + constant WORD_SIZE : positive := 13; + signal a, const : unsigned(WORD_SIZE-1 downto 0); + signal sum : unsigned(WORD_SIZE downto 0); + + constant SLICES : positive := 1; +begin + + stim: process + begin + a <= (others => '0'); + const <= (others => '0'); + + reset <= '1', '0' after SYS_CLOCK_PERIOD * 4; + + wait until reset = '0'; + wait until falling_edge(clock); + + a <= to_unsigned(33, a'length); + const <= to_unsigned(10, const'length); + + wait for SYS_CLOCK_PERIOD * SLICES; + a <= to_unsigned(254, a'length); + const <= to_unsigned(1, const'length); + + wait for SYS_CLOCK_PERIOD * SLICES; + a <= to_unsigned(255, a'length); + --const <= to_unsigned(1, const'length); + + wait for SYS_CLOCK_PERIOD; + a <= to_unsigned(15, a'length); + --const <= to_unsigned(1, const'length); + + wait for SYS_CLOCK_PERIOD; + a <= to_unsigned(2**WORD_SIZE - 10, a'length); + + wait for SYS_CLOCK_PERIOD; + a <= to_unsigned(200, a'length); + const <= to_unsigned(300, a'length); + + + wait for SYS_CLOCK_PERIOD * 30; + + done <= true; + end process; + + pa: pipelined_adder + generic map ( + SLICES => SLICES, + CONST_B_INPUT => false + ) + port map ( + Clock => clock, + Reset => reset, + + A => a, + B => const, + + Sum => sum + ); + + sys_clock_gen: process + begin + clock_gen(clock, done, SYS_CLOCK_FREQ); + wait; + end process; + +end architecture;