From 7f344f45e6379c2a0e0fd3b43d0e1b32b24c781a Mon Sep 17 00:00:00 2001 From: Kevin Thibedeau Date: Thu, 28 Jun 2018 23:40:05 -0400 Subject: [PATCH] Add bit_ops and filtering packages --- doc/rst/modules/auto/arithmetic.rst | 44 +- doc/rst/modules/auto/bcd_conversion.rst | 2 +- doc/rst/modules/auto/binaryio.rst | 2 +- doc/rst/modules/auto/bit_ops.rst | 2 +- doc/rst/modules/auto/characters_handling.rst | 2 +- doc/rst/modules/auto/characters_latin_1.rst | 2 +- doc/rst/modules/auto/common_2008.rst | 2 +- doc/rst/modules/auto/cordic.rst | 2 +- doc/rst/modules/auto/crc_ops.rst | 4 +- doc/rst/modules/auto/ddfs.rst | 2 +- doc/rst/modules/auto/fifos.rst | 2 +- doc/rst/modules/auto/filtering.rst | 49 +- doc/rst/modules/auto/glitch_filtering.rst | 2 +- doc/rst/modules/auto/gray_code.rst | 2 +- doc/rst/modules/auto/hamming_edac.rst | 2 +- doc/rst/modules/auto/interrupt_ctl.rst | 2 +- doc/rst/modules/auto/lcar_ops.rst | 2 +- doc/rst/modules/auto/lfsr_ops.rst | 2 +- doc/rst/modules/auto/memory.rst | 2 +- doc/rst/modules/auto/muxing.rst | 2 +- doc/rst/modules/auto/muxing_2008.rst | 2 +- doc/rst/modules/auto/oscillator.rst | 2 +- doc/rst/modules/auto/parity_ops.rst | 2 +- doc/rst/modules/auto/pipelining.rst | 2 +- doc/rst/modules/auto/pipelining_2008.rst | 2 +- doc/rst/modules/auto/prng.rst | 2 +- doc/rst/modules/auto/random.rst | 2 +- doc/rst/modules/auto/random_20xx.rst | 2 +- doc/rst/modules/auto/reg_file.rst | 2 +- doc/rst/modules/auto/reg_file_2008.rst | 2 +- doc/rst/modules/auto/secded_codec.rst | 2 +- doc/rst/modules/auto/secded_edac.rst | 2 +- doc/rst/modules/auto/sizing.rst | 2 +- doc/rst/modules/auto/strings.rst | 2 +- doc/rst/modules/auto/strings_bounded.rst | 2 +- doc/rst/modules/auto/strings_fixed.rst | 2 +- doc/rst/modules/auto/strings_maps.rst | 2 +- .../modules/auto/strings_maps_constants.rst | 2 +- doc/rst/modules/auto/strings_unbounded.rst | 2 +- doc/rst/modules/auto/synchronizing.rst | 2 +- doc/rst/modules/auto/text_buffering.rst | 2 +- doc/rst/modules/auto/timing_ops.rst | 10 +- doc/rst/modules/auto/timing_ops_xilinx.rst | 2 +- doc/rst/modules/ddfs.rst | 1 + doc/rst/modules/filtering.rst | 4 +- doc/rst/modules/oscillator.rst | 13 +- rtl/extras/bit_ops.vhdl | 333 ++++++++ rtl/extras/ddfs.vhdl | 2 +- rtl/extras/timing_ops.vhdl | 8 +- rtl/extras_2008/filtering.vhdl | 765 ++++++++++++++++++ 50 files changed, 1168 insertions(+), 143 deletions(-) create mode 100644 rtl/extras/bit_ops.vhdl create mode 100644 rtl/extras_2008/filtering.vhdl diff --git a/doc/rst/modules/auto/arithmetic.rst b/doc/rst/modules/auto/arithmetic.rst index 883a2d9..fc32bba 100644 --- a/doc/rst/modules/auto/arithmetic.rst +++ b/doc/rst/modules/auto/arithmetic.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/arithmetic.vhdl on 2017-08-02 00:26:38.024403 +.. Generated from ../rtl/extras/arithmetic.vhdl on 2018-06-28 23:37:28.806720 .. vhdl:package:: extras.arithmetic @@ -6,48 +6,6 @@ Components ---------- -coloration_test -~~~~~~~~~~~~~~~ - -.. symbolator:: - :name: arithmetic-coloration_test - - component coloration_test is - port ( - --# {{aaa}} - aaa : in std_ulogic; - --# {{bbb}} - bbb : in std_ulogic; - --# {{ccc}} - ccc : out std_ulogic; - --# {{ddd}} - ddd : out std_ulogic; - --# {{eee}} - eee : inout std_ulogic; - --# {{fff}} - fff : in std_ulogic - ); - end component; - -| - - -.. vhdl:entity:: coloration_test - - - :port aaa: None - :ptype aaa: in std_ulogic - :port bbb: None - :ptype bbb: in std_ulogic - :port ccc: None - :ptype ccc: out std_ulogic - :port ddd: None - :ptype ddd: out std_ulogic - :port eee: None - :ptype eee: inout std_ulogic - :port fff: None - :ptype fff: in std_ulogic - pipelined_adder ~~~~~~~~~~~~~~~ diff --git a/doc/rst/modules/auto/bcd_conversion.rst b/doc/rst/modules/auto/bcd_conversion.rst index e9e9869..9888b89 100644 --- a/doc/rst/modules/auto/bcd_conversion.rst +++ b/doc/rst/modules/auto/bcd_conversion.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/bcd_conversion.vhdl on 2017-08-02 00:26:38.337644 +.. Generated from ../rtl/extras/bcd_conversion.vhdl on 2018-06-28 23:37:29.130821 .. vhdl:package:: extras.bcd_conversion diff --git a/doc/rst/modules/auto/binaryio.rst b/doc/rst/modules/auto/binaryio.rst index 71cac2e..b4057ee 100644 --- a/doc/rst/modules/auto/binaryio.rst +++ b/doc/rst/modules/auto/binaryio.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/binaryio.vhdl on 2017-08-02 00:26:37.681279 +.. Generated from ../rtl/extras/binaryio.vhdl on 2018-06-28 23:37:28.459290 .. vhdl:package:: extras.binaryio diff --git a/doc/rst/modules/auto/bit_ops.rst b/doc/rst/modules/auto/bit_ops.rst index 6f0103e..8add62d 100644 --- a/doc/rst/modules/auto/bit_ops.rst +++ b/doc/rst/modules/auto/bit_ops.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/bit_ops.vhdl on 2017-08-02 00:26:38.213920 +.. Generated from ../rtl/extras/bit_ops.vhdl on 2018-06-28 23:37:29.004041 .. vhdl:package:: extras.bit_ops diff --git a/doc/rst/modules/auto/characters_handling.rst b/doc/rst/modules/auto/characters_handling.rst index c895511..bf95f70 100644 --- a/doc/rst/modules/auto/characters_handling.rst +++ b/doc/rst/modules/auto/characters_handling.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/characters_handling.vhdl on 2017-08-02 00:26:38.250604 +.. Generated from ../rtl/extras/characters_handling.vhdl on 2018-06-28 23:37:29.041308 .. vhdl:package:: extras.characters_handling diff --git a/doc/rst/modules/auto/characters_latin_1.rst b/doc/rst/modules/auto/characters_latin_1.rst index 9fbb5a8..a9ed6ff 100644 --- a/doc/rst/modules/auto/characters_latin_1.rst +++ b/doc/rst/modules/auto/characters_latin_1.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/characters_latin_1.vhdl on 2017-08-02 00:26:38.364290 +.. Generated from ../rtl/extras/characters_latin_1.vhdl on 2018-06-28 23:37:29.157809 .. vhdl:package:: extras.characters_latin_1 diff --git a/doc/rst/modules/auto/common_2008.rst b/doc/rst/modules/auto/common_2008.rst index 89066bd..7a50eff 100644 --- a/doc/rst/modules/auto/common_2008.rst +++ b/doc/rst/modules/auto/common_2008.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras_2008/common_2008.vhdl on 2017-08-02 00:26:38.887626 +.. Generated from ../rtl/extras_2008/common_2008.vhdl on 2018-06-28 23:37:30.056215 .. vhdl:package:: extras_2008.common diff --git a/doc/rst/modules/auto/cordic.rst b/doc/rst/modules/auto/cordic.rst index bd87e89..c5da149 100644 --- a/doc/rst/modules/auto/cordic.rst +++ b/doc/rst/modules/auto/cordic.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/cordic.vhdl on 2017-08-02 00:26:37.839517 +.. Generated from ../rtl/extras/cordic.vhdl on 2018-06-28 23:37:28.609517 .. vhdl:package:: extras.cordic diff --git a/doc/rst/modules/auto/crc_ops.rst b/doc/rst/modules/auto/crc_ops.rst index 16d4455..261d892 100644 --- a/doc/rst/modules/auto/crc_ops.rst +++ b/doc/rst/modules/auto/crc_ops.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/crc_ops.vhdl on 2017-08-02 00:26:38.383136 +.. Generated from ../rtl/extras/crc_ops.vhdl on 2018-06-28 23:37:29.176993 .. vhdl:package:: extras.crc_ops @@ -103,7 +103,7 @@ Subprograms :param Crc: Current CRC state :type Crc: bit_vector - :param Reflect_out: Reverse bits of result wien true + :param Reflect_out: Reverse bits of result when true :type Reflect_out: boolean :param Xor_out: Apply XOR to final state (inversion) :type Xor_out: bit_vector diff --git a/doc/rst/modules/auto/ddfs.rst b/doc/rst/modules/auto/ddfs.rst index a024404..cf590e2 100644 --- a/doc/rst/modules/auto/ddfs.rst +++ b/doc/rst/modules/auto/ddfs.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/ddfs.vhdl on 2017-08-02 00:26:38.071989 +.. Generated from ../rtl/extras/ddfs.vhdl on 2018-06-28 23:37:28.856560 .. vhdl:package:: extras.ddfs_pkg diff --git a/doc/rst/modules/auto/fifos.rst b/doc/rst/modules/auto/fifos.rst index 07883e8..3aa8e11 100644 --- a/doc/rst/modules/auto/fifos.rst +++ b/doc/rst/modules/auto/fifos.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/fifos.vhdl on 2017-08-02 00:26:37.750141 +.. Generated from ../rtl/extras/fifos.vhdl on 2018-06-28 23:37:28.517436 .. vhdl:package:: extras.fifos diff --git a/doc/rst/modules/auto/filtering.rst b/doc/rst/modules/auto/filtering.rst index 0313ede..a01589b 100644 --- a/doc/rst/modules/auto/filtering.rst +++ b/doc/rst/modules/auto/filtering.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras_2008/filtering.vhdl on 2017-08-02 00:26:38.757514 +.. Generated from ../rtl/extras_2008/filtering.vhdl on 2018-06-28 23:37:29.915180 .. vhdl:package:: extras_2008.filtering @@ -24,51 +24,6 @@ fir_filter generic ( RESET_ACTIVE_LEVEL : std_ulogic ); - port ( - --# {{clocks|}} - Clock : in std_ulogic; - Reset : in std_ulogic; - --# {{control|}} - Coefficients : in signed_array; - --# {{data|}} - New_data : in std_ulogic; - Data_in : in signed; - Data_out : out signed - ); - end component; - -| - - -.. vhdl:entity:: fir_filter - - - :generic RESET_ACTIVE_LEVEL: Asynch. reset control level - :gtype RESET_ACTIVE_LEVEL: std_ulogic - - :port Clock: None - :ptype Clock: in std_ulogic - :port Reset: None - :ptype Reset: in std_ulogic - :port Coefficients: None - :ptype Coefficients: in signed_array - :port New_data: None - :ptype New_data: in std_ulogic - :port Data_in: None - :ptype Data_in: in signed - :port Data_out: None - :ptype Data_out: out signed - -fir_filter_2 -~~~~~~~~~~~~ - -.. symbolator:: - :name: filtering-fir_filter_2 - - component fir_filter_2 is - generic ( - RESET_ACTIVE_LEVEL : std_ulogic - ); port ( --# {{clocks|}} Clock : in std_ulogic; @@ -89,7 +44,7 @@ fir_filter_2 | -.. vhdl:entity:: fir_filter_2 +.. vhdl:entity:: fir_filter Finite Impulse Response filter. diff --git a/doc/rst/modules/auto/glitch_filtering.rst b/doc/rst/modules/auto/glitch_filtering.rst index 4806d4c..e00bce4 100644 --- a/doc/rst/modules/auto/glitch_filtering.rst +++ b/doc/rst/modules/auto/glitch_filtering.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/glitch_filtering.vhdl on 2017-08-02 00:26:37.888949 +.. Generated from ../rtl/extras/glitch_filtering.vhdl on 2018-06-28 23:37:28.660046 .. vhdl:package:: extras.glitch_filtering diff --git a/doc/rst/modules/auto/gray_code.rst b/doc/rst/modules/auto/gray_code.rst index d9aee8a..fa0c59f 100644 --- a/doc/rst/modules/auto/gray_code.rst +++ b/doc/rst/modules/auto/gray_code.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/gray_code.vhdl on 2017-08-02 00:26:38.404926 +.. Generated from ../rtl/extras/gray_code.vhdl on 2018-06-28 23:37:29.198622 .. vhdl:package:: extras.gray_code diff --git a/doc/rst/modules/auto/hamming_edac.rst b/doc/rst/modules/auto/hamming_edac.rst index 18a4072..585ba35 100644 --- a/doc/rst/modules/auto/hamming_edac.rst +++ b/doc/rst/modules/auto/hamming_edac.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/hamming_edac.vhdl on 2017-08-02 00:26:38.109685 +.. Generated from ../rtl/extras/hamming_edac.vhdl on 2018-06-28 23:37:28.895194 .. vhdl:package:: extras.hamming_edac diff --git a/doc/rst/modules/auto/interrupt_ctl.rst b/doc/rst/modules/auto/interrupt_ctl.rst index ff95c95..ed5d8be 100644 --- a/doc/rst/modules/auto/interrupt_ctl.rst +++ b/doc/rst/modules/auto/interrupt_ctl.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/interrupt_ctl.vhdl on 2017-08-02 00:26:38.372356 +.. Generated from ../rtl/extras/interrupt_ctl.vhdl on 2018-06-28 23:37:29.166059 .. vhdl:package:: extras.interrupt_ctl_pkg diff --git a/doc/rst/modules/auto/lcar_ops.rst b/doc/rst/modules/auto/lcar_ops.rst index b4512fb..15c0e64 100644 --- a/doc/rst/modules/auto/lcar_ops.rst +++ b/doc/rst/modules/auto/lcar_ops.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/lcar_ops.vhdl on 2017-08-02 00:26:37.714580 +.. Generated from ../rtl/extras/lcar_ops.vhdl on 2018-06-28 23:37:28.480199 .. vhdl:package:: extras.lcar_ops diff --git a/doc/rst/modules/auto/lfsr_ops.rst b/doc/rst/modules/auto/lfsr_ops.rst index 83dab55..74347c8 100644 --- a/doc/rst/modules/auto/lfsr_ops.rst +++ b/doc/rst/modules/auto/lfsr_ops.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/lfsr_ops.vhdl on 2017-08-02 00:26:38.181267 +.. Generated from ../rtl/extras/lfsr_ops.vhdl on 2018-06-28 23:37:28.970293 .. vhdl:package:: extras.lfsr_ops diff --git a/doc/rst/modules/auto/memory.rst b/doc/rst/modules/auto/memory.rst index 6024419..67e3551 100644 --- a/doc/rst/modules/auto/memory.rst +++ b/doc/rst/modules/auto/memory.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/memory.vhdl on 2017-08-02 00:26:38.082354 +.. Generated from ../rtl/extras/memory.vhdl on 2018-06-28 23:37:28.866907 .. vhdl:package:: extras.memory diff --git a/doc/rst/modules/auto/muxing.rst b/doc/rst/modules/auto/muxing.rst index 67fc8fa..0374f71 100644 --- a/doc/rst/modules/auto/muxing.rst +++ b/doc/rst/modules/auto/muxing.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/muxing.vhdl on 2017-08-02 00:26:38.393986 +.. Generated from ../rtl/extras/muxing.vhdl on 2018-06-28 23:37:29.187662 .. vhdl:package:: extras.muxing diff --git a/doc/rst/modules/auto/muxing_2008.rst b/doc/rst/modules/auto/muxing_2008.rst index 395c44d..9347fcd 100644 --- a/doc/rst/modules/auto/muxing_2008.rst +++ b/doc/rst/modules/auto/muxing_2008.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras_2008/muxing_2008.vhdl on 2017-08-02 00:26:38.900445 +.. Generated from ../rtl/extras_2008/muxing_2008.vhdl on 2018-06-28 23:37:30.069880 .. vhdl:package:: extras_2008.muxing diff --git a/doc/rst/modules/auto/oscillator.rst b/doc/rst/modules/auto/oscillator.rst index 905606c..fa423f0 100644 --- a/doc/rst/modules/auto/oscillator.rst +++ b/doc/rst/modules/auto/oscillator.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/oscillator.vhdl on 2017-08-02 00:26:37.934436 +.. Generated from ../rtl/extras/oscillator.vhdl on 2018-06-28 23:37:28.705068 .. vhdl:package:: extras.oscillator diff --git a/doc/rst/modules/auto/parity_ops.rst b/doc/rst/modules/auto/parity_ops.rst index b9923db..8f175ed 100644 --- a/doc/rst/modules/auto/parity_ops.rst +++ b/doc/rst/modules/auto/parity_ops.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/parity_ops.vhdl on 2017-08-02 00:26:37.672327 +.. Generated from ../rtl/extras/parity_ops.vhdl on 2018-06-28 23:37:28.450478 .. vhdl:package:: extras.parity_ops diff --git a/doc/rst/modules/auto/pipelining.rst b/doc/rst/modules/auto/pipelining.rst index 714e18d..e18157c 100644 --- a/doc/rst/modules/auto/pipelining.rst +++ b/doc/rst/modules/auto/pipelining.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/pipelining.vhdl on 2017-08-02 00:26:38.158752 +.. Generated from ../rtl/extras/pipelining.vhdl on 2018-06-28 23:37:28.946316 .. vhdl:package:: extras.pipelining diff --git a/doc/rst/modules/auto/pipelining_2008.rst b/doc/rst/modules/auto/pipelining_2008.rst index 945ebbc..3ef5a44 100644 --- a/doc/rst/modules/auto/pipelining_2008.rst +++ b/doc/rst/modules/auto/pipelining_2008.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras_2008/pipelining_2008.vhdl on 2017-08-02 00:26:38.904736 +.. Generated from ../rtl/extras_2008/pipelining_2008.vhdl on 2018-06-28 23:37:30.074654 .. vhdl:package:: extras_2008.pipelining diff --git a/doc/rst/modules/auto/prng.rst b/doc/rst/modules/auto/prng.rst index 25cf470..68c8813 100644 --- a/doc/rst/modules/auto/prng.rst +++ b/doc/rst/modules/auto/prng.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/prng.vhdl on 2017-08-02 00:26:37.903735 +.. Generated from ../rtl/extras/prng.vhdl on 2018-06-28 23:37:28.675257 .. vhdl:package:: extras.prng diff --git a/doc/rst/modules/auto/random.rst b/doc/rst/modules/auto/random.rst index 3cb0319..38d7470 100644 --- a/doc/rst/modules/auto/random.rst +++ b/doc/rst/modules/auto/random.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/random.vhdl on 2017-08-02 00:26:37.964770 +.. Generated from ../rtl/extras/random.vhdl on 2018-06-28 23:37:28.740908 .. vhdl:package:: extras.random diff --git a/doc/rst/modules/auto/random_20xx.rst b/doc/rst/modules/auto/random_20xx.rst index d6d56f1..7f35f67 100644 --- a/doc/rst/modules/auto/random_20xx.rst +++ b/doc/rst/modules/auto/random_20xx.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras_2008/random_20xx.vhdl on 2017-08-02 00:26:38.870427 +.. Generated from ../rtl/extras_2008/random_20xx.vhdl on 2018-06-28 23:37:30.037475 .. vhdl:package:: extras_2008.random diff --git a/doc/rst/modules/auto/reg_file.rst b/doc/rst/modules/auto/reg_file.rst index 8247c2f..05d6f7e 100644 --- a/doc/rst/modules/auto/reg_file.rst +++ b/doc/rst/modules/auto/reg_file.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/reg_file.vhdl on 2017-08-02 00:26:37.667782 +.. Generated from ../rtl/extras/reg_file.vhdl on 2018-06-28 23:37:28.444060 .. vhdl:package:: extras.reg_file_pkg diff --git a/doc/rst/modules/auto/reg_file_2008.rst b/doc/rst/modules/auto/reg_file_2008.rst index 2f72216..c9fbb66 100644 --- a/doc/rst/modules/auto/reg_file_2008.rst +++ b/doc/rst/modules/auto/reg_file_2008.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras_2008/reg_file_2008.vhdl on 2017-08-02 00:26:38.914305 +.. Generated from ../rtl/extras_2008/reg_file_2008.vhdl on 2018-06-28 23:37:30.084771 .. vhdl:package:: extras_2008.reg_file_pkg diff --git a/doc/rst/modules/auto/secded_codec.rst b/doc/rst/modules/auto/secded_codec.rst index f74aaf7..c82d894 100644 --- a/doc/rst/modules/auto/secded_codec.rst +++ b/doc/rst/modules/auto/secded_codec.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/secded_codec.vhdl on 2017-08-02 00:26:37.981619 +.. Generated from ../rtl/extras/secded_codec.vhdl on 2018-06-28 23:37:28.760142 .. vhdl:package:: extras.secded_codec_pkg diff --git a/doc/rst/modules/auto/secded_edac.rst b/doc/rst/modules/auto/secded_edac.rst index 1754ea6..252ef97 100644 --- a/doc/rst/modules/auto/secded_edac.rst +++ b/doc/rst/modules/auto/secded_edac.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/secded_edac.vhdl on 2017-08-02 00:26:37.947544 +.. Generated from ../rtl/extras/secded_edac.vhdl on 2018-06-28 23:37:28.719963 .. vhdl:package:: extras.secded_edac diff --git a/doc/rst/modules/auto/sizing.rst b/doc/rst/modules/auto/sizing.rst index aa35deb..f70c3e5 100644 --- a/doc/rst/modules/auto/sizing.rst +++ b/doc/rst/modules/auto/sizing.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/sizing.vhdl on 2017-08-02 00:26:37.955897 +.. Generated from ../rtl/extras/sizing.vhdl on 2018-06-28 23:37:28.729892 .. vhdl:package:: extras.sizing diff --git a/doc/rst/modules/auto/strings.rst b/doc/rst/modules/auto/strings.rst index 417e3d1..6004dcc 100644 --- a/doc/rst/modules/auto/strings.rst +++ b/doc/rst/modules/auto/strings.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/strings.vhdl on 2017-08-02 00:26:38.406926 +.. Generated from ../rtl/extras/strings.vhdl on 2018-06-28 23:37:29.201044 .. vhdl:package:: extras.strings diff --git a/doc/rst/modules/auto/strings_bounded.rst b/doc/rst/modules/auto/strings_bounded.rst index 5f0b116..bfcc1a2 100644 --- a/doc/rst/modules/auto/strings_bounded.rst +++ b/doc/rst/modules/auto/strings_bounded.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras_2008/strings_bounded.vhdl on 2017-08-02 00:26:38.860177 +.. Generated from ../rtl/extras_2008/strings_bounded.vhdl on 2018-06-28 23:37:30.027279 .. vhdl:package:: extras_2008.strings_bounded diff --git a/doc/rst/modules/auto/strings_fixed.rst b/doc/rst/modules/auto/strings_fixed.rst index 278f500..d19bc05 100644 --- a/doc/rst/modules/auto/strings_fixed.rst +++ b/doc/rst/modules/auto/strings_fixed.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/strings_fixed.vhdl on 2017-08-02 00:26:37.797249 +.. Generated from ../rtl/extras/strings_fixed.vhdl on 2018-06-28 23:37:28.566470 .. vhdl:package:: extras.strings_fixed diff --git a/doc/rst/modules/auto/strings_maps.rst b/doc/rst/modules/auto/strings_maps.rst index c600321..0872c5c 100644 --- a/doc/rst/modules/auto/strings_maps.rst +++ b/doc/rst/modules/auto/strings_maps.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/strings_maps.vhdl on 2017-08-02 00:26:38.200781 +.. Generated from ../rtl/extras/strings_maps.vhdl on 2018-06-28 23:37:28.990407 .. vhdl:package:: extras.strings_maps diff --git a/doc/rst/modules/auto/strings_maps_constants.rst b/doc/rst/modules/auto/strings_maps_constants.rst index a9ba88e..dc4a61e 100644 --- a/doc/rst/modules/auto/strings_maps_constants.rst +++ b/doc/rst/modules/auto/strings_maps_constants.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/strings_maps_constants.vhdl on 2017-08-02 00:26:38.315587 +.. Generated from ../rtl/extras/strings_maps_constants.vhdl on 2018-06-28 23:37:29.109320 .. vhdl:package:: extras.strings_maps_constants diff --git a/doc/rst/modules/auto/strings_unbounded.rst b/doc/rst/modules/auto/strings_unbounded.rst index d939afd..70b012e 100644 --- a/doc/rst/modules/auto/strings_unbounded.rst +++ b/doc/rst/modules/auto/strings_unbounded.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/strings_unbounded.vhdl on 2017-08-02 00:26:37.872868 +.. Generated from ../rtl/extras/strings_unbounded.vhdl on 2018-06-28 23:37:28.643702 .. vhdl:package:: extras.strings_unbounded diff --git a/doc/rst/modules/auto/synchronizing.rst b/doc/rst/modules/auto/synchronizing.rst index 0370784..369c7ab 100644 --- a/doc/rst/modules/auto/synchronizing.rst +++ b/doc/rst/modules/auto/synchronizing.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/synchronizing.vhdl on 2017-08-02 00:26:38.123486 +.. Generated from ../rtl/extras/synchronizing.vhdl on 2018-06-28 23:37:28.909058 .. vhdl:package:: extras.synchronizing diff --git a/doc/rst/modules/auto/text_buffering.rst b/doc/rst/modules/auto/text_buffering.rst index 1da8dfa..a03f93b 100644 --- a/doc/rst/modules/auto/text_buffering.rst +++ b/doc/rst/modules/auto/text_buffering.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/text_buffering.vhdl on 2017-08-02 00:26:38.231382 +.. Generated from ../rtl/extras/text_buffering.vhdl on 2018-06-28 23:37:29.021524 .. vhdl:package:: extras.text_buffering diff --git a/doc/rst/modules/auto/timing_ops.rst b/doc/rst/modules/auto/timing_ops.rst index d6749a3..7c99c62 100644 --- a/doc/rst/modules/auto/timing_ops.rst +++ b/doc/rst/modules/auto/timing_ops.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/timing_ops.vhdl on 2017-08-02 00:26:38.013241 +.. Generated from ../rtl/extras/timing_ops.vhdl on 2018-06-28 23:37:28.795715 .. vhdl:package:: extras.timing_ops @@ -330,7 +330,7 @@ Subprograms :type Actual_secs: in time -.. vhdl:procedure:: procedure clock_gen(Clock : out std_ulogic; Stop_clock : in boolean; Clock_freq : in frequency; Duty : duty_cycle := 0.5); +.. vhdl:procedure:: procedure clock_gen(Clock : out std_ulogic; Stop_clock : in boolean; Clock_freq : in frequency; Duty : in duty_cycle := 0.5); Generate clock waveform for simulation only. @@ -341,10 +341,10 @@ Subprograms :param Clock_freq: Frequency of the generated clock :type Clock_freq: in frequency :param Duty: Optional duty cycle of the generated clock (0.0 to 1.0) - :type Duty: None duty_cycle + :type Duty: in duty_cycle -.. vhdl:procedure:: procedure clock_gen(Clock : out std_ulogic; Stop_clock : in boolean; Clock_period : in delay_length; Duty : duty_cycle := 0.5); +.. vhdl:procedure:: procedure clock_gen(Clock : out std_ulogic; Stop_clock : in boolean; Clock_period : in delay_length; Duty : in duty_cycle := 0.5); Generate clock waveform for simulation only. @@ -355,5 +355,5 @@ Subprograms :param Clock_period: Period of the generated clock :type Clock_period: in delay_length :param Duty: Optional duty cycle of the generated clock (0.0 to 1.0) - :type Duty: None duty_cycle + :type Duty: in duty_cycle diff --git a/doc/rst/modules/auto/timing_ops_xilinx.rst b/doc/rst/modules/auto/timing_ops_xilinx.rst index 5904a83..f27e6c6 100644 --- a/doc/rst/modules/auto/timing_ops_xilinx.rst +++ b/doc/rst/modules/auto/timing_ops_xilinx.rst @@ -1,4 +1,4 @@ -.. Generated from ../rtl/extras/timing_ops_xilinx.vhdl on 2017-08-02 00:26:38.039828 +.. Generated from ../rtl/extras/timing_ops_xilinx.vhdl on 2018-06-28 23:37:28.823301 .. vhdl:package:: extras.timing_ops diff --git a/doc/rst/modules/ddfs.rst b/doc/rst/modules/ddfs.rst index edc33fa..aa61201 100644 --- a/doc/rst/modules/ddfs.rst +++ b/doc/rst/modules/ddfs.rst @@ -9,6 +9,7 @@ Dependencies ------------ :doc:`sizing` +:doc:`arithmetic` Description ----------- diff --git a/doc/rst/modules/filtering.rst b/doc/rst/modules/filtering.rst index 5dd0fb9..880666b 100644 --- a/doc/rst/modules/filtering.rst +++ b/doc/rst/modules/filtering.rst @@ -10,17 +10,19 @@ Dependencies ------------ :doc:`common_2008` +:doc:`pipelining_2008 ` Description ----------- +This package implements general purpose digital filters. Example usage ~~~~~~~~~~~~~ .. code-block:: vhdl - + TODO .. include:: auto/filtering.rst diff --git a/doc/rst/modules/oscillator.rst b/doc/rst/modules/oscillator.rst index fd815cc..2c72552 100644 --- a/doc/rst/modules/oscillator.rst +++ b/doc/rst/modules/oscillator.rst @@ -16,13 +16,24 @@ Dependencies Description ----------- +This package provides a set of components that implement arbitrary +sinusoidal frequency generators. They come in two variants. One generates +a fixed frequency that is specified at elaboration time as a generic +parameter. The other generates a dynamic frequency that can be altered +at run time. Each of these oscillator variants comes in two versions. One +is based around a pipelined CORDIC unit that produces new valid output on +every clock cycle. The other uses a more compact sequential CORDIC +implementation that takes multiple clock cycles to produce each output. + +All oscillators output sine, cosine, the current phase angle, and a generated +clock at the target frequency. Example usage ~~~~~~~~~~~~~ .. code-block:: vhdl - + TODO .. include:: auto/oscillator.rst diff --git a/rtl/extras/bit_ops.vhdl b/rtl/extras/bit_ops.vhdl new file mode 100644 index 0000000..42d0afc --- /dev/null +++ b/rtl/extras/bit_ops.vhdl @@ -0,0 +1,333 @@ +-------------------------------------------------------------------- +-- _ __ __ __ ____ __ = -- +-- | | / // / / // __ \ / / = -- +-- | | / // /_/ // / / // / = .__ |/ _/_ .__ .__ __ -- +-- | |/ // __ // /_/ // /___ = /___) | / / ) / ) (_ ` -- +-- |___//_/ /_//_____//_____/ = (___ /| (_ / (___(_ (__) -- +-- ===== / -- +-- === -- +----------------------------- = ---------------------------------- +--# bit_ops.vhdl - Bitwise operations +--# Freely available from VHDL-extras (http://github.com/kevinpt/vhdl-extras) +--# +--# Copyright © 2017 Kevin Thibedeau +--# (kevin 'period' thibedeau 'at' gmail 'punto' com) +--# +--# Permission is hereby granted, free of charge, to any person obtaining a +--# copy of this software and associated documentation files (the "Software"), +--# to deal in the Software without restriction, including without limitation +--# the rights to use, copy, modify, merge, publish, distribute, sublicense, +--# and/or sell copies of the Software, and to permit persons to whom the +--# Software is furnished to do so, subject to the following conditions: +--# +--# The above copyright notice and this permission notice shall be included in +--# all copies or substantial portions of the Software. +--# +--# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +--# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +--# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +--# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +--# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +--# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +--# DEALINGS IN THE SOFTWARE. +--# +--# DEPENDENCIES: sizing +--# +--# DESCRIPTION: +--# This package provides components that count the number of set bits in a +--# vector. Multiple implementations are available with different performance +--# characteristics. +--# +--# EXAMPLE USAGE: +--# +--# signal value : unsigned(11 downto 0); +--# signal ones_count : unsigned(bit_size(value'length)-1 downto 0); +--# +--# -- Basic combinational circuit: +--# basic: count_ones +--# port map ( +--# Value => value, +--# Ones_count => ones_count +--# ); +--# +--# -- Chunked combinational circuit: +--# basic: count_ones_chunked +--# generic map ( +--# TABLE_BITS => 4 -- Constant table with 16 entries +--# ) +--# port map ( +--# Value => value, +--# Ones_count => ones_count +--# ); +--# +--# -- Chunked sequential circuit: +--# basic: count_ones_sequential +--# generic map ( +--# TABLE_BITS => 4 -- Constant table with 16 entries +--# ) +--# port map ( +--# Clock => clock, +--# Reset => reset, +--# +--# Start => start, +--# Busy => busy, +--# Done => done, +--# +--# Value => value, +--# Ones_count => ones_count +--# ); +-------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library extras; +use extras.sizing.bit_size; + + +package bit_ops is + + --# Vector of natural numbers. + type natural_vector is array(natural range <>) of natural; + + --## Create a precomputed table of bit counts. + --# Args: + --# Size : Number of bits in vector + --# Returns: + --# Array of bit count values with 2**Size entries. + function gen_count_ones_table( Size : positive ) return natural_vector; + + + --# Count the number of set bits in a vector. + component count_ones is + port ( + --# {{data|}} + Value : in unsigned; --# Vector to count set bits + Ones_count : out unsigned --# Number of set bits in ``Value`` + ); + end component; + + + --# Count the number of set bits in a vector with a reduced constant table. + component count_ones_chunked is + generic ( + TABLE_BITS : positive --# Number of bits for constant table + ); + port ( + --# {{data|}} + Value : in unsigned; --# Vector to count set bits + Ones_count : out unsigned --# Number of set bits in ``Value`` + ); + end component; + + --# Count the number of set bits in a vector with a reduced constant table. + component count_ones_sequential is + generic ( + TABLE_BITS : positive; --# Number of bits for constant table + RESET_ACTIVE_LEVEL : std_ulogic := '1' --# Asynch. reset control level + ); + port ( + --# {{clocks|}} + Clock : in std_ulogic; --# System clock + Reset : in std_ulogic; --# Asynchronous reset + + --# {{control|}} + Start : in std_ulogic; --# Start counting + Busy : out std_ulogic; --# Count is in progress + Done : out std_ulogic; --# Count is done + + --# {{data|}} + Value : in unsigned; --# Vector to count set bits + Ones_count : out unsigned --# Number of set bits in ``Value`` + ); + end component; + +end package; + +package body bit_ops is + + function gen_count_ones_table( Size : positive ) return natural_vector is + + function count_ones(v : unsigned) return natural is + variable cnt : natural := 0; + begin + for i in v'range loop + if v(i) = '1' then + cnt := cnt + 1; + end if; + end loop; + + return cnt; + end function; + + variable table : natural_vector(0 to 2**Size-1); + begin + assert Size <= bit_size(integer'high) + report "Size is too large. Max is " & integer'image(bit_size(integer'high)) + severity failure; + + for i in table'range loop + table(i) := count_ones(to_unsigned(i, Size)); + end loop; + + return table; + end function; + +end package body; + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library extras; +use extras.bit_ops.all; + +entity count_ones is + port ( + Value : in unsigned; + Ones_count : out unsigned + ); +end entity; + +architecture rtl of count_ones is + constant ONES_TABLE : natural_vector := gen_count_ones_table(Value'length); +begin + + Ones_count <= to_unsigned(ONES_TABLE(to_integer(Value)), Ones_count'length); + +end architecture; + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library extras; +use extras.bit_ops.all; + +entity count_ones_chunked is + generic ( + TABLE_BITS : positive + ); + port ( + Value : in unsigned; + Ones_count : out unsigned + ); +end entity; + +architecture rtl of count_ones_chunked is + constant ONES_TABLE : natural_vector := gen_count_ones_table(TABLE_BITS); + + constant PIECES : natural := (Value'length + TABLE_BITS - 1) / TABLE_BITS; + signal expanded : unsigned(PIECES*TABLE_BITS - 1 downto 0); + +begin + + expanded <= resize(Value, expanded'length); + + counter: process(expanded) is + variable slice : unsigned(TABLE_BITS-1 downto 0); + variable count : unsigned(Ones_count'length-1 downto 0); + begin + count := (others => '0'); + + for i in 0 to PIECES-1 loop + slice := expanded((i+1)*TABLE_BITS-1 downto i*TABLE_BITS); + count := count + ONES_TABLE(to_integer(slice)); + end loop; + + Ones_count <= count; + end process; + +end architecture; + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library extras; +use extras.bit_ops.all; +use extras.sizing.bit_size; + +entity count_ones_sequential is + generic ( + TABLE_BITS : positive; + RESET_ACTIVE_LEVEL : std_ulogic := '1' + ); + port ( + Clock : in std_ulogic; + Reset : in std_ulogic; + + Start : in std_ulogic; + Busy : out std_ulogic; + Done : out std_ulogic; + + Value : in unsigned; + Ones_count : out unsigned + ); +end entity; + +architecture rtl of count_ones_sequential is + constant ONES_TABLE : natural_vector := gen_count_ones_table(TABLE_BITS); + + constant PIECES : natural := (Value'length + TABLE_BITS - 1) / TABLE_BITS; + signal expanded : unsigned(PIECES*TABLE_BITS - 1 downto 0); + --signal slice : unsigned(TABLE_BITS-1 downto 0); + + subtype slice is unsigned(TABLE_BITS-1 downto 0); + type slice_vec is array(natural range <>) of slice; + signal slices : slice_vec(PIECES-1 downto 0); + --signal slices : unsigned(PIECES-1 downto 0)(TABLE_BITS-1 downto 0); + + signal counting : std_ulogic; + signal count : unsigned(Ones_count'length-1 downto 0); + + --subtype piece_index is integer range 0 to PIECES-1; + --signal ix : piece_index; + + signal ix : unsigned(bit_size(PIECES)-1 downto 0); + +begin + + expanded <= resize(Value, expanded'length); + --slice <= expanded((ix+1)*TABLE_BITS-1 downto ix*TABLE_BITS); + + sg: for i in 0 to PIECES-1 generate + slices(i) <= expanded((i+1)*TABLE_BITS-1 downto i*TABLE_BITS); + end generate; + + counter: process(Clock, Reset) is + begin + if Reset = RESET_ACTIVE_LEVEL then + Busy <= '0'; + counting <= '0'; + count <= (others => '0'); + ix <= (others => '0'); + elsif rising_edge(Clock) then + Busy <= '0'; + + if Start = '1' then -- Start counting down through the pieces + Busy <= '1'; + counting <= '1'; + count <= (others => '0'); + ix <= to_unsigned(PIECES-1, ix'length); + elsif counting = '1' then + Busy <= '1'; + count <= count + ONES_TABLE(to_integer(slices(to_integer(ix)))); + ix <= ix - 1; + end if; + + if ix = 0 then + counting <= '0'; + end if; + end if; + end process; + + Done <= '1' when ix = 0 else '0'; + Ones_count <= count; + +end architecture; + diff --git a/rtl/extras/ddfs.vhdl b/rtl/extras/ddfs.vhdl index 07b9225..8c134d1 100644 --- a/rtl/extras/ddfs.vhdl +++ b/rtl/extras/ddfs.vhdl @@ -31,7 +31,7 @@ --# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER --# DEALINGS IN THE SOFTWARE. --# ---# DEPENDENCIES: sizing +--# DEPENDENCIES: sizing arithmetic --# --# DESCRIPTION: --# This package provides a set of functions and a component used for diff --git a/rtl/extras/timing_ops.vhdl b/rtl/extras/timing_ops.vhdl index 70b36d7..7cb65f4 100644 --- a/rtl/extras/timing_ops.vhdl +++ b/rtl/extras/timing_ops.vhdl @@ -324,7 +324,7 @@ package timing_ops is --# Clock_freq: Frequency of the generated clock --# Duty : Optional duty cycle of the generated clock (0.0 to 1.0) procedure clock_gen( signal Clock : out std_ulogic; signal Stop_clock : in boolean; - constant Clock_freq : in frequency; constant Duty : duty_cycle := 0.5 ); + constant Clock_freq : in frequency; constant Duty : in duty_cycle := 0.5 ); --## Generate clock waveform for simulation only. --# Args: @@ -333,7 +333,7 @@ package timing_ops is --# Clock_period: Period of the generated clock --# Duty : Optional duty cycle of the generated clock (0.0 to 1.0) procedure clock_gen( signal Clock : out std_ulogic; signal Stop_clock : in boolean; - constant Clock_period : in delay_length; constant Duty : duty_cycle := 0.5 ); + constant Clock_period : in delay_length; constant Duty : in duty_cycle := 0.5 ); end package; @@ -583,7 +583,7 @@ package body timing_ops is --# Clock_freq: the frequency of the clock --# Duty : duty cycle of the generated clock from 0.0 to 1.0 procedure clock_gen( signal Clock : out std_ulogic; signal Stop_clock : in boolean; - constant Clock_freq : in frequency; constant Duty : duty_cycle := 0.5 ) is + constant Clock_freq : in frequency; constant Duty : in duty_cycle := 0.5 ) is constant PERIOD : delay_length := to_period(Clock_freq); constant HIGH_TIME : delay_length := PERIOD * Duty; @@ -601,7 +601,7 @@ package body timing_ops is --## Same as above with Clock_period replacing Clock_freq procedure clock_gen( signal Clock : out std_ulogic; signal Stop_clock : in boolean; - constant Clock_period : in delay_length; constant Duty : duty_cycle := 0.5 ) is + constant Clock_period : in delay_length; constant Duty : in duty_cycle := 0.5 ) is constant HIGH_TIME : delay_length := Clock_period * Duty; constant LOW_TIME : delay_length := Clock_period - HIGH_TIME; diff --git a/rtl/extras_2008/filtering.vhdl b/rtl/extras_2008/filtering.vhdl new file mode 100644 index 0000000..76c1db4 --- /dev/null +++ b/rtl/extras_2008/filtering.vhdl @@ -0,0 +1,765 @@ +-------------------------------------------------------------------- +-- _ __ __ __ ____ __ = -- +-- | | / // / / // __ \ / / = -- +-- | | / // /_/ // / / // / = .__ |/ _/_ .__ .__ __ -- +-- | |/ // __ // /_/ // /___ = /___) | / / ) / ) (_ ` -- +-- |___//_/ /_//_____//_____/ = (___ /| (_ / (___(_ (__) -- +-- ===== / -- +-- === -- +----------------------------- = ---------------------------------- +--# filtering.vhdl - Digital filters +--# Freely available from VHDL-extras (http://github.com/kevinpt/vhdl-extras) +--# +--# Copyright © 2017 Kevin Thibedeau +--# (kevin 'period' thibedeau 'at' gmail 'punto' com) +--# +--# Permission is hereby granted, free of charge, to any person obtaining a +--# copy of this software and associated documentation files (the "Software"), +--# to deal in the Software without restriction, including without limitation +--# the rights to use, copy, modify, merge, publish, distribute, sublicense, +--# and/or sell copies of the Software, and to permit persons to whom the +--# Software is furnished to do so, subject to the following conditions: +--# +--# The above copyright notice and this permission notice shall be included in +--# all copies or substantial portions of the Software. +--# +--# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +--# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +--# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +--# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +--# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +--# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +--# DEALINGS IN THE SOFTWARE. +--# +--# DEPENDENCIES: common_2008 pipelining_2008 +--# +--# DESCRIPTION: +--# This package implements general purpose digital filters. +--# +--# EXAMPLE USAGE: +-------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library extras_2008; +use extras_2008.common.all; + +package filtering is + + --# Attenuation gain from 0.0 to 1.0. + subtype attenuation_factor is real range 0.0 to 1.0; + + --## Convert attenuation factor into a signed factor + --# Args: + --# Factor: Factor for gain value + --# Size: Number of bits in the result + --# Returns: + --# Signed value representing the Factor scaled to the range of Size. + function attenuation_gain(Factor : attenuation_factor; Size : positive) return signed; + + +-- component fir_filter is +-- generic ( +-- RESET_ACTIVE_LEVEL : std_ulogic := '1' --# Asynch. reset control level +-- ); +-- port ( +-- --# {{clocks|}} +-- Clock : in std_ulogic; +-- Reset : in std_ulogic; + +-- --# {{control|}} +-- Coefficients : in signed_array; + +-- --# {{data|}} +-- New_data : in std_ulogic; +-- Data_in : in signed; +-- Data_out : out signed +-- ); +-- end component; + + --# Finite Impulse Response filter. + component fir_filter is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic := '1' --# Asynch. reset control level + ); + port ( + --# {{clocks|}} + Clock : in std_ulogic; --# System clock + Reset : in std_ulogic; --# Asynchronous reset + + --# {{control|}} + Coefficients : in signed_array; --# Filter tap coefficients + + --# {{data|Write port}} + Data_valid : in std_ulogic; --# Indicate when ``Data`` is valid + Data : in signed; --# Data input to the filter + Busy : out std_ulogic; --# Indicate when filter is ready to accept new data + + --# {{Read port}} + Result_valid : out std_ulogic; --# Indicates when a new filter result is valid + Result : out signed; --# Filtered output + In_use : in std_ulogic --# Request to keep ``Result`` unchanged + ); + end component; + + + --## Compute the alpha value for a lowpass filter + --# Args: + --# Tau: Time constant + --# Sample_period: Sample period of the filtered data + --# Returns: + --# Alpha constant passed to the lowpass_filter component. + function lowpass_alpha(Tau : real; Sample_period : real) return real; + + --## First order lowpass filter. + --# This filter operates in two modes. When REGISTERED_MULTIPLY is false + --# the filter processes a new data sample on every clock cycle. + component lowpass_filter is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic := '1'; --# Asynch. reset control level + ALPHA : real; --# Alpha parameter computed with lowpass_alpha() + REGISTERED_MULTIPLY : boolean := false --# Control registration of internal mutiplier + ); + port ( + --# {{clocks|}} + Clock : in std_ulogic; --# System clock + Reset : in std_ulogic; --# Asynchronous reset + + --# {{data|}} + Data : in signed; --# Data input to the filter + Result : out signed --# Filtered output + ); + end component; + + --# Scale samples by an attenuation factor. + component attenuate is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic := '1' --# Asynch. reset control level + ); + port ( + --# {{clocks|}} + Clock : in std_ulogic; --# System clock + Reset : in std_ulogic; --# Asynchronous reset + + --# {{control|}} + Gain : in signed; --# Attenuation factor + + --# {{data|Write port}} + Data_valid : in std_ulogic; --# Indicate when ``Data`` is valid + Data : in signed; --# Data input to the filter + + --# {{Read port}} + Result_valid : out std_ulogic; --# Indicates when a new filter result is valid + Result : out signed --# Filtered output + ); + end component; + + --# Convert binary data into numeric samples. + component sampler is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic := '1' --# Asynch. reset control level + ); + port ( + --# {{clocks|}} + Clock : in std_ulogic; --# System clock + Reset : in std_ulogic; --# Asynchronous reset + + --# {{data|Write port}} + Data_valid : in std_ulogic; --# Indicate when ``Data`` is valid + Data : in std_ulogic; --# Data input to the filter + + --# {{Read port}} + Result_valid : out std_ulogic; --# Indicates when a new filter result is valid + Result : out signed --# Filtered output + ); + end component; + + --# Capture and hold data samples. + component sample_and_hold is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic := '1' --# Asynch. reset control level + ); + port ( + --# {{clocks|}} + Clock : in std_ulogic; --# System clock + Reset : in std_ulogic; --# Asynchronous reset + + --# {{data|Write port}} + Data_valid : in std_ulogic; --# Indicate when ``Data`` is valid + Data : in signed; --# Data input to the filter + Busy : out std_ulogic; --# Indicate when filter is ready to accept new data + + --# {{Read port}} + Result_valid : out std_ulogic; --# Indicates when a new filter result is valid + Result : out signed; --# Filtered output + In_use : in std_ulogic --# Request to keep ``Result`` unchanged + ); + end component; + +end package; + +package body filtering is + + function saturate(N : unsigned) return unsigned is + variable result : unsigned(N'length-2 downto 0); + begin + if N(N'high) = '1' then -- Saturate + result := (others => '1'); + else -- Trim bit + result := resize(N, result'length); + end if; + + return result; + end function; + + + function saturate(N : signed) return signed is + variable result : signed(N'length-2 downto 0); + begin + if N(N'high) /= N(N'high-1) then -- Saturate + -- Preserve sign and replicate guard bit + result := N(N'high) & resize(N(N'high-1 downto N'high-1), result'length-1); + else -- Trim bit + result := resize(N, result'length); + end if; + + return result; + end function; + + + function attenuation_gain(Factor : attenuation_factor; Size : positive) return signed is + begin + return to_signed(integer(factor * 2.0**Size) / 2 - 1, Size); + end function; + + function lowpass_alpha(Tau : real; Sample_period : real) return real is + begin + return 1.0 / ((Tau / Sample_Period) + 1.0); + end function; + +end package body; + + + +--library ieee; +--use ieee.std_logic_1164.all; +--use ieee.numeric_std.all; + +--library extras; +--use extras.sizing.ceil_log2; + +--library extras_2008; +--use extras_2008.common.all; +--use extras_2008.filtering.all; +--use extras_2008.pipelining.tapped_delay_line; + +--entity fir_filter is +-- generic ( +-- RESET_ACTIVE_LEVEL : std_ulogic := '1' --# Asynch. reset control level +-- ); +-- port ( +-- Clock : in std_ulogic; +-- Reset : in std_ulogic; +-- +-- Coefficients : in signed_array; + +-- New_data : in std_ulogic; +-- Data_in : in signed; +-- Data_out : out signed +-- ); +--end entity; + +--architecture rtl of fir_filter is +-- constant ACCUM_LEN : positive := Data_out'length + +-- ceil_log2(Coefficients'length) + +-- Coefficients'element'length; +-- signal accum : signed(ACCUM_LEN-1 downto 0); + +-- signal din : std_ulogic_vector(Data_in'length-1 downto 0); +-- signal taps_sulv : sulv_array(0 to Coefficients'length-1)(Data_in'range); +-- signal taps : signed_array(0 to Coefficients'length-1)(Data_in'range); + +-- subtype filter_taps is integer range 0 to Coefficients'length-1; +-- signal ix : filter_taps; +-- signal shift_en : std_ulogic; +--begin + +-- din <= to_stdulogicvector(std_logic_vector(Data_in)); + +-- dl: tapped_delay_line +-- generic map ( +-- RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL, +-- REGISTER_FIRST_STAGE => true +-- ) +-- port map ( +-- Clock => Clock, +-- Reset => Reset, +-- Enable => shift_en, +-- Data => din, +-- Taps => taps_sulv +-- ); +-- +-- taps <= to_signed_array(taps_sulv); + +-- filt: process(Clock, Reset) is +-- variable prod : signed(Data_in'length + Coefficients'element'length - 1 downto 0); +-- begin +-- if Reset = RESET_ACTIVE_LEVEL then +-- ix <= filter_taps'high; +-- accum <= (others => '0'); +-- Data_out <= (Data_out'range => '0'); +-- shift_en <= '0'; +-- elsif rising_edge(Clock) then +-- -- Multiply current tap with its coefficient +-- prod := taps(ix) * Coefficients(ix); +-- accum <= accum + resize(prod, accum'length); + +-- shift_en <= '0'; + +-- if ix /= 0 then -- Cycle through taps +-- ix <= ix - 1; +-- elsif New_data = '1' then -- Done with each tap +-- ix <= filter_taps'high; +-- shift_en <= '1'; +-- Data_out <= accum(Coefficients'element'length + Data_out'length - 1 downto Coefficients'element'length); +-- accum <= (others => '0'); -- Reset accumulator +-- end if; +-- end if; +-- end process; + +--end architecture; + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library extras; +use extras.sizing.ceil_log2; + +library extras_2008; +use extras_2008.common.all; +use extras_2008.filtering.all; +use extras_2008.pipelining.tapped_delay_line; + + +entity fir_filter is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic := '1' --# Asynch. reset control level + ); + port ( + Clock : in std_ulogic; + Reset : in std_ulogic; + + Coefficients : in signed_array; + + Data_valid : in std_ulogic; + Data : in signed; + Busy : out std_ulogic; + + Result_valid : out std_ulogic; + Result : out signed; + In_use : in std_ulogic + ); +end entity; + + +architecture rtl of fir_filter is + constant ACCUM_LEN : positive := Result'length + + ceil_log2(Coefficients'length) + + Coefficients'element'length; + signal accum : signed(ACCUM_LEN-1 downto 0); + + signal din : std_ulogic_vector(Data'length-1 downto 0); + signal taps_sulv : sulv_array(0 to Coefficients'length-1)(Data'range); + signal taps : signed_array(0 to Coefficients'length-1)(Data'range); + + subtype filter_taps is integer range 0 to Coefficients'length-1; + signal ix : filter_taps; + signal shift_en, data_valid_dly : std_ulogic; +begin + + din <= to_stdulogicvector(std_logic_vector(Data)); + + dl: tapped_delay_line + generic map ( + RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL, + REGISTER_FIRST_STAGE => true + ) + port map ( + Clock => Clock, + Reset => Reset, + Enable => shift_en, + Data => din, + Taps => taps_sulv + ); + + taps <= to_signed_array(taps_sulv); + + filt: process(Clock, Reset) is + variable prod : signed(Data'length + Coefficients'element'length - 1 downto 0); + begin + if Reset = RESET_ACTIVE_LEVEL then + ix <= filter_taps'high; + accum <= (others => '0'); + Result <= (Result'range => '0'); + Result_valid <= '0'; + Busy <= '0'; + --shift_en <= '0'; + data_valid_dly <= '1'; + elsif rising_edge(Clock) then + -- Multiply current tap with its coefficient + prod := taps(ix) * Coefficients(ix); + accum <= accum + resize(prod, accum'length); + + Result_valid <= '0'; + Busy <= '0'; + --shift_en <= '0'; + data_valid_dly <= Data_valid; + + if ix /= 0 then -- Cycle through taps + ix <= ix - 1; + Busy <= '1'; + elsif Data_valid = '1' and In_use = '0' then -- Done with each tap + ix <= filter_taps'high; + --shift_en <= '1'; + Result <= accum(Coefficients'element'length + Result'length - 1 downto Coefficients'element'length); + Result_valid <= '1'; + accum <= (others => '0'); -- Reset accumulator + end if; + end if; + end process; + + shift_en <= Data_valid and not data_valid_dly; + +end architecture; + + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library extras_2008; +use extras_2008.common.all; + +entity lowpass_filter_one_cycle is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic := '1'; --# Asynch. reset control level + ALPHA : real + ); + port ( + Clock : in std_ulogic; + Reset : in std_ulogic; + + Data : in signed; + Result : out signed + ); +end entity; + +architecture rtl of lowpass_filter_one_cycle is + + -- Convert a real to signed fixed point + function to_sfixed(N : real; Size : positive) return signed is + begin + return to_signed(integer(N * 2.0**(Size-1)), Size); + end function; + + + constant PROD_LEN : positive := Data'length * 2; + + -- Alpha value in fixed point form + constant C0 : signed(Data'length-1 downto 0) := to_sfixed(ALPHA, Data'length); + --constant C1 : signed(Data'length-1 downto 0) := to_sfixed(1.0 - ALPHA, Data'length); + + signal delay : signed(Data'length-1 downto 0); +begin + filt: process(Clock, Reset) is + variable delta : signed(Data'length downto 0); + variable p0 : signed(delta'length + C0'length - 1 downto 0); + begin + if Reset = RESET_ACTIVE_LEVEL then + delay <= (others => '0'); + elsif rising_edge(Clock) then + -- result' <= result + Alpha * (Data - delay) + delta := resize(Data, delta'length) - resize(delay, delta'length); + p0 := C0 * delta; + delay <= delay + resize(p0(p0'high downto C0'length-1), delay'length); + end if; + end process; + + Result <= resize(delay, Result'length); + +end architecture; + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library extras_2008; +use extras_2008.common.all; +use extras_2008.filtering.lowpass_alpha; + +entity lowpass_filter_reg_mult is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic := '1'; --# Asynch. reset control level + ALPHA : real + ); + port ( + Clock : in std_ulogic; + Reset : in std_ulogic; + + Data : in signed; + Result : out signed + ); +end entity; + +architecture rtl of lowpass_filter_reg_mult is + + function to_sfixed(N : real; Size : positive) return signed is + begin + return to_signed(integer(N * 2.0**(Size-1)), Size); + end function; + + constant Q : real := (1.0 - ALPHA) / ALPHA; -- Tau / Period + constant ALPHA_ADJ : real := lowpass_alpha(0.5 * Q, 1.0); -- Correct Alpha to account for extra cycle delay + + constant PROD_LEN : positive := Data'length * 2; + constant C0 : signed(Data'length-1 downto 0) := to_sfixed(ALPHA_ADJ, Data'length); + + signal p0 : signed(Data'length + C0'length downto 0); + signal delay : signed(Data'length-1 downto 0); + signal new_product : std_ulogic; +begin + filt: process(Clock, Reset) is + variable delta : signed(Data'length downto 0); + + begin + if Reset = RESET_ACTIVE_LEVEL then + delay <= (others => '0'); + new_product <= '0'; + elsif rising_edge(Clock) then + delta := resize(Data, delta'length) - resize(delay, delta'length); + p0 <= C0 * delta; + new_product <= not new_product; + + if new_product = '1' then + delay <= delay + resize(p0(p0'high downto C0'length-1), delay'length); + end if; + end if; + end process; + + Result <= resize(delay, Result'length); + +end architecture; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library extras_2008; +use extras_2008.common.all; + +entity lowpass_filter is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic := '1'; --# Asynch. reset control level + ALPHA : real; + REGISTERED_MULTIPLY : boolean := false + ); + port ( + Clock : in std_ulogic; + Reset : in std_ulogic; + + Data : in signed; + Result : out signed + ); +end entity; + +architecture rtl of lowpass_filter is + + component lowpass_filter_one_cycle is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic := '1'; --# Asynch. reset control level + ALPHA : real + ); + port ( + Clock : in std_ulogic; + Reset : in std_ulogic; + + Data : in signed; + Result : out signed + ); + end component; + + component lowpass_filter_reg_mult is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic := '1'; --# Asynch. reset control level + ALPHA : real + ); + port ( + Clock : in std_ulogic; + Reset : in std_ulogic; + + Data : in signed; + Result : out signed + ); + end component; + +begin + g: if REGISTERED_MULTIPLY = true generate + lp: lowpass_filter_reg_mult + generic map ( + RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL, + ALPHA => ALPHA + ) + port map ( + Clock => Clock, + Reset => Reset, + Data => Data, + Result => Result + ); + else generate + lp: lowpass_filter_one_cycle + generic map ( + RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL, + ALPHA => ALPHA + ) + port map ( + Clock => Clock, + Reset => Reset, + Data => Data, + Result => Result + ); + end generate; +end architecture; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity attenuate is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic := '1' --# Asynch. reset control level + ); + port ( + Clock : in std_ulogic; + Reset : in std_ulogic; + + Gain : in signed; + + Data_valid : in std_ulogic; + Data : in signed; + + Result_valid : out std_ulogic; + Result : out signed + ); +end entity; + +architecture rtl of attenuate is + signal prod : signed(Data'length + Gain'length - 1 downto 0); +begin + atten: process(Clock, Reset) is + begin + if Reset = RESET_ACTIVE_LEVEL then + Result <= (Result'range => '0'); + Result_valid <= '0'; + elsif rising_edge(Clock) then + prod <= Gain * Data; + -- Skipping extra sign bit + Result <= prod(prod'high-1 downto prod'high - Result'length); + Result_valid <= Data_valid; + end if; + end process; +end architecture; + + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sampler is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic := '1' --# Asynch. reset control level + ); + port ( + Clock : in std_ulogic; + Reset : in std_ulogic; + + Data_valid : in std_ulogic; + Data : in std_ulogic; + + Result_valid : out std_ulogic; + Result : out signed + ); +end entity; + + +architecture rtl of sampler is + signal sample : signed(Result'length-1 downto 0); +begin + s: process(Clock, Reset) is + begin + if Reset = RESET_ACTIVE_LEVEL then + sample <= (others => '0'); + Result_valid <= '0'; + elsif rising_edge(Clock) then + if Data = '1' then + sample <= to_signed(2**(sample'length-1) - 1, sample'length); + else + sample <= to_signed(-2**(sample'length-1), sample'length); + end if; + Result_valid <= Data_valid; + end if; + end process; + + Result <= sample; +end architecture; + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sample_and_hold is + generic ( + RESET_ACTIVE_LEVEL : std_ulogic := '1' --# Asynch. reset control level + ); + port ( + Clock : in std_ulogic; + Reset : in std_ulogic; + + Data_valid : in std_ulogic; + Data : in signed; + Busy : out std_ulogic; + + Result_valid : out std_ulogic; + Result : out signed; + In_use : in std_ulogic + ); +end entity; + +architecture rtl of sample_and_hold is +begin + s: process(Clock, Reset) is + begin + if Reset = RESET_ACTIVE_LEVEL then + Result_valid <= '0'; + Result <= (Result'range => '0'); + Busy <= '0'; + elsif rising_edge(Clock) then + Result_valid <= '0'; + + if Data_valid = '1' and In_use = '0' then + Result <= Data; + Result_valid <= '1'; + end if; + Busy <= In_use; + end if; + end process; + +end architecture; +