diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6410.h b/arch/arm/include/asm/arch-s3c64xx/s3c6410.h index 7d7d6ae..672f7b2 100644 --- a/arch/arm/include/asm/arch-s3c64xx/s3c6410.h +++ b/arch/arm/include/asm/arch-s3c64xx/s3c6410.h @@ -574,7 +574,15 @@ #define NFMECC1_OFFSET 0x38 #define NFSECC_OFFSET 0x3c #define NFMLCBITPT_OFFSET 0x40 - +#define NF8ECCERR0_OFFSET 0x44 +#define NF8ECCERR1_OFFSET 0x48 +#define NF8ECCERR2_OFFSET 0x4c +#define NFM8ECC0_OFFSET 0x50 +#define NFM8ECC1_OFFSET 0x54 +#define NFM8ECC2_OFFSET 0x58 +#define NFM8ECC3_OFFSET 0x5c +#define NFMLC8BITPT0_OFFSET 0x60 +#define NFMLC8BITPT1_OFFSET 0x64 #define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET) #define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET) #define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET) @@ -592,6 +600,15 @@ #define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET) #define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET) #define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) +#define NF8ECCERR0 (ELFIN_NAND_BASE + NF8ECCERR0_OFFSET) +#define NF8ECCERR1 (ELFIN_NAND_BASE + NF8ECCERR1_OFFSET) +#define NF8ECCERR2 (ELFIN_NAND_BASE + NF8ECCERR2_OFFSET) +#define NFM8ECC0 (ELFIN_NAND_BASE + NFM8ECC0_OFFSET) +#define NFM8ECC1 (ELFIN_NAND_BASE + NFM8ECC1_OFFSET) +#define NFM8ECC2 (ELFIN_NAND_BASE + NFM8ECC2_OFFSET) +#define NFM8ECC3 (ELFIN_NAND_BASE + NFM8ECC3_OFFSET) +#define NFMLC8BITPT0 (ELFIN_NAND_BASE + NFMLC8BITPT0_OFFSET) +#define NFMLC8BITPT1 (ELFIN_NAND_BASE + NFMLC8BITPT0_OFFSET) #define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET) #define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET) @@ -611,6 +628,15 @@ #define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET) #define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET) #define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) +#define NF8ECCERR0_REG __REG(ELFIN_NAND_BASE + NF8ECCERR0_OFFSET) +#define NF8ECCERR1_REG __REG(ELFIN_NAND_BASE + NF8ECCERR1_OFFSET) +#define NF8ECCERR2_REG __REG(ELFIN_NAND_BASE + NF8ECCERR2_OFFSET) +#define NFM8ECC0_REG __REG(ELFIN_NAND_BASE + NFM8ECC0_OFFSET) +#define NFM8ECC1_REG __REG(ELFIN_NAND_BASE + NFM8ECC1_OFFSET) +#define NFM8ECC2_REG __REG(ELFIN_NAND_BASE + NFM8ECC2_OFFSET) +#define NFM8ECC3_REG __REG(ELFIN_NAND_BASE + NFM8ECC3_OFFSET) +#define NFMLC8BITPT0_REG __REG(ELFIN_NAND_BASE + NFMLC8BITPT0_OFFSET) +#define NFMLC8BITPT1_REG __REG(ELFIN_NAND_BASE + NFMLC8BITPT0_OFFSET) #define NFCONF_ECC_4BIT (1<<24) @@ -718,6 +744,32 @@ */ #define ELFIN_TIMER_BASE 0x7F006000 +#define TCFG0_REG __REG(0x7F006000) +#define ULCON1_REG __REG(0x7F005400) +#define UCON1_REG __REG(0x7F005404) +#define UFCON1_REG __REG(0x7F005408) +#define UMCON1_REG __REG(0x7F00540C) +#define UTRSTAT1_REG __REG(0x7F005410) +#define UERSTAT1_REG __REG(0x7F005414) +#define UFSTAT1_REG __REG(0x7F005418) +#define UMSTAT1_REG __REG(0x7F00541c) +#define UTXH1_REG __REG(0x7F005420) +#define URXH1_REG __REG(0x7F005424) +#define UBRDIV1_REG __REG(0x7F005428) +#define UDIVSLOT1_REG __REG(0x7F00542c) +#define UINTP1_REG __REG(0x7F005430) +#define UINTSP1_REG __REG(0x7F005434) +#define UINTM1_REG __REG(0x7F005438) + +#define UTRSTAT_TX_EMPTY (1 << 2) +#define UTRSTAT_RX_READY (1 << 0) +#define UART_ERR_MASK 0xF + +/* + * PWM timer + */ +#define ELFIN_TIMER_BASE 0x7F006000 + #define TCFG0_REG __REG(0x7F006000) #define TCFG1_REG __REG(0x7F006004) #define TCON_REG __REG(0x7F006008) @@ -894,3 +946,4 @@ static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr) #endif #endif /*__S3C6410_H__*/ + diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index d1b3a19..3411e32 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -103,6 +103,17 @@ _main: /*call by start.S*/ #if defined(CONFIG_NAND_SPL) /* deprecated, use instead CONFIG_SPL_BUILD */ ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) /*0x0c002000 smdk6410.h*/ + +// ldr r0, = __bss_start /* this is auto-relocated! */ + // ldr r1, =__bss_end__ /* this is auto-relocated! */ + + // mov r2, #0x00000000 /* prepare zero to clear BSS */ +//bss_clean:cmp r0, r1 /* while not at end of BSS */ + // strlo r2, [r0] /* clear 32-bit BSS word */ + // addlo r0, r0, #4 /* move to next */ + // blo bss_clean + ldr pc, = nand_boot + #elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) ldr sp, =(CONFIG_SPL_STACK) #else diff --git a/board/samsung/smdk6410/lowlevel_init.S b/board/samsung/smdk6410/lowlevel_init.S index b2d6117..2ac9deb 100644 --- a/board/samsung/smdk6410/lowlevel_init.S +++ b/board/samsung/smdk6410/lowlevel_init.S @@ -59,7 +59,7 @@ lowlevel_init: /*call by start.S*/ ldr r1, =0x00000555 str r1, [r0, #GPMPUD_OFFSET] /* all of LEDs are power on*/ - ldr r1, =0x000f + ldr r1, =0x0005 str r1, [r0, #GPMDAT_OFFSET] /*¹Ø±Õ¿´ÃŹ·*/ /* Disable Watchdog, write 0 to 0x7e004000*/ @@ -274,8 +274,8 @@ uart_asm_init: nand_asm_init: ldr r0, =ELFIN_NAND_BASE ldr r1, [r0, #NFCONF_OFFSET] - orr r1, r1, #0x70 - orr r1, r1, #0x7700 + orr r1, r1, #0x1 /*TWRPH1 = 0*/ + orr r1, r1, #0x1300 /*TWRPH0 = 2, TACLS = 0*/ str r1, [r0, #NFCONF_OFFSET] ldr r1, [r0, #NFCONT_OFFSET] diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 32348f3..1bd53f7 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -659,6 +659,22 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) (u_char *)addr, WITH_DROP_FFS); #endif + }else if((!read) && (s != NULL) && (!strcmp(s, ".uboot")) && nand->writesize == 4096){ + rwsize = 4096; + nand_write(nand, off, &rwsize, (u_char *)addr); + off+= 4096; + addr+= 2048; + nand_write(nand, off, &rwsize, (u_char *)addr); + off+= 4096; + addr+= 2048; + nand_write(nand, off, &rwsize, (u_char *)addr); + off+= 4096; + addr+= 2048; + nand_write(nand, off, &rwsize, (u_char *)addr); + off+= 4096; + addr+= 2048; + rwsize = CONFIG_SYS_NAND_U_BOOT_SIZE - 8*1024; + ret = nand_write(nand, off, &rwsize, (u_char *)addr); #ifdef CONFIG_CMD_NAND_YAFFS } else if (!strcmp(s, ".yaffs")) { if (read) { @@ -666,6 +682,8 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; } ret = nand_write_skip_bad(nand, off, &rwsize, + +q (u_char *)addr, WITH_INLINE_OOB); #endif diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index 3953549..fb50c87 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -112,7 +112,8 @@ const struct nand_flash_dev nand_flash_ids[] = { /* 16 Gigabit */ {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS}, - {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS}, +// {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS}, + {"NAND 2GiB 3,3V 8-bit", 0xD5, 4096, 2048, 4096*128, LP_OPTIONS}, {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16}, {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16}, diff --git a/drivers/mtd/nand/s3c64xx.c b/drivers/mtd/nand/s3c64xx.c index bb6ae8d..1964b25 100644 --- a/drivers/mtd/nand/s3c64xx.c +++ b/drivers/mtd/nand/s3c64xx.c @@ -126,6 +126,218 @@ static int s3c_nand_device_ready(struct mtd_info *mtdinfo) * This function is called before encoding ecc codes to ready ecc engine. * Written by jsgood */ + +#if defined(CONFIG_NAND_BL1_8BIT_ECC) && (defined(CONFIG_S3C6410) || defined(CONFIG_S3C6430)) + /*************************************************************** + * jsgood: Temporary 8 Bit H/W ECC supports for BL1 (6410/6430 only) + ***************************************************************/ + int cur_ecc_mode=0; + /* + * Function for checking ECCEncDone in NFSTAT + * Written by jsgood + */ + static void s3c_nand_wait_enc(void) + { + while (!(readl(NFSTAT) & NFSTAT_ECCENCDONE)) {} + } + + /* + * Function for checking ECCDecDone in NFSTAT + * Written by jsgood + */ + static void s3c_nand_wait_dec(void) + { + while (!(readl(NFSTAT) & NFSTAT_ECCDECDONE)) {} + } + + static void s3c_nand_wait_ecc_busy_8bit(void) + { + while (readl(NF8ECCERR0) & NFESTAT0_ECCBUSY) {} + } + void s3c_nand_enable_hwecc_8bit(struct mtd_info *mtd, int mode) +{ + u_long nfcont, nfconf; + + cur_ecc_mode = mode; + + /* 8 bit selection */ + nfconf = readl(NFCONF); + + nfconf &= ~(0x3 << 23); + nfconf |= (0x1 << 23); + + writel(nfconf, NFCONF); + + /* Initialize & unlock */ + nfcont = readl(NFCONT); + nfcont |= NFCONT_INITECC; + nfcont &= ~NFCONT_MECCLOCK; + + if (mode == NAND_ECC_WRITE) + nfcont |= NFCONT_ECC_ENC; + else if (mode == NAND_ECC_READ) + nfcont &= ~NFCONT_ECC_ENC; + + writel(nfcont, NFCONT); +} +int s3c_nand_calculate_ecc_8bit(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) +{ + u_long nfcont, nfm8ecc0, nfm8ecc1, nfm8ecc2, nfm8ecc3; + + /* Lock */ + nfcont = readl(NFCONT); + nfcont |= NFCONT_MECCLOCK; + writel(nfcont, NFCONT); + + if (cur_ecc_mode == NAND_ECC_READ) + s3c_nand_wait_dec(); + else { + s3c_nand_wait_enc(); + + nfm8ecc0 = readl(NFM8ECC0); + nfm8ecc1 = readl(NFM8ECC1); + nfm8ecc2 = readl(NFM8ECC2); + nfm8ecc3 = readl(NFM8ECC3); + + ecc_code[0] = nfm8ecc0 & 0xff; + ecc_code[1] = (nfm8ecc0 >> 8) & 0xff; + ecc_code[2] = (nfm8ecc0 >> 16) & 0xff; + ecc_code[3] = (nfm8ecc0 >> 24) & 0xff; + ecc_code[4] = nfm8ecc1 & 0xff; + ecc_code[5] = (nfm8ecc1 >> 8) & 0xff; + ecc_code[6] = (nfm8ecc1 >> 16) & 0xff; + ecc_code[7] = (nfm8ecc1 >> 24) & 0xff; + ecc_code[8] = nfm8ecc2 & 0xff; + ecc_code[9] = (nfm8ecc2 >> 8) & 0xff; + ecc_code[10] = (nfm8ecc2 >> 16) & 0xff; + ecc_code[11] = (nfm8ecc2 >> 24) & 0xff; + ecc_code[12] = nfm8ecc3 & 0xff; + } + + return 0; +} + +int s3c_nand_correct_data_8bit(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) +{ + int ret = -1; + u_long nf8eccerr0, nf8eccerr1, nf8eccerr2, nfmlc8bitpt0, nfmlc8bitpt1; + u_char err_type; + + s3c_nand_wait_ecc_busy_8bit(); + + nf8eccerr0 = readl(NF8ECCERR0); + nf8eccerr1 = readl(NF8ECCERR1); + nf8eccerr2 = readl(NF8ECCERR2); + nfmlc8bitpt0 = readl(NFMLC8BITPT0); + nfmlc8bitpt1 = readl(NFMLC8BITPT1); + + err_type = (nf8eccerr0 >> 25) & 0xf; + + /* No error, If free page (all 0xff) */ + if ((nf8eccerr0 >> 29) & 0x1) + err_type = 0; + + switch (err_type) + { + case 8: /* 8 bit error (Correctable) */ + dat[(nf8eccerr2 >> 22) & 0x3ff] ^= ((nfmlc8bitpt1 >> 24) & 0xff); + printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type); + + case 7: /* 7 bit error (Correctable) */ + dat[(nf8eccerr2 >> 11) & 0x3ff] ^= ((nfmlc8bitpt1 >> 16) & 0xff); + printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type); + + case 6: /* 6 bit error (Correctable) */ + dat[nf8eccerr2 & 0x3ff] ^= ((nfmlc8bitpt1 >> 8) & 0xff); + printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type); + + case 5: /* 5 bit error (Correctable) */ + dat[(nf8eccerr1 >> 22) & 0x3ff] ^= (nfmlc8bitpt1 & 0xff); + printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type); + + case 4: /* 4 bit error (Correctable) */ + dat[(nf8eccerr1 >> 11) & 0x3ff] ^= ((nfmlc8bitpt0 >> 24) & 0xff); + printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type); + + case 3: /* 3 bit error (Correctable) */ + dat[nf8eccerr1 & 0x3ff] ^= ((nfmlc8bitpt0 >> 16) & 0xff); + printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type); + + case 2: /* 2 bit error (Correctable) */ + dat[(nf8eccerr0 >> 15) & 0x3ff] ^= ((nfmlc8bitpt0 >> 8) & 0xff); + printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type); + + + case 1: /* 1 bit error (Correctable) */ + printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type); + dat[nf8eccerr0 & 0x3ff] ^= (nfmlc8bitpt0 & 0xff); + ret = err_type; + break; + + case 0: /* No error */ + ret = 0; + break; + + } + + return ret; +} + +void s3c_nand_write_page_8bit(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf) +{ + int i, eccsize = 512; + int eccbytes = 13; + int eccsteps = mtd->writesize / eccsize; + uint8_t *ecc_calc = chip->buffers->ecccalc; + uint8_t *p = buf; + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + s3c_nand_enable_hwecc_8bit(mtd, NAND_ECC_WRITE); + chip->write_buf(mtd, p, eccsize); + s3c_nand_calculate_ecc_8bit(mtd, p, &ecc_calc[i]); + } + + for (i = 0; i < eccbytes * (mtd->writesize / eccsize); i++) + chip->oob_poi[i+24] = ecc_calc[i]; + chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); +} + +int s3c_nand_read_page_8bit(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf) +{ + int i, stat, eccsize = 512; + int eccbytes = 13; + int eccsteps = mtd->writesize / eccsize; + int col = 0; + uint8_t *p = buf; + + /* Step1: read whole oob */ + col = mtd->writesize; + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1); + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); + + col = 0; + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1); + s3c_nand_enable_hwecc_8bit(mtd, NAND_ECC_READ); + chip->read_buf(mtd, p, eccsize); + chip->write_buf(mtd, chip->oob_poi + 24 + (((mtd->writesize / eccsize) - eccsteps) * eccbytes), eccbytes); + s3c_nand_calculate_ecc_8bit(mtd, 0, 0); + stat = s3c_nand_correct_data_8bit(mtd, p, 0, 0); + + if (stat == -1) + mtd->ecc_stats.failed++; + + col = eccsize * ((mtd->writesize / eccsize) + 1 - eccsteps); + } + + return 0; +} + +/********************************************************/ +#endif + static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode) { u_long nfcont, nfconf; @@ -135,8 +347,9 @@ static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode) * those with non-zero ID[3][3:2], which anyway only holds for ST * (Numonyx) chips */ - nfconf = readl(NFCONF) & ~NFCONF_ECC_4BIT; + nfconf = readl(NFCONF) & ~NFCONF_ECC_4BIT; + writel(nfconf, NFCONF); /* Initialize & unlock */ @@ -161,7 +374,6 @@ static int s3c_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { u_long nfcont, nfmecc0; - /* Lock */ nfcont = readl(NFCONT); nfcont |= NFCONT_MECCLOCK; @@ -173,7 +385,7 @@ static int s3c_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, ecc_code[1] = (nfmecc0 >> 8) & 0xff; ecc_code[2] = (nfmecc0 >> 16) & 0xff; ecc_code[3] = (nfmecc0 >> 24) & 0xff; - + return 0; } @@ -278,10 +490,19 @@ int board_nand_init(struct nand_chip *nand) #endif #ifdef CONFIG_SYS_S3C_NAND_HWECC + #ifdef CONFIG_NAND_BL1_8BIT_ECC + printf("USE HWECC 8BIT\n"); + nand->ecc.hwctl = s3c_nand_enable_hwecc_8bit; + nand->ecc.calculate = s3c_nand_calculate_ecc_8bit; + nand->ecc.correct = s3c_nand_correct_data_8bit; + nand->ecc.read_page = s3c_nand_read_page_8bit; + nand->ecc.write_page = s3c_nand_write_page_8bit; + #else + printf("USE HWECC Default\n"); nand->ecc.hwctl = s3c_nand_enable_hwecc; nand->ecc.calculate = s3c_nand_calculate_ecc; nand->ecc.correct = s3c_nand_correct_data; - + #endif /* * If you get more than 1 NAND-chip with different page-sizes on the * board one day, it will get more complicated... @@ -289,6 +510,7 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.mode = NAND_ECC_HW; nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; + printf("ECC Size:%d ECC Bytes:%d\n",nand->ecc.size,nand->ecc.bytes);//zxd #else nand->ecc.mode = NAND_ECC_SOFT; #endif /* ! CONFIG_SYS_S3C_NAND_HWECC */ @@ -297,3 +519,4 @@ int board_nand_init(struct nand_chip *nand) return 0; } + diff --git a/include/configs/smdk6410.h b/include/configs/smdk6410.h index db7d423..a030163 100644 --- a/include/configs/smdk6410.h +++ b/include/configs/smdk6410.h @@ -210,19 +210,20 @@ "bootm 0xc0018000" #else #define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE -#define CONFIG_BOOTCOMMAND "nand read 0x50018000 0x60000 0x1c0000;" \ - "bootm 0x50018000" +/*#define CONFIG_BOOTCOMMAND "nand read 0x50018000 0x60000 0x1c0000;" \ + "bootm 0x50018000"*/ #endif /* NAND U-Boot load and start address */ #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_MAPPED_RAM_BASE + 0x07e00000) -#define CONFIG_ENV_OFFSET 0x0040000 +#define CONFIG_ENV_OFFSET 0x80000 /*Must be integer times of block size*/ /* NAND configuration */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x70200010 #define CONFIG_SYS_S3C_NAND_HWECC +#define CONFIG_NAND_BL1_8BIT_ECC #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ #define CONFIG_SYS_NAND_WP 1 @@ -232,15 +233,15 @@ #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_PHY_UBOOT_BASE /* NUB load-addr */ #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* NUB start-addr */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS (4 * 1024) /* Offset to RAM U-Boot image */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE (252 * 1024) /* Size of RAM U-Boot image */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 * 1024) /* Offset to RAM U-Boot image */ +#define CONFIG_SYS_NAND_U_BOOT_SIZE (300 * 1024) /* Size of RAM U-Boot image, mast big than the size of u-boot.bin */ /* NAND chip page size */ -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_PAGE_SIZE 4096 /* NAND chip block size */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 4096) /* NAND chip page per block count */ -#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_COUNT 128 /* Location of the bad-block label */ #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 /* Extra address cycle for > 128MiB */ @@ -274,12 +275,20 @@ */ /* Settings as above boot configuration */ -/* + #ifdef CONFIG_BOOT_SD +#define CONFIG_BOOTCOMMAND "fatload mmc 0 50008000 u-boot-nand.bin;"\ + "nand erase.chip;"\ + "nand write.uboot 50008000 0 0" +/* #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 -#endif */ +#else +#define CONFIG_BOOTCOMMAND "fatload mmc 0 50008000 uImage;"\ + "bootm 50008000" +#endif + #define CONFIG_ENV_IS_IN_NAND #define CONFIG_BOOTARGS "console=ttySAC,115200" diff --git a/nand_spl/board/samsung/smdk6410/config.mk b/nand_spl/board/samsung/smdk6410/config.mk index 8bea498..f56b542 100644 --- a/nand_spl/board/samsung/smdk6410/config.mk +++ b/nand_spl/board/samsung/smdk6410/config.mk @@ -32,8 +32,8 @@ include $(TOPDIR)/board/$(BOARDDIR)/config.mk # PAD_TO used to generate a 4kByte binary needed for the combined image -# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 4096 -PAD_TO := $(shell expr $$[$(CONFIG_SYS_TEXT_BASE) + 4096]) +# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 8192 /*8*1024*/ +PAD_TO := $(shell expr $(CONFIG_SYS_TEXT_BASE) + 8192) ifeq ($(debug),1) PLATFORM_CPPFLAGS += -DDEBUG