Connect UART hardware flow control to FPGA

[jago85]

When sending data faster than the host PC removes it from the RX FIFO, bytes will be lost. The FT232R can set /RTS when the RX FIFO is full and hardware flow control is active. The FPGA must wait until /RTS is cleared. Through setting /CTS the FPGA can delay the host from sending data.

/RTS and /CTS should be connected from the FT232R to the FPGA.