From fef040d834a11b55a0c662b0b27fe35123c90594 Mon Sep 17 00:00:00 2001 From: billow Date: Wed, 18 Sep 2024 22:56:52 +0800 Subject: [PATCH] Xtensa fix --- MCInst.c | 6 -- MCInst.h | 2 - arch/Xtensa/XtensaMapping.c | 3 +- arch/Xtensa/XtensaMapping.h | 4 +- bindings/python/tests/test_xtensa.py | 70 ------------------ cs.c | 74 ++++++++++--------- cstool/cstool.c | 5 -- cstool/cstool.h | 2 +- cstool/{cstool_xtensa.inc => cstool_xtensa.c} | 2 +- include/capstone/capstone.h | 1 - suite/auto-sync/src/autosync/ASUpdater.py | 13 +--- suite/auto-sync/src/autosync/MCUpdater.py | 4 +- suite/cstest/src/test_run.c | 3 +- 13 files changed, 51 insertions(+), 138 deletions(-) delete mode 100755 bindings/python/tests/test_xtensa.py rename cstool/{cstool_xtensa.inc => cstool_xtensa.c} (96%) diff --git a/MCInst.c b/MCInst.c index 1e17736d310..0894a3f00a2 100644 --- a/MCInst.c +++ b/MCInst.c @@ -179,12 +179,6 @@ void MCOperand_setFPImm(MCOperand *op, double Val) op->FPImmVal = Val; } -int64_t MCOperand_getExpr(const MCOperand *MC) -{ - CS_ASSERT(MC->Kind == kExpr); - return MC->ImmVal; -} - MCOperand *MCOperand_CreateReg1(MCInst *mcInst, unsigned Reg) { MCOperand *op = &(mcInst->Operands[MCINST_CACHE]); diff --git a/MCInst.h b/MCInst.h index 2279ce76ace..7e67321a292 100644 --- a/MCInst.h +++ b/MCInst.h @@ -84,8 +84,6 @@ const MCInst *MCOperand_getInst(const MCOperand *op); void MCOperand_setInst(MCOperand *op, const MCInst *Val); -int64_t MCOperand_getExpr(const MCOperand *MC); - // create Reg operand in the next slot void MCOperand_CreateReg0(MCInst *inst, unsigned Reg); diff --git a/arch/Xtensa/XtensaMapping.c b/arch/Xtensa/XtensaMapping.c index 7ded3803036..7098814b465 100644 --- a/arch/Xtensa/XtensaMapping.c +++ b/arch/Xtensa/XtensaMapping.c @@ -216,7 +216,6 @@ void Xtensa_add_cs_detail(MCInst *MI, xtensa_op_group op_group, va_list args) } break; } - const map_insn_ops *ops = insn_operands + MCInst_getOpcode(MI); - xop->access = (ops->ops + op_num)->access; + xop->access = map_get_op_access(MI, op_num); Xtensa_inc_op_count(MI); } \ No newline at end of file diff --git a/arch/Xtensa/XtensaMapping.h b/arch/Xtensa/XtensaMapping.h index bd5b4b99f96..33e2269c0e0 100644 --- a/arch/Xtensa/XtensaMapping.h +++ b/arch/Xtensa/XtensaMapping.h @@ -4,6 +4,8 @@ #ifndef XTENSA_MAPPING_H #define XTENSA_MAPPING_H +#include "../../Mapping.h" + typedef enum { #include "XtensaGenCSOpGroup.inc" } xtensa_op_group; @@ -26,7 +28,7 @@ void Xtensa_add_cs_detail(MCInst *MI, xtensa_op_group op_group, va_list args); static inline void add_cs_detail(MCInst *MI, xtensa_op_group op_group, ...) { - if (!MI->flat_insn->detail) + if (!detail_is_set(MI)) return; va_list args; va_start(args, op_group); diff --git a/bindings/python/tests/test_xtensa.py b/bindings/python/tests/test_xtensa.py deleted file mode 100755 index a5bc4bb4d7e..00000000000 --- a/bindings/python/tests/test_xtensa.py +++ /dev/null @@ -1,70 +0,0 @@ -#!/usr/bin/env python - -# Capstone Python bindings test, by billow - -from __future__ import print_function -from capstone import * -from capstone.xtensa import * -from xprint import to_hex, to_x - -all_tests = ( - (CS_ARCH_XTENSA, CS_MODE_LITTLE_ENDIAN, b'\x60\x51\x60\x32\x51\x02', "Xtensa"), -) - - -def print_insn_detail(insn: CsInsn): - # print address, mnemonic and operands - print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - - # "data" instruction generated by SKIPDATA option has no detail - if insn.id == 0: - return - - if len(insn.operands) > 0: - print("\top_count: %u" % len(insn.operands)) - c = 0 - for i in insn.operands: - if i.type == CS_OP_REG: - print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) - if i.type == CS_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) - if i.type == CS_OP_MEM: - print("\t\toperands[%u].type: MEM" % c) - if i.mem.base != 0: - print(f"\t\t\t.mem.base: REG = {insn.reg_name(i.mem.base)}") - if i.mem.disp != 0: - print(f"\t\t\t.mem.disp:{i.mem.disp:#x}") - if i.access == CS_AC_READ: - print("\t\t\t.access: READ") - elif i.access == CS_AC_WRITE: - print("\t\t\t.access: WRITE") - elif i.access == (CS_AC_READ & CS_AC_WRITE): - print("\t\t\t.access: READ | WRITE") - c += 1 - - rs, ws = insn.regs_access() - if len(rs) > 0: - print(f"\tRegisters read: {' '.join(map(insn.reg_name, rs))}") - if len(ws) > 0: - print(f"\tRegisters modified: {' '.join(map(insn.reg_name, ws))}") - - -# ## Test class Cs -def test_class(): - for (arch, mode, code, comment) in all_tests: - print("*" * 16) - print("Platform: %s" % comment) - print("Code: %s" % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - md.detail = True - for insn in md.disasm(code, 0x1000): - print_insn_detail(insn) - except CsError as e: - print("ERROR: %s" % e) - - -if __name__ == '__main__': - test_class() diff --git a/cs.c b/cs.c index 8f512a97b9d..d75a87b1f15 100644 --- a/cs.c +++ b/cs.c @@ -258,7 +258,9 @@ typedef struct cs_arch_config { } #define CS_ARCH_CONFIG_XTENSA \ { \ - Xtensa_global_init, Xtensa_option, ~(CS_MODE_XTENSA), \ + Xtensa_global_init, \ + Xtensa_option, \ + ~(CS_MODE_XTENSA), \ } #ifdef CAPSTONE_USE_ARCH_REGISTRATION @@ -365,8 +367,8 @@ static const cs_arch_config arch_configs[MAX_ARCH] = { { HPPA_global_init, HPPA_option, - ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11 - | CS_MODE_HPPA_20 | CS_MODE_HPPA_20W), + ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11 | + CS_MODE_HPPA_20 | CS_MODE_HPPA_20W), }, #else { NULL, NULL, 0 }, @@ -386,72 +388,72 @@ static const cs_arch_config arch_configs[MAX_ARCH] = { // bitmask of enabled architectures static const uint32_t all_arch = 0 #ifdef CAPSTONE_HAS_ARM - | (1 << CS_ARCH_ARM) + | (1 << CS_ARCH_ARM) #endif #if defined(CAPSTONE_HAS_AARCH64) || defined(CAPSTONE_HAS_ARM64) - | (1 << CS_ARCH_AARCH64) + | (1 << CS_ARCH_AARCH64) #endif #ifdef CAPSTONE_HAS_MIPS - | (1 << CS_ARCH_MIPS) + | (1 << CS_ARCH_MIPS) #endif #ifdef CAPSTONE_HAS_X86 - | (1 << CS_ARCH_X86) + | (1 << CS_ARCH_X86) #endif #ifdef CAPSTONE_HAS_POWERPC - | (1 << CS_ARCH_PPC) + | (1 << CS_ARCH_PPC) #endif #ifdef CAPSTONE_HAS_SPARC - | (1 << CS_ARCH_SPARC) + | (1 << CS_ARCH_SPARC) #endif #ifdef CAPSTONE_HAS_SYSTEMZ - | (1 << CS_ARCH_SYSTEMZ) + | (1 << CS_ARCH_SYSTEMZ) #endif #ifdef CAPSTONE_HAS_XCORE - | (1 << CS_ARCH_XCORE) + | (1 << CS_ARCH_XCORE) #endif #ifdef CAPSTONE_HAS_M68K - | (1 << CS_ARCH_M68K) + | (1 << CS_ARCH_M68K) #endif #ifdef CAPSTONE_HAS_TMS320C64X - | (1 << CS_ARCH_TMS320C64X) + | (1 << CS_ARCH_TMS320C64X) #endif #ifdef CAPSTONE_HAS_M680X - | (1 << CS_ARCH_M680X) + | (1 << CS_ARCH_M680X) #endif #ifdef CAPSTONE_HAS_EVM - | (1 << CS_ARCH_EVM) + | (1 << CS_ARCH_EVM) #endif #ifdef CAPSTONE_HAS_MOS65XX - | (1 << CS_ARCH_MOS65XX) + | (1 << CS_ARCH_MOS65XX) #endif #ifdef CAPSTONE_HAS_WASM - | (1 << CS_ARCH_WASM) + | (1 << CS_ARCH_WASM) #endif #ifdef CAPSTONE_HAS_BPF - | (1 << CS_ARCH_BPF) + | (1 << CS_ARCH_BPF) #endif #ifdef CAPSTONE_HAS_RISCV - | (1 << CS_ARCH_RISCV) + | (1 << CS_ARCH_RISCV) #endif #ifdef CAPSTONE_HAS_SH - | (1 << CS_ARCH_SH) + | (1 << CS_ARCH_SH) #endif #ifdef CAPSTONE_HAS_TRICORE - | (1 << CS_ARCH_TRICORE) + | (1 << CS_ARCH_TRICORE) #endif #ifdef CAPSTONE_HAS_ALPHA - | (1 << CS_ARCH_ALPHA) + | (1 << CS_ARCH_ALPHA) #endif #ifdef CAPSTONE_HAS_HPPA - | (1 << CS_ARCH_HPPA) + | (1 << CS_ARCH_HPPA) #endif #ifdef CAPSTONE_HAS_LOONGARCH - | (1 << CS_ARCH_LOONGARCH) + | (1 << CS_ARCH_LOONGARCH) #endif #ifdef CAPSTONE_HAS_XTENSA | (1 << CS_ARCH_XTENSA) #endif -; + ; #endif @@ -683,17 +685,17 @@ bool CAPSTONE_API cs_support(int query) { if (query == CS_ARCH_ALL) return all_arch == - ((1 << CS_ARCH_ARM) | (1 << CS_ARCH_AARCH64) | - (1 << CS_ARCH_MIPS) | (1 << CS_ARCH_X86) | - (1 << CS_ARCH_PPC) | (1 << CS_ARCH_SPARC) | - (1 << CS_ARCH_SYSTEMZ) | (1 << CS_ARCH_XCORE) | - (1 << CS_ARCH_M68K) | (1 << CS_ARCH_TMS320C64X) | - (1 << CS_ARCH_M680X) | (1 << CS_ARCH_EVM) | - (1 << CS_ARCH_RISCV) | (1 << CS_ARCH_MOS65XX) | - (1 << CS_ARCH_WASM) | (1 << CS_ARCH_BPF) | - (1 << CS_ARCH_SH) | (1 << CS_ARCH_TRICORE) | - (1 << CS_ARCH_ALPHA) | (1 << CS_ARCH_HPPA) | - (1 << CS_ARCH_LOONGARCH) | (1 << CS_ARCH_XTENSA)); + ((1 << CS_ARCH_ARM) | (1 << CS_ARCH_AARCH64) | + (1 << CS_ARCH_MIPS) | (1 << CS_ARCH_X86) | + (1 << CS_ARCH_PPC) | (1 << CS_ARCH_SPARC) | + (1 << CS_ARCH_SYSTEMZ) | (1 << CS_ARCH_XCORE) | + (1 << CS_ARCH_M68K) | (1 << CS_ARCH_TMS320C64X) | + (1 << CS_ARCH_M680X) | (1 << CS_ARCH_EVM) | + (1 << CS_ARCH_RISCV) | (1 << CS_ARCH_MOS65XX) | + (1 << CS_ARCH_WASM) | (1 << CS_ARCH_BPF) | + (1 << CS_ARCH_SH) | (1 << CS_ARCH_TRICORE) | + (1 << CS_ARCH_ALPHA) | (1 << CS_ARCH_HPPA) | + (1 << CS_ARCH_LOONGARCH) | (1 << CS_ARCH_XTENSA)); if ((unsigned int)query < CS_ARCH_MAX) return all_arch & (1 << query); diff --git a/cstool/cstool.c b/cstool/cstool.c index f8fd28eccb1..d88cb4e0a2a 100644 --- a/cstool/cstool.c +++ b/cstool/cstool.c @@ -343,11 +343,6 @@ static void usage(char *prog) printf(")\n"); } - if (cs_support(CS_ARCH_XTENSA)) { - printf(" xtensa Xtensa\n"); - printf(" xtensabe Xtensa + big endian\n"); - } - printf("\nExtra options:\n"); printf(" -d show detailed information of the instructions\n"); printf(" -r show detailed information of the real instructions (even for alias)\n"); diff --git a/cstool/cstool.h b/cstool/cstool.h index 9f128a7f7c8..b55cf70cc86 100644 --- a/cstool/cstool.h +++ b/cstool/cstool.h @@ -22,6 +22,6 @@ void print_insn_detail_tricore(csh handle, cs_insn *ins); void print_insn_detail_alpha(csh handle, cs_insn *ins); void print_insn_detail_hppa(csh handle, cs_insn *ins); void print_insn_detail_loongarch(csh handle, cs_insn *ins); -#include "cstool_xtensa.inc" +void print_insn_detail_xtensa(csh handle, cs_insn *ins); #endif //CAPSTONE_CSTOOL_CSTOOL_H_ diff --git a/cstool/cstool_xtensa.inc b/cstool/cstool_xtensa.c similarity index 96% rename from cstool/cstool_xtensa.inc rename to cstool/cstool_xtensa.c index 6fb44dcbe3e..3a533723d36 100644 --- a/cstool/cstool_xtensa.inc +++ b/cstool/cstool_xtensa.c @@ -4,7 +4,7 @@ #include #include -static inline void print_insn_detail_xtensa(csh handle, cs_insn *ins) +void print_insn_detail_xtensa(csh handle, cs_insn *ins) { int i; cs_regs regs_read, regs_write; diff --git a/include/capstone/capstone.h b/include/capstone/capstone.h index ccef8af6218..56961137edf 100644 --- a/include/capstone/capstone.h +++ b/include/capstone/capstone.h @@ -284,7 +284,6 @@ typedef enum cs_mode { CS_MODE_SYSTEMZ_Z16 = 1 << 14, ///< Enables features of the Z16 processor CS_MODE_SYSTEMZ_GENERIC = 1 << 15, ///< Enables features of the generic processor CS_MODE_XTENSA = 1 << 1, ///< Xtensa - CS_MODE_XTENSA = 1 << 0, ///< Xtensa } cs_mode; typedef void* (CAPSTONE_API *cs_malloc_t)(size_t size); diff --git a/suite/auto-sync/src/autosync/ASUpdater.py b/suite/auto-sync/src/autosync/ASUpdater.py index 7163d0e5c0e..08c5fac7685 100755 --- a/suite/auto-sync/src/autosync/ASUpdater.py +++ b/suite/auto-sync/src/autosync/ASUpdater.py @@ -56,21 +56,12 @@ def __init__( self.inc_list = inc_list self.wait_for_user = wait_for_user if USteps.ALL in steps: - if arch not in ["Xtensa"]: - self.steps = [ + self.steps = [ USteps.INC_GEN, USteps.TRANS, USteps.DIFF, - USteps.MC, USteps.PATCH_HEADER, - ] - else: - self.steps = [ - USteps.INC_GEN, - USteps.TRANS, - USteps.DIFF, - USteps.PATCH_HEADER, - ] + ] else: self.steps = steps self.copy_translated = copy_translated diff --git a/suite/auto-sync/src/autosync/MCUpdater.py b/suite/auto-sync/src/autosync/MCUpdater.py index 5737666d731..a55516b85fa 100755 --- a/suite/auto-sync/src/autosync/MCUpdater.py +++ b/suite/auto-sync/src/autosync/MCUpdater.py @@ -480,7 +480,9 @@ def extract_llvm_mc_cmds(self, cmds: str) -> list[LLVM_MC_Command]: def gen_all(self): log.info("Check prerequisites") disas_tests = self.mc_dir.joinpath(f"Disassembler/{self.arch}") - test_paths = [disas_tests, self.mc_dir.joinpath(self.arch)] + test_paths = [disas_tests] + if self.arch == "Xtensa": + test_paths.append(self.mc_dir.joinpath(self.arch)) self.check_prerequisites(test_paths) log.info("Generate MC regression tests") llvm_mc_cmds = self.run_llvm_lit( diff --git a/suite/cstest/src/test_run.c b/suite/cstest/src/test_run.c index 197c8b855cc..0d08d81aff5 100644 --- a/suite/cstest/src/test_run.c +++ b/suite/cstest/src/test_run.c @@ -123,7 +123,8 @@ static bool parse_input_options(const TestInput *input, cs_arch *arch, fprintf(stderr, "Too many options given in: '%s'. Maximum is: %" PRId64 "\n", - opt_str, (uint64_t)opt_arr_size); + opt_str, + (uint64_t)opt_arr_size); return false; } opt_arr[opt_idx++] = test_option_map[k].opt;