diff --git a/arch/Xtensa/XtensaDisassembler.c b/arch/Xtensa/XtensaDisassembler.c index 213d57a399..c4d9f1d6a4 100644 --- a/arch/Xtensa/XtensaDisassembler.c +++ b/arch/Xtensa/XtensaDisassembler.c @@ -95,6 +95,7 @@ static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, static DecodeStatus decodeCallOperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 18)(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, (SignExtend64((Imm << 2), 20))); return MCDisassembler_Success; } @@ -102,6 +103,7 @@ static DecodeStatus decodeCallOperand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeJumpOperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 18)(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, (SignExtend64((Imm), 18))); return MCDisassembler_Success; } @@ -114,14 +116,14 @@ static DecodeStatus decodeBranchOperand(MCInst *Inst, uint64_t Imm, case Xtensa_BGEZ: case Xtensa_BLTZ: case Xtensa_BNEZ: - + CS_ASSERT(CONCAT(isUInt, 12)(Imm) && "Invalid immediate"); if (!tryAddingSymbolicOperand( SignExtend64((Imm), 12) + 4 + Address, true, Address, 0, 3, Inst, Decoder)) MCOperand_CreateImm0(Inst, (SignExtend64((Imm), 12))); break; default: - + CS_ASSERT(CONCAT(isUInt, 8)(Imm) && "Invalid immediate"); if (!tryAddingSymbolicOperand( SignExtend64((Imm), 8) + 4 + Address, true, Address, 0, 3, Inst, Decoder)) @@ -133,6 +135,7 @@ static DecodeStatus decodeBranchOperand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeL32ROperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 16)(Imm) && "Invalid immediate"); MCOperand_CreateImm0( Inst, (SignExtend64(((Imm << 2) + 0x40000 + (Address & 0x3)), 17))); @@ -142,6 +145,7 @@ static DecodeStatus decodeL32ROperand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeImm8Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 8)(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, (SignExtend64((Imm), 8))); return MCDisassembler_Success; } @@ -149,6 +153,7 @@ static DecodeStatus decodeImm8Operand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeImm8_sh8Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 8)(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, (SignExtend64((Imm << 8), 16))); return MCDisassembler_Success; } @@ -156,6 +161,7 @@ static DecodeStatus decodeImm8_sh8Operand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeImm12Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 12)(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, (SignExtend64((Imm), 12))); return MCDisassembler_Success; } @@ -163,6 +169,7 @@ static DecodeStatus decodeImm12Operand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeUimm4Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 4)(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, (Imm)); return MCDisassembler_Success; } @@ -170,6 +177,7 @@ static DecodeStatus decodeUimm4Operand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeUimm5Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 5)(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, (Imm)); return MCDisassembler_Success; } @@ -177,6 +185,7 @@ static DecodeStatus decodeUimm5Operand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeImm1_16Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 4)(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, (Imm + 1)); return MCDisassembler_Success; } @@ -184,6 +193,7 @@ static DecodeStatus decodeImm1_16Operand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeShimm1_31Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 5)(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, (32 - Imm)); return MCDisassembler_Success; } @@ -193,6 +203,8 @@ static int64_t TableB4const[16] = { -1, 1, 2, 3, 4, 5, 6, 7, static DecodeStatus decodeB4constOperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 4)(Imm) && "Invalid immediate"); + MCOperand_CreateImm0(Inst, (TableB4const[Imm])); return MCDisassembler_Success; } @@ -202,6 +214,8 @@ static int64_t TableB4constu[16] = { 32768, 65536, 2, 3, 4, 5, 6, 7, static DecodeStatus decodeB4constuOperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 4)(Imm) && "Invalid immediate"); + MCOperand_CreateImm0(Inst, (TableB4constu[Imm])); return MCDisassembler_Success; } @@ -209,6 +223,7 @@ static DecodeStatus decodeB4constuOperand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeMem8Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 12)(Imm) && "Invalid immediate"); DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder); MCOperand_CreateImm0(Inst, ((Imm >> 4) & 0xff)); return MCDisassembler_Success; @@ -217,6 +232,7 @@ static DecodeStatus decodeMem8Operand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeMem16Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 12)(Imm) && "Invalid immediate"); DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder); MCOperand_CreateImm0(Inst, ((Imm >> 3) & 0x1fe)); return MCDisassembler_Success; @@ -225,6 +241,7 @@ static DecodeStatus decodeMem16Operand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeMem32Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 12)(Imm) && "Invalid immediate"); DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder); MCOperand_CreateImm0(Inst, ((Imm >> 2) & 0x3fc)); return MCDisassembler_Success; diff --git a/arch/Xtensa/XtensaInstPrinter.c b/arch/Xtensa/XtensaInstPrinter.c index 6317c69e13..a6862f18a6 100644 --- a/arch/Xtensa/XtensaInstPrinter.c +++ b/arch/Xtensa/XtensaInstPrinter.c @@ -35,6 +35,7 @@ #include "../../SStream.h" #include "./priv.h" #include "../../Mapping.h" +#include "XtensaMapping.h" #define CONCAT(a, b) CONCAT_(a, b) #define CONCAT_(a, b) a##_##b @@ -59,6 +60,7 @@ static void printOperand(MCInst *MI, int OpNum, SStream *O) static inline void printMemOperand(MCInst *MI, int OpNum, SStream *OS) { + add_cs_detail(MI, XTENSA_OP_GROUP_MEMOPERAND, OpNum); SStream_concat0(OS, getRegisterName(MCOperand_getReg( MCInst_getOperand(MI, (OpNum))))); SStream_concat0(OS, ", "); @@ -110,13 +112,16 @@ static inline void printCallOperand(MCInst *MI, int OpNum, SStream *OS) static inline void printL32RTarget(MCInst *MI, int OpNum, SStream *O) { + add_cs_detail(MI, XTENSA_OP_GROUP_L32RTARGET, OpNum); MCOperand *MC = MCInst_getOperand(MI, (OpNum)); if (MCOperand_isImm(MC)) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); int64_t InstrOff = Value & 0x3; Value -= InstrOff; - + CS_ASSERT( + (Value >= -262144 && Value <= -4) && + "Invalid argument, value must be in ranges [-262144,-4]"); Value += ((InstrOff + 0x3) & 0x4) - InstrOff; SStream_concat0(O, ". "); printInt64(O, Value); @@ -126,10 +131,13 @@ static inline void printL32RTarget(MCInst *MI, int OpNum, SStream *O) static inline void printImm8_AsmOperand(MCInst *MI, int OpNum, SStream *O) { + add_cs_detail(MI, XTENSA_OP_GROUP_IMM8_ASMOPERAND, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); - + CS_ASSERT( + CONCAT(isInt, 8)(Value) && + "Invalid argument, value must be in ranges [-128,127]"); printInt64(O, Value); } else { printOperand(MI, OpNum, O); @@ -138,10 +146,11 @@ static inline void printImm8_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printImm8_sh8_AsmOperand(MCInst *MI, int OpNum, SStream *O) { + add_cs_detail(MI, XTENSA_OP_GROUP_UIMM4_ASMOPERAND, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); - + CS_ASSERT((Value >= 0 && Value <= 15) && "Invalid argument"); printInt64(O, Value); } else printOperand(MI, OpNum, O); @@ -149,10 +158,11 @@ static inline void printImm8_sh8_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printImm12m_AsmOperand(MCInst *MI, int OpNum, SStream *O) { + add_cs_detail(MI, XTENSA_OP_GROUP_UIMM5_ASMOPERAND, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); - + CS_ASSERT((Value >= 0 && Value <= 31) && "Invalid argument"); printInt64(O, Value); } else printOperand(MI, OpNum, O); @@ -160,10 +170,12 @@ static inline void printImm12m_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printUimm4_AsmOperand(MCInst *MI, int OpNum, SStream *O) { + add_cs_detail(MI, XTENSA_OP_GROUP_SHIMM1_31_ASMOPERAND, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); - + CS_ASSERT((Value >= 1 && Value <= 31) && + "Invalid argument, value must be in range [1,31]"); printInt64(O, Value); } else printOperand(MI, OpNum, O); @@ -171,10 +183,12 @@ static inline void printUimm4_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printUimm5_AsmOperand(MCInst *MI, int OpNum, SStream *O) { + add_cs_detail(MI, XTENSA_OP_GROUP_IMM1_16_ASMOPERAND, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); - + CS_ASSERT((Value >= 1 && Value <= 16) && + "Invalid argument, value must be in range [1,16]"); printInt64(O, Value); } else printOperand(MI, OpNum, O); @@ -182,10 +196,12 @@ static inline void printUimm5_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printShimm1_31_AsmOperand(MCInst *MI, int OpNum, SStream *O) { + add_cs_detail(MI, XTENSA_OP_GROUP_OFFSET8M8_ASMOPERAND, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); - + CS_ASSERT((Value >= 0 && Value <= 255) && + "Invalid argument, value must be in range [0,255]"); printInt64(O, Value); } else printOperand(MI, OpNum, O); @@ -193,10 +209,13 @@ static inline void printShimm1_31_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printImm1_16_AsmOperand(MCInst *MI, int OpNum, SStream *O) { + add_cs_detail(MI, XTENSA_OP_GROUP_OFFSET8M16_ASMOPERAND, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); - + CS_ASSERT( + (Value >= 0 && Value <= 510 && ((Value & 0x1) == 0)) && + "Invalid argument, value must be multiples of two in range [0,510]"); printInt64(O, Value); } else printOperand(MI, OpNum, O); @@ -204,6 +223,7 @@ static inline void printImm1_16_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printB4const_AsmOperand(MCInst *MI, int OpNum, SStream *O) { + add_cs_detail(MI, XTENSA_OP_GROUP_B4CONST_ASMOPERAND, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); @@ -227,7 +247,7 @@ static inline void printB4const_AsmOperand(MCInst *MI, int OpNum, SStream *O) case 256: break; default: - break; + CS_ASSERT((0) && "Invalid B4const argument"); } printInt64(O, Value); } else @@ -236,6 +256,7 @@ static inline void printB4const_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printB4constu_AsmOperand(MCInst *MI, int OpNum, SStream *O) { + add_cs_detail(MI, XTENSA_OP_GROUP_B4CONSTU_ASMOPERAND, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); @@ -259,7 +280,7 @@ static inline void printB4constu_AsmOperand(MCInst *MI, int OpNum, SStream *O) case 256: break; default: - break; + CS_ASSERT((0) && "Invalid B4constu argument"); } printInt64(O, Value); } else diff --git a/arch/Xtensa/XtensaMapping.c b/arch/Xtensa/XtensaMapping.c index 07bb09e713..881b2d1afa 100644 --- a/arch/Xtensa/XtensaMapping.c +++ b/arch/Xtensa/XtensaMapping.c @@ -12,6 +12,7 @@ #include "XtensaDisassembler.h" #include "XtensaInstPrinter.h" #include "priv.h" +#include "XtensaMapping.h" #ifndef CAPSTONE_DIET @@ -207,3 +208,41 @@ void Xtensa_reg_access(const cs_insn *insn, cs_regs regs_read, *regs_write_count = write_count; } #endif + +void Xtensa_add_cs_detail(MCInst *MI, xtensa_op_group op_group, va_list args) +{ + CS_ASSERT(0 && "unimplemented"); + switch (op_group) { + case XTENSA_OP_GROUP_OPERAND: + break; + case XTENSA_OP_GROUP_IMM8_ASMOPERAND: { + unsigned OpNum = va_arg(args, unsigned); + } + case XTENSA_OP_GROUP_IMM8_SH8_ASMOPERAND: + break; + case XTENSA_OP_GROUP_BRANCHTARGET: + break; + case XTENSA_OP_GROUP_UIMM5_ASMOPERAND: + break; + case XTENSA_OP_GROUP_B4CONST_ASMOPERAND: + break; + case XTENSA_OP_GROUP_B4CONSTU_ASMOPERAND: + break; + case XTENSA_OP_GROUP_CALLOPERAND: + break; + case XTENSA_OP_GROUP_IMM1_16_ASMOPERAND: + break; + case XTENSA_OP_GROUP_JUMPTARGET: + break; + case XTENSA_OP_GROUP_MEMOPERAND: + break; + case XTENSA_OP_GROUP_L32RTARGET: + break; + case XTENSA_OP_GROUP_IMM12M_ASMOPERAND: + break; + case XTENSA_OP_GROUP_SHIMM1_31_ASMOPERAND: + break; + case XTENSA_OP_GROUP_UIMM4_ASMOPERAND: + break; + } +} \ No newline at end of file diff --git a/arch/Xtensa/XtensaMapping.h b/arch/Xtensa/XtensaMapping.h index acc60ad9b3..bd5b4b99f9 100644 --- a/arch/Xtensa/XtensaMapping.h +++ b/arch/Xtensa/XtensaMapping.h @@ -22,4 +22,16 @@ void Xtensa_reg_access(const cs_insn *insn, cs_regs regs_read, uint8_t *regs_write_count); #endif +void Xtensa_add_cs_detail(MCInst *MI, xtensa_op_group op_group, va_list args); + +static inline void add_cs_detail(MCInst *MI, xtensa_op_group op_group, ...) +{ + if (!MI->flat_insn->detail) + return; + va_list args; + va_start(args, op_group); + Xtensa_add_cs_detail(MI, op_group, args); + va_end(args); +} + #endif diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py b/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py index f826f694a0..6c5d8d7a44 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py @@ -315,6 +315,7 @@ def get_Xtensa_includes(filename: str) -> bytes: return """ #include "../../MCInstPrinter.h" #include "../../SStream.h" +#include "XtensaMapping.h" #include "priv.h" """ case _: diff --git a/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json b/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json index 3bb9163df8..430c31eba4 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json +++ b/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json @@ -1500,5 +1500,43 @@ "new_hash": "02eaaa869cf975da8203666135470c113ad9246dd2f73061dbf6ee1706683299", "edit": "" } + }, + "XtensaDisassembler.c": { + "\"../../SStream.h\"": { + "apply_type": "OLD", + "old_hash": "2b45d68382f855f8fdc8a7cf177cda2d4dee75318bab9e1304026375ba05284f", + "new_hash": "", + "edit": "" + }, + "\"../../cs_priv.h\"": { + "apply_type": "OLD", + "old_hash": "9cf77913cc1ba047983eb15f5e6dce657fb26b09f32757f02de5df2cf4023d87", + "new_hash": "", + "edit": "" + }, + "\"XtensaGenInstrInfo.inc\"": { + "apply_type": "OLD", + "old_hash": "7dada799dde9a9ea873fe6933799f19a60273bd85d56804c06e7e87b761c973d", + "new_hash": "", + "edit": "" + }, + "\"priv.h\"": { + "apply_type": "OLD", + "old_hash": "d09344b441eba2a943ba1323088ec14a8bad410b94e47900e170c51876794892", + "new_hash": "", + "edit": "" + }, + "DecodeSRRegisterClass": { + "apply_type": "OLD", + "old_hash": "21ddebca1aac12b568bfba25e971d02c3166147ff2ba8308e7f95e07bc754e28", + "new_hash": "0bfba6491089483244f115b4130ebe5c03d5572c8267bf015f704bb5fd1526a7", + "edit": "" + }, + "Xtensa_LLVM_getInstruction": { + "apply_type": "OLD", + "old_hash": "f62a9a80e3667fa51669fe7fa22da87b1c95bb1235e0840e5455069731ca42d1", + "new_hash": "", + "edit": "" + } } } \ No newline at end of file