diff --git a/MCInst.c b/MCInst.c index 8ffc2d2dbb..999093ce01 100644 --- a/MCInst.c +++ b/MCInst.c @@ -165,6 +165,12 @@ void MCOperand_setFPImm(MCOperand *op, double Val) op->FPImmVal = Val; } +MCExpr *MCOperand_getExpr(const MCOperand *MC) +{ + assert(0 && "unimplemented expr"); + return NULL; +} + MCOperand *MCOperand_CreateReg1(MCInst *mcInst, unsigned Reg) { MCOperand *op = &(mcInst->Operands[MCINST_CACHE]); diff --git a/MCInst.h b/MCInst.h index 5d24603abf..45ff30bc44 100644 --- a/MCInst.h +++ b/MCInst.h @@ -26,7 +26,7 @@ typedef struct MCInst MCInst; typedef struct cs_struct cs_struct; typedef struct MCOperand MCOperand; -typedef unsigned MCRegister; +typedef void MCExpr; /// MCOperand - Instances of this class represent operands of the MCInst class. /// This is a simple discriminated union. @@ -81,6 +81,8 @@ const MCInst *MCOperand_getInst(const MCOperand *op); void MCOperand_setInst(MCOperand *op, const MCInst *Val); +MCExpr *MCOperand_getExpr(const MCOperand *MC); + // create Reg operand in the next slot void MCOperand_CreateReg0(MCInst *inst, unsigned Reg); diff --git a/MCRegisterInfo.c b/MCRegisterInfo.c index 37889907e7..ce9a237a47 100644 --- a/MCRegisterInfo.c +++ b/MCRegisterInfo.c @@ -149,9 +149,3 @@ bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg) return (c->RegSet[Byte] & (1 << InByte)) != 0; } - -MCExpr *MCOperand_getExpr(const MCOperand *MC) -{ - assert(0 && "unimplemented expr"); - return NULL; -} diff --git a/MCRegisterInfo.h b/MCRegisterInfo.h index 60d8dffa04..a8a1cfd2af 100644 --- a/MCRegisterInfo.h +++ b/MCRegisterInfo.h @@ -20,7 +20,6 @@ #define CS_LLVM_MC_MCREGISTERINFO_H #include "capstone/platform.h" -#include "MCInst.h" #include "SStream.h" /// An unsigned integer type large enough to represent all physical registers, @@ -28,7 +27,6 @@ typedef int16_t MCPhysReg; typedef const MCPhysReg* iterator; typedef uint16_t MCRegister; -typedef void MCExpr; typedef struct MCRegisterClass2 { iterator RegsBegin; @@ -117,6 +115,4 @@ const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsi bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg); -MCExpr *MCOperand_getExpr(const MCOperand *MC); - #endif diff --git a/arch/Xtensa/XtensaDisassembler.c b/arch/Xtensa/XtensaDisassembler.c index 213d57a399..c4d9f1d6a4 100644 --- a/arch/Xtensa/XtensaDisassembler.c +++ b/arch/Xtensa/XtensaDisassembler.c @@ -95,6 +95,7 @@ static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, static DecodeStatus decodeCallOperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 18)(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, (SignExtend64((Imm << 2), 20))); return MCDisassembler_Success; } @@ -102,6 +103,7 @@ static DecodeStatus decodeCallOperand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeJumpOperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 18)(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, (SignExtend64((Imm), 18))); return MCDisassembler_Success; } @@ -114,14 +116,14 @@ static DecodeStatus decodeBranchOperand(MCInst *Inst, uint64_t Imm, case Xtensa_BGEZ: case Xtensa_BLTZ: case Xtensa_BNEZ: - + CS_ASSERT(CONCAT(isUInt, 12)(Imm) && "Invalid immediate"); if (!tryAddingSymbolicOperand( SignExtend64((Imm), 12) + 4 + Address, true, Address, 0, 3, Inst, Decoder)) MCOperand_CreateImm0(Inst, (SignExtend64((Imm), 12))); break; default: - + CS_ASSERT(CONCAT(isUInt, 8)(Imm) && "Invalid immediate"); if (!tryAddingSymbolicOperand( SignExtend64((Imm), 8) + 4 + Address, true, Address, 0, 3, Inst, Decoder)) @@ -133,6 +135,7 @@ static DecodeStatus decodeBranchOperand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeL32ROperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 16)(Imm) && "Invalid immediate"); MCOperand_CreateImm0( Inst, (SignExtend64(((Imm << 2) + 0x40000 + (Address & 0x3)), 17))); @@ -142,6 +145,7 @@ static DecodeStatus decodeL32ROperand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeImm8Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 8)(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, (SignExtend64((Imm), 8))); return MCDisassembler_Success; } @@ -149,6 +153,7 @@ static DecodeStatus decodeImm8Operand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeImm8_sh8Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 8)(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, (SignExtend64((Imm << 8), 16))); return MCDisassembler_Success; } @@ -156,6 +161,7 @@ static DecodeStatus decodeImm8_sh8Operand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeImm12Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 12)(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, (SignExtend64((Imm), 12))); return MCDisassembler_Success; } @@ -163,6 +169,7 @@ static DecodeStatus decodeImm12Operand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeUimm4Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 4)(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, (Imm)); return MCDisassembler_Success; } @@ -170,6 +177,7 @@ static DecodeStatus decodeUimm4Operand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeUimm5Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 5)(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, (Imm)); return MCDisassembler_Success; } @@ -177,6 +185,7 @@ static DecodeStatus decodeUimm5Operand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeImm1_16Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 4)(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, (Imm + 1)); return MCDisassembler_Success; } @@ -184,6 +193,7 @@ static DecodeStatus decodeImm1_16Operand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeShimm1_31Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 5)(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, (32 - Imm)); return MCDisassembler_Success; } @@ -193,6 +203,8 @@ static int64_t TableB4const[16] = { -1, 1, 2, 3, 4, 5, 6, 7, static DecodeStatus decodeB4constOperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 4)(Imm) && "Invalid immediate"); + MCOperand_CreateImm0(Inst, (TableB4const[Imm])); return MCDisassembler_Success; } @@ -202,6 +214,8 @@ static int64_t TableB4constu[16] = { 32768, 65536, 2, 3, 4, 5, 6, 7, static DecodeStatus decodeB4constuOperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 4)(Imm) && "Invalid immediate"); + MCOperand_CreateImm0(Inst, (TableB4constu[Imm])); return MCDisassembler_Success; } @@ -209,6 +223,7 @@ static DecodeStatus decodeB4constuOperand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeMem8Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 12)(Imm) && "Invalid immediate"); DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder); MCOperand_CreateImm0(Inst, ((Imm >> 4) & 0xff)); return MCDisassembler_Success; @@ -217,6 +232,7 @@ static DecodeStatus decodeMem8Operand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeMem16Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 12)(Imm) && "Invalid immediate"); DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder); MCOperand_CreateImm0(Inst, ((Imm >> 3) & 0x1fe)); return MCDisassembler_Success; @@ -225,6 +241,7 @@ static DecodeStatus decodeMem16Operand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeMem32Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + CS_ASSERT(CONCAT(isUInt, 12)(Imm) && "Invalid immediate"); DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder); MCOperand_CreateImm0(Inst, ((Imm >> 2) & 0x3fc)); return MCDisassembler_Success; diff --git a/arch/Xtensa/XtensaInstPrinter.c b/arch/Xtensa/XtensaInstPrinter.c index 6317c69e13..dbbcd92574 100644 --- a/arch/Xtensa/XtensaInstPrinter.c +++ b/arch/Xtensa/XtensaInstPrinter.c @@ -35,6 +35,7 @@ #include "../../SStream.h" #include "./priv.h" #include "../../Mapping.h" +#include "XtensaMapping.h" #define CONCAT(a, b) CONCAT_(a, b) #define CONCAT_(a, b) a##_##b @@ -59,6 +60,7 @@ static void printOperand(MCInst *MI, int OpNum, SStream *O) static inline void printMemOperand(MCInst *MI, int OpNum, SStream *OS) { + add_cs_detail(MI, XTENSA_OP_GROUP_MEMOPERAND, OpNum); SStream_concat0(OS, getRegisterName(MCOperand_getReg( MCInst_getOperand(MI, (OpNum))))); SStream_concat0(OS, ", "); @@ -67,6 +69,7 @@ static inline void printMemOperand(MCInst *MI, int OpNum, SStream *OS) static inline void printBranchTarget(MCInst *MI, int OpNum, SStream *OS) { + add_cs_detail(MI, XTENSA_OP_GROUP_BRANCHTARGET, OpNum); MCOperand *MC = MCInst_getOperand(MI, (OpNum)); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Val = MCOperand_getImm(MC) + 4; @@ -81,6 +84,7 @@ static inline void printBranchTarget(MCInst *MI, int OpNum, SStream *OS) static inline void printJumpTarget(MCInst *MI, int OpNum, SStream *OS) { + add_cs_detail(MI, XTENSA_OP_GROUP_JUMPTARGET, OpNum); MCOperand *MC = MCInst_getOperand(MI, (OpNum)); if (MCOperand_isImm(MC)) { int64_t Val = MCOperand_getImm(MC) + 4; @@ -96,6 +100,7 @@ static inline void printJumpTarget(MCInst *MI, int OpNum, SStream *OS) static inline void printCallOperand(MCInst *MI, int OpNum, SStream *OS) { + add_cs_detail(MI, XTENSA_OP_GROUP_CALLOPERAND, OpNum); MCOperand *MC = MCInst_getOperand(MI, (OpNum)); if (MCOperand_isImm(MC)) { int64_t Val = MCOperand_getImm(MC) + 4; @@ -110,13 +115,16 @@ static inline void printCallOperand(MCInst *MI, int OpNum, SStream *OS) static inline void printL32RTarget(MCInst *MI, int OpNum, SStream *O) { + add_cs_detail(MI, XTENSA_OP_GROUP_L32RTARGET, OpNum); MCOperand *MC = MCInst_getOperand(MI, (OpNum)); if (MCOperand_isImm(MC)) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); int64_t InstrOff = Value & 0x3; Value -= InstrOff; - + CS_ASSERT( + (Value >= -262144 && Value <= -4) && + "Invalid argument, value must be in ranges [-262144,-4]"); Value += ((InstrOff + 0x3) & 0x4) - InstrOff; SStream_concat0(O, ". "); printInt64(O, Value); @@ -126,10 +134,13 @@ static inline void printL32RTarget(MCInst *MI, int OpNum, SStream *O) static inline void printImm8_AsmOperand(MCInst *MI, int OpNum, SStream *O) { + add_cs_detail(MI, XTENSA_OP_GROUP_IMM8_ASMOPERAND, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); - + CS_ASSERT( + CONCAT(isInt, 8)(Value) && + "Invalid argument, value must be in ranges [-128,127]"); printInt64(O, Value); } else { printOperand(MI, OpNum, O); @@ -138,10 +149,14 @@ static inline void printImm8_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printImm8_sh8_AsmOperand(MCInst *MI, int OpNum, SStream *O) { + add_cs_detail(MI, XTENSA_OP_GROUP_IMM8_SH8_ASMOPERAND, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); - + CS_ASSERT( + (CONCAT(isInt, 16)(Value) && ((Value & 0xFF) == 0)) && + "Invalid argument, value must be multiples of 256 in range " + "[-32768,32512]"); printInt64(O, Value); } else printOperand(MI, OpNum, O); @@ -149,10 +164,13 @@ static inline void printImm8_sh8_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printImm12m_AsmOperand(MCInst *MI, int OpNum, SStream *O) { + add_cs_detail(MI, XTENSA_OP_GROUP_IMM12M_ASMOPERAND, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); - + CS_ASSERT( + (Value >= -2048 && Value <= 2047) && + "Invalid argument, value must be in ranges [-2048,2047]"); printInt64(O, Value); } else printOperand(MI, OpNum, O); @@ -160,10 +178,11 @@ static inline void printImm12m_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printUimm4_AsmOperand(MCInst *MI, int OpNum, SStream *O) { + add_cs_detail(MI, XTENSA_OP_GROUP_UIMM4_ASMOPERAND, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); - + CS_ASSERT((Value >= 0 && Value <= 15) && "Invalid argument"); printInt64(O, Value); } else printOperand(MI, OpNum, O); @@ -171,10 +190,11 @@ static inline void printUimm4_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printUimm5_AsmOperand(MCInst *MI, int OpNum, SStream *O) { + add_cs_detail(MI, XTENSA_OP_GROUP_UIMM5_ASMOPERAND, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); - + CS_ASSERT((Value >= 0 && Value <= 31) && "Invalid argument"); printInt64(O, Value); } else printOperand(MI, OpNum, O); @@ -182,10 +202,12 @@ static inline void printUimm5_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printShimm1_31_AsmOperand(MCInst *MI, int OpNum, SStream *O) { + add_cs_detail(MI, XTENSA_OP_GROUP_SHIMM1_31_ASMOPERAND, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); - + CS_ASSERT((Value >= 1 && Value <= 31) && + "Invalid argument, value must be in range [1,31]"); printInt64(O, Value); } else printOperand(MI, OpNum, O); @@ -193,10 +215,12 @@ static inline void printShimm1_31_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printImm1_16_AsmOperand(MCInst *MI, int OpNum, SStream *O) { + add_cs_detail(MI, XTENSA_OP_GROUP_IMM1_16_ASMOPERAND, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); - + CS_ASSERT((Value >= 1 && Value <= 16) && + "Invalid argument, value must be in range [1,16]"); printInt64(O, Value); } else printOperand(MI, OpNum, O); @@ -204,6 +228,7 @@ static inline void printImm1_16_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printB4const_AsmOperand(MCInst *MI, int OpNum, SStream *O) { + add_cs_detail(MI, XTENSA_OP_GROUP_B4CONST_ASMOPERAND, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); @@ -227,7 +252,7 @@ static inline void printB4const_AsmOperand(MCInst *MI, int OpNum, SStream *O) case 256: break; default: - break; + CS_ASSERT((0) && "Invalid B4const argument"); } printInt64(O, Value); } else @@ -236,6 +261,7 @@ static inline void printB4const_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printB4constu_AsmOperand(MCInst *MI, int OpNum, SStream *O) { + add_cs_detail(MI, XTENSA_OP_GROUP_B4CONSTU_ASMOPERAND, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); @@ -259,7 +285,7 @@ static inline void printB4constu_AsmOperand(MCInst *MI, int OpNum, SStream *O) case 256: break; default: - break; + CS_ASSERT((0) && "Invalid B4constu argument"); } printInt64(O, Value); } else diff --git a/arch/Xtensa/XtensaMapping.c b/arch/Xtensa/XtensaMapping.c index 07bb09e713..3969b4dcea 100644 --- a/arch/Xtensa/XtensaMapping.c +++ b/arch/Xtensa/XtensaMapping.c @@ -12,6 +12,7 @@ #include "XtensaDisassembler.h" #include "XtensaInstPrinter.h" #include "priv.h" +#include "XtensaMapping.h" #ifndef CAPSTONE_DIET @@ -207,3 +208,40 @@ void Xtensa_reg_access(const cs_insn *insn, cs_regs regs_read, *regs_write_count = write_count; } #endif + +void Xtensa_add_cs_detail(MCInst *MI, xtensa_op_group op_group, va_list args) +{ + CS_ASSERT(0 && "unimplemented"); + switch (op_group) { + case XTENSA_OP_GROUP_OPERAND: + break; + case XTENSA_OP_GROUP_IMM8_ASMOPERAND: + break; + case XTENSA_OP_GROUP_IMM8_SH8_ASMOPERAND: + break; + case XTENSA_OP_GROUP_BRANCHTARGET: + break; + case XTENSA_OP_GROUP_UIMM5_ASMOPERAND: + break; + case XTENSA_OP_GROUP_B4CONST_ASMOPERAND: + break; + case XTENSA_OP_GROUP_B4CONSTU_ASMOPERAND: + break; + case XTENSA_OP_GROUP_CALLOPERAND: + break; + case XTENSA_OP_GROUP_IMM1_16_ASMOPERAND: + break; + case XTENSA_OP_GROUP_JUMPTARGET: + break; + case XTENSA_OP_GROUP_MEMOPERAND: + break; + case XTENSA_OP_GROUP_L32RTARGET: + break; + case XTENSA_OP_GROUP_IMM12M_ASMOPERAND: + break; + case XTENSA_OP_GROUP_SHIMM1_31_ASMOPERAND: + break; + case XTENSA_OP_GROUP_UIMM4_ASMOPERAND: + break; + } +} \ No newline at end of file diff --git a/arch/Xtensa/XtensaMapping.h b/arch/Xtensa/XtensaMapping.h index acc60ad9b3..bd5b4b99f9 100644 --- a/arch/Xtensa/XtensaMapping.h +++ b/arch/Xtensa/XtensaMapping.h @@ -22,4 +22,16 @@ void Xtensa_reg_access(const cs_insn *insn, cs_regs regs_read, uint8_t *regs_write_count); #endif +void Xtensa_add_cs_detail(MCInst *MI, xtensa_op_group op_group, va_list args); + +static inline void add_cs_detail(MCInst *MI, xtensa_op_group op_group, ...) +{ + if (!MI->flat_insn->detail) + return; + va_list args; + va_start(args, op_group); + Xtensa_add_cs_detail(MI, op_group, args); + va_end(args); +} + #endif diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py b/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py index 2dd66bf9fd..855e9befa1 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py @@ -314,6 +314,7 @@ def get_Xtensa_includes(filename: str) -> bytes: return """ #include "../../MCInstPrinter.h" #include "../../SStream.h" +#include "XtensaMapping.h" #include "priv.h" """ case _: diff --git a/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json b/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json index 8fe03810d4..9d3cdd2605 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json +++ b/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json @@ -2376,5 +2376,179 @@ "new_hash": "b148e4b22d7b4797a64a9a818430da372d8224dee020bf5ec049c07677bff5cc", "edit": "" } + }, + "XtensaDisassembler.c": { + "\"../../SStream.h\"": { + "apply_type": "OLD", + "old_hash": "2b45d68382f855f8fdc8a7cf177cda2d4dee75318bab9e1304026375ba05284f", + "new_hash": "", + "edit": "" + }, + "\"../../cs_priv.h\"": { + "apply_type": "OLD", + "old_hash": "9cf77913cc1ba047983eb15f5e6dce657fb26b09f32757f02de5df2cf4023d87", + "new_hash": "", + "edit": "" + }, + "\"XtensaGenInstrInfo.inc\"": { + "apply_type": "OLD", + "old_hash": "7dada799dde9a9ea873fe6933799f19a60273bd85d56804c06e7e87b761c973d", + "new_hash": "", + "edit": "" + }, + "\"priv.h\"": { + "apply_type": "OLD", + "old_hash": "d09344b441eba2a943ba1323088ec14a8bad410b94e47900e170c51876794892", + "new_hash": "", + "edit": "" + }, + "DecodeSRRegisterClass": { + "apply_type": "OLD", + "old_hash": "21ddebca1aac12b568bfba25e971d02c3166147ff2ba8308e7f95e07bc754e28", + "new_hash": "0bfba6491089483244f115b4130ebe5c03d5572c8267bf015f704bb5fd1526a7", + "edit": "" + }, + "Xtensa_LLVM_getInstruction": { + "apply_type": "OLD", + "old_hash": "f62a9a80e3667fa51669fe7fa22da87b1c95bb1235e0840e5455069731ca42d1", + "new_hash": "", + "edit": "" + }, + "getInstruction": { + "apply_type": "OLD", + "old_hash": "50b6a904fc89bab054302112bd312dff8befdca7e0fdeebbfdc5d37cb49a2eeb", + "new_hash": "9215f65202a5f06de4718f9562adc149b5271358b49ce03be887dde2fdf03a25", + "edit": "" + }, + "readInstruction24": { + "apply_type": "OLD", + "old_hash": "496be4020feedac98bcb88b969c1e9a2013f664120193b45b76ff4a683e12d0d", + "new_hash": "2c39773dba873ff597df8420c2a710ecd3604ecb232406dc8b2f20bc3a11e655", + "edit": "" + }, + "tryAddingSymbolicOperand": { + "apply_type": "OLD", + "old_hash": "abfdc1e7fb69748a05a49a9829618b7ff43e913c7a46476c5a5e69151e44872c", + "new_hash": "b1a20345c1f90c2ef792825a3ecd379a856dca51240a92c3b9ce3a3685f09e2a", + "edit": "" + } + }, + "XtensaInstPrinter.c": { + "\"../../MCInstPrinter.h\"": { + "apply_type": "OLD", + "old_hash": "ea06257675896d185a423f8471328a8b98e74c260aad3e2e614d0ef48a744004", + "new_hash": "", + "edit": "" + }, + "\"../../Mapping.h\"": { + "apply_type": "OLD", + "old_hash": "204ac68dcb32024c325b99a0843719c321ab57c60c41b12adbea497c20b7d436", + "new_hash": "", + "edit": "" + }, + "\"../../SStream.h\"": { + "apply_type": "OLD", + "old_hash": "2b45d68382f855f8fdc8a7cf177cda2d4dee75318bab9e1304026375ba05284f", + "new_hash": "", + "edit": "" + }, + "\"./priv.h\"": { + "apply_type": "OLD", + "old_hash": "f5f8c480fe3869886ac96a2b8b2567c6056d7a0054da06433dee8e916abbe752", + "new_hash": "", + "edit": "" + }, + "\"XtensaMapping.h\"": { + "apply_type": "OLD", + "old_hash": "5dc6afd5c4beb43ecf77407bd50c579ace7cc07013610ee1e72933981da27ee2", + "new_hash": "", + "edit": "" + }, + "Xtensa_LLVM_getRegisterName": { + "apply_type": "OLD", + "old_hash": "87e2ae763d6d60ffd9da21d1b70f147c552cb75960b11ae98b8b21fe58bb938c", + "new_hash": "", + "edit": "" + }, + "Xtensa_LLVM_printInstruction": { + "apply_type": "OLD", + "old_hash": "1407d0fd0871a19025128731e3438bbff398ff173720e14f58cc1dbc781e5d51", + "new_hash": "", + "edit": "" + }, + "printBranchTarget": { + "apply_type": "NEW", + "old_hash": "c91f9d98415c1c413489ef360bc11ebb11b6f9e3b1564d4b57d0577c0a6feaa8", + "new_hash": "760223784267d403ac29f9ed51c2a30ff2ef1ddf9679b59db71b741f23c03719", + "edit": "" + }, + "printCallOperand": { + "apply_type": "NEW", + "old_hash": "62f875bf3eae5d3502f03df40ff473ddd838e38c87711a1fb5922d41960e74ed", + "new_hash": "5e936d44076c6ab4dfb8bf579b368f7107954dd391ea5f82d489afbe26184985", + "edit": "" + }, + "printImm12m_AsmOperand": { + "apply_type": "NEW", + "old_hash": "a656e5282b4444835dc20ffb645e92c51b5512ed43aabb7c9f2eafa1d2c81a76", + "new_hash": "64a9511d7f18e2fce3b4d08179b8cb6681d1e5df195241706a30d00c3ea2288e", + "edit": "" + }, + "printImm1_16_AsmOperand": { + "apply_type": "NEW", + "old_hash": "4a34c1913614bdaee2795f1c94d395b78be60f4d1ae84a0f28ea0e8a573381f9", + "new_hash": "c9956b1881ed5107439d2e4606cec93870837a3390436264a6e0c66762b68a5c", + "edit": "" + }, + "printImm8_sh8_AsmOperand": { + "apply_type": "NEW", + "old_hash": "9affee556485b99036667d0fde115610b9b67037c5ffdfedf9f5eb379b89c146", + "new_hash": "e4ab93bab36ba4c3436618523e3ff14b330819652e4cada4f19001ad63e92560", + "edit": "" + }, + "printJumpTarget": { + "apply_type": "NEW", + "old_hash": "b3fb61b967ddbdcd4ba31c0d7f6cbdb5b52880eba2d0f3b6961cb8736d65e6e0", + "new_hash": "0810cb753da2c503ec8cf969c4fa7bfb9f47fd6a9d66a83eb2c8b0166489512f", + "edit": "" + }, + "printL32RTarget": { + "apply_type": "NEW", + "old_hash": "518eb907a827efe2ae569b32ec9acfda29bd106c28f53a997fa40233c84f5433", + "new_hash": "66fcd5c6ce5d625014bffc3c23bdab57a78b467dabfe3bdcb5d67af2cdfc8192", + "edit": "" + }, + "printOperand": { + "apply_type": "OLD", + "old_hash": "1c19f6735e6c56ef62a9ce8eabe0a2f50e530fc6efb505b30de99a28b8299f6c", + "new_hash": "", + "edit": "" + }, + "printShimm1_31_AsmOperand": { + "apply_type": "NEW", + "old_hash": "a87790f5ac96dd626e1ae77a2949ff6ca9f3ac042b4ec87069b5b20e5bc43ba6", + "new_hash": "0a881b7568ff8a62cbf47caef513cabd32928af5cd182584da59a9be618b6c2e", + "edit": "" + }, + "printUimm4_AsmOperand": { + "apply_type": "NEW", + "old_hash": "d8dbc1a930c08cbb2047c4462f6102ce7a9dc516754ee06d69ed88ceb3624c64", + "new_hash": "3ba7c11490ec5eacc67595df5d26db88c4db327dc12c06f91349a29b3a31320c", + "edit": "" + }, + "printUimm5_AsmOperand": { + "apply_type": "NEW", + "old_hash": "0c4dd11b6282b42f5e08458fe206ef5f34e738626f5dbf57521355f96dd820a4", + "new_hash": "5c8fe6e58c1463f1556d33c60896696340eb444e5938270d5e23c9df6a1ab4e8", + "edit": "" + } + }, + "XtensaInstPrinter.h": { + "\"priv.h\"": { + "apply_type": "OLD", + "old_hash": "d09344b441eba2a943ba1323088ec14a8bad410b94e47900e170c51876794892", + "new_hash": "", + "edit": "" + } } } \ No newline at end of file