From 2cdb9e3607e1844f6796d9ec16251d89af27dce5 Mon Sep 17 00:00:00 2001 From: billow Date: Fri, 11 Oct 2024 17:44:36 +0800 Subject: [PATCH] Fix Branch Target --- arch/Xtensa/XtensaDisassembler.c | 2 +- arch/Xtensa/XtensaMapping.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/Xtensa/XtensaDisassembler.c b/arch/Xtensa/XtensaDisassembler.c index df56c75aa4a..6e3dee49c2b 100644 --- a/arch/Xtensa/XtensaDisassembler.c +++ b/arch/Xtensa/XtensaDisassembler.c @@ -90,7 +90,7 @@ static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, { // return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, // Offset, /*OpSize=*/0, InstSize); - return true; + return false; } static DecodeStatus decodeCallOperand(MCInst *Inst, uint64_t Imm, diff --git a/arch/Xtensa/XtensaMapping.c b/arch/Xtensa/XtensaMapping.c index c4a01a703a3..78828d88f11 100644 --- a/arch/Xtensa/XtensaMapping.c +++ b/arch/Xtensa/XtensaMapping.c @@ -195,8 +195,8 @@ void Xtensa_add_cs_detail(MCInst *MI, xtensa_op_group op_group, va_list args) case XTENSA_OP_GROUP_CALLOPERAND: { int64_t val = MCOperand_getImm(MCInst_getOperand(MI, op_num)) + 4; - xop->type = XTENSA_OP_MEM_IMM; - xop->mem.base = (int32_t)val; + xop->type = XTENSA_OP_IMM; + xop->imm = (int32_t)val; } break; case XTENSA_OP_GROUP_L32RTARGET: { int64_t Value =