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vivado.log
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vivado.log
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#-----------------------------------------------------------
# Vivado v2013.4 (64-bit)
# SW Build 353583 on Mon Dec 9 17:49:19 MST 2013
# IP Build 208076 on Mon Dec 2 12:38:17 MST 2013
# Start of session at: Fri Apr 21 16:33:08 2017
# Process ID: 7004
# Log file: C:/Users/Ian/Documents/GitHub/project_tubii_7020/vivado.log
# Journal file: C:/Users/Ian/Documents/GitHub/project_tubii_7020\vivado.jou
#-----------------------------------------------------------
Attempting to get a license: Implementation
Feature available: Implementation
Loading parts and site information from C:/Xilinx/Vivado/2013.4/data/parts/arch.xml
Parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
start_gui
open_project {C:\Users\Ian\Documents\GitHub\project_tubii_7020\project_tubii_7020.xpr}
INFO: [Project 1-313] Project file moved from 'C:/Users/Ian/project_tubii_7020' since last save.
CRITICAL WARNING: [Project 1-311] Could not find the file 'C:/Users/Ian/Documents/GitHub/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/ip/system_buttonTrigger_0_0/system_buttonTrigger_0_0.upgrade_log', nor could it be found using path 'C:/Users/Ian/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/ip/system_buttonTrigger_0_0/system_buttonTrigger_0_0.upgrade_log'.
IP Repository Path: Could not find the directory 'C:/Users/Ian/Documents/GitHub/project_tubii_7020/sync_gtid_1.0', nor could it be found using path 'C:/Users/Ian/project_tubii_7020/sync_gtid_1.0'.
IP Repository Path: Could not find the directory 'C:/Users/Ian/Documents/GitHub/project_tubii_7020/SyncGTID_1.0', nor could it be found using path 'C:/Users/Ian/project_tubii_7020/SyncGTID_1.0'.
IP Repository Path: Could not find the directory 'C:/Users/Ian/Documents/GitHub/project_tubii_7020/tubii_triggers_1.0', nor could it be found using path 'C:/Users/Ian/project_tubii_7020/tubii_triggers_1.0'.
IP Repository Path: Could not find the directory 'C:/Users/Ian/Documents/GitHub/project_tubii_7020/tubii_triggers_1.0', nor could it be found using path 'C:/Users/Ian/project_tubii_7020/tubii_triggers_1.0'.
IP Repository Path: Could not find the directory 'C:/Users/Ian/Documents/GitHub/project_tubii_7020/ShiftReg_1.0', nor could it be found using path 'C:/Users/Ian/project_tubii_7020/ShiftReg_1.0'.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/triggers_2.0'.
WARNING: [IP_Flow 19-2207] Repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/triggers_2.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/triggers_2.0'.
WARNING: [IP_Flow 19-2207] Repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/triggers_2.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/triggers_2.0'.
WARNING: [IP_Flow 19-2207] Repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/triggers_2.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/triggers_2.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/prescaleSignal_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/sync_gtid_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/SyncGTID_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/triggers_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/tubii_triggers_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
WARNING: [IP_Flow 19-2207] Repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/tubii_triggers_1.0' already exists; ignoring attempt to add it again.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/tubii_triggers_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/ShiftRegisters_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/ShiftRegisters_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/ShiftRegisters_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/buttonTrigger_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/ShiftReg_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/implement_gtid_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/TrigWordDelay_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/oneshot_pulse_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/fifo_readout_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/counter_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/project_tubii_7020/ShiftRegs_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/countDisplay_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/comboTrigger_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/testPulser_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/project_tubii_7020/triggerOut_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/clockLogic_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/triggerSplit_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/testDelay_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/prescaleTrigger_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Ian/Documents/GitHub/project_tubii_7020/burstTrigger_1.0'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2013.4/data/ip'.
open_project: Time (s): cpu = 00:00:48 ; elapsed = 00:00:33 . Memory (MB): peak = 1242.008 ; gain = 456.625
open_bd_design {C:/Users/Ian/Documents/GitHub/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/system.bd}
Adding component instance block -- xilinx.com:ip:processing_system7:5.3 - processing_system7_0
Adding component instance block -- xilinx.com:ip:fifo_generator:11.0 - fifo_generator_0
INFO: [xilinx.com:ip:fifo_generator:11.0-5968] /fifo_generator_0Executing the post_config_ip from bd
Adding component instance block -- xilinx.com:user:countDisplay:1.0 - countDisplay_0
Adding component instance block -- xilinx.com:user:comboTrigger:1.0 - comboTrigger_0
Adding component instance block -- xilinx.com:user:ShiftRegisters:1.0 - ShiftRegisters_0
Adding component instance block -- xilinx.com:ip:xadc_wiz:3.0 - xadc_wiz_0
Adding component instance block -- xilinx.com:user:implement_gtid:1.0 - implement_gtid_0
Adding component instance block -- xilinx.com:user:fifo_readout:1.0 - fifo_readout_0
Adding component instance block -- xilinx.com:ip:util_vector_logic:1.0 - util_vector_logic_0
Adding component instance block -- xilinx.com:ip:util_reduced_logic:1.0 - util_reduced_logic_0
Adding component instance block -- xilinx.com:ip:xlconcat:1.0 - xlconcat_0
Adding component instance block -- xilinx.com:ip:xlconcat:1.0 - xlconcat_1
Adding component instance block -- xilinx.com:ip:util_vector_logic:1.0 - util_vector_logic_1
Adding component instance block -- xilinx.com:ip:util_reduced_logic:1.0 - util_reduced_logic_1
Adding component instance block -- xilinx.com:ip:util_vector_logic:1.0 - util_vector_logic_2
Adding component instance block -- xilinx.com:ip:util_reduced_logic:1.0 - util_reduced_logic_2
Adding component instance block -- xilinx.com:ip:util_vector_logic:1.0 - util_vector_logic_3
Adding component instance block -- xilinx.com:ip:util_vector_logic:1.0 - util_vector_logic_4
Adding component instance block -- xilinx.com:ip:util_reduced_logic:1.0 - util_reduced_logic_3
Adding component instance block -- xilinx.com:user:triggers:2.0 - triggers_0
Adding component instance block -- xilinx.com:ip:util_vector_logic:1.0 - util_vector_logic_5
Adding component instance block -- xilinx.com:user:prescaleTrigger:1.0 - prescaleTrigger_0
Adding component instance block -- xilinx.com:ip:util_reduced_logic:1.0 - util_reduced_logic_4
Adding component instance block -- xilinx.com:ip:util_vector_logic:1.0 - util_vector_logic_6
Adding component instance block -- xilinx.com:user:prescaleSignal:1.0 - prescaleSignal_0
Adding component instance block -- xilinx.com:user:prescaleSignal:1.0 - prescaleSignal_1
Adding component instance block -- xilinx.com:user:burstTrigger:1.0 - burstTrigger_0
Adding component instance block -- xilinx.com:ip:util_vector_logic:1.0 - util_vector_logic_7
Adding component instance block -- xilinx.com:ip:util_reduced_logic:1.0 - util_reduced_logic_5
Adding component instance block -- xilinx.com:ip:util_vector_logic:1.0 - util_vector_logic_8
Adding component instance block -- xilinx.com:ip:util_reduced_logic:1.0 - util_reduced_logic_6
Adding component instance block -- xilinx.com:ip:util_vector_logic:1.0 - util_vector_logic_9
Adding component instance block -- xilinx.com:user:testDelay:1.0 - genericDelay
Adding component instance block -- xilinx.com:user:testDelay:1.0 - gtDelay
Adding component instance block -- xilinx.com:user:testDelay:1.0 - smellieDelay
Adding component instance block -- xilinx.com:user:testDelay:1.0 - tellieDelay
Adding component instance block -- xilinx.com:user:testPulser:1.0 - MZ_Happy
Adding component instance block -- xilinx.com:user:testPulser:1.0 - genericPulser
Adding component instance block -- xilinx.com:user:testPulser:1.0 - smelliePulser
Adding component instance block -- xilinx.com:user:testPulser:1.0 - telliePulser
Adding component instance block -- xilinx.com:user:clockLogic:1.0 - clockLogic_0
Adding component instance block -- xilinx.com:user:testPulser:1.0 - testPulser_0
Adding component instance block -- xilinx.com:user:oneshot_pulse:1.0 - oneshot_pulse_0
Adding component instance block -- xilinx.com:user:oneshot_pulse:1.0 - oneshot_pulse_1
Adding component instance block -- xilinx.com:user:TrigWordDelay:1.0 - TrigWordDelay_0
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - tier2_xbar_0
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - tier2_xbar_1
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - tier2_xbar_2
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Successfully read diagram <system> from BD file <C:/Users/Ian/Documents/GitHub/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/system.bd>
open_bd_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 1401.762 ; gain = 98.164
disconnect_bd_net /testPulser_0_pulser_out2 [get_bd_pins xlconcat_0/In2]
connect_bd_net -net [get_bd_nets prescaleTrigger_0_s00_axi_trigout] [get_bd_pins xlconcat_0/In2] [get_bd_pins util_vector_logic_6/Res]
disconnect_bd_net /prescaleTrigger_0_s00_axi_trigout [get_bd_pins xlconcat_0/In3]
connect_bd_net -net [get_bd_nets testPulser_0_pulser_out2] [get_bd_pins xlconcat_0/In3] [get_bd_pins testPulser_0/pulser_out]
disconnect_bd_net /prescaleTrigger_0_s00_axi_trigout [get_bd_pins xlconcat_0/In2]
connect_bd_net -net [get_bd_nets testPulser_0_pulser_out2] [get_bd_pins xlconcat_0/In2] [get_bd_pins testPulser_0/pulser_out]
disconnect_bd_net /testPulser_0_pulser_out2 [get_bd_pins xlconcat_0/In3]
connect_bd_net -net [get_bd_nets prescaleTrigger_0_s00_axi_trigout] [get_bd_pins xlconcat_0/In3] [get_bd_pins util_vector_logic_6/Res]
disconnect_bd_net /processing_system7_0_FCLK_CLK0 [get_bd_pins testPulser_0/s00_axi_aclk]
connect_bd_net -net [get_bd_nets clk_in] [get_bd_ports Clk_in] [get_bd_pins testPulser_0/s00_axi_aclk]
disconnect_bd_net /processing_system7_0_FCLK_CLK0 [get_bd_pins genericPulser/s00_axi_aclk]
disconnect_bd_net /processing_system7_0_FCLK_CLK0 [get_bd_pins telliePulser/s00_axi_aclk]
disconnect_bd_net /processing_system7_0_FCLK_CLK0 [get_bd_pins smelliePulser/s00_axi_aclk]
connect_bd_net -net [get_bd_nets clk_in] [get_bd_ports Clk_in] [get_bd_pins genericPulser/s00_axi_aclk]
connect_bd_net -net [get_bd_nets clk_in] [get_bd_ports Clk_in] [get_bd_pins telliePulser/s00_axi_aclk]
connect_bd_net -net [get_bd_nets clk_in] [get_bd_ports Clk_in] [get_bd_pins smelliePulser/s00_axi_aclk]
disconnect_bd_net /processing_system7_0_FCLK_CLK0 [get_bd_pins tellieDelay/s00_axi_aclk]
disconnect_bd_net /processing_system7_0_FCLK_CLK0 [get_bd_pins smellieDelay/s00_axi_aclk]
disconnect_bd_net /processing_system7_0_FCLK_CLK0 [get_bd_pins genericDelay/s00_axi_aclk]
connect_bd_net -net [get_bd_nets clk_in] [get_bd_ports Clk_in] [get_bd_pins tellieDelay/s00_axi_aclk]
connect_bd_net -net [get_bd_nets clk_in] [get_bd_ports Clk_in] [get_bd_pins smellieDelay/s00_axi_aclk]
connect_bd_net -net [get_bd_nets clk_in] [get_bd_ports Clk_in] [get_bd_pins genericDelay/s00_axi_aclk]
disconnect_bd_net /processing_system7_0_FCLK_CLK0 [get_bd_pins axi_interconnect_0/M15_ACLK]
disconnect_bd_net /processing_system7_0_FCLK_CLK0 [get_bd_pins axi_interconnect_0/M17_ACLK]
disconnect_bd_net /processing_system7_0_FCLK_CLK0 [get_bd_pins axi_interconnect_0/M16_ACLK]
disconnect_bd_net /processing_system7_0_FCLK_CLK0 [get_bd_pins axi_interconnect_0/M12_ACLK]
disconnect_bd_net /processing_system7_0_FCLK_CLK0 [get_bd_pins axi_interconnect_0/M22_ACLK]
disconnect_bd_net /processing_system7_0_FCLK_CLK0 [get_bd_pins axi_interconnect_0/M14_ACLK]
disconnect_bd_net /processing_system7_0_FCLK_CLK0 [get_bd_pins axi_interconnect_0/M19_ACLK]
connect_bd_net -net [get_bd_nets clk_in] [get_bd_ports Clk_in] [get_bd_pins axi_interconnect_0/M22_ACLK]
connect_bd_net -net [get_bd_nets clk_in] [get_bd_ports Clk_in] [get_bd_pins axi_interconnect_0/M19_ACLK]
connect_bd_net -net [get_bd_nets clk_in] [get_bd_ports Clk_in] [get_bd_pins axi_interconnect_0/M17_ACLK]
connect_bd_net -net [get_bd_nets clk_in] [get_bd_ports Clk_in] [get_bd_pins axi_interconnect_0/M16_ACLK]
connect_bd_net -net [get_bd_nets clk_in] [get_bd_ports Clk_in] [get_bd_pins axi_interconnect_0/M15_ACLK]
connect_bd_net -net [get_bd_nets clk_in] [get_bd_ports Clk_in] [get_bd_pins axi_interconnect_0/M14_ACLK]
connect_bd_net -net [get_bd_nets clk_in] [get_bd_ports Clk_in] [get_bd_pins axi_interconnect_0/M12_ACLK]
validate_bd_design
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In0_width) on /xlconcat_0 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In1_width) on /xlconcat_0 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In6_width) on /xlconcat_0 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In7_width) on /xlconcat_0 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In0_width) on /xlconcat_1 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In1_width) on /xlconcat_1 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In0_width) on /xlconcat_1 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In1_width) on /xlconcat_1 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In0_width) on /xlconcat_0 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In1_width) on /xlconcat_0 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In6_width) on /xlconcat_0 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In7_width) on /xlconcat_0 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In0_width) on /xlconcat_1 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In1_width) on /xlconcat_1 that is set by user. Command ignored
validate_bd_design: Time (s): cpu = 00:00:51 ; elapsed = 00:00:35 . Memory (MB): peak = 1446.801 ; gain = 0.000
success
save_bd_design
Wrote : <C:/Users/Ian/Documents/GitHub/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/system.bd>
reset_run synth_1
reset_run: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1542.336 ; gain = 95.535
launch_runs synth_1
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In0_width) on /xlconcat_0 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In1_width) on /xlconcat_0 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In6_width) on /xlconcat_0 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In7_width) on /xlconcat_0 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In0_width) on /xlconcat_1 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In1_width) on /xlconcat_1 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In0_width) on /xlconcat_0 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In1_width) on /xlconcat_0 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In6_width) on /xlconcat_0 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In7_width) on /xlconcat_0 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In0_width) on /xlconcat_1 that is set by user. Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite parameter (In1_width) on /xlconcat_1 that is set by user. Command ignored
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified.
Please check your design and connect them if needed:
/xadc_wiz_0/vp_in
/xadc_wiz_0/vn_in
VHDL Output written to : system.vhd
VHDL Output written to : system_wrapper.vhd
Wrote : <C:/Users/Ian/Documents/GitHub/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/system.bd>
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_processing_system7_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /processing_system7_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_xbar_0'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_xbar_0' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/xbar .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_comboTrigger_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /comboTrigger_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_burstTrigger_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /burstTrigger_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_prescaleTrigger_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /prescaleTrigger_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_countDisplay_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /countDisplay_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_clockLogic_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /clockLogic_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_testDelay_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /genericDelay .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_testDelay_2_5'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /tellieDelay .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_testDelay_3_6'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /smellieDelay .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_testPulser_0_7'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /MZ_Happy .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_testDelay_0_7'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /gtDelay .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_testPulser_0_9'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /genericPulser .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_testPulser_0_10'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /telliePulser .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_testPulser_1_11'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /smelliePulser .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_fifo_generator_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /fifo_generator_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_fifo_readout_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /fifo_readout_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_oneshot_pulse_1_1'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /oneshot_pulse_1 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_oneshot_pulse_0_2'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /oneshot_pulse_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_TrigWordDelay_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /TrigWordDelay_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_implement_gtid_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /implement_gtid_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_ShiftRegisters_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /ShiftRegisters_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_triggers_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /triggers_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_xadc_wiz_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /xadc_wiz_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_vector_logic_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_vector_logic_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_reduced_logic_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_reduced_logic_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_xlconcat_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /xlconcat_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_xlconcat_1_6'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /xlconcat_1 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_vector_logic_1_1'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_vector_logic_1 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_reduced_logic_1_1'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_reduced_logic_1 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_vector_logic_2_2'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_vector_logic_2 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_reduced_logic_2_2'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_reduced_logic_2 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_prescaleSignal_0_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /prescaleSignal_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_vector_logic_3_3'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_vector_logic_3 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_vector_logic_4_4'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_vector_logic_4 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_reduced_logic_3_3'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_reduced_logic_3 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_vector_logic_5_5'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_vector_logic_5 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_reduced_logic_4_4'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_reduced_logic_4 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_prescaleSignal_1_1'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /prescaleSignal_1 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_vector_logic_6_6'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_vector_logic_6 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_vector_logic_7_7'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_vector_logic_7 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_reduced_logic_5_5'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_reduced_logic_5 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_vector_logic_8_8'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_vector_logic_8 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_reduced_logic_6_6'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_reduced_logic_6 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_vector_logic_9_9'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_vector_logic_9 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_testPulser_0_12'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block /testPulser_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_tier2_xbar_0_1523'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_tier2_xbar_0_1523' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/tier2_xbar_0 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_tier2_xbar_1_1524'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_tier2_xbar_1_1524' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/tier2_xbar_1 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_tier2_xbar_2_1525'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_tier2_xbar_2_1525' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/tier2_xbar_2 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_auto_cc_787'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_cc_787' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m02_couplers/auto_cc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_auto_cc_788'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_cc_788' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m03_couplers/auto_cc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_auto_cc_789'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_cc_789' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m12_couplers/auto_cc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_auto_cc_790'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_cc_790' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m14_couplers/auto_cc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_auto_cc_791'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_cc_791' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m15_couplers/auto_cc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_auto_cc_792'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_cc_792' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m16_couplers/auto_cc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_auto_cc_793'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_cc_793' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m17_couplers/auto_cc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_auto_cc_794'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_cc_794' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m19_couplers/auto_cc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_auto_cc_795'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_cc_795' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m21_couplers/auto_cc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_auto_cc_796'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_cc_796' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m22_couplers/auto_cc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_auto_cc_797'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_cc_797' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/m23_couplers/auto_cc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_auto_pc_146'...
WARNING: [IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_pc_146' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:fifo_generator:11.0' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [IP_Flow 19-616] The current project language is set to Verilog. However the IP definition 'xilinx.com:ip:blk_mem_gen:8.1' does not support 'Verilog Synthesis' output products, delivering 'VHDL Synthesis' output products instead.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/s00_couplers/auto_pc .
INFO: [BD 41-539] Not generating up to date 'Implementation' target for block design system
INFO: [BD 41-1029] Generation completed for the IP Integrator block /processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /axi_interconnect_0/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /comboTrigger_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /burstTrigger_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /prescaleTrigger_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /countDisplay_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /clockLogic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /genericDelay .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /tellieDelay .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /smellieDelay .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /MZ_Happy .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /gtDelay .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /genericPulser .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /telliePulser .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /smelliePulser .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /fifo_generator_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /fifo_readout_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /oneshot_pulse_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /oneshot_pulse_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /TrigWordDelay_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /implement_gtid_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /ShiftRegisters_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /triggers_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /xadc_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_vector_logic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_reduced_logic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /xlconcat_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /xlconcat_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_vector_logic_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_reduced_logic_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_vector_logic_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_reduced_logic_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /prescaleSignal_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_vector_logic_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_vector_logic_4 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_reduced_logic_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_vector_logic_5 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /util_reduced_logic_4 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block /prescaleSignal_1 .
INFO: [Common 17-14] Message 'BD 41-1029' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
[Fri Apr 21 16:47:37 2017] Launched synth_1...
Run output will be captured here: C:/Users/Ian/Documents/GitHub/project_tubii_7020/project_tubii_7020.runs/synth_1/runme.log
launch_runs: Time (s): cpu = 00:01:53 ; elapsed = 00:02:40 . Memory (MB): peak = 1557.832 ; gain = 15.496
launch_runs impl_1
[Fri Apr 21 17:08:20 2017] Launched impl_1...
Run output will be captured here: C:/Users/Ian/Documents/GitHub/project_tubii_7020/project_tubii_7020.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 1653.992 ; gain = 75.590
open_run impl_1
INFO: [Netlist 29-17] Analyzing 400 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2013.4
Loading clock regions from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/zynq/zynq/xc7z020/ClockRegion.xml
Loading clock buffers from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/zynq/zynq/xc7z020/ClockBuffers.xml
Loading clock placement rules from C:/Xilinx/Vivado/2013.4/data/parts/xilinx/zynq/ClockPlacerRules.xml
Loading package pin functions from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/zynq/PinFunctions.xml...
Loading package from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/zynq/zynq/xc7z020/clg400/Package.xml
Loading io standards from C:/Xilinx/Vivado/2013.4/data\./parts/xilinx/zynq/IOStandards.xml
Parsing XDC File [c:/Users/Ian/Documents/GitHub/project_tubii_7020/.Xil/Vivado-7004-Ian-Penn/dcp/system_wrapper.xdc]
Finished Parsing XDC File [c:/Users/Ian/Documents/GitHub/project_tubii_7020/.Xil/Vivado-7004-Ian-Penn/dcp/system_wrapper.xdc]
Reading XDEF placement.
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2366.125 ; gain = 0.000
Restoring placement.
Restored 6863 out of 6863 XDEF sites from archive | CPU: 6.000000 secs | Memory: 0.000000 MB |
INFO: [Opt 31-138] Pushed 0 inverter(s).
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files:
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 286 instances were transformed.
RAM16X1D => RAM16X1D (RAMD32, RAMD32, GND): 22 instances
RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 264 instances
open_run: Time (s): cpu = 00:01:15 ; elapsed = 00:01:23 . Memory (MB): peak = 2501.496 ; gain = 831.945
export_hardware [get_files C:/Users/Ian/Documents/GitHub/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/system.bd]
Exporting to file C:/Users/Ian/Documents/GitHub/project_tubii_7020/project_tubii_7020.sdk/SDK/SDK_Export/hw/system.xml
export_hardware: Time (s): cpu = 00:00:18 ; elapsed = 00:00:29 . Memory (MB): peak = 2526.453 ; gain = 22.820
launch_runs impl_1 -to_step write_bitstream
[Fri Apr 21 17:28:05 2017] Launched impl_1...
Run output will be captured here: C:/Users/Ian/Documents/GitHub/project_tubii_7020/project_tubii_7020.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2588.281 ; gain = 61.828
export_hardware [get_files C:/Users/Ian/Documents/GitHub/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/system.bd] [get_runs impl_1] -bitstream
WARNING: [Vivado 12-690] Backannotated BMM file does not exist in the run dir:C:/Users/Ian/Documents/GitHub/project_tubii_7020/project_tubii_7020.runs/impl_1/system_wrapper_bd.bmm
Exporting to file C:/Users/Ian/Documents/GitHub/project_tubii_7020/project_tubii_7020.sdk/SDK/SDK_Export/hw/system.xml
INFO: [BD 41-436] exporting bit file 'C:/Users/Ian/Documents/GitHub/project_tubii_7020/project_tubii_7020.runs/impl_1/system_wrapper.bit'...
export_hardware: Time (s): cpu = 00:00:30 ; elapsed = 00:01:05 . Memory (MB): peak = 2631.395 ; gain = 26.668
export_hardware [get_files C:/Users/Ian/Documents/GitHub/project_tubii_7020/project_tubii_7020.srcs/sources_1/bd/system/system.bd] [get_runs impl_1] -bitstream
WARNING: [Vivado 12-690] Backannotated BMM file does not exist in the run dir:C:/Users/Ian/Documents/GitHub/project_tubii_7020/project_tubii_7020.runs/impl_1/system_wrapper_bd.bmm
Exporting to file C:/Users/Ian/Documents/GitHub/project_tubii_7020/project_tubii_7020.sdk/SDK/SDK_Export/hw/system.xml
INFO: [BD 41-436] exporting bit file 'C:/Users/Ian/Documents/GitHub/project_tubii_7020/project_tubii_7020.runs/impl_1/system_wrapper.bit'...
export_hardware: Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2631.395 ; gain = 0.000
exit
INFO: [Common 17-206] Exiting Vivado at Fri Apr 21 17:38:11 2017...