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Build failing on MPC8541 #100

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jpillora opened this issue Dec 5, 2013 · 22 comments
Open

Build failing on MPC8541 #100

jpillora opened this issue Dec 5, 2013 · 22 comments

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@jpillora
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jpillora commented Dec 5, 2013

@andrewlow currently has SSH access to the hardware. Updates will go here :)

@andrewlow
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SSH access isn't working (yet) - get Alex to check his email.

From the log that was mailed to me I see this:

CXX(target) /root/v8ppc/out/ppc.debug/obj.target/v8_base/src/compiler.o
g++: internal compiler error: Killed (program cc1plus)

So either, you've got a bug in GCC - or you're pushing the machine too hard and it's run out of memory and gcc was the victim of the kernel killing stuff off to stay alive.

@jpillora
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jpillora commented Dec 5, 2013

I'd guess it was the latter, is there anyway to slow it down? I can give it to you now, ping me at [email protected]

@jpillora
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jpillora commented Dec 5, 2013

Sent it to your @IBM address :)

@andrewlow
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It looks like you used;

make -j8 ppc &>log.txt

The j flag to make tells it the number of parallel compiles to run. Remove that flag entirely.

make ppc &> log.txt

@jpillora
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jpillora commented Dec 5, 2013

Ah ha, yup that'd kill a single-core 1.5Ghz sure enough

@andrewlow
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For reference (in case I need it in the future)

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8541E

Programmer reference manual
http://cache.freescale.com/files/32bit/doc/ref_manual/EREF_RM.pdf

@andrewlow
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The build crashed creating the snapshot.

  AR(target) /home/v8ppc/out/ppc.release/obj.target/tools/gyp/libv8_nosnapshot.a
  CXX(target) /home/v8ppc/out/ppc.release/obj.target/mksnapshot/src/mksnapshot.o
  LINK(target) /home/v8ppc/out/ppc.release/mksnapshot
  ACTION tools_gyp_v8_gyp_v8_snapshot_target_run_mksnapshot /home/v8ppc/out/ppc.  release/obj.target/v8_snapshot/geni/snapshot.cc
Illegal instruction (core dumped)
make[1]: *** [/home/v8ppc/out/ppc.release/obj.target/v8_snapshot/geni/snapshot.c  c] Error 132
make[1]: Leaving directory `/home/v8ppc/out'
make: *** [ppc.release] Error 2

This indicates there is some assembly code incompatibility. Next step, build with snapshot=off

@andrewlow
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Well that took a long time to build..

I tried running the tests on it

nohup tools/run-tests.py --progress=dots --no-presubmit --arch-and-mode=ppc.release  | tee test.log

but it seemed things were very bad right away (lots of crashes). I then tried just running the d8 command:

#out/ppc.debug/d8
Illegal instruction (core dumped)

Not good.

The machine doesn't appear to have gdb installed. So I installed it: "apt-get install gdb" (the dangers of giving me root :)

So gdb says I'm crashing on the instruction with the arrow =>

(gdb) x/20i $pc-16
   0x282288b0:  mflr    r0
   0x282288b4:  stwu    r0,-4(r1)
   0x282288b8:  stwu    r31,-4(r1)
   0x282288bc:  stwu    r20,-4(r1)
=> 0x282288c0:  stwu    r4,-4(r1)
   0x282288c4:  lwz     r12,20(r21)

of course, that's not believable - and causes me to remember that the instruction cache flush code is probably wrong for this platform. The size defaults to 128, when this platform is 64 I believe.

The cache size is defined here: constants-ppc.h:const unsigned int kCacheLineSizeLog2 = 7;

So I changed that to 6 to represent 64, and ran another build "nohup make ppc snapshot=off | tee log.txt"

@andrewlow
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Hmm, still not happy. I think the cache line size is 32bytes based on this doc: http://cache.freescale.com/files/32bit/doc/data_sheet/MPC8541EEC.pdf

Changed and trying again. I suspect once we get past these issues - we'll find this is very similar or identical to issue #99 - the good news is we've got remote access to the hardware, so it might get fixed faster.

@andrewlow
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Ok, that worked.

#./out/ppc.debug/d8
V8 version 3.14.5 (candidate) [console: dumb]
d8> print("Hello world");
Hello world
d8>

Now to test.

@jpillora
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jpillora commented Dec 6, 2013

Awesome :D

On Fri, Dec 6, 2013 at 12:47 PM, Andrew Low [email protected]:

Ok, that worked.

#./out/ppc.debug/d8
V8 version 3.14.5 (candidate) [console: dumb]
d8> print("Hello world");
Hello world
d8>

Now to test.


Reply to this email directly or view it on GitHubhttps://github.com//issues/100#issuecomment-29957093
.

@andrewlow
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/out/ppc.debug/cctest test-api/ConversionNumber --nobreak-on-abort --nodead-code-elimination --testing_serialization_file=./out/.serdes/serdes_ConversionNumber

I haven't done a full test run, but looking at issue #99 I tried the above test and it crashed on this platform as well.

Running under gdb we see

Program received signal SIGILL, Illegal instruction.
0x2183d5a4 in ?? ()
(gdb) x/20i $pc -16
   0x2183d594:  stw     r0,0(r1)
   0x2183d598:  stw     r22,4(r1)
   0x2183d59c:  .long 0xc8210000
   0x2183d5a0:  addi    r1,r1,8
=> 0x2183d5a4:  .long 0xfc200e9c
   0x2183d5a8:  clrlwi. r0,r5,31
   0x2183d5ac:  srawi   r22,r5,1
   0x2183d5b0:  beq-    0x2183d710
   0x2183d5b4:  lwz     r22,-1(r5)
   0x2183d5b8:  cmpw    cr7,r22,r8
   0x2183d5bc:  bne-    cr7,0x2183d7b0
   0x2183d5c0:  .long 0xc8450003
   0x2183d5c4:  .long 0xfc00165e
   0x2183d5c8:  addi    r1,r1,-8
   0x2183d5cc:  .long 0xd8010000
   0x2183d5d0:  lwz     r10,0(r1)

The .long's in the code are worrying. They are instructions that this version of gdb doesn't want to disassemble for us - pointing out that they may not be supported.

Manually decoding them gives us:

0xc8210000 lfd
0xfc200e9c fctiw[.]
0xc8450003 lfd
0xfc00165e fctiwz[.]
0xd8010000 lfd

@jpillora
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jpillora commented Dec 6, 2013

Interesting, indeed looks similar to gdb output from #99, could this be a possible blocker?

@andrewlow
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Referring the the programming manual (assuming I'm looking at the correct one http://cache.freescale.com/files/32bit/doc/ref_manual/EREF_RM.pdf) - lfd is supported. We also didn't crash on that line, so it's probably ok. This just means gdb is lying to us a little bit.

But I'm puzzled as it looks like fctiw is also implemented - but clearly we're crashing here.

Ah - http://cache.freescale.com/files/32bit/doc/ref_manual/E500CORERM.pdf has a list of instructions NOT supported on the Book E processors (which this is one of them)

image
image

@andrewlow
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Some we don't use at all, but others are actually quite frequently used. This may be a bigger effort than I had hoped at the start.

Some grepping around in the source is required here. The good news is that I think we've got a firm list of issues to look at.

This is also concerning
image

@andrewlow
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From the test log

>>> Running tests for ppc.release
No connection to distribution server; running tests locally.
Running 8979 tests
....

===
=== 1017 tests failed
=== 1008 tests CRASHED
===

More evidence this is basically the same issue as #99 - I think we'll continue to track these independently just for clarity of the investigations.

@jpillora
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jpillora commented Dec 6, 2013

Hey Andrew, are those CRASHED tests included in the failed? that is, were there 9 tests that didn't crash?

@andrewlow
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A little scripting and it seems that there are 283 locations in the code where we make use of the instructions that are not supported on the e500 based on table 3-2.

Resolving this issue completely will require addressing each of these locations.

assembler-ppc.cc:1419:void Assembler::lfd(const DwVfpRegister frt, const MemOperand &src) {
assembler-ppc.cc:1428:void Assembler::lfdu(const DwVfpRegister frt, const MemOperand &src) {
assembler-ppc.cc:1437:void Assembler::lfdx(const DwVfpRegister frt, const MemOperand &src) {
assembler-ppc.cc:1444:void Assembler::lfdux(const DwVfpRegister frt, const MemOperand & src) {
assembler-ppc.cc:1451:void Assembler::lfs(const DwVfpRegister frt, const MemOperand &src) {
assembler-ppc.cc:1461:void Assembler::lfsu(const DwVfpRegister frt, const MemOperand &src) {
assembler-ppc.cc:1471:void Assembler::lfsx(const DwVfpRegister frt, const MemOperand &src) {
assembler-ppc.cc:1478:void Assembler::lfsux(const DwVfpRegister frt, const MemOperand & src) {
assembler-ppc.cc:1485:void Assembler::stfd(const DwVfpRegister frs, const MemOperand &src) {
assembler-ppc.cc:1495:void Assembler::stfdu(const DwVfpRegister frs, const MemOperand &src) {
assembler-ppc.cc:1505:void Assembler::stfdx(const DwVfpRegister frs, const MemOperand &src) {
assembler-ppc.cc:1512:void Assembler::stfdux(const DwVfpRegister frs, const MemOperand &src) {
assembler-ppc.cc:1519:void Assembler::stfs(const DwVfpRegister frs, const MemOperand &src) {
assembler-ppc.cc:1529:void Assembler::stfsu(const DwVfpRegister frs, const MemOperand &src) {
assembler-ppc.cc:1539:void Assembler::stfsx(const DwVfpRegister frs, const MemOperand &src) {
assembler-ppc.cc:1546:void Assembler::stfsux(const DwVfpRegister frs, const MemOperand &src) {
assembler-ppc.cc:1553:void Assembler::fsub(const DwVfpRegister frt,
assembler-ppc.cc:1560:void Assembler::fadd(const DwVfpRegister frt,
assembler-ppc.cc:1566:void Assembler::fmul(const DwVfpRegister frt,
assembler-ppc.cc:1572:void Assembler::fdiv(const DwVfpRegister frt,
assembler-ppc.cc:1579:void Assembler::fcmpu(const DwVfpRegister fra,
assembler-ppc.cc:1586:void Assembler::fmr(const DwVfpRegister frt,
assembler-ppc.cc:1592:void Assembler::fctiwz(const DwVfpRegister frt,
assembler-ppc.cc:1597:void Assembler::fctiw(const DwVfpRegister frt,
assembler-ppc.cc:1607:void Assembler::frsp(const DwVfpRegister frt,
assembler-ppc.cc:1613:void Assembler::fcfid(const DwVfpRegister frt,
assembler-ppc.cc:1619:void Assembler::fctid(const DwVfpRegister frt,
assembler-ppc.cc:1625:void Assembler::fctidz(const DwVfpRegister frt,
assembler-ppc.cc:1631:void Assembler::fsel(const DwVfpRegister frt, const DwVfpRegister fra,
assembler-ppc.cc:1638:void Assembler::fneg(const DwVfpRegister frt,
assembler-ppc.cc:1644:void Assembler::mtfsfi(int bf, int immediate, RCBit rc) {
assembler-ppc.cc:1648:void Assembler::mffs(const DwVfpRegister frt, RCBit rc) {
assembler-ppc.cc:1652:void Assembler::mtfsf(const DwVfpRegister frb, bool L,
assembler-ppc.cc:1657:void Assembler::fsqrt(const DwVfpRegister frt,
assembler-ppc.cc:1663:void Assembler::fabs(const DwVfpRegister frt,
assembler-ppc.h:1000:  void stfdx(const DwVfpRegister frs, const MemOperand& src);
assembler-ppc.h:1001:  void stfdux(const DwVfpRegister frs, const MemOperand& src);
assembler-ppc.h:1002:  void stfs(const DwVfpRegister frs, const MemOperand& src);
assembler-ppc.h:1003:  void stfsu(const DwVfpRegister frs, const MemOperand& src);
assembler-ppc.h:1004:  void stfsx(const DwVfpRegister frs, const MemOperand& src);
assembler-ppc.h:1005:  void stfsux(const DwVfpRegister frs, const MemOperand& src);
assembler-ppc.h:1007:  void fadd(const DwVfpRegister frt, const DwVfpRegister fra,
assembler-ppc.h:1009:  void fsub(const DwVfpRegister frt, const DwVfpRegister fra,
assembler-ppc.h:1011:  void fdiv(const DwVfpRegister frt, const DwVfpRegister fra,
assembler-ppc.h:1013:  void fmul(const DwVfpRegister frt, const DwVfpRegister fra,
assembler-ppc.h:1015:  void fcmpu(const DwVfpRegister fra, const DwVfpRegister frb,
assembler-ppc.h:1017:  void fmr(const DwVfpRegister frt, const DwVfpRegister frb,
assembler-ppc.h:1019:  void fctiwz(const DwVfpRegister frt, const DwVfpRegister frb);
assembler-ppc.h:1020:  void fctiw(const DwVfpRegister frt, const DwVfpRegister frb);
assembler-ppc.h:1022:  void frsp(const DwVfpRegister frt, const DwVfpRegister frb,
assembler-ppc.h:1024:  void fcfid(const DwVfpRegister frt, const DwVfpRegister frb,
assembler-ppc.h:1026:  void fctid(const DwVfpRegister frt, const DwVfpRegister frb,
assembler-ppc.h:1028:  void fctidz(const DwVfpRegister frt, const DwVfpRegister frb,
assembler-ppc.h:1030:  void fsel(const DwVfpRegister frt, const DwVfpRegister fra,
assembler-ppc.h:1033:  void fneg(const DwVfpRegister frt, const DwVfpRegister frb,
assembler-ppc.h:1035:  void mtfsfi(int bf, int immediate, RCBit rc = LeaveRC);
assembler-ppc.h:1036:  void mffs(const DwVfpRegister frt, RCBit rc = LeaveRC);
assembler-ppc.h:1037:  void mtfsf(const DwVfpRegister frb, bool L = 1, int FLM = 0, bool W = 0,
assembler-ppc.h:1039:  void fsqrt(const DwVfpRegister frt, const DwVfpRegister frb,
assembler-ppc.h:1041:  void fabs(const DwVfpRegister frt, const DwVfpRegister frb,
assembler-ppc.h:990:  void lfd(const DwVfpRegister frt, const MemOperand& src);
assembler-ppc.h:991:  void lfdu(const DwVfpRegister frt, const MemOperand& src);
assembler-ppc.h:992:  void lfdx(const DwVfpRegister frt, const MemOperand& src);
assembler-ppc.h:993:  void lfdux(const DwVfpRegister frt, const MemOperand& src);
assembler-ppc.h:994:  void lfs(const DwVfpRegister frt, const MemOperand& src);
assembler-ppc.h:995:  void lfsu(const DwVfpRegister frt, const MemOperand& src);
assembler-ppc.h:996:  void lfsx(const DwVfpRegister frt, const MemOperand& src);
assembler-ppc.h:997:  void lfsux(const DwVfpRegister frt, const MemOperand& src);
assembler-ppc.h:998:  void stfd(const DwVfpRegister frs, const MemOperand& src);
assembler-ppc.h:999:  void stfdu(const DwVfpRegister frs, const MemOperand& src);
codegen-ppc.cc:226:  __ stfd(d0, MemOperand(r10, 0));
code-stubs-ppc.cc:1077:  __ lfd(d6, FieldMemOperand(rhs, HeapNumber::kValueOffset));
code-stubs-ppc.cc:1105:  __ lfd(d7, FieldMemOperand(lhs, HeapNumber::kValueOffset));
code-stubs-ppc.cc:1172:  __ lfd(d6, FieldMemOperand(rhs, HeapNumber::kValueOffset));
code-stubs-ppc.cc:1173:  __ lfd(d7, FieldMemOperand(lhs, HeapNumber::kValueOffset));
code-stubs-ppc.cc:1277:    __ lfd(d0, FieldMemOperand(object, HeapNumber::kValueOffset));
code-stubs-ppc.cc:1278:    __ lfd(d1, FieldMemOperand(probe, HeapNumber::kValueOffset));
code-stubs-ppc.cc:1279:    __ fcmpu(d0, d1);
code-stubs-ppc.cc:1380:  __ fcmpu(d7, d6);
code-stubs-ppc.cc:1559:    __ lfd(d1, FieldMemOperand(tos_, HeapNumber::kValueOffset));
code-stubs-ppc.cc:1565:    __ lfd(d2, MemOperand(sp, 0));
code-stubs-ppc.cc:1567:    __ fcmpu(d1, d2);
code-stubs-ppc.cc:1637:      __ stfd(reg, MemOperand(sp, i * kDoubleSize));
code-stubs-ppc.cc:1654:      __ lfd(reg, MemOperand(sp, i * kDoubleSize));
code-stubs-ppc.cc:1891:  __ stfd(d0, FieldMemOperand(r3, HeapNumber::kValueOffset));
code-stubs-ppc.cc:2277:          __ fadd(d1, d1, d2);
code-stubs-ppc.cc:2280:          __ fsub(d1, d1, d2);
code-stubs-ppc.cc:2283:          __ fmul(d1, d1, d2);
code-stubs-ppc.cc:2286:          __ fdiv(d1, d1, d2);
code-stubs-ppc.cc:2301:      __ stfd(d1, FieldMemOperand(result, HeapNumber::kValueOffset));
code-stubs-ppc.cc:2415:      __ stfd(d0, FieldMemOperand(r3, HeapNumber::kValueOffset));
code-stubs-ppc.cc:2579:          __ fadd(d1, d1, d2);
code-stubs-ppc.cc:2582:          __ fsub(d1, d1, d2);
code-stubs-ppc.cc:2585:          __ fmul(d1, d1, d2);
code-stubs-ppc.cc:2588:          __ fdiv(d1, d1, d2);
code-stubs-ppc.cc:2645:        __ stfd(d1, MemOperand(sp, 0));
code-stubs-ppc.cc:2680:        __ stfd(d1, FieldMemOperand(heap_number_result,
code-stubs-ppc.cc:2795:      __ stfd(double_scratch0, FieldMemOperand(heap_number_result,
code-stubs-ppc.cc:3014:    __ stfd(d6, MemOperand(sp, 0));
code-stubs-ppc.cc:3039:    __ stfd(d2, MemOperand(sp, 0));
code-stubs-ppc.cc:3126:    __ lfd(d2, FieldMemOperand(r9, HeapNumber::kValueOffset));
code-stubs-ppc.cc:3155:    __ stfd(d2, FieldMemOperand(r9, HeapNumber::kValueOffset));
code-stubs-ppc.cc:3166:    __ stfd(d2, FieldMemOperand(r3, HeapNumber::kValueOffset));
code-stubs-ppc.cc:3172:    __ lfd(d2, FieldMemOperand(r3, HeapNumber::kValueOffset));
code-stubs-ppc.cc:3205:  __ fmr(d1, d2);
code-stubs-ppc.cc:3285:    __ lfd(double_base, FieldMemOperand(base, HeapNumber::kValueOffset));
code-stubs-ppc.cc:3297:    __ lfd(double_exponent,
code-stubs-ppc.cc:3303:    __ lfd(double_exponent,
code-stubs-ppc.cc:3325:      __ fcmpu(double_exponent, double_scratch);
code-stubs-ppc.cc:3331:      __ fcmpu(double_base, double_scratch);
code-stubs-ppc.cc:3333:      __ fneg(double_result, double_scratch);
code-stubs-ppc.cc:3338:      __ fadd(double_scratch, double_base, kDoubleRegZero);
code-stubs-ppc.cc:3339:      __ fsqrt(double_result, double_scratch);
code-stubs-ppc.cc:3344:      __ fcmpu(double_exponent, double_scratch);
code-stubs-ppc.cc:3350:      __ fcmpu(double_base, double_scratch);
code-stubs-ppc.cc:3352:      __ fmr(double_result, kDoubleRegZero);
code-stubs-ppc.cc:3357:      __ fadd(double_scratch, double_base, kDoubleRegZero);
code-stubs-ppc.cc:3359:      __ fsqrt(double_scratch, double_scratch);
code-stubs-ppc.cc:3360:      __ fdiv(double_result, double_result, double_scratch);
code-stubs-ppc.cc:3390:  __ fmr(double_scratch, double_base);  // Back up base.
code-stubs-ppc.cc:3405:  __ fmul(double_result, double_result, double_scratch);
code-stubs-ppc.cc:3409:  __ fmul(double_scratch, double_scratch, double_scratch);
code-stubs-ppc.cc:3418:  __ fdiv(double_result, double_scratch, double_result);
code-stubs-ppc.cc:3421:  __ fcmpu(double_result, kDoubleRegZero);
code-stubs-ppc.cc:3439:    __ stfd(double_result,
code-stubs-ppc.cc:603:  __ lfd(dst, FieldMemOperand(object, HeapNumber::kValueOffset));
code-stubs-ppc.cc:6508:  __ lfd(d0, FieldMemOperand(r4, HeapNumber::kValueOffset));
code-stubs-ppc.cc:6509:  __ lfd(d1, FieldMemOperand(r3, HeapNumber::kValueOffset));
code-stubs-ppc.cc:6512:  __ fcmpu(d0, d1);
code-stubs-ppc.cc:6720:    // Call the runtime system in a fresh internal frame.
code-stubs-ppc.cc:678:  __ lfd(double_dst, MemOperand(sp, 0));
code-stubs-ppc.cc:683:  __ fcfid(double_dst, double_dst);
code-stubs-ppc.cc:710:  __ lfd(double_dst, MemOperand(sp, 0));
code-stubs-ppc.cc:715:  __ fcfid(double_dst, double_dst);
code-stubs-ppc.cc:740:  __ lfd(dst, MemOperand(sp, 0));
code-stubs-ppc.cc:744:  __ fcfid(dst, dst);
code-stubs-ppc.cc:745:  __ frsp(dst, dst);
code-stubs-ppc.cc:776:  __ lfd(double_dst, FieldMemOperand(object, HeapNumber::kValueOffset));
code-stubs-ppc.cc:818:  __ lfd(double_scratch0, FieldMemOperand(object, HeapNumber::kValueOffset));
code-stubs-ppc.cc:923:  __ stfd(d1, FieldMemOperand(heap_number_result, HeapNumber::kValueOffset));
code-stubs-ppc.h:544:          masm->stfd(reg, MemOperand(sp, (i - 1) * kDoubleSize));
code-stubs-ppc.h:556:          masm->lfd(reg, MemOperand(sp, (i - 1) * kDoubleSize));
deoptimizer-ppc.cc:1066:    __ stfd(fpu_reg, MemOperand(sp, offset));
deoptimizer-ppc.cc:1135:    __ lfd(d0, MemOperand(sp, src_offset));
deoptimizer-ppc.cc:1136:    __ stfd(d0, MemOperand(r4, dst_offset));
disasm-ppc.cc:1169:      Format(instr, "lfs     'Dt, 'int16('ra)");
disasm-ppc.cc:1173:      Format(instr, "lfsu    'Dt, 'int16('ra)");
disasm-ppc.cc:1177:      Format(instr, "lfd     'Dt, 'int16('ra)");
disasm-ppc.cc:1181:      Format(instr, "lfdu    'Dt, 'int16('ra)");
disasm-ppc.cc:1185:      Format(instr, "stfs    'Dt, 'int16('ra)");
disasm-ppc.cc:1189:      Format(instr, "stfsu   'Dt, 'int16('ra)");
disasm-ppc.cc:1193:      Format(instr, "stfd    'Dt, 'int16('ra)");
disasm-ppc.cc:1197:      Format(instr, "stfdu   'Dt, 'int16('ra)");
disasm-ppc.cc:603:      Format(instr, "lfsx    'rt, 'ra, 'rb");
disasm-ppc.cc:607:      Format(instr, "lfsux   'rt, 'ra, 'rb");
disasm-ppc.cc:611:      Format(instr, "lfdx    'rt, 'ra, 'rb");
disasm-ppc.cc:615:      Format(instr, "lfdux   'rt, 'ra, 'rb");
disasm-ppc.cc:619:      Format(instr, "stfsx    'rs, 'ra, 'rb");
disasm-ppc.cc:623:      Format(instr, "stfsux   'rs, 'ra, 'rb");
disasm-ppc.cc:627:      Format(instr, "stfdx    'rs, 'ra, 'rb");
disasm-ppc.cc:631:      Format(instr, "stfdux   'rs, 'ra, 'rb");
disasm-ppc.cc:844:      Format(instr, "fdiv'.   'Dt, 'Da, 'Db");
disasm-ppc.cc:848:      Format(instr, "fsub'.   'Dt, 'Da, 'Db");
disasm-ppc.cc:852:      Format(instr, "fadd'.   'Dt, 'Da, 'Db");
disasm-ppc.cc:856:      Format(instr, "fsqrt'.  'Dt, 'Db");
disasm-ppc.cc:860:      Format(instr, "fsel'.   'Dt, 'Da, 'Dc, 'Db");
disasm-ppc.cc:864:      Format(instr, "fmul'.   'Dt, 'Da, 'Dc");
disasm-ppc.cc:871:      Format(instr, "fcmpu   'Da, 'Db");
disasm-ppc.cc:875:      Format(instr, "frsp'.   'Dt, 'Db");
disasm-ppc.cc:879:      Format(instr, "fcfid'.  'Dt, 'Db");
disasm-ppc.cc:883:      Format(instr, "fctid   'Dt, 'Db");
disasm-ppc.cc:887:      Format(instr, "fctidz  'Dt, 'Db");
disasm-ppc.cc:891:      Format(instr, "fctiw'. 'Dt, 'Db");
disasm-ppc.cc:895:      Format(instr, "fctiwz'. 'Dt, 'Db");
disasm-ppc.cc:899:      Format(instr, "fmr'.    'Dt, 'Db");
disasm-ppc.cc:903:      Format(instr, "mtfsfi'.  ?,?");
disasm-ppc.cc:907:      Format(instr, "mffs'.   'Dt");
disasm-ppc.cc:911:      Format(instr, "mtfsf'.  'Db ?,?,?");
disasm-ppc.cc:915:      Format(instr, "fabs'.   'Dt, 'Db");
disasm-ppc.cc:923:      Format(instr, "fneg'.   'Dt, 'Db");
lithium-codegen-ppc.cc:1565:    __ fcmpu(left_reg, right_reg);
lithium-codegen-ppc.cc:1572:    __ fcmpu(left_reg, kDoubleRegZero);
lithium-codegen-ppc.cc:1579:      __ fneg(left_reg, left_reg);
lithium-codegen-ppc.cc:1580:      __ fsub(result_reg, left_reg, right_reg);
lithium-codegen-ppc.cc:1581:      __ fneg(result_reg, result_reg);
lithium-codegen-ppc.cc:1584:      __ fadd(result_reg, left_reg, right_reg);
lithium-codegen-ppc.cc:1589:    __ fcmpu(left_reg, left_reg);
lithium-codegen-ppc.cc:1594:      __ fmr(result_reg, right_reg);
lithium-codegen-ppc.cc:1600:      __ fmr(result_reg, left_reg);
lithium-codegen-ppc.cc:1613:      __ fadd(result, left, right);
lithium-codegen-ppc.cc:1616:      __ fsub(result, left, right);
lithium-codegen-ppc.cc:1619:      __ fmul(result, left, right);
lithium-codegen-ppc.cc:1622:      __ fdiv(result, left, right);
lithium-codegen-ppc.cc:1702:    __ fcmpu(reg, kDoubleRegZero, cr7);
lithium-codegen-ppc.cc:1789:        __ lfd(dbl_scratch, FieldMemOperand(reg, HeapNumber::kValueOffset));
lithium-codegen-ppc.cc:1790:        __ fcmpu(dbl_scratch, kDoubleRegZero);
lithium-codegen-ppc.cc:1865:      __ fcmpu(ToDoubleRegister(left), ToDoubleRegister(right));
lithium-codegen-ppc.cc:2860:  __ lfd(result, MemOperand(elements, address_offset));
lithium-codegen-ppc.cc:2944:      __ lfs(result, MemOperand(scratch0(), additional_offset));
lithium-codegen-ppc.cc:2946:      __ lfd(result, MemOperand(scratch0(), additional_offset));
lithium-codegen-ppc.cc:3411:    __ fabs(result, input);
lithium-codegen-ppc.cc:3447:    __ stfd(input, MemOperand(sp));
lithium-codegen-ppc.cc:3470:  __ stfd(input, MemOperand(sp));
lithium-codegen-ppc.cc:3496:  __ fadd(double_scratch0(), input, double_scratch0());
lithium-codegen-ppc.cc:3505:  __ stfd(double_scratch0(), MemOperand(sp, 0));
lithium-codegen-ppc.cc:3536:    __ stfd(input, MemOperand(sp));
lithium-codegen-ppc.cc:3553:  __ fsqrt(result, input);
lithium-codegen-ppc.cc:3568:  __ fcmpu(input, temp);
lithium-codegen-ppc.cc:3570:  __ fneg(result, temp);
lithium-codegen-ppc.cc:3575:  __ fadd(result, input, kDoubleRegZero);
lithium-codegen-ppc.cc:3576:  __ fsqrt(result, result);
lithium-codegen-ppc.cc:3690:  __ lfd(d7, MemOperand(sp, 0));
lithium-codegen-ppc.cc:3701:  __ lfd(d8, MemOperand(sp, 0));
lithium-codegen-ppc.cc:3706:  __ fsub(d7, d7, d8);
lithium-codegen-ppc.cc:4076:    __ fcmpu(value, value);
lithium-codegen-ppc.cc:4098:  __ stfd(value, MemOperand(scratch, dst_offset));
lithium-codegen-ppc.cc:4134:      __ frsp(double_scratch0(), value);
lithium-codegen-ppc.cc:4135:      __ stfs(double_scratch0(), MemOperand(scratch0(), additional_offset));
lithium-codegen-ppc.cc:4137:      __ stfd(value, MemOperand(scratch0(), additional_offset));
lithium-codegen-ppc.cc:4488:  __ stfd(dbl_scratch, FieldMemOperand(dst, HeapNumber::kValueOffset));
lithium-codegen-ppc.cc:4518:  __ stfd(input_reg, FieldMemOperand(reg, HeapNumber::kValueOffset));
lithium-codegen-ppc.cc:4586:    __ lfd(result_reg, FieldMemOperand(ip, HeapNumber::kValueOffset));
lithium-codegen-ppc.cc:4592:  __ lfd(result_reg, FieldMemOperand(input_reg, HeapNumber::kValueOffset));
lithium-codegen-ppc.cc:4595:    __ stfd(result_reg, MemOperand(sp));
lithium-codegen-ppc.cc:4655:    __ lfd(double_scratch2,
lithium-codegen-ppc.cc:4669:    __ lfd(double_scratch,
lithium-codegen-ppc.cc:4921:  __ lfd(double_scratch0(), FieldMemOperand(input_reg,
lithium-gap-resolver-ppc.cc:177:    __ fmr(kScratchDoubleReg, cgen_->ToDoubleRegister(source));
lithium-gap-resolver-ppc.cc:179:    __ lfd(kScratchDoubleReg, cgen_->ToMemOperand(source));
lithium-gap-resolver-ppc.cc:198:    __ fmr(cgen_->ToDoubleRegister(saved_destination_), kScratchDoubleReg);
lithium-gap-resolver-ppc.cc:200:    __ stfd(kScratchDoubleReg, cgen_->ToMemOperand(saved_destination_));
lithium-gap-resolver-ppc.cc:267:      __ fmr(cgen_->ToDoubleRegister(destination), source_register);
lithium-gap-resolver-ppc.cc:270:      __ stfd(source_register, cgen_->ToMemOperand(destination));
lithium-gap-resolver-ppc.cc:276:      __ lfd(cgen_->ToDoubleRegister(destination), source_operand);
lithium-gap-resolver-ppc.cc:297:        __ lfd(kScratchDoubleReg, source_operand);
lithium-gap-resolver-ppc.cc:298:        __ stfd(kScratchDoubleReg, destination_operand);
macro-assembler-ppc.cc:1866:  stfd(d0, MemOperand(scratch1, 0));
macro-assembler-ppc.cc:2256:  lfd(double_scratch, FieldMemOperand(source, HeapNumber::kValueOffset));
macro-assembler-ppc.cc:2259:  fctidz(double_scratch, double_scratch);
macro-assembler-ppc.cc:2262:  stfd(double_scratch, MemOperand(sp, 0));
macro-assembler-ppc.cc:2295:    fctidz(double_scratch, double_input);
macro-assembler-ppc.cc:2298:    fctid(double_scratch, double_input);
macro-assembler-ppc.cc:2303:  stfd(double_scratch, MemOperand(sp, 0));
macro-assembler-ppc.cc:2330:    fcfid(double_scratch, double_scratch);
macro-assembler-ppc.cc:2331:    fcmpu(double_scratch, double_input);
macro-assembler-ppc.cc:2434:  fctidz(double_scratch, double_input);
macro-assembler-ppc.cc:2437:  stfdu(double_scratch, MemOperand(sp, -8));
macro-assembler-ppc.cc:2460:  stfd(double_input, MemOperand(sp));
macro-assembler-ppc.cc:279:    fmr(dst, src);
macro-assembler-ppc.cc:3049:  stfd(value, FieldMemOperand(result, HeapNumber::kValueOffset));
macro-assembler-ppc.cc:3798:  mtfsfi(7, RN);
macro-assembler-ppc.cc:3802:  mtfsfi(7, kRoundToNearest);  // reset (default is kRoundToNearest)
macro-assembler-ppc.cc:3814:  fcmpu(input_reg, temp_double_reg);
macro-assembler-ppc.cc:3824:  fcmpu(input_reg, temp_double_reg);
macro-assembler-ppc.cc:3833:  fctiw(temp_double_reg, input_reg);
macro-assembler-ppc.cc:3836:  stfdu(temp_double_reg, MemOperand(sp, -8));
macro-assembler-ppc.cc:3960:  lfd(result, MemOperand(sp, 0));
macro-assembler-ppc.cc:650:      stfd(reg, MemOperand(sp, i * kDoubleSize));
macro-assembler-ppc.cc:715:      lfd(reg, MemOperand(r6, i * kDoubleSize));
macro-assembler-ppc.cc:744:  fmr(dst, d1);
simulator-ppc.cc:2462:      // frsp round 8-byte double-precision value to 8-byte
simulator-ppc.cc:2561:            if (fabs(static_cast<double>(frt_val) - frb_val) == 0.5 &&
stub-cache-ppc.cc:2139:  __ lfd(d1, FieldMemOperand(r3, HeapNumber::kValueOffset));
stub-cache-ppc.cc:2147:    __ fctidz(d1, d1);
stub-cache-ppc.cc:2149:    __ fctiwz(d1, d1);
stub-cache-ppc.cc:2158:    __ fctid(d1, d1);
stub-cache-ppc.cc:2160:    __ fctiw(d1, d1);
stub-cache-ppc.cc:2165:  __ stfdu(d1, MemOperand(sp, -8));
stub-cache-ppc.cc:3600:  __ lfd(double_scratch0, FieldMemOperand(key, HeapNumber::kValueOffset));
stub-cache-ppc.cc:3687:      __ lfsx(d0, MemOperand(r6, value));
stub-cache-ppc.cc:3691:      __ lfdx(d0, MemOperand(r6, value));
stub-cache-ppc.cc:3737:    __ stfd(d0, FieldMemOperand(r3, HeapNumber::kValueOffset));
stub-cache-ppc.cc:3761:    __ stfd(d0, FieldMemOperand(r3, HeapNumber::kValueOffset));
stub-cache-ppc.cc:3772:    __ stfd(d0, FieldMemOperand(r5, HeapNumber::kValueOffset));
stub-cache-ppc.cc:3782:    __ stfd(d0, FieldMemOperand(r5, HeapNumber::kValueOffset));
stub-cache-ppc.cc:3888:      __ stfsx(d0, MemOperand(r6, r10));
stub-cache-ppc.cc:3896:      __ stfdx(d0, MemOperand(r6, r10));
stub-cache-ppc.cc:3928:        __ lfd(d0, FieldMemOperand(r3, HeapNumber::kValueOffset));
stub-cache-ppc.cc:3930:        __ frsp(d0, d0);
stub-cache-ppc.cc:3931:        __ stfsx(d0, MemOperand(r6, r8));
stub-cache-ppc.cc:3933:        __ lfd(d0, FieldMemOperand(r3, HeapNumber::kValueOffset));
stub-cache-ppc.cc:3935:        __ stfdx(d0, MemOperand(r6, r8));
stub-cache-ppc.cc:3939:        __ lfd(d0, FieldMemOperand(r8, HeapNumber::kValueOffset));

@andrewlow
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@jpillora The test results should be interpreted like this:

8979 total number of tests
1017 + 1008 tests did not work as expected

A bit of math and we know 6954 passed -> 77% pass rate

Of the ones that didn't work as expected
1017 tests failed
1008 tests CRASHED

@jpillora
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jpillora commented Dec 6, 2013

Sure is a long list! How many missing instructions is that?

@jpillora
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jpillora commented Dec 6, 2013

Ah I see, so based on the types and number of missing instructions, do you have closer estimate of work required?

@andrewlow
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FWIW - a bit more sifting of the data - there are 117 locations in the code that need to be changed to make this work (if we disable crankshaft).

I'm providing this as a way to figure out the lower bound on the effort to bring this up on the e500 series. Of course, many of those 117 changes will be very similar - so we're not re-inventing the wheel each time as well.

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