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shapeoko-endstop.kicad_pcb
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shapeoko-endstop.kicad_pcb
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(kicad_pcb (version 4) (host pcbnew no-vcs-found-product)
(general
(links 21)
(no_connects 2)
(area 145.978 59.848 174.575001 114.825001)
(thickness 1.6)
(drawings 5)
(tracks 58)
(zones 0)
(modules 12)
(nets 9)
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
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(zone_45_only no)
(trace_min 0.2)
(segment_width 0.2)
(edge_width 0.15)
(via_size 0.6)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
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(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
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(usegerberextensions false)
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(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 5)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net 1 Z_ARD)
(net 2 GND)
(net 3 Y_ARD)
(net 4 X_ARD)
(net 5 Z_NO)
(net 6 Y_NO)
(net 7 X_NO)
(net 8 5V)
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
(via_dia 0.6)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net 5V)
(add_net GND)
(add_net X_ARD)
(add_net X_NO)
(add_net Y_ARD)
(add_net Y_NO)
(add_net Z_ARD)
(add_net Z_NO)
)
(module w_capacitors:cnp_6mm_disc (layer F.Cu) (tedit 0) (tstamp 56E1DF33)
(at 159.75 71.04 270)
(descr "6mm disc ceramic capacitor")
(tags C)
(path /56E1E702)
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(net 2 GND))
(model walter/capacitors/cnp_6mm_disc.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module w_capacitors:cnp_6mm_disc (layer F.Cu) (tedit 0) (tstamp 56E1DF3D)
(at 164.75 71.04 270)
(descr "6mm disc ceramic capacitor")
(tags C)
(path /56E1E52A)
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(pad 2 thru_hole circle (at 2.54 0 270) (size 1.50114 1.50114) (drill 0.8001) (layers *.Cu *.Mask F.SilkS)
(net 2 GND))
(model walter/capacitors/cnp_6mm_disc.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module w_capacitors:cnp_6mm_disc (layer F.Cu) (tedit 0) (tstamp 56E1DF47)
(at 167.5 71.04 270)
(descr "6mm disc ceramic capacitor")
(tags C)
(path /56E1DF9B)
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(pad 2 thru_hole circle (at 2.54 0 270) (size 1.50114 1.50114) (drill 0.8001) (layers *.Cu *.Mask F.SilkS)
(net 2 GND))
(model walter/capacitors/cnp_6mm_disc.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module w_pin_strip:pin_strip_6 (layer F.Cu) (tedit 0) (tstamp 56E1DF56)
(at 150.75 88.35 90)
(descr "Pin strip 6pin")
(tags "CONN DEV")
(path /56E1D91F)
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(effects (font (size 1.016 1.016) (thickness 0.2032)))
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(net 2 GND))
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(net 5 Z_NO))
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(net 2 GND))
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(net 6 Y_NO))
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(net 2 GND))
(pad 6 thru_hole oval (at 6.35 0 90) (size 1.524 2.19964) (drill 1.00076) (layers *.Cu *.Mask F.SilkS)
(net 7 X_NO))
(model walter/pin_strip/pin_strip_6.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module w_pin_strip:pin_strip_6 locked (layer F.Cu) (tedit 0) (tstamp 56E1DF65)
(at 160.996 64.62)
(descr "Pin strip 6pin")
(tags "CONN DEV")
(path /56E1D799)
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(fp_line (start 7.62 -1.27) (end 7.62 1.27) (layer F.SilkS) (width 0.3048))
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(net 1 Z_ARD))
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(net 3 Y_ARD))
(pad 6 thru_hole oval (at 6.35 0) (size 1.524 2.19964) (drill 1.00076) (layers *.Cu *.Mask F.SilkS)
(net 4 X_ARD))
(model walter/pin_strip/pin_strip_6.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module w_pin_strip:pin_strip_1 locked (layer F.Cu) (tedit 0) (tstamp 56E1DF6E)
(at 166.33 117.96)
(descr "Pin strip 1pin")
(tags "CONN DEV")
(path /56E1D813)
(fp_text reference P3 (at 2.67 0.12) (layer F.SilkS)
(effects (font (size 1.016 1.016) (thickness 0.2032)))
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(fp_line (start -1.27 1.27) (end -1.27 -1.27) (layer F.SilkS) (width 0.3048))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.3048))
(pad 1 thru_hole rect (at 0 0) (size 1.524 2.19964) (drill 1.00076) (layers *.Cu *.Mask F.SilkS)
(net 8 5V))
(model walter/pin_strip/pin_strip_1.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module w_pth_resistors:RC05 (layer F.Cu) (tedit 0) (tstamp 56E1DF7A)
(at 159.58 97.5)
(descr "Resistor, RC05")
(tags R)
(path /56E1E6EC)
(autoplace_cost180 10)
(fp_text reference R1 (at 0 0) (layer F.SilkS)
(effects (font (size 1.397 1.27) (thickness 0.2032)))
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(fp_text value 680 (at 0 2.032) (layer F.SilkS) hide
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(net 5 Z_NO))
(pad 2 thru_hole circle (at 5.08 0) (size 1.99898 1.99898) (drill 0.8001) (layers *.Cu *.Mask F.SilkS)
(net 8 5V))
(model walter/pth_resistors/rc05.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module w_pth_resistors:RC05 (layer F.Cu) (tedit 0) (tstamp 56E1DF86)
(at 167.83 93.75 180)
(descr "Resistor, RC05")
(tags R)
(path /56E1E6F8)
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(model walter/pth_resistors/rc05.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module w_pth_resistors:RC05 (layer F.Cu) (tedit 0) (tstamp 56E1DF92)
(at 159.58 89.5)
(descr "Resistor, RC05")
(tags R)
(path /56E1E514)
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(descr "Resistor, RC05")
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