virtio: PCI BAR mapping may be accessing invalid slots

[cagatay-y]

According to the pci-types documentation, the EndpointHeader::bar function should not be called on slots that make up the second part of a 64-bit BAR. However, map_bar_mem calls the function (indirectly) for all slots in the maximum BAR count range, without checking if the previous BAR was 64-bits.

kernel/src/drivers/virtio/env.rs

Lines 33 to 41 in 0245c53

	pub(crate) fn map_bar_mem(
	device: &PciDevice<PciConfigRegion>,
	) -> Result<Vec<VirtioPciBar>, PciError> {
	let mapped_bars: Vec<VirtioPciBar> = (0..u8::try_from(MAX_BARS).unwrap())
	.filter_map(|i| {
	device
	.memory_map_bar(i, true)
	.map(|(addr, size)| (i, addr, size))
	})

Additionally, it seems like the BARs are always 64-bit based on the lines below:

kernel/src/drivers/pci.rs

Lines 147 to 150 in 0245c53

	if width != 64 {
	warn!("Currently only mapping of 64 bit bars is supported!");
	return None;
	}