diff --git a/Cargo.lock b/Cargo.lock
index 66c5ec7971..22ab49952c 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -569,7 +569,7 @@ dependencies = [
  "pci_types",
  "rand_chacha",
  "riscv",
- "sbi",
+ "sbi-rt",
  "semihosting",
  "shell-words",
  "simple-shell",
@@ -1116,10 +1116,19 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "80af6f9131f277a45a3fba6ce8e2258037bb0477a67e610d3c1fe046ab31de47"
 
 [[package]]
-name = "sbi"
-version = "0.2.0"
+name = "sbi-rt"
+version = "0.0.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7fbaa69be1eedc61c426e6d489b2260482e928b465360576900d52d496a58bd0"
+dependencies = [
+ "sbi-spec",
+]
+
+[[package]]
+name = "sbi-spec"
+version = "0.0.7"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "29cb0870400aca7e4487e8ec1e93f9d4288da763cb1da2cedc5102e62b6522ad"
+checksum = "e6e36312fb5ddc10d08ecdc65187402baba4ac34585cb9d1b78522ae2358d890"
 
 [[package]]
 name = "scopeguard"
diff --git a/Cargo.toml b/Cargo.toml
index cfa0942db6..5421c12d52 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -137,7 +137,7 @@ semihosting = { version = "0.1", optional = true }
 
 [target.'cfg(target_arch = "riscv64")'.dependencies]
 riscv = "0.11"
-sbi = "0.2"
+sbi-rt = "0.0.3"
 trapframe = "0.9"
 semihosting = { version = "0.1", optional = true }
 
diff --git a/src/arch/riscv64/kernel/mod.rs b/src/arch/riscv64/kernel/mod.rs
index 3fa0708dc8..54a72983bd 100644
--- a/src/arch/riscv64/kernel/mod.rs
+++ b/src/arch/riscv64/kernel/mod.rs
@@ -123,7 +123,7 @@ pub fn message_output_init() {
 
 pub fn output_message_buf(buf: &[u8]) {
 	for byte in buf {
-		sbi::legacy::console_putchar(*byte);
+		sbi_rt::console_write_byte(*byte);
 	}
 }
 
@@ -198,7 +198,7 @@ fn finish_processor_init() {
 
 		//When running bare-metal/QEMU we use the firmware to start the next hart
 		if !env::is_uhyve() {
-			sbi::hart_state_management::hart_start(
+			sbi_rt::hart_start(
 				next_hart_id as usize,
 				start::_start as usize,
 				RAW_BOOT_INFO.load(Ordering::Relaxed) as usize,
diff --git a/src/arch/riscv64/kernel/processor.rs b/src/arch/riscv64/kernel/processor.rs
index 07242f8b5a..9151a89340 100644
--- a/src/arch/riscv64/kernel/processor.rs
+++ b/src/arch/riscv64/kernel/processor.rs
@@ -234,7 +234,10 @@ pub fn shutdown(error_code: i32) -> ! {
 			semihosting::process::exit(error_code)
 		} else {
 			// use SBI shutdown
-			sbi::legacy::shutdown()
+			sbi_rt::system_reset(sbi_rt::ColdReboot, sbi_rt::NoReason);
+			loop {
+				core::hint::spin_loop();
+			}
 		}
 	}
 }
@@ -270,16 +273,16 @@ pub fn set_oneshot_timer(wakeup_time: Option<u64>) {
 		}
 		let next_time = wt * u64::from(get_frequency());
 
-		sbi::legacy::set_timer(next_time);
+		sbi_rt::set_timer(next_time);
 	} else {
 		// Disable the Timer (and clear a pending interrupt)
 		debug!("Stopping Timer");
-		sbi::legacy::set_timer(u64::MAX);
+		sbi_rt::set_timer(u64::MAX);
 	}
 }
 
 pub fn wakeup_core(core_to_wakeup: CoreId) {
 	let hart_id = unsafe { HARTS_AVAILABLE[core_to_wakeup as usize] };
 	debug!("Wakeup core: {} , hart_id: {}", core_to_wakeup, hart_id);
-	sbi::legacy::send_ipi(&[1 << hart_id]);
+	sbi_rt::send_ipi(sbi_rt::HartMask::from_mask_base(0b1, hart_id));
 }