From 0df0d1f65b3b4e9b9ab862c4b93a96a48970817d Mon Sep 17 00:00:00 2001
From: Vladimir Pouzanov <farcaller@gmail.com>
Date: Fri, 9 Jan 2015 22:10:25 +0000
Subject: [PATCH 01/32] New Box::new syntax

---
 src/ioreg/ioreg.rs  | 2 +-
 src/ioreg/parser.rs | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/ioreg/ioreg.rs b/src/ioreg/ioreg.rs
index 0e62831b..7d277123 100644
--- a/src/ioreg/ioreg.rs
+++ b/src/ioreg/ioreg.rs
@@ -371,7 +371,7 @@ pub struct MacItems {
 
 impl MacItems {
   pub fn new(items: Vec<P<ast::Item>>) -> Box<MacResult+'static> {
-    box MacItems { items: items } as Box<MacResult>
+    Box::new(MacItems { items: items })
   }
 }
 
diff --git a/src/ioreg/parser.rs b/src/ioreg/parser.rs
index 4fbe14f7..74332338 100644
--- a/src/ioreg/parser.rs
+++ b/src/ioreg/parser.rs
@@ -50,8 +50,8 @@ impl<'a> Parser<'a> {
   pub fn new(cx: &'a ExtCtxt<'a>, tts: &[TokenTree]) -> Parser<'a> {
     let sess = cx.parse_sess();
     let ttsvec = tts.iter().map(|x| (*x).clone()).collect();
-    let mut reader = box lexer::new_tt_reader(
-        &sess.span_diagnostic, None, ttsvec) as Box<lexer::Reader>;
+    let mut reader = Box::new(lexer::new_tt_reader(
+        &sess.span_diagnostic, None, None, ttsvec)) as Box<lexer::Reader>;
 
     let tok0 = reader.next_token();
     let token = tok0.tok;
@@ -565,7 +565,7 @@ impl<'a> Parser<'a> {
   fn bump(&mut self) -> token::Token {
     let tok = self.token.clone();
     self.last_span = self.span;
-    self.last_token = Some(box tok.clone());
+    self.last_token = Some(Box::new(tok.clone()));
 
     let next = self.reader.next_token();
 

From d0b9742ab8753b99819c7ff6691279cbc03abd52 Mon Sep 17 00:00:00 2001
From: Vladimir Pouzanov <farcaller@gmail.com>
Date: Fri, 9 Jan 2015 22:10:34 +0000
Subject: [PATCH 02/32] New closure syntax

---
 src/zinc/drivers/lcd/mod.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/zinc/drivers/lcd/mod.rs b/src/zinc/drivers/lcd/mod.rs
index 0e6ee8c5..3931462d 100644
--- a/src/zinc/drivers/lcd/mod.rs
+++ b/src/zinc/drivers/lcd/mod.rs
@@ -197,7 +197,7 @@ mod test {
 
     fn axis(&self) -> Range<uint> { range(0u, 16) }
 
-    fn for_each(&self, block: |(u32, u32), u16|) {
+    fn for_each<F>(&self, block: F) where F: Fn((u32, u32), u16) {
       for x in self.axis() {
         for y in self.axis() {
           block(self.coords(x, y), self.pixbuf[x][y].get());
@@ -205,7 +205,7 @@ mod test {
       }
     }
 
-    fn map_each(&self, block: |(u32, u32), u16| -> u16) {
+    fn map_each<F>(&self, block: F) where F: Fn((u32, u32), u16) -> u16 {
       for x in self.axis() {
         for y in self.axis() {
           self.pixbuf[x][y].set(block(self.coords(x, y), self.pixbuf[x][y].get()));

From 3d2d6e629d3c90c319a4f7543c7b9487d2066b45 Mon Sep 17 00:00:00 2001
From: Vladimir Pouzanov <farcaller@gmail.com>
Date: Fri, 9 Jan 2015 22:10:41 +0000
Subject: [PATCH 03/32] Features cleanup

---
 src/zinc/lib.rs | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/zinc/lib.rs b/src/zinc/lib.rs
index 972dd65f..551bd8f4 100644
--- a/src/zinc/lib.rs
+++ b/src/zinc/lib.rs
@@ -13,7 +13,7 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#![feature(globs, macro_rules, asm, phase, unsafe_destructor, lang_items, associated_types)]
+#![feature(asm, unsafe_destructor, lang_items)]
 #![crate_name="zinc"]
 #![crate_type="rlib"]
 #![allow(improper_ctypes)]
@@ -47,11 +47,11 @@ The code is generic enough to support other MCUs in the same family (LPC17xx and
 STM32F403/407).
 */
 
-#[phase(plugin,link)] extern crate core;
+#[macro_use] extern crate core;
 #[cfg(not(test))] extern crate rlibc;
 
-#[cfg(test)] #[phase(plugin,link)] extern crate std;
-#[phase(plugin)] extern crate ioreg;
+#[macro_use] extern crate std;
+#[plugin] extern crate ioreg;
 
 pub mod drivers;
 pub mod hal;

From d548504d3fdcf1c8ef0e79871970eaecf2f99048 Mon Sep 17 00:00:00 2001
From: Ben Gamari <bgamari.foss@gmail.com>
Date: Sat, 10 Jan 2015 14:34:34 -0500
Subject: [PATCH 04/32] ioreg: feature(associated_types) now unnecessary

---
 src/ioreg/ioreg.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/ioreg/ioreg.rs b/src/ioreg/ioreg.rs
index 7d277123..4bad4ae9 100644
--- a/src/ioreg/ioreg.rs
+++ b/src/ioreg/ioreg.rs
@@ -327,7 +327,7 @@ N => NAME
 
 */
 
-#![feature(quote, plugin_registrar, associated_types)]
+#![feature(quote, plugin_registrar)]
 #![crate_name="ioreg"]
 #![crate_type="dylib"]
 

From 03772d374d13cbed69340b18a515f3acf748aaa9 Mon Sep 17 00:00:00 2001
From: Ben Gamari <bgamari.foss@gmail.com>
Date: Sat, 10 Jan 2015 15:17:56 -0500
Subject: [PATCH 05/32] ioreg: Validate bit offsets

---
 src/ioreg/parser.rs | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/src/ioreg/parser.rs b/src/ioreg/parser.rs
index 74332338..d2502026 100644
--- a/src/ioreg/parser.rs
+++ b/src/ioreg/parser.rs
@@ -208,7 +208,7 @@ impl<'a> Parser<'a> {
 
     let ty = match ty {
       RegType::RegPrim(width, _) => {
-        match self.parse_fields() {
+        match self.parse_fields(width) {
           None => return None,
           Some(mut fields) => {
             // Check for overlapping fields
@@ -257,7 +257,7 @@ impl<'a> Parser<'a> {
     })
   }
 
-  fn parse_fields(&mut self) -> Option<Vec<node::Field>> {
+  fn parse_fields(&mut self, reg_width: node::RegWidth) -> Option<Vec<node::Field>> {
     // sitting at starting bit number
     let mut fields: Vec<node::Field> = Vec::new();
     loop {
@@ -272,7 +272,7 @@ impl<'a> Parser<'a> {
         break;
       }
 
-      match self.parse_field() {
+      match self.parse_field(reg_width) {
         None => return None,
         Some(field) => fields.push(field),
       }
@@ -287,12 +287,17 @@ impl<'a> Parser<'a> {
   /// already seen the comma before the docstring) in addition to the
   /// parsed field.
   ///
-  fn parse_field(&mut self) -> Option<node::Field> {
+  fn parse_field(&mut self, reg_width: node::RegWidth) -> Option<node::Field> {
     // potentially an initial outer docstring
     let docstring = self.parse_docstring(Scope::Outer);
 
     // sitting at starting bit number
     let low_bit = match self.expect_uint() {
+      Some(bit) if bit >= reg_width.size() * 8 => {
+        self.error(format!("Start bit of field ({}) is greater than width of register ({})",
+          bit, 8*reg_width.size()));
+        return None;
+      },
       Some(bit) => bit,
       None => return None,
     };
@@ -301,6 +306,11 @@ impl<'a> Parser<'a> {
       token::DotDot => {
         self.bump();
         match self.expect_uint() {
+          Some(bit) if bit >= reg_width.size() * 8 => {
+            self.error(format!("End bit of field ({}) is greater than width of register ({})",
+              bit, 8*reg_width.size()));
+            return None;
+          },
           Some(bit) => bit as uint,
           None => return None,
         }

From 48b39fd12d3923e9879577acd98945d881ba45e9 Mon Sep 17 00:00:00 2001
From: Ben Gamari <bgamari.foss@gmail.com>
Date: Sat, 10 Jan 2015 15:18:20 -0500
Subject: [PATCH 06/32] ioreg: int renaming fallout

---
 src/ioreg/builder/accessors.rs |  6 +++---
 src/ioreg/builder/getter.rs    |  2 +-
 src/ioreg/builder/setter.rs    |  4 ++--
 src/ioreg/builder/union.rs     | 18 ++++++++++--------
 src/ioreg/builder/utils.rs     |  2 +-
 src/ioreg/node.rs              | 28 ++++++++++++++--------------
 src/ioreg/parser.rs            | 28 ++++++++++++++++------------
 7 files changed, 47 insertions(+), 41 deletions(-)

diff --git a/src/ioreg/builder/accessors.rs b/src/ioreg/builder/accessors.rs
index 170e53e3..0a2ade8d 100644
--- a/src/ioreg/builder/accessors.rs
+++ b/src/ioreg/builder/accessors.rs
@@ -143,7 +143,7 @@ fn build_field_set_fn(cx: &ExtCtxt, path: &Vec<String>,
   } else {
     quote_method!(cx,
       #[allow(dead_code, missing_docs)]
-      pub fn $fn_name<'a>(&'a self, idx: uint, new_value: $field_ty) -> $setter_ty<'a> {
+      pub fn $fn_name<'a>(&'a self, idx: usize, new_value: $field_ty) -> $setter_ty<'a> {
         let mut setter: $setter_ty = $setter_ty::new(self);
         setter.$fn_name(idx, new_value);
         setter
@@ -170,7 +170,7 @@ fn build_field_get_fn(cx: &ExtCtxt, path: &Vec<String>,
   } else {
     quote_method!(cx,
       #[allow(dead_code, missing_docs)]
-      pub fn $fn_name(&self, idx: uint) -> $field_ty {
+      pub fn $fn_name(&self, idx: usize) -> $field_ty {
         $getter_ty::new(self).$fn_name(idx)
       }
     )
@@ -196,7 +196,7 @@ fn build_field_clear_fn(cx: &ExtCtxt, path: &Vec<String>,
   } else {
     quote_method!(cx,
       #[allow(dead_code, missing_docs)]
-      pub fn $fn_name<'a>(&'a self, idx: uint) -> $setter_ty<'a> {
+      pub fn $fn_name<'a>(&'a self, idx: usize) -> $setter_ty<'a> {
         let mut setter: $setter_ty = $setter_ty::new(self);
         setter.$fn_name(idx);
         setter
diff --git a/src/ioreg/builder/getter.rs b/src/ioreg/builder/getter.rs
index ee930225..7ff041fd 100644
--- a/src/ioreg/builder/getter.rs
+++ b/src/ioreg/builder/getter.rs
@@ -202,7 +202,7 @@ fn build_field_get_fn(cx: &ExtCtxt, path: &Vec<String>, reg: &node::Reg,
       quote_expr!(cx, (self.value >> $shift) & $mask));
     quote_method!(cx,
       $doc_attr
-      pub fn $fn_name(&self, idx: uint) -> $field_ty {
+      pub fn $fn_name(&self, idx: usize) -> $field_ty {
         $value
       }
     )
diff --git a/src/ioreg/builder/setter.rs b/src/ioreg/builder/setter.rs
index f7860bd1..29f8208f 100644
--- a/src/ioreg/builder/setter.rs
+++ b/src/ioreg/builder/setter.rs
@@ -237,7 +237,7 @@ fn build_field_set_fn(cx: &ExtCtxt, path: &Vec<String>, reg: &node::Reg,
     let shift = utils::shift(cx, Some(quote_expr!(cx, idx)), field);
     quote_method!(cx,
       $doc_attr
-      pub fn $fn_name<'b>(&'b mut self, idx: uint, new_value: $field_ty)
+      pub fn $fn_name<'b>(&'b mut self, idx: usize, new_value: $field_ty)
           -> &'b mut $setter_ty<'a> {
         self.value |= (self.value & ! $mask) | ((new_value as $unpacked_ty) & $mask) << $shift;
         self.mask |= $mask << $shift;
@@ -278,7 +278,7 @@ fn build_field_clear_fn(cx: &ExtCtxt, path: &Vec<String>,
     let shift = utils::shift(cx, Some(quote_expr!(cx, idx)), field);
     quote_method!(cx,
       $doc_attr
-      pub fn $fn_name<'b>(&'b mut self, idx: uint) -> &'b mut $setter_ty<'a> {
+      pub fn $fn_name<'b>(&'b mut self, idx: usize) -> &'b mut $setter_ty<'a> {
         self.value |= $mask << $shift;
         self.mask |= $mask << $shift;
         self
diff --git a/src/ioreg/builder/union.rs b/src/ioreg/builder/union.rs
index 39f7297d..614e15b0 100644
--- a/src/ioreg/builder/union.rs
+++ b/src/ioreg/builder/union.rs
@@ -31,15 +31,15 @@ enum RegOrPadding<'a> {
   /// A register
   Reg(&'a node::Reg),
   /// A given number of bytes of padding
-  Pad(uint)
+  Pad(u64)
 }
 
 /// An iterator which takes a potentially unsorted list of registers,
 /// sorts them, and adds padding to make offsets correct
 struct PaddedRegsIterator<'a> {
   sorted_regs: &'a Vec<node::Reg>,
-  index: uint,
-  last_offset: uint,
+  index: usize,
+  last_offset: u64,
 }
 
 impl<'a> PaddedRegsIterator<'a> {
@@ -86,6 +86,10 @@ impl<'a> BuildUnionTypes<'a> {
   }
 }
 
+fn expr_u64(cx: &ExtCtxt, n: u64) -> P<ast::Expr> {
+  cx.expr_lit(DUMMY_SP, ast::LitInt(n as u64, ast::UnsignedIntLit(ast::TyU64)))
+}
+
 /// Returns the type of the field representing the given register
 /// within a `RegGroup` struct
 fn reg_struct_type(cx: &ExtCtxt, path: &Vec<String>, reg: &node::Reg)
@@ -96,8 +100,7 @@ fn reg_struct_type(cx: &ExtCtxt, path: &Vec<String>, reg: &node::Reg)
     1 => base_ty,
     n =>
       cx.ty(DUMMY_SP,
-            ast::TyFixedLengthVec(base_ty,
-                                  cx.expr_uint(DUMMY_SP, n))),
+            ast::TyFixedLengthVec(base_ty, expr_u64(cx, n as u64))),
   }
 }
 
@@ -139,7 +142,7 @@ impl<'a> BuildUnionTypes<'a> {
 
   /// Build field for padding or a register
   fn build_pad_or_reg(&self, path: &Vec<String>, reg_or_pad: RegOrPadding,
-                      index: uint) -> ast::StructField {
+                      index: usize) -> ast::StructField {
     match reg_or_pad {
       RegOrPadding::Reg(reg) => self.build_reg_union_field(path, reg),
       RegOrPadding::Pad(length) => {
@@ -150,8 +153,7 @@ impl<'a> BuildUnionTypes<'a> {
         let ty: P<ast::Ty> =
           self.cx.ty(
             DUMMY_SP,
-            ast::TyFixedLengthVec(u8_ty,
-                                  self.cx.expr_uint(DUMMY_SP, length)));
+            ast::TyFixedLengthVec(u8_ty, expr_u64(self.cx, length)));
         dummy_spanned(
           ast::StructField_ {
             kind: ast::NamedField(
diff --git a/src/ioreg/builder/utils.rs b/src/ioreg/builder/utils.rs
index db423869..d462682f 100644
--- a/src/ioreg/builder/utils.rs
+++ b/src/ioreg/builder/utils.rs
@@ -110,7 +110,7 @@ pub fn field_type_path(cx: &ExtCtxt, path: &Vec<String>,
 
 /// Build an expression for the mask of a field
 pub fn mask(cx: &ExtCtxt, field: &node::Field) -> P<ast::Expr> {
-  expr_int(cx, ((1i << field.width) - 1) as i64)
+  expr_int(cx, ((1 << field.width) - 1) as i64)
 }
 
 /// Build an expression for the shift of a field (including the array
diff --git a/src/ioreg/node.rs b/src/ioreg/node.rs
index e0990e0d..4da8e0b9 100644
--- a/src/ioreg/node.rs
+++ b/src/ioreg/node.rs
@@ -22,7 +22,7 @@ use syntax::ast;
 #[derive(Clone)]
 pub struct Variant {
   pub name: Spanned<String>,
-  pub value: Spanned<uint>,
+  pub value: Spanned<u64>,
   pub docstring: Option<Spanned<ast::Ident>>,
 }
 
@@ -53,11 +53,11 @@ pub enum Access {
 pub struct Field {
   pub name: Spanned<String>,
   /// The index of the first (lowest order) bit of the field
-  pub low_bit: uint,
+  pub low_bit: u8,
   /// The width in bits of a single array element
-  pub width: uint,
+  pub width: u8,
   /// The number of array elements
-  pub count: Spanned<uint>,
+  pub count: Spanned<u8>,
   pub bit_range_span: Span,
   pub access: Access,
   pub ty: Spanned<FieldType>,
@@ -66,7 +66,7 @@ pub struct Field {
 
 impl Field {
   /// The index of the highest order bit owned by this field
-  pub fn high_bit(&self) -> uint {
+  pub fn high_bit(&self) -> u8 {
     self.low_bit + self.width * self.count.node - 1
   }
 }
@@ -83,7 +83,7 @@ pub enum RegWidth {
 
 impl RegWidth {
   /// Size of register type in bytes
-  pub fn size(&self) -> uint {
+  pub fn size(&self) -> u64 {
     match *self {
       RegWidth::Reg32 => 4,
       RegWidth::Reg16 => 2,
@@ -102,9 +102,9 @@ pub enum RegType {
 
 impl RegType {
   /// Size of register type in bytes
-  pub fn size(&self) -> uint {
+  pub fn size(&self) -> u64 {
     match self {
-      &RegType::RegPrim(ref width, _)  => width.size(),
+      &RegType::RegPrim(ref width, _)  => width.size() as u64,
       &RegType::RegUnion(ref regs) => regs_size(regs.deref()),
     }
   }
@@ -113,26 +113,26 @@ impl RegType {
 /// A single register, either a union or primitive
 #[derive(Clone)]
 pub struct Reg {
-  pub offset: uint,
+  pub offset: u64,
   pub name: Spanned<String>,
   pub ty: RegType,
-  pub count: Spanned<uint>,
+  pub count: Spanned<u32>,
   pub docstring: Option<Spanned<ast::Ident>>,
 }
 
 impl Reg {
   /// Size of a register in bytes
-  pub fn size(&self) -> uint {
-    self.count.node * self.ty.size()
+  pub fn size(&self) -> u64 {
+    self.count.node as u64 * self.ty.size()
   }
   /// The offset of the last byte owned by this register
-  pub fn last_byte(&self) -> uint {
+  pub fn last_byte(&self) -> u64 {
     self.offset + self.size() - 1
   }
 }
 
 /// Size of registers of register group in bytes
-pub fn regs_size(regs: &Vec<Reg>) -> uint {
+pub fn regs_size(regs: &Vec<Reg>) -> u64 {
   match regs.iter().max_by(|r| r.offset) {
     Some(last) => last.offset + last.ty.size(),
     None => 0,
diff --git a/src/ioreg/parser.rs b/src/ioreg/parser.rs
index d2502026..cccbe40c 100644
--- a/src/ioreg/parser.rs
+++ b/src/ioreg/parser.rs
@@ -226,7 +226,7 @@ impl<'a> Parser<'a> {
 
             // Verify fields fit in register
             match fields.last().map(|f| f.high_bit()) {
-              Some(last_bit) if last_bit >= 8*width.size() => {
+              Some(last_bit) if last_bit >= 8*width.size() as u8 => {
                 self.sess.span_diagnostic.span_err(
                   name.span,
                   format!("Width of fields ({} bits) exceeds access size of register ({} bits)",
@@ -298,7 +298,7 @@ impl<'a> Parser<'a> {
           bit, 8*reg_width.size()));
         return None;
       },
-      Some(bit) => bit,
+      Some(bit) => bit as u8,
       None => return None,
     };
     let bits_span = self.span;
@@ -311,11 +311,11 @@ impl<'a> Parser<'a> {
               bit, 8*reg_width.size()));
             return None;
           },
-          Some(bit) => bit as uint,
+          Some(bit) => bit as u8,
           None => return None,
         }
       },
-      _ => low_bit as uint,
+      _ => low_bit as u8,
     };
 
     // TODO(bgamari): Do we want to enforce an order here?
@@ -335,12 +335,12 @@ impl<'a> Parser<'a> {
       None => return None,
     };
 
-    let (count, width): (Spanned<uint>, uint) =
+    let (count, width): (Spanned<u8>, u8) =
       match self.parse_count() {
         Some(count) => {
           let w = high_bit - low_bit + 1;
-          if w % count.node == 0 {
-            (count, w / count.node)
+          if w as u32 % count.node == 0 {
+            (Spanned {node: count.node as u8, span: count.span}, w as u8 / count.node as u8)
           } else {
             self.sess.span_diagnostic.span_err(
               mk_sp(bits_span.lo, self.last_span.hi),
@@ -514,7 +514,7 @@ impl<'a> Parser<'a> {
     }
   }
 
-  fn parse_uint(&mut self) -> Option<uint> {
+  fn parse_uint(&mut self) -> Option<u64> {
     match self.token {
       token::Literal(token::Integer(n), suf) => {
         self.bump();
@@ -523,7 +523,7 @@ impl<'a> Parser<'a> {
                                      &self.sess.span_diagnostic,
                                      self.span);
         match lit {
-          ast::LitInt(n, _)  => Some(n as uint),
+          ast::LitInt(n, _)  => Some(n),
           _ => None,
         }
       },
@@ -531,7 +531,7 @@ impl<'a> Parser<'a> {
     }
   }
 
-  fn expect_uint(&mut self) -> Option<uint> {
+  fn expect_uint(&mut self) -> Option<u64> {
     match self.parse_uint() {
       Some(n) => Some(n),
       None => {
@@ -544,12 +544,16 @@ impl<'a> Parser<'a> {
 
   /// `None` indicates parse failure.
   /// If no count is given, a default of 1 is used
-  fn parse_count(&mut self) -> Option<Spanned<uint>> {
+  fn parse_count(&mut self) -> Option<Spanned<u32>> {
     match self.token {
       token::OpenDelim(token::Bracket) => {
         self.bump();
         let ret = match self.expect_uint() {
-          Some(count) => respan(self.last_span, count),
+          Some(count) if count >= 1<<32 => {
+            self.error(format!("count unreasonably large ({})", count));
+            return None;
+          },
+          Some(count) => respan(self.last_span, count as u32),
           None => return None,
         };
         if !self.expect(&token::CloseDelim(token::Bracket)) {

From ac15313d3026ac9e8d2dc27e9bd6204c0e08aa56 Mon Sep 17 00:00:00 2001
From: Ben Gamari <bgamari.foss@gmail.com>
Date: Sat, 10 Jan 2015 15:20:55 -0500
Subject: [PATCH 07/32] ioreg: Allow(unstable)

This seems reasonable since the plugin relies on so many unstable rustc
interfaces
---
 src/ioreg/ioreg.rs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/ioreg/ioreg.rs b/src/ioreg/ioreg.rs
index 4bad4ae9..fceed591 100644
--- a/src/ioreg/ioreg.rs
+++ b/src/ioreg/ioreg.rs
@@ -330,6 +330,7 @@ N => NAME
 #![feature(quote, plugin_registrar)]
 #![crate_name="ioreg"]
 #![crate_type="dylib"]
+#![allow(unstable)]
 
 extern crate rustc;
 extern crate syntax;

From 4b72bd2890698ed0c5921c52b74186770820466e Mon Sep 17 00:00:00 2001
From: Ben Gamari <bgamari.foss@gmail.com>
Date: Sat, 10 Jan 2015 15:29:37 -0500
Subject: [PATCH 08/32] Switch to #[macro_use]

---
 src/zinc/hal/k20/uart.rs                 | 3 ++-
 src/zinc/hal/lpc17xx/peripheral_clock.rs | 3 ++-
 src/zinc/hal/lpc17xx/pin.rs              | 3 ++-
 src/zinc/hal/lpc17xx/system_clock.rs     | 6 ++++--
 src/zinc/hal/lpc17xx/timer.rs            | 3 ++-
 src/zinc/hal/lpc17xx/uart.rs             | 6 ++++--
 src/zinc/hal/stm32f4/init.rs             | 6 ++++--
 src/zinc/hal/stm32f4/pin.rs              | 3 ++-
 src/zinc/hal/stm32f4/timer.rs            | 3 ++-
 src/zinc/hal/stm32l1/init.rs             | 3 ++-
 src/zinc/hal/stm32l1/spi.rs              | 3 ++-
 src/zinc/hal/stm32l1/usart.rs            | 3 ++-
 src/zinc/hal/timer.rs                    | 3 ++-
 src/zinc/hal/tiva_c/sysctl.rs            | 3 ++-
 src/zinc/hal/tiva_c/uart.rs              | 6 ++++--
 src/zinc/util/ioreg.rs                   | 2 --
 src/zinc/util/wait_for.rs                | 2 --
 17 files changed, 38 insertions(+), 23 deletions(-)

diff --git a/src/zinc/hal/k20/uart.rs b/src/zinc/hal/k20/uart.rs
index c941f20c..a4b7f930 100644
--- a/src/zinc/hal/k20/uart.rs
+++ b/src/zinc/hal/k20/uart.rs
@@ -24,7 +24,8 @@ use hal::uart;
 
 use self::UARTPeripheral::*;
 
-#[path="../../util/wait_for.rs"] mod wait_for;
+#[path="../../util/wait_for.rs"]
+#[macro_use] mod wait_for;
 
 /// Available UART peripherals.
 #[allow(missing_docs)]
diff --git a/src/zinc/hal/lpc17xx/peripheral_clock.rs b/src/zinc/hal/lpc17xx/peripheral_clock.rs
index c57b3ab4..dd3ae02c 100644
--- a/src/zinc/hal/lpc17xx/peripheral_clock.rs
+++ b/src/zinc/hal/lpc17xx/peripheral_clock.rs
@@ -26,7 +26,8 @@ use self::PeripheralClock::*;
 use self::PeripheralDivisor::*;
 use core::kinds::Copy;
 
-#[path="../../util/ioreg.rs"] mod ioreg;
+#[path="../../util/ioreg.rs"]
+#[macro_use] mod ioreg;
 
 /// Configures the state of peripheral clock.
 #[allow(missing_docs)]
diff --git a/src/zinc/hal/lpc17xx/pin.rs b/src/zinc/hal/lpc17xx/pin.rs
index b49a5acf..d2d6263a 100644
--- a/src/zinc/hal/lpc17xx/pin.rs
+++ b/src/zinc/hal/lpc17xx/pin.rs
@@ -26,7 +26,8 @@ use core::kinds::Copy;
 
 use self::Port::*;
 
-#[path="../../util/ioreg.rs"] mod ioreg;
+#[path="../../util/ioreg.rs"]
+#[macro_use] mod ioreg;
 
 /// Available port names.
 #[allow(missing_docs)]
diff --git a/src/zinc/hal/lpc17xx/system_clock.rs b/src/zinc/hal/lpc17xx/system_clock.rs
index d8ec9ac2..3480750d 100644
--- a/src/zinc/hal/lpc17xx/system_clock.rs
+++ b/src/zinc/hal/lpc17xx/system_clock.rs
@@ -22,8 +22,10 @@ performing initial peripheral configuration.
 
 use core::option::Option::{self, Some, None};
 
-#[path="../../util/ioreg.rs"] mod ioreg;
-#[path="../../util/wait_for.rs"] mod wait_for;
+#[path="../../util/ioreg.rs"]
+#[macro_use] mod ioreg;
+#[path="../../util/wait_for.rs"]
+#[macro_use] mod wait_for;
 
 /// PLL clock source.
 #[derive(Copy)]
diff --git a/src/zinc/hal/lpc17xx/timer.rs b/src/zinc/hal/lpc17xx/timer.rs
index a3b46000..8e15c671 100644
--- a/src/zinc/hal/lpc17xx/timer.rs
+++ b/src/zinc/hal/lpc17xx/timer.rs
@@ -23,7 +23,8 @@ use hal::timer;
 
 use self::TimerPeripheral::*;
 
-#[path="../../util/ioreg.rs"] mod ioreg;
+#[path="../../util/ioreg.rs"]
+#[macro_use] mod ioreg;
 
 /// Available timer peripherals.
 #[allow(missing_docs)]
diff --git a/src/zinc/hal/lpc17xx/uart.rs b/src/zinc/hal/lpc17xx/uart.rs
index b32a33a3..b7130940 100644
--- a/src/zinc/hal/lpc17xx/uart.rs
+++ b/src/zinc/hal/lpc17xx/uart.rs
@@ -32,8 +32,10 @@ use hal::uart;
 
 use self::UARTPeripheral::*;
 
-#[path="../../util/ioreg.rs"] mod ioreg;
-#[path="../../util/wait_for.rs"] mod wait_for;
+#[path="../../util/ioreg.rs"]
+#[macro_use] mod ioreg;
+#[path="../../util/wait_for.rs"]
+#[macro_use] mod wait_for;
 
 
 /// Available UART peripherals.
diff --git a/src/zinc/hal/stm32f4/init.rs b/src/zinc/hal/stm32f4/init.rs
index 66cc49ee..96516091 100644
--- a/src/zinc/hal/stm32f4/init.rs
+++ b/src/zinc/hal/stm32f4/init.rs
@@ -21,8 +21,10 @@
 use hal::mem_init::init_data;
 use core::intrinsics::abort;
 
-#[path="../../util/ioreg.rs"] mod ioreg;
-#[path="../../util/wait_for.rs"] mod wait_for;
+#[path="../../util/ioreg.rs"]
+#[macro_use] mod ioreg;
+#[path="../../util/wait_for.rs"]
+#[macro_use] mod wait_for;
 
 /// System clock source.
 #[derive(Copy)]
diff --git a/src/zinc/hal/stm32f4/pin.rs b/src/zinc/hal/stm32f4/pin.rs
index de923a1b..101a6b9b 100644
--- a/src/zinc/hal/stm32f4/pin.rs
+++ b/src/zinc/hal/stm32f4/pin.rs
@@ -23,7 +23,8 @@ use core::intrinsics::abort;
 
 use self::Port::*;
 
-#[path="../../util/ioreg.rs"] mod ioreg;
+#[path="../../util/ioreg.rs"]
+#[macro_use] mod ioreg;
 
 /// Available port names.
 #[allow(missing_docs)]
diff --git a/src/zinc/hal/stm32f4/timer.rs b/src/zinc/hal/stm32f4/timer.rs
index c36f3baa..1e3c0de5 100644
--- a/src/zinc/hal/stm32f4/timer.rs
+++ b/src/zinc/hal/stm32f4/timer.rs
@@ -20,7 +20,8 @@
 use super::peripheral_clock;
 use hal::timer;
 
-#[path="../../util/ioreg.rs"] mod ioreg;
+#[path="../../util/ioreg.rs"]
+#[macro_use] mod ioreg;
 
 /// Available timer peripherals.
 #[allow(missing_docs)]
diff --git a/src/zinc/hal/stm32l1/init.rs b/src/zinc/hal/stm32l1/init.rs
index 33fb0fba..3fa79986 100644
--- a/src/zinc/hal/stm32l1/init.rs
+++ b/src/zinc/hal/stm32l1/init.rs
@@ -27,7 +27,8 @@ use core::kinds::Copy;
 use self::MsiSpeed::*;
 use self::SystemClockSource::*;
 
-#[path="../../util/wait_for.rs"] mod wait_for;
+#[path="../../util/wait_for.rs"]
+#[macro_use] mod wait_for;
 
 /// Phase-locked loop clock source.
 #[repr(u8)]
diff --git a/src/zinc/hal/stm32l1/spi.rs b/src/zinc/hal/stm32l1/spi.rs
index edf3d175..b29d0107 100644
--- a/src/zinc/hal/stm32l1/spi.rs
+++ b/src/zinc/hal/stm32l1/spi.rs
@@ -19,7 +19,8 @@ use core::result::Result;
 use core::result::Result::{Ok, Err};
 use core::kinds::Copy;
 
-#[path="../../util/wait_for.rs"] mod wait_for;
+#[path="../../util/wait_for.rs"]
+#[macro_use] mod wait_for;
 
 /// Available SPI peripherals.
 #[allow(missing_docs)]
diff --git a/src/zinc/hal/stm32l1/usart.rs b/src/zinc/hal/stm32l1/usart.rs
index 3a5fc417..7b465a19 100644
--- a/src/zinc/hal/stm32l1/usart.rs
+++ b/src/zinc/hal/stm32l1/usart.rs
@@ -28,7 +28,8 @@ use hal::stm32l1::init;
 
 use self::UsartPeripheral::*;
 
-#[path="../../util/wait_for.rs"] mod wait_for;
+#[path="../../util/wait_for.rs"]
+#[macro_use] mod wait_for;
 
 /// Available USART peripherals.
 #[allow(missing_docs)]
diff --git a/src/zinc/hal/timer.rs b/src/zinc/hal/timer.rs
index 1c232ac3..baeb0b59 100644
--- a/src/zinc/hal/timer.rs
+++ b/src/zinc/hal/timer.rs
@@ -21,7 +21,8 @@ TimerConf is a MCU-specific struct.
 Timers provide a simple way to delay program execution for some time.
 */
 
-#[path="../util/wait_for.rs"] mod wait_for;
+#[path="../util/wait_for.rs"]
+#[macro_use] mod wait_for;
 
 /// Timer implementation.
 pub trait Timer {
diff --git a/src/zinc/hal/tiva_c/sysctl.rs b/src/zinc/hal/tiva_c/sysctl.rs
index 07bec006..ed313ccf 100644
--- a/src/zinc/hal/tiva_c/sysctl.rs
+++ b/src/zinc/hal/tiva_c/sysctl.rs
@@ -18,7 +18,8 @@ use core::kinds::Copy;
 
 use util::support::get_reg_ref;
 
-#[path="../../util/wait_for.rs"] mod wait_for;
+#[path="../../util/wait_for.rs"]
+#[macro_use] mod wait_for;
 
 fn sysctl_get() -> &'static reg::SysCtl {
   get_reg_ref(reg::SYSCTL)
diff --git a/src/zinc/hal/tiva_c/uart.rs b/src/zinc/hal/tiva_c/uart.rs
index 9eaafc95..000431fb 100644
--- a/src/zinc/hal/tiva_c/uart.rs
+++ b/src/zinc/hal/tiva_c/uart.rs
@@ -21,8 +21,10 @@ use util::support::get_reg_ref;
 use drivers::chario::CharIO;
 use hal::uart;
 
-#[path="../../util/ioreg.rs"] mod ioreg;
-#[path="../../util/wait_for.rs"] mod wait_for;
+#[path="../../util/ioreg.rs"]
+#[macro_use] mod ioreg;
+#[path="../../util/wait_for.rs"]
+#[macro_use] mod wait_for;
 
 /// There are 8 UART instances in total
 #[allow(missing_docs)]
diff --git a/src/zinc/util/ioreg.rs b/src/zinc/util/ioreg.rs
index 03002cdc..b6293b9b 100644
--- a/src/zinc/util/ioreg.rs
+++ b/src/zinc/util/ioreg.rs
@@ -13,8 +13,6 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#![macro_escape]
-
 macro_rules! ioreg_old(
   ($io:ident: $ty:ty, $($reg:ident),+) => (
     #[allow(non_snake_case)]
diff --git a/src/zinc/util/wait_for.rs b/src/zinc/util/wait_for.rs
index 8175f935..0e944643 100644
--- a/src/zinc/util/wait_for.rs
+++ b/src/zinc/util/wait_for.rs
@@ -13,8 +13,6 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#![macro_escape]
-
 macro_rules! wait_for(
   ($cond:expr) => (
     loop {

From 78a3db8ec174010495c6ff477ad02945e0c35e97 Mon Sep 17 00:00:00 2001
From: Ben Gamari <bgamari.foss@gmail.com>
Date: Sat, 10 Jan 2015 15:32:27 -0500
Subject: [PATCH 09/32] Add feature(plugin)

---
 src/zinc/lib.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/zinc/lib.rs b/src/zinc/lib.rs
index 551bd8f4..5f5626db 100644
--- a/src/zinc/lib.rs
+++ b/src/zinc/lib.rs
@@ -13,7 +13,7 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#![feature(asm, unsafe_destructor, lang_items)]
+#![feature(asm, unsafe_destructor, lang_items, plugin)]
 #![crate_name="zinc"]
 #![crate_type="rlib"]
 #![allow(improper_ctypes)]

From f2cdb21ac38211ffa1da2e732d8e82d630da3269 Mon Sep 17 00:00:00 2001
From: Vladimir Pouzanov <farcaller@gmail.com>
Date: Sun, 11 Jan 2015 22:19:55 +0000
Subject: [PATCH 10/32] Removed std crate, why did we have it anyway?

---
 src/zinc/lib.rs | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/zinc/lib.rs b/src/zinc/lib.rs
index 5f5626db..215f14c9 100644
--- a/src/zinc/lib.rs
+++ b/src/zinc/lib.rs
@@ -50,7 +50,6 @@ STM32F403/407).
 #[macro_use] extern crate core;
 #[cfg(not(test))] extern crate rlibc;
 
-#[macro_use] extern crate std;
 #[plugin] extern crate ioreg;
 
 pub mod drivers;

From 26ed252dcd2ad80f06998030892d4c307617b491 Mon Sep 17 00:00:00 2001
From: Vladimir Pouzanov <farcaller@gmail.com>
Date: Sun, 11 Jan 2015 22:21:08 +0000
Subject: [PATCH 11/32] core::kinds::marker moved to core::marker

---
 src/ioreg/builder/getter.rs              | 2 +-
 src/zinc/hal/k20/pin.rs                  | 2 +-
 src/zinc/hal/lpc17xx/peripheral_clock.rs | 2 +-
 src/zinc/hal/lpc17xx/pin.rs              | 2 +-
 src/zinc/hal/lpc17xx/uart.rs             | 2 +-
 src/zinc/hal/stm32f4/peripheral_clock.rs | 2 +-
 src/zinc/hal/stm32l1/init.rs             | 2 +-
 src/zinc/hal/stm32l1/peripheral_clock.rs | 2 +-
 src/zinc/hal/stm32l1/spi.rs              | 2 +-
 src/zinc/hal/tiva_c/sysctl.rs            | 2 +-
 src/zinc/lib.rs                          | 2 +-
 src/zinc/os/cond_var.rs                  | 8 ++++----
 src/zinc/os/mutex.rs                     | 4 ++--
 src/zinc/util/shared.rs                  | 4 ++--
 src/zinc/util/volatile_cell.rs           | 6 +++---
 15 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/src/ioreg/builder/getter.rs b/src/ioreg/builder/getter.rs
index 7ff041fd..7c9725f7 100644
--- a/src/ioreg/builder/getter.rs
+++ b/src/ioreg/builder/getter.rs
@@ -55,7 +55,7 @@ impl<'a> node::RegVisitor for BuildGetters<'a> {
       // Build Copy impl
       let ty_name = utils::getter_name(self.cx, path);
       let it = quote_item!(self.cx,
-                           impl ::core::kinds::Copy for $ty_name {});
+                           impl ::core::marker::Copy for $ty_name {});
       self.builder.push_item(it.unwrap());
     }
   }
diff --git a/src/zinc/hal/k20/pin.rs b/src/zinc/hal/k20/pin.rs
index ec3e0d46..fed1db48 100644
--- a/src/zinc/hal/k20/pin.rs
+++ b/src/zinc/hal/k20/pin.rs
@@ -21,7 +21,7 @@ on the package.
 */
 
 use core::option::Option;
-use core::kinds::Copy;
+use core::marker::Copy;
 
 use super::sim;
 
diff --git a/src/zinc/hal/lpc17xx/peripheral_clock.rs b/src/zinc/hal/lpc17xx/peripheral_clock.rs
index dd3ae02c..a67d1ca5 100644
--- a/src/zinc/hal/lpc17xx/peripheral_clock.rs
+++ b/src/zinc/hal/lpc17xx/peripheral_clock.rs
@@ -24,7 +24,7 @@ use core::intrinsics::abort;
 use super::system_clock::system_clock;
 use self::PeripheralClock::*;
 use self::PeripheralDivisor::*;
-use core::kinds::Copy;
+use core::marker::Copy;
 
 #[path="../../util/ioreg.rs"]
 #[macro_use] mod ioreg;
diff --git a/src/zinc/hal/lpc17xx/pin.rs b/src/zinc/hal/lpc17xx/pin.rs
index d2d6263a..fd310c03 100644
--- a/src/zinc/hal/lpc17xx/pin.rs
+++ b/src/zinc/hal/lpc17xx/pin.rs
@@ -22,7 +22,7 @@ on the package.
 
 use core::intrinsics::abort;
 use core::option::Option;
-use core::kinds::Copy;
+use core::marker::Copy;
 
 use self::Port::*;
 
diff --git a/src/zinc/hal/lpc17xx/uart.rs b/src/zinc/hal/lpc17xx/uart.rs
index b7130940..41a27a5b 100644
--- a/src/zinc/hal/lpc17xx/uart.rs
+++ b/src/zinc/hal/lpc17xx/uart.rs
@@ -21,7 +21,7 @@ than other UARTs in MCU).
 */
 
 use core::intrinsics::abort;
-use core::kinds::Copy;
+use core::marker::Copy;
 
 use hal::lpc17xx::peripheral_clock::PeripheralClock;
 use hal::lpc17xx::peripheral_clock::PeripheralClock::UART0Clock;
diff --git a/src/zinc/hal/stm32f4/peripheral_clock.rs b/src/zinc/hal/stm32f4/peripheral_clock.rs
index b5549d1c..c07084d0 100644
--- a/src/zinc/hal/stm32f4/peripheral_clock.rs
+++ b/src/zinc/hal/stm32f4/peripheral_clock.rs
@@ -20,7 +20,7 @@
 //! Note: this module is used as part of initial setup if PLL is used.
 
 use super::init::reg;
-use core::kinds::Copy;
+use core::marker::Copy;
 
 use self::PeripheralClock::*;
 
diff --git a/src/zinc/hal/stm32l1/init.rs b/src/zinc/hal/stm32l1/init.rs
index 3fa79986..04f6ae4c 100644
--- a/src/zinc/hal/stm32l1/init.rs
+++ b/src/zinc/hal/stm32l1/init.rs
@@ -22,7 +22,7 @@
 use core::default;
 use core::intrinsics::abort;
 use core::option::Option;
-use core::kinds::Copy;
+use core::marker::Copy;
 
 use self::MsiSpeed::*;
 use self::SystemClockSource::*;
diff --git a/src/zinc/hal/stm32l1/peripheral_clock.rs b/src/zinc/hal/stm32l1/peripheral_clock.rs
index 44f153e3..889e4818 100644
--- a/src/zinc/hal/stm32l1/peripheral_clock.rs
+++ b/src/zinc/hal/stm32l1/peripheral_clock.rs
@@ -20,7 +20,7 @@
 //! Note: this module is used as part of initial setup if PLL is used.
 
 use super::init::{ClockConfig, reg};
-use core::kinds::Copy;
+use core::marker::Copy;
 
 pub use self::PeripheralClock::*;
 
diff --git a/src/zinc/hal/stm32l1/spi.rs b/src/zinc/hal/stm32l1/spi.rs
index b29d0107..b84fc544 100644
--- a/src/zinc/hal/stm32l1/spi.rs
+++ b/src/zinc/hal/stm32l1/spi.rs
@@ -17,7 +17,7 @@
 
 use core::result::Result;
 use core::result::Result::{Ok, Err};
-use core::kinds::Copy;
+use core::marker::Copy;
 
 #[path="../../util/wait_for.rs"]
 #[macro_use] mod wait_for;
diff --git a/src/zinc/hal/tiva_c/sysctl.rs b/src/zinc/hal/tiva_c/sysctl.rs
index ed313ccf..4a22eb59 100644
--- a/src/zinc/hal/tiva_c/sysctl.rs
+++ b/src/zinc/hal/tiva_c/sysctl.rs
@@ -14,7 +14,7 @@
 // limitations under the License.
 
 //! Low level system control (PLL, clock gating, ...)
-use core::kinds::Copy;
+use core::marker::Copy;
 
 use util::support::get_reg_ref;
 
diff --git a/src/zinc/lib.rs b/src/zinc/lib.rs
index 215f14c9..5de9fce7 100644
--- a/src/zinc/lib.rs
+++ b/src/zinc/lib.rs
@@ -68,5 +68,5 @@ pub mod std {
   pub use core::cmp;  // used for #[derive(Eq)] until fixed in rust.
   pub use core::option;
   pub use core::num;
-  pub use core::kinds;
+  pub use core::marker;
 }
diff --git a/src/zinc/os/cond_var.rs b/src/zinc/os/cond_var.rs
index 8e75af43..b2a4f871 100644
--- a/src/zinc/os/cond_var.rs
+++ b/src/zinc/os/cond_var.rs
@@ -21,8 +21,8 @@ pub use os::cond_var::internal::{CondVar, COND_VAR_INIT};
 mod internal {
   use core::option::{None, Some};
   use core::ty::Unsafe;
-  use core::kinds::marker;
-  use core::kinds::Sync;
+  use core::marker;
+  use core::marker::Sync;
 
   use hal::cortex_m3::sched::NoInterrupts;
   use util::queue::{Queue, Node};
@@ -92,8 +92,8 @@ mod internal {
 
 #[cfg(not(multitasking))]
 mod internal {
-  use core::kinds::marker;
-  use core::kinds::Sync;
+  use core::marker;
+  use core::marker::Sync;
   use core::cell::UnsafeCell;
 
   use util::support::wfi;
diff --git a/src/zinc/os/mutex.rs b/src/zinc/os/mutex.rs
index e7e013a1..976cdf37 100644
--- a/src/zinc/os/mutex.rs
+++ b/src/zinc/os/mutex.rs
@@ -19,7 +19,7 @@ pub use os::mutex::internal::{MUTEX_INIT, Mutex, Guard};
 
 #[cfg(multitasking)]
 mod internal {
-  use core::kinds::marker;
+  use core::marker;
   use core::ty::Unsafe;
   use core::kinds::Sync;
   use core::option::Option::{None, Some};
@@ -142,7 +142,7 @@ mod internal {
 
 #[cfg(not(multitasking))]
 mod internal {
-  use core::kinds::Sync;
+  use core::marker::Sync;
   use core::option::Option::{self, None, Some};
   use core::ops::Drop;
   use core::intrinsics::abort;
diff --git a/src/zinc/util/shared.rs b/src/zinc/util/shared.rs
index 91e17080..95df0793 100644
--- a/src/zinc/util/shared.rs
+++ b/src/zinc/util/shared.rs
@@ -17,8 +17,8 @@
 
 use core::cell::UnsafeCell;
 use core::ops::{Deref, DerefMut};
-use core::kinds::{Sync, Send};
-use core::kinds::marker;
+use core::marker::{Sync, Send};
+use core::marker;
 
 use hal::cortex_m3::irq::NoInterrupts;
 
diff --git a/src/zinc/util/volatile_cell.rs b/src/zinc/util/volatile_cell.rs
index bc19b813..2fbdb0ac 100644
--- a/src/zinc/util/volatile_cell.rs
+++ b/src/zinc/util/volatile_cell.rs
@@ -15,14 +15,14 @@
 
 //! A cell that with volatile setter and getter.
 
-use core::kinds::{marker, Copy};
+use core::marker::{Copy, InvariantType};
 use core::intrinsics::{volatile_load, volatile_store};
 
 /// This structure is used to represent a hardware register.
 /// It is mostly used by the ioreg family of macros.
 pub struct VolatileCell<T> {
   value: T,
-  invariant: marker::InvariantType<T>,
+  invariant: InvariantType<T>,
 }
 
 impl<T: Copy> Copy for VolatileCell<T> {}
@@ -32,7 +32,7 @@ impl<T> VolatileCell<T> {
   pub fn new(value: T) -> VolatileCell<T> {
     VolatileCell {
       value: value,
-      invariant: marker::InvariantType::<T>,
+      invariant: InvariantType::<T>,
     }
   }
 

From 67d24f470d84d95e780f1fb68f9c205397fb9255 Mon Sep 17 00:00:00 2001
From: Vladimir Pouzanov <farcaller@gmail.com>
Date: Sun, 11 Jan 2015 22:22:28 +0000
Subject: [PATCH 12/32] Removed Copy impls from ioreg

---
 src/ioreg/builder/register.rs | 7 +++----
 src/ioreg/builder/setter.rs   | 6 ------
 src/ioreg/builder/union.rs    | 4 ----
 3 files changed, 3 insertions(+), 14 deletions(-)

diff --git a/src/ioreg/builder/register.rs b/src/ioreg/builder/register.rs
index c9d8fd5e..26d89199 100644
--- a/src/ioreg/builder/register.rs
+++ b/src/ioreg/builder/register.rs
@@ -86,8 +86,7 @@ fn build_field_type(cx: &ExtCtxt, path: &Vec<String>,
         attrs: attrs,
         span: field.ty.span,
       });
-      let copy_impl = quote_item!(cx, impl ::core::kinds::Copy for $name {}).unwrap();
-      vec!(ty_item, copy_impl)
+      vec!(ty_item)
     },
     _ => Vec::new()
   }
@@ -123,8 +122,8 @@ fn build_reg_struct(cx: &ExtCtxt, path: &Vec<String>,
   );
   let mut item: ast::Item = item.unwrap().deref().clone();
   item.span = reg.name.span;
-  let copy_impl = quote_item!(cx, impl ::core::kinds::Copy for $ty_name {}).unwrap();
-  vec!(P(item), copy_impl)
+  // let copy_impl = quote_item!(cx, impl ::core::marker::Copy for $ty_name {}).unwrap();
+  vec!(P(item))
 }
 
 /// Build a variant of an `EnumField`
diff --git a/src/ioreg/builder/setter.rs b/src/ioreg/builder/setter.rs
index 29f8208f..97c1b392 100644
--- a/src/ioreg/builder/setter.rs
+++ b/src/ioreg/builder/setter.rs
@@ -54,12 +54,6 @@ impl<'a> node::RegVisitor for BuildSetters<'a> {
 
       let it = build_impl(self.cx, path, reg, fields);
       self.builder.push_item(it);
-
-      // Build Copy impl
-      let ty_name = utils::setter_name(self.cx, path);
-      let it = quote_item!(self.cx,
-                           impl<'a> ::core::kinds::Copy for $ty_name<'a> {});
-      self.builder.push_item(it.unwrap());
     }
   }
 }
diff --git a/src/ioreg/builder/union.rs b/src/ioreg/builder/union.rs
index 614e15b0..31c93edc 100644
--- a/src/ioreg/builder/union.rs
+++ b/src/ioreg/builder/union.rs
@@ -111,10 +111,6 @@ impl<'a> node::RegVisitor for BuildUnionTypes<'a> {
     let union_type = self.build_union_type(path, reg, &*subregs);
     let ty_name = union_type.ident.clone();
     self.builder.push_item(union_type);
-
-    let copy_impl = quote_item!(self.cx,
-                                impl ::core::kinds::Copy for $ty_name {});
-    self.builder.push_item(copy_impl.unwrap());
   }
 }
 

From a9c4fda08aae357d44fb2d12a6b86a60e675e7f2 Mon Sep 17 00:00:00 2001
From: Vladimir Pouzanov <farcaller@gmail.com>
Date: Sun, 11 Jan 2015 22:23:18 +0000
Subject: [PATCH 13/32] expr_u64 now returns size for whatever reason.

@bgamari will need to take a second look at this one.
---
 src/ioreg/builder/union.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/ioreg/builder/union.rs b/src/ioreg/builder/union.rs
index 31c93edc..4b6337c1 100644
--- a/src/ioreg/builder/union.rs
+++ b/src/ioreg/builder/union.rs
@@ -87,7 +87,7 @@ impl<'a> BuildUnionTypes<'a> {
 }
 
 fn expr_u64(cx: &ExtCtxt, n: u64) -> P<ast::Expr> {
-  cx.expr_lit(DUMMY_SP, ast::LitInt(n as u64, ast::UnsignedIntLit(ast::TyU64)))
+  cx.expr_lit(DUMMY_SP, ast::LitInt(n as u64, ast::UnsignedIntLit(ast::TyUs(false))))
 }
 
 /// Returns the type of the field representing the given register

From b287fb69c28a224972e08eefced016899e2b0c3b Mon Sep 17 00:00:00 2001
From: Vladimir Pouzanov <farcaller@gmail.com>
Date: Sun, 11 Jan 2015 22:23:46 +0000
Subject: [PATCH 14/32] Box::new fixes for PT

---
 src/macro/platformtree.rs  | 4 ++--
 src/platformtree/parser.rs | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/macro/platformtree.rs b/src/macro/platformtree.rs
index f8ab56dc..bf55985c 100644
--- a/src/macro/platformtree.rs
+++ b/src/macro/platformtree.rs
@@ -47,7 +47,7 @@ pub fn plugin_registrar(reg: &mut Registry) {
   reg.register_macro("platformtree", macro_platformtree);
   reg.register_macro("platformtree_verbose", macro_platformtree_verbose);
   reg.register_syntax_extension(syntax::parse::token::intern("zinc_task"),
-      Modifier(box macro_zinc_task));
+      Modifier(Box::new(macro_zinc_task)));
 }
 
 pub fn macro_platformtree(cx: &mut ExtCtxt, _: Span, tts: &[ast::TokenTree])
@@ -128,7 +128,7 @@ pub struct MacItems {
 
 impl MacItems {
   pub fn new(items: Vec<P<ast::Item>>) -> Box<MacResult+'static> {
-    box MacItems { items: items } as Box<MacResult>
+    Box::new(MacItems { items: items })
   }
 }
 impl MacResult for MacItems {
diff --git a/src/platformtree/parser.rs b/src/platformtree/parser.rs
index c045e8b7..5f309bf6 100644
--- a/src/platformtree/parser.rs
+++ b/src/platformtree/parser.rs
@@ -37,8 +37,8 @@ impl<'a> Parser<'a> {
   pub fn new(cx: &'a ExtCtxt, tts: &[TokenTree]) -> Parser<'a> {
     let sess = cx.parse_sess();
     let ttsvec = tts.iter().map(|x| (*x).clone()).collect();
-    let mut reader = box lexer::new_tt_reader(
-        &sess.span_diagnostic, None, ttsvec) as Box<lexer::Reader>;
+    let mut reader = Box::new(lexer::new_tt_reader(
+        &sess.span_diagnostic, None, None, ttsvec)) as Box<lexer::Reader>;
 
     let tok0 = reader.next_token();
     let token = tok0.tok;
@@ -401,7 +401,7 @@ impl<'a> Parser<'a> {
   fn bump(&mut self) -> token::Token {
     let tok = self.token.clone();
     self.last_span = self.span;
-    self.last_token = Some(box tok.clone());
+    self.last_token = Some(Box::new(tok.clone()));
 
     let next = self.reader.next_token();
 

From a4328ea35184706f3512529d4e6c2cbdf66d6448 Mon Sep 17 00:00:00 2001
From: Vladimir Pouzanov <farcaller@gmail.com>
Date: Sun, 11 Jan 2015 22:24:54 +0000
Subject: [PATCH 15/32] Various closure fixes to make things work

---
 src/platformtree/node.rs         |  3 ++-
 src/platformtree/test_helpers.rs | 10 ++++++----
 src/zinc/hal/tiva_c/pin_pt.rs    |  2 +-
 src/zinc/hal/tiva_c/timer_pt.rs  |  2 +-
 src/zinc/hal/tiva_c/uart_pt.rs   |  2 +-
 5 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/src/platformtree/node.rs b/src/platformtree/node.rs
index af1cc574..dbacf4a5 100644
--- a/src/platformtree/node.rs
+++ b/src/platformtree/node.rs
@@ -242,7 +242,8 @@ impl Node {
 
   /// Invokes the closure for each node from node's subnodes passing a path and
   /// weak node reference.
-  pub fn with_subnodes_map(&self, f: |&HashMap<String, Weak<Node>>|) {
+  pub fn with_subnodes_map<F>(&self, mut f: F)
+      where F: FnMut(&HashMap<String, Weak<Node>>) {
     let borrow = self.subnodes.borrow();
     f(borrow.as_map());
   }
diff --git a/src/platformtree/test_helpers.rs b/src/platformtree/test_helpers.rs
index b624eec2..4ea1a215 100644
--- a/src/platformtree/test_helpers.rs
+++ b/src/platformtree/test_helpers.rs
@@ -49,20 +49,22 @@ pub fn fails_to_build(src: &str) {
 /// Yields an ExtCtxt, parser error state and parsed PT.
 ///
 /// TODO(farcaller): get rid of that bool, it's broken.
-pub fn with_parsed(src: &str,
-    block: |&mut ExtCtxt, *mut bool, Rc<node::PlatformTree>|) {
+pub fn with_parsed<F>(src: &str, block: F)
+    where F: Fn(&mut ExtCtxt, *mut bool, Rc<node::PlatformTree>) {
   with_parsed_tts(src, |cx, failed, pt| {
     block(cx, failed, pt.unwrap());
   });
 }
 
-pub fn with_parsed_node(name: &str, src: &str, block: |Rc<node::Node>|) {
+pub fn with_parsed_node<F>(name: &str, src: &str, block: F)
+    where F: Fn(Rc<node::Node>) {
   with_parsed(src, |_, _, pt| {
     block(pt.get_by_path(name).unwrap());
   });
 }
 
-pub fn with_parsed_tts(src: &str, block: |&mut ExtCtxt, *mut bool, Option<Rc<node::PlatformTree>>|) {
+pub fn with_parsed_tts<F>(src: &str, block: F)
+    where F: Fn(&mut ExtCtxt, *mut bool, Option<Rc<node::PlatformTree>>) {
   let mut failed = false;
   let failptr = &mut failed as *mut bool;
   let ce = box CustomEmmiter::new(failptr);
diff --git a/src/zinc/hal/tiva_c/pin_pt.rs b/src/zinc/hal/tiva_c/pin_pt.rs
index 550c94e0..53333649 100644
--- a/src/zinc/hal/tiva_c/pin_pt.rs
+++ b/src/zinc/hal/tiva_c/pin_pt.rs
@@ -50,7 +50,7 @@ fn build_pin(builder: &mut Builder, cx: &mut ExtCtxt, node: Rc<node::Node>) {
   let port_node = node.parent.clone().unwrap().upgrade().unwrap();
   let ref port_path = port_node.path;
 
-  let error = | err: &str | {
+  let error = |&: err: &str | {
     cx.parse_sess().span_diagnostic.span_err(port_node.path_span, err);
   };
 
diff --git a/src/zinc/hal/tiva_c/timer_pt.rs b/src/zinc/hal/tiva_c/timer_pt.rs
index edcf2381..287ca339 100644
--- a/src/zinc/hal/tiva_c/timer_pt.rs
+++ b/src/zinc/hal/tiva_c/timer_pt.rs
@@ -35,7 +35,7 @@ pub fn verify(_: &mut Builder, cx: &mut ExtCtxt, node: Rc<node::Node>) {
 
 fn build_timer(builder: &mut Builder, cx: &mut ExtCtxt, node: Rc<node::Node>) {
 
-  let error = | err: &str | {
+  let error = |&: err: &str | {
     cx.parse_sess().span_diagnostic.span_err(node.path_span, err);
   };
 
diff --git a/src/zinc/hal/tiva_c/uart_pt.rs b/src/zinc/hal/tiva_c/uart_pt.rs
index 82f1ecb6..429fb521 100644
--- a/src/zinc/hal/tiva_c/uart_pt.rs
+++ b/src/zinc/hal/tiva_c/uart_pt.rs
@@ -38,7 +38,7 @@ pub fn verify(_: &mut Builder, cx: &mut ExtCtxt, node: Rc<node::Node>) {
 pub fn build_uart(builder: &mut Builder,
                   cx: &mut ExtCtxt,
                   sub: Rc<node::Node>) {
-  let error = | err: &str | {
+  let error = |&: err: &str | {
     cx.parse_sess().span_diagnostic.span_err(sub.path_span, err);
   };
 

From 0ae08de2997b88d921a7fd353ab9e20b84d4e5d2 Mon Sep 17 00:00:00 2001
From: Vladimir Pouzanov <farcaller@gmail.com>
Date: Sun, 11 Jan 2015 22:25:24 +0000
Subject: [PATCH 16/32] hash::hash fix

[insert I have no idea what I am doing meme here]
---
 src/platformtree/builder/meta_args.rs | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/platformtree/builder/meta_args.rs b/src/platformtree/builder/meta_args.rs
index cfbcbbf0..0aaa44d5 100644
--- a/src/platformtree/builder/meta_args.rs
+++ b/src/platformtree/builder/meta_args.rs
@@ -19,6 +19,7 @@ use syntax::ext::base::ExtCtxt;
 use syntax::ext::build::AstBuilder;
 use syntax::parse::token::{InternedString, intern_and_get_ident};
 use syntax::ptr::P;
+use std::hash::{hash, Hash, SipHasher};
 
 static TAG: &'static str = "__zinc_task_ty_params";
 
@@ -28,7 +29,8 @@ pub trait ToTyHash {
 
 impl ToTyHash for String {
   fn to_tyhash(&self) -> String {
-    format!("Ty{:X}", ::std::hash::hash(self))
+    let h: u64 = hash::<_, SipHasher>(&self);
+    format!("Ty{:X}", h)
   }
 }
 

From 8900158be89ecc10059effca1583d30b5d968e84 Mon Sep 17 00:00:00 2001
From: Vladimir Pouzanov <farcaller@gmail.com>
Date: Sun, 11 Jan 2015 22:26:19 +0000
Subject: [PATCH 17/32] Some strange thing that seems to compile and work

but I have absolutely no idea what is happening around
here, the syntax seems to be very odd.
---
 src/zinc/hal/lpc17xx/pin_pt.rs | 9 +++++----
 src/zinc/hal/lpc17xx/pinmap.rs | 4 ++--
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/zinc/hal/lpc17xx/pin_pt.rs b/src/zinc/hal/lpc17xx/pin_pt.rs
index ea2ef8f3..14bbb97c 100644
--- a/src/zinc/hal/lpc17xx/pin_pt.rs
+++ b/src/zinc/hal/lpc17xx/pin_pt.rs
@@ -89,16 +89,17 @@ fn build_pin(builder: &mut Builder, cx: &mut ExtCtxt, node: Rc<node::Node>) {
     None => "Gpio".to_string(),
     Some(fun) => {
       let pins = &port_def[*port_path];
-      let maybe_pin_index = node.path.as_slice().parse().unwrap();
-      match pins[maybe_pin_index] {
-        None => {
+      let maybe_pin_index: usize = node.path.as_slice().parse().unwrap();
+      let maybe_pin: &Option<pinmap::PinDef> = pins.get(maybe_pin_index).unwrap();
+      match maybe_pin {
+        &None => {
           cx.parse_sess().span_diagnostic.span_err(
               node.get_attr("function").value_span,
               format!("unknown pin function `{}`, only GPIO avaliable on this pin",
                   fun).as_slice());
           return;
         }
-        Some(ref pin_funcs) => {
+        &Some(ref pin_funcs) => {
           let maybe_func = pin_funcs.get(&fun);
           match maybe_func {
             None => {
diff --git a/src/zinc/hal/lpc17xx/pinmap.rs b/src/zinc/hal/lpc17xx/pinmap.rs
index 34553347..309e61f1 100644
--- a/src/zinc/hal/lpc17xx/pinmap.rs
+++ b/src/zinc/hal/lpc17xx/pinmap.rs
@@ -20,8 +20,8 @@
 //! This module provides all possible pin configurations for LPC17xx.
 use std::collections::HashMap;
 
-type PinDef = HashMap<String, uint>;
-type PinsDef = Vec<Option<PinDef>>;
+pub type PinDef = HashMap<String, uint>;
+pub type PinsDef = Vec<Option<PinDef>>;
 
 pub fn port_def() -> HashMap<String, PinsDef> {
   let mut h = HashMap::new();

From 0e674c94e97b27659d78fb0ccae4164cac8b2272 Mon Sep 17 00:00:00 2001
From: Vladimir Pouzanov <farcaller@gmail.com>
Date: Sun, 11 Jan 2015 22:26:53 +0000
Subject: [PATCH 18/32] Replaced feature phase with plugin

---
 apps/app_blink.rs                | 4 ++--
 apps/app_blink_tiva_c.rs         | 2 +-
 apps/app_dht22.rs                | 4 ++--
 apps/app_empty.rs                | 4 ++--
 apps/app_lcd_tiva_c.rs           | 3 +--
 apps/app_uart.rs                 | 4 ++--
 apps/app_uart_tiva_c.rs          | 2 +-
 src/platformtree/platformtree.rs | 2 +-
 src/zinc/lib.rs                  | 2 +-
 9 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/apps/app_blink.rs b/apps/app_blink.rs
index 831ad023..169b28dd 100644
--- a/apps/app_blink.rs
+++ b/apps/app_blink.rs
@@ -1,10 +1,10 @@
-#![feature(phase)]
+#![feature(plugin)]
 #![crate_type="staticlib"]
 #![no_std]
 
 extern crate core;
 extern crate zinc;
-#[phase(plugin)] extern crate macro_platformtree;
+#[macro_use] #[plugin] #[no_link] extern crate macro_platformtree;
 
 platformtree!(
   lpc17xx@mcu {
diff --git a/apps/app_blink_tiva_c.rs b/apps/app_blink_tiva_c.rs
index 34dd11bb..78f07a31 100644
--- a/apps/app_blink_tiva_c.rs
+++ b/apps/app_blink_tiva_c.rs
@@ -4,7 +4,7 @@
 
 extern crate core;
 extern crate zinc;
-#[phase(plugin)] extern crate macro_platformtree;
+#[macro_use] #[plugin] #[no_link] extern crate macro_platformtree;
 
 platformtree!(
   tiva_c@mcu {
diff --git a/apps/app_dht22.rs b/apps/app_dht22.rs
index 6a1d151b..7b7625bb 100644
--- a/apps/app_dht22.rs
+++ b/apps/app_dht22.rs
@@ -1,10 +1,10 @@
-#![feature(phase)]
+#![feature(plugin)]
 #![crate_type="staticlib"]
 #![no_std]
 
 extern crate core;
 extern crate zinc;
-#[phase(plugin)] extern crate macro_platformtree;
+#[macro_use] #[plugin] #[no_link] extern crate macro_platformtree;
 
 use core::option::Option::{Some, None};
 
diff --git a/apps/app_empty.rs b/apps/app_empty.rs
index 94e2b279..673daaa6 100644
--- a/apps/app_empty.rs
+++ b/apps/app_empty.rs
@@ -1,10 +1,10 @@
-#![feature(phase, asm)]
+#![feature(plugin, asm)]
 #![crate_type="staticlib"]
 #![no_std]
 
 extern crate core;
 extern crate zinc;
-#[phase(plugin)] extern crate macro_platformtree;
+#[macro_use] #[plugin] #[no_link] extern crate macro_platformtree;
 
 platformtree!(
   lpc17xx@mcu {
diff --git a/apps/app_lcd_tiva_c.rs b/apps/app_lcd_tiva_c.rs
index 7fdb5c02..44ccba2a 100644
--- a/apps/app_lcd_tiva_c.rs
+++ b/apps/app_lcd_tiva_c.rs
@@ -1,10 +1,9 @@
-#![feature(phase)]
 #![crate_type="staticlib"]
 #![no_std]
 
 extern crate core;
 extern crate zinc;
-#[phase(plugin)] extern crate macro_platformtree;
+#[macro_use] #[plugin] #[no_link] extern crate macro_platformtree;
 
 use zinc::drivers::chario::CharIO;
 use zinc::drivers::lcd::hd44780u::{Hd44780u, Font};
diff --git a/apps/app_uart.rs b/apps/app_uart.rs
index 8db6168b..c8bd646a 100644
--- a/apps/app_uart.rs
+++ b/apps/app_uart.rs
@@ -1,10 +1,10 @@
-#![feature(phase)]
+#![feature(plugin)]
 #![crate_type="staticlib"]
 #![no_std]
 
 extern crate core;
 extern crate zinc;
-#[phase(plugin)] extern crate macro_platformtree;
+#[macro_use] #[plugin] #[no_link] extern crate macro_platformtree;
 
 platformtree!(
   lpc17xx@mcu {
diff --git a/apps/app_uart_tiva_c.rs b/apps/app_uart_tiva_c.rs
index 85b5c95f..ff3b1474 100644
--- a/apps/app_uart_tiva_c.rs
+++ b/apps/app_uart_tiva_c.rs
@@ -4,7 +4,7 @@
 
 extern crate core;
 extern crate zinc;
-#[phase(plugin)] extern crate macro_platformtree;
+#[macro_use] #[plugin] #[no_link] extern crate macro_platformtree;
 
 use zinc::drivers::chario::CharIO;
 
diff --git a/src/platformtree/platformtree.rs b/src/platformtree/platformtree.rs
index 976eff8f..f1bd7129 100644
--- a/src/platformtree/platformtree.rs
+++ b/src/platformtree/platformtree.rs
@@ -16,7 +16,7 @@
 //! Platform tree operations crate
 
 #![experimental]
-#![feature(quote, globs, phase)]
+#![feature(quote, globs)]
 
 #![crate_name="platformtree"]
 #![crate_type="rlib"]
diff --git a/src/zinc/lib.rs b/src/zinc/lib.rs
index 5de9fce7..b589de8b 100644
--- a/src/zinc/lib.rs
+++ b/src/zinc/lib.rs
@@ -50,7 +50,7 @@ STM32F403/407).
 #[macro_use] extern crate core;
 #[cfg(not(test))] extern crate rlibc;
 
-#[plugin] extern crate ioreg;
+#[macro_use] #[no_link] #[plugin] extern crate ioreg;
 
 pub mod drivers;
 pub mod hal;

From 89ed470118865bdebe147f8b3639f11fa127c027 Mon Sep 17 00:00:00 2001
From: Vladimir Pouzanov <farcaller@gmail.com>
Date: Sun, 11 Jan 2015 22:36:09 +0000
Subject: [PATCH 19/32] Moved rlibc crate in tree, it's reasonably tiny

---
 support/rake.rb                |   4 -
 thirdparty/librlibc/.gitignore |   2 +
 thirdparty/librlibc/Cargo.toml |  11 ++
 thirdparty/librlibc/src/lib.rs | 187 +++++++++++++++++++++++++++++++++
 4 files changed, 200 insertions(+), 4 deletions(-)
 create mode 100644 thirdparty/librlibc/.gitignore
 create mode 100644 thirdparty/librlibc/Cargo.toml
 create mode 100644 thirdparty/librlibc/src/lib.rs

diff --git a/support/rake.rb b/support/rake.rb
index 1cddd0e5..5069b8da 100644
--- a/support/rake.rb
+++ b/support/rake.rb
@@ -153,10 +153,6 @@ def provide_stdlibs
     sh "git clone --single-branch --depth 1 https://github.com/rust-lang/rust #{t.name}"
   end.invoke
 
-  Rake::FileTask.define_task 'thirdparty/librlibc'.in_root do |t|
-    sh "git clone https://github.com/bharrisau/rust-librlibc #{t.name}"
-  end.invoke
-
   Rake::FileTask.define_task 'thirdparty/libcore/lib.rs'.in_root do |t|
     sh "ln -s rust/src/libcore thirdparty/libcore"
   end.invoke
diff --git a/thirdparty/librlibc/.gitignore b/thirdparty/librlibc/.gitignore
new file mode 100644
index 00000000..80faedec
--- /dev/null
+++ b/thirdparty/librlibc/.gitignore
@@ -0,0 +1,2 @@
+Cargo.lock
+/target/
diff --git a/thirdparty/librlibc/Cargo.toml b/thirdparty/librlibc/Cargo.toml
new file mode 100644
index 00000000..550e8910
--- /dev/null
+++ b/thirdparty/librlibc/Cargo.toml
@@ -0,0 +1,11 @@
+[package]
+name = "rlibc"
+version = "0.13.0"
+authors = ["Ben Harris <mail@bharr.is>"]
+
+[lib]
+name = "rlibc"
+path = "src/lib.rs"
+
+[dependencies.core]
+git = "https://github.com/bharrisau/rust-libcore.git"
diff --git a/thirdparty/librlibc/src/lib.rs b/thirdparty/librlibc/src/lib.rs
new file mode 100644
index 00000000..640b50d7
--- /dev/null
+++ b/thirdparty/librlibc/src/lib.rs
@@ -0,0 +1,187 @@
+// Copyright 2014 The Rust Project Developers. See the COPYRIGHT
+// file at the top-level directory of this distribution and at
+// http://rust-lang.org/COPYRIGHT.
+//
+// Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
+// http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
+// <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
+// option. This file may not be copied, modified, or distributed
+// except according to those terms.
+
+//! A bare-metal library supplying functions rustc may lower code to
+//!
+//! This library is not intended for general use, and is superseded by a system
+//! libc if one is available. In a freestanding context, however, common
+//! functions such as memset, memcpy, etc are not implemented. This library
+//! provides an implementation of these functions which are either required by
+//! libcore or called by rustc implicitly.
+//!
+//! This library is never included by default, and must be manually included if
+//! necessary. It is an error to include this library when also linking with
+//! the system libc library.
+
+#![crate_name = "rlibc"]
+#![crate_type = "rlib"]
+
+#![no_std]
+
+// This library defines the builtin functions, so it would be a shame for
+// LLVM to optimize these function calls to themselves!
+#![no_builtins]
+
+extern crate core;
+
+#[phase(plugin, link)]
+#[cfg(test)] extern crate std;
+#[cfg(test)] extern crate native;
+
+use core::ptr::PtrExt;
+
+#[no_mangle]
+pub unsafe extern fn memcpy(dest: *mut u8, src: *const u8,
+                            n: uint) -> *mut u8 {
+    let mut i = 0;
+    while i < n {
+        *dest.offset(i as int) = *src.offset(i as int);
+        i += 1;
+    }
+    return dest;
+}
+
+#[no_mangle]
+pub unsafe extern fn memmove(dest: *mut u8, src: *const u8,
+                             n: uint) -> *mut u8 {
+    if src < dest as *const u8 { // copy from end
+        let mut i = n;
+        while i != 0 {
+            i -= 1;
+            *dest.offset(i as int) = *src.offset(i as int);
+        }
+    } else { // copy from beginning
+        let mut i = 0;
+        while i < n {
+            *dest.offset(i as int) = *src.offset(i as int);
+            i += 1;
+        }
+    }
+    return dest;
+}
+
+#[no_mangle]
+pub unsafe extern fn memset(s: *mut u8, c: i32, n: uint) -> *mut u8 {
+    let mut i = 0;
+    while i < n {
+        *s.offset(i as int) = c as u8;
+        i += 1;
+    }
+    return s;
+}
+
+#[no_mangle]
+pub unsafe extern fn memcmp(s1: *const u8, s2: *const u8, n: uint) -> i32 {
+    let mut i = 0;
+    while i < n {
+        let a = *s1.offset(i as int);
+        let b = *s2.offset(i as int);
+        if a != b {
+            return a as i32 - b as i32
+        }
+        i += 1;
+    }
+    return 0;
+}
+
+#[cfg(test)]
+mod test {
+    use core::str::StrSlice;
+    use core::slice::{MutableSlice, ImmutableSlice};
+
+    use super::{memcmp, memset, memcpy, memmove};
+
+    #[test]
+    fn memcmp_single_byte_pointers() {
+        unsafe {
+            assert_eq!(memcmp(&0xFAu8, &0xFAu8, 1), 0x00);
+            assert!(memcmp(&0xEFu8, &0xFEu8, 1) < 0x00);
+        }
+    }
+
+    #[test]
+    fn memcmp_strings() {
+        {
+            let (x, z) = ("Hello!", "Good Bye.");
+            let l = x.len();
+            unsafe {
+                assert_eq!(memcmp(x.as_ptr(), x.as_ptr(), l), 0);
+                assert!(memcmp(x.as_ptr(), z.as_ptr(), l) > 0);
+                assert!(memcmp(z.as_ptr(), x.as_ptr(), l) < 0);
+            }
+        }
+        {
+            let (x, z) = ("hey!", "hey.");
+            let l = x.len();
+            unsafe {
+                assert!(memcmp(x.as_ptr(), z.as_ptr(), l) < 0);
+            }
+        }
+    }
+
+    #[test]
+    fn memset_single_byte_pointers() {
+        let mut x: u8 = 0xFF;
+        unsafe {
+            memset(&mut x, 0xAA, 1);
+            assert_eq!(x, 0xAA);
+            memset(&mut x, 0x00, 1);
+            assert_eq!(x, 0x00);
+            x = 0x01;
+            memset(&mut x, 0x12, 0);
+            assert_eq!(x, 0x01);
+        }
+    }
+
+    #[test]
+    fn memset_array() {
+        let mut buffer = [b'X', .. 100];
+        unsafe {
+            memset(buffer.as_mut_ptr(), b'#' as i32, buffer.len());
+        }
+        for byte in buffer.iter() { assert_eq!(*byte, b'#'); }
+    }
+
+    #[test]
+    fn memcpy_and_memcmp_arrays() {
+        let (src, mut dst) = ([b'X', .. 100], [b'Y', .. 100]);
+        unsafe {
+            assert!(memcmp(src.as_ptr(), dst.as_ptr(), 100) != 0);
+            let _ = memcpy(dst.as_mut_ptr(), src.as_ptr(), 100);
+            assert_eq!(memcmp(src.as_ptr(), dst.as_ptr(), 100), 0);
+        }
+    }
+
+    #[test]
+    fn memmove_overlapping() {
+        {
+            let mut buffer = [ b'0', b'1', b'2', b'3', b'4', b'5', b'6', b'7', b'8', b'9' ];
+            unsafe {
+                memmove(&mut buffer[4], &buffer[0], 6);
+                let mut i = 0;
+                for byte in b"0123012345".iter() {
+                    assert_eq!(buffer[i], *byte);
+                    i += 1;
+                }
+            }
+        }
+        {
+            let mut buffer = [ b'0', b'1', b'2', b'3', b'4', b'5', b'6', b'7', b'8', b'9' ];
+            unsafe {
+                memmove(&mut buffer[0], &buffer[4], 6);
+                let mut i = 0;
+                for byte in b"4567896789".iter() {
+                    assert_eq!(buffer[i], *byte);
+                    i += 1;
+                }
+            }
+        }
+    }
+}

From 3e049cf3c9e3286a6b136f51404fb8ab1e96cce1 Mon Sep 17 00:00:00 2001
From: Vladimir Pouzanov <farcaller@gmail.com>
Date: Sun, 11 Jan 2015 22:41:45 +0000
Subject: [PATCH 20/32] Fixed all the other demo apps

---
 apps/app_blink_k20.rs       | 2 +-
 apps/app_blink_k20_isr.rs   | 2 +-
 apps/app_blink_stm32f4.rs   | 2 +-
 apps/app_blink_stm32l1.rs   | 2 +-
 apps/app_blink_tiva_c.rs    | 2 +-
 apps/app_bluenrg_stm32l1.rs | 2 +-
 apps/app_uart_tiva_c.rs     | 2 +-
 apps/app_usart_stm32l1.rs   | 2 +-
 8 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/apps/app_blink_k20.rs b/apps/app_blink_k20.rs
index fcfa299e..e275df2b 100644
--- a/apps/app_blink_k20.rs
+++ b/apps/app_blink_k20.rs
@@ -1,4 +1,4 @@
-#![feature(phase)]
+#![feature(plugin)]
 #![crate_type="staticlib"]
 #![no_std]
 
diff --git a/apps/app_blink_k20_isr.rs b/apps/app_blink_k20_isr.rs
index 4c60c874..250a7fe4 100644
--- a/apps/app_blink_k20_isr.rs
+++ b/apps/app_blink_k20_isr.rs
@@ -1,4 +1,4 @@
-#![feature(phase)]
+#![feature(plugin)]
 #![feature(asm)]
 #![crate_type="staticlib"]
 #![no_std]
diff --git a/apps/app_blink_stm32f4.rs b/apps/app_blink_stm32f4.rs
index bfb8ffcb..d1ad204b 100644
--- a/apps/app_blink_stm32f4.rs
+++ b/apps/app_blink_stm32f4.rs
@@ -1,4 +1,4 @@
-#![feature(phase)]
+#![feature(plugin)]
 #![crate_type="staticlib"]
 #![no_std]
 
diff --git a/apps/app_blink_stm32l1.rs b/apps/app_blink_stm32l1.rs
index 6d998635..e4031d1c 100644
--- a/apps/app_blink_stm32l1.rs
+++ b/apps/app_blink_stm32l1.rs
@@ -1,4 +1,4 @@
-#![feature(phase)]
+#![feature(plugin)]
 #![crate_type="staticlib"]
 #![no_std]
 
diff --git a/apps/app_blink_tiva_c.rs b/apps/app_blink_tiva_c.rs
index 78f07a31..db574638 100644
--- a/apps/app_blink_tiva_c.rs
+++ b/apps/app_blink_tiva_c.rs
@@ -1,4 +1,4 @@
-#![feature(phase)]
+#![feature(plugin)]
 #![crate_type="staticlib"]
 #![no_std]
 
diff --git a/apps/app_bluenrg_stm32l1.rs b/apps/app_bluenrg_stm32l1.rs
index 3f6cf035..23221c6e 100644
--- a/apps/app_bluenrg_stm32l1.rs
+++ b/apps/app_bluenrg_stm32l1.rs
@@ -1,4 +1,4 @@
-#![feature(phase)]
+#![feature(plugin)]
 #![crate_type="staticlib"]
 #![no_std]
 
diff --git a/apps/app_uart_tiva_c.rs b/apps/app_uart_tiva_c.rs
index ff3b1474..8b7ded92 100644
--- a/apps/app_uart_tiva_c.rs
+++ b/apps/app_uart_tiva_c.rs
@@ -1,4 +1,4 @@
-#![feature(phase)]
+#![feature(plugin)]
 #![crate_type="staticlib"]
 #![no_std]
 
diff --git a/apps/app_usart_stm32l1.rs b/apps/app_usart_stm32l1.rs
index 5cf8f95e..662a37d6 100644
--- a/apps/app_usart_stm32l1.rs
+++ b/apps/app_usart_stm32l1.rs
@@ -1,4 +1,4 @@
-#![feature(phase)]
+#![feature(plugin)]
 #![crate_type="staticlib"]
 #![no_std]
 

From fe84f5a516617d048dd857e94beccd7b2999b154 Mon Sep 17 00:00:00 2001
From: Ben Gamari <bgamari.foss@gmail.com>
Date: Tue, 13 Jan 2015 18:02:34 -0500
Subject: [PATCH 21/32] ioreg::test: Fix imports

---
 src/ioreg/test.rs | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/ioreg/test.rs b/src/ioreg/test.rs
index aa1167c9..2af137c3 100644
--- a/src/ioreg/test.rs
+++ b/src/ioreg/test.rs
@@ -15,9 +15,10 @@
 
 //! Tests for ioreg! syntax extension
 
-#![feature(phase)]
-#[phase(plugin)] extern crate ioreg;
-#[phase(plugin,link)] extern crate shiny;
+#![feature(plugin)]
+
+#[plugin] extern crate ioreg;
+#[plugin] extern crate shiny;
 extern crate core;
 
 #[path="../zinc/util/volatile_cell.rs"] mod volatile_cell;

From fff99307d112510e07b539d66636a9aec0a17c68 Mon Sep 17 00:00:00 2001
From: Ben Gamari <bgamari.foss@gmail.com>
Date: Tue, 13 Jan 2015 18:05:51 -0500
Subject: [PATCH 22/32] ioreg::test: Fix uint and int references

---
 src/ioreg/test.rs | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/ioreg/test.rs b/src/ioreg/test.rs
index 2af137c3..4aeca2c4 100644
--- a/src/ioreg/test.rs
+++ b/src/ioreg/test.rs
@@ -29,10 +29,10 @@ mod test {
   use std::ptr::PtrExt;
   use volatile_cell::VolatileCell;
 
-  fn get_value<'a, T>(v: &'a T, offset: uint) -> u32 {
+  fn get_value<'a, T>(v: &'a T, offset: usize) -> u32 {
     unsafe {
       let ptr: *const u32 = transmute(v);
-      *(ptr.offset(offset as int))
+      *(ptr.offset(offset as isize))
     }
   }
 
@@ -163,15 +163,15 @@ mod test {
     }
     it "has zero base offset" {
       let addr = &test.reg1 as *const GAP_TEST_reg1;
-      assert_eq!(addr as uint - base as uint, 0x0);
+      assert_eq!(addr as usize - base as usize, 0x0);
     }
     it "computes the correct first gap" {
       let addr = &test.reg2 as *const GAP_TEST_reg2;
-      assert_eq!(addr as uint - base as uint, 0x10);
+      assert_eq!(addr as usize - base as usize, 0x10);
     }
     it "computes the correct second gap" {
       let addr = &test.reg4 as *const GAP_TEST_reg4;
-      assert_eq!(addr as uint - base as uint, 0x20);
+      assert_eq!(addr as usize - base as usize, 0x20);
     }
   );
 }

From bcf26a84f485251c175fc4e072e024aa99de5e3b Mon Sep 17 00:00:00 2001
From: Ben Gamari <bgamari.foss@gmail.com>
Date: Tue, 13 Jan 2015 18:22:02 -0500
Subject: [PATCH 23/32] ioreg::builder::union: Give unions Copy impls

---
 src/ioreg/builder/union.rs | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/src/ioreg/builder/union.rs b/src/ioreg/builder/union.rs
index 4b6337c1..a19df6f1 100644
--- a/src/ioreg/builder/union.rs
+++ b/src/ioreg/builder/union.rs
@@ -108,9 +108,10 @@ fn reg_struct_type(cx: &ExtCtxt, path: &Vec<String>, reg: &node::Reg)
 impl<'a> node::RegVisitor for BuildUnionTypes<'a> {
   fn visit_union_reg<'b>(&'b mut self, path: &Vec<String>, reg: &'b node::Reg,
                          subregs: Rc<Vec<node::Reg>>) {
-    let union_type = self.build_union_type(path, reg, &*subregs);
-    let ty_name = union_type.ident.clone();
-    self.builder.push_item(union_type);
+    let items = self.build_union_type(path, reg, &*subregs);
+    for item in items.into_iter() {
+      self.builder.push_item(item);
+    }
   }
 }
 
@@ -166,9 +167,8 @@ impl<'a> BuildUnionTypes<'a> {
 
   /// Build the type associated with a register group
   fn build_union_type(&self, path: &Vec<String>, reg: &node::Reg,
-                      regs: &Vec<node::Reg>) -> P<ast::Item> {
-    let name = String::from_str(
-        token::get_ident(utils::path_ident(self.cx, path)).get());
+                      regs: &Vec<node::Reg>) -> Vec<P<ast::Item>> {
+    let name = utils::path_ident(self.cx, path);
     // Registers are already sorted by parser
     let mut regs = regs.clone();
     let padded_regs = PaddedRegsIterator::new(&mut regs);
@@ -190,13 +190,15 @@ impl<'a> BuildUnionTypes<'a> {
           utils::doc_attribute(self.cx, token::get_ident(docstring.node))),
       None => (),
     }
-    P(ast::Item {
-      ident: self.cx.ident_of(name.as_slice()),
+    let struct_item = P(ast::Item {
+      ident: name,
       attrs: attrs,
       id: ast::DUMMY_NODE_ID,
       node: ast::ItemStruct(P(struct_def), empty_generics()),
       vis: ast::Public,
       span: reg.name.span,
-    })
+    });
+    let copy_impl = quote_item!(self.cx, impl ::core::marker::Copy for $name {}).unwrap();
+    vec!(struct_item, copy_impl)
   }
 }

From f71928b75f62d8f862f1033f3f4f39dd45820b23 Mon Sep 17 00:00:00 2001
From: Ben Gamari <bgamari.foss@gmail.com>
Date: Tue, 13 Jan 2015 18:56:20 -0500
Subject: [PATCH 24/32] ioreg: Fix integer overflow

---
 src/ioreg/builder/utils.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/ioreg/builder/utils.rs b/src/ioreg/builder/utils.rs
index d462682f..d01483bb 100644
--- a/src/ioreg/builder/utils.rs
+++ b/src/ioreg/builder/utils.rs
@@ -110,7 +110,7 @@ pub fn field_type_path(cx: &ExtCtxt, path: &Vec<String>,
 
 /// Build an expression for the mask of a field
 pub fn mask(cx: &ExtCtxt, field: &node::Field) -> P<ast::Expr> {
-  expr_int(cx, ((1 << field.width) - 1) as i64)
+  expr_int(cx, ((1 << field.width as u64) - 1))
 }
 
 /// Build an expression for the shift of a field (including the array

From 2cbfdef0aace6d5af33e707e41c7776f8191681a Mon Sep 17 00:00:00 2001
From: Ben Gamari <bgamari.foss@gmail.com>
Date: Tue, 13 Jan 2015 18:57:06 -0500
Subject: [PATCH 25/32] ioreg: Add Copy impl for primitive register structs

---
 src/ioreg/builder/register.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/ioreg/builder/register.rs b/src/ioreg/builder/register.rs
index 26d89199..c6961829 100644
--- a/src/ioreg/builder/register.rs
+++ b/src/ioreg/builder/register.rs
@@ -122,8 +122,8 @@ fn build_reg_struct(cx: &ExtCtxt, path: &Vec<String>,
   );
   let mut item: ast::Item = item.unwrap().deref().clone();
   item.span = reg.name.span;
-  // let copy_impl = quote_item!(cx, impl ::core::marker::Copy for $ty_name {}).unwrap();
-  vec!(P(item))
+  let copy_impl = quote_item!(cx, impl ::core::marker::Copy for $ty_name {}).unwrap();
+  vec!(P(item), copy_impl)
 }
 
 /// Build a variant of an `EnumField`

From 604347d6c0dfc81b9ca70886c149f3a6dced19f1 Mon Sep 17 00:00:00 2001
From: Ben Gamari <bgamari.foss@gmail.com>
Date: Tue, 13 Jan 2015 18:57:56 -0500
Subject: [PATCH 26/32] platformtree: Use Box::new instead of box

---
 src/platformtree/test_helpers.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/platformtree/test_helpers.rs b/src/platformtree/test_helpers.rs
index 4ea1a215..b58367e5 100644
--- a/src/platformtree/test_helpers.rs
+++ b/src/platformtree/test_helpers.rs
@@ -67,7 +67,7 @@ pub fn with_parsed_tts<F>(src: &str, block: F)
     where F: Fn(&mut ExtCtxt, *mut bool, Option<Rc<node::PlatformTree>>) {
   let mut failed = false;
   let failptr = &mut failed as *mut bool;
-  let ce = box CustomEmmiter::new(failptr);
+  let ce = Box::new(CustomEmmiter::new(failptr));
   let sh = mk_span_handler(mk_handler(ce), CodeMap::new());
   let parse_sess = new_parse_sess_special_handler(sh);
   let cfg = Vec::new();

From 21f5ad890b4acedaa5deac1d3303f3d89511daeb Mon Sep 17 00:00:00 2001
From: Ben Gamari <bgamari.foss@gmail.com>
Date: Tue, 13 Jan 2015 18:59:03 -0500
Subject: [PATCH 27/32] platformtree: deriving_hash_type_parameter no longer
 exists

---
 src/platformtree/test_helpers.rs | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/platformtree/test_helpers.rs b/src/platformtree/test_helpers.rs
index b58367e5..74f61f47 100644
--- a/src/platformtree/test_helpers.rs
+++ b/src/platformtree/test_helpers.rs
@@ -73,7 +73,6 @@ pub fn with_parsed_tts<F>(src: &str, block: F)
   let cfg = Vec::new();
   let ecfg = ExpansionConfig {
     crate_name: ("test").parse().unwrap(),
-    deriving_hash_type_parameter: false,
     enable_quotes: true,
     recursion_limit: 10,
   };

From 077c2071899afea66fb082eb2385e7daa1790521 Mon Sep 17 00:00:00 2001
From: Ben Gamari <bgamari.foss@gmail.com>
Date: Tue, 13 Jan 2015 18:59:39 -0500
Subject: [PATCH 28/32] bluenrg: macro_use instead of phase(plugin)

---
 apps/app_bluenrg_stm32l1.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/apps/app_bluenrg_stm32l1.rs b/apps/app_bluenrg_stm32l1.rs
index 23221c6e..1e5b8b7b 100644
--- a/apps/app_bluenrg_stm32l1.rs
+++ b/apps/app_bluenrg_stm32l1.rs
@@ -5,7 +5,7 @@
 //! Sample application for BlueNRG communication over SPI in X-NUCLEO-IDB04A1
 //! extension board for NUCLEO-L152RE
 
-#[phase(plugin, link)]
+#[macro_use] #[plugin]
 extern crate core;
 extern crate zinc;
 

From 03a8cf7c8fec6fedf28bacf164fff1e3bbb46130 Mon Sep 17 00:00:00 2001
From: Ben Gamari <bgamari.foss@gmail.com>
Date: Tue, 13 Jan 2015 19:18:46 -0500
Subject: [PATCH 29/32] platformtree: Fix usize literal suffix in test

---
 src/platformtree/builder/os.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/platformtree/builder/os.rs b/src/platformtree/builder/os.rs
index 720cf46e..9a5cf39a 100644
--- a/src/platformtree/builder/os.rs
+++ b/src/platformtree/builder/os.rs
@@ -273,7 +273,7 @@ mod test {
       assert_equal_source(builder.main_stmts[0].deref(),
           "loop {
             run(&pt::run_args {
-              a: 1u,
+              a: 1us,
               b: \"a\",
               c: &named,
             });

From dd46e7f67b1ca73d69592383ff0d64915c554eda Mon Sep 17 00:00:00 2001
From: Vladimir Pouzanov <farcaller@gmail.com>
Date: Wed, 14 Jan 2015 18:06:27 +0000
Subject: [PATCH 30/32] Return std that is used in tests

---
 src/zinc/drivers/lcd/mod.rs | 1 +
 src/zinc/lib.rs             | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/src/zinc/drivers/lcd/mod.rs b/src/zinc/drivers/lcd/mod.rs
index 3931462d..b6bec101 100644
--- a/src/zinc/drivers/lcd/mod.rs
+++ b/src/zinc/drivers/lcd/mod.rs
@@ -160,6 +160,7 @@ mod test {
   use core::mem::zeroed;
   use core::iter::{Range, range};
   use core::cell::Cell;
+  use core::ops::Fn;
 
   use drivers::chario::CharIO;
   use drivers::lcd::LCD;
diff --git a/src/zinc/lib.rs b/src/zinc/lib.rs
index b589de8b..0963cb6f 100644
--- a/src/zinc/lib.rs
+++ b/src/zinc/lib.rs
@@ -52,6 +52,8 @@ STM32F403/407).
 
 #[macro_use] #[no_link] #[plugin] extern crate ioreg;
 
+#[cfg(test)] extern crate std;
+
 pub mod drivers;
 pub mod hal;
 pub mod util;

From 110c5ab06de71767a224ecb6ce6ab95b5ff8095e Mon Sep 17 00:00:00 2001
From: Vladimir Pouzanov <farcaller@gmail.com>
Date: Wed, 14 Jan 2015 18:19:09 +0000
Subject: [PATCH 31/32] "Fixed" bluenrg demo to compile.

---
 apps/app_bluenrg_stm32l1.rs | 35 ++++++++++++++++++++++-------------
 1 file changed, 22 insertions(+), 13 deletions(-)

diff --git a/apps/app_bluenrg_stm32l1.rs b/apps/app_bluenrg_stm32l1.rs
index 1e5b8b7b..d232facf 100644
--- a/apps/app_bluenrg_stm32l1.rs
+++ b/apps/app_bluenrg_stm32l1.rs
@@ -97,23 +97,32 @@ pub unsafe fn main() {
     pin::PullType::PullUp);
 
   bnrg_reset.set_low();
-  let _ = write!(&mut uart, "SPI created, status = {}\n",
-    map_byte(spi.get_status()));
+  let status_s = map_byte(spi.get_status());
+  let _ = write!(&mut uart, "SPI created, status = {}{}\n", status_s.0, status_s.1);
   bnrg_reset.set_high();
 
   let blue = bluenrg::BlueNrg::new(spi_csn, spi);
 
-  let _ = match blue.wakeup(100) {
-    Result::Ok((size_write, size_read)) => write!(&mut uart,
-      "BlueNRG is ready, write size = {}, read size = {}\n",
-      map_byte(size_write as u8), map_byte(size_read as u8)),
-    Result::Err(bluenrg::Error::Sleeping) => write!(&mut uart,
-      "BlueNRG is sleeping\n"),
-    Result::Err(bluenrg::Error::Allocating) => write!(&mut uart,
-      "BlueNRG is allocating buffers\n"),
-    Result::Err(bluenrg::Error::Unknown(status)) => write!(&mut uart,
-      "BlueNRG unknown status = {}\n", map_byte(status)),
-    Result::Err(bluenrg::Error::BufferSize(_)) => write!(&mut uart, ""),
+  match blue.wakeup(100) {
+    Result::Ok((size_write, size_read)) => {
+      let size_write_s = map_byte(size_write as u8);
+      let size_read_s = map_byte(size_read as u8);
+      write!(&mut uart,
+        "BlueNRG is ready, write size = {}{}, read size = {}{}\n",
+        size_write_s.0, size_write_s.1, size_read_s.0, size_read_s.1);
+    },
+    Result::Err(bluenrg::Error::Sleeping) => {
+      write!(&mut uart, "BlueNRG is sleeping\n");
+    },
+    Result::Err(bluenrg::Error::Allocating) => {
+      write!(&mut uart, "BlueNRG is allocating buffers\n");
+    },
+    Result::Err(bluenrg::Error::Unknown(status)) => {
+      let status_s = map_byte(status);
+      write!(&mut uart,
+        "BlueNRG unknown status = {}{}\n", status_s.0, status_s.1);
+    },
+    Result::Err(bluenrg::Error::BufferSize(_)) => { write!(&mut uart, ""); }
   };
 
   loop {}

From 0b0a412e808fd5e46ab94ff333f10bff684ffdb3 Mon Sep 17 00:00:00 2001
From: Vladimir Pouzanov <farcaller@gmail.com>
Date: Wed, 14 Jan 2015 18:20:05 +0000
Subject: [PATCH 32/32] Fixed missing plugin feature in tiva_c demo

---
 apps/app_lcd_tiva_c.rs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/apps/app_lcd_tiva_c.rs b/apps/app_lcd_tiva_c.rs
index 44ccba2a..86b6d93f 100644
--- a/apps/app_lcd_tiva_c.rs
+++ b/apps/app_lcd_tiva_c.rs
@@ -1,3 +1,4 @@
+#![feature(plugin)]
 #![crate_type="staticlib"]
 #![no_std]