diff --git a/test/tint/builtins/gen/literal/quadSwapDiagonal/15ac75.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapDiagonal/15ac75.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..8f8055eb54c
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapDiagonal/15ac75.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+vector<float16_t, 2> quadSwapDiagonal_15ac75() {
+  vector<float16_t, 2> res = QuadReadAcrossDiagonal((float16_t(1.0h)).xx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<vector<float16_t, 2> >(0u, quadSwapDiagonal_15ac75());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<vector<float16_t, 2> >(0u, quadSwapDiagonal_15ac75());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapDiagonal/2be5e7.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapDiagonal/2be5e7.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..8d969f2b173
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapDiagonal/2be5e7.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float16_t quadSwapDiagonal_2be5e7() {
+  float16_t res = QuadReadAcrossDiagonal(float16_t(1.0h));
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<float16_t>(0u, quadSwapDiagonal_2be5e7());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<float16_t>(0u, quadSwapDiagonal_2be5e7());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapDiagonal/331804.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapDiagonal/331804.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..05e5a753240
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapDiagonal/331804.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float4 quadSwapDiagonal_331804() {
+  float4 res = QuadReadAcrossDiagonal((1.0f).xxxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapDiagonal_331804()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapDiagonal_331804()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapDiagonal/348173.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapDiagonal/348173.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..978671961a3
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapDiagonal/348173.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint2 quadSwapDiagonal_348173() {
+  uint2 res = QuadReadAcrossDiagonal((1u).xx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store2(0u, quadSwapDiagonal_348173());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store2(0u, quadSwapDiagonal_348173());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapDiagonal/486196.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapDiagonal/486196.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..6bb38627828
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapDiagonal/486196.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float quadSwapDiagonal_486196() {
+  float res = QuadReadAcrossDiagonal(1.0f);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store(0u, asuint(quadSwapDiagonal_486196()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store(0u, asuint(quadSwapDiagonal_486196()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapDiagonal/730e40.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapDiagonal/730e40.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..f2e47e613a5
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapDiagonal/730e40.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint quadSwapDiagonal_730e40() {
+  uint res = QuadReadAcrossDiagonal(1u);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store(0u, quadSwapDiagonal_730e40());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store(0u, quadSwapDiagonal_730e40());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapDiagonal/8077c8.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapDiagonal/8077c8.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..fcdc9598b0f
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapDiagonal/8077c8.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float2 quadSwapDiagonal_8077c8() {
+  float2 res = QuadReadAcrossDiagonal((1.0f).xx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapDiagonal_8077c8()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapDiagonal_8077c8()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapDiagonal/856536.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapDiagonal/856536.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..1f908ab20a7
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapDiagonal/856536.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint3 quadSwapDiagonal_856536() {
+  uint3 res = QuadReadAcrossDiagonal((1u).xxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store3(0u, quadSwapDiagonal_856536());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store3(0u, quadSwapDiagonal_856536());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapDiagonal/9ccb38.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapDiagonal/9ccb38.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..cdf5db1ef39
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapDiagonal/9ccb38.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int quadSwapDiagonal_9ccb38() {
+  int res = QuadReadAcrossDiagonal(1);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store(0u, asuint(quadSwapDiagonal_9ccb38()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store(0u, asuint(quadSwapDiagonal_9ccb38()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapDiagonal/a090b0.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapDiagonal/a090b0.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..e9a9661bd9d
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapDiagonal/a090b0.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int2 quadSwapDiagonal_a090b0() {
+  int2 res = QuadReadAcrossDiagonal((1).xx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapDiagonal_a090b0()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapDiagonal_a090b0()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapDiagonal/a665b1.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapDiagonal/a665b1.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..19fd095481c
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapDiagonal/a665b1.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int4 quadSwapDiagonal_a665b1() {
+  int4 res = QuadReadAcrossDiagonal((1).xxxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapDiagonal_a665b1()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapDiagonal_a665b1()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapDiagonal/a82e1d.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapDiagonal/a82e1d.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..5357a73e4d3
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapDiagonal/a82e1d.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int3 quadSwapDiagonal_a82e1d() {
+  int3 res = QuadReadAcrossDiagonal((1).xxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapDiagonal_a82e1d()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapDiagonal_a82e1d()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapDiagonal/af19a5.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapDiagonal/af19a5.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..ee2b3c95ff2
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapDiagonal/af19a5.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+vector<float16_t, 4> quadSwapDiagonal_af19a5() {
+  vector<float16_t, 4> res = QuadReadAcrossDiagonal((float16_t(1.0h)).xxxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<vector<float16_t, 4> >(0u, quadSwapDiagonal_af19a5());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<vector<float16_t, 4> >(0u, quadSwapDiagonal_af19a5());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapDiagonal/b905fc.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapDiagonal/b905fc.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..b787d591e3b
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapDiagonal/b905fc.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float3 quadSwapDiagonal_b905fc() {
+  float3 res = QuadReadAcrossDiagonal((1.0f).xxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapDiagonal_b905fc()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapDiagonal_b905fc()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapDiagonal/c31636.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapDiagonal/c31636.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..45f47928cd0
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapDiagonal/c31636.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint4 quadSwapDiagonal_c31636() {
+  uint4 res = QuadReadAcrossDiagonal((1u).xxxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store4(0u, quadSwapDiagonal_c31636());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store4(0u, quadSwapDiagonal_c31636());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapDiagonal/e4bec8.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapDiagonal/e4bec8.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..cd4700f8327
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapDiagonal/e4bec8.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+vector<float16_t, 3> quadSwapDiagonal_e4bec8() {
+  vector<float16_t, 3> res = QuadReadAcrossDiagonal((float16_t(1.0h)).xxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<vector<float16_t, 3> >(0u, quadSwapDiagonal_e4bec8());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<vector<float16_t, 3> >(0u, quadSwapDiagonal_e4bec8());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapX/02834c.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapX/02834c.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..5b0cb7bdaa5
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapX/02834c.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+vector<float16_t, 4> quadSwapX_02834c() {
+  vector<float16_t, 4> res = QuadReadAcrossX((float16_t(1.0h)).xxxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<vector<float16_t, 4> >(0u, quadSwapX_02834c());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<vector<float16_t, 4> >(0u, quadSwapX_02834c());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapX/053f3b.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapX/053f3b.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..2776a64b42d
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapX/053f3b.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int3 quadSwapX_053f3b() {
+  int3 res = QuadReadAcrossX((1).xxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapX_053f3b()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapX_053f3b()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapX/07f1fc.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapX/07f1fc.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..b75db53c7a1
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapX/07f1fc.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint4 quadSwapX_07f1fc() {
+  uint4 res = QuadReadAcrossX((1u).xxxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store4(0u, quadSwapX_07f1fc());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store4(0u, quadSwapX_07f1fc());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapX/150d6f.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapX/150d6f.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..3a05dc07568
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapX/150d6f.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float3 quadSwapX_150d6f() {
+  float3 res = QuadReadAcrossX((1.0f).xxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapX_150d6f()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapX_150d6f()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapX/19f8ce.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapX/19f8ce.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..a68dab65ea6
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapX/19f8ce.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint2 quadSwapX_19f8ce() {
+  uint2 res = QuadReadAcrossX((1u).xx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store2(0u, quadSwapX_19f8ce());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store2(0u, quadSwapX_19f8ce());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapX/1e1086.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapX/1e1086.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..9a5e50e4277
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapX/1e1086.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int quadSwapX_1e1086() {
+  int res = QuadReadAcrossX(1);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store(0u, asuint(quadSwapX_1e1086()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store(0u, asuint(quadSwapX_1e1086()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapX/69af6a.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapX/69af6a.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..45ddbcadb26
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapX/69af6a.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float4 quadSwapX_69af6a() {
+  float4 res = QuadReadAcrossX((1.0f).xxxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapX_69af6a()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapX_69af6a()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapX/8203ad.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapX/8203ad.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..c430b8399e9
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapX/8203ad.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint quadSwapX_8203ad() {
+  uint res = QuadReadAcrossX(1u);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store(0u, quadSwapX_8203ad());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store(0u, quadSwapX_8203ad());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapX/879738.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapX/879738.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..3d9293ef073
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapX/879738.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float2 quadSwapX_879738() {
+  float2 res = QuadReadAcrossX((1.0f).xx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapX_879738()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapX_879738()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapX/9bea80.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapX/9bea80.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..4b93bea00d0
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapX/9bea80.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float quadSwapX_9bea80() {
+  float res = QuadReadAcrossX(1.0f);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store(0u, asuint(quadSwapX_9bea80()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store(0u, asuint(quadSwapX_9bea80()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapX/a4e103.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapX/a4e103.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..03ca6e0e7bd
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapX/a4e103.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float16_t quadSwapX_a4e103() {
+  float16_t res = QuadReadAcrossX(float16_t(1.0h));
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<float16_t>(0u, quadSwapX_a4e103());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<float16_t>(0u, quadSwapX_a4e103());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapX/b1a5fe.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapX/b1a5fe.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..ca6b53c6eaa
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapX/b1a5fe.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int2 quadSwapX_b1a5fe() {
+  int2 res = QuadReadAcrossX((1).xx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapX_b1a5fe()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapX_b1a5fe()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapX/bc2013.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapX/bc2013.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..21849b3a9e5
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapX/bc2013.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+vector<float16_t, 3> quadSwapX_bc2013() {
+  vector<float16_t, 3> res = QuadReadAcrossX((float16_t(1.0h)).xxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<vector<float16_t, 3> >(0u, quadSwapX_bc2013());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<vector<float16_t, 3> >(0u, quadSwapX_bc2013());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapX/bddb9f.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapX/bddb9f.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..3e7cf033c0c
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapX/bddb9f.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint3 quadSwapX_bddb9f() {
+  uint3 res = QuadReadAcrossX((1u).xxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store3(0u, quadSwapX_bddb9f());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store3(0u, quadSwapX_bddb9f());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapX/d60cec.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapX/d60cec.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..014a63606af
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapX/d60cec.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+vector<float16_t, 2> quadSwapX_d60cec() {
+  vector<float16_t, 2> res = QuadReadAcrossX((float16_t(1.0h)).xx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<vector<float16_t, 2> >(0u, quadSwapX_d60cec());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<vector<float16_t, 2> >(0u, quadSwapX_d60cec());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapX/edfa1f.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapX/edfa1f.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..da5a0c166da
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapX/edfa1f.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int4 quadSwapX_edfa1f() {
+  int4 res = QuadReadAcrossX((1).xxxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapX_edfa1f()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapX_edfa1f()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapY/06a67c.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapY/06a67c.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..9f6ff07c1db
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapY/06a67c.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint3 quadSwapY_06a67c() {
+  uint3 res = QuadReadAcrossY((1u).xxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store3(0u, quadSwapY_06a67c());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store3(0u, quadSwapY_06a67c());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapY/0c4938.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapY/0c4938.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..f6aee479d41
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapY/0c4938.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint quadSwapY_0c4938() {
+  uint res = QuadReadAcrossY(1u);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store(0u, quadSwapY_0c4938());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store(0u, quadSwapY_0c4938());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapY/0d05a8.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapY/0d05a8.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..3c3408b9062
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapY/0d05a8.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int2 quadSwapY_0d05a8() {
+  int2 res = QuadReadAcrossY((1).xx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapY_0d05a8()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapY_0d05a8()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapY/14bb9a.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapY/14bb9a.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..c90ea4dd7e8
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapY/14bb9a.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int4 quadSwapY_14bb9a() {
+  int4 res = QuadReadAcrossY((1).xxxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapY_14bb9a()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapY_14bb9a()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapY/1f1a06.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapY/1f1a06.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..6189828f065
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapY/1f1a06.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float2 quadSwapY_1f1a06() {
+  float2 res = QuadReadAcrossY((1.0f).xx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapY_1f1a06()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapY_1f1a06()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapY/264908.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapY/264908.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..e0e368c82b4
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapY/264908.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+vector<float16_t, 3> quadSwapY_264908() {
+  vector<float16_t, 3> res = QuadReadAcrossY((float16_t(1.0h)).xxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<vector<float16_t, 3> >(0u, quadSwapY_264908());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<vector<float16_t, 3> >(0u, quadSwapY_264908());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapY/5b2e67.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapY/5b2e67.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..248f4d57c21
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapY/5b2e67.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+vector<float16_t, 4> quadSwapY_5b2e67() {
+  vector<float16_t, 4> res = QuadReadAcrossY((float16_t(1.0h)).xxxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<vector<float16_t, 4> >(0u, quadSwapY_5b2e67());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<vector<float16_t, 4> >(0u, quadSwapY_5b2e67());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapY/6f6bc9.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapY/6f6bc9.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..3cacb46a3ab
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapY/6f6bc9.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float quadSwapY_6f6bc9() {
+  float res = QuadReadAcrossY(1.0f);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store(0u, asuint(quadSwapY_6f6bc9()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store(0u, asuint(quadSwapY_6f6bc9()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapY/9277e9.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapY/9277e9.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..21314d18384
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapY/9277e9.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float16_t quadSwapY_9277e9() {
+  float16_t res = QuadReadAcrossY(float16_t(1.0h));
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<float16_t>(0u, quadSwapY_9277e9());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<float16_t>(0u, quadSwapY_9277e9());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapY/94ab6d.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapY/94ab6d.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..e14e70701ef
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapY/94ab6d.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int quadSwapY_94ab6d() {
+  int res = QuadReadAcrossY(1);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store(0u, asuint(quadSwapY_94ab6d()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store(0u, asuint(quadSwapY_94ab6d()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapY/a27e1c.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapY/a27e1c.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..31b44b46396
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapY/a27e1c.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint2 quadSwapY_a27e1c() {
+  uint2 res = QuadReadAcrossY((1u).xx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store2(0u, quadSwapY_a27e1c());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store2(0u, quadSwapY_a27e1c());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapY/a50fcb.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapY/a50fcb.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..f85dde5d9d0
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapY/a50fcb.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+vector<float16_t, 2> quadSwapY_a50fcb() {
+  vector<float16_t, 2> res = QuadReadAcrossY((float16_t(1.0h)).xx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<vector<float16_t, 2> >(0u, quadSwapY_a50fcb());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<vector<float16_t, 2> >(0u, quadSwapY_a50fcb());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapY/b9d9e7.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapY/b9d9e7.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..46a48eee369
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapY/b9d9e7.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float4 quadSwapY_b9d9e7() {
+  float4 res = QuadReadAcrossY((1.0f).xxxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapY_b9d9e7()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapY_b9d9e7()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapY/bb697b.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapY/bb697b.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..0161e71cd85
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapY/bb697b.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint4 quadSwapY_bb697b() {
+  uint4 res = QuadReadAcrossY((1u).xxxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store4(0u, quadSwapY_bb697b());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store4(0u, quadSwapY_bb697b());
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapY/be4e72.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapY/be4e72.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..0168d0da835
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapY/be4e72.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int3 quadSwapY_be4e72() {
+  int3 res = QuadReadAcrossY((1).xxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapY_be4e72()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapY_be4e72()));
+}
+
diff --git a/test/tint/builtins/gen/literal/quadSwapY/d1ab4d.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/quadSwapY/d1ab4d.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..06c54cb8e38
--- /dev/null
+++ b/test/tint/builtins/gen/literal/quadSwapY/d1ab4d.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,16 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float3 quadSwapY_d1ab4d() {
+  float3 res = QuadReadAcrossY((1.0f).xxx);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapY_d1ab4d()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapY_d1ab4d()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapDiagonal/15ac75.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapDiagonal/15ac75.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..57855d13152
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapDiagonal/15ac75.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+vector<float16_t, 2> quadSwapDiagonal_15ac75() {
+  vector<float16_t, 2> arg_0 = (float16_t(1.0h)).xx;
+  vector<float16_t, 2> res = QuadReadAcrossDiagonal(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<vector<float16_t, 2> >(0u, quadSwapDiagonal_15ac75());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<vector<float16_t, 2> >(0u, quadSwapDiagonal_15ac75());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapDiagonal/2be5e7.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapDiagonal/2be5e7.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..454c27c3069
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapDiagonal/2be5e7.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float16_t quadSwapDiagonal_2be5e7() {
+  float16_t arg_0 = float16_t(1.0h);
+  float16_t res = QuadReadAcrossDiagonal(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<float16_t>(0u, quadSwapDiagonal_2be5e7());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<float16_t>(0u, quadSwapDiagonal_2be5e7());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapDiagonal/331804.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapDiagonal/331804.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..897bd2c5e80
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapDiagonal/331804.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float4 quadSwapDiagonal_331804() {
+  float4 arg_0 = (1.0f).xxxx;
+  float4 res = QuadReadAcrossDiagonal(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapDiagonal_331804()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapDiagonal_331804()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapDiagonal/348173.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapDiagonal/348173.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..ed7273edc2a
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapDiagonal/348173.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint2 quadSwapDiagonal_348173() {
+  uint2 arg_0 = (1u).xx;
+  uint2 res = QuadReadAcrossDiagonal(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store2(0u, quadSwapDiagonal_348173());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store2(0u, quadSwapDiagonal_348173());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapDiagonal/486196.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapDiagonal/486196.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..62114c74796
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapDiagonal/486196.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float quadSwapDiagonal_486196() {
+  float arg_0 = 1.0f;
+  float res = QuadReadAcrossDiagonal(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store(0u, asuint(quadSwapDiagonal_486196()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store(0u, asuint(quadSwapDiagonal_486196()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapDiagonal/730e40.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapDiagonal/730e40.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..06a46fbeac2
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapDiagonal/730e40.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint quadSwapDiagonal_730e40() {
+  uint arg_0 = 1u;
+  uint res = QuadReadAcrossDiagonal(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store(0u, quadSwapDiagonal_730e40());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store(0u, quadSwapDiagonal_730e40());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapDiagonal/8077c8.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapDiagonal/8077c8.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..0ee9b2a654c
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapDiagonal/8077c8.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float2 quadSwapDiagonal_8077c8() {
+  float2 arg_0 = (1.0f).xx;
+  float2 res = QuadReadAcrossDiagonal(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapDiagonal_8077c8()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapDiagonal_8077c8()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapDiagonal/856536.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapDiagonal/856536.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..791dfedfc35
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapDiagonal/856536.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint3 quadSwapDiagonal_856536() {
+  uint3 arg_0 = (1u).xxx;
+  uint3 res = QuadReadAcrossDiagonal(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store3(0u, quadSwapDiagonal_856536());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store3(0u, quadSwapDiagonal_856536());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapDiagonal/9ccb38.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapDiagonal/9ccb38.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..60710a8c21f
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapDiagonal/9ccb38.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int quadSwapDiagonal_9ccb38() {
+  int arg_0 = 1;
+  int res = QuadReadAcrossDiagonal(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store(0u, asuint(quadSwapDiagonal_9ccb38()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store(0u, asuint(quadSwapDiagonal_9ccb38()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapDiagonal/a090b0.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapDiagonal/a090b0.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..da01676ce2d
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapDiagonal/a090b0.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int2 quadSwapDiagonal_a090b0() {
+  int2 arg_0 = (1).xx;
+  int2 res = QuadReadAcrossDiagonal(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapDiagonal_a090b0()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapDiagonal_a090b0()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapDiagonal/a665b1.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapDiagonal/a665b1.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..0af211aa5c5
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapDiagonal/a665b1.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int4 quadSwapDiagonal_a665b1() {
+  int4 arg_0 = (1).xxxx;
+  int4 res = QuadReadAcrossDiagonal(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapDiagonal_a665b1()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapDiagonal_a665b1()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapDiagonal/a82e1d.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapDiagonal/a82e1d.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..c9a884ee73d
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapDiagonal/a82e1d.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int3 quadSwapDiagonal_a82e1d() {
+  int3 arg_0 = (1).xxx;
+  int3 res = QuadReadAcrossDiagonal(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapDiagonal_a82e1d()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapDiagonal_a82e1d()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapDiagonal/af19a5.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapDiagonal/af19a5.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..381b6002d22
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapDiagonal/af19a5.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+vector<float16_t, 4> quadSwapDiagonal_af19a5() {
+  vector<float16_t, 4> arg_0 = (float16_t(1.0h)).xxxx;
+  vector<float16_t, 4> res = QuadReadAcrossDiagonal(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<vector<float16_t, 4> >(0u, quadSwapDiagonal_af19a5());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<vector<float16_t, 4> >(0u, quadSwapDiagonal_af19a5());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapDiagonal/b905fc.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapDiagonal/b905fc.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..9c752d9ae4d
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapDiagonal/b905fc.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float3 quadSwapDiagonal_b905fc() {
+  float3 arg_0 = (1.0f).xxx;
+  float3 res = QuadReadAcrossDiagonal(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapDiagonal_b905fc()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapDiagonal_b905fc()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapDiagonal/c31636.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapDiagonal/c31636.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..f5ab37e7c32
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapDiagonal/c31636.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint4 quadSwapDiagonal_c31636() {
+  uint4 arg_0 = (1u).xxxx;
+  uint4 res = QuadReadAcrossDiagonal(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store4(0u, quadSwapDiagonal_c31636());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store4(0u, quadSwapDiagonal_c31636());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapDiagonal/e4bec8.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapDiagonal/e4bec8.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..3a3230bf1c4
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapDiagonal/e4bec8.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+vector<float16_t, 3> quadSwapDiagonal_e4bec8() {
+  vector<float16_t, 3> arg_0 = (float16_t(1.0h)).xxx;
+  vector<float16_t, 3> res = QuadReadAcrossDiagonal(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<vector<float16_t, 3> >(0u, quadSwapDiagonal_e4bec8());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<vector<float16_t, 3> >(0u, quadSwapDiagonal_e4bec8());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapX/02834c.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapX/02834c.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..babcfc1bb79
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapX/02834c.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+vector<float16_t, 4> quadSwapX_02834c() {
+  vector<float16_t, 4> arg_0 = (float16_t(1.0h)).xxxx;
+  vector<float16_t, 4> res = QuadReadAcrossX(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<vector<float16_t, 4> >(0u, quadSwapX_02834c());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<vector<float16_t, 4> >(0u, quadSwapX_02834c());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapX/053f3b.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapX/053f3b.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..9aa037729d9
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapX/053f3b.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int3 quadSwapX_053f3b() {
+  int3 arg_0 = (1).xxx;
+  int3 res = QuadReadAcrossX(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapX_053f3b()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapX_053f3b()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapX/07f1fc.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapX/07f1fc.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..0f01037475b
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapX/07f1fc.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint4 quadSwapX_07f1fc() {
+  uint4 arg_0 = (1u).xxxx;
+  uint4 res = QuadReadAcrossX(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store4(0u, quadSwapX_07f1fc());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store4(0u, quadSwapX_07f1fc());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapX/150d6f.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapX/150d6f.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..da39059c688
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapX/150d6f.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float3 quadSwapX_150d6f() {
+  float3 arg_0 = (1.0f).xxx;
+  float3 res = QuadReadAcrossX(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapX_150d6f()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapX_150d6f()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapX/19f8ce.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapX/19f8ce.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..b873484931b
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapX/19f8ce.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint2 quadSwapX_19f8ce() {
+  uint2 arg_0 = (1u).xx;
+  uint2 res = QuadReadAcrossX(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store2(0u, quadSwapX_19f8ce());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store2(0u, quadSwapX_19f8ce());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapX/1e1086.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapX/1e1086.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..31e19e4393f
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapX/1e1086.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int quadSwapX_1e1086() {
+  int arg_0 = 1;
+  int res = QuadReadAcrossX(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store(0u, asuint(quadSwapX_1e1086()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store(0u, asuint(quadSwapX_1e1086()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapX/69af6a.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapX/69af6a.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..e67c60d1dde
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapX/69af6a.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float4 quadSwapX_69af6a() {
+  float4 arg_0 = (1.0f).xxxx;
+  float4 res = QuadReadAcrossX(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapX_69af6a()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapX_69af6a()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapX/8203ad.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapX/8203ad.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..cfd73a5edbe
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapX/8203ad.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint quadSwapX_8203ad() {
+  uint arg_0 = 1u;
+  uint res = QuadReadAcrossX(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store(0u, quadSwapX_8203ad());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store(0u, quadSwapX_8203ad());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapX/879738.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapX/879738.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..69f029534df
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapX/879738.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float2 quadSwapX_879738() {
+  float2 arg_0 = (1.0f).xx;
+  float2 res = QuadReadAcrossX(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapX_879738()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapX_879738()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapX/9bea80.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapX/9bea80.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..d7d637a3411
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapX/9bea80.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float quadSwapX_9bea80() {
+  float arg_0 = 1.0f;
+  float res = QuadReadAcrossX(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store(0u, asuint(quadSwapX_9bea80()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store(0u, asuint(quadSwapX_9bea80()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapX/a4e103.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapX/a4e103.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..5ef0fa9ff6b
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapX/a4e103.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float16_t quadSwapX_a4e103() {
+  float16_t arg_0 = float16_t(1.0h);
+  float16_t res = QuadReadAcrossX(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<float16_t>(0u, quadSwapX_a4e103());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<float16_t>(0u, quadSwapX_a4e103());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapX/b1a5fe.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapX/b1a5fe.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..55c7cd3530f
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapX/b1a5fe.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int2 quadSwapX_b1a5fe() {
+  int2 arg_0 = (1).xx;
+  int2 res = QuadReadAcrossX(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapX_b1a5fe()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapX_b1a5fe()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapX/bc2013.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapX/bc2013.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..5b9dd6d8b8f
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapX/bc2013.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+vector<float16_t, 3> quadSwapX_bc2013() {
+  vector<float16_t, 3> arg_0 = (float16_t(1.0h)).xxx;
+  vector<float16_t, 3> res = QuadReadAcrossX(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<vector<float16_t, 3> >(0u, quadSwapX_bc2013());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<vector<float16_t, 3> >(0u, quadSwapX_bc2013());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapX/bddb9f.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapX/bddb9f.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..b3cf4152d24
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapX/bddb9f.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint3 quadSwapX_bddb9f() {
+  uint3 arg_0 = (1u).xxx;
+  uint3 res = QuadReadAcrossX(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store3(0u, quadSwapX_bddb9f());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store3(0u, quadSwapX_bddb9f());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapX/d60cec.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapX/d60cec.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..e20451c88fd
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapX/d60cec.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+vector<float16_t, 2> quadSwapX_d60cec() {
+  vector<float16_t, 2> arg_0 = (float16_t(1.0h)).xx;
+  vector<float16_t, 2> res = QuadReadAcrossX(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<vector<float16_t, 2> >(0u, quadSwapX_d60cec());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<vector<float16_t, 2> >(0u, quadSwapX_d60cec());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapX/edfa1f.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapX/edfa1f.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..5f6222dda2c
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapX/edfa1f.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int4 quadSwapX_edfa1f() {
+  int4 arg_0 = (1).xxxx;
+  int4 res = QuadReadAcrossX(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapX_edfa1f()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapX_edfa1f()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapY/06a67c.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapY/06a67c.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..545aeee1147
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapY/06a67c.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint3 quadSwapY_06a67c() {
+  uint3 arg_0 = (1u).xxx;
+  uint3 res = QuadReadAcrossY(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store3(0u, quadSwapY_06a67c());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store3(0u, quadSwapY_06a67c());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapY/0c4938.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapY/0c4938.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..dbf0137d7d6
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapY/0c4938.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint quadSwapY_0c4938() {
+  uint arg_0 = 1u;
+  uint res = QuadReadAcrossY(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store(0u, quadSwapY_0c4938());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store(0u, quadSwapY_0c4938());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapY/0d05a8.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapY/0d05a8.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..9f524ad7fb6
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapY/0d05a8.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int2 quadSwapY_0d05a8() {
+  int2 arg_0 = (1).xx;
+  int2 res = QuadReadAcrossY(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapY_0d05a8()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapY_0d05a8()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapY/14bb9a.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapY/14bb9a.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..83642e43b1c
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapY/14bb9a.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int4 quadSwapY_14bb9a() {
+  int4 arg_0 = (1).xxxx;
+  int4 res = QuadReadAcrossY(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapY_14bb9a()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapY_14bb9a()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapY/1f1a06.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapY/1f1a06.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..09d4ebfc1bc
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapY/1f1a06.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float2 quadSwapY_1f1a06() {
+  float2 arg_0 = (1.0f).xx;
+  float2 res = QuadReadAcrossY(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapY_1f1a06()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store2(0u, asuint(quadSwapY_1f1a06()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapY/264908.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapY/264908.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..9d044160296
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapY/264908.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+vector<float16_t, 3> quadSwapY_264908() {
+  vector<float16_t, 3> arg_0 = (float16_t(1.0h)).xxx;
+  vector<float16_t, 3> res = QuadReadAcrossY(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<vector<float16_t, 3> >(0u, quadSwapY_264908());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<vector<float16_t, 3> >(0u, quadSwapY_264908());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapY/5b2e67.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapY/5b2e67.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..e174f4b6c14
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapY/5b2e67.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+vector<float16_t, 4> quadSwapY_5b2e67() {
+  vector<float16_t, 4> arg_0 = (float16_t(1.0h)).xxxx;
+  vector<float16_t, 4> res = QuadReadAcrossY(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<vector<float16_t, 4> >(0u, quadSwapY_5b2e67());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<vector<float16_t, 4> >(0u, quadSwapY_5b2e67());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapY/6f6bc9.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapY/6f6bc9.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..15c386712ed
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapY/6f6bc9.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float quadSwapY_6f6bc9() {
+  float arg_0 = 1.0f;
+  float res = QuadReadAcrossY(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store(0u, asuint(quadSwapY_6f6bc9()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store(0u, asuint(quadSwapY_6f6bc9()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapY/9277e9.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapY/9277e9.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..679fbd33205
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapY/9277e9.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float16_t quadSwapY_9277e9() {
+  float16_t arg_0 = float16_t(1.0h);
+  float16_t res = QuadReadAcrossY(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<float16_t>(0u, quadSwapY_9277e9());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<float16_t>(0u, quadSwapY_9277e9());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapY/94ab6d.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapY/94ab6d.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..3d14e93c5d2
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapY/94ab6d.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int quadSwapY_94ab6d() {
+  int arg_0 = 1;
+  int res = QuadReadAcrossY(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store(0u, asuint(quadSwapY_94ab6d()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store(0u, asuint(quadSwapY_94ab6d()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapY/a27e1c.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapY/a27e1c.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..abbe520abcf
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapY/a27e1c.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint2 quadSwapY_a27e1c() {
+  uint2 arg_0 = (1u).xx;
+  uint2 res = QuadReadAcrossY(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store2(0u, quadSwapY_a27e1c());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store2(0u, quadSwapY_a27e1c());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapY/a50fcb.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapY/a50fcb.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..b2fab464264
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapY/a50fcb.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+vector<float16_t, 2> quadSwapY_a50fcb() {
+  vector<float16_t, 2> arg_0 = (float16_t(1.0h)).xx;
+  vector<float16_t, 2> res = QuadReadAcrossY(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store<vector<float16_t, 2> >(0u, quadSwapY_a50fcb());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store<vector<float16_t, 2> >(0u, quadSwapY_a50fcb());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapY/b9d9e7.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapY/b9d9e7.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..8fb08483eac
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapY/b9d9e7.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float4 quadSwapY_b9d9e7() {
+  float4 arg_0 = (1.0f).xxxx;
+  float4 res = QuadReadAcrossY(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapY_b9d9e7()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store4(0u, asuint(quadSwapY_b9d9e7()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapY/bb697b.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapY/bb697b.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..1fc0c9a8d45
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapY/bb697b.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+uint4 quadSwapY_bb697b() {
+  uint4 arg_0 = (1u).xxxx;
+  uint4 res = QuadReadAcrossY(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store4(0u, quadSwapY_bb697b());
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store4(0u, quadSwapY_bb697b());
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapY/be4e72.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapY/be4e72.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..37e4a9f2035
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapY/be4e72.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+int3 quadSwapY_be4e72() {
+  int3 arg_0 = (1).xxx;
+  int3 res = QuadReadAcrossY(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapY_be4e72()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapY_be4e72()));
+}
+
diff --git a/test/tint/builtins/gen/var/quadSwapY/d1ab4d.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/var/quadSwapY/d1ab4d.wgsl.expected.ir.dxc.hlsl
new file mode 100644
index 00000000000..19fed752d52
--- /dev/null
+++ b/test/tint/builtins/gen/var/quadSwapY/d1ab4d.wgsl.expected.ir.dxc.hlsl
@@ -0,0 +1,17 @@
+
+RWByteAddressBuffer prevent_dce : register(u0);
+float3 quadSwapY_d1ab4d() {
+  float3 arg_0 = (1.0f).xxx;
+  float3 res = QuadReadAcrossY(arg_0);
+  return res;
+}
+
+void fragment_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapY_d1ab4d()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+  prevent_dce.Store3(0u, asuint(quadSwapY_d1ab4d()));
+}
+