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ssem_map.mrp
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Release 14.1 Map P.15xf (nt64)
Xilinx Mapping Report File for Design 'ssem'
Design Information
------------------
Command Line : map -intstyle ise -p xc3s1200e-fg320-5 -cm area -ir off -pr off
-c 100 -o ssem_map.ncd ssem.ngd ssem.pcf
Target Device : xc3s1200e
Target Package : fg320
Target Speed : -5
Mapper Version : spartan3e -- $Revision: 1.55 $
Mapped Date : Sun Jul 19 23:01:56 2015
Design Summary
--------------
Number of errors: 0
Number of warnings: 16
Logic Utilization:
Number of Slice Flip Flops: 547 out of 17,344 3%
Number of 4 input LUTs: 923 out of 17,344 5%
Logic Distribution:
Number of occupied Slices: 617 out of 8,672 7%
Number of Slices containing only related logic: 617 out of 617 100%
Number of Slices containing unrelated logic: 0 out of 617 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 970 out of 17,344 5%
Number used as logic: 921
Number used as a route-thru: 47
Number used as Shift registers: 2
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
Number of bonded IOBs: 55 out of 250 22%
Number of RAMB16s: 2 out of 28 7%
Number of BUFGMUXs: 5 out of 24 20%
Average Fanout of Non-Clock Nets: 3.27
Peak Memory Usage: 263 MB
Total REAL time to MAP completion: 7 secs
Total CPU time to MAP completion: 3 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
WARNING:PhysDesignRules:812 - Dangling pin <DOB4> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB5> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB6> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB7> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB12> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB13> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB14> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB15> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB20> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB21> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB22> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB23> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB28> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB29> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB30> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB31> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
Section 3 - Informational
-------------------------
INFO:Security:54 - 'xc3s1200e' is a WebPack part.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
Section 4 - Removed Logic Summary
---------------------------------
11 block(s) optimized away
Section 5 - Removed Logic
-------------------------
Optimized Block(s):
TYPE BLOCK
GND
ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND
VCC
ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/XST_VCC
GND ROM/XST_GND
VCC ROM/XST_VCC
GND XST_GND
VCC XST_VCC
GND
store/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GN
D
GND store/XST_GND
VCC store/XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| KAC | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
| KC | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
| KCC | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
| KSC | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
| Load_button | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
| MCP_S_CLK | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| MCP_S_CS | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| MCP_S_SI | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| MCP_S_SO | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
| MCP_T_CLK | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| MCP_T_CS | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| MCP_T_SI | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| MCP_T_SO | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
| PC_BUSY | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| PC_Data | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
| PC_Write | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
| blue_out | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| clk50_in | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
| disp_sw<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
| disp_sw<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
| disp_sw<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
| green_out<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| green_out<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| green_out<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| halt_led | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| hooter | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| hs_out | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| led_anodes<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| led_anodes<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| led_anodes<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| led_anodes<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| led_segs<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| led_segs<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| led_segs<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| led_segs<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| led_segs<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| led_segs<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| led_segs<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| led_segs<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| leds<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| leds<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| leds<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| leds<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| leds<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| leds<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| leds<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| leds<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| pc_dash | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| pc_sync | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| red_out | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| store_read | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| sw0 | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
| sw6 | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
| sw7 | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
| vs_out | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
This design was not run using timing mode.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
No control set information for this architecture.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.