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ssem_map.map
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Release 14.1 Map P.15xf (nt64)
Xilinx Map Application Log File for Design 'ssem'
Design Information
------------------
Command Line : map -intstyle ise -p xc3s1200e-fg320-5 -cm area -ir off -pr off
-c 100 -o ssem_map.ncd ssem.ngd ssem.pcf
Target Device : xc3s1200e
Target Package : fg320
Target Speed : -5
Mapper Version : spartan3e -- $Revision: 1.55 $
Mapped Date : Sun Jul 19 23:01:56 2015
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc3s1200e' is a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...
WARNING:PhysDesignRules:812 - Dangling pin <DOB4> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB5> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB6> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB7> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB12> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB13> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB14> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB15> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB20> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB21> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB22> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB23> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB28> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB29> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB30> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB31> on
block:<ROM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/
ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 16
Logic Utilization:
Number of Slice Flip Flops: 547 out of 17,344 3%
Number of 4 input LUTs: 923 out of 17,344 5%
Logic Distribution:
Number of occupied Slices: 617 out of 8,672 7%
Number of Slices containing only related logic: 617 out of 617 100%
Number of Slices containing unrelated logic: 0 out of 617 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 970 out of 17,344 5%
Number used as logic: 921
Number used as a route-thru: 47
Number used as Shift registers: 2
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
Number of bonded IOBs: 55 out of 250 22%
Number of RAMB16s: 2 out of 28 7%
Number of BUFGMUXs: 5 out of 24 20%
Average Fanout of Non-Clock Nets: 3.27
Peak Memory Usage: 263 MB
Total REAL time to MAP completion: 7 secs
Total CPU time to MAP completion: 3 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Mapping completed.
See MAP report file "ssem_map.mrp" for details.