From 4ca6dd90bb8bb167d351461567a7bb790d636b3a Mon Sep 17 00:00:00 2001 From: Kentaro Kawakami Date: Mon, 11 Sep 2023 07:11:53 +0900 Subject: [PATCH] Add output of sample/cpuinfo --- sample/cpuinfo.FX700.a64fx.centOS.8_3.txt | 18 +++++++++++++++++ ...nfo.JetsonNano.Cortex-A57.ubuntu.18_04.txt | 18 +++++++++++++++++ sample/cpuinfo.Mac_mini.M1.macOS.13_5_2.txt | 18 +++++++++++++++++ ...Kit2023.Snapdragon_8cx_Gen3.windows.11.txt | 20 +++++++++++++++++++ ...info.c7g_medium.Graviton3.ubuntu.22_04.txt | 20 +++++++++++++++++++ 5 files changed, 94 insertions(+) create mode 100644 sample/cpuinfo.FX700.a64fx.centOS.8_3.txt create mode 100644 sample/cpuinfo.JetsonNano.Cortex-A57.ubuntu.18_04.txt create mode 100644 sample/cpuinfo.Mac_mini.M1.macOS.13_5_2.txt create mode 100644 sample/cpuinfo.WindowsDevKit2023.Snapdragon_8cx_Gen3.windows.11.txt create mode 100644 sample/cpuinfo.c7g_medium.Graviton3.ubuntu.22_04.txt diff --git a/sample/cpuinfo.FX700.a64fx.centOS.8_3.txt b/sample/cpuinfo.FX700.a64fx.centOS.8_3.txt new file mode 100644 index 0000000..a97e6ef --- /dev/null +++ b/sample/cpuinfo.FX700.a64fx.centOS.8_3.txt @@ -0,0 +1,18 @@ +Implementer: Fujitsu Ltd. +CPU type: 000000000000001e +HW_CAP: advsimd fp sve(64) atomic +# of CPU cores: 48 +Data cache level: 2 +L1D cache size: 65536 +L2 cache size: 8388608 +L1D cache sharing cores: 1 +L2 cache sharing cores: 12 + +numCores=48 +L1, 3, 65536, 65536, 0, 1, 1, 0 +L2, 4, 0, 0, 8388608, 0, 0, 12 +L3, 0, 0, 0, 0, 0, 0, 0 +L4, 0, 0, 0, 0, 0, 0, 0 +L5, 0, 0, 0, 0, 0, 0, 0 +L6, 0, 0, 0, 0, 0, 0, 0 +L7, 0, 0, 0, 0, 0, 0, 0 diff --git a/sample/cpuinfo.JetsonNano.Cortex-A57.ubuntu.18_04.txt b/sample/cpuinfo.JetsonNano.Cortex-A57.ubuntu.18_04.txt new file mode 100644 index 0000000..93bbee6 --- /dev/null +++ b/sample/cpuinfo.JetsonNano.Cortex-A57.ubuntu.18_04.txt @@ -0,0 +1,18 @@ +Implementer: Arm Limited +CPU type: 0000000000000006 +HW_CAP: advsimd fp +# of CPU cores: 4 +Data cache level: 2 +L1D cache size: 32768 +L2 cache size: 2097152 +L1D cache sharing cores: 1 +L2 cache sharing cores: 4 + +numCores=4 +L1, 3, 49152, 32768, 0, 1, 1, 0 +L2, 4, 0, 0, 2097152, 0, 0, 4 +L3, 0, 0, 0, 0, 0, 0, 0 +L4, 0, 0, 0, 0, 0, 0, 0 +L5, 0, 0, 0, 0, 0, 0, 0 +L6, 0, 0, 0, 0, 0, 0, 0 +L7, 0, 0, 0, 0, 0, 0, 0 \ No newline at end of file diff --git a/sample/cpuinfo.Mac_mini.M1.macOS.13_5_2.txt b/sample/cpuinfo.Mac_mini.M1.macOS.13_5_2.txt new file mode 100644 index 0000000..cd0e875 --- /dev/null +++ b/sample/cpuinfo.Mac_mini.M1.macOS.13_5_2.txt @@ -0,0 +1,18 @@ +Implementer: Apple Inc. +CPU type: 0000000000000016 +HW_CAP: advsimd fp atomic +# of CPU cores: 8 +Data cache level: 2 +L1D cache size: 65536 +L2 cache size: 4194304 +L1D cache sharing cores: 1 +L2 cache sharing cores: 4 + +numCores=8 +L1, 3, 131072, 65536, 0, 1, 1, 0 +L2, 4, 0, 0, 4194304, 0, 0, 4 +L3, 4, 0, 0, 0, 0, 0, 0 +L4, 0, 0, 0, 0, 0, 0, 0 +L5, 0, 0, 0, 0, 0, 0, 0 +L6, 0, 0, 0, 0, 0, 0, 0 +L7, 0, 0, 0, 0, 0, 0, 0 \ No newline at end of file diff --git a/sample/cpuinfo.WindowsDevKit2023.Snapdragon_8cx_Gen3.windows.11.txt b/sample/cpuinfo.WindowsDevKit2023.Snapdragon_8cx_Gen3.windows.11.txt new file mode 100644 index 0000000..4f08d51 --- /dev/null +++ b/sample/cpuinfo.WindowsDevKit2023.Snapdragon_8cx_Gen3.windows.11.txt @@ -0,0 +1,20 @@ +Implementer: Reserved for software use +CPU type: 0000000000000012 +HW_CAP: advsimd atomic +# of CPU cores: 8 +Data cache level: 3 +L1D cache size: 65536 +L2 cache size: 1048576 +L3 cache size: 8388608 +L1D cache sharing cores: 1 +L2 cache sharing cores: 1 +L3 cache sharing cores: 8 + +numCores=8 +L1, 3, 65536, 65536, 0, 1, 1, 0 +L2, 4, 0, 0, 1048576, 0, 0, 1 +L3, 4, 0, 0, 8388608, 0, 0, 8 +L4, 0, 0, 0, 0, 0, 0, 0 +L5, 0, 0, 0, 0, 0, 0, 0 +L6, 0, 0, 0, 0, 0, 0, 0 +L7, 0, 0, 0, 0, 0, 0, 0 diff --git a/sample/cpuinfo.c7g_medium.Graviton3.ubuntu.22_04.txt b/sample/cpuinfo.c7g_medium.Graviton3.ubuntu.22_04.txt new file mode 100644 index 0000000..3c24a4d --- /dev/null +++ b/sample/cpuinfo.c7g_medium.Graviton3.ubuntu.22_04.txt @@ -0,0 +1,20 @@ +Implementer: Arm Limited +CPU type: 000000000000003e +HW_CAP: advsimd fp sve(32) atomic bf16 +# of CPU cores: 1 +Data cache level: 3 +L1D cache size: 65536 +L2 cache size: 1048576 +L3 cache size: 33554432 +L1D cache sharing cores: 1 +L2 cache sharing cores: 1 +L3 cache sharing cores: 1 + +numCores=1 +L1, 3, 65536, 65536, 0, 1, 1, 0 +L2, 4, 0, 0, 1048576, 0, 0, 1 +L3, 4, 0, 0, 33554432, 0, 0, 1 +L4, 0, 0, 0, 0, 0, 0, 0 +L5, 0, 0, 0, 0, 0, 0, 0 +L6, 0, 0, 0, 0, 0, 0, 0 +L7, 0, 0, 0, 0, 0, 0, 0