Help in understanding the vhdl code

[gioregg]

Hi,

With hls4ml I have generated the ip block for vivado, using the function: hls_model.build(csim=True,synth=True,cosim=True,export=True) . When I import the the ip in vivado and generate the output products, the generated entity in vhdl has some parameters I can not understand their meaning. The data_in has dimension 480, probably because I use a cnn model (for binary classification) with 30 inputs with precision fixed on 16 bits. But I can not understand the meaning of the outputs and why some of them are on 16 bits.
I am using as a backend 'Vivado' and I would like to generate the bitstream for ZCU102 and KCU105 boards.

I have got also doubts on how to write a test bench for checking the correct working of the block.

The entity of the generated vhdl file is this one:

entity design_1 is
port (
ap_done : out STD_LOGIC;
ap_idle : out STD_LOGIC;
ap_ready : out STD_LOGIC;
ap_start : in STD_LOGIC;
clk_in1 : in STD_LOGIC;
const_size_in_1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
const_size_in_1_ap_vld : out STD_LOGIC;
const_size_out_1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
const_size_out_1_ap_vld : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR ( 479 downto 0 );
layer7_out_0_V : out STD_LOGIC_VECTOR ( 15 downto 0 );
layer7_out_0_V_ap_vld : out STD_LOGIC;
reset : in STD_LOGIC;
valid : in STD_LOGIC
);

Does someone have got some resources regarding this things?

Thank you,

Gio

[jmitrevs]

What is the top-level HLS function? There is a simple C++ test-bench that is also produced by hls4ml with a default name of myproject_test.cpp, myproject renamed to the project name if you give it a name.

[gioregg]

Hi,

This is my_project.cpp with the top level function.

include <gmp.h>
#define __gmp_const const

#include

#include "myproject.h"
#include "parameters.h"

void myproject(
input_t fc1_input[N_INPUT_1_1],
result_t layer7_out[N_LAYER_5],
unsigned short &const_size_in_1,
unsigned short &const_size_out_1
) {

//hls-fpga-machine-learning insert IO
#pragma HLS ARRAY_RESHAPE variable=fc1_input complete dim=0
#pragma HLS ARRAY_PARTITION variable=layer7_out complete dim=0
#pragma HLS INTERFACE ap_vld port=fc1_input,layer7_out 
#pragma HLS PIPELINE 

const_size_in_1 = N_INPUT_1_1;
const_size_out_1 = N_LAYER_5;

#ifndef SYNTHESIS
static bool loaded_weights = false;
if (!loaded_weights) {
//hls-fpga-machine-learning insert load weights
nnet::load_weights_from_txt<model_default_t, 600>(w2, "w2.txt");
nnet::load_weights_from_txt<model_default_t, 20>(b2, "b2.txt");
nnet::load_weights_from_txt<model_default_t, 20>(w5, "w5.txt");
nnet::load_weights_from_txt<model_default_t, 1>(b5, "b5.txt");
loaded_weights = true;
}
#endif

// ****************************************
// NETWORK INSTANTIATION
// ****************************************

//hls-fpga-machine-learning insert layers

layer2_t layer2_out[N_LAYER_2];
#pragma HLS ARRAY_PARTITION variable=layer2_out complete dim=0
nnet::dense<input_t, layer2_t, config2>(fc1_input, layer2_out, w2, b2); // fc1

layer4_t layer4_out[N_LAYER_2];
#pragma HLS ARRAY_PARTITION variable=layer4_out complete dim=0
nnet::sigmoid<layer2_t, layer4_t, sigmoid_config4>(layer2_out, layer4_out); // sigmoid1

layer5_t layer5_out[N_LAYER_5];
#pragma HLS ARRAY_PARTITION variable=layer5_out complete dim=0
nnet::dense<layer4_t, layer5_t, config5>(layer4_out, layer5_out, w5, b5); // output

nnet::sigmoid<layer5_t, result_t, sigmoid_config7>(layer5_out, layer7_out); // sigmoid2

}

Is there a way to test the ip blok generated also on vivado?

Thank you

[bo3z]

There are 2 parts to this question - the bit-width of inputs and outputs and the additional control signals.

Regarding the bit width - Vivado HLS will concatenate multiple signals (inputs or outputs) into one wide bus. In your case, there are 30 inputs (this is the signal data_in), each of which is 16 bits, hence a 480-bit bus. There is only one output (layer_7_out), so it's a 16-bit bus. Importantly, if you don't specify the precision, hls4ml will default to ap_fixed<16, 6> (16 bits in total for each variable, 6 of which are for the integer part of a fixed point number). You can specify the per-layer precision (and many other attributes of a layer), see the tutorial: https://github.com/fastmachinelearning/hls4ml-tutorial/blob/main/part2_advanced_config.ipynb.

Now there are 2 additional signals in your case const_size_in_1 and const_size_out_1 which I am not sure where these come from. My guess is that they are tied to your model, since they are also there in the .cpp file, so they are not a by-product of HLS synthesis (i.e. they are inserted by hls4ml from Python). Since they have a type of short in C++, which is 2 bytes / 16 bits in standard C++, Vivado HLS correctly inferred the 16 bits for this.

Lastly, there are all the additional signals *_done, *_valid, clock, reset etc. These are generated by Vivado HLS so that you could connect your IP with the rest of your design. These are standard digital circuit hand-shake signals which are used to indicate when the block is ready to accept new inputs, when the output is ready, the clock to it, reset signal etc. There are many interfaces that can be set, see here (this is from Vitis HLS, the newer version but these remain largely unchanged from version to version): https://docs.amd.com/r/en-US/ug1399-vitis-hls/pragma-HLS-interface. It seems that you're using hls4ml with io_parallel (depending on the size of your CNN I might also recommend using io_stream, which propagates data in a streaming fashion between layers and uses less resources, scaling better to large resources, see tutorial: https://github.com/fastmachinelearning/hls4ml-tutorial/blob/main/part6_cnns.ipynb). In io_parallel, the interface used is ap_vld, which is described here: https://docs.amd.com/r/en-US/ug1399-vitis-hls/Port-Level-Protocols-for-Vivado-IP-Flow. There are some examples of waves and how the circuit / block behaves over time and when the signals go high.

[gioregg]

Hi @bo3z ,

Thank you for helping me out.
By reading all the files generated by hls4ml and the output from the test bench in Vivado , I understood that const_size_in_1 and const_size_out_2 represent the dimensions of the input and output of my model.

Thank you again,

Gio