From 121f7c35866e318fe259b662b9f1dddbfc39b102 Mon Sep 17 00:00:00 2001 From: arm Date: Wed, 12 Jun 2024 17:59:57 +0330 Subject: [PATCH 1/6] feat(board): Adding ViraLink IoT Gate Boards --- boards.txt | 196 ++++++++++++++++++++++++++ variants/ViraLink-G0.1/pins_arduino.h | 42 ++++++ variants/ViraLink-G1.1/pins_arduino.h | 46 ++++++ 3 files changed, 284 insertions(+) create mode 100644 variants/ViraLink-G0.1/pins_arduino.h create mode 100644 variants/ViraLink-G1.1/pins_arduino.h diff --git a/boards.txt b/boards.txt index 5163a2d84c9..89190816fb3 100644 --- a/boards.txt +++ b/boards.txt @@ -8699,6 +8699,202 @@ lolin32.menu.EraseFlash.all.upload.erase_cmd=-e ############################################################## +viralink32g01.name=ViraLink Gate32-0.1 + +viralink32g01.bootloader.tool=esptool_py +viralink32g01.bootloader.tool.default=esptool_py + +viralink32g01.upload.tool=esptool_py +viralink32g01.upload.tool.default=esptool_py +viralink32g01.upload.tool.network=esp_ota + +viralink32g01.upload.maximum_size=1310720 +viralink32g01.upload.maximum_data_size=327680 +viralink32g01.upload.flags= +viralink32g01.upload.extra_flags= + +viralink32g01.serial.disableDTR=true +viralink32g01.serial.disableRTS=true + +viralink32g01.build.tarch=xtensa +viralink32g01.build.bootloader_addr=0x1000 +viralink32g01.build.target=esp32 +viralink32g01.build.mcu=esp32 +viralink32g01.build.core=esp32 +viralink32g01.build.variant=ViraLink-G0.1 +viralink32g01.build.board=ViraLink-Gate32-0.1 + +viralink32g01.build.f_cpu=240000000L +viralink32g01.build.flash_mode=dio +viralink32g01.build.flash_size=4MB +viralink32g01.build.boot=dio +viralink32g01.build.partitions=default +viralink32g01.build.defines= + +viralink32g01.menu.FlashFreq.80=80MHz +viralink32g01.menu.FlashFreq.80.build.flash_freq=80m +viralink32g01.menu.FlashFreq.40=40MHz +viralink32g01.menu.FlashFreq.40.build.flash_freq=40m + +viralink32g01.menu.PartitionScheme.default=Default +viralink32g01.menu.PartitionScheme.default.build.partitions=default +viralink32g01.menu.PartitionScheme.no_ota=No OTA (Large APP) +viralink32g01.menu.PartitionScheme.no_ota.build.partitions=no_ota +viralink32g01.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +viralink32g01.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +viralink32g01.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +viralink32g01.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +viralink32g01.menu.CPUFreq.240=240MHz (WiFi/BT) +viralink32g01.menu.CPUFreq.240.build.f_cpu=240000000L +viralink32g01.menu.CPUFreq.160=160MHz (WiFi/BT) +viralink32g01.menu.CPUFreq.160.build.f_cpu=160000000L +viralink32g01.menu.CPUFreq.80=80MHz (WiFi/BT) +viralink32g01.menu.CPUFreq.80.build.f_cpu=80000000L +viralink32g01.menu.CPUFreq.40=40MHz (40MHz XTAL) +viralink32g01.menu.CPUFreq.40.build.f_cpu=40000000L +viralink32g01.menu.CPUFreq.26=26MHz (26MHz XTAL) +viralink32g01.menu.CPUFreq.26.build.f_cpu=26000000L +viralink32g01.menu.CPUFreq.20=20MHz (40MHz XTAL) +viralink32g01.menu.CPUFreq.20.build.f_cpu=20000000L +viralink32g01.menu.CPUFreq.13=13MHz (26MHz XTAL) +viralink32g01.menu.CPUFreq.13.build.f_cpu=13000000L +viralink32g01.menu.CPUFreq.10=10MHz (40MHz XTAL) +viralink32g01.menu.CPUFreq.10.build.f_cpu=10000000L + +viralink32g01.menu.UploadSpeed.921600=921600 +viralink32g01.menu.UploadSpeed.921600.upload.speed=921600 +viralink32g01.menu.UploadSpeed.115200=115200 +viralink32g01.menu.UploadSpeed.115200.upload.speed=115200 +viralink32g01.menu.UploadSpeed.256000.windows=256000 +viralink32g01.menu.UploadSpeed.256000.upload.speed=256000 +viralink32g01.menu.UploadSpeed.230400.windows.upload.speed=256000 +viralink32g01.menu.UploadSpeed.230400=230400 +viralink32g01.menu.UploadSpeed.230400.upload.speed=230400 +viralink32g01.menu.UploadSpeed.460800.linux=460800 +viralink32g01.menu.UploadSpeed.460800.macosx=460800 +viralink32g01.menu.UploadSpeed.460800.upload.speed=460800 +viralink32g01.menu.UploadSpeed.512000.windows=512000 +viralink32g01.menu.UploadSpeed.512000.upload.speed=512000 + +viralink32g01.menu.DebugLevel.none=None +viralink32g01.menu.DebugLevel.none.build.code_debug=0 +viralink32g01.menu.DebugLevel.error=Error +viralink32g01.menu.DebugLevel.error.build.code_debug=1 +viralink32g01.menu.DebugLevel.warn=Warn +viralink32g01.menu.DebugLevel.warn.build.code_debug=2 +viralink32g01.menu.DebugLevel.info=Info +viralink32g01.menu.DebugLevel.info.build.code_debug=3 +viralink32g01.menu.DebugLevel.debug=Debug +viralink32g01.menu.DebugLevel.debug.build.code_debug=4 +viralink32g01.menu.DebugLevel.verbose=Verbose +viralink32g01.menu.DebugLevel.verbose.build.code_debug=5 + +viralink32g01.menu.EraseFlash.none=Disabled +viralink32g01.menu.EraseFlash.none.upload.erase_cmd= +viralink32g01.menu.EraseFlash.all=Enabled +viralink32g01.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +viralink32g11.name=ViraLink Gate32-1.1 + +viralink32g11.bootloader.tool=esptool_py +viralink32g11.bootloader.tool.default=esptool_py + +viralink32g11.upload.tool=esptool_py +viralink32g11.upload.tool.default=esptool_py +viralink32g11.upload.tool.network=esp_ota + +viralink32g11.upload.maximum_size=1310720 +viralink32g11.upload.maximum_data_size=327680 +viralink32g11.upload.flags= +viralink32g11.upload.extra_flags= + +viralink32g11.serial.disableDTR=true +viralink32g11.serial.disableRTS=true + +viralink32g11.build.tarch=xtensa +viralink32g11.build.bootloader_addr=0x1000 +viralink32g11.build.target=esp32 +viralink32g11.build.mcu=esp32 +viralink32g11.build.core=esp32 +viralink32g11.build.variant=ViraLink-G1.1 +viralink32g11.build.board=ViraLink-Gate32-1.1 + +viralink32g11.build.f_cpu=240000000L +viralink32g11.build.flash_mode=dio +viralink32g11.build.flash_size=4MB +viralink32g11.build.boot=dio +viralink32g11.build.partitions=default +viralink32g11.build.defines= + +viralink32g11.menu.FlashFreq.80=80MHz +viralink32g11.menu.FlashFreq.80.build.flash_freq=80m +viralink32g11.menu.FlashFreq.40=40MHz +viralink32g11.menu.FlashFreq.40.build.flash_freq=40m + +viralink32g11.menu.PartitionScheme.default=Default +viralink32g11.menu.PartitionScheme.default.build.partitions=default +viralink32g11.menu.PartitionScheme.no_ota=No OTA (Large APP) +viralink32g11.menu.PartitionScheme.no_ota.build.partitions=no_ota +viralink32g11.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +viralink32g11.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +viralink32g11.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +viralink32g11.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +viralink32g11.menu.CPUFreq.240=240MHz (WiFi/BT) +viralink32g11.menu.CPUFreq.240.build.f_cpu=240000000L +viralink32g11.menu.CPUFreq.160=160MHz (WiFi/BT) +viralink32g11.menu.CPUFreq.160.build.f_cpu=160000000L +viralink32g11.menu.CPUFreq.80=80MHz (WiFi/BT) +viralink32g11.menu.CPUFreq.80.build.f_cpu=80000000L +viralink32g11.menu.CPUFreq.40=40MHz (40MHz XTAL) +viralink32g11.menu.CPUFreq.40.build.f_cpu=40000000L +viralink32g11.menu.CPUFreq.26=26MHz (26MHz XTAL) +viralink32g11.menu.CPUFreq.26.build.f_cpu=26000000L +viralink32g11.menu.CPUFreq.20=20MHz (40MHz XTAL) +viralink32g11.menu.CPUFreq.20.build.f_cpu=20000000L +viralink32g11.menu.CPUFreq.13=13MHz (26MHz XTAL) +viralink32g11.menu.CPUFreq.13.build.f_cpu=13000000L +viralink32g11.menu.CPUFreq.10=10MHz (40MHz XTAL) +viralink32g11.menu.CPUFreq.10.build.f_cpu=10000000L + +viralink32g11.menu.UploadSpeed.921600=921600 +viralink32g11.menu.UploadSpeed.921600.upload.speed=921600 +viralink32g11.menu.UploadSpeed.115200=115200 +viralink32g11.menu.UploadSpeed.115200.upload.speed=115200 +viralink32g11.menu.UploadSpeed.256000.windows=256000 +viralink32g11.menu.UploadSpeed.256000.upload.speed=256000 +viralink32g11.menu.UploadSpeed.230400.windows.upload.speed=256000 +viralink32g11.menu.UploadSpeed.230400=230400 +viralink32g11.menu.UploadSpeed.230400.upload.speed=230400 +viralink32g11.menu.UploadSpeed.460800.linux=460800 +viralink32g11.menu.UploadSpeed.460800.macosx=460800 +viralink32g11.menu.UploadSpeed.460800.upload.speed=460800 +viralink32g11.menu.UploadSpeed.512000.windows=512000 +viralink32g11.menu.UploadSpeed.512000.upload.speed=512000 + +viralink32g11.menu.DebugLevel.none=None +viralink32g11.menu.DebugLevel.none.build.code_debug=0 +viralink32g11.menu.DebugLevel.error=Error +viralink32g11.menu.DebugLevel.error.build.code_debug=1 +viralink32g11.menu.DebugLevel.warn=Warn +viralink32g11.menu.DebugLevel.warn.build.code_debug=2 +viralink32g11.menu.DebugLevel.info=Info +viralink32g11.menu.DebugLevel.info.build.code_debug=3 +viralink32g11.menu.DebugLevel.debug=Debug +viralink32g11.menu.DebugLevel.debug.build.code_debug=4 +viralink32g11.menu.DebugLevel.verbose=Verbose +viralink32g11.menu.DebugLevel.verbose.build.code_debug=5 + +viralink32g11.menu.EraseFlash.none=Disabled +viralink32g11.menu.EraseFlash.none.upload.erase_cmd= +viralink32g11.menu.EraseFlash.all=Enabled +viralink32g11.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + lolin32-lite.name=WEMOS LOLIN32 Lite lolin32-lite.bootloader.tool=esptool_py diff --git a/variants/ViraLink-G0.1/pins_arduino.h b/variants/ViraLink-G0.1/pins_arduino.h new file mode 100644 index 00000000000..6e5df460454 --- /dev/null +++ b/variants/ViraLink-G0.1/pins_arduino.h @@ -0,0 +1,42 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 5; +#define BUILTIN_LED LED_BUILTIN +#define LED_BUILTIN LED_BUILTIN + +static const uint8_t RESET_KEY = 0; + +static const uint8_t RS485_TX = 32; +static const uint8_t RS485_RX = 35; + +static const uint8_t SDA = 4; +static const uint8_t SCL = 16; + +static const uint8_t BUZZER = 12; +static const uint8_t RELAY1_PIN = 2; +static const uint8_t RELAY2_PIN = 13; +static const uint8_t RELAY3_PIN = 14; +static const uint8_t RELAY4_PIN = 33; + +static const uint8_t Wiegand1_D0 = 15; +static const uint8_t Wiegand1_D1 = 34; + +static const uint8_t Wiegand2_D0 = 39; +static const uint8_t Wiegand2_D1 = 36; + +static const uint8_t ETH_CLK_OUT = 17; + +static const uint8_t EMAC_MDIO = 18; +static const uint8_t EMAC_TXD0 = 19; +static const uint8_t EMAC_TX_EN = 21; +static const uint8_t EMAC_TXD1 = 22; +static const uint8_t EMAC_MDC = 23; +static const uint8_t EMAC_RXD0 = 25; +static const uint8_t EMAC_RXD1 = 26; +static const uint8_t EMAC_RXD_DV = 27; + + +#endif /* Pins_Arduino_h */ diff --git a/variants/ViraLink-G1.1/pins_arduino.h b/variants/ViraLink-G1.1/pins_arduino.h new file mode 100644 index 00000000000..9ed501e1d2a --- /dev/null +++ b/variants/ViraLink-G1.1/pins_arduino.h @@ -0,0 +1,46 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t RESET_KEY = 0; + +static const uint8_t RF433 = 5; + +static const uint8_t RS485_TX = 32; +static const uint8_t RS485_RX = 35; + +static const uint8_t GSM1_TX = 15; +static const uint8_t GSM1_RX = 34; + +static const uint8_t GSM2_TX = 32; +static const uint8_t GSM2_RX = 35; + +static const uint8_t GSM_PWR = 33; + +static const uint8_t SDA = 4; +static const uint8_t SCL = 16; + +static const uint8_t EXT1 = 12; +static const uint8_t EXT2 = 13; +static const uint8_t PCF1_INT = 14; + +static const uint8_t Wiegand1_D0 = 15; +static const uint8_t Wiegand1_D1 = 34; + +static const uint8_t Wiegand2_D0 = 39; +static const uint8_t Wiegand2_D1 = 36; + +static const uint8_t ETH_CLK_OUT = 17; + +static const uint8_t EMAC_MDIO = 18; +static const uint8_t EMAC_TXD0 = 19; +static const uint8_t EMAC_TX_EN = 21; +static const uint8_t EMAC_TXD1 = 22; +static const uint8_t EMAC_MDC = 23; +static const uint8_t EMAC_RXD0 = 25; +static const uint8_t EMAC_RXD1 = 26; +static const uint8_t EMAC_RXD_DV = 27; + + +#endif /* Pins_Arduino_h */ From a7a4d7939d9568255f4ac30acf56f7bc326c0a54 Mon Sep 17 00:00:00 2001 From: arm Date: Wed, 12 Jun 2024 18:11:09 +0330 Subject: [PATCH 2/6] feat(board): Adding ViraLink IoT Gate Boards --- boards.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boards.txt b/boards.txt index 89190816fb3..9db90f74bd2 100644 --- a/boards.txt +++ b/boards.txt @@ -8722,7 +8722,7 @@ viralink32g01.build.target=esp32 viralink32g01.build.mcu=esp32 viralink32g01.build.core=esp32 viralink32g01.build.variant=ViraLink-G0.1 -viralink32g01.build.board=ViraLink-Gate32-0.1 +viralink32g01.build.board=ViraLink_Gate32_01 viralink32g01.build.f_cpu=240000000L viralink32g01.build.flash_mode=dio @@ -8820,7 +8820,7 @@ viralink32g11.build.target=esp32 viralink32g11.build.mcu=esp32 viralink32g11.build.core=esp32 viralink32g11.build.variant=ViraLink-G1.1 -viralink32g11.build.board=ViraLink-Gate32-1.1 +viralink32g11.build.board=ViraLink_Gate32_11 viralink32g11.build.f_cpu=240000000L viralink32g11.build.flash_mode=dio From 2a8713c92af4cbe40ac8bf1464b3454b03f89dd9 Mon Sep 17 00:00:00 2001 From: arm Date: Sat, 22 Jun 2024 19:02:59 +0330 Subject: [PATCH 3/6] feat(board): Adding ViraLink IoT Gate Boards --- boards.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boards.txt b/boards.txt index 9db90f74bd2..be0dc08b7e2 100644 --- a/boards.txt +++ b/boards.txt @@ -8722,7 +8722,7 @@ viralink32g01.build.target=esp32 viralink32g01.build.mcu=esp32 viralink32g01.build.core=esp32 viralink32g01.build.variant=ViraLink-G0.1 -viralink32g01.build.board=ViraLink_Gate32_01 +viralink32g01.build.board=VIRALINK_GATE32_01 viralink32g01.build.f_cpu=240000000L viralink32g01.build.flash_mode=dio @@ -8820,7 +8820,7 @@ viralink32g11.build.target=esp32 viralink32g11.build.mcu=esp32 viralink32g11.build.core=esp32 viralink32g11.build.variant=ViraLink-G1.1 -viralink32g11.build.board=ViraLink_Gate32_11 +viralink32g11.build.board=VIRALINK_GATE32_11 viralink32g11.build.f_cpu=240000000L viralink32g11.build.flash_mode=dio From 5a01e73891203072d625e2ac3d17eb16d252c54f Mon Sep 17 00:00:00 2001 From: arm Date: Tue, 25 Jun 2024 11:34:41 +0330 Subject: [PATCH 4/6] feat(board): Adding ViraLink IoT Gate Boards added spi pins --- variants/ViraLink-G0.1/pins_arduino.h | 5 +++++ variants/ViraLink-G1.1/pins_arduino.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/variants/ViraLink-G0.1/pins_arduino.h b/variants/ViraLink-G0.1/pins_arduino.h index 6e5df460454..1a1000443fb 100644 --- a/variants/ViraLink-G0.1/pins_arduino.h +++ b/variants/ViraLink-G0.1/pins_arduino.h @@ -38,5 +38,10 @@ static const uint8_t EMAC_RXD0 = 25; static const uint8_t EMAC_RXD1 = 26; static const uint8_t EMAC_RXD_DV = 27; +static const uint8_t SS = -1; +static const uint8_t MOSI = -1; +static const uint8_t SCK = -1; +static const uint8_t MISO = -1; + #endif /* Pins_Arduino_h */ diff --git a/variants/ViraLink-G1.1/pins_arduino.h b/variants/ViraLink-G1.1/pins_arduino.h index 9ed501e1d2a..4c5f647b9e7 100644 --- a/variants/ViraLink-G1.1/pins_arduino.h +++ b/variants/ViraLink-G1.1/pins_arduino.h @@ -42,5 +42,10 @@ static const uint8_t EMAC_RXD0 = 25; static const uint8_t EMAC_RXD1 = 26; static const uint8_t EMAC_RXD_DV = 27; +static const uint8_t SS = -1; +static const uint8_t MOSI = -1; +static const uint8_t SCK = -1; +static const uint8_t MISO = -1; + #endif /* Pins_Arduino_h */ From 7913fe9bc3c056b6b76840f84e431e5d863ac38f Mon Sep 17 00:00:00 2001 From: arm Date: Tue, 25 Jun 2024 11:48:10 +0330 Subject: [PATCH 5/6] feat(board): Adding ViraLink IoT Gate Boards added spi pins --- variants/ViraLink-G1.1/pins_arduino.h | 1 - 1 file changed, 1 deletion(-) diff --git a/variants/ViraLink-G1.1/pins_arduino.h b/variants/ViraLink-G1.1/pins_arduino.h index 4c5f647b9e7..e509b0d0e79 100644 --- a/variants/ViraLink-G1.1/pins_arduino.h +++ b/variants/ViraLink-G1.1/pins_arduino.h @@ -47,5 +47,4 @@ static const uint8_t MOSI = -1; static const uint8_t SCK = -1; static const uint8_t MISO = -1; - #endif /* Pins_Arduino_h */ From 1852cd009f8f79d23e08e318fe3bd0cfe82d2a9e Mon Sep 17 00:00:00 2001 From: "pre-commit-ci-lite[bot]" <117423508+pre-commit-ci-lite[bot]@users.noreply.github.com> Date: Tue, 25 Jun 2024 09:26:28 +0000 Subject: [PATCH 6/6] ci(pre-commit): Apply automatic fixes --- variants/ViraLink-G0.1/pins_arduino.h | 1 - 1 file changed, 1 deletion(-) diff --git a/variants/ViraLink-G0.1/pins_arduino.h b/variants/ViraLink-G0.1/pins_arduino.h index 1a1000443fb..7e11a91ce18 100644 --- a/variants/ViraLink-G0.1/pins_arduino.h +++ b/variants/ViraLink-G0.1/pins_arduino.h @@ -43,5 +43,4 @@ static const uint8_t MOSI = -1; static const uint8_t SCK = -1; static const uint8_t MISO = -1; - #endif /* Pins_Arduino_h */