From 25ebe440e277123e7a9235e8bd240f9988e0e50a Mon Sep 17 00:00:00 2001 From: Thomas Jentzsch <76921504+yellobyte@users.noreply.github.com> Date: Mon, 16 Dec 2024 23:36:33 +0100 Subject: [PATCH 1/2] add board yb_esp32s3_eth --- boards.txt | 219 +++++++++++++++++++++++++ variants/yb_esp32s3_eth/pins_arduino.h | 63 +++++++ 2 files changed, 282 insertions(+) create mode 100644 variants/yb_esp32s3_eth/pins_arduino.h diff --git a/boards.txt b/boards.txt index 791396da338..a740bde11d8 100644 --- a/boards.txt +++ b/boards.txt @@ -47922,3 +47922,222 @@ yb_esp32s3_amp_v3.menu.EraseFlash.all=Enabled yb_esp32s3_amp_v3.menu.EraseFlash.all.upload.erase_cmd=-e ############################################################## + +yb_esp32s3_eth.name=YelloByte YB-ESP32-S3-ETH + +yb_esp32s3_eth.bootloader.tool=esptool_py +yb_esp32s3_eth.bootloader.tool.default=esptool_py + +yb_esp32s3_eth.upload.tool=esptool_py +yb_esp32s3_eth.upload.tool.default=esptool_py +yb_esp32s3_eth.upload.tool.network=esp_ota + +yb_esp32s3_eth.upload.maximum_size=1310720 +yb_esp32s3_eth.upload.maximum_data_size=327680 +yb_esp32s3_eth.upload.flags= +yb_esp32s3_eth.upload.extra_flags= +yb_esp32s3_eth.upload.use_1200bps_touch=false +yb_esp32s3_eth.upload.wait_for_upload_port=false + +yb_esp32s3_eth.serial.disableDTR=false +yb_esp32s3_eth.serial.disableRTS=false + +yb_esp32s3_eth.build.tarch=xtensa +yb_esp32s3_eth.build.bootloader_addr=0x0 +yb_esp32s3_eth.build.target=esp32s3 +yb_esp32s3_eth.build.mcu=esp32s3 +yb_esp32s3_eth.build.core=esp32 +yb_esp32s3_eth.build.variant=yb_esp32s3_eth +yb_esp32s3_eth.build.board=YB_ESP32S3_ETH + +yb_esp32s3_eth.build.usb_mode=1 +yb_esp32s3_eth.build.cdc_on_boot=0 +yb_esp32s3_eth.build.msc_on_boot=0 +yb_esp32s3_eth.build.dfu_on_boot=0 +yb_esp32s3_eth.build.f_cpu=240000000L +yb_esp32s3_eth.build.flash_size=4MB +yb_esp32s3_eth.build.flash_freq=80m +yb_esp32s3_eth.build.flash_mode=dio +yb_esp32s3_eth.build.boot=qio +yb_esp32s3_eth.build.boot_freq=80m +yb_esp32s3_eth.build.partitions=default +yb_esp32s3_eth.build.defines= +yb_esp32s3_eth.build.loop_core= +yb_esp32s3_eth.build.event_core= +yb_esp32s3_eth.build.psram_type=qspi +yb_esp32s3_eth.build.memory_type={build.boot}_{build.psram_type} + +yb_esp32s3_eth.menu.JTAGAdapter.default=Disabled +yb_esp32s3_eth.menu.JTAGAdapter.default.build.copy_jtag_files=0 +yb_esp32s3_eth.menu.JTAGAdapter.builtin=Integrated USB JTAG +yb_esp32s3_eth.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +yb_esp32s3_eth.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +yb_esp32s3_eth.menu.JTAGAdapter.external=FTDI Adapter +yb_esp32s3_eth.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +yb_esp32s3_eth.menu.JTAGAdapter.external.build.copy_jtag_files=1 +yb_esp32s3_eth.menu.JTAGAdapter.bridge=ESP USB Bridge +yb_esp32s3_eth.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +yb_esp32s3_eth.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +yb_esp32s3_eth.menu.LoopCore.1=Core 1 +yb_esp32s3_eth.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +yb_esp32s3_eth.menu.LoopCore.0=Core 0 +yb_esp32s3_eth.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +yb_esp32s3_eth.menu.EventsCore.1=Core 1 +yb_esp32s3_eth.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +yb_esp32s3_eth.menu.EventsCore.0=Core 0 +yb_esp32s3_eth.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +yb_esp32s3_eth.menu.USBMode.hwcdc=Hardware CDC and JTAG +yb_esp32s3_eth.menu.USBMode.hwcdc.build.usb_mode=1 +yb_esp32s3_eth.menu.USBMode.default=USB-OTG (TinyUSB) +yb_esp32s3_eth.menu.USBMode.default.build.usb_mode=0 + +yb_esp32s3_eth.menu.CDCOnBoot.default=Disabled +yb_esp32s3_eth.menu.CDCOnBoot.default.build.cdc_on_boot=0 +yb_esp32s3_eth.menu.CDCOnBoot.cdc=Enabled +yb_esp32s3_eth.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +yb_esp32s3_eth.menu.MSCOnBoot.default=Disabled +yb_esp32s3_eth.menu.MSCOnBoot.default.build.msc_on_boot=0 +yb_esp32s3_eth.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +yb_esp32s3_eth.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +yb_esp32s3_eth.menu.DFUOnBoot.default=Disabled +yb_esp32s3_eth.menu.DFUOnBoot.default.build.dfu_on_boot=0 +yb_esp32s3_eth.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +yb_esp32s3_eth.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +yb_esp32s3_eth.menu.UploadMode.default=UART0 / Hardware CDC +yb_esp32s3_eth.menu.UploadMode.default.upload.use_1200bps_touch=false +yb_esp32s3_eth.menu.UploadMode.default.upload.wait_for_upload_port=false +yb_esp32s3_eth.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +yb_esp32s3_eth.menu.UploadMode.cdc.upload.use_1200bps_touch=true +yb_esp32s3_eth.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +yb_esp32s3_eth.menu.PSRAM.disabled=Disabled +yb_esp32s3_eth.menu.PSRAM.disabled.build.defines= +yb_esp32s3_eth.menu.PSRAM.disabled.build.psram_type=qspi +yb_esp32s3_eth.menu.PSRAM.enabled=QSPI PSRAM +yb_esp32s3_eth.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +yb_esp32s3_eth.menu.PSRAM.enabled.build.psram_type=qspi +yb_esp32s3_eth.menu.PSRAM.opi=OPI PSRAM +yb_esp32s3_eth.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +yb_esp32s3_eth.menu.PSRAM.opi.build.psram_type=opi + +yb_esp32s3_eth.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +yb_esp32s3_eth.menu.PartitionScheme.default.build.partitions=default +yb_esp32s3_eth.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +yb_esp32s3_eth.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +yb_esp32s3_eth.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +yb_esp32s3_eth.menu.PartitionScheme.default_16MB=16M with spiffs (6.25MB APP/3.43MB SPIFFS) +yb_esp32s3_eth.menu.PartitionScheme.default_16MB.build.partitions=default_16MB +yb_esp32s3_eth.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600 +yb_esp32s3_eth.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS) +yb_esp32s3_eth.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB +yb_esp32s3_eth.menu.PartitionScheme.max_app_8MB.upload.maximum_size=8257536 +yb_esp32s3_eth.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +yb_esp32s3_eth.menu.PartitionScheme.fatflash.build.partitions=ffat +yb_esp32s3_eth.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +yb_esp32s3_eth.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +yb_esp32s3_eth.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +yb_esp32s3_eth.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +yb_esp32s3_eth.menu.PartitionScheme.minimal.build.partitions=minimal +yb_esp32s3_eth.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +yb_esp32s3_eth.menu.PartitionScheme.no_ota.build.partitions=no_ota +yb_esp32s3_eth.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +yb_esp32s3_eth.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +yb_esp32s3_eth.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +yb_esp32s3_eth.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +yb_esp32s3_eth.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +yb_esp32s3_eth.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +yb_esp32s3_eth.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +yb_esp32s3_eth.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +yb_esp32s3_eth.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +yb_esp32s3_eth.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +yb_esp32s3_eth.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +yb_esp32s3_eth.menu.PartitionScheme.huge_app.build.partitions=huge_app +yb_esp32s3_eth.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +yb_esp32s3_eth.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS) +yb_esp32s3_eth.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +yb_esp32s3_eth.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +yb_esp32s3_eth.menu.PartitionScheme.custom=Custom +yb_esp32s3_eth.menu.PartitionScheme.custom.build.partitions= +yb_esp32s3_eth.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +yb_esp32s3_eth.menu.CPUFreq.240=240MHz (WiFi) +yb_esp32s3_eth.menu.CPUFreq.240.build.f_cpu=240000000L +yb_esp32s3_eth.menu.CPUFreq.160=160MHz (WiFi) +yb_esp32s3_eth.menu.CPUFreq.160.build.f_cpu=160000000L +yb_esp32s3_eth.menu.CPUFreq.80=80MHz (WiFi) +yb_esp32s3_eth.menu.CPUFreq.80.build.f_cpu=80000000L +yb_esp32s3_eth.menu.CPUFreq.40=40MHz +yb_esp32s3_eth.menu.CPUFreq.40.build.f_cpu=40000000L +yb_esp32s3_eth.menu.CPUFreq.20=20MHz +yb_esp32s3_eth.menu.CPUFreq.20.build.f_cpu=20000000L +yb_esp32s3_eth.menu.CPUFreq.10=10MHz +yb_esp32s3_eth.menu.CPUFreq.10.build.f_cpu=10000000L + +yb_esp32s3_eth.menu.FlashMode.qio=QIO 80MHz +yb_esp32s3_eth.menu.FlashMode.qio.build.flash_mode=dio +yb_esp32s3_eth.menu.FlashMode.qio.build.boot=qio +yb_esp32s3_eth.menu.FlashMode.qio.build.boot_freq=80m +yb_esp32s3_eth.menu.FlashMode.qio.build.flash_freq=80m +yb_esp32s3_eth.menu.FlashMode.qio120=QIO 120MHz +yb_esp32s3_eth.menu.FlashMode.qio120.build.flash_mode=dio +yb_esp32s3_eth.menu.FlashMode.qio120.build.boot=qio +yb_esp32s3_eth.menu.FlashMode.qio120.build.boot_freq=120m +yb_esp32s3_eth.menu.FlashMode.qio120.build.flash_freq=80m +yb_esp32s3_eth.menu.FlashMode.dio=DIO 80MHz +yb_esp32s3_eth.menu.FlashMode.dio.build.flash_mode=dio +yb_esp32s3_eth.menu.FlashMode.dio.build.boot=dio +yb_esp32s3_eth.menu.FlashMode.dio.build.boot_freq=80m +yb_esp32s3_eth.menu.FlashMode.dio.build.flash_freq=80m +yb_esp32s3_eth.menu.FlashMode.opi=OPI 80MHz +yb_esp32s3_eth.menu.FlashMode.opi.build.flash_mode=dout +yb_esp32s3_eth.menu.FlashMode.opi.build.boot=opi +yb_esp32s3_eth.menu.FlashMode.opi.build.boot_freq=80m +yb_esp32s3_eth.menu.FlashMode.opi.build.flash_freq=80m + +yb_esp32s3_eth.menu.FlashSize.4M=4MB (32Mb) +yb_esp32s3_eth.menu.FlashSize.4M.build.flash_size=4MB +yb_esp32s3_eth.menu.FlashSize.8M=8MB (64Mb) +yb_esp32s3_eth.menu.FlashSize.8M.build.flash_size=8MB +yb_esp32s3_eth.menu.FlashSize.16M=16MB (128Mb) +yb_esp32s3_eth.menu.FlashSize.16M.build.flash_size=16MB + +yb_esp32s3_eth.menu.UploadSpeed.921600=921600 +yb_esp32s3_eth.menu.UploadSpeed.921600.upload.speed=921600 +yb_esp32s3_eth.menu.UploadSpeed.115200=115200 +yb_esp32s3_eth.menu.UploadSpeed.115200.upload.speed=115200 +yb_esp32s3_eth.menu.UploadSpeed.256000.windows=256000 +yb_esp32s3_eth.menu.UploadSpeed.256000.upload.speed=256000 +yb_esp32s3_eth.menu.UploadSpeed.230400.windows.upload.speed=256000 +yb_esp32s3_eth.menu.UploadSpeed.230400=230400 +yb_esp32s3_eth.menu.UploadSpeed.230400.upload.speed=230400 +yb_esp32s3_eth.menu.UploadSpeed.460800.linux=460800 +yb_esp32s3_eth.menu.UploadSpeed.460800.macosx=460800 +yb_esp32s3_eth.menu.UploadSpeed.460800.upload.speed=460800 +yb_esp32s3_eth.menu.UploadSpeed.512000.windows=512000 +yb_esp32s3_eth.menu.UploadSpeed.512000.upload.speed=512000 + +yb_esp32s3_eth.menu.DebugLevel.none=None +yb_esp32s3_eth.menu.DebugLevel.none.build.code_debug=0 +yb_esp32s3_eth.menu.DebugLevel.error=Error +yb_esp32s3_eth.menu.DebugLevel.error.build.code_debug=1 +yb_esp32s3_eth.menu.DebugLevel.warn=Warn +yb_esp32s3_eth.menu.DebugLevel.warn.build.code_debug=2 +yb_esp32s3_eth.menu.DebugLevel.info=Info +yb_esp32s3_eth.menu.DebugLevel.info.build.code_debug=3 +yb_esp32s3_eth.menu.DebugLevel.debug=Debug +yb_esp32s3_eth.menu.DebugLevel.debug.build.code_debug=4 +yb_esp32s3_eth.menu.DebugLevel.verbose=Verbose +yb_esp32s3_eth.menu.DebugLevel.verbose.build.code_debug=5 + +yb_esp32s3_eth.menu.EraseFlash.none=Disabled +yb_esp32s3_eth.menu.EraseFlash.none.upload.erase_cmd= +yb_esp32s3_eth.menu.EraseFlash.all=Enabled +yb_esp32s3_eth.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## diff --git a/variants/yb_esp32s3_eth/pins_arduino.h b/variants/yb_esp32s3_eth/pins_arduino.h new file mode 100644 index 00000000000..d7ac750489a --- /dev/null +++ b/variants/yb_esp32s3_eth/pins_arduino.h @@ -0,0 +1,63 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303A +#define USB_PID 0x1001 + +static const uint8_t LED_BUILTIN = 47; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +// Definitions for onboard WIZnet W5500 ethernet controller chip +static const uint8_t W5500_SS = 14; // W5500 chip select +static const uint8_t W5500_INT = 18; // available only if solder bridge "INT" is closed (default open) +static const uint8_t W5500_RST = 21; // set GPIO21 to INPUT (high impedance) if RST signal is unused + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ From 4d0ae18aee4168b72d1d7848a6c264883be5344c Mon Sep 17 00:00:00 2001 From: "pre-commit-ci-lite[bot]" <117423508+pre-commit-ci-lite[bot]@users.noreply.github.com> Date: Tue, 17 Dec 2024 06:37:40 +0000 Subject: [PATCH 2/2] ci(pre-commit): Apply automatic fixes --- variants/yb_esp32s3_eth/pins_arduino.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variants/yb_esp32s3_eth/pins_arduino.h b/variants/yb_esp32s3_eth/pins_arduino.h index d7ac750489a..77fcf6923fc 100644 --- a/variants/yb_esp32s3_eth/pins_arduino.h +++ b/variants/yb_esp32s3_eth/pins_arduino.h @@ -22,7 +22,7 @@ static const uint8_t MISO = 13; static const uint8_t SCK = 12; // Definitions for onboard WIZnet W5500 ethernet controller chip -static const uint8_t W5500_SS = 14; // W5500 chip select +static const uint8_t W5500_SS = 14; // W5500 chip select static const uint8_t W5500_INT = 18; // available only if solder bridge "INT" is closed (default open) static const uint8_t W5500_RST = 21; // set GPIO21 to INPUT (high impedance) if RST signal is unused