Add basic esp32p4 support

.github/actions/check-esp-hal/action.yml

@@ -20,7 +20,7 @@ runs:
         big_target=$(echo "${{ matrix.device.target }}" | tr [:lower:] [:upper:] | tr '-' '_')
         # Set the *target specific* RUSTFLAGS for the current device:
         echo "CARGO_TARGET_${big_target}_RUSTFLAGS=-Dwarnings" >> $GITHUB_ENV
-        # Linting toolchain (stable cant build documentation)
+        # Linting toolchain (stable can't build documentation)
         if [ "${{ inputs.toolchain }}" == "nightly" ]; then
           echo "LINTING_TOOLCHAIN=+nightly" >> $GITHUB_ENV
         else
@@ -29,12 +29,15 @@ runs:
     # Clippy and docs checks
     - name: Clippy
       shell: bash
+      if: ${{ !contains(fromJson('["esp32p4"]'), inputs.device) }} # TODO: Remove when `esp32p4` is added to all the packages
       run: cargo $LINTING_TOOLCHAIN xtask lint-packages --chips ${{ inputs.device }}
     - name: Check doc-tests
       shell: bash
+      if: ${{ !contains(fromJson('["esp32p4"]'), inputs.device) }} # TODO: Remove when `esp32p4` is added to all the packages
       run: cargo $LINTING_TOOLCHAIN xtask run-doc-test esp-hal ${{ inputs.device }}
     - name: Check documentation
       shell: bash
+      if: ${{ !contains(fromJson('["esp32p4"]'), inputs.device) }} # TODO: Remove when `esp32p4` is added to all the packages
       run: cargo $LINTING_TOOLCHAIN xtask build-documentation --packages esp-hal --chips ${{ inputs.device }}
     # Build all supported examples for the low-power core first (if present):
     - name: Build prerequisite examples (esp-lp-hal)

.github/workflows/ci.yml

@@ -58,6 +58,7 @@ jobs:
             { soc: "esp32c3", target: "riscv32imc-unknown-none-elf", toolchain: "stable" },
             { soc: "esp32c6", target: "riscv32imac-unknown-none-elf", toolchain: "stable" },
             { soc: "esp32h2", target: "riscv32imac-unknown-none-elf", toolchain: "stable" },
+            { soc: "esp32p4", target: "riscv32imafc-unknown-none-elf", toolchain: "stable" },
             # Xtensa devices:
             { soc: "esp32", target: "xtensa-esp32-none-elf", toolchain: "esp" },
             { soc: "esp32s2", target: "xtensa-esp32s2-none-elf", toolchain: "esp" },
@@ -73,7 +74,7 @@ jobs:
       # Install the Rust stable toolchain for RISC-V devices:
       - uses: dtolnay/rust-toolchain@v1
         with:
-          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf
+          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf,riscv32imafc-unknown-none-elf
           toolchain: stable
           components: rust-src
 
@@ -122,7 +123,7 @@ jobs:
           version: ${{ env.MSRV }}
       - uses: dtolnay/rust-toolchain@v1
         with:
-          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf
+          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf,riscv32imafc-unknown-none-elf
           toolchain: ${{ env.MSRV }}
           components: rust-src
       - uses: Swatinem/rust-cache@v2
@@ -134,6 +135,7 @@ jobs:
           cargo xtask build-package --features=esp32c3,ci --target=riscv32imc-unknown-none-elf   esp-hal
           cargo xtask build-package --features=esp32c6,ci --target=riscv32imac-unknown-none-elf  esp-hal
           cargo xtask build-package --features=esp32h2,ci --target=riscv32imac-unknown-none-elf  esp-hal
+          cargo xtask build-package --features=esp32p4,ci --target=riscv32imafc-unknown-none-elf  esp-hal
 
       - name: msrv RISCV (esp-wifi)
         run: |

.github/workflows/ci_nightly.yml

@@ -32,14 +32,15 @@ jobs:
             { soc: "esp32c3", target: "riscv32imc-unknown-none-elf" },
             { soc: "esp32c6", target: "riscv32imac-unknown-none-elf" },
             { soc: "esp32h2", target: "riscv32imac-unknown-none-elf" },
+            { soc: "esp32p4", target: "riscv32imafc-unknown-none-elf" },
           ]
     steps:
       - uses: actions/checkout@v4
 
       # Install the Rust nightly toolchain for RISC-V devices:
       - uses: dtolnay/rust-toolchain@v1
         with:
-          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf
+          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf,riscv32imafc-unknown-none-elf
           toolchain: nightly
           components: rust-src, clippy, rustfmt
 

esp-hal-embassy/CHANGELOG.md

@@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ### Added
 
 - `ESP_HAL_EMBASSY_LOW_POWER_WAIT` configuration option. (#2329)
+- Add basic `esp32p4` support (#2466)
 
 ### Changed
 

esp-hal-embassy/Cargo.toml

@@ -36,6 +36,7 @@ esp32c2 = ["esp-hal/esp32c2"]
 esp32c3 = ["esp-hal/esp32c3"]
 esp32c6 = ["esp-hal/esp32c6"]
 esp32h2 = ["esp-hal/esp32h2"]
+esp32p4 = ["esp-hal/esp32p4"]
 esp32s2 = ["esp-hal/esp32s2"]
 esp32s3 = ["esp-hal/esp32s3"]
 

esp-hal-embassy/build.rs

@@ -8,7 +8,7 @@ fn main() -> Result<(), Box<dyn Error>> {
     // NOTE: update when adding new device support!
     // Ensure that exactly one chip has been specified:
     assert_unique_used_features!(
-        "esp32", "esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32s2", "esp32s3"
+        "esp32", "esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32p4", "esp32s2", "esp32s3"
     );
 
     // NOTE: update when adding new device support!
@@ -23,6 +23,8 @@ fn main() -> Result<(), Box<dyn Error>> {
         "esp32c6"
     } else if cfg!(feature = "esp32h2") {
         "esp32h2"
+    } else if cfg!(feature = "esp32p4") {
+        "esp32p4"
     } else if cfg!(feature = "esp32s2") {
         "esp32s2"
     } else if cfg!(feature = "esp32s3") {

esp-hal/CHANGELOG.md

@@ -39,6 +39,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - I8080: Added `set_8bits_order()` to set the byte order in 8-bit mode (#2487)
 - `I2c::{apply_config(), with_sda(), with_scl()}` (#2477)
 - ESP32-S2: Added missing GPIO alternate functions (#2512)
+- Add basic `esp32p4` support (#2466)
 
 ### Changed
 

esp-hal/Cargo.toml

@@ -61,6 +61,7 @@ esp32c2 = { version = "0.23.0", features = ["critical-section", "rt"], optional
 esp32c3 = { version = "0.26.0", features = ["critical-section", "rt"], optional = true }
 esp32c6 = { version = "0.17.0", features = ["critical-section", "rt"], optional = true }
 esp32h2 = { version = "0.13.0", features = ["critical-section", "rt"], optional = true }
+esp32p4 = { path = "../../esp-pacs/esp32p4", features = ["critical-section", "rt"], optional = true }
 esp32s2 = { version = "0.25.0", features = ["critical-section", "rt"], optional = true }
 esp32s3 = { version = "0.29.0", features = ["critical-section", "rt"], optional = true }
 
@@ -97,6 +98,7 @@ debug = [
     "esp32c3?/impl-register-debug",
     "esp32c6?/impl-register-debug",
     "esp32h2?/impl-register-debug",
+    "esp32p4?/impl-register-debug",
     "esp32s2?/impl-register-debug",
     "esp32s3?/impl-register-debug",
 ]
@@ -114,6 +116,8 @@ esp32c3 = ["dep:esp32c3", "riscv",  "portable-atomic/unsafe-assume-single-core",
 esp32c6 = ["dep:esp32c6", "riscv",  "procmacros/has-lp-core", "esp-riscv-rt/rtc-ram"]
 # Target the ESP32-H2.
 esp32h2 = ["dep:esp32h2", "riscv", "esp-riscv-rt/rtc-ram"]
+# Target the ESP32-P4.
+esp32p4 = ["dep:esp32p4", "riscv"]
 # Target the ESP32-S2.
 esp32s2 = ["dep:esp32s2", "xtensa", "portable-atomic/critical-section", "procmacros/has-ulp-core", "xtensa-lx-rt/esp32s2", "usb-otg"]
 # Target the ESP32-S3.
@@ -138,6 +142,7 @@ defmt = [
     "esp32c3?/defmt",
     "esp32c6?/defmt",
     "esp32h2?/defmt",
+    "esp32p4?/defmt",
     "esp32s2?/defmt",
     "esp32s3?/defmt",
     "fugit/defmt",

esp-hal/build.rs

@@ -24,7 +24,7 @@ fn main() -> Result<(), Box<dyn Error>> {
     // NOTE: update when adding new device support!
     // Ensure that exactly one chip has been specified:
     assert_unique_used_features!(
-        "esp32", "esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32s2", "esp32s3"
+        "esp32", "esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32p4", "esp32s2", "esp32s3"
     );
 
     #[cfg(all(
@@ -45,6 +45,8 @@ fn main() -> Result<(), Box<dyn Error>> {
         "esp32c6"
     } else if cfg!(feature = "esp32h2") {
         "esp32h2"
+    } else if cfg!(feature = "esp32p4") {
+        "esp32p4"
     } else if cfg!(feature = "esp32s2") {
         "esp32s2"
     } else if cfg!(feature = "esp32s3") {

esp-hal/ld/esp32p4/esp32p4.x

@@ -0,0 +1,75 @@
+ENTRY(_start)
+
+PROVIDE(_stext = ORIGIN(ROTEXT));
+PROVIDE(_max_hart_id = 1);
+
+PROVIDE(UserSoft = DefaultHandler);
+PROVIDE(SupervisorSoft = DefaultHandler);
+PROVIDE(MachineSoft = DefaultHandler);
+PROVIDE(UserTimer = DefaultHandler);
+PROVIDE(SupervisorTimer = DefaultHandler);
+PROVIDE(MachineTimer = DefaultHandler);
+PROVIDE(UserExternal = DefaultHandler);
+PROVIDE(SupervisorExternal = DefaultHandler);
+PROVIDE(MachineExternal = DefaultHandler);
+
+PROVIDE(ExceptionHandler = DefaultExceptionHandler);
+
+/* The ESP32-C2 and ESP32-C3 have interrupt IDs 1-31, while the ESP32-C6,
+   ESP32-H2, and ESP32-P4 have IDs 0-31, so we much define the handler for the
+   one additional interrupt ID: */
+PROVIDE(interrupt0 = DefaultHandler);
+
+PROVIDE(__post_init = default_post_init);
+
+/* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */
+PROVIDE(_setup_interrupts = default_setup_interrupts);
+
+/* # Multi-processing hook function
+   fn _mp_hook() -> bool;
+
+   This function is called from all the harts and must return true only for one hart,
+   which will perform memory initialization. For other harts it must return false
+   and implement wake-up in platform-dependent way (e.g. after waiting for a user interrupt).
+*/
+PROVIDE(_mp_hook = default_mp_hook);
+
+/* # Start trap function override
+  By default uses the riscv crates default trap handler
+  but by providing the `_start_trap` symbol external crates can override.
+*/
+PROVIDE(_start_trap = default_start_trap);
+
+/* Must be called __global_pointer$ for linker relaxations to work. */
+PROVIDE(__global_pointer$ = _data_start + 0x800);
+
+SECTIONS {
+  .trap : ALIGN(4)
+  {
+    KEEP(*(.trap));
+    *(.trap.*);
+  } > RWTEXT
+}
+INSERT BEFORE .rwtext;
+
+SECTIONS {
+  /**
+   * Bootloader really wants to have separate segments for ROTEXT and RODATA
+   * It also needs to be located in a separate 64k flash segment.
+   */
+  .text_gap (NOLOAD): {
+    . = ALIGN(0x10000) + 0x20;
+  } > ROM
+}
+INSERT BEFORE .rodata;
+
+/* Shared sections - ordering matters */
+INCLUDE "text.x"
+INCLUDE "rwtext.x"
+INCLUDE "rodata.x"
+INCLUDE "rwdata.x"
+INCLUDE "rtc_fast.x"
+INCLUDE "stack.x"
+/* End of Shared sections */
+
+INCLUDE "debug.x"

esp-hal/ld/esp32p4/linkall.x

@@ -0,0 +1,14 @@
+INCLUDE "memory.x"
+
+REGION_ALIAS("ROTEXT", ROM);
+REGION_ALIAS("RODATA", ROM);
+
+REGION_ALIAS("RWTEXT", RAM);
+REGION_ALIAS("RWDATA", RAM);
+
+REGION_ALIAS("RTC_FAST_RWTEXT", RTC_FAST);
+REGION_ALIAS("RTC_FAST_RWDATA", RTC_FAST);
+
+INCLUDE "esp32p4.x"
+INCLUDE "hal-defaults.x"
+INCLUDE "rom-functions.x"

esp-hal/ld/esp32p4/memory.x

@@ -0,0 +1,26 @@
+MEMORY
+{
+    /* MEMORY_MAP = [
+        [0x00000000, 0x00010000, "PADDING"],
+        [0x40000000, 0x4C000000, "DROM"],
+        [0x4FF00000, 0x4FFA0000, "DRAM"],
+        [0x4FF00000, 0x4FFA0000, "BYTE_ACCESSIBLE"],
+        [0x4FC00000, 0x4FC20000, "DROM_MASK"],
+        [0x4FC00000, 0x4FC20000, "IROM_MASK"],
+        [0x40000000, 0x4C000000, "IROM"],
+        [0x4FF00000, 0x4FFA0000, "IRAM"],
+        [0x50108000, 0x50110000, "RTC_IRAM"],
+        [0x50108000, 0x50110000, "RTC_DRAM"],
+        [0x600FE000, 0x60100000, "MEM_INTERNAL2"],
+    ] */
+
+    /* 768K of on soc RAM */
+    RAM : ORIGIN = 0x4FF00000, LENGTH = 0xC0000
+
+    /* External flash */
+    /* Instruction and Data ROM */
+    ROM : ORIGIN = 0x40000000 + 0x20, LENGTH = 0x400000 - 0x20
+
+    /* RTC fast memory (executable). Persists over deep sleep. */
+    RTC_FAST : ORIGIN = 0x50108000, LENGTH = 32K /*- ESP_BOOTLOADER_RESERVE_RTC*/
+}

esp-hal/ld/esp32p4/rom-functions.x

@@ -0,0 +1,7 @@
+INCLUDE "rom/esp32p4.rom.api.ld"
+INCLUDE "rom/esp32p4.rom.ld"
+INCLUDE "rom/esp32p4.rom.libgcc.ld"
+INCLUDE "rom/esp32p4.rom.rvfp.ld"
+INCLUDE "rom/esp32p4.rom.version.ld"
+
+INCLUDE "rom/additional.ld"

esp-hal/ld/esp32p4/rom/additional.ld

@@ -0,0 +1,10 @@
+memset = 0x4fc00268;
+memcpy = 0x4fc0026c;
+memmove = 0x4fc00270;
+memcmp = 0x4fc00274;
+
+strcpy = 0x4fc00278;
+strncpy = 0x4fc0027c;
+strncmp = 0x4fc00284;
+
+abs = 0x4fc00338;

esp-hal/ld/esp32p4/rom/esp32p4.rom.api.ld

@@ -0,0 +1,65 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/** ROM APIs
+ */
+
+PROVIDE ( esp_rom_crc32_le = crc32_le );
+PROVIDE ( esp_rom_crc16_le = crc16_le );
+PROVIDE ( esp_rom_crc8_le  = crc8_le );
+PROVIDE ( esp_rom_crc32_be = crc32_be );
+PROVIDE ( esp_rom_crc16_be = crc16_be );
+PROVIDE ( esp_rom_crc8_be  = crc8_be );
+
+PROVIDE ( esp_rom_gpio_pad_select_gpio    = gpio_pad_select_gpio );
+PROVIDE ( esp_rom_gpio_pad_pullup_only    = gpio_pad_pullup );
+PROVIDE ( esp_rom_gpio_pad_set_drv        = gpio_pad_set_drv );
+PROVIDE ( esp_rom_gpio_pad_unhold         = gpio_pad_unhold );
+PROVIDE ( esp_rom_gpio_connect_in_signal  = gpio_matrix_in );
+PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );
+
+PROVIDE ( esp_rom_efuse_mac_address_crc8       = esp_crc8 );
+PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled );
+
+PROVIDE ( esp_rom_uart_flush_tx       = uart_tx_flush );
+PROVIDE ( esp_rom_uart_tx_one_char    = uart_tx_one_char2 );
+PROVIDE ( esp_rom_uart_tx_wait_idle   = uart_tx_wait_idle );
+PROVIDE ( esp_rom_uart_rx_one_char    = uart_rx_one_char );
+PROVIDE ( esp_rom_uart_rx_string      = UartRxString );
+PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
+PROVIDE ( esp_rom_uart_putc           = ets_write_char_uart );
+
+PROVIDE ( esp_rom_output_flush_tx       = uart_tx_flush );
+PROVIDE ( esp_rom_output_tx_one_char    = uart_tx_one_char );
+PROVIDE ( esp_rom_output_tx_wait_idle   = uart_tx_wait_idle );
+PROVIDE ( esp_rom_output_rx_one_char    = uart_rx_one_char );
+PROVIDE ( esp_rom_output_rx_string      = UartRxString );
+PROVIDE ( esp_rom_output_set_as_console = uart_tx_switch );
+PROVIDE ( esp_rom_output_putc           = ets_write_char_uart );
+
+PROVIDE ( esp_rom_md5_init   = MD5Init );
+PROVIDE ( esp_rom_md5_update = MD5Update );
+PROVIDE ( esp_rom_md5_final  = MD5Final );
+
+PROVIDE ( esp_rom_software_reset_system = software_reset );
+PROVIDE ( esp_rom_software_reset_cpu    = software_reset_cpu );
+
+PROVIDE ( esp_rom_printf   = ets_printf );
+PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
+PROVIDE ( esp_rom_delay_us = ets_delay_us );
+PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
+PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
+PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
+PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency );
+
+PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach );
+PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
+PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable );
+PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea );
+
+PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix );
+PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs);
+PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction );
+PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command );