TrigSrc-Sel doesn't set 0x500 register

[krmpotic]

Setting SoftSeq*TrigSrc-Sel PV to "Front0" does not cause the sequence to be triggered by front panel input. What is missing is setting the EVM 0x500 register's bit 8 (FP0SEQ0) (and bit 9 FP0SEQ1, for "Front1").

Example test procedure (mTCA-EVM-300):

1. provide 1Hz signal to FP0 input
2. configure mrfioc2 with EVM1 & EVR1
3. set up EVR event counter PV and MRF example sequence

## linux shell
# monitor event 3
caput MRF:{EVR1}EvtB-SP.OUT "@OBJ=evr1,Code=3"

# sequence with three events 3
caput -a MRF:{EVM1-SoftSeq:0}Timestamp-SP 4  0 100000 150000  200000
caput -a MRF:{EVM1-SoftSeq:0}EvtCode-SP   4  3      3      3     127

# enable sequence
caput MRF:{EVM1-SoftSeq:0}TrigSrc-Sel "Front0"
caput MRF:{EVM1-SoftSeq:0}RunMode-Sel "Normal"
caput MRF:{EVM1-SoftSeq:0}Load-Cmd 1
caput MRF:{EVM1-SoftSeq:0}Commit-Cmd 1
caput MRF:{EVM1-SoftSeq:0}Enable-Cmd 1

4. monitor EVR event counter - notice counter stays at 0!

## linux shell
camonitor MRF:{EVR1}EvtBCnt-I

5. set EVM 0x500="Front Panel Input Mapping Register" FP0SEQ0 bit manually

## EPICS IOC shell
pcidiagset 13    # <-- configure to your own EVM PCI bus number
pciread 32 0x500 # read inital value (gives "0x00000000 00000000")
pciwrite 32 0x500 0x100 # set FP0SEQ0 bit manually

only after step 5 does MRF:{EVR1}EvtBCnt-I start increasing

[krmpotic]

The problem is that FPGA clears the sequence trigger bits of 0x500 (Front Panel 0 Input Mapping Register) while writing zero to 0x504 (Front Panel 1...).

It happens like this:
After

dbpf MRF:{EVM1-SoftSeq:0}TrigSrc-Sel "Front0"
dbpf MRF:{EVM1-SoftSeq:0}Load-Cmd 1
dbpf MRF:{EVM1-SoftSeq:0}Commit-Cmd 1

EvgSeqManager::mapTriggerSrc(0,** 0x2010000) gets called.

In order to assure that only "Front0" evgInput is triggering the sequence, it goes through all the evgInputs, and if the evgInput is "Front0" (match == true) it sets sequence trigger bit SEQ0, else it clears it.

mrfioc2/evgMrmApp/src/mrmevgseq.cpp

Lines 63 to 75 in a8cb48d

	for(evgMrm::inputs_iterator it = owner->beginInputs(), end = owner->endInputs();
	it!=end; ++it)
	{
	bool match = it->first.second==itype && it->first.first==idx;
	evgInput *inp = it->second;
	epicsUInt32 map = inp->getSeqTrigMap();
	// set or clear sequencer trigger bit
	if(match)
	map |= 1u<<i;
	else
	map &= ~(1u<<i);
	inp->setSeqTrigMap(map);
	}

When clearing the SEQ0 bit of 0x504 (FP1), bit SEQ0 of 0x500 (FP0) also gets cleared. So function doesn't achieve what it wanted because of FPGA behavior.

To see what the FPGA is doing do the following:

# EPICS IOC shell
pcidiagset 13 # <--- change 13 to bus number of your EVM
pciwrite 32 0x500 0x100 # <-- set SEQ0 bit of FP0 mapping register
pciread  32 0x500       # 0x100
pciwrite 32 0x504 0     # <-- clear SEQ0 bit of FP1 mapping register
pciread  32 0x500       # gives 0!

it is interesting that setting (instead of clearing) the SEQ0 bit of 0x504 doesn't affect 0x500.

pciwrite 32 0x500 0x100 # <-- set SEQ0 bit of FP0 mapping register
pciread  32 0x500       # 0x100
pciwrite 32 0x504 0x100 # <-- set SEQ0 bit of FP1 mapping register
pciread  32 0x500       # still 0x100

P.S.
EVM is running firmware 207.c

[krmpotic]

0x500, 0x504... 0x50C refer to the same register.
First EvgSeqManager::mapTriggerSrc sets SEQ0 at 0x500, then clears SEQ0 at 0x504. Effectively undoing its work.

[krmpotic]

My PR still needs to solve the problem of evgDbus.db evgTrigEvt.db hardcoding FrontInp0 & FrontInp1. For mtca-evm-300 there shouldn't be a reference to FrontInp1.

[jerzyjamroz]

@krmpotic , is this issue still valid? Could you redo the test with "Front1"?