From 468220bfe919eedfc05b7591500540e6d8b20e02 Mon Sep 17 00:00:00 2001 From: lij Date: Wed, 21 Nov 2018 09:11:49 +0100 Subject: [PATCH] When external XTAL is not present then the ACLK falls back to the REFO clock instead of the VLO for the MSP430FR2xx_4xx family. This patch matches the vlo_freq variable to the REFO frequency. --- hardware/msp430/cores/msp430/wiring.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hardware/msp430/cores/msp430/wiring.c b/hardware/msp430/cores/msp430/wiring.c index bb717833e37..aa4d518ce3b 100644 --- a/hardware/msp430/cores/msp430/wiring.c +++ b/hardware/msp430/cores/msp430/wiring.c @@ -136,10 +136,10 @@ void enableXtal() /* Test the fault flag */ }while (SFRIFG1 & OFIFG); - /* If starting the XTAL timed out then fall back to VLO */ + /* If starting the XTAL timed out then fall back to REFO */ if(!timeout) { - /* ACLK = VLO = ~ 12 KHz */ - vlo_freq = 8000; + /* ACLK = REFO = ~ 32 KHz */ + vlo_freq = 32768; /* Source ACLK from REFO */ CSCTL4 |= SELA__REFOCLK; }